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rustc SIGSEGV on RISC-V when compiling serde and other crates (stack overflow on 4 GB stack)

A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.

A-LTOArea: Link-time optimization (LTO)Area: Link-time optimization (LTO)

C-bugCategory: This is a bug.Category: This is a bug.

I-crashIssue: The compiler crashes (SIGSEGV, SIGABRT, etc). Use I-ICE instead when the compiler panics.Issue: The compiler crashes (SIGSEGV, SIGABRT, etc). Use I-ICE instead when the compiler panics.

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

Status: Open.

#143749 In rust-lang/rust;

· planetryan opened on Jul 10, 2025

tests/run-make/link-eh-frame-terminator/rmake.rs recipe fails during test run for link-eh-frame-terminator on riscv64 target in x86 QEMU environment

A-run-makeArea: port run-make Makefiles to rmake.rsArea: port run-make Makefiles to rmake.rs

C-bugCategory: This is a bug.Category: This is a bug.

needs-triageThis issue may need triage. Remove it if it has been sufficiently triaged.This issue may need triage. Remove it if it has been sufficiently triaged.

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

Status: Open.

#143726 In rust-lang/rust;

· CaiWeiran opened on Jul 10, 2025

std doesn't compile for riscv32gc-unknown-linux-musl

A-atomicArea: Atomics, barriers, and sync primitivesArea: Atomics, barriers, and sync primitives

C-bugCategory: This is a bug.Category: This is a bug.

O-linuxOperating system: LinuxOperating system: Linux

O-muslTarget: The musl libcTarget: The musl libc

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

T-libsRelevant to the library team, which will review and decide on the PR/issue.Relevant to the library team, which will review and decide on the PR/issue.

Status: Open.

#143440 In rust-lang/rust;

· Noratrieb opened on Jul 4, 2025

riscv64gc-unknown-linux-gnu target fails some UI tests in CI

A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.

C-bugCategory: This is a bug.Category: This is a bug.

C-external-bugCategory: issue that is caused by bugs in software beyond our controlCategory: issue that is caused by bugs in software beyond our control

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#143319 In rust-lang/rust;

· CaiWeiran opened on Jul 2, 2025

Parameter ABI inconsistency error in Rust for RISC-V

A-ABIArea: Concerning the application binary interface (ABI)Area: Concerning the application binary interface (ABI)

C-bugCategory: This is a bug.Category: This is a bug.

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#141972 In rust-lang/rust;

· YingkaiLi-VM opened on Jun 3, 2025

<code>-Clto</code> stack overflows with <code>-Ccode-model=large</code> for riscv64

A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.

A-LTOArea: Link-time optimization (LTO)Area: Link-time optimization (LTO)

C-bugCategory: This is a bug.Category: This is a bug.

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

P-lowLow priorityLow priority

regression-from-stable-to-stablePerformance or correctness regression from one stable version to another.Performance or correctness regression from one stable version to another.

S-has-mcveStatus: A Minimal Complete and Verifiable Example has been found for this issueStatus: A Minimal Complete and Verifiable Example has been found for this issue

Status: Open.

#139479 In rust-lang/rust;

· kxxt opened on Apr 7, 2025

is_riscv_feature_detected doesn't seem to actually detect anything at runtime

A-target-featureArea: Enabling/disabling target features like AVX, Neon, etc.Area: Enabling/disabling target features like AVX, Neon, etc.

C-bugCategory: This is a bug.Category: This is a bug.

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

T-libsRelevant to the library team, which will review and decide on the PR/issue.Relevant to the library team, which will review and decide on the PR/issue.

Status: Open.

#139139 In rust-lang/rust;

· ThomasHabets opened on Mar 30, 2025

RISC-V RVV not enabled despite <code>-Ctarget-cpu=native</code>

A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.

A-target-featureArea: Enabling/disabling target features like AVX, Neon, etc.Area: Enabling/disabling target features like AVX, Neon, etc.

C-bugCategory: This is a bug.Category: This is a bug.

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#138789 In rust-lang/rust;

· ThomasHabets opened on Mar 21, 2025

RISC-V intrinsics with one or more target features are not inlined

A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.

C-bugCategory: This is a bug.Category: This is a bug.

C-optimizationCategory: An issue highlighting optimization opportunities or PRs implementing suchCategory: An issue highlighting optimization opportunities or PRs implementing such

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#137293 In rust-lang/rust;

· brkydnc opened on Feb 19, 2025

<code>-C force-frame-pointers=yes</code> not respected by <code>-Z build-std</code> or <code>opt-level = "z"</code> on <code>riscv32imc-unknown-none-elf</code>

A-backtraceArea: BacktracesArea: Backtraces

A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.

C-bugCategory: This is a bug.Category: This is a bug.

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#136198 In rust-lang/rust;

· rslawson opened on Jan 28, 2025

How should we handle dynamic vector ABIs?

A-ABIArea: Concerning the application binary interface (ABI)Area: Concerning the application binary interface (ABI)

A-SIMDArea: SIMD (Single Instruction Multiple Data)Area: SIMD (Single Instruction Multiple Data)

C-discussionCategory: Discussion or questions that doesn't represent real issues.Category: Discussion or questions that doesn't represent real issues.

E-needs-designThis issue needs exploration and design to see how and if we can fix/implement itThis issue needs exploration and design to see how and if we can fix/implement it

O-AArch64Armv8-A or later processors in AArch64 modeArmv8-A or later processors in AArch64 mode

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#133146 In rust-lang/rust;

· workingjubilee opened on Nov 17, 2024

Most <code>extern "*-interrupt-*" fn</code> should enforce 0-sized signatures

A-ABIArea: Concerning the application binary interface (ABI)Area: Concerning the application binary interface (ABI)

A-hardware-interruptsArea: Code for handling the "interrupt ABI" of various processorsArea: Code for handling the "interrupt ABI" of various processors

A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.

C-bugCategory: This is a bug.Category: This is a bug.

O-AVRTarget: AVR processors (ATtiny, ATmega, etc.)Target: AVR processors (ATtiny, ATmega, etc.)

O-msp430

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#132837 In rust-lang/rust;

· workingjubilee opened on Nov 10, 2024