LOGIC PLAYGROUND

A collection of FPGA learning projects and reference implementations—VHDL RTL, Vivado IP–based designs, MicroBlaze/Zynq SoC examples, and DSP-on-FPGA exercises—organized for quick study and reuse.

VHDL/RTL Design

1. VHDL TEMPLATE & SYNTAX NOTES
2. VHDL Notes: Behaviors, Pitfalls, and Useful Tricks
3. BRAM USAGE — Single-Port Block RAM
4. N-Bit Adder with VIO (CMOD A7)
5. DEBOUNCER
6. PMODDA4 Driver (DAC AD5628)
7. PWM GENERATOR
8. Edge Detection & D Flip-Flop Notes
9. Programming FPGA with Quad SPI Flash
10. UART Transmitter
11. UART Receiver

DSP

1. Sine Wave Generation using Xilinx DDS Compiler

Credits

This repository borrows ideas and references from vendor docs, textbooks, Youtube and community resources. Original sources are cited within each subproject.