diff --git a/firmware/RFSoC4x2_commonclk_dc/bd_4x2_2020-2.tcl b/firmware/RFSoC4x2_commonclk_dc/bd_4x2_2020-2.tcl deleted file mode 100644 index ca5e75e..0000000 --- a/firmware/RFSoC4x2_commonclk_dc/bd_4x2_2020-2.tcl +++ /dev/null @@ -1,1541 +0,0 @@ - -################################################################ -# This is a generated script based on design: d_1 -# -# Though there are limitations about the generated script, -# the main purpose of this utility is to make learning -# IP Integrator Tcl commands easier. -################################################################ - -namespace eval _tcl { -proc get_script_folder {} { - set script_path [file normalize [info script]] - set script_folder [file dirname $script_path] - return $script_folder -} -} -variable script_folder -set script_folder [_tcl::get_script_folder] - -################################################################ -# Check if script is running in correct Vivado version. -################################################################ -set scripts_vivado_version 2020.2 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 -} - -################################################################ -# START -################################################################ - -# To test this script, run the following commands from Vivado Tcl console: -# source d_1_script.tcl - - -# The design that will be created by this Tcl script contains the following -# module references: -# vect2bits_16 - -# Please add the sources of those modules before sourcing this Tcl script. - -# If there is no project opened, this script will create a -# project, but make sure you do not have an existing project -# <./myproj/project_1.xpr> in the current working folder. - -set list_projs [get_projects -quiet] -if { $list_projs eq "" } { - create_project project_1 myproj -part xczu48dr-ffvg1517-2-e - set_property BOARD_PART realdigital.org:rfsoc4x2:part0:1.0 [current_project] -} - - -# CHANGE DESIGN NAME HERE -variable design_name -set design_name d_1 - -# If you do not already have an existing IP Integrator design open, -# you can create a design using the following command: -# create_bd_design $design_name - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} - -common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." - -if { $nRet != 0 } { - catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} - return $nRet -} - -set bCheckIPsPassed 1 -################################################################## -# CHECK IPs -################################################################## -set bCheckIPs 1 -if { $bCheckIPs == 1 } { - set list_check_ips "\ -xilinx.com:ip:axi_bram_ctrl:4.1\ -xilinx.com:ip:blk_mem_gen:8.4\ -xilinx.com:ip:axi_dma:7.1\ -xilinx.com:ip:smartconnect:1.0\ -user.org:user:axis_avg_buffer:1.0\ -xilinx.com:ip:axis_clock_converter:1.1\ -user.org:user:axis_constant:1.0\ -user.org:user:axis_readout_v2:1.0\ -user.org:user:axis_register_slice_nb:1.0\ -xilinx.com:ip:axis_register_slice:1.1\ -user.org:user:axis_set_reg:1.0\ -user.org:user:axis_signal_gen_v6:1.0\ -xilinx.com:ip:axis_switch:1.1\ -user.org:user:axis_tproc64x32_x8:1.0\ -xilinx.com:ip:clk_wiz:6.0\ -user.org:user:mr_buffer_et:1.0\ -xilinx.com:ip:proc_sys_reset:5.0\ -xilinx.com:ip:usp_rf_data_converter:2.4\ -xilinx.com:ip:xlconstant:1.1\ -xilinx.com:ip:zynq_ultra_ps_e:3.3\ -" - - set list_ips_missing "" - common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." - - foreach ip_vlnv $list_check_ips { - set ip_obj [get_ipdefs -all $ip_vlnv] - if { $ip_obj eq "" } { - lappend list_ips_missing $ip_vlnv - } - } - - if { $list_ips_missing ne "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } - set bCheckIPsPassed 0 - } - -} - -################################################################## -# CHECK Modules -################################################################## -set bCheckModules 1 -if { $bCheckModules == 1 } { - set list_check_mods "\ -vect2bits_16\ -" - - set list_mods_missing "" - common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." - - foreach mod_vlnv $list_check_mods { - if { [can_resolve_reference $mod_vlnv] == 0 } { - lappend list_mods_missing $mod_vlnv - } - } - - if { $list_mods_missing ne "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } - common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." - set bCheckIPsPassed 0 - } -} - -if { $bCheckIPsPassed != 1 } { - common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." - return 3 -} - -################################################################## -# DESIGN PROCs -################################################################## - - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell } { - - variable script_folder - variable design_name - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - - # Create interface ports - set adc0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc0_clk ] - - set dac0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac0_clk ] - - set dac2_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac2_clk ] - - set sysref_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0 sysref_in ] - - set vin0_01 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin0_01 ] - - set vin0_23 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin0_23 ] - - set vout00 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout00 ] - - set vout20 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout20 ] - - - # Create ports - set PMOD0_0 [ create_bd_port -dir O PMOD0_0 ] - set PMOD0_1 [ create_bd_port -dir O PMOD0_1 ] - set PMOD0_2 [ create_bd_port -dir O PMOD0_2 ] - set PMOD0_3 [ create_bd_port -dir O PMOD0_3 ] - - # Create instance: axi_bram_ctrl_0, and set properties - set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - CONFIG.ECC_TYPE {0} \ - CONFIG.SINGLE_PORT_BRAM {1} \ - ] $axi_bram_ctrl_0 - - # Create instance: axi_bram_ctrl_0_bram, and set properties - set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] - set_property -dict [ list \ - CONFIG.Byte_Size {8} \ - CONFIG.EN_SAFETY_CKT {false} \ - CONFIG.Enable_32bit_Address {true} \ - CONFIG.Memory_Type {True_Dual_Port_RAM} \ - CONFIG.Read_Width_B {64} \ - CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ - CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \ - CONFIG.Use_Byte_Write_Enable {true} \ - CONFIG.Use_RSTA_Pin {true} \ - CONFIG.Use_RSTB_Pin {true} \ - CONFIG.Write_Width_B {64} \ - CONFIG.use_bram_block {BRAM_Controller} \ - ] $axi_bram_ctrl_0_bram - - # Create instance: axi_dma_avg, and set properties - set axi_dma_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_avg ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_avg - - # Create instance: axi_dma_buf, and set properties - set axi_dma_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_buf ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_buf - - # Create instance: axi_dma_gen, and set properties - set axi_dma_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_gen ] - set_property -dict [ list \ - CONFIG.c_include_s2mm {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_gen - - # Create instance: axi_dma_readout, and set properties - set axi_dma_readout [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_readout ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_readout - - # Create instance: axi_dma_tproc, and set properties - set axi_dma_tproc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_tproc ] - set_property -dict [ list \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - ] $axi_dma_tproc - - # Create instance: axi_smc, and set properties - set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] - set_property -dict [ list \ - CONFIG.NUM_SI {6} \ - ] $axi_smc - - # Create instance: axis_avg_buffer_0, and set properties - set axis_avg_buffer_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.0 axis_avg_buffer_0 ] - set_property -dict [ list \ - CONFIG.N_BUF {14} \ - ] $axis_avg_buffer_0 - - # Create instance: axis_avg_buffer_1, and set properties - set axis_avg_buffer_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.0 axis_avg_buffer_1 ] - set_property -dict [ list \ - CONFIG.N_BUF {14} \ - ] $axis_avg_buffer_1 - - # Create instance: axis_cc_avg_0, and set properties - set axis_cc_avg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_cc_avg_0 ] - - # Create instance: axis_cc_avg_1, and set properties - set axis_cc_avg_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_cc_avg_1 ] - - # Create instance: axis_cc_sg_0, and set properties - set axis_cc_sg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_cc_sg_0 ] - - # Create instance: axis_cc_sg_1, and set properties - set axis_cc_sg_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_cc_sg_1 ] - - # Create instance: axis_constant_0, and set properties - set axis_constant_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - ] $axis_constant_0 - - # Create instance: axis_constant_1, and set properties - set axis_constant_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_1 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - ] $axis_constant_1 - - # Create instance: axis_readout_v2_0, and set properties - set axis_readout_v2_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_0 ] - - # Create instance: axis_readout_v2_1, and set properties - set axis_readout_v2_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_1 ] - - # Create instance: axis_register_slice_0, and set properties - set axis_register_slice_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_register_slice_nb:1.0 axis_register_slice_0 ] - set_property -dict [ list \ - CONFIG.B {256} \ - ] $axis_register_slice_0 - - # Create instance: axis_register_slice_1, and set properties - set axis_register_slice_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_register_slice_nb:1.0 axis_register_slice_1 ] - set_property -dict [ list \ - CONFIG.B {256} \ - ] $axis_register_slice_1 - - # Create instance: axis_register_slice_2, and set properties - set axis_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_2 ] - set_property -dict [ list \ - CONFIG.REG_CONFIG {8} \ - ] $axis_register_slice_2 - - # Create instance: axis_register_slice_3, and set properties - set axis_register_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_3 ] - set_property -dict [ list \ - CONFIG.REG_CONFIG {8} \ - ] $axis_register_slice_3 - - # Create instance: axis_set_reg_0, and set properties - set axis_set_reg_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_set_reg:1.0 axis_set_reg_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {160} \ - ] $axis_set_reg_0 - - # Create instance: axis_signal_gen_v6_0, and set properties - set axis_signal_gen_v6_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_0 ] - - # Create instance: axis_signal_gen_v6_1, and set properties - set axis_signal_gen_v6_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_1 ] - - # Create instance: axis_switch_avg, and set properties - set axis_switch_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_avg ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_avg - - # Create instance: axis_switch_buf, and set properties - set axis_switch_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_buf ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_buf - - # Create instance: axis_switch_gen, and set properties - set axis_switch_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_gen ] - set_property -dict [ list \ - CONFIG.DECODER_REG {1} \ - CONFIG.NUM_MI {2} \ - CONFIG.NUM_SI {1} \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_gen - - # Create instance: axis_switch_readout, and set properties - set axis_switch_readout [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_readout ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_readout - - # Create instance: axis_tproc64x32_x8_0, and set properties - set axis_tproc64x32_x8_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_tproc64x32_x8:1.0 axis_tproc64x32_x8_0 ] - - # Create instance: clk_adc0_x2, and set properties - set clk_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_adc0_x2 ] - set_property -dict [ list \ - CONFIG.CLKOUT1_JITTER {79.964} \ - CONFIG.CLKOUT1_PHASE_ERROR {81.720} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {409.6} \ - CONFIG.MMCM_CLKFBOUT_MULT_F {5.750} \ - CONFIG.MMCM_CLKOUT0_DIVIDE_F {2.875} \ - CONFIG.MMCM_DIVCLK_DIVIDE {1} \ - CONFIG.RESET_PORT {resetn} \ - CONFIG.RESET_TYPE {ACTIVE_LOW} \ - ] $clk_adc0_x2 - - # Create instance: mr_buffer_et_0, and set properties - set mr_buffer_et_0 [ create_bd_cell -type ip -vlnv user.org:user:mr_buffer_et:1.0 mr_buffer_et_0 ] - set_property -dict [ list \ - CONFIG.B {32} \ - ] $mr_buffer_et_0 - - # Create instance: ps8_0_axi_periph, and set properties - set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] - set_property -dict [ list \ - CONFIG.NUM_MI {19} \ - ] $ps8_0_axi_periph - - # Create instance: rst_100, and set properties - set rst_100 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_100 ] - - # Create instance: rst_adc0, and set properties - set rst_adc0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0 ] - - # Create instance: rst_adc0_x2, and set properties - set rst_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0_x2 ] - - # Create instance: rst_dac0, and set properties - set rst_dac0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac0 ] - - # Create instance: rst_dac1, and set properties - set rst_dac1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac1 ] - - # Create instance: usp_rf_data_converter_0, and set properties - set usp_rf_data_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.4 usp_rf_data_converter_0 ] - set_property -dict [ list \ - CONFIG.ADC0_Fabric_Freq {409.600} \ - CONFIG.ADC0_Link_Coupling {1} \ - CONFIG.ADC0_Outclk_Freq {204.800} \ - CONFIG.ADC0_PLL_Enable {true} \ - CONFIG.ADC0_Refclk_Freq {409.600} \ - CONFIG.ADC0_Sampling_Rate {3.2768} \ - CONFIG.ADC_Coarse_Mixer_Freq02 {3} \ - CONFIG.ADC_Coarse_Mixer_Freq03 {3} \ - CONFIG.ADC_Data_Width00 {8} \ - CONFIG.ADC_Data_Width01 {8} \ - CONFIG.ADC_Data_Width02 {8} \ - CONFIG.ADC_Data_Width03 {8} \ - CONFIG.ADC_Decimation_Mode02 {1} \ - CONFIG.ADC_Decimation_Mode03 {1} \ - CONFIG.ADC_Mixer_Type02 {1} \ - CONFIG.ADC_Mixer_Type03 {1} \ - CONFIG.ADC_RESERVED_1_00 {false} \ - CONFIG.ADC_RESERVED_1_02 {false} \ - CONFIG.ADC_Slice02_Enable {true} \ - CONFIG.ADC_Slice03_Enable {true} \ - CONFIG.DAC0_Enable {1} \ - CONFIG.DAC0_Fabric_Freq {409.600} \ - CONFIG.DAC0_Outclk_Freq {409.600} \ - CONFIG.DAC0_PLL_Enable {true} \ - CONFIG.DAC0_Refclk_Freq {409.600} \ - CONFIG.DAC0_Sampling_Rate {6.5536} \ - CONFIG.DAC2_Enable {1} \ - CONFIG.DAC2_Fabric_Freq {409.600} \ - CONFIG.DAC2_Outclk_Freq {409.600} \ - CONFIG.DAC2_PLL_Enable {true} \ - CONFIG.DAC2_Refclk_Freq {409.600} \ - CONFIG.DAC2_Sampling_Rate {6.5536} \ - CONFIG.DAC_Coarse_Mixer_Freq00 {3} \ - CONFIG.DAC_Coarse_Mixer_Freq20 {3} \ - CONFIG.DAC_Interpolation_Mode00 {1} \ - CONFIG.DAC_Interpolation_Mode20 {1} \ - CONFIG.DAC_Mixer_Type00 {1} \ - CONFIG.DAC_Mixer_Type20 {1} \ - CONFIG.DAC_Mode00 {3} \ - CONFIG.DAC_Mode20 {3} \ - CONFIG.DAC_RESERVED_1_00 {false} \ - CONFIG.DAC_RESERVED_1_01 {false} \ - CONFIG.DAC_RESERVED_1_02 {false} \ - CONFIG.DAC_RESERVED_1_03 {false} \ - CONFIG.DAC_RESERVED_1_20 {false} \ - CONFIG.DAC_RESERVED_1_21 {false} \ - CONFIG.DAC_RESERVED_1_22 {false} \ - CONFIG.DAC_RESERVED_1_23 {false} \ - CONFIG.DAC_Slice00_Enable {true} \ - CONFIG.DAC_Slice20_Enable {true} \ - ] $usp_rf_data_converter_0 - - # Create instance: vect2bits_16_0, and set properties - set block_name vect2bits_16 - set block_cell_name vect2bits_16_0 - if { [catch {set vect2bits_16_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } elseif { $vect2bits_16_0 eq "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } - - # Create instance: xlconstant_0, and set properties - set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {64} \ - ] $xlconstant_0 - - # Create instance: xlconstant_1, and set properties - set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {1} \ - CONFIG.CONST_WIDTH {1} \ - ] $xlconstant_1 - - # Create instance: xlconstant_2, and set properties - set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {1} \ - ] $xlconstant_2 - - # Create instance: xlconstant_3, and set properties - set xlconstant_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_3 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {8} \ - ] $xlconstant_3 - - # Create instance: zynq_ultra_ps_e_0, and set properties - set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ] - set_property -dict [ list \ - CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS33} \ - CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ - CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ - CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ - CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \ - CONFIG.PSU_MIO_0_DIRECTION {inout} \ - CONFIG.PSU_MIO_0_POLARITY {Default} \ - CONFIG.PSU_MIO_10_DIRECTION {inout} \ - CONFIG.PSU_MIO_10_POLARITY {Default} \ - CONFIG.PSU_MIO_11_DIRECTION {inout} \ - CONFIG.PSU_MIO_11_POLARITY {Default} \ - CONFIG.PSU_MIO_12_DIRECTION {inout} \ - CONFIG.PSU_MIO_12_POLARITY {Default} \ - CONFIG.PSU_MIO_13_DIRECTION {inout} \ - CONFIG.PSU_MIO_13_POLARITY {Default} \ - CONFIG.PSU_MIO_14_DIRECTION {inout} \ - CONFIG.PSU_MIO_14_POLARITY {Default} \ - CONFIG.PSU_MIO_15_DIRECTION {inout} \ - CONFIG.PSU_MIO_15_POLARITY {Default} \ - CONFIG.PSU_MIO_16_DIRECTION {inout} \ - CONFIG.PSU_MIO_16_POLARITY {Default} \ - CONFIG.PSU_MIO_17_DIRECTION {inout} \ - CONFIG.PSU_MIO_17_POLARITY {Default} \ - CONFIG.PSU_MIO_18_DIRECTION {inout} \ - CONFIG.PSU_MIO_18_POLARITY {Default} \ - CONFIG.PSU_MIO_19_DIRECTION {inout} \ - CONFIG.PSU_MIO_19_POLARITY {Default} \ - CONFIG.PSU_MIO_1_DIRECTION {out} \ - CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_1_POLARITY {Default} \ - CONFIG.PSU_MIO_20_DIRECTION {inout} \ - CONFIG.PSU_MIO_20_POLARITY {Default} \ - CONFIG.PSU_MIO_21_DIRECTION {inout} \ - CONFIG.PSU_MIO_21_POLARITY {Default} \ - CONFIG.PSU_MIO_22_DIRECTION {out} \ - CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_22_POLARITY {Default} \ - CONFIG.PSU_MIO_23_DIRECTION {inout} \ - CONFIG.PSU_MIO_23_POLARITY {Default} \ - CONFIG.PSU_MIO_24_DIRECTION {in} \ - CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_24_POLARITY {Default} \ - CONFIG.PSU_MIO_24_SLEW {fast} \ - CONFIG.PSU_MIO_25_DIRECTION {in} \ - CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_25_POLARITY {Default} \ - CONFIG.PSU_MIO_25_SLEW {fast} \ - CONFIG.PSU_MIO_26_DIRECTION {inout} \ - CONFIG.PSU_MIO_26_POLARITY {Default} \ - CONFIG.PSU_MIO_27_DIRECTION {out} \ - CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_27_POLARITY {Default} \ - CONFIG.PSU_MIO_28_DIRECTION {in} \ - CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_28_POLARITY {Default} \ - CONFIG.PSU_MIO_28_SLEW {fast} \ - CONFIG.PSU_MIO_29_DIRECTION {out} \ - CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_29_POLARITY {Default} \ - CONFIG.PSU_MIO_2_DIRECTION {out} \ - CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_2_POLARITY {Default} \ - CONFIG.PSU_MIO_30_DIRECTION {in} \ - CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_30_POLARITY {Default} \ - CONFIG.PSU_MIO_30_SLEW {fast} \ - CONFIG.PSU_MIO_31_DIRECTION {inout} \ - CONFIG.PSU_MIO_31_POLARITY {Default} \ - CONFIG.PSU_MIO_32_DIRECTION {out} \ - CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_32_POLARITY {Default} \ - CONFIG.PSU_MIO_33_DIRECTION {in} \ - CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_33_POLARITY {Default} \ - CONFIG.PSU_MIO_33_SLEW {fast} \ - CONFIG.PSU_MIO_34_DIRECTION {inout} \ - CONFIG.PSU_MIO_34_POLARITY {Default} \ - CONFIG.PSU_MIO_35_DIRECTION {inout} \ - CONFIG.PSU_MIO_35_POLARITY {Default} \ - CONFIG.PSU_MIO_36_DIRECTION {inout} \ - CONFIG.PSU_MIO_36_POLARITY {Default} \ - CONFIG.PSU_MIO_37_DIRECTION {inout} \ - CONFIG.PSU_MIO_37_POLARITY {Default} \ - CONFIG.PSU_MIO_38_DIRECTION {out} \ - CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_38_POLARITY {Default} \ - CONFIG.PSU_MIO_39_DIRECTION {out} \ - CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_39_POLARITY {Default} \ - CONFIG.PSU_MIO_3_DIRECTION {inout} \ - CONFIG.PSU_MIO_3_POLARITY {Default} \ - CONFIG.PSU_MIO_40_DIRECTION {out} \ - CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_40_POLARITY {Default} \ - CONFIG.PSU_MIO_41_DIRECTION {out} \ - CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_41_POLARITY {Default} \ - CONFIG.PSU_MIO_42_DIRECTION {out} \ - CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_42_POLARITY {Default} \ - CONFIG.PSU_MIO_43_DIRECTION {out} \ - CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_43_POLARITY {Default} \ - CONFIG.PSU_MIO_44_DIRECTION {in} \ - CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_44_POLARITY {Default} \ - CONFIG.PSU_MIO_44_SLEW {fast} \ - CONFIG.PSU_MIO_45_DIRECTION {in} \ - CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_45_POLARITY {Default} \ - CONFIG.PSU_MIO_45_SLEW {fast} \ - CONFIG.PSU_MIO_46_DIRECTION {in} \ - CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_46_POLARITY {Default} \ - CONFIG.PSU_MIO_46_SLEW {fast} \ - CONFIG.PSU_MIO_47_DIRECTION {in} \ - CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_47_POLARITY {Default} \ - CONFIG.PSU_MIO_47_SLEW {fast} \ - CONFIG.PSU_MIO_48_DIRECTION {in} \ - CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_48_POLARITY {Default} \ - CONFIG.PSU_MIO_48_SLEW {fast} \ - CONFIG.PSU_MIO_49_DIRECTION {in} \ - CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_49_POLARITY {Default} \ - CONFIG.PSU_MIO_49_SLEW {fast} \ - CONFIG.PSU_MIO_4_DIRECTION {inout} \ - CONFIG.PSU_MIO_4_POLARITY {Default} \ - CONFIG.PSU_MIO_50_DIRECTION {out} \ - CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_50_POLARITY {Default} \ - CONFIG.PSU_MIO_51_DIRECTION {inout} \ - CONFIG.PSU_MIO_51_POLARITY {Default} \ - CONFIG.PSU_MIO_52_DIRECTION {in} \ - CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_52_POLARITY {Default} \ - CONFIG.PSU_MIO_52_SLEW {fast} \ - CONFIG.PSU_MIO_53_DIRECTION {in} \ - CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_53_POLARITY {Default} \ - CONFIG.PSU_MIO_53_SLEW {fast} \ - CONFIG.PSU_MIO_54_DIRECTION {inout} \ - CONFIG.PSU_MIO_54_POLARITY {Default} \ - CONFIG.PSU_MIO_55_DIRECTION {in} \ - CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_55_POLARITY {Default} \ - CONFIG.PSU_MIO_55_SLEW {fast} \ - CONFIG.PSU_MIO_56_DIRECTION {inout} \ - CONFIG.PSU_MIO_56_POLARITY {Default} \ - CONFIG.PSU_MIO_57_DIRECTION {inout} \ - CONFIG.PSU_MIO_57_POLARITY {Default} \ - CONFIG.PSU_MIO_58_DIRECTION {out} \ - CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_58_POLARITY {Default} \ - CONFIG.PSU_MIO_59_DIRECTION {inout} \ - CONFIG.PSU_MIO_59_POLARITY {Default} \ - CONFIG.PSU_MIO_5_DIRECTION {inout} \ - CONFIG.PSU_MIO_5_POLARITY {Default} \ - CONFIG.PSU_MIO_60_DIRECTION {inout} \ - CONFIG.PSU_MIO_60_POLARITY {Default} \ - CONFIG.PSU_MIO_61_DIRECTION {inout} \ - CONFIG.PSU_MIO_61_POLARITY {Default} \ - CONFIG.PSU_MIO_62_DIRECTION {inout} \ - CONFIG.PSU_MIO_62_POLARITY {Default} \ - CONFIG.PSU_MIO_63_DIRECTION {inout} \ - CONFIG.PSU_MIO_63_POLARITY {Default} \ - CONFIG.PSU_MIO_64_DIRECTION {in} \ - CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_64_POLARITY {Default} \ - CONFIG.PSU_MIO_64_SLEW {fast} \ - CONFIG.PSU_MIO_65_DIRECTION {in} \ - CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_65_POLARITY {Default} \ - CONFIG.PSU_MIO_65_SLEW {fast} \ - CONFIG.PSU_MIO_66_DIRECTION {inout} \ - CONFIG.PSU_MIO_66_POLARITY {Default} \ - CONFIG.PSU_MIO_67_DIRECTION {in} \ - CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_67_POLARITY {Default} \ - CONFIG.PSU_MIO_67_SLEW {fast} \ - CONFIG.PSU_MIO_68_DIRECTION {inout} \ - CONFIG.PSU_MIO_68_POLARITY {Default} \ - CONFIG.PSU_MIO_69_DIRECTION {inout} \ - CONFIG.PSU_MIO_69_POLARITY {Default} \ - CONFIG.PSU_MIO_6_DIRECTION {inout} \ - CONFIG.PSU_MIO_6_POLARITY {Default} \ - CONFIG.PSU_MIO_70_DIRECTION {out} \ - CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_70_POLARITY {Default} \ - CONFIG.PSU_MIO_71_DIRECTION {inout} \ - CONFIG.PSU_MIO_71_POLARITY {Default} \ - CONFIG.PSU_MIO_72_DIRECTION {inout} \ - CONFIG.PSU_MIO_72_POLARITY {Default} \ - CONFIG.PSU_MIO_73_DIRECTION {inout} \ - CONFIG.PSU_MIO_73_POLARITY {Default} \ - CONFIG.PSU_MIO_74_DIRECTION {inout} \ - CONFIG.PSU_MIO_74_POLARITY {Default} \ - CONFIG.PSU_MIO_75_DIRECTION {inout} \ - CONFIG.PSU_MIO_75_POLARITY {Default} \ - CONFIG.PSU_MIO_76_DIRECTION {inout} \ - CONFIG.PSU_MIO_76_POLARITY {Default} \ - CONFIG.PSU_MIO_77_DIRECTION {inout} \ - CONFIG.PSU_MIO_77_POLARITY {Default} \ - CONFIG.PSU_MIO_7_DIRECTION {inout} \ - CONFIG.PSU_MIO_7_POLARITY {Default} \ - CONFIG.PSU_MIO_8_DIRECTION {inout} \ - CONFIG.PSU_MIO_8_POLARITY {Default} \ - CONFIG.PSU_MIO_9_DIRECTION {inout} \ - CONFIG.PSU_MIO_9_POLARITY {Default} \ - CONFIG.PSU_MIO_TREE_PERIPHERALS {SPI 0#SPI 0#SPI 0#SPI 0#SPI 0#SPI 0#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#I2C 0#I2C 0#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#SD 0#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#UART 1#UART 1#GPIO1 MIO#GPIO1 MIO#I2C 1#I2C 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#MDIO 1#MDIO 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \ - CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#n_ss_out[2]#n_ss_out[1]#n_ss_out[0]#miso#mosi#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#scl_out#sda_out#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#sdio0_wp#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#txd#rxd#gpio1[34]#gpio1[35]#scl_out#sda_out#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem1_mdc#gem1_mdio_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \ - CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \ - CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ - CONFIG.PSU__ACT_DDR_FREQ_MHZ {1199.999756} \ - CONFIG.PSU__AFI0_COHERENCY {0} \ - CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ - CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.999756} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {599.999878} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1200} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.999878} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {72} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.999996} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {21} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.249996} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {20} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {299.999939} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.999878} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {399.999908} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {524.999939} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {533.333} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999992} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.999908} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.999756} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {124.999977} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {262.499969} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {267} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {524.999939} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {533.333} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.499969} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {63} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.499969} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {7} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.499969} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.499969} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {33.333328} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999996} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ - CONFIG.PSU__DDRC__ADDR_MIRROR {0} \ - CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \ - CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ - CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ - CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ - CONFIG.PSU__DDRC__CL {16} \ - CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ - CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ - CONFIG.PSU__DDRC__COMPONENTS {Components} \ - CONFIG.PSU__DDRC__CWL {12} \ - CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {1} \ - CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ - CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ - CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ - CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ - CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ - CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ - CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ - CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ - CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ - CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ - CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ - CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ - CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ - CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ - CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ - CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ - CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ - CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ - CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ - CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ - CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ - CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ - CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ - CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ - CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ - CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ - CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ - CONFIG.PSU__DDRC__ECC {Disabled} \ - CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ - CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ - CONFIG.PSU__DDRC__FGRM {1X} \ - CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__LP_ASR {manual normal} \ - CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ - CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ - CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ - CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ - CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ - CONFIG.PSU__DDRC__ROW_ADDR_COUNT {17} \ - CONFIG.PSU__DDRC__SB_TARGET {16-16-16} \ - CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ - CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2400R} \ - CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ - CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ - CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ - CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ - CONFIG.PSU__DDRC__T_FAW {30.0} \ - CONFIG.PSU__DDRC__T_RAS_MIN {32.0} \ - CONFIG.PSU__DDRC__T_RC {45.32} \ - CONFIG.PSU__DDRC__T_RCD {16} \ - CONFIG.PSU__DDRC__T_RP {16} \ - CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ - CONFIG.PSU__DDRC__VREF {1} \ - CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ - CONFIG.PSU__DDR__INTERFACE__FREQMHZ {600.000} \ - CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ - CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ - CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \ - CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \ - CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__DLL__ISUSED {1} \ - CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ - CONFIG.PSU__DP__LANE_SEL {Dual Lower} \ - CONFIG.PSU__DP__REF_CLK_FREQ {27} \ - CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk0} \ - CONFIG.PSU__ENET1__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {1} \ - CONFIG.PSU__ENET1__GRP_MDIO__IO {MIO 50 .. 51} \ - CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__ENET1__PERIPHERAL__IO {MIO 38 .. 49} \ - CONFIG.PSU__ENET1__PTP__ENABLE {0} \ - CONFIG.PSU__ENET1__TSU__ENABLE {0} \ - CONFIG.PSU__FPGA_PL0_ENABLE {1} \ - CONFIG.PSU__GEM1_COHERENCY {0} \ - CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__GEM__TSU__ENABLE {0} \ - CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ - CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ - CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \ - CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO_EMIO_WIDTH {41} \ - CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {41} \ - CONFIG.PSU__GT__LINK_SPEED {HBR} \ - CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ - CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ - CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \ - CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 18 .. 19} \ - CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 36 .. 37} \ - CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \ - CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \ - CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ - CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ - CONFIG.PSU__PL_CLK0_BUF {TRUE} \ - CONFIG.PSU__PMU_COHERENCY {0} \ - CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ - CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ - CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ - CONFIG.PSU__PMU__GPI0__ENABLE {0} \ - CONFIG.PSU__PMU__GPI1__ENABLE {0} \ - CONFIG.PSU__PMU__GPI2__ENABLE {0} \ - CONFIG.PSU__PMU__GPI3__ENABLE {0} \ - CONFIG.PSU__PMU__GPI4__ENABLE {0} \ - CONFIG.PSU__PMU__GPI5__ENABLE {0} \ - CONFIG.PSU__PMU__GPO0__ENABLE {0} \ - CONFIG.PSU__PMU__GPO1__ENABLE {0} \ - CONFIG.PSU__PMU__GPO2__ENABLE {0} \ - CONFIG.PSU__PMU__GPO3__ENABLE {0} \ - CONFIG.PSU__PMU__GPO4__ENABLE {0} \ - CONFIG.PSU__PMU__GPO5__ENABLE {0} \ - CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ - CONFIG.PSU__PRESET_APPLIED {1} \ - CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;0|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;1|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ - CONFIG.PSU__PROTECTION__SLAVES { \ - LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;0|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;0|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;1|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1 \ - } \ - CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.33333} \ - CONFIG.PSU__QSPI_COHERENCY {0} \ - CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \ - CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \ - CONFIG.PSU__SD0_COHERENCY {0} \ - CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \ - CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \ - CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \ - CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \ - CONFIG.PSU__SD0__GRP_WP__ENABLE {1} \ - CONFIG.PSU__SD0__GRP_WP__IO {MIO 25} \ - CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \ - CONFIG.PSU__SD0__RESET__ENABLE {0} \ - CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \ - CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \ - CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 3} \ - CONFIG.PSU__SPI0__GRP_SS1__ENABLE {1} \ - CONFIG.PSU__SPI0__GRP_SS1__IO {MIO 2} \ - CONFIG.PSU__SPI0__GRP_SS2__ENABLE {1} \ - CONFIG.PSU__SPI0__GRP_SS2__IO {MIO 1} \ - CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 0 .. 5} \ - CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \ - CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \ - CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \ - CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \ - CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \ - CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ - CONFIG.PSU__UART0__MODEM__ENABLE {0} \ - CONFIG.PSU__UART0__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__UART1__BAUD_RATE {115200} \ - CONFIG.PSU__UART1__MODEM__ENABLE {0} \ - CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 32 .. 33} \ - CONFIG.PSU__USB0_COHERENCY {0} \ - CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ - CONFIG.PSU__USB0__REF_CLK_FREQ {100} \ - CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk1} \ - CONFIG.PSU__USB0__RESET__ENABLE {0} \ - CONFIG.PSU__USB1_COHERENCY {0} \ - CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \ - CONFIG.PSU__USB1__REF_CLK_FREQ {100} \ - CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk1} \ - CONFIG.PSU__USB1__RESET__ENABLE {0} \ - CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ - CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ - CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \ - CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ - CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ - CONFIG.PSU__USE__IRQ0 {1} \ - CONFIG.PSU__USE__IRQ1 {1} \ - CONFIG.PSU__USE__M_AXI_GP0 {1} \ - CONFIG.PSU__USE__M_AXI_GP1 {0} \ - CONFIG.PSU__USE__M_AXI_GP2 {0} \ - CONFIG.PSU__USE__S_AXI_GP0 {1} \ - CONFIG.SUBPRESET1 {Custom} \ - ] $zynq_ultra_ps_e_0 - - # Create interface connections - connect_bd_intf_net -intf_net adc0_clk_1 [get_bd_intf_ports adc0_clk] [get_bd_intf_pins usp_rf_data_converter_0/adc0_clk] - connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTA] - connect_bd_intf_net -intf_net axi_dma_avg_M_AXI_S2MM [get_bd_intf_pins axi_dma_avg/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S00_AXI] - connect_bd_intf_net -intf_net axi_dma_buf_M_AXI_S2MM [get_bd_intf_pins axi_dma_buf/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S01_AXI] - connect_bd_intf_net -intf_net axi_dma_gen_M_AXIS_MM2S [get_bd_intf_pins axi_dma_gen/M_AXIS_MM2S] [get_bd_intf_pins axis_switch_gen/S00_AXIS] - connect_bd_intf_net -intf_net axi_dma_gen_M_AXI_MM2S [get_bd_intf_pins axi_dma_gen/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S03_AXI] - connect_bd_intf_net -intf_net axi_dma_readout_M_AXI_S2MM [get_bd_intf_pins axi_dma_readout/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S02_AXI] - connect_bd_intf_net -intf_net axi_dma_tproc_M_AXIS_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXIS_MM2S] [get_bd_intf_pins axis_tproc64x32_x8_0/s0_axis] - connect_bd_intf_net -intf_net axi_dma_tproc_M_AXI_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S04_AXI] - connect_bd_intf_net -intf_net axi_dma_tproc_M_AXI_S2MM [get_bd_intf_pins axi_dma_tproc/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S05_AXI] - connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HPC0_FPD] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m0_axis [get_bd_intf_pins axis_avg_buffer_0/m0_axis] [get_bd_intf_pins axis_switch_avg/S00_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/m1_axis] [get_bd_intf_pins axis_switch_buf/S00_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m2_axis [get_bd_intf_pins axis_avg_buffer_0/m2_axis] [get_bd_intf_pins axis_cc_avg_0/S_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m0_axis [get_bd_intf_pins axis_avg_buffer_1/m0_axis] [get_bd_intf_pins axis_switch_avg/S01_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/m1_axis] [get_bd_intf_pins axis_switch_buf/S01_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m2_axis [get_bd_intf_pins axis_avg_buffer_1/m2_axis] [get_bd_intf_pins axis_cc_avg_1/S_AXIS] - connect_bd_intf_net -intf_net axis_cc_avg_0_M_AXIS [get_bd_intf_pins axis_cc_avg_0/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s1_axis] - connect_bd_intf_net -intf_net axis_cc_avg_1_M_AXIS [get_bd_intf_pins axis_cc_avg_1/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s2_axis] - connect_bd_intf_net -intf_net axis_cc_sg_0_M_AXIS [get_bd_intf_pins axis_cc_sg_0/M_AXIS] [get_bd_intf_pins axis_signal_gen_v6_0/s1_axis] - connect_bd_intf_net -intf_net axis_cc_sg_1_M_AXIS [get_bd_intf_pins axis_cc_sg_1/M_AXIS] [get_bd_intf_pins axis_signal_gen_v6_1/s1_axis] - connect_bd_intf_net -intf_net axis_constant_0_m_axis [get_bd_intf_pins axis_constant_0/m_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/s3_axis] - connect_bd_intf_net -intf_net axis_constant_1_m_axis [get_bd_intf_pins axis_constant_1/m_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/s4_axis] - connect_bd_intf_net -intf_net axis_readout_v2_0_m0_axis [get_bd_intf_pins axis_readout_v2_0/m0_axis] [get_bd_intf_pins axis_switch_readout/S00_AXIS] - connect_bd_intf_net -intf_net axis_readout_v2_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/s_axis] [get_bd_intf_pins axis_readout_v2_0/m1_axis] - connect_bd_intf_net -intf_net axis_readout_v2_1_m0_axis [get_bd_intf_pins axis_readout_v2_1/m0_axis] [get_bd_intf_pins axis_switch_readout/S01_AXIS] - connect_bd_intf_net -intf_net axis_readout_v2_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/s_axis] [get_bd_intf_pins axis_readout_v2_1/m1_axis] - connect_bd_intf_net -intf_net axis_register_slice_2_M_AXIS [get_bd_intf_pins axis_readout_v2_0/s_axis] [get_bd_intf_pins axis_register_slice_2/M_AXIS] - connect_bd_intf_net -intf_net axis_register_slice_3_M_AXIS [get_bd_intf_pins axis_readout_v2_1/s_axis] [get_bd_intf_pins axis_register_slice_3/M_AXIS] - connect_bd_intf_net -intf_net axis_register_slice_4_m_axis [get_bd_intf_pins axis_register_slice_1/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s20_axis] - connect_bd_intf_net -intf_net axis_register_slice_6_m_axis [get_bd_intf_pins axis_register_slice_0/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s00_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_0_m_axis [get_bd_intf_pins axis_register_slice_0/s_axis] [get_bd_intf_pins axis_signal_gen_v6_0/m_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_1_m_axis [get_bd_intf_pins axis_register_slice_1/s_axis] [get_bd_intf_pins axis_signal_gen_v6_1/m_axis] - connect_bd_intf_net -intf_net axis_switch_0_M00_AXIS [get_bd_intf_pins axis_switch_readout/M00_AXIS] [get_bd_intf_pins mr_buffer_et_0/s00_axis] - connect_bd_intf_net -intf_net axis_switch_avg_M00_AXIS [get_bd_intf_pins axi_dma_avg/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_avg/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_buf_M00_AXIS [get_bd_intf_pins axi_dma_buf/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_buf/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_gen_M00_AXIS [get_bd_intf_pins axis_signal_gen_v6_0/s0_axis] [get_bd_intf_pins axis_switch_gen/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_gen_M01_AXIS [get_bd_intf_pins axis_signal_gen_v6_1/s0_axis] [get_bd_intf_pins axis_switch_gen/M01_AXIS] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m0_axis [get_bd_intf_pins axi_dma_tproc/S_AXIS_S2MM] [get_bd_intf_pins axis_tproc64x32_x8_0/m0_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m1_axis [get_bd_intf_pins axis_cc_sg_0/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m1_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m2_axis [get_bd_intf_pins axis_cc_sg_1/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m2_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m8_axis [get_bd_intf_pins axis_set_reg_0/s_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m8_axis] - connect_bd_intf_net -intf_net dac0_clk_1 [get_bd_intf_ports dac0_clk] [get_bd_intf_pins usp_rf_data_converter_0/dac0_clk] - connect_bd_intf_net -intf_net dac2_clk_1 [get_bd_intf_ports dac2_clk] [get_bd_intf_pins usp_rf_data_converter_0/dac2_clk] - connect_bd_intf_net -intf_net mr_buffer_et_0_m00_axis [get_bd_intf_pins axi_dma_readout/S_AXIS_S2MM] [get_bd_intf_pins mr_buffer_et_0/m00_axis] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_dma_avg/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins axi_dma_buf/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M02_AXI [get_bd_intf_pins axi_dma_readout/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M02_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M03_AXI [get_bd_intf_pins axis_avg_buffer_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M03_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M04_AXI [get_bd_intf_pins axis_readout_v2_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M04_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M05_AXI [get_bd_intf_pins axis_readout_v2_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M05_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M06_AXI [get_bd_intf_pins axis_switch_avg/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M06_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M07_AXI [get_bd_intf_pins axis_switch_buf/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M07_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M08_AXI [get_bd_intf_pins axis_switch_readout/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M08_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M09_AXI [get_bd_intf_pins axis_tproc64x32_x8_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M09_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M10_AXI [get_bd_intf_pins mr_buffer_et_0/s00_axi] [get_bd_intf_pins ps8_0_axi_periph/M10_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M11_AXI [get_bd_intf_pins ps8_0_axi_periph/M11_AXI] [get_bd_intf_pins usp_rf_data_converter_0/s_axi] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M12_AXI [get_bd_intf_pins axis_avg_buffer_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M12_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M13_AXI [get_bd_intf_pins axis_signal_gen_v6_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M13_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M14_AXI [get_bd_intf_pins axis_signal_gen_v6_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M14_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M15_AXI [get_bd_intf_pins axi_dma_gen/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M15_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M16_AXI [get_bd_intf_pins axis_switch_gen/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M16_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M17_AXI [get_bd_intf_pins axi_dma_tproc/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M17_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M18_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M18_AXI] - connect_bd_intf_net -intf_net sysref_in_1 [get_bd_intf_ports sysref_in] [get_bd_intf_pins usp_rf_data_converter_0/sysref_in] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_m00_axis [get_bd_intf_pins axis_register_slice_2/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m00_axis] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_m02_axis [get_bd_intf_pins axis_register_slice_3/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m02_axis] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout00 [get_bd_intf_ports vout00] [get_bd_intf_pins usp_rf_data_converter_0/vout00] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout20 [get_bd_intf_ports vout20] [get_bd_intf_pins usp_rf_data_converter_0/vout20] - connect_bd_intf_net -intf_net vin0_01_1 [get_bd_intf_ports vin0_01] [get_bd_intf_pins usp_rf_data_converter_0/vin0_01] - connect_bd_intf_net -intf_net vin0_23_1 [get_bd_intf_ports vin0_23] [get_bd_intf_pins usp_rf_data_converter_0/vin0_23] - connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD] - - # Create port connections - connect_bd_net -net axi_bram_ctrl_0_bram_doutb [get_bd_pins axi_bram_ctrl_0_bram/doutb] [get_bd_pins axis_tproc64x32_x8_0/pmem_do] - connect_bd_net -net axis_set_reg_0_dout [get_bd_pins axis_set_reg_0/dout] [get_bd_pins vect2bits_16_0/din] - connect_bd_net -net axis_tproc64x32_x8_0_pmem_addr [get_bd_pins axi_bram_ctrl_0_bram/addrb] [get_bd_pins axis_tproc64x32_x8_0/pmem_addr] - connect_bd_net -net clk_adc0_x2_clk_out1 [get_bd_pins axis_avg_buffer_0/s_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/aclk] [get_bd_pins axis_readout_v2_1/aclk] [get_bd_pins axis_register_slice_2/aclk] [get_bd_pins axis_register_slice_3/aclk] [get_bd_pins axis_switch_readout/aclk] [get_bd_pins clk_adc0_x2/clk_out1] [get_bd_pins mr_buffer_et_0/s00_axis_aclk] [get_bd_pins rst_adc0_x2/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/m0_axis_aclk] - connect_bd_net -net clk_adc0_x2_locked [get_bd_pins clk_adc0_x2/locked] [get_bd_pins rst_adc0_x2/dcm_locked] - connect_bd_net -net rst_adc0_peripheral_aresetn [get_bd_pins clk_adc0_x2/resetn] [get_bd_pins rst_adc0/peripheral_aresetn] - connect_bd_net -net rst_adc0_x2_peripheral_aresetn [get_bd_pins axis_avg_buffer_0/s_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/aresetn] [get_bd_pins axis_readout_v2_1/aresetn] [get_bd_pins axis_register_slice_2/aresetn] [get_bd_pins axis_register_slice_3/aresetn] [get_bd_pins axis_switch_readout/aresetn] [get_bd_pins mr_buffer_et_0/s00_axis_aresetn] [get_bd_pins rst_adc0_x2/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/m0_axis_aresetn] - connect_bd_net -net rst_dac0_peripheral_aresetn [get_bd_pins axis_cc_avg_0/m_axis_aresetn] [get_bd_pins axis_cc_avg_1/m_axis_aresetn] [get_bd_pins axis_cc_sg_0/m_axis_aresetn] [get_bd_pins axis_cc_sg_0/s_axis_aresetn] [get_bd_pins axis_cc_sg_1/s_axis_aresetn] [get_bd_pins axis_constant_0/m_axis_aresetn] [get_bd_pins axis_constant_1/m_axis_aresetn] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins axis_set_reg_0/s_axis_aresetn] [get_bd_pins axis_signal_gen_v6_0/aresetn] [get_bd_pins axis_tproc64x32_x8_0/aresetn] [get_bd_pins rst_dac0/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s0_axis_aresetn] - connect_bd_net -net rst_dac1_peripheral_aresetn [get_bd_pins axis_cc_sg_1/m_axis_aresetn] [get_bd_pins axis_register_slice_1/aresetn] [get_bd_pins axis_signal_gen_v6_1/aresetn] [get_bd_pins rst_dac1/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s2_axis_aresetn] - connect_bd_net -net rst_ps8_0_99M_peripheral_aresetn [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_dma_avg/axi_resetn] [get_bd_pins axi_dma_buf/axi_resetn] [get_bd_pins axi_dma_gen/axi_resetn] [get_bd_pins axi_dma_readout/axi_resetn] [get_bd_pins axi_dma_tproc/axi_resetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins axis_avg_buffer_0/m_axis_aresetn] [get_bd_pins axis_avg_buffer_0/s_axi_aresetn] [get_bd_pins axis_avg_buffer_1/m_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axi_aresetn] [get_bd_pins axis_cc_avg_0/s_axis_aresetn] [get_bd_pins axis_cc_avg_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/s_axi_aresetn] [get_bd_pins axis_readout_v2_1/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_0/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_0/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_1/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_1/s_axi_aresetn] [get_bd_pins axis_switch_avg/aresetn] [get_bd_pins axis_switch_avg/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_buf/aresetn] [get_bd_pins axis_switch_buf/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_gen/aresetn] [get_bd_pins axis_switch_gen/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_readout/s_axi_ctrl_aresetn] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aresetn] [get_bd_pins mr_buffer_et_0/m00_axis_aresetn] [get_bd_pins mr_buffer_et_0/s00_axi_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/M02_ARESETN] [get_bd_pins ps8_0_axi_periph/M03_ARESETN] [get_bd_pins ps8_0_axi_periph/M04_ARESETN] [get_bd_pins ps8_0_axi_periph/M05_ARESETN] [get_bd_pins ps8_0_axi_periph/M06_ARESETN] [get_bd_pins ps8_0_axi_periph/M07_ARESETN] [get_bd_pins ps8_0_axi_periph/M08_ARESETN] [get_bd_pins ps8_0_axi_periph/M09_ARESETN] [get_bd_pins ps8_0_axi_periph/M10_ARESETN] [get_bd_pins ps8_0_axi_periph/M11_ARESETN] [get_bd_pins ps8_0_axi_periph/M12_ARESETN] [get_bd_pins ps8_0_axi_periph/M13_ARESETN] [get_bd_pins ps8_0_axi_periph/M14_ARESETN] [get_bd_pins ps8_0_axi_periph/M15_ARESETN] [get_bd_pins ps8_0_axi_periph/M16_ARESETN] [get_bd_pins ps8_0_axi_periph/M17_ARESETN] [get_bd_pins ps8_0_axi_periph/M18_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_100/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s_axi_aresetn] - connect_bd_net -net usp_rf_data_converter_0_clk_adc0 [get_bd_pins clk_adc0_x2/clk_in1] [get_bd_pins rst_adc0/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_adc0] - connect_bd_net -net usp_rf_data_converter_0_clk_dac0 [get_bd_pins axi_bram_ctrl_0_bram/clkb] [get_bd_pins axis_cc_avg_0/m_axis_aclk] [get_bd_pins axis_cc_avg_1/m_axis_aclk] [get_bd_pins axis_cc_sg_0/m_axis_aclk] [get_bd_pins axis_cc_sg_0/s_axis_aclk] [get_bd_pins axis_cc_sg_1/s_axis_aclk] [get_bd_pins axis_constant_0/m_axis_aclk] [get_bd_pins axis_constant_1/m_axis_aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_set_reg_0/s_axis_aclk] [get_bd_pins axis_signal_gen_v6_0/aclk] [get_bd_pins axis_tproc64x32_x8_0/aclk] [get_bd_pins rst_dac0/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_dac0] [get_bd_pins usp_rf_data_converter_0/s0_axis_aclk] - connect_bd_net -net usp_rf_data_converter_0_clk_dac2 [get_bd_pins axis_cc_sg_1/m_axis_aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins axis_signal_gen_v6_1/aclk] [get_bd_pins rst_dac1/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_dac2] [get_bd_pins usp_rf_data_converter_0/s2_axis_aclk] - connect_bd_net -net vect2bits_16_0_dout0 [get_bd_ports PMOD0_0] [get_bd_pins vect2bits_16_0/dout0] - connect_bd_net -net vect2bits_16_0_dout1 [get_bd_ports PMOD0_1] [get_bd_pins vect2bits_16_0/dout1] - connect_bd_net -net vect2bits_16_0_dout2 [get_bd_ports PMOD0_2] [get_bd_pins vect2bits_16_0/dout2] - connect_bd_net -net vect2bits_16_0_dout3 [get_bd_ports PMOD0_3] [get_bd_pins vect2bits_16_0/dout3] - connect_bd_net -net vect2bits_16_0_dout4 [get_bd_pins axis_avg_buffer_0/trigger] [get_bd_pins vect2bits_16_0/dout4] - connect_bd_net -net vect2bits_16_0_dout5 [get_bd_pins axis_avg_buffer_1/trigger] [get_bd_pins vect2bits_16_0/dout5] - connect_bd_net -net vect2bits_16_0_dout6 [get_bd_pins mr_buffer_et_0/trigger] [get_bd_pins vect2bits_16_0/dout6] - connect_bd_net -net xlconstant_0_dout [get_bd_pins axi_bram_ctrl_0_bram/dinb] [get_bd_pins xlconstant_0/dout] - connect_bd_net -net xlconstant_1_dout [get_bd_pins axi_bram_ctrl_0_bram/enb] [get_bd_pins axis_tproc64x32_x8_0/start] [get_bd_pins xlconstant_1/dout] - connect_bd_net -net xlconstant_2_dout [get_bd_pins axi_bram_ctrl_0_bram/rstb] [get_bd_pins xlconstant_2/dout] - connect_bd_net -net xlconstant_3_dout [get_bd_pins axi_bram_ctrl_0_bram/web] [get_bd_pins xlconstant_3/dout] - connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_dma_avg/m_axi_s2mm_aclk] [get_bd_pins axi_dma_avg/s_axi_lite_aclk] [get_bd_pins axi_dma_buf/m_axi_s2mm_aclk] [get_bd_pins axi_dma_buf/s_axi_lite_aclk] [get_bd_pins axi_dma_gen/m_axi_mm2s_aclk] [get_bd_pins axi_dma_gen/s_axi_lite_aclk] [get_bd_pins axi_dma_readout/m_axi_s2mm_aclk] [get_bd_pins axi_dma_readout/s_axi_lite_aclk] [get_bd_pins axi_dma_tproc/m_axi_mm2s_aclk] [get_bd_pins axi_dma_tproc/m_axi_s2mm_aclk] [get_bd_pins axi_dma_tproc/s_axi_lite_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins axis_avg_buffer_0/m_axis_aclk] [get_bd_pins axis_avg_buffer_0/s_axi_aclk] [get_bd_pins axis_avg_buffer_1/m_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axi_aclk] [get_bd_pins axis_cc_avg_0/s_axis_aclk] [get_bd_pins axis_cc_avg_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/s_axi_aclk] [get_bd_pins axis_readout_v2_1/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_0/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_0/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_1/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_1/s_axi_aclk] [get_bd_pins axis_switch_avg/aclk] [get_bd_pins axis_switch_avg/s_axi_ctrl_aclk] [get_bd_pins axis_switch_buf/aclk] [get_bd_pins axis_switch_buf/s_axi_ctrl_aclk] [get_bd_pins axis_switch_gen/aclk] [get_bd_pins axis_switch_gen/s_axi_ctrl_aclk] [get_bd_pins axis_switch_readout/s_axi_ctrl_aclk] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aclk] [get_bd_pins mr_buffer_et_0/m00_axis_aclk] [get_bd_pins mr_buffer_et_0/s00_axi_aclk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/M02_ACLK] [get_bd_pins ps8_0_axi_periph/M03_ACLK] [get_bd_pins ps8_0_axi_periph/M04_ACLK] [get_bd_pins ps8_0_axi_periph/M05_ACLK] [get_bd_pins ps8_0_axi_periph/M06_ACLK] [get_bd_pins ps8_0_axi_periph/M07_ACLK] [get_bd_pins ps8_0_axi_periph/M08_ACLK] [get_bd_pins ps8_0_axi_periph/M09_ACLK] [get_bd_pins ps8_0_axi_periph/M10_ACLK] [get_bd_pins ps8_0_axi_periph/M11_ACLK] [get_bd_pins ps8_0_axi_periph/M12_ACLK] [get_bd_pins ps8_0_axi_periph/M13_ACLK] [get_bd_pins ps8_0_axi_periph/M14_ACLK] [get_bd_pins ps8_0_axi_periph/M15_ACLK] [get_bd_pins ps8_0_axi_periph/M16_ACLK] [get_bd_pins ps8_0_axi_periph/M17_ACLK] [get_bd_pins ps8_0_axi_periph/M18_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_100/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/s_axi_aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihpc0_fpd_aclk] - connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_100/ext_reset_in] [get_bd_pins rst_adc0/ext_reset_in] [get_bd_pins rst_adc0_x2/ext_reset_in] [get_bd_pins rst_dac0/ext_reset_in] [get_bd_pins rst_dac1/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] - - # Create address segments - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_readout/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0xA0140000 -range 0x00002000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_avg/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_buf/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0110000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_gen/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_readout/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0130000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_tproc/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA00A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_1/s_axi/reg0] -force - assign_bd_address -offset 0xA0040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_1/s_axi/reg0] -force - assign_bd_address -offset 0xA00B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_1/s_axi/reg0] -force - assign_bd_address -offset 0xA0060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_avg/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0xA0070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_buf/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0xA0120000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_gen/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0xA0080000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_readout/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0x000400000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_tproc64x32_x8_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mr_buffer_et_0/s00_axi/reg0] -force - assign_bd_address -offset 0xA00C0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs usp_rf_data_converter_0/s_axi/Reg] -force - - # Exclude Address Segments - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_readout/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_readout/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - - # Perform GUI Layout - regenerate_bd_layout -layout_string { - "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"0.530464", - "Default View_TopLeft":"-632,0", - "ExpandedHierarchyInLayout":"", - "guistr":"# # String gsaved with Nlview 7.0r4 2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS -# -string -flagsOSRD -preplace port adc0_clk -pg 1 -lvl 0 -x -10 -y 2500 -defaultsOSRD -preplace port dac0_clk -pg 1 -lvl 0 -x -10 -y 2520 -defaultsOSRD -preplace port dac2_clk -pg 1 -lvl 0 -x -10 -y 2540 -defaultsOSRD -preplace port sysref_in -pg 1 -lvl 0 -x -10 -y 2600 -defaultsOSRD -preplace port vin0_01 -pg 1 -lvl 0 -x -10 -y 2560 -defaultsOSRD -preplace port vin0_23 -pg 1 -lvl 0 -x -10 -y 2580 -defaultsOSRD -preplace port vout00 -pg 1 -lvl 11 -x 4610 -y 2620 -defaultsOSRD -preplace port vout20 -pg 1 -lvl 11 -x 4610 -y 2640 -defaultsOSRD -preplace port PMOD0_0 -pg 1 -lvl 11 -x 4610 -y 2660 -defaultsOSRD -preplace port PMOD0_1 -pg 1 -lvl 11 -x 4610 -y 2680 -defaultsOSRD -preplace port PMOD0_2 -pg 1 -lvl 11 -x 4610 -y 2700 -defaultsOSRD -preplace port PMOD0_3 -pg 1 -lvl 11 -x 4610 -y 2720 -defaultsOSRD -preplace inst axi_bram_ctrl_0 -pg 1 -lvl 1 -x 180 -y 2010 -defaultsOSRD -preplace inst axi_bram_ctrl_0_bram -pg 1 -lvl 2 -x 620 -y 2250 -defaultsOSRD -preplace inst axi_dma_avg -pg 1 -lvl 10 -x 4390 -y 1960 -defaultsOSRD -preplace inst axi_dma_buf -pg 1 -lvl 10 -x 4390 -y 2140 -defaultsOSRD -resize 320 156 -preplace inst axi_dma_gen -pg 1 -lvl 2 -x 620 -y 1290 -defaultsOSRD -preplace inst axi_dma_readout -pg 1 -lvl 10 -x 4390 -y 2320 -defaultsOSRD -resize 320 156 -preplace inst axi_dma_tproc -pg 1 -lvl 2 -x 620 -y 1520 -defaultsOSRD -preplace inst axi_smc -pg 1 -lvl 5 -x 1770 -y 1040 -defaultsOSRD -preplace inst axis_avg_buffer_0 -pg 1 -lvl 8 -x 3600 -y 1690 -defaultsOSRD -preplace inst axis_avg_buffer_1 -pg 1 -lvl 8 -x 3600 -y 2020 -defaultsOSRD -resize 220 236 -preplace inst axis_cc_avg_0 -pg 1 -lvl 9 -x 4010 -y 1560 -defaultsOSRD -preplace inst axis_cc_avg_1 -pg 1 -lvl 9 -x 4010 -y 1740 -defaultsOSRD -resize 220 156 -preplace inst axis_cc_sg_0 -pg 1 -lvl 3 -x 1040 -y 1620 -defaultsOSRD -preplace inst axis_cc_sg_1 -pg 1 -lvl 3 -x 1040 -y 1840 -defaultsOSRD -resize 220 156 -preplace inst axis_constant_0 -pg 1 -lvl 1 -x 180 -y 1730 -defaultsOSRD -preplace inst axis_constant_1 -pg 1 -lvl 1 -x 180 -y 1850 -defaultsOSRD -resize 220 96 -preplace inst axis_register_slice_2 -pg 1 -lvl 6 -x 2440 -y 1770 -defaultsOSRD -resize 180 116 -preplace inst axis_register_slice_3 -pg 1 -lvl 6 -x 2440 -y 2010 -defaultsOSRD -resize 180 116 -preplace inst axis_set_reg_0 -pg 1 -lvl 6 -x 2440 -y 2870 -defaultsOSRD -preplace inst axis_signal_gen_v6_0 -pg 1 -lvl 4 -x 1450 -y 2100 -defaultsOSRD -preplace inst axis_signal_gen_v6_1 -pg 1 -lvl 4 -x 1450 -y 2390 -defaultsOSRD -resize 220 236 -preplace inst axis_switch_avg -pg 1 -lvl 9 -x 4010 -y 1980 -defaultsOSRD -resize 240 196 -preplace inst axis_switch_buf -pg 1 -lvl 9 -x 4010 -y 2250 -defaultsOSRD -resize 240 196 -preplace inst axis_switch_gen -pg 1 -lvl 3 -x 1040 -y 1430 -defaultsOSRD -preplace inst axis_switch_readout -pg 1 -lvl 8 -x 3600 -y 2320 -defaultsOSRD -preplace inst axis_tproc64x32_x8_0 -pg 1 -lvl 2 -x 620 -y 1880 -defaultsOSRD -preplace inst clk_adc0_x2 -pg 1 -lvl 6 -x 2440 -y 690 -defaultsOSRD -preplace inst mr_buffer_et_0 -pg 1 -lvl 9 -x 4010 -y 2490 -defaultsOSRD -preplace inst ps8_0_axi_periph -pg 1 -lvl 7 -x 3110 -y 1090 -defaultsOSRD -preplace inst rst_100 -pg 1 -lvl 6 -x 2440 -y 290 -defaultsOSRD -preplace inst rst_adc0 -pg 1 -lvl 6 -x 2440 -y 490 -defaultsOSRD -preplace inst rst_adc0_x2 -pg 1 -lvl 6 -x 2440 -y 840 -defaultsOSRD -resize 320 156 -preplace inst rst_dac0 -pg 1 -lvl 6 -x 2440 -y 1060 -defaultsOSRD -resize 320 156 -preplace inst rst_dac1 -pg 1 -lvl 6 -x 2440 -y 1240 -defaultsOSRD -resize 320 156 -preplace inst usp_rf_data_converter_0 -pg 1 -lvl 6 -x 2440 -y 2560 -defaultsOSRD -preplace inst xlconstant_0 -pg 1 -lvl 1 -x 180 -y 2130 -defaultsOSRD -preplace inst xlconstant_1 -pg 1 -lvl 1 -x 180 -y 2240 -defaultsOSRD -resize 140 88 -preplace inst xlconstant_2 -pg 1 -lvl 1 -x 180 -y 2350 -defaultsOSRD -resize 140 88 -preplace inst xlconstant_3 -pg 1 -lvl 1 -x 180 -y 2460 -defaultsOSRD -resize 140 88 -preplace inst zynq_ultra_ps_e_0 -pg 1 -lvl 6 -x 2440 -y 110 -defaultsOSRD -preplace inst axis_register_slice_0 -pg 1 -lvl 5 -x 1770 -y 2120 -defaultsOSRD -preplace inst axis_register_slice_1 -pg 1 -lvl 5 -x 1770 -y 2440 -defaultsOSRD -preplace inst vect2bits_16_0 -pg 1 -lvl 7 -x 3110 -y 2810 -defaultsOSRD -preplace inst axis_readout_v2_0 -pg 1 -lvl 7 -x 3110 -y 1730 -defaultsOSRD -preplace inst axis_readout_v2_1 -pg 1 -lvl 7 -x 3110 -y 2050 -defaultsOSRD -resize 200 176 -preplace netloc axi_bram_ctrl_0_bram_doutb 1 1 1 400 2030n -preplace netloc axis_set_reg_0_dout 1 6 1 2790 2810n -preplace netloc axis_tproc64x32_x8_0_pmem_addr 1 1 2 420 2110 800 -preplace netloc clk_adc0_x2_clk_out1 1 5 4 2050 950 2830 1880 3440 2440 3740 -preplace netloc clk_adc0_x2_locked 1 5 2 2080 940 2760 -preplace netloc rst_adc0_peripheral_aresetn 1 5 2 2080 610 2760 -preplace netloc rst_adc0_x2_peripheral_aresetn 1 5 4 2060 1870 2800 1890 3450 2530 N -preplace netloc rst_dac0_peripheral_aresetn 1 0 9 10 1640 360 1640 840 1740 1220 1940 1590J 2200 1940J 2200 2810 1870 N 1870 3770 -preplace netloc rst_dac1_peripheral_aresetn 1 2 5 860 2470 1280 2560 1620J 2560 1920J 2330 2770 -preplace netloc rst_ps8_0_99M_peripheral_aresetn 1 0 10 30 1920 370 1380 840 1320 1230 1320 1580 1170 1960 1340 2860 1900 3420 1840 3830J 2120 4170 -preplace netloc usp_rf_data_converter_0_clk_adc0 1 5 2 2070 620 2780 -preplace netloc usp_rf_data_converter_0_clk_dac0 1 0 9 40 1660 340 1660 850 1960 1270 1960 1620 1960 1970 2210 2870 2180 3380 1830 3780 -preplace netloc usp_rf_data_converter_0_clk_dac2 1 2 5 870 2450 1240 2590 1590 2360 2000 2340 2770 -preplace netloc vect2bits_16_0_dout0 1 7 4 N 2660 NJ 2660 NJ 2660 NJ -preplace netloc vect2bits_16_0_dout1 1 7 4 N 2680 NJ 2680 NJ 2680 NJ -preplace netloc vect2bits_16_0_dout2 1 7 4 N 2700 NJ 2700 NJ 2700 NJ -preplace netloc vect2bits_16_0_dout3 1 7 4 N 2720 NJ 2720 NJ 2720 NJ -preplace netloc vect2bits_16_0_dout4 1 7 1 3370 1690n -preplace netloc vect2bits_16_0_dout5 1 7 1 3430 2020n -preplace netloc vect2bits_16_0_dout6 1 7 2 3460 2450 NJ -preplace netloc xlconstant_0_dout 1 1 1 320 2130n -preplace netloc xlconstant_1_dout 1 1 1 380 2010n -preplace netloc xlconstant_2_dout 1 1 1 350 2310n -preplace netloc xlconstant_3_dout 1 1 1 410 2330n -preplace netloc zynq_ultra_ps_e_0_pl_clk0 1 0 10 40 1930 330 1200 860 1200 1250 1090 1580 910 2020 1350 2790 1620 3410 1540 3760J 2130 4200 -preplace netloc zynq_ultra_ps_e_0_pl_resetn0 1 5 2 2060 600 2780 -preplace netloc adc0_clk_1 1 0 6 40 2530 N 2530 N 2530 N 2530 N 2530 1950 -preplace netloc axis_avg_buffer_1_m2_axis 1 8 1 3810 1700n -preplace netloc axi_dma_readout_M_AXI_S2MM 1 4 7 1620J 1180 2010 1560 2850J 1850 3340J 1860 NJ 1860 NJ 1860 4580 -preplace netloc axi_dma_tproc_M_AXI_MM2S 1 2 3 820 1050 NJ 1050 N -preplace netloc axi_dma_gen_M_AXIS_MM2S 1 2 1 850 1280n -preplace netloc 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axis_register_slice_6_m_axis 1 5 1 1950 2120n -preplace netloc axis_signal_gen_v6_1_m_axis 1 4 1 1580 2390n -preplace netloc sysref_in_1 1 0 6 NJ 2600 NJ 2600 NJ 2600 NJ 2600 NJ 2600 1930 -preplace netloc usp_rf_data_converter_0_m02_axis 1 5 2 2080 1930 2750 -preplace netloc ps8_0_axi_periph_M17_AXI 1 1 7 380 390 NJ 390 NJ 390 NJ 390 NJ 390 NJ 390 3320 -preplace netloc ps8_0_axi_periph_M13_AXI 1 3 5 1290 1610 NJ 1610 NJ 1610 NJ 1610 3280 -preplace netloc ps8_0_axi_periph_M11_AXI 1 5 3 2070 1860 NJ 1860 3300J -preplace netloc ps8_0_axi_periph_M15_AXI 1 1 7 390 590 N 590 N 590 NJ 590 NJ 590 NJ 590 3290 -preplace netloc usp_rf_data_converter_0_vout20 1 6 5 N 2550 3270 2640 N 2640 N 2640 N -preplace netloc vin0_23_1 1 0 6 N 2580 N 2580 N 2580 N 2580 1610 2550 2040 -preplace netloc ps8_0_axi_periph_M09_AXI 1 1 7 400 1670 810 1730 N 1730 NJ 1730 1910 1850 2840J 1840 3310J -preplace netloc ps8_0_axi_periph_M08_AXI 1 7 1 3350 1070n -preplace netloc usp_rf_data_converter_0_vout00 1 6 5 N 2530 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/firmware/RFSoC4x2_commonclk_dc/timing_4x2.xdc b/firmware/RFSoC4x2_commonclk_dc/timing_4x2.xdc deleted file mode 100644 index 19848db..0000000 --- a/firmware/RFSoC4x2_commonclk_dc/timing_4x2.xdc +++ /dev/null @@ -1,34 +0,0 @@ -set clk_axi [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/zynq_ultra_ps_e_0/pl_clk0]]] -set clk_adc0 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_adc0]]] -set clk_dac0 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac0]]] -set clk_dac2 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac2]]] -set clk_adc0_x2 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/clk_adc0_x2/clk_out1]]] -#set clk_tproc [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/clk_tproc/clk_out1]]] - -set_clock_group -name clk_axi_to_adc0_x2 -asynchronous \ - -group [get_clocks $clk_axi] \ - -group [get_clocks $clk_adc0_x2] - -set_clock_group -name clk_axi_to_dac0 -asynchronous \ - -group [get_clocks $clk_axi] \ - -group [get_clocks $clk_dac0] - -set_clock_group -name clk_axi_to_dac2 -asynchronous \ - -group [get_clocks $clk_axi] \ - -group [get_clocks $clk_dac2] - -#set_clock_group -name clk_axi_to_tproc -asynchronous \ -# -group [get_clocks $clk_axi] \ -# -group [get_clocks $clk_tproc] - -#set_clock_group -name clk_tproc_to_dac0 -asynchronous \ -# -group [get_clocks $clk_tproc] \ -# -group [get_clocks $clk_dac0] - -set_clock_group -name clk_tproc_to_dac2 -asynchronous \ - -group [get_clocks $clk_dac0] \ - -group [get_clocks $clk_dac2] - -set_clock_group -name clk_tproc_to_adc0_x2 -asynchronous \ - -group [get_clocks $clk_dac0] \ - -group [get_clocks $clk_adc0_x2] \ No newline at end of file diff --git a/firmware/RFSoc_4x2/RF4x2_src/bd_2023-1.tcl b/firmware/RFSoc_4x2/RF4x2_src/bd_2023-1.tcl new file mode 100644 index 0000000..d10fa5c --- /dev/null +++ b/firmware/RFSoc_4x2/RF4x2_src/bd_2023-1.tcl @@ -0,0 +1,2056 @@ + +################################################################ +# This is a generated script based on design: d_1 +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2023.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source d_1_script.tcl + + +# The design that will be created by this Tcl script contains the following +# module references: +# vect2bits_16 + +# Please add the sources of those modules before sourcing this Tcl script. + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu48dr-ffvg1517-2-e + set_property BOARD_PART realdigital.org:rfsoc4x2:part0:1.0 [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name d_1 + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_intc:4.1\ +user.org:user:axis_buffer_ddr_v1:1.0\ +user.org:user:axis_register_slice_nb:1.0\ +user.org:user:axis_set_reg:1.0\ +user.org:user:axis_signal_gen_v6:1.0\ +user.org:user:axis_tproc64x32_x8:1.0\ +user.org:user:mr_buffer_et:1.1\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:xlconcat:2.1\ +user.org:user:axis_avg_buffer:1.1\ +xilinx.com:ip:axi_bram_ctrl:4.1\ +xilinx.com:ip:blk_mem_gen:8.4\ +xilinx.com:ip:axi_dma:7.1\ +xilinx.com:ip:smartconnect:1.0\ +xilinx.com:ip:axis_broadcaster:1.1\ +xilinx.com:ip:axis_clock_converter:1.1\ +xilinx.com:ip:axis_dwidth_converter:1.1\ +user.org:user:axis_readout_v2:1.0\ +xilinx.com:ip:axis_register_slice:1.1\ +xilinx.com:ip:axis_switch:1.1\ +xilinx.com:ip:clk_wiz:6.0\ +xilinx.com:ip:ddr4:2.2\ +xilinx.com:ip:usp_rf_data_converter:2.6\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:zynq_ultra_ps_e:3.5\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 1 +if { $bCheckModules == 1 } { + set list_check_mods "\ +vect2bits_16\ +" + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set adc0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc0_clk ] + + set dac0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac0_clk ] + + set dac2_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac2_clk ] + + set ddr4_pl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_pl ] + + set sys_clk_ddr4 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk_ddr4 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {200000000} \ + ] $sys_clk_ddr4 + + set sysref_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0 sysref_in ] + + set vin0_01 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin0_01 ] + + set vin0_23 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin0_23 ] + + set vout00 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout00 ] + + set vout20 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout20 ] + + + # Create ports + set PMOD0_0 [ create_bd_port -dir O PMOD0_0 ] + set PMOD0_1 [ create_bd_port -dir O PMOD0_1 ] + set PMOD0_2 [ create_bd_port -dir O PMOD0_2 ] + set PMOD0_3 [ create_bd_port -dir O PMOD0_3 ] + set PMOD0_4 [ create_bd_port -dir O PMOD0_4 ] + set PMOD0_5 [ create_bd_port -dir O PMOD0_5 ] + set PMOD0_6 [ create_bd_port -dir O PMOD0_6 ] + set PMOD0_7 [ create_bd_port -dir O PMOD0_7 ] + set PMOD1_0 [ create_bd_port -dir I PMOD1_0 ] + + # Create instance: axi_intc_0, and set properties + set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ] + set_property CONFIG.C_IRQ_CONNECTION {1} $axi_intc_0 + + + # Create instance: axis_buffer_ddr_v1_0, and set properties + set axis_buffer_ddr_v1_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_buffer_ddr_v1:1.0 axis_buffer_ddr_v1_0 ] + set_property CONFIG.TARGET_SLAVE_BASE_ADDR {0x00000000} $axis_buffer_ddr_v1_0 + + + # Create instance: axis_register_slice_0, and set properties + set axis_register_slice_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_register_slice_nb:1.0 axis_register_slice_0 ] + set_property -dict [list \ + CONFIG.B {256} \ + CONFIG.N {4} \ + ] $axis_register_slice_0 + + + # Create instance: axis_register_slice_1, and set properties + set axis_register_slice_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_register_slice_nb:1.0 axis_register_slice_1 ] + set_property -dict [list \ + CONFIG.B {256} \ + CONFIG.N {4} \ + ] $axis_register_slice_1 + + + # Create instance: axis_set_reg_0, and set properties + set axis_set_reg_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_set_reg:1.0 axis_set_reg_0 ] + set_property CONFIG.DATA_WIDTH {160} $axis_set_reg_0 + + + # Create instance: axis_signal_gen_v6_0, and set properties + set axis_signal_gen_v6_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_0 ] + + # Create instance: axis_signal_gen_v6_1, and set properties + set axis_signal_gen_v6_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_1 ] + + # Create instance: axis_tproc64x32_x8_0, and set properties + set axis_tproc64x32_x8_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_tproc64x32_x8:1.0 axis_tproc64x32_x8_0 ] + + # Create instance: mr_buffer_et_0, and set properties + set mr_buffer_et_0 [ create_bd_cell -type ip -vlnv user.org:user:mr_buffer_et:1.1 mr_buffer_et_0 ] + set_property -dict [list \ + CONFIG.B {32} \ + CONFIG.N {10} \ + ] $mr_buffer_et_0 + + + # Create instance: rst_100, and set properties + set rst_100 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_100 ] + + # Create instance: rst_adc0, and set properties + set rst_adc0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0 ] + + # Create instance: rst_adc0_x2, and set properties + set rst_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0_x2 ] + + # Create instance: rst_dac0, and set properties + set rst_dac0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac0 ] + + # Create instance: rst_dac1, and set properties + set rst_dac1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac1 ] + + # Create instance: rst_ddr4, and set properties + set rst_ddr4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ddr4 ] + + # Create instance: vect2bits_16_0, and set properties + set block_name vect2bits_16 + set block_cell_name vect2bits_16_0 + if { [catch {set vect2bits_16_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $vect2bits_16_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property CONFIG.NUM_PORTS {6} $xlconcat_0 + + + # Create instance: axis_avg_buffer_0, and set properties + set axis_avg_buffer_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.1 axis_avg_buffer_0 ] + set_property -dict [list \ + CONFIG.N_AVG {14} \ + CONFIG.N_BUF {10} \ + ] $axis_avg_buffer_0 + + + # Create instance: axis_avg_buffer_1, and set properties + set axis_avg_buffer_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.1 axis_avg_buffer_1 ] + set_property -dict [list \ + CONFIG.N_AVG {14} \ + CONFIG.N_BUF {10} \ + ] $axis_avg_buffer_1 + + + # Create instance: axi_bram_ctrl_0, and set properties + set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ] + set_property -dict [list \ + CONFIG.DATA_WIDTH {64} \ + CONFIG.SINGLE_PORT_BRAM {1} \ + ] $axi_bram_ctrl_0 + + + # Create instance: axi_bram_ctrl_0_bram, and set properties + set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] + set_property -dict [list \ + CONFIG.EN_SAFETY_CKT {false} \ + CONFIG.Enable_32bit_Address {true} \ + CONFIG.Enable_B {Use_ENB_Pin} \ + CONFIG.Memory_Type {True_Dual_Port_RAM} \ + CONFIG.Port_B_Clock {100} \ + CONFIG.Port_B_Enable_Rate {100} \ + CONFIG.Port_B_Write_Rate {50} \ + CONFIG.Read_Width_B {64} \ + CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ + CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \ + CONFIG.Use_RSTA_Pin {true} \ + CONFIG.Use_RSTB_Pin {true} \ + CONFIG.Write_Width_B {64} \ + CONFIG.use_bram_block {BRAM_Controller} \ + ] $axi_bram_ctrl_0_bram + + + # Create instance: axi_dma_avg, and set properties + set axi_dma_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_avg ] + set_property -dict [list \ + CONFIG.c_include_mm2s {0} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_avg + + + # Create instance: axi_dma_buf, and set properties + set axi_dma_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_buf ] + set_property -dict [list \ + CONFIG.c_include_mm2s {0} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_buf + + + # Create instance: axi_dma_gen, and set properties + set axi_dma_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_gen ] + set_property -dict [list \ + CONFIG.c_include_s2mm {0} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_gen + + + # Create instance: axi_dma_mr, and set properties + set axi_dma_mr [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_mr ] + set_property -dict [list \ + CONFIG.c_include_mm2s {0} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_mr + + + # Create instance: axi_dma_tproc, and set properties + set axi_dma_tproc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_tproc ] + set_property CONFIG.c_include_sg {0} $axi_dma_tproc + + + # Create instance: axi_smc, and set properties + set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] + set_property CONFIG.NUM_SI {6} $axi_smc + + + # Create instance: axis_broadcaster_0, and set properties + set axis_broadcaster_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 axis_broadcaster_0 ] + set_property -dict [list \ + CONFIG.HAS_TREADY {0} \ + ] $axis_broadcaster_0 + + + # Create instance: axis_broadcaster_1, and set properties + set axis_broadcaster_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 axis_broadcaster_1 ] + set_property -dict [list \ + CONFIG.HAS_TREADY {0} \ + ] $axis_broadcaster_1 + + + # Create instance: axis_cc_avg_0, and set properties + set axis_cc_avg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_cc_avg_0 ] + + # Create instance: axis_cc_avg_1, and set properties + set axis_cc_avg_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_cc_avg_1 ] + + # Create instance: axis_cc_sg_0, and set properties + set axis_cc_sg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_cc_sg_0 ] + set_property CONFIG.SYNCHRONIZATION_STAGES {4} $axis_cc_sg_0 + + + # Create instance: axis_cc_sg_1, and set properties + set axis_cc_sg_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_cc_sg_1 ] + set_property CONFIG.SYNCHRONIZATION_STAGES {4} $axis_cc_sg_1 + + + # Create instance: axis_clock_converter_0, and set properties + set axis_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clock_converter_0 ] + + # Create instance: axis_dwidth_converter_0, and set properties + set axis_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_converter_0 ] + set_property CONFIG.M_TDATA_NUM_BYTES {64} $axis_dwidth_converter_0 + + + # Create instance: axis_readout_v2_0, and set properties + set axis_readout_v2_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_0 ] + + # Create instance: axis_readout_v2_1, and set properties + set axis_readout_v2_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_1 ] + + # Create instance: axis_register_slice_2, and set properties + set axis_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_2 ] + set_property CONFIG.REG_CONFIG {16} $axis_register_slice_2 + + + # Create instance: axis_register_slice_3, and set properties + set axis_register_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_3 ] + set_property CONFIG.REG_CONFIG {16} $axis_register_slice_3 + + + # Create instance: axis_switch_avg, and set properties + set axis_switch_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_avg ] + set_property CONFIG.ROUTING_MODE {1} $axis_switch_avg + + + # Create instance: axis_switch_buf, and set properties + set axis_switch_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_buf ] + set_property CONFIG.ROUTING_MODE {1} $axis_switch_buf + + + # Create instance: axis_switch_ddr4, and set properties + set axis_switch_ddr4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_ddr4 ] + set_property CONFIG.ROUTING_MODE {1} $axis_switch_ddr4 + + + # Create instance: axis_switch_gen, and set properties + set axis_switch_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_gen ] + set_property -dict [list \ + CONFIG.DECODER_REG {1} \ + CONFIG.NUM_MI {2} \ + CONFIG.NUM_SI {1} \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_gen + + + # Create instance: axis_switch_mr, and set properties + set axis_switch_mr [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_mr ] + set_property CONFIG.ROUTING_MODE {1} $axis_switch_mr + + + # Create instance: clk_adc0_x2, and set properties + set clk_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_adc0_x2 ] + set_property -dict [list \ + CONFIG.CLKIN1_JITTER_PS {65.10000000000001} \ + CONFIG.CLKOUT1_JITTER {88.197} \ + CONFIG.CLKOUT1_PHASE_ERROR {84.444} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {307.2} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {7.750} \ + CONFIG.MMCM_CLKIN1_PERIOD {6.510} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {3.875} \ + CONFIG.MMCM_DIVCLK_DIVIDE {1} \ + CONFIG.OPTIMIZE_CLOCKING_STRUCTURE_EN {true} \ + CONFIG.PRIM_SOURCE {Global_buffer} \ + CONFIG.RESET_PORT {resetn} \ + CONFIG.RESET_TYPE {ACTIVE_LOW} \ + ] $clk_adc0_x2 + + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [list \ + CONFIG.C0.BANK_GROUP_WIDTH {1} \ + CONFIG.C0.DDR4_AxiAddressWidth {32} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_CasLatency {16} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_DataWidth {64} \ + CONFIG.C0.DDR4_InputClockPeriod {4998} \ + CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-083E} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.System_Clock {Differential} \ + ] $ddr4_0 + + + # Create instance: ps8_0_axi_periph, and set properties + set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] + set_property CONFIG.NUM_MI {22} $ps8_0_axi_periph + + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + + # Create instance: usp_rf_data_converter_0, and set properties + set usp_rf_data_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.6 usp_rf_data_converter_0 ] + set_property -dict [list \ + CONFIG.ADC0_Outclk_Freq {153.600} \ + CONFIG.ADC0_PLL_Enable {true} \ + CONFIG.ADC0_Refclk_Freq {409.600} \ + CONFIG.ADC0_Sampling_Rate {2.4576} \ + CONFIG.ADC_Coarse_Mixer_Freq02 {3} \ + CONFIG.ADC_Data_Width00 {8} \ + CONFIG.ADC_Data_Width02 {8} \ + CONFIG.ADC_Decimation_Mode02 {1} \ + CONFIG.ADC_Mixer_Type02 {1} \ + CONFIG.ADC_Slice02_Enable {true} \ + CONFIG.DAC0_Outclk_Freq {307.200} \ + CONFIG.DAC0_PLL_Enable {true} \ + CONFIG.DAC0_Refclk_Freq {409.600} \ + CONFIG.DAC0_Sampling_Rate {4.9152} \ + CONFIG.DAC2_Outclk_Freq {307.200} \ + CONFIG.DAC2_PLL_Enable {true} \ + CONFIG.DAC2_Refclk_Freq {409.600} \ + CONFIG.DAC2_Sampling_Rate {4.9152} \ + CONFIG.DAC_Coarse_Mixer_Freq00 {3} \ + CONFIG.DAC_Coarse_Mixer_Freq20 {3} \ + CONFIG.DAC_Interpolation_Mode00 {1} \ + CONFIG.DAC_Interpolation_Mode20 {1} \ + CONFIG.DAC_Mixer_Type00 {1} \ + CONFIG.DAC_Mixer_Type20 {1} \ + CONFIG.DAC_Mode00 {3} \ + CONFIG.DAC_Mode20 {3} \ + CONFIG.DAC_Slice00_Enable {true} \ + CONFIG.DAC_Slice20_Enable {true} \ + ] $usp_rf_data_converter_0 + + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property -dict [list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {64} \ + ] $xlconstant_0 + + + # Create instance: xlconstant_1, and set properties + set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] + set_property -dict [list \ + CONFIG.CONST_VAL {1} \ + CONFIG.CONST_WIDTH {1} \ + ] $xlconstant_1 + + + # Create instance: xlconstant_2, and set properties + set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ] + set_property -dict [list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {1} \ + ] $xlconstant_2 + + + # Create instance: xlconstant_3, and set properties + set xlconstant_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_3 ] + set_property -dict [list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {8} \ + ] $xlconstant_3 + + + # Create instance: zynq_ultra_ps_e_0, and set properties + set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 zynq_ultra_ps_e_0 ] + set_property -dict [list \ + CONFIG.CAN0_BOARD_INTERFACE {custom} \ + CONFIG.CAN1_BOARD_INTERFACE {custom} \ + CONFIG.CSU_BOARD_INTERFACE {custom} \ + CONFIG.DP_BOARD_INTERFACE {custom} \ + CONFIG.GEM0_BOARD_INTERFACE {custom} \ + CONFIG.GEM1_BOARD_INTERFACE {custom} \ + CONFIG.GEM2_BOARD_INTERFACE {custom} \ + CONFIG.GEM3_BOARD_INTERFACE {custom} \ + CONFIG.GPIO_BOARD_INTERFACE {custom} \ + CONFIG.IIC0_BOARD_INTERFACE {custom} \ + CONFIG.IIC1_BOARD_INTERFACE {custom} \ + CONFIG.NAND_BOARD_INTERFACE {custom} \ + CONFIG.PCIE_BOARD_INTERFACE {custom} \ + CONFIG.PJTAG_BOARD_INTERFACE {custom} \ + CONFIG.PMU_BOARD_INTERFACE {custom} \ + CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS33} \ + CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ + CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ + CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ + CONFIG.PSU_IMPORT_BOARD_PRESET {} \ + CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_0_SLEW {fast} \ + CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_10_SLEW {fast} \ + CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_11_SLEW {fast} \ + CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_12_POLARITY {Default} \ + CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_12_SLEW {fast} \ + CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_13_SLEW {fast} \ + CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_14_SLEW {fast} \ + CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_15_SLEW {fast} \ + CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_16_SLEW {fast} \ + CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_17_POLARITY {Default} \ + CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_17_SLEW {fast} \ + CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_18_SLEW {fast} \ + CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_19_SLEW {fast} \ + CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_1_SLEW {fast} \ + CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_20_POLARITY {Default} \ + CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_20_SLEW {fast} \ + CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_21_SLEW {fast} \ + CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_22_SLEW {fast} \ + CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_23_POLARITY {Default} \ + CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_23_SLEW {fast} \ + CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_26_POLARITY {Default} \ + CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_26_SLEW {fast} \ + CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_27_SLEW {fast} \ + CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_29_SLEW {fast} \ + CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_2_SLEW {fast} \ + CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_31_POLARITY {Default} \ + CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_31_SLEW {fast} \ + CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_32_SLEW {fast} \ + CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_34_POLARITY {Default} \ + CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_34_SLEW {fast} \ + CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_35_POLARITY {Default} \ + CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_35_SLEW {fast} \ + CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_36_SLEW {fast} \ + CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_37_SLEW {fast} \ + CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_38_SLEW {fast} \ + CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_39_SLEW {fast} \ + CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_3_SLEW {fast} \ + CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_40_SLEW {fast} \ + CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_41_SLEW {fast} \ + CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_42_SLEW {fast} \ + CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_43_SLEW {fast} \ + CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_4_SLEW {fast} \ + CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_50_SLEW {fast} \ + CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_51_SLEW {fast} \ + CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_54_SLEW {fast} \ + CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_56_SLEW {fast} \ + CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_57_SLEW {fast} \ + CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_58_SLEW {fast} \ + CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_59_SLEW {fast} \ + CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_5_SLEW {fast} \ + CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_60_SLEW {fast} \ + CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_61_SLEW {fast} \ + CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_62_SLEW {fast} \ + CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_63_SLEW {fast} \ + CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_66_SLEW {fast} \ + CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_68_SLEW {fast} \ + CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_69_SLEW {fast} \ + CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_6_SLEW {fast} \ + CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_70_SLEW {fast} \ + CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_71_SLEW {fast} \ + CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_72_SLEW {fast} \ + CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_73_SLEW {fast} \ + CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_74_SLEW {fast} \ + CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_75_SLEW {fast} \ + CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_76_POLARITY {Default} \ + CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_76_SLEW {fast} \ + CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_77_POLARITY {Default} \ + CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_77_SLEW {fast} \ + CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_7_POLARITY {Default} \ + CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_7_SLEW {fast} \ + CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_8_POLARITY {Default} \ + CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_8_SLEW {fast} \ + CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_9_SLEW {fast} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {SPI 0#SPI 0#SPI 0#SPI 0#SPI 0#SPI 0#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#I2C 0#I2C 0#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD\ +0#SD 0#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#UART 1#UART 1#GPIO1 MIO#GPIO1 MIO#I2C 1#I2C 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#MDIO 1#MDIO 1#USB 0#USB 0#USB 0#USB\ +0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \ + CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#n_ss_out[2]#n_ss_out[1]#n_ss_out[0]#miso#mosi#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#scl_out#sda_out#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#sdio0_wp#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#txd#rxd#gpio1[34]#gpio1[35]#scl_out#sda_out#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem1_mdc#gem1_mdio_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]}\ +\ + CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \ + CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \ + CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_SMC_CYCLE_T0 {NA} \ + CONFIG.PSU_SMC_CYCLE_T1 {NA} \ + CONFIG.PSU_SMC_CYCLE_T2 {NA} \ + CONFIG.PSU_SMC_CYCLE_T3 {NA} \ + CONFIG.PSU_SMC_CYCLE_T4 {NA} \ + CONFIG.PSU_SMC_CYCLE_T5 {NA} \ + CONFIG.PSU_SMC_CYCLE_T6 {NA} \ + CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ + CONFIG.PSU_VALUE_SILVERSION {3} \ + CONFIG.PSU__ACPU0__POWER__ON {1} \ + CONFIG.PSU__ACPU1__POWER__ON {1} \ + CONFIG.PSU__ACPU2__POWER__ON {1} \ + CONFIG.PSU__ACPU3__POWER__ON {1} \ + CONFIG.PSU__ACTUAL__IP {1} \ + CONFIG.PSU__ACT_DDR_FREQ_MHZ {1199.999756} \ + CONFIG.PSU__AFI0_COHERENCY {0} \ + CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \ + CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.999756} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {599.999878} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.999878} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.999996} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.249996} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {299.999939} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.999878} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {0} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \ + CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {399.999908} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {524.999939} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {533.333} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999992} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.999908} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.999756} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {124.999977} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {262.499969} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {267} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {524.999939} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {533.333} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.499969} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {300} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.499969} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.499969} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.499969} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {33.333328} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999996} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ + CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \ + CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__DDRC__AL {0} \ + CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ + CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ + CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ + CONFIG.PSU__DDRC__CL {16} \ + CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ + CONFIG.PSU__DDRC__COMPONENTS {Components} \ + CONFIG.PSU__DDRC__CWL {12} \ + CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {1} \ + CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ + CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ + CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ + CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ + CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ + CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ + CONFIG.PSU__DDRC__ECC {Disabled} \ + CONFIG.PSU__DDRC__ECC_SCRUB {0} \ + CONFIG.PSU__DDRC__ENABLE {1} \ + CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \ + CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \ + CONFIG.PSU__DDRC__EN_2ND_CLK {0} \ + CONFIG.PSU__DDRC__FGRM {1X} \ + CONFIG.PSU__DDRC__FREQ_MHZ {1} \ + CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \ + CONFIG.PSU__DDRC__LP_ASR {manual normal} \ + CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ + CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ + CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ + CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ + CONFIG.PSU__DDRC__PLL_BYPASS {0} \ + CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ + CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \ + CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \ + CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ + CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2400R} \ + CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ + CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ + CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ + CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ + CONFIG.PSU__DDRC__T_FAW {30.0} \ + CONFIG.PSU__DDRC__T_RAS_MIN {32.0} \ + CONFIG.PSU__DDRC__T_RC {45.32} \ + CONFIG.PSU__DDRC__T_RCD {16} \ + CONFIG.PSU__DDRC__T_RP {16} \ + CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \ + CONFIG.PSU__DDRC__VREF {1} \ + CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ + CONFIG.PSU__DDR_QOS_ENABLE {0} \ + CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \ + CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \ + CONFIG.PSU__DDR__INTERFACE__FREQMHZ {600.000} \ + CONFIG.PSU__DEVICE_TYPE {RFSOC} \ + CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ + CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ + CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \ + CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \ + CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DLL__ISUSED {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ + CONFIG.PSU__DP__LANE_SEL {Dual Lower} \ + CONFIG.PSU__DP__REF_CLK_FREQ {27} \ + CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk0} \ + CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \ + CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET1__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {1} \ + CONFIG.PSU__ENET1__GRP_MDIO__IO {MIO 50 .. 51} \ + CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__ENET1__PERIPHERAL__IO {MIO 38 .. 49} \ + CONFIG.PSU__ENET1__PTP__ENABLE {0} \ + CONFIG.PSU__ENET1__TSU__ENABLE {0} \ + CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \ + CONFIG.PSU__EN_EMIO_TRACE {0} \ + CONFIG.PSU__EP__IP {0} \ + CONFIG.PSU__EXPAND__CORESIGHT {0} \ + CONFIG.PSU__EXPAND__FPD_SLAVES {0} \ + CONFIG.PSU__EXPAND__GIC {0} \ + CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \ + CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \ + CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100} \ + CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100} \ + CONFIG.PSU__FPGA_PL0_ENABLE {1} \ + CONFIG.PSU__FPGA_PL1_ENABLE {0} \ + CONFIG.PSU__FPGA_PL2_ENABLE {0} \ + CONFIG.PSU__FPGA_PL3_ENABLE {0} \ + CONFIG.PSU__FP__POWER__ON {1} \ + CONFIG.PSU__FTM__CTI_IN_0 {0} \ + CONFIG.PSU__FTM__CTI_IN_1 {0} \ + CONFIG.PSU__FTM__CTI_IN_2 {0} \ + CONFIG.PSU__FTM__CTI_IN_3 {0} \ + CONFIG.PSU__FTM__CTI_OUT_0 {0} \ + CONFIG.PSU__FTM__CTI_OUT_1 {0} \ + CONFIG.PSU__FTM__CTI_OUT_2 {0} \ + CONFIG.PSU__FTM__CTI_OUT_3 {0} \ + CONFIG.PSU__FTM__GPI {0} \ + CONFIG.PSU__FTM__GPO {0} \ + CONFIG.PSU__GEM1_COHERENCY {0} \ + CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM__TSU__ENABLE {0} \ + CONFIG.PSU__GEN_IPI_0__MASTER {APU} \ + CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \ + CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \ + CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \ + CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ + CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ + CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \ + CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO_EMIO_WIDTH {95} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {95} \ + CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \ + CONFIG.PSU__GPU_PP0__POWER__ON {0} \ + CONFIG.PSU__GPU_PP1__POWER__ON {0} \ + CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__GT__LINK_SPEED {HBR} \ + CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ + CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ + CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \ + CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 18 .. 19} \ + CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 36 .. 37} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100} \ + CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \ + CONFIG.PSU__IRQ_P2F_AMS__INT {0} \ + CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \ + CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \ + CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT1_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT1__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPU__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \ + CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \ + CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \ + CONFIG.PSU__IRQ_P2F_SATA__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO0_WAKE__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO0__INT {0} \ + CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \ + CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \ + CONFIG.PSU__IRQ_P2F_UART1__INT {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \ + CONFIG.PSU__L2_BANK0__POWER__ON {1} \ + CONFIG.PSU__LPDMA0_COHERENCY {0} \ + CONFIG.PSU__LPDMA1_COHERENCY {0} \ + CONFIG.PSU__LPDMA2_COHERENCY {0} \ + CONFIG.PSU__LPDMA3_COHERENCY {0} \ + CONFIG.PSU__LPDMA4_COHERENCY {0} \ + CONFIG.PSU__LPDMA5_COHERENCY {0} \ + CONFIG.PSU__LPDMA6_COHERENCY {0} \ + CONFIG.PSU__LPDMA7_COHERENCY {0} \ + CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100} \ + CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \ + CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \ + CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \ + CONFIG.PSU__NUM_FABRIC_RESETS {1} \ + CONFIG.PSU__OCM_BANK0__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK1__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK2__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK3__POWER__ON {1} \ + CONFIG.PSU__OVERRIDE_HPX_QOS {0} \ + CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ + CONFIG.PSU__PCIE__ACS_VIOLAION {0} \ + CONFIG.PSU__PCIE__AER_CAPABILITY {0} \ + CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \ + CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \ + CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \ + CONFIG.PSU__PCIE__DEVICE_ID {} \ + CONFIG.PSU__PCIE__INTX_GENERATION {0} \ + CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \ + CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \ + CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \ + CONFIG.PSU__PCIE__REVISION_ID {} \ + CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \ + CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \ + CONFIG.PSU__PCIE__VENDOR_ID {} \ + CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PL_CLK0_BUF {TRUE} \ + CONFIG.PSU__PL__POWER__ON {1} \ + CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PRESET_APPLIED {1} \ + CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__ENABLE {0} \ + CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware | SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write;\ +subsystemId:Secure Subsystem} \ + CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU\ +Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\ +SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000\ +; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000\ +; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \ + CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;0|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;1|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\ +\ + CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure}\ +\ + CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \ + CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;0|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;0|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;1|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\ +Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\ +\ + CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \ + CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \ + CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.33333} \ + CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__REPORT__DBGLOG {0} \ + CONFIG.PSU__RPU_COHERENCY {0} \ + CONFIG.PSU__RPU__POWER__ON {1} \ + CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \ + CONFIG.PSU__SD0_COHERENCY {0} \ + CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__SD0__CLK_50_SDR_ITAP_DLY {0x15} \ + CONFIG.PSU__SD0__CLK_50_SDR_OTAP_DLY {0x5} \ + CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \ + CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \ + CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \ + CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \ + CONFIG.PSU__SD0__GRP_WP__ENABLE {1} \ + CONFIG.PSU__SD0__GRP_WP__IO {MIO 25} \ + CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \ + CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \ + CONFIG.PSU__SD1__CLK_100_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD1__CLK_200_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD1__CLK_50_DDR_ITAP_DLY {0x3D} \ + CONFIG.PSU__SD1__CLK_50_DDR_OTAP_DLY {0x4} \ + CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \ + CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \ + CONFIG.PSU__SD1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SD1__RESET__ENABLE {0} \ + CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 3} \ + CONFIG.PSU__SPI0__GRP_SS1__ENABLE {1} \ + CONFIG.PSU__SPI0__GRP_SS1__IO {MIO 2} \ + CONFIG.PSU__SPI0__GRP_SS2__ENABLE {1} \ + CONFIG.PSU__SPI0__GRP_SS2__IO {MIO 1} \ + CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 0 .. 5} \ + CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \ + CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \ + CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \ + CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \ + CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \ + CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TCM0A__POWER__ON {1} \ + CONFIG.PSU__TCM0B__POWER__ON {1} \ + CONFIG.PSU__TCM1A__POWER__ON {1} \ + CONFIG.PSU__TCM1B__POWER__ON {1} \ + CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \ + CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TRISTATE__INVERTED {1} \ + CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ + CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \ + CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \ + CONFIG.PSU__UART0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__UART1__BAUD_RATE {115200} \ + CONFIG.PSU__UART1__MODEM__ENABLE {0} \ + CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 32 .. 33} \ + CONFIG.PSU__USB0_COHERENCY {0} \ + CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ + CONFIG.PSU__USB0__REF_CLK_FREQ {100} \ + CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk1} \ + CONFIG.PSU__USB1_COHERENCY {0} \ + CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \ + CONFIG.PSU__USB1__REF_CLK_FREQ {100} \ + CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk1} \ + CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ + CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \ + CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ + CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \ + CONFIG.PSU__USE__ADMA {0} \ + CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \ + CONFIG.PSU__USE__AUDIO {0} \ + CONFIG.PSU__USE__CLK {0} \ + CONFIG.PSU__USE__CLK0 {0} \ + CONFIG.PSU__USE__CLK1 {0} \ + CONFIG.PSU__USE__CLK2 {0} \ + CONFIG.PSU__USE__CLK3 {0} \ + CONFIG.PSU__USE__CROSS_TRIGGER {0} \ + CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \ + CONFIG.PSU__USE__DEBUG__TEST {0} \ + CONFIG.PSU__USE__EVENT_RPU {0} \ + CONFIG.PSU__USE__FABRIC__RST {1} \ + CONFIG.PSU__USE__FTM {0} \ + CONFIG.PSU__USE__GDMA {0} \ + CONFIG.PSU__USE__IRQ {0} \ + CONFIG.PSU__USE__IRQ0 {1} \ + CONFIG.PSU__USE__IRQ1 {1} \ + CONFIG.PSU__USE__M_AXI_GP0 {1} \ + CONFIG.PSU__USE__M_AXI_GP1 {1} \ + CONFIG.PSU__USE__M_AXI_GP2 {0} \ + CONFIG.PSU__USE__PROC_EVENT_BUS {0} \ + CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \ + CONFIG.PSU__USE__RST0 {0} \ + CONFIG.PSU__USE__RST1 {0} \ + CONFIG.PSU__USE__RST2 {0} \ + CONFIG.PSU__USE__RST3 {0} \ + CONFIG.PSU__USE__RTC {0} \ + CONFIG.PSU__USE__STM {0} \ + CONFIG.PSU__USE__S_AXI_ACE {0} \ + CONFIG.PSU__USE__S_AXI_ACP {0} \ + CONFIG.PSU__USE__S_AXI_GP0 {1} \ + CONFIG.PSU__USE__S_AXI_GP1 {0} \ + CONFIG.PSU__USE__S_AXI_GP2 {0} \ + CONFIG.PSU__USE__S_AXI_GP3 {0} \ + CONFIG.PSU__USE__S_AXI_GP4 {0} \ + CONFIG.PSU__USE__S_AXI_GP5 {0} \ + CONFIG.PSU__USE__S_AXI_GP6 {0} \ + CONFIG.PSU__USE__USB3_0_HUB {0} \ + CONFIG.PSU__USE__USB3_1_HUB {0} \ + CONFIG.PSU__USE__VIDEO {0} \ + CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \ + CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \ + CONFIG.QSPI_BOARD_INTERFACE {custom} \ + CONFIG.SATA_BOARD_INTERFACE {custom} \ + CONFIG.SD0_BOARD_INTERFACE {custom} \ + CONFIG.SD1_BOARD_INTERFACE {custom} \ + CONFIG.SPI0_BOARD_INTERFACE {custom} \ + CONFIG.SPI1_BOARD_INTERFACE {custom} \ + CONFIG.SUBPRESET1 {Custom} \ + CONFIG.SUBPRESET2 {Custom} \ + CONFIG.SWDT0_BOARD_INTERFACE {custom} \ + CONFIG.SWDT1_BOARD_INTERFACE {custom} \ + CONFIG.TRACE_BOARD_INTERFACE {custom} \ + CONFIG.TTC0_BOARD_INTERFACE {custom} \ + CONFIG.TTC1_BOARD_INTERFACE {custom} \ + CONFIG.TTC2_BOARD_INTERFACE {custom} \ + CONFIG.TTC3_BOARD_INTERFACE {custom} \ + CONFIG.UART0_BOARD_INTERFACE {custom} \ + CONFIG.UART1_BOARD_INTERFACE {custom} \ + CONFIG.USB0_BOARD_INTERFACE {custom} \ + CONFIG.USB1_BOARD_INTERFACE {custom} \ + ] $zynq_ultra_ps_e_0 + + + # Create interface connections + connect_bd_intf_net -intf_net adc0_clk_1 [get_bd_intf_ports adc0_clk] [get_bd_intf_pins usp_rf_data_converter_0/adc0_clk] + connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTA] + connect_bd_intf_net -intf_net axi_dma_avg_M_AXI_S2MM [get_bd_intf_pins axi_dma_avg/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S00_AXI] + connect_bd_intf_net -intf_net axi_dma_buf_M_AXI_S2MM [get_bd_intf_pins axi_dma_buf/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S01_AXI] + connect_bd_intf_net -intf_net axi_dma_gen_M_AXIS_MM2S [get_bd_intf_pins axi_dma_gen/M_AXIS_MM2S] [get_bd_intf_pins axis_switch_gen/S00_AXIS] + connect_bd_intf_net -intf_net axi_dma_gen_M_AXI_MM2S [get_bd_intf_pins axi_dma_gen/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S03_AXI] + connect_bd_intf_net -intf_net axi_dma_readout_M_AXI_S2MM [get_bd_intf_pins axi_dma_mr/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S02_AXI] + connect_bd_intf_net -intf_net axi_dma_tproc_M_AXIS_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXIS_MM2S] [get_bd_intf_pins axis_tproc64x32_x8_0/s0_axis] + connect_bd_intf_net -intf_net axi_dma_tproc_M_AXI_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S04_AXI] + connect_bd_intf_net -intf_net axi_dma_tproc_M_AXI_S2MM [get_bd_intf_pins axi_dma_tproc/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S05_AXI] + connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HPC0_FPD] + connect_bd_intf_net -intf_net axis_avg_buffer_0_m0_axis [get_bd_intf_pins axis_avg_buffer_0/m0_axis] [get_bd_intf_pins axis_switch_avg/S00_AXIS] + connect_bd_intf_net -intf_net axis_avg_buffer_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/m1_axis] [get_bd_intf_pins axis_switch_buf/S00_AXIS] + connect_bd_intf_net -intf_net axis_avg_buffer_0_m2_axis [get_bd_intf_pins axis_avg_buffer_0/m2_axis] [get_bd_intf_pins axis_cc_avg_0/S_AXIS] + connect_bd_intf_net -intf_net axis_avg_buffer_1_m0_axis [get_bd_intf_pins axis_avg_buffer_1/m0_axis] [get_bd_intf_pins axis_switch_avg/S01_AXIS] + connect_bd_intf_net -intf_net axis_avg_buffer_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/m1_axis] [get_bd_intf_pins axis_switch_buf/S01_AXIS] + connect_bd_intf_net -intf_net axis_avg_buffer_1_m2_axis [get_bd_intf_pins axis_avg_buffer_1/m2_axis] [get_bd_intf_pins axis_cc_avg_1/S_AXIS] + connect_bd_intf_net -intf_net axis_broadcaster_0_M00_AXIS [get_bd_intf_pins axis_avg_buffer_0/s_axis] [get_bd_intf_pins axis_broadcaster_0/M00_AXIS] + connect_bd_intf_net -intf_net axis_broadcaster_0_M01_AXIS [get_bd_intf_pins axis_broadcaster_0/M01_AXIS] [get_bd_intf_pins axis_switch_ddr4/S00_AXIS] + connect_bd_intf_net -intf_net axis_broadcaster_1_M00_AXIS [get_bd_intf_pins axis_avg_buffer_1/s_axis] [get_bd_intf_pins axis_broadcaster_1/M00_AXIS] + connect_bd_intf_net -intf_net axis_broadcaster_1_M01_AXIS [get_bd_intf_pins axis_broadcaster_1/M01_AXIS] [get_bd_intf_pins axis_switch_ddr4/S01_AXIS] + connect_bd_intf_net -intf_net axis_buffer_ddr_v1_0_m_axi [get_bd_intf_pins axis_buffer_ddr_v1_0/m_axi] [get_bd_intf_pins smartconnect_0/S01_AXI] + connect_bd_intf_net -intf_net axis_cc_avg_0_M_AXIS [get_bd_intf_pins axis_cc_avg_0/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s1_axis] + connect_bd_intf_net -intf_net axis_cc_avg_1_M_AXIS [get_bd_intf_pins axis_cc_avg_1/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s2_axis] + connect_bd_intf_net -intf_net axis_cc_sg_0_M_AXIS [get_bd_intf_pins axis_cc_sg_0/M_AXIS] [get_bd_intf_pins axis_signal_gen_v6_0/s1_axis] + connect_bd_intf_net -intf_net axis_cc_sg_1_M_AXIS [get_bd_intf_pins axis_cc_sg_1/M_AXIS] [get_bd_intf_pins axis_signal_gen_v6_1/s1_axis] + connect_bd_intf_net -intf_net axis_clock_converter_0_M_AXIS [get_bd_intf_pins axis_buffer_ddr_v1_0/s_axis] [get_bd_intf_pins axis_clock_converter_0/M_AXIS] + connect_bd_intf_net -intf_net axis_dwidth_converter_0_M_AXIS [get_bd_intf_pins axis_clock_converter_0/S_AXIS] [get_bd_intf_pins axis_dwidth_converter_0/M_AXIS] + connect_bd_intf_net -intf_net axis_readout_v2_0_m0_axis [get_bd_intf_pins axis_readout_v2_0/m0_axis] [get_bd_intf_pins axis_switch_mr/S00_AXIS] + connect_bd_intf_net -intf_net axis_readout_v2_0_m1_axis [get_bd_intf_pins axis_broadcaster_0/S_AXIS] [get_bd_intf_pins axis_readout_v2_0/m1_axis] + connect_bd_intf_net -intf_net axis_readout_v2_1_m0_axis [get_bd_intf_pins axis_readout_v2_1/m0_axis] [get_bd_intf_pins axis_switch_mr/S01_AXIS] + connect_bd_intf_net -intf_net axis_readout_v2_1_m1_axis [get_bd_intf_pins axis_broadcaster_1/S_AXIS] [get_bd_intf_pins axis_readout_v2_1/m1_axis] + connect_bd_intf_net -intf_net axis_register_slice_2_M_AXIS [get_bd_intf_pins axis_readout_v2_0/s_axis] [get_bd_intf_pins axis_register_slice_2/M_AXIS] + connect_bd_intf_net -intf_net axis_register_slice_3_M_AXIS [get_bd_intf_pins axis_readout_v2_1/s_axis] [get_bd_intf_pins axis_register_slice_3/M_AXIS] + connect_bd_intf_net -intf_net axis_register_slice_4_m_axis [get_bd_intf_pins axis_register_slice_1/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s20_axis] + connect_bd_intf_net -intf_net axis_register_slice_6_m_axis [get_bd_intf_pins axis_register_slice_0/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s00_axis] + connect_bd_intf_net -intf_net axis_signal_gen_v6_0_m_axis [get_bd_intf_pins axis_register_slice_0/s_axis] [get_bd_intf_pins axis_signal_gen_v6_0/m_axis] + connect_bd_intf_net -intf_net axis_signal_gen_v6_1_m_axis [get_bd_intf_pins axis_register_slice_1/s_axis] [get_bd_intf_pins axis_signal_gen_v6_1/m_axis] + connect_bd_intf_net -intf_net axis_switch_0_M00_AXIS [get_bd_intf_pins axis_switch_mr/M00_AXIS] [get_bd_intf_pins mr_buffer_et_0/s00_axis] + connect_bd_intf_net -intf_net axis_switch_avg_M00_AXIS [get_bd_intf_pins axi_dma_avg/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_avg/M00_AXIS] + connect_bd_intf_net -intf_net axis_switch_buf_M00_AXIS [get_bd_intf_pins axi_dma_buf/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_buf/M00_AXIS] + connect_bd_intf_net -intf_net axis_switch_ddr4_M00_AXIS [get_bd_intf_pins axis_dwidth_converter_0/S_AXIS] [get_bd_intf_pins axis_switch_ddr4/M00_AXIS] + connect_bd_intf_net -intf_net axis_switch_gen_M00_AXIS [get_bd_intf_pins axis_signal_gen_v6_0/s0_axis] [get_bd_intf_pins axis_switch_gen/M00_AXIS] + connect_bd_intf_net -intf_net axis_switch_gen_M01_AXIS [get_bd_intf_pins axis_signal_gen_v6_1/s0_axis] [get_bd_intf_pins axis_switch_gen/M01_AXIS] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m0_axis [get_bd_intf_pins axi_dma_tproc/S_AXIS_S2MM] [get_bd_intf_pins axis_tproc64x32_x8_0/m0_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m1_axis [get_bd_intf_pins axis_cc_sg_0/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m1_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m2_axis [get_bd_intf_pins axis_cc_sg_1/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m2_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m8_axis [get_bd_intf_pins axis_set_reg_0/s_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m8_axis] + connect_bd_intf_net -intf_net dac0_clk_1 [get_bd_intf_ports dac0_clk] [get_bd_intf_pins usp_rf_data_converter_0/dac0_clk] + connect_bd_intf_net -intf_net dac2_clk_1 [get_bd_intf_ports dac2_clk] [get_bd_intf_pins usp_rf_data_converter_0/dac2_clk] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_pl] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net mr_buffer_et_0_m00_axis [get_bd_intf_pins axi_dma_mr/S_AXIS_S2MM] [get_bd_intf_pins mr_buffer_et_0/m00_axis] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_dma_avg/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins axi_dma_buf/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M02_AXI [get_bd_intf_pins axi_dma_mr/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M02_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M03_AXI [get_bd_intf_pins axis_avg_buffer_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M03_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M04_AXI [get_bd_intf_pins axis_readout_v2_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M04_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M05_AXI [get_bd_intf_pins axis_readout_v2_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M05_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M06_AXI [get_bd_intf_pins axis_switch_avg/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M06_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M07_AXI [get_bd_intf_pins axis_switch_buf/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M07_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M08_AXI [get_bd_intf_pins axis_switch_mr/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M08_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M09_AXI [get_bd_intf_pins axis_tproc64x32_x8_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M09_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M10_AXI [get_bd_intf_pins mr_buffer_et_0/s00_axi] [get_bd_intf_pins ps8_0_axi_periph/M10_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M11_AXI [get_bd_intf_pins ps8_0_axi_periph/M11_AXI] [get_bd_intf_pins usp_rf_data_converter_0/s_axi] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M12_AXI [get_bd_intf_pins axis_avg_buffer_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M12_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M13_AXI [get_bd_intf_pins axis_signal_gen_v6_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M13_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M14_AXI [get_bd_intf_pins axis_signal_gen_v6_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M14_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M15_AXI [get_bd_intf_pins axi_dma_gen/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M15_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M16_AXI [get_bd_intf_pins axis_switch_gen/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M16_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M17_AXI [get_bd_intf_pins axi_dma_tproc/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M17_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M18_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M18_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M19_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M19_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M20_AXI [get_bd_intf_pins axis_buffer_ddr_v1_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M20_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M21_AXI [get_bd_intf_pins axis_switch_ddr4/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M21_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] + connect_bd_intf_net -intf_net sys_clk_ddr4_1 [get_bd_intf_ports sys_clk_ddr4] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net -intf_net sysref_in_1 [get_bd_intf_ports sysref_in] [get_bd_intf_pins usp_rf_data_converter_0/sysref_in] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_m00_axis [get_bd_intf_pins axis_register_slice_2/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m00_axis] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_m02_axis [get_bd_intf_pins axis_register_slice_3/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m02_axis] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout00 [get_bd_intf_ports vout00] [get_bd_intf_pins usp_rf_data_converter_0/vout00] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout20 [get_bd_intf_ports vout20] [get_bd_intf_pins usp_rf_data_converter_0/vout20] + connect_bd_intf_net -intf_net vin0_01_1 [get_bd_intf_ports vin0_01] [get_bd_intf_pins usp_rf_data_converter_0/vin0_01] + connect_bd_intf_net -intf_net vin0_23_1 [get_bd_intf_ports vin0_23] [get_bd_intf_pins usp_rf_data_converter_0/vin0_23] + connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD] + connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM1_FPD [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM1_FPD] + + # Create port connections + connect_bd_net -net PMOD1_0_1 [get_bd_ports PMOD1_0] [get_bd_pins axis_tproc64x32_x8_0/start] + connect_bd_net -net axi_bram_ctrl_0_bram_doutb [get_bd_pins axi_bram_ctrl_0_bram/doutb] [get_bd_pins axis_tproc64x32_x8_0/pmem_do] + connect_bd_net -net axi_dma_avg_s2mm_introut [get_bd_pins axi_dma_avg/s2mm_introut] [get_bd_pins xlconcat_0/In3] + connect_bd_net -net axi_dma_buf_s2mm_introut [get_bd_pins axi_dma_buf/s2mm_introut] [get_bd_pins xlconcat_0/In4] + connect_bd_net -net axi_dma_gen_mm2s_introut [get_bd_pins axi_dma_gen/mm2s_introut] [get_bd_pins xlconcat_0/In0] + connect_bd_net -net axi_dma_readout_s2mm_introut [get_bd_pins axi_dma_mr/s2mm_introut] [get_bd_pins xlconcat_0/In5] + connect_bd_net -net axi_dma_tproc_mm2s_introut [get_bd_pins axi_dma_tproc/mm2s_introut] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net axi_dma_tproc_s2mm_introut [get_bd_pins axi_dma_tproc/s2mm_introut] [get_bd_pins xlconcat_0/In2] + connect_bd_net -net axi_intc_0_irq [get_bd_pins axi_intc_0/irq] [get_bd_pins zynq_ultra_ps_e_0/pl_ps_irq0] + connect_bd_net -net axis_set_reg_0_dout [get_bd_pins axis_set_reg_0/dout] [get_bd_pins vect2bits_16_0/din] + connect_bd_net -net axis_tproc64x32_x8_0_pmem_addr [get_bd_pins axis_tproc64x32_x8_0/pmem_addr] [get_bd_pins axi_bram_ctrl_0_bram/addrb] + connect_bd_net -net clk_adc0_x2_clk_out1 [get_bd_pins clk_adc0_x2/clk_out1] [get_bd_pins mr_buffer_et_0/s00_axis_aclk] [get_bd_pins rst_adc0_x2/slowest_sync_clk] [get_bd_pins axis_avg_buffer_0/s_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axis_aclk] [get_bd_pins axis_broadcaster_0/aclk] [get_bd_pins axis_broadcaster_1/aclk] [get_bd_pins axis_clock_converter_0/s_axis_aclk] [get_bd_pins axis_dwidth_converter_0/aclk] [get_bd_pins axis_readout_v2_0/aclk] [get_bd_pins axis_readout_v2_1/aclk] [get_bd_pins axis_register_slice_2/aclk] [get_bd_pins axis_register_slice_3/aclk] [get_bd_pins axis_switch_ddr4/aclk] [get_bd_pins axis_switch_mr/aclk] [get_bd_pins usp_rf_data_converter_0/m0_axis_aclk] + connect_bd_net -net clk_adc0_x2_locked [get_bd_pins clk_adc0_x2/locked] [get_bd_pins rst_adc0_x2/dcm_locked] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins axis_buffer_ddr_v1_0/aclk] [get_bd_pins rst_ddr4/slowest_sync_clk] [get_bd_pins axis_clock_converter_0/m_axis_aclk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm1_fpd_aclk] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk_sync_rst [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] [get_bd_pins rst_ddr4/ext_reset_in] + connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins rst_ddr4/peripheral_aresetn] [get_bd_pins axis_buffer_ddr_v1_0/aresetn] [get_bd_pins axis_clock_converter_0/m_axis_aresetn] [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins smartconnect_0/aresetn] + connect_bd_net -net rst_100_bus_struct_reset [get_bd_pins rst_100/bus_struct_reset] [get_bd_pins ddr4_0/sys_rst] + connect_bd_net -net rst_adc0_peripheral_aresetn [get_bd_pins rst_adc0/peripheral_aresetn] [get_bd_pins clk_adc0_x2/resetn] + connect_bd_net -net rst_adc0_x2_peripheral_aresetn [get_bd_pins rst_adc0_x2/peripheral_aresetn] [get_bd_pins mr_buffer_et_0/s00_axis_aresetn] [get_bd_pins axis_avg_buffer_0/s_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axis_aresetn] [get_bd_pins axis_broadcaster_0/aresetn] [get_bd_pins axis_broadcaster_1/aresetn] [get_bd_pins axis_clock_converter_0/s_axis_aresetn] [get_bd_pins axis_dwidth_converter_0/aresetn] [get_bd_pins axis_readout_v2_0/aresetn] [get_bd_pins axis_readout_v2_1/aresetn] [get_bd_pins axis_register_slice_2/aresetn] [get_bd_pins axis_register_slice_3/aresetn] [get_bd_pins axis_switch_ddr4/aresetn] [get_bd_pins axis_switch_mr/aresetn] [get_bd_pins usp_rf_data_converter_0/m0_axis_aresetn] + connect_bd_net -net rst_dac0_peripheral_aresetn [get_bd_pins rst_dac0/peripheral_aresetn] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins axis_set_reg_0/s_axis_aresetn] [get_bd_pins axis_signal_gen_v6_0/aresetn] [get_bd_pins axis_tproc64x32_x8_0/aresetn] [get_bd_pins axis_cc_avg_0/m_axis_aresetn] [get_bd_pins axis_cc_avg_1/m_axis_aresetn] [get_bd_pins axis_cc_sg_0/s_axis_aresetn] [get_bd_pins axis_cc_sg_0/m_axis_aresetn] [get_bd_pins axis_cc_sg_1/s_axis_aresetn] [get_bd_pins usp_rf_data_converter_0/s0_axis_aresetn] + connect_bd_net -net rst_dac1_peripheral_aresetn [get_bd_pins rst_dac1/peripheral_aresetn] [get_bd_pins axis_register_slice_1/aresetn] [get_bd_pins axis_signal_gen_v6_1/aresetn] [get_bd_pins axis_cc_sg_1/m_axis_aresetn] [get_bd_pins usp_rf_data_converter_0/s2_axis_aresetn] + connect_bd_net -net rst_ps8_0_99M_peripheral_aresetn [get_bd_pins rst_100/peripheral_aresetn] [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axis_buffer_ddr_v1_0/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_0/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_0/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_1/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_1/s_axi_aresetn] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aresetn] [get_bd_pins mr_buffer_et_0/m00_axis_aresetn] [get_bd_pins mr_buffer_et_0/s00_axi_aresetn] [get_bd_pins axis_avg_buffer_0/s_axi_aresetn] [get_bd_pins axis_avg_buffer_0/m_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axi_aresetn] [get_bd_pins axis_avg_buffer_1/m_axis_aresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_dma_avg/axi_resetn] [get_bd_pins axi_dma_buf/axi_resetn] [get_bd_pins axi_dma_gen/axi_resetn] [get_bd_pins axi_dma_mr/axi_resetn] [get_bd_pins axi_dma_tproc/axi_resetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins axis_cc_avg_0/s_axis_aresetn] [get_bd_pins axis_cc_avg_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/s_axi_aresetn] [get_bd_pins axis_readout_v2_1/s_axi_aresetn] [get_bd_pins axis_switch_avg/aresetn] [get_bd_pins axis_switch_avg/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_buf/aresetn] [get_bd_pins axis_switch_buf/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_ddr4/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_gen/aresetn] [get_bd_pins axis_switch_gen/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_mr/s_axi_ctrl_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/M02_ARESETN] [get_bd_pins ps8_0_axi_periph/M03_ARESETN] [get_bd_pins ps8_0_axi_periph/M04_ARESETN] [get_bd_pins ps8_0_axi_periph/M05_ARESETN] [get_bd_pins ps8_0_axi_periph/M06_ARESETN] [get_bd_pins ps8_0_axi_periph/M07_ARESETN] [get_bd_pins ps8_0_axi_periph/M08_ARESETN] [get_bd_pins ps8_0_axi_periph/M09_ARESETN] [get_bd_pins ps8_0_axi_periph/M10_ARESETN] [get_bd_pins ps8_0_axi_periph/M11_ARESETN] [get_bd_pins ps8_0_axi_periph/M12_ARESETN] [get_bd_pins ps8_0_axi_periph/M13_ARESETN] [get_bd_pins ps8_0_axi_periph/M14_ARESETN] [get_bd_pins ps8_0_axi_periph/M15_ARESETN] [get_bd_pins ps8_0_axi_periph/M16_ARESETN] [get_bd_pins ps8_0_axi_periph/M17_ARESETN] [get_bd_pins ps8_0_axi_periph/M18_ARESETN] [get_bd_pins ps8_0_axi_periph/M19_ARESETN] [get_bd_pins ps8_0_axi_periph/M20_ARESETN] [get_bd_pins ps8_0_axi_periph/M21_ARESETN] [get_bd_pins usp_rf_data_converter_0/s_axi_aresetn] + connect_bd_net -net usp_rf_data_converter_0_clk_adc0 [get_bd_pins usp_rf_data_converter_0/clk_adc0] [get_bd_pins rst_adc0/slowest_sync_clk] [get_bd_pins clk_adc0_x2/clk_in1] + connect_bd_net -net usp_rf_data_converter_0_clk_dac0 [get_bd_pins usp_rf_data_converter_0/clk_dac0] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_set_reg_0/s_axis_aclk] [get_bd_pins axis_signal_gen_v6_0/aclk] [get_bd_pins axis_tproc64x32_x8_0/aclk] [get_bd_pins rst_dac0/slowest_sync_clk] [get_bd_pins axi_bram_ctrl_0_bram/clkb] [get_bd_pins axis_cc_avg_0/m_axis_aclk] [get_bd_pins axis_cc_avg_1/m_axis_aclk] [get_bd_pins axis_cc_sg_0/s_axis_aclk] [get_bd_pins axis_cc_sg_0/m_axis_aclk] [get_bd_pins axis_cc_sg_1/s_axis_aclk] [get_bd_pins usp_rf_data_converter_0/s0_axis_aclk] + connect_bd_net -net usp_rf_data_converter_0_clk_dac2 [get_bd_pins usp_rf_data_converter_0/clk_dac2] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins axis_signal_gen_v6_1/aclk] [get_bd_pins rst_dac1/slowest_sync_clk] [get_bd_pins axis_cc_sg_1/m_axis_aclk] [get_bd_pins usp_rf_data_converter_0/s2_axis_aclk] + connect_bd_net -net vect2bits_16_0_dout0 [get_bd_pins vect2bits_16_0/dout0] [get_bd_ports PMOD0_0] + connect_bd_net -net vect2bits_16_0_dout1 [get_bd_pins vect2bits_16_0/dout1] [get_bd_ports PMOD0_1] + connect_bd_net -net vect2bits_16_0_dout2 [get_bd_pins vect2bits_16_0/dout2] [get_bd_ports PMOD0_2] + connect_bd_net -net vect2bits_16_0_dout3 [get_bd_pins vect2bits_16_0/dout3] [get_bd_ports PMOD0_3] + connect_bd_net -net vect2bits_16_0_dout4 [get_bd_pins vect2bits_16_0/dout4] [get_bd_ports PMOD0_4] + connect_bd_net -net vect2bits_16_0_dout5 [get_bd_pins vect2bits_16_0/dout5] [get_bd_ports PMOD0_5] + connect_bd_net -net vect2bits_16_0_dout6 [get_bd_pins vect2bits_16_0/dout6] [get_bd_ports PMOD0_6] + connect_bd_net -net vect2bits_16_0_dout7 [get_bd_pins vect2bits_16_0/dout7] [get_bd_ports PMOD0_7] + connect_bd_net -net vect2bits_16_0_dout12 [get_bd_pins vect2bits_16_0/dout12] [get_bd_pins mr_buffer_et_0/trigger] + connect_bd_net -net vect2bits_16_0_dout13 [get_bd_pins vect2bits_16_0/dout13] [get_bd_pins axis_buffer_ddr_v1_0/trigger] + connect_bd_net -net vect2bits_16_0_dout14 [get_bd_pins vect2bits_16_0/dout14] [get_bd_pins axis_avg_buffer_0/trigger] + connect_bd_net -net vect2bits_16_0_dout15 [get_bd_pins vect2bits_16_0/dout15] [get_bd_pins axis_avg_buffer_1/trigger] + connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins axi_intc_0/intr] + connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconstant_0/dout] [get_bd_pins axi_bram_ctrl_0_bram/dinb] + connect_bd_net -net xlconstant_1_dout [get_bd_pins xlconstant_1/dout] [get_bd_pins axi_bram_ctrl_0_bram/enb] + connect_bd_net -net xlconstant_2_dout [get_bd_pins xlconstant_2/dout] [get_bd_pins axi_bram_ctrl_0_bram/rstb] + connect_bd_net -net xlconstant_3_dout [get_bd_pins xlconstant_3/dout] [get_bd_pins axi_bram_ctrl_0_bram/web] + connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axis_buffer_ddr_v1_0/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_0/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_0/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_1/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_1/s_axi_aclk] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aclk] [get_bd_pins mr_buffer_et_0/m00_axis_aclk] [get_bd_pins mr_buffer_et_0/s00_axi_aclk] [get_bd_pins rst_100/slowest_sync_clk] [get_bd_pins axis_avg_buffer_0/s_axi_aclk] [get_bd_pins axis_avg_buffer_0/m_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axi_aclk] [get_bd_pins axis_avg_buffer_1/m_axis_aclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_dma_avg/s_axi_lite_aclk] [get_bd_pins axi_dma_avg/m_axi_s2mm_aclk] [get_bd_pins axi_dma_buf/s_axi_lite_aclk] [get_bd_pins axi_dma_buf/m_axi_s2mm_aclk] [get_bd_pins axi_dma_gen/s_axi_lite_aclk] [get_bd_pins axi_dma_gen/m_axi_mm2s_aclk] [get_bd_pins axi_dma_mr/s_axi_lite_aclk] [get_bd_pins axi_dma_mr/m_axi_s2mm_aclk] [get_bd_pins axi_dma_tproc/s_axi_lite_aclk] [get_bd_pins axi_dma_tproc/m_axi_mm2s_aclk] [get_bd_pins axi_dma_tproc/m_axi_s2mm_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins axis_cc_avg_0/s_axis_aclk] [get_bd_pins axis_cc_avg_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/s_axi_aclk] [get_bd_pins axis_readout_v2_1/s_axi_aclk] [get_bd_pins axis_switch_avg/aclk] [get_bd_pins axis_switch_avg/s_axi_ctrl_aclk] [get_bd_pins axis_switch_buf/aclk] [get_bd_pins axis_switch_buf/s_axi_ctrl_aclk] [get_bd_pins axis_switch_ddr4/s_axi_ctrl_aclk] [get_bd_pins axis_switch_gen/aclk] [get_bd_pins axis_switch_gen/s_axi_ctrl_aclk] [get_bd_pins axis_switch_mr/s_axi_ctrl_aclk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/M02_ACLK] [get_bd_pins ps8_0_axi_periph/M03_ACLK] [get_bd_pins ps8_0_axi_periph/M04_ACLK] [get_bd_pins ps8_0_axi_periph/M05_ACLK] [get_bd_pins ps8_0_axi_periph/M06_ACLK] [get_bd_pins ps8_0_axi_periph/M07_ACLK] [get_bd_pins ps8_0_axi_periph/M08_ACLK] [get_bd_pins ps8_0_axi_periph/M09_ACLK] [get_bd_pins ps8_0_axi_periph/M10_ACLK] [get_bd_pins ps8_0_axi_periph/M11_ACLK] [get_bd_pins ps8_0_axi_periph/M12_ACLK] [get_bd_pins ps8_0_axi_periph/M13_ACLK] [get_bd_pins ps8_0_axi_periph/M14_ACLK] [get_bd_pins ps8_0_axi_periph/M15_ACLK] [get_bd_pins ps8_0_axi_periph/M16_ACLK] [get_bd_pins ps8_0_axi_periph/M17_ACLK] [get_bd_pins ps8_0_axi_periph/M18_ACLK] [get_bd_pins ps8_0_axi_periph/M19_ACLK] [get_bd_pins ps8_0_axi_periph/M20_ACLK] [get_bd_pins ps8_0_axi_periph/M21_ACLK] [get_bd_pins usp_rf_data_converter_0/s_axi_aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihpc0_fpd_aclk] + connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] [get_bd_pins rst_100/ext_reset_in] [get_bd_pins rst_adc0/ext_reset_in] [get_bd_pins rst_adc0_x2/ext_reset_in] [get_bd_pins rst_dac0/ext_reset_in] [get_bd_pins rst_dac1/ext_reset_in] + + # Create address segments + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axis_buffer_ddr_v1_0/m_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_mr/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0x400140000 -range 0x00002000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x400200000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_avg/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0x400201000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_buf/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0x400202000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_gen/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0x400203000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_mr/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0x400204000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_tproc/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0x400205000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_intc_0/S_AXI/Reg] -force + assign_bd_address -offset 0x400206000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_0/s_axi/reg0] -force + assign_bd_address -offset 0x400207000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_1/s_axi/reg0] -force + assign_bd_address -offset 0x400208000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_buffer_ddr_v1_0/s_axi/reg0] -force + assign_bd_address -offset 0x400209000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_0/s_axi/reg0] -force + assign_bd_address -offset 0x40020A000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_1/s_axi/reg0] -force + assign_bd_address -offset 0x40020B000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_0/s_axi/reg0] -force + assign_bd_address -offset 0x40020C000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_1/s_axi/reg0] -force + assign_bd_address -offset 0x40020D000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_avg/S_AXI_CTRL/Reg] -force + assign_bd_address -offset 0x40020E000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_buf/S_AXI_CTRL/Reg] -force + assign_bd_address -offset 0x40020F000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_ddr4/S_AXI_CTRL/Reg] -force + assign_bd_address -offset 0x400210000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_gen/S_AXI_CTRL/Reg] -force + assign_bd_address -offset 0x400211000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_mr/S_AXI_CTRL/Reg] -force + assign_bd_address -offset 0x4400000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_tproc64x32_x8_0/s_axi/reg0] -force + assign_bd_address -offset 0x004800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x400212000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mr_buffer_et_0/s00_axi/reg0] -force + assign_bd_address -offset 0x400240000 -range 0x00040000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs usp_rf_data_converter_0/s_axi/Reg] -force + + # Exclude Address Segments + exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] + exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] + exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] + exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_mr/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_mr/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] + exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] + exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] + + # Perform GUI Layout + regenerate_bd_layout -layout_string { + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"0.474398", + "Default View_TopLeft":"-634,-70", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS +# -string -flagsOSRD +preplace port adc0_clk -pg 1 -lvl 0 -x -50 -y 2600 -defaultsOSRD +preplace port dac0_clk -pg 1 -lvl 0 -x -50 -y 2620 -defaultsOSRD +preplace port dac2_clk -pg 1 -lvl 0 -x -50 -y 2640 -defaultsOSRD +preplace port ddr4_pl -pg 1 -lvl 12 -x 5320 -y 2450 -defaultsOSRD +preplace port sys_clk_ddr4 -pg 1 -lvl 12 -x 5320 -y 2380 -defaultsOSRD -right +preplace port sysref_in -pg 1 -lvl 0 -x -50 -y 2700 -defaultsOSRD +preplace port vin0_01 -pg 1 -lvl 0 -x -50 -y 2660 -defaultsOSRD +preplace port vin0_23 -pg 1 -lvl 0 -x -50 -y 2680 -defaultsOSRD +preplace port vout00 -pg 1 -lvl 12 -x 5320 -y 2670 -defaultsOSRD +preplace port vout20 -pg 1 -lvl 12 -x 5320 -y 2690 -defaultsOSRD +preplace port port-id_PMOD0_0 -pg 1 -lvl 12 -x 5320 -y 2890 -defaultsOSRD +preplace port port-id_PMOD0_1 -pg 1 -lvl 12 -x 5320 -y 2910 -defaultsOSRD +preplace port port-id_PMOD0_2 -pg 1 -lvl 12 -x 5320 -y 2930 -defaultsOSRD +preplace port port-id_PMOD0_3 -pg 1 -lvl 12 -x 5320 -y 2950 -defaultsOSRD +preplace port port-id_PMOD0_4 -pg 1 -lvl 12 -x 5320 -y 2970 -defaultsOSRD +preplace port port-id_PMOD0_5 -pg 1 -lvl 12 -x 5320 -y 2990 -defaultsOSRD +preplace port port-id_PMOD0_6 -pg 1 -lvl 12 -x 5320 -y 3010 -defaultsOSRD +preplace port port-id_PMOD0_7 -pg 1 -lvl 12 -x 5320 -y 3030 -defaultsOSRD +preplace port port-id_PMOD1_0 -pg 1 -lvl 0 -x -50 -y 1880 -defaultsOSRD +preplace inst axi_intc_0 -pg 1 -lvl 5 -x 1720 -y 130 -defaultsOSRD +preplace inst axis_buffer_ddr_v1_0 -pg 1 -lvl 9 -x 4220 -y 2470 -defaultsOSRD +preplace inst axis_register_slice_0 -pg 1 -lvl 5 -x 1720 -y 2120 -defaultsOSRD +preplace inst axis_register_slice_1 -pg 1 -lvl 5 -x 1720 -y 2410 -defaultsOSRD +preplace inst axis_set_reg_0 -pg 1 -lvl 6 -x 2400 -y 3040 -defaultsOSRD +preplace inst axis_signal_gen_v6_0 -pg 1 -lvl 4 -x 1400 -y 2100 -defaultsOSRD +preplace inst axis_signal_gen_v6_1 -pg 1 -lvl 4 -x 1400 -y 2390 -defaultsOSRD -resize 220 236 +preplace inst axis_tproc64x32_x8_0 -pg 1 -lvl 2 -x 570 -y 1880 -defaultsOSRD +preplace inst mr_buffer_et_0 -pg 1 -lvl 9 -x 4220 -y 1940 -defaultsOSRD +preplace inst rst_100 -pg 1 -lvl 6 -x 2400 -y 300 -defaultsOSRD +preplace inst rst_adc0 -pg 1 -lvl 6 -x 2400 -y 490 -defaultsOSRD +preplace inst rst_adc0_x2 -pg 1 -lvl 6 -x 2400 -y 840 -defaultsOSRD -resize 320 156 +preplace inst rst_dac0 -pg 1 -lvl 6 -x 2400 -y 1060 -defaultsOSRD -resize 320 156 +preplace inst rst_dac1 -pg 1 -lvl 6 -x 2400 -y 1240 -defaultsOSRD -resize 320 156 +preplace inst rst_ddr4 -pg 1 -lvl 6 -x 2400 -y 1770 -defaultsOSRD +preplace inst vect2bits_16_0 -pg 1 -lvl 7 -x 3060 -y 3040 -defaultsOSRD +preplace inst xlconcat_0 -pg 1 -lvl 4 -x 1400 -y 160 -defaultsOSRD +preplace inst axis_avg_buffer_0 -pg 1 -lvl 8 -x 3700 -y 1300 -defaultsOSRD +preplace inst axis_avg_buffer_1 -pg 1 -lvl 8 -x 3700 -y 1560 -defaultsOSRD -resize 220 236 +preplace inst axi_bram_ctrl_0 -pg 1 -lvl 1 -x 140 -y 2010 -defaultsOSRD +preplace inst axi_bram_ctrl_0_bram -pg 1 -lvl 2 -x 570 -y 2400 -defaultsOSRD +preplace inst axi_dma_avg -pg 1 -lvl 10 -x 4640 -y 880 -defaultsOSRD +preplace inst axi_dma_buf -pg 1 -lvl 10 -x 4640 -y 1100 -defaultsOSRD -resize 320 156 +preplace inst axi_dma_gen -pg 1 -lvl 2 -x 570 -y 1290 -defaultsOSRD +preplace inst axi_dma_mr -pg 1 -lvl 10 -x 4640 -y 1970 -defaultsOSRD -resize 320 156 +preplace inst axi_dma_tproc -pg 1 -lvl 2 -x 570 -y 1520 -defaultsOSRD +preplace inst axi_smc -pg 1 -lvl 5 -x 1720 -y 1040 -defaultsOSRD +preplace inst axis_broadcaster_0 -pg 1 -lvl 7 -x 3060 -y 1850 -defaultsOSRD +preplace inst axis_broadcaster_1 -pg 1 -lvl 7 -x 3060 -y 2190 -defaultsOSRD +preplace inst axis_cc_avg_0 -pg 1 -lvl 9 -x 4220 -y 1360 -defaultsOSRD +preplace inst axis_cc_avg_1 -pg 1 -lvl 9 -x 4220 -y 1620 -defaultsOSRD -resize 220 156 +preplace inst axis_cc_sg_0 -pg 1 -lvl 3 -x 1000 -y 2040 -defaultsOSRD +preplace inst axis_cc_sg_1 -pg 1 -lvl 3 -x 1000 -y 2330 -defaultsOSRD -resize 220 156 +preplace inst axis_clock_converter_0 -pg 1 -lvl 9 -x 4220 -y 2230 -defaultsOSRD +preplace inst axis_dwidth_converter_0 -pg 1 -lvl 8 -x 3700 -y 2340 -defaultsOSRD +preplace inst axis_readout_v2_0 -pg 1 -lvl 7 -x 3060 -y 1680 -defaultsOSRD +preplace inst axis_readout_v2_1 -pg 1 -lvl 7 -x 3060 -y 2020 -defaultsOSRD -resize 200 176 +preplace inst axis_register_slice_2 -pg 1 -lvl 6 -x 2400 -y 2070 -defaultsOSRD -resize 180 116 +preplace inst axis_register_slice_3 -pg 1 -lvl 6 -x 2400 -y 2220 -defaultsOSRD -resize 180 116 +preplace inst axis_switch_avg -pg 1 -lvl 9 -x 4220 -y 860 -defaultsOSRD -resize 240 196 +preplace inst axis_switch_buf -pg 1 -lvl 9 -x 4220 -y 1080 -defaultsOSRD -resize 240 196 +preplace inst axis_switch_ddr4 -pg 1 -lvl 8 -x 3700 -y 2080 -defaultsOSRD +preplace inst axis_switch_gen -pg 1 -lvl 3 -x 1000 -y 1330 -defaultsOSRD +preplace inst axis_switch_mr -pg 1 -lvl 8 -x 3700 -y 1860 -defaultsOSRD +preplace inst clk_adc0_x2 -pg 1 -lvl 6 -x 2400 -y 690 -defaultsOSRD +preplace inst ddr4_0 -pg 1 -lvl 11 -x 5080 -y 2500 -defaultsOSRD +preplace inst ps8_0_axi_periph -pg 1 -lvl 7 -x 3060 -y 560 -defaultsOSRD +preplace inst smartconnect_0 -pg 1 -lvl 10 -x 4640 -y 2490 -defaultsOSRD +preplace inst usp_rf_data_converter_0 -pg 1 -lvl 6 -x 2400 -y 2700 -defaultsOSRD +preplace inst xlconstant_0 -pg 1 -lvl 1 -x 140 -y 2130 -defaultsOSRD +preplace inst xlconstant_1 -pg 1 -lvl 1 -x 140 -y 2240 -defaultsOSRD -resize 140 88 +preplace inst xlconstant_2 -pg 1 -lvl 1 -x 140 -y 2350 -defaultsOSRD -resize 140 88 +preplace inst xlconstant_3 -pg 1 -lvl 1 -x 140 -y 2480 -defaultsOSRD -resize 140 88 +preplace inst zynq_ultra_ps_e_0 -pg 1 -lvl 6 -x 2400 -y 110 -defaultsOSRD +preplace netloc PMOD1_0_1 1 0 2 NJ 1880 330 +preplace netloc axi_bram_ctrl_0_bram_doutb 1 1 1 360 2030n +preplace netloc axi_dma_avg_s2mm_introut 1 3 8 1200 -60 NJ -60 NJ -60 NJ -60 NJ -60 NJ -60 NJ -60 4830 +preplace netloc axi_dma_buf_s2mm_introut 1 3 8 1270 -50 NJ -50 NJ -50 NJ -50 NJ -50 NJ -50 NJ -50 4840 +preplace netloc axi_dma_gen_mm2s_introut 1 2 2 750 110 NJ +preplace netloc axi_dma_readout_s2mm_introut 1 3 8 1260 2250 NJ 2250 1870J 2300 NJ 2300 3540J 2250 3950J 2330 NJ 2330 4820 +preplace netloc axi_dma_tproc_mm2s_introut 1 2 2 770 130 NJ +preplace netloc axi_dma_tproc_s2mm_introut 1 2 2 790 150 NJ +preplace netloc axi_intc_0_irq 1 5 1 2040 130n +preplace netloc axis_set_reg_0_dout 1 6 1 N 3040 +preplace netloc axis_tproc64x32_x8_0_pmem_addr 1 1 2 380 2100 750 +preplace netloc clk_adc0_x2_clk_out1 1 5 4 2040 610 2830 1370 3520 2230 4060 +preplace netloc clk_adc0_x2_locked 1 5 2 2090 620 2730 +preplace netloc ddr4_0_c0_ddr4_ui_clk 1 5 7 2050 1970 2750 2290 3550J 2260 3940J 2600 4400J 2600 4870 2610 5270 +preplace netloc ddr4_0_c0_ddr4_ui_clk_sync_rst 1 5 7 2070 2470 NJ 2470 NJ 2470 3850J 2620 NJ 2620 NJ 2620 5260 +preplace netloc proc_sys_reset_0_peripheral_aresetn 1 6 5 2760 2280 3510 2240 4070 2590 4460 2580 4850 +preplace netloc rst_100_bus_struct_reset 1 6 5 2740J -40 NJ -40 NJ -40 NJ -40 4860 +preplace netloc rst_adc0_peripheral_aresetn 1 5 2 2080 590 2730 +preplace netloc rst_adc0_x2_peripheral_aresetn 1 5 4 2050 1980 2770 1340 3450 1730 3940 +preplace netloc rst_dac0_peripheral_aresetn 1 1 8 390 2090 810 2140 1190 1950 1580J 1950 1990J 1370 2760 1160 3370 1150 3990 +preplace netloc rst_dac1_peripheral_aresetn 1 2 5 850 2470 1190 2530 1580J 2490 2030J 2480 2720 +preplace netloc rst_ps8_0_99M_peripheral_aresetn 1 0 10 -20 1920 340 1640 860 1660 1210 1660 1540 1660 2010 1660 2860 1150 3360 1110 4040J 1230 4460 +preplace netloc usp_rf_data_converter_0_clk_adc0 1 5 2 2070 600 2740 +preplace netloc usp_rf_data_converter_0_clk_dac0 1 1 8 370 2110 830 2150 1240 1960 1530 1960 1980 1560 2780 1560 3400 1710 4000 +preplace netloc usp_rf_data_converter_0_clk_dac2 1 2 5 860 2450 1270 2540 1530 2500 2020 2920 2720 +preplace netloc vect2bits_16_0_dout0 1 7 5 N 2890 NJ 2890 NJ 2890 NJ 2890 N +preplace netloc vect2bits_16_0_dout1 1 7 5 N 2910 NJ 2910 NJ 2910 NJ 2910 N +preplace netloc vect2bits_16_0_dout2 1 7 5 N 2930 NJ 2930 NJ 2930 NJ 2930 N +preplace netloc vect2bits_16_0_dout3 1 7 5 N 2950 NJ 2950 NJ 2950 NJ 2950 N +preplace netloc vect2bits_16_0_dout4 1 7 5 N 2970 NJ 2970 NJ 2970 NJ 2970 N +preplace netloc vect2bits_16_0_dout5 1 7 5 N 2990 NJ 2990 NJ 2990 NJ 2990 N +preplace netloc vect2bits_16_0_dout6 1 7 5 N 3010 NJ 3010 NJ 3010 NJ 3010 N +preplace netloc vect2bits_16_0_dout7 1 7 5 N 3030 NJ 3030 NJ 3030 NJ 3030 N +preplace netloc vect2bits_16_0_dout12 1 7 2 3490 1740 3850J +preplace netloc vect2bits_16_0_dout13 1 7 2 3560 2480 4060J +preplace netloc vect2bits_16_0_dout14 1 7 1 3470 1300n +preplace netloc vect2bits_16_0_dout15 1 7 1 3530 1560n +preplace netloc xlconcat_0_dout 1 4 1 N 160 +preplace netloc xlconstant_0_dout 1 1 1 300 2130n +preplace netloc xlconstant_1_dout 1 1 1 290 2240n +preplace netloc xlconstant_2_dout 1 1 1 280 2350n +preplace netloc xlconstant_3_dout 1 1 1 N 2480 +preplace netloc zynq_ultra_ps_e_0_pl_clk0 1 0 10 0 1930 320 1380 850 1450 1230 1090 1530 40 2000 1400 2870 1170 3500 1160 4030J 1240 4450 +preplace netloc zynq_ultra_ps_e_0_pl_resetn0 1 5 2 2060 0 2730 +preplace netloc adc0_clk_1 1 0 6 N 2600 N 2600 N 2600 N 2600 N 2600 N +preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 1 1 310 2010n +preplace netloc axi_dma_avg_M_AXI_S2MM 1 4 7 1570 1450 N 1450 N 1450 3420 1700 4010 1520 N 1520 4820 +preplace netloc axi_dma_buf_M_AXI_S2MM 1 4 7 1550J 1460 1860 1550 NJ 1550 3410J 1720 NJ 1720 NJ 1720 4830 +preplace netloc axi_dma_gen_M_AXIS_MM2S 1 2 1 N 1280 +preplace netloc axi_dma_gen_M_AXI_MM2S 1 2 3 760 1030 N 1030 N +preplace netloc axi_dma_readout_M_AXI_S2MM 1 4 7 1580J 1170 1990 1340 2730J 1130 NJ 1130 4060J 1200 NJ 1200 4850 +preplace netloc axi_dma_tproc_M_AXIS_MM2S 1 1 2 380 1650 750 +preplace netloc axi_dma_tproc_M_AXI_MM2S 1 2 3 780 1050 NJ 1050 N +preplace netloc axi_dma_tproc_M_AXI_S2MM 1 2 3 800 1070 NJ 1070 N +preplace netloc axi_smc_M00_AXI 1 5 1 1860 60n +preplace netloc axis_avg_buffer_0_m0_axis 1 8 1 3840 800n +preplace netloc axis_avg_buffer_0_m1_axis 1 8 1 3880 1020n +preplace netloc axis_avg_buffer_0_m2_axis 1 8 1 N 1320 +preplace netloc axis_avg_buffer_1_m0_axis 1 8 1 3870 820n +preplace netloc axis_avg_buffer_1_m1_axis 1 8 1 3980 1040n +preplace netloc axis_avg_buffer_1_m2_axis 1 8 1 N 1580 +preplace netloc axis_broadcaster_0_M00_AXIS 1 7 1 3390 1220n +preplace netloc axis_broadcaster_0_M01_AXIS 1 7 1 3230 1860n +preplace netloc axis_broadcaster_1_M00_AXIS 1 7 1 3430 1480n +preplace netloc axis_broadcaster_1_M01_AXIS 1 7 1 3480 2040n +preplace netloc axis_buffer_ddr_v1_0_m_axi 1 9 1 N 2480 +preplace netloc axis_cc_avg_0_M_AXIS 1 1 9 350 890 N 890 N 890 NJ 890 2030 940 2840J 1140 NJ 1140 4000J 1210 4360 +preplace netloc axis_cc_avg_1_M_AXIS 1 1 9 360 900 N 900 N 900 NJ 900 2020 950 2850J 1100 3450J 1120 4010J 1220 4370 +preplace netloc axis_cc_sg_0_M_AXIS 1 3 1 N 2040 +preplace netloc axis_cc_sg_1_M_AXIS 1 3 1 N 2330 +preplace netloc axis_clock_converter_0_M_AXIS 1 8 2 4080 2340 4360 +preplace netloc axis_dwidth_converter_0_M_AXIS 1 8 1 4050 2190n +preplace netloc axis_readout_v2_0_m0_axis 1 7 1 3270 1670n +preplace netloc axis_readout_v2_0_m1_axis 1 6 2 2890 1570 3220 +preplace netloc axis_readout_v2_1_m0_axis 1 7 1 3460 1820n +preplace netloc axis_readout_v2_1_m1_axis 1 6 2 2900 2270 3220 +preplace netloc axis_register_slice_2_M_AXIS 1 6 1 2730 1630n +preplace netloc axis_register_slice_3_M_AXIS 1 6 1 2840 1970n +preplace netloc axis_register_slice_4_m_axis 1 5 1 1870J 2410n +preplace netloc axis_register_slice_6_m_axis 1 5 1 1880 2120n +preplace netloc axis_signal_gen_v6_0_m_axis 1 4 1 N 2100 +preplace netloc axis_signal_gen_v6_1_m_axis 1 4 1 N 2390 +preplace netloc axis_switch_0_M00_AXIS 1 8 1 N 1860 +preplace netloc axis_switch_avg_M00_AXIS 1 9 1 N 860 +preplace netloc axis_switch_buf_M00_AXIS 1 9 1 N 1080 +preplace netloc axis_switch_ddr4_M00_AXIS 1 7 2 3560 2200 3840 +preplace netloc axis_switch_gen_M00_AXIS 1 3 1 1220 1320n +preplace netloc axis_switch_gen_M01_AXIS 1 3 1 1200 1340n +preplace netloc axis_tproc64x32_x8_0_m0_axis 1 1 2 390 1670 750 +preplace netloc axis_tproc64x32_x8_0_m1_axis 1 2 1 810 1810n +preplace netloc axis_tproc64x32_x8_0_m2_axis 1 2 1 770 1830n +preplace netloc axis_tproc64x32_x8_0_m8_axis 1 2 4 830J 1940 NJ 1940 NJ 1940 1860 +preplace netloc dac0_clk_1 1 0 6 N 2620 N 2620 N 2620 N 2620 N 2620 N +preplace netloc dac2_clk_1 1 0 6 N 2640 N 2640 N 2640 N 2640 N 2640 N +preplace netloc ddr4_0_C0_DDR4 1 11 1 N 2450 +preplace netloc mr_buffer_et_0_m00_axis 1 9 1 4360 1940n +preplace netloc ps8_0_axi_periph_M00_AXI 1 7 3 3560 710 3850 720 4420J +preplace netloc ps8_0_axi_periph_M01_AXI 1 7 3 3550 730 N 730 4400J +preplace netloc ps8_0_axi_periph_M02_AXI 1 7 3 3540 740 N 740 4390J +preplace netloc ps8_0_axi_periph_M03_AXI 1 7 1 3510 410n +preplace netloc ps8_0_axi_periph_M04_AXI 1 6 2 2900 20 3220J +preplace netloc ps8_0_axi_periph_M05_AXI 1 6 2 2880 10 3240J +preplace netloc ps8_0_axi_periph_M06_AXI 1 7 2 3530 820 3860 +preplace netloc ps8_0_axi_periph_M07_AXI 1 7 2 3520 840 3850 +preplace netloc ps8_0_axi_periph_M08_AXI 1 7 1 3440 510n +preplace netloc ps8_0_axi_periph_M09_AXI 1 1 7 370 910 N 910 N 910 NJ 910 2010 960 2780J 1110 3220J +preplace netloc ps8_0_axi_periph_M10_AXI 1 7 2 3500 900 4020 +preplace netloc ps8_0_axi_periph_M11_AXI 1 5 3 2060 1380 NJ 1380 3260J +preplace netloc ps8_0_axi_periph_M12_AXI 1 7 1 3470 590n +preplace netloc ps8_0_axi_periph_M13_AXI 1 3 5 1270 1390 NJ 1390 NJ 1390 NJ 1390 3250 +preplace netloc ps8_0_axi_periph_M14_AXI 1 3 5 1250 1350 NJ 1350 NJ 1350 NJ 1350 3240 +preplace netloc ps8_0_axi_periph_M15_AXI 1 1 7 390 -30 N -30 N -30 NJ -30 NJ -30 NJ -30 3230 +preplace netloc ps8_0_axi_periph_M16_AXI 1 2 6 860 -20 N -20 N -20 NJ -20 NJ -20 3270 +preplace netloc ps8_0_axi_periph_M17_AXI 1 1 7 380 -10 NJ -10 NJ -10 NJ -10 NJ -10 2790J 0 3300 +preplace netloc ps8_0_axi_periph_M18_AXI 1 0 8 -10 1400 NJ 1400 810J 1440 NJ 1440 NJ 1440 NJ 1440 NJ 1440 3270 +preplace netloc ps8_0_axi_periph_M19_AXI 1 4 4 1560 1360 N 1360 N 1360 3230 +preplace netloc ps8_0_axi_periph_M20_AXI 1 7 2 3490 1100 3970 +preplace netloc ps8_0_axi_periph_M21_AXI 1 7 1 3380 770n +preplace netloc smartconnect_0_M00_AXI 1 10 1 N 2490 +preplace netloc sys_clk_ddr4_1 1 10 2 4900 2380 NJ +preplace netloc sysref_in_1 1 0 6 NJ 2700 NJ 2700 NJ 2700 NJ 2700 NJ 2700 N +preplace netloc usp_rf_data_converter_0_m00_axis 1 5 2 2090 1990 2710 +preplace netloc usp_rf_data_converter_0_m02_axis 1 5 2 2080 2310 2730 +preplace netloc usp_rf_data_converter_0_vout00 1 6 6 N 2670 N 2670 N 2670 N 2670 N 2670 N +preplace netloc usp_rf_data_converter_0_vout20 1 6 6 N 2690 N 2690 N 2690 N 2690 N 2690 N +preplace netloc vin0_01_1 1 0 6 N 2660 N 2660 N 2660 N 2660 N 2660 N +preplace netloc vin0_23_1 1 0 6 N 2680 N 2680 N 2680 N 2680 N 2680 N +preplace netloc zynq_ultra_ps_e_0_M_AXI_HPM0_FPD 1 6 1 2830J 70n +preplace netloc zynq_ultra_ps_e_0_M_AXI_HPM1_FPD 1 6 4 2820 -10 N -10 N -10 4380 +levelinfo -pg 1 -50 140 570 1000 1400 1720 2400 3060 3700 4220 4640 5080 5320 +pagesize -pg 1 -db -bbox -sgen -170 -100 5460 3560 +" +} + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/firmware/RFSoc_4x2/RF4x2_src/ios.xdc b/firmware/RFSoc_4x2/RF4x2_src/ios.xdc new file mode 100644 index 0000000..946c504 --- /dev/null +++ b/firmware/RFSoc_4x2/RF4x2_src/ios.xdc @@ -0,0 +1,162 @@ +set_property PACKAGE_PIN AF16 [get_ports PMOD0_0] +set_property PACKAGE_PIN AG17 [get_ports PMOD0_1] +set_property PACKAGE_PIN AJ16 [get_ports PMOD0_2] +set_property PACKAGE_PIN AK17 [get_ports PMOD0_3] +set_property PACKAGE_PIN AF15 [get_ports PMOD0_4] +set_property PACKAGE_PIN AF17 [get_ports PMOD0_5] +set_property PACKAGE_PIN AH17 [get_ports PMOD0_6] +set_property PACKAGE_PIN AK16 [get_ports PMOD0_7] +set_property IOSTANDARD LVCMOS18 [get_ports PMOD0*] + +set_property PACKAGE_PIN AW13 [get_ports PMOD1_0] +#set_property PACKAGE_PIN AR13 [ get_ports "PMOD1_1" ] +#set_property PACKAGE_PIN AU13 [ get_ports "PMOD1_2" ] +#set_property PACKAGE_PIN AV13 [ get_ports "PMOD1_3" ] +#set_property PACKAGE_PIN AU15 [ get_ports "PMOD1_4" ] +#set_property PACKAGE_PIN AP14 [ get_ports "PMOD1_5" ] +#set_property PACKAGE_PIN AT15 [ get_ports "PMOD1_6" ] +#set_property PACKAGE_PIN AU14 [ get_ports "PMOD1_7" ] +set_property IOSTANDARD LVCMOS18 [get_ports PMOD1*] + +#set_property PACKAGE_PIN AW16 [ get_ports "PMOD01_0" ] +#set_property PACKAGE_PIN AW15 [ get_ports "PMOD01_1" ] +#set_property PACKAGE_PIN AW14 [ get_ports "PMOD01_2" ] +#set_property PACKAGE_PIN AR16 [ get_ports "PMOD01_3" ] +#set_property PACKAGE_PIN AV16 [ get_ports "PMOD01_4" ] +#set_property PACKAGE_PIN AT16 [ get_ports "PMOD01_5" ] +#set_property IOSTANDARD LVCMOS18 [ get_ports "PMOD01*"] + +## PL ddr4 from https://github.com/Xilinx/RFSoC-MTS/blob/main/boards/RFSoC4x2/build_mts/mts.xdc +set_property PACKAGE_PIN G13 [get_ports sys_clk_ddr4_clk_p] +set_property PACKAGE_PIN B13 [get_ports {ddr4_pl_adr[0]}] +set_property PACKAGE_PIN G6 [get_ports {ddr4_pl_adr[1]}] +set_property PACKAGE_PIN A14 [get_ports {ddr4_pl_adr[2]}] +set_property PACKAGE_PIN F10 [get_ports {ddr4_pl_adr[3]}] +set_property PACKAGE_PIN D14 [get_ports {ddr4_pl_adr[4]}] +set_property PACKAGE_PIN F11 [get_ports {ddr4_pl_adr[5]}] +set_property PACKAGE_PIN J7 [get_ports {ddr4_pl_adr[6]}] +set_property PACKAGE_PIN H13 [get_ports {ddr4_pl_adr[7]}] +set_property PACKAGE_PIN A11 [get_ports {ddr4_pl_adr[8]}] +set_property PACKAGE_PIN H6 [get_ports {ddr4_pl_adr[9]}] +set_property PACKAGE_PIN C15 [get_ports {ddr4_pl_adr[10]}] +set_property PACKAGE_PIN G7 [get_ports {ddr4_pl_adr[11]}] +set_property PACKAGE_PIN D13 [get_ports {ddr4_pl_adr[12]}] +set_property PACKAGE_PIN H11 [get_ports {ddr4_pl_adr[13]}] +set_property PACKAGE_PIN K13 [get_ports {ddr4_pl_adr[14]}] +set_property PACKAGE_PIN F14 [get_ports {ddr4_pl_adr[15]}] +set_property PACKAGE_PIN E13 [get_ports {ddr4_pl_adr[16]}] +set_property PACKAGE_PIN B14 [get_ports ddr4_pl_act_n] +set_property PACKAGE_PIN A12 [get_ports {ddr4_pl_ba[0]}] +set_property PACKAGE_PIN H10 [get_ports {ddr4_pl_ba[1]}] +set_property PACKAGE_PIN H12 [get_ports {ddr4_pl_bg[0]}] +set_property PACKAGE_PIN J11 [get_ports {ddr4_pl_ck_t[0]}] +set_property PACKAGE_PIN J10 [get_ports {ddr4_pl_ck_c[0]}] +set_property PACKAGE_PIN F12 [get_ports {ddr4_pl_cke[0]}] +set_property PACKAGE_PIN E11 [get_ports {ddr4_pl_cs_n[0]}] +set_property PACKAGE_PIN J15 [get_ports {ddr4_pl_dm_n[0]}] +set_property PACKAGE_PIN N14 [get_ports {ddr4_pl_dm_n[1]}] +set_property PACKAGE_PIN D18 [get_ports {ddr4_pl_dm_n[2]}] +set_property PACKAGE_PIN G17 [get_ports {ddr4_pl_dm_n[3]}] +set_property PACKAGE_PIN F21 [get_ports {ddr4_pl_dm_n[4]}] +set_property PACKAGE_PIN J23 [get_ports {ddr4_pl_dm_n[5]}] +set_property PACKAGE_PIN C23 [get_ports {ddr4_pl_dm_n[6]}] +set_property PACKAGE_PIN N20 [get_ports {ddr4_pl_dm_n[7]}] +set_property PACKAGE_PIN K17 [get_ports {ddr4_pl_dq[0]}] +set_property PACKAGE_PIN J16 [get_ports {ddr4_pl_dq[1]}] +set_property PACKAGE_PIN H17 [get_ports {ddr4_pl_dq[2]}] +set_property PACKAGE_PIN H16 [get_ports {ddr4_pl_dq[3]}] +set_property PACKAGE_PIN J18 [get_ports {ddr4_pl_dq[4]}] +set_property PACKAGE_PIN K16 [get_ports {ddr4_pl_dq[5]}] +set_property PACKAGE_PIN J19 [get_ports {ddr4_pl_dq[6]}] +set_property PACKAGE_PIN L17 [get_ports {ddr4_pl_dq[7]}] +set_property PACKAGE_PIN N17 [get_ports {ddr4_pl_dq[8]}] +set_property PACKAGE_PIN N13 [get_ports {ddr4_pl_dq[9]}] +set_property PACKAGE_PIN N15 [get_ports {ddr4_pl_dq[10]}] +set_property PACKAGE_PIN L12 [get_ports {ddr4_pl_dq[11]}] +set_property PACKAGE_PIN M17 [get_ports {ddr4_pl_dq[12]}] +set_property PACKAGE_PIN M13 [get_ports {ddr4_pl_dq[13]}] +set_property PACKAGE_PIN M15 [get_ports {ddr4_pl_dq[14]}] +set_property PACKAGE_PIN M12 [get_ports {ddr4_pl_dq[15]}] +set_property PACKAGE_PIN D16 [get_ports {ddr4_pl_dq[16]}] +set_property PACKAGE_PIN A17 [get_ports {ddr4_pl_dq[17]}] +set_property PACKAGE_PIN C17 [get_ports {ddr4_pl_dq[18]}] +set_property PACKAGE_PIN A19 [get_ports {ddr4_pl_dq[19]}] +set_property PACKAGE_PIN D15 [get_ports {ddr4_pl_dq[20]}] +set_property PACKAGE_PIN C16 [get_ports {ddr4_pl_dq[21]}] +set_property PACKAGE_PIN B19 [get_ports {ddr4_pl_dq[22]}] +set_property PACKAGE_PIN A16 [get_ports {ddr4_pl_dq[23]}] +set_property PACKAGE_PIN G18 [get_ports {ddr4_pl_dq[24]}] +set_property PACKAGE_PIN E16 [get_ports {ddr4_pl_dq[25]}] +set_property PACKAGE_PIN F16 [get_ports {ddr4_pl_dq[26]}] +set_property PACKAGE_PIN G15 [get_ports {ddr4_pl_dq[27]}] +set_property PACKAGE_PIN H18 [get_ports {ddr4_pl_dq[28]}] +set_property PACKAGE_PIN E17 [get_ports {ddr4_pl_dq[29]}] +set_property PACKAGE_PIN E18 [get_ports {ddr4_pl_dq[30]}] +set_property PACKAGE_PIN F15 [get_ports {ddr4_pl_dq[31]}] +set_property PACKAGE_PIN E24 [get_ports {ddr4_pl_dq[32]}] +set_property PACKAGE_PIN D21 [get_ports {ddr4_pl_dq[33]}] +set_property PACKAGE_PIN E22 [get_ports {ddr4_pl_dq[34]}] +set_property PACKAGE_PIN E21 [get_ports {ddr4_pl_dq[35]}] +set_property PACKAGE_PIN E23 [get_ports {ddr4_pl_dq[36]}] +set_property PACKAGE_PIN F20 [get_ports {ddr4_pl_dq[37]}] +set_property PACKAGE_PIN F24 [get_ports {ddr4_pl_dq[38]}] +set_property PACKAGE_PIN G20 [get_ports {ddr4_pl_dq[39]}] +set_property PACKAGE_PIN J21 [get_ports {ddr4_pl_dq[40]}] +set_property PACKAGE_PIN G22 [get_ports {ddr4_pl_dq[41]}] +set_property PACKAGE_PIN K24 [get_ports {ddr4_pl_dq[42]}] +set_property PACKAGE_PIN G23 [get_ports {ddr4_pl_dq[43]}] +set_property PACKAGE_PIN L24 [get_ports {ddr4_pl_dq[44]}] +set_property PACKAGE_PIN H22 [get_ports {ddr4_pl_dq[45]}] +set_property PACKAGE_PIN H23 [get_ports {ddr4_pl_dq[46]}] +set_property PACKAGE_PIN H21 [get_ports {ddr4_pl_dq[47]}] +set_property PACKAGE_PIN C21 [get_ports {ddr4_pl_dq[48]}] +set_property PACKAGE_PIN A24 [get_ports {ddr4_pl_dq[49]}] +set_property PACKAGE_PIN B24 [get_ports {ddr4_pl_dq[50]}] +set_property PACKAGE_PIN A20 [get_ports {ddr4_pl_dq[51]}] +set_property PACKAGE_PIN C22 [get_ports {ddr4_pl_dq[52]}] +set_property PACKAGE_PIN A21 [get_ports {ddr4_pl_dq[53]}] +set_property PACKAGE_PIN C20 [get_ports {ddr4_pl_dq[54]}] +set_property PACKAGE_PIN B20 [get_ports {ddr4_pl_dq[55]}] +set_property PACKAGE_PIN M20 [get_ports {ddr4_pl_dq[56]}] +set_property PACKAGE_PIN L20 [get_ports {ddr4_pl_dq[57]}] +set_property PACKAGE_PIN L22 [get_ports {ddr4_pl_dq[58]}] +set_property PACKAGE_PIN L21 [get_ports {ddr4_pl_dq[59]}] +set_property PACKAGE_PIN N19 [get_ports {ddr4_pl_dq[60]}] +set_property PACKAGE_PIN M19 [get_ports {ddr4_pl_dq[61]}] +set_property PACKAGE_PIN L23 [get_ports {ddr4_pl_dq[62]}] +set_property PACKAGE_PIN L19 [get_ports {ddr4_pl_dq[63]}] +set_property PACKAGE_PIN K19 [get_ports {ddr4_pl_dqs_t[0]}] +set_property PACKAGE_PIN K18 [get_ports {ddr4_pl_dqs_c[0]}] +set_property PACKAGE_PIN L15 [get_ports {ddr4_pl_dqs_t[1]}] +set_property PACKAGE_PIN L14 [get_ports {ddr4_pl_dqs_c[1]}] +set_property PACKAGE_PIN B18 [get_ports {ddr4_pl_dqs_t[2]}] +set_property PACKAGE_PIN B17 [get_ports {ddr4_pl_dqs_c[2]}] +set_property PACKAGE_PIN G19 [get_ports {ddr4_pl_dqs_t[3]}] +set_property PACKAGE_PIN F19 [get_ports {ddr4_pl_dqs_c[3]}] +set_property PACKAGE_PIN D23 [get_ports {ddr4_pl_dqs_t[4]}] +set_property PACKAGE_PIN D24 [get_ports {ddr4_pl_dqs_c[4]}] +set_property PACKAGE_PIN J20 [get_ports {ddr4_pl_dqs_t[5]}] +set_property PACKAGE_PIN H20 [get_ports {ddr4_pl_dqs_c[5]}] +set_property PACKAGE_PIN B22 [get_ports {ddr4_pl_dqs_t[6]}] +set_property PACKAGE_PIN A22 [get_ports {ddr4_pl_dqs_c[6]}] +set_property PACKAGE_PIN K21 [get_ports {ddr4_pl_dqs_t[7]}] +set_property PACKAGE_PIN K22 [get_ports {ddr4_pl_dqs_c[7]}] +set_property PACKAGE_PIN A15 [get_ports {ddr4_pl_odt[0]}] +set_property PACKAGE_PIN E14 [get_ports ddr4_pl_reset_n] + +set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_ddr4_clk_p] +set_property IOSTANDARD SSTL12_DCI [get_ports ddr4_pl_act_n] +set_property IOSTANDARD SSTL12_DCI [get_ports {ddr4_pl_ba[?]}] +set_property IOSTANDARD SSTL12_DCI [get_ports {ddr4_pl_bg[0]}] +set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports {ddr4_pl_ck_c[0]}] +set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports {ddr4_pl_ck_t[0]}] +set_property IOSTANDARD SSTL12_DCI [get_ports {ddr4_pl_cke[0]}] +set_property IOSTANDARD SSTL12_DCI [get_ports {ddr4_pl_cs_n[0]}] +set_property IOSTANDARD POD12_DCI [get_ports {ddr4_pl_dm_n[?]}] +set_property IOSTANDARD SSTL12_DCI [get_ports {ddr4_pl_adr[?]}] +set_property IOSTANDARD SSTL12_DCI [get_ports {ddr4_pl_odt[?]}] +set_property IOSTANDARD LVCMOS12 [get_ports ddr4_pl_reset_n] +set_property IOSTANDARD DIFF_POD12_DCI [get_ports {ddr4_pl_dqs_t[?]}] +set_property IOSTANDARD DIFF_POD12_DCI [get_ports {ddr4_pl_dqs_c[?]}] +set_property IOSTANDARD POD12_DCI [get_ports {ddr4_pl_dq[?]}] + diff --git a/firmware/RFSoc_4x2/RF4x2_src/proj.tcl b/firmware/RFSoc_4x2/RF4x2_src/proj.tcl new file mode 100644 index 0000000..255e113 --- /dev/null +++ b/firmware/RFSoc_4x2/RF4x2_src/proj.tcl @@ -0,0 +1,79 @@ +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "top" + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/"]" + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu48dr-ffvg1517-2-e + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "board_part_repo_paths" -value "[file normalize "$origin_dir/../../board_files"]" -objects $obj +set_property -name "board_part" -value "realdigital.org:rfsoc4x2:part0:1.0" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "platform.board_id" -value "rfsoc4x2" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj + +# Set IP repository paths +set obj [get_filesets sources_1] +set_property "ip_repo_paths" [concat [file normalize "$origin_dir/../../ip"] [file normalize "$origin_dir/ip"]] $obj + +# Rebuild user ip_repo's index before adding any source files +update_ip_catalog -rebuild + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [ file normalize "$origin_dir/../../hdl/vect2bits_16.v"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set files [list \ + [ file normalize "$origin_dir/timing.xdc"] \ + [ file normalize "$origin_dir/ios.xdc"] \ +] +add_files -fileset $obj $files + +# Source Block Design. +set file "[file normalize "$origin_dir/bd_2023-1.tcl"]" +source $file + +# Update compile order. +#update_compile_order -fileset sources_1 + +# Set sources_1 fileset object +set obj [get_filesets sources_1] +# Create HDL Wrapper. +make_wrapper -files [get_files d_1.bd] -top + +# Add files to sources_1 fileset +set files [list \ + [file normalize "${origin_dir}/top/top.srcs/sources_1/bd/d_1/hdl/d_1_wrapper.v" ]\ +] +add_files -fileset $obj $files + +set_property strategy "Flow_PerfOptimized_high" [get_runs synth_1] +set_property strategy "Performance_NetDelay_high" [get_runs impl_1] diff --git a/firmware/RFSoc_4x2/RF4x2_src/timing.xdc b/firmware/RFSoc_4x2/RF4x2_src/timing.xdc new file mode 100644 index 0000000..b07aa56 --- /dev/null +++ b/firmware/RFSoc_4x2/RF4x2_src/timing.xdc @@ -0,0 +1,35 @@ + + +# AXI to gen/RO fabric +set_clock_groups -name clk_axi_to_adc0_x2 -asynchronous -group [get_clocks [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/zynq_ultra_ps_e_0/pl_clk0]]]] -group [get_clocks [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/clk_adc0_x2/clk_out1]]]] + +set_clock_groups -name clk_axi_to_dac0 -asynchronous -group [get_clocks [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/zynq_ultra_ps_e_0/pl_clk0]]]] -group [get_clocks [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac0]]]] + +set_clock_groups -name clk_axi_to_dac2 -asynchronous -group [get_clocks [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/zynq_ultra_ps_e_0/pl_clk0]]]] -group [get_clocks [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac2]]]] + +## AXI to tproc +#set_clock_group -name clk_axi_to_tproc -asynchronous # -group [get_clocks $clk_axi] # -group [get_clocks $clk_tproc] + +## tproc to gen/RO fabric +#set_clock_group -name clk_tproc_to_dac0 -asynchronous # -group [get_clocks $clk_tproc] # -group [get_clocks $clk_dac0] + +set_clock_groups -name clk_tproc_to_dac2 -asynchronous -group [get_clocks [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac0]]]] -group [get_clocks [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac2]]]] + +set_clock_groups -name clk_tproc_to_adc0_x2 -asynchronous -group [get_clocks [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac0]]]] -group [get_clocks [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/clk_adc0_x2/clk_out1]]]] + +# axi to DDR4, DDR4 to RO fabric +set_clock_groups -name clk_axi_to_ddr4 -asynchronous -group [get_clocks [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/zynq_ultra_ps_e_0/pl_clk0]]]] -group [get_clocks [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/ddr4_0/c0_ddr4_ui_clk]]]] + +set_clock_groups -name clk_ddr4_to_adc0_x2 -asynchronous -group [get_clocks [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/ddr4_0/c0_ddr4_ui_clk]]]] -group [get_clocks [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/clk_adc0_x2/clk_out1]]]] + +set_false_path -from [get_cells d_1_i/axis_set_reg_0/U0/dout_r_reg*] + + + +# from https://github.com/Xilinx/RFSoC-MTS/blob/main/boards/RFSoC4x2/build_mts/mts.xdc +#set_property BLOCK_SYNTH.RETIMING 1 [get_cells d_1_i/ddr4_0] +#set_property BLOCK_SYNTH.STRATEGY {PERFORMANCE_OPTIMIZED} [get_cells d_1_i/ddr4_0] + +#set_property BLOCK_SYNTH.RETIMING 1 [get_cells {d_1_i/usp_rf_data_converter_0/*}] +#set_property BLOCK_SYNTH.STRATEGY {PERFORMANCE_OPTIMIZED} [get_cells {d_1_i/usp_rf_data_converter_0/*}] + diff --git a/firmware/photon_counting_9ghz/qick_4x2.bit b/firmware/RFSoc_4x2/qickdawg_4x2.bit similarity index 85% rename from firmware/photon_counting_9ghz/qick_4x2.bit rename to firmware/RFSoc_4x2/qickdawg_4x2.bit index de8591b..7c9de21 100644 Binary files a/firmware/photon_counting_9ghz/qick_4x2.bit and b/firmware/RFSoc_4x2/qickdawg_4x2.bit differ diff --git a/firmware/photon_counting/qick_4x2.hwh b/firmware/RFSoc_4x2/qickdawg_4x2.hwh similarity index 96% rename from firmware/photon_counting/qick_4x2.hwh rename to firmware/RFSoc_4x2/qickdawg_4x2.hwh index f396d97..26257ae 100644 --- a/firmware/photon_counting/qick_4x2.hwh +++ b/firmware/RFSoc_4x2/qickdawg_4x2.hwh @@ -1,5 +1,5 @@  - + @@ -309,7 +309,7 @@ - + @@ -654,8 +654,8 @@ - - + + @@ -945,7 +945,7 @@ - + @@ -1208,7 +1208,7 @@ - + @@ -1224,7 +1224,7 @@ - + @@ -1384,7 +1384,7 @@ - + @@ -1644,7 +1644,7 @@ - + @@ -1804,7 +1804,7 @@ - + @@ -2088,8 +2088,8 @@ - - + + @@ -2428,7 +2428,7 @@ - + @@ -2444,7 +2444,7 @@ - + @@ -2604,7 +2604,7 @@ - + @@ -2864,7 +2864,7 @@ - + @@ -3024,7 +3024,7 @@ - + @@ -3308,8 +3308,8 @@ - - + + @@ -3648,7 +3648,7 @@ - + @@ -3664,7 +3664,7 @@ - + @@ -3824,7 +3824,7 @@ - + @@ -4084,7 +4084,7 @@ - + @@ -4244,7 +4244,7 @@ - + @@ -4528,8 +4528,8 @@ - - + + @@ -4855,7 +4855,7 @@ - + @@ -4871,7 +4871,7 @@ - + @@ -5031,7 +5031,7 @@ - + @@ -5291,7 +5291,7 @@ - + @@ -5451,7 +5451,7 @@ - + @@ -5735,8 +5735,8 @@ - - + + @@ -6075,7 +6075,7 @@ - + @@ -6091,7 +6091,7 @@ - + @@ -6251,7 +6251,7 @@ - + @@ -6511,7 +6511,7 @@ - + @@ -6671,7 +6671,7 @@ - + @@ -6955,8 +6955,8 @@ - - + + @@ -9000,8 +9000,8 @@ - - + + @@ -9165,7 +9165,7 @@ - + @@ -9355,6 +9355,171 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -9653,171 +9818,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -10213,8 +10213,8 @@ - - + + @@ -10564,8 +10564,8 @@ - - + + @@ -10904,7 +10904,7 @@ - + @@ -11066,7 +11066,7 @@ - + @@ -11240,8 +11240,8 @@ - - + + @@ -11749,13 +11749,13 @@ - + - + @@ -11880,7 +11880,7 @@ - + @@ -12005,7 +12005,7 @@ - + @@ -12130,7 +12130,7 @@ - + @@ -12255,7 +12255,7 @@ - + @@ -12380,7 +12380,7 @@ - + @@ -12497,8 +12497,8 @@ - - + + @@ -12784,8 +12784,8 @@ - - + + @@ -13248,7 +13248,7 @@ - + @@ -13366,7 +13366,7 @@ - + @@ -13550,7 +13550,7 @@ - + @@ -13558,10 +13558,12 @@ + + - - + + @@ -13852,7 +13854,7 @@ - + @@ -13860,10 +13862,12 @@ + + - - + + @@ -14154,7 +14158,7 @@ - + @@ -14178,7 +14182,7 @@ - + @@ -14494,8 +14498,8 @@ - - + + @@ -14768,7 +14772,7 @@ - + @@ -14792,7 +14796,7 @@ - + @@ -15108,8 +15112,8 @@ - - + + @@ -15382,7 +15386,7 @@ - + @@ -15406,7 +15410,7 @@ - + @@ -15722,8 +15726,8 @@ - - + + @@ -15964,7 +15968,7 @@ - + @@ -16304,8 +16308,8 @@ - - + + @@ -16580,7 +16584,7 @@ - + @@ -16604,7 +16608,7 @@ - + @@ -16920,8 +16924,8 @@ - - + + @@ -17188,8 +17192,8 @@ - - + + @@ -17818,7 +17822,7 @@ - + @@ -18410,6 +18414,8 @@ + + @@ -18422,8 +18428,6 @@ - - @@ -18435,7 +18439,7 @@ - + @@ -18586,6 +18590,8 @@ + + @@ -18707,8 +18713,8 @@ - - + + @@ -18797,8 +18803,8 @@ - + @@ -19103,7 +19109,7 @@ - + @@ -19114,10 +19120,11 @@ + - - + + @@ -19390,7 +19397,7 @@ - + @@ -19753,2424 +19760,2759 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + + + + + + + + + - + - + - + - + - + - + + + - + - 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+ - + - + - + + + + + + - + - + + + - + - + - + - + - + - + - + - + + - + - + - + - + - + - + + + + + + + + + - + - + - + - + - + - + + + - + - + - + - + - + - - + - + - + - + - + - + - - + + + + + + + + + - + - + - + - + - + - + - + - + + - + - + - + - - + - + - + - + - + - + - + - + - + - + - + - + - @@ -22179,7 +22521,6 @@ - @@ -22187,11 +22528,9 @@ - - @@ -22200,36 +22539,56 @@ - - + + + + + + + + + + + + + + + + + + + + + + @@ -22237,22 +22596,38 @@ + + + + + + + + + + + + + + + + @@ -22260,22 +22635,38 @@ + + + + + + + + + + + + + + + + @@ -22283,22 +22674,38 @@ + + + + + + + + + + + + + + + + @@ -22306,22 +22713,38 @@ + + + + + + + + + + + + + + + + @@ -22329,22 +22752,38 @@ + + + + + + + + + + + + + + + + @@ -22352,22 +22791,38 @@ + + + + + + + + + + + + + + + + @@ -22375,22 +22830,38 @@ + + + + + + + + + + + + + + + + @@ -22398,22 +22869,38 @@ + + + + + + + + + + + + + + + + @@ -22421,22 +22908,38 @@ + + + + + + + + + + + + + + + + @@ -22444,22 +22947,38 @@ + + + + + + + + + + + + + + + + @@ -22467,22 +22986,38 @@ + + + + + + + + + + + + + + + + @@ -22490,22 +23025,38 @@ + + + + + + + + + + + + + + + + @@ -22513,22 +23064,38 @@ + + + + + + + + + + + + + + + + @@ -22536,22 +23103,38 @@ + + + + + + + + + + + + + + + + @@ -22559,22 +23142,38 @@ + + + + + + + + + + + + + + + + @@ -22582,22 +23181,38 @@ + + + + + + + + + + + + + + + + @@ -22605,22 +23220,38 @@ + + + + + + + + + + + + + + + + @@ -22667,22 +23298,38 @@ + + + + + + + + + + + + + + + + @@ -22690,22 +23337,38 @@ + + + + + + + + + + + + + + + + @@ -22713,22 +23376,38 @@ + + + + + + + + + + + + + + + + @@ -22778,27 +23457,32 @@ + + + + + + + + + + + + + + + - - - - - - - - - - @@ -22807,12 +23491,8 @@ - - - - - + @@ -22835,7 +23515,6 @@ - @@ -22930,6 +23609,7 @@ + @@ -22942,7 +23622,6 @@ - @@ -22988,15 +23667,15 @@ - - - - - + + + + + @@ -23042,9 +23721,9 @@ - + @@ -23099,7 +23778,7 @@ - + @@ -23892,7 +24571,7 @@ - + @@ -25536,8 +26215,8 @@ - - + + @@ -25552,8 +26231,8 @@ - + @@ -25568,17 +26247,17 @@ - - - - - - + + + + + + @@ -25594,10 +26273,10 @@ - + @@ -26349,25 +27028,10 @@ - + - + - - - - - - - - - - - - - - - @@ -26620,7 +27284,7 @@ - + @@ -28697,33 +29361,39 @@ + + + + + + + + + + + + + + + + - - + - + - + + + - - - - - - - - - - - @@ -28732,12 +29402,8 @@ - - - - - + @@ -28760,8 +29426,6 @@ - - @@ -29000,29 +29664,29 @@ - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/common_clock/README.txt b/firmware/common_clock/README.txt deleted file mode 100644 index cfabd6a..0000000 --- a/firmware/common_clock/README.txt +++ /dev/null @@ -1 +0,0 @@ -standard firmware, but DAC+ADC fabric clks, tproc clk are all 409.6 MHz diff --git a/firmware/common_clock/bd_4x2_2020-2.tcl b/firmware/common_clock/bd_4x2_2020-2.tcl deleted file mode 100644 index 2f486ea..0000000 --- a/firmware/common_clock/bd_4x2_2020-2.tcl +++ /dev/null @@ -1,1540 +0,0 @@ - -################################################################ -# This is a generated script based on design: d_1 -# -# Though there are limitations about the generated script, -# the main purpose of this utility is to make learning -# IP Integrator Tcl commands easier. -################################################################ - -namespace eval _tcl { -proc get_script_folder {} { - set script_path [file normalize [info script]] - set script_folder [file dirname $script_path] - return $script_folder -} -} -variable script_folder -set script_folder [_tcl::get_script_folder] - -################################################################ -# Check if script is running in correct Vivado version. -################################################################ -set scripts_vivado_version 2020.2 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 -} - -################################################################ -# START -################################################################ - -# To test this script, run the following commands from Vivado Tcl console: -# source d_1_script.tcl - - -# The design that will be created by this Tcl script contains the following -# module references: -# vect2bits_16 - -# Please add the sources of those modules before sourcing this Tcl script. - -# If there is no project opened, this script will create a -# project, but make sure you do not have an existing project -# <./myproj/project_1.xpr> in the current working folder. - -set list_projs [get_projects -quiet] -if { $list_projs eq "" } { - create_project project_1 myproj -part xczu48dr-ffvg1517-2-e - set_property BOARD_PART realdigital.org:rfsoc4x2:part0:1.0 [current_project] -} - - -# CHANGE DESIGN NAME HERE -variable design_name -set design_name d_1 - -# If you do not already have an existing IP Integrator design open, -# you can create a design using the following command: -# create_bd_design $design_name - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} - -common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." - -if { $nRet != 0 } { - catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} - return $nRet -} - -set bCheckIPsPassed 1 -################################################################## -# CHECK IPs -################################################################## -set bCheckIPs 1 -if { $bCheckIPs == 1 } { - set list_check_ips "\ -xilinx.com:ip:axi_bram_ctrl:4.1\ -xilinx.com:ip:blk_mem_gen:8.4\ -xilinx.com:ip:axi_dma:7.1\ -xilinx.com:ip:smartconnect:1.0\ -user.org:user:axis_avg_buffer:1.0\ -xilinx.com:ip:axis_clock_converter:1.1\ -user.org:user:axis_constant:1.0\ -user.org:user:axis_readout_v2:1.0\ -user.org:user:axis_register_slice_nb:1.0\ -xilinx.com:ip:axis_register_slice:1.1\ -user.org:user:axis_set_reg:1.0\ -user.org:user:axis_signal_gen_v6:1.0\ -xilinx.com:ip:axis_switch:1.1\ -user.org:user:axis_tproc64x32_x8:1.0\ -xilinx.com:ip:clk_wiz:6.0\ -user.org:user:mr_buffer_et:1.0\ -xilinx.com:ip:proc_sys_reset:5.0\ -xilinx.com:ip:usp_rf_data_converter:2.4\ -xilinx.com:ip:xlconstant:1.1\ -xilinx.com:ip:zynq_ultra_ps_e:3.3\ -" - - set list_ips_missing "" - common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." - - foreach ip_vlnv $list_check_ips { - set ip_obj [get_ipdefs -all $ip_vlnv] - if { $ip_obj eq "" } { - lappend list_ips_missing $ip_vlnv - } - } - - if { $list_ips_missing ne "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } - set bCheckIPsPassed 0 - } - -} - -################################################################## -# CHECK Modules -################################################################## -set bCheckModules 1 -if { $bCheckModules == 1 } { - set list_check_mods "\ -vect2bits_16\ -" - - set list_mods_missing "" - common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." - - foreach mod_vlnv $list_check_mods { - if { [can_resolve_reference $mod_vlnv] == 0 } { - lappend list_mods_missing $mod_vlnv - } - } - - if { $list_mods_missing ne "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } - common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." - set bCheckIPsPassed 0 - } -} - -if { $bCheckIPsPassed != 1 } { - common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." - return 3 -} - -################################################################## -# DESIGN PROCs -################################################################## - - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell } { - - variable script_folder - variable design_name - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - - # Create interface ports - set adc0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc0_clk ] - - set dac0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac0_clk ] - - set dac2_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac2_clk ] - - set sysref_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0 sysref_in ] - - set vin0_01 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin0_01 ] - - set vin0_23 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin0_23 ] - - set vout00 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout00 ] - - set vout20 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout20 ] - - - # Create ports - set PMOD0_0 [ create_bd_port -dir O PMOD0_0 ] - set PMOD0_1 [ create_bd_port -dir O PMOD0_1 ] - set PMOD0_2 [ create_bd_port -dir O PMOD0_2 ] - set PMOD0_3 [ create_bd_port -dir O PMOD0_3 ] - - # Create instance: axi_bram_ctrl_0, and set properties - set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - CONFIG.ECC_TYPE {0} \ - CONFIG.SINGLE_PORT_BRAM {1} \ - ] $axi_bram_ctrl_0 - - # Create instance: axi_bram_ctrl_0_bram, and set properties - set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] - set_property -dict [ list \ - CONFIG.Byte_Size {8} \ - CONFIG.EN_SAFETY_CKT {false} \ - CONFIG.Enable_32bit_Address {true} \ - CONFIG.Memory_Type {True_Dual_Port_RAM} \ - CONFIG.Read_Width_B {64} \ - CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ - CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \ - CONFIG.Use_Byte_Write_Enable {true} \ - CONFIG.Use_RSTA_Pin {true} \ - CONFIG.Use_RSTB_Pin {true} \ - CONFIG.Write_Width_B {64} \ - CONFIG.use_bram_block {BRAM_Controller} \ - ] $axi_bram_ctrl_0_bram - - # Create instance: axi_dma_avg, and set properties - set axi_dma_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_avg ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_avg - - # Create instance: axi_dma_buf, and set properties - set axi_dma_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_buf ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_buf - - # Create instance: axi_dma_gen, and set properties - set axi_dma_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_gen ] - set_property -dict [ list \ - CONFIG.c_include_s2mm {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_gen - - # Create instance: axi_dma_readout, and set properties - set axi_dma_readout [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_readout ] - set_property -dict [ list \ - CONFIG.c_include_mm2s {0} \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - CONFIG.c_sg_length_width {26} \ - ] $axi_dma_readout - - # Create instance: axi_dma_tproc, and set properties - set axi_dma_tproc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_tproc ] - set_property -dict [ list \ - CONFIG.c_include_sg {0} \ - CONFIG.c_sg_include_stscntrl_strm {0} \ - ] $axi_dma_tproc - - # Create instance: axi_smc, and set properties - set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] - set_property -dict [ list \ - CONFIG.NUM_SI {6} \ - ] $axi_smc - - # Create instance: axis_avg_buffer_0, and set properties - set axis_avg_buffer_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.0 axis_avg_buffer_0 ] - set_property -dict [ list \ - CONFIG.N_BUF {14} \ - ] $axis_avg_buffer_0 - - # Create instance: axis_avg_buffer_1, and set properties - set axis_avg_buffer_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.0 axis_avg_buffer_1 ] - set_property -dict [ list \ - CONFIG.N_BUF {14} \ - ] $axis_avg_buffer_1 - - # Create instance: axis_cc_avg_0, and set properties - set axis_cc_avg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_cc_avg_0 ] - - # Create instance: axis_cc_avg_1, and set properties - set axis_cc_avg_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_cc_avg_1 ] - - # Create instance: axis_cc_sg_0, and set properties - set axis_cc_sg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_cc_sg_0 ] - - # Create instance: axis_cc_sg_1, and set properties - set axis_cc_sg_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_cc_sg_1 ] - - # Create instance: axis_constant_0, and set properties - set axis_constant_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - ] $axis_constant_0 - - # Create instance: axis_constant_1, and set properties - set axis_constant_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_constant:1.0 axis_constant_1 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {64} \ - ] $axis_constant_1 - - # Create instance: axis_readout_v2_0, and set properties - set axis_readout_v2_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_0 ] - - # Create instance: axis_readout_v2_1, and set properties - set axis_readout_v2_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_1 ] - - # Create instance: axis_register_slice_0, and set properties - set axis_register_slice_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_register_slice_nb:1.0 axis_register_slice_0 ] - set_property -dict [ list \ - CONFIG.B {256} \ - ] $axis_register_slice_0 - - # Create instance: axis_register_slice_1, and set properties - set axis_register_slice_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_register_slice_nb:1.0 axis_register_slice_1 ] - set_property -dict [ list \ - CONFIG.B {256} \ - ] $axis_register_slice_1 - - # Create instance: axis_register_slice_2, and set properties - set axis_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_2 ] - set_property -dict [ list \ - CONFIG.REG_CONFIG {8} \ - ] $axis_register_slice_2 - - # Create instance: axis_register_slice_3, and set properties - set axis_register_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_3 ] - set_property -dict [ list \ - CONFIG.REG_CONFIG {8} \ - ] $axis_register_slice_3 - - # Create instance: axis_set_reg_0, and set properties - set axis_set_reg_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_set_reg:1.0 axis_set_reg_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {160} \ - ] $axis_set_reg_0 - - # Create instance: axis_signal_gen_v6_0, and set properties - set axis_signal_gen_v6_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_0 ] - - # Create instance: axis_signal_gen_v6_1, and set properties - set axis_signal_gen_v6_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_1 ] - - # Create instance: axis_switch_avg, and set properties - set axis_switch_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_avg ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_avg - - # Create instance: axis_switch_buf, and set properties - set axis_switch_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_buf ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_buf - - # Create instance: axis_switch_gen, and set properties - set axis_switch_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_gen ] - set_property -dict [ list \ - CONFIG.DECODER_REG {1} \ - CONFIG.NUM_MI {2} \ - CONFIG.NUM_SI {1} \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_gen - - # Create instance: axis_switch_readout, and set properties - set axis_switch_readout [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_readout ] - set_property -dict [ list \ - CONFIG.ROUTING_MODE {1} \ - ] $axis_switch_readout - - # Create instance: axis_tproc64x32_x8_0, and set properties - set axis_tproc64x32_x8_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_tproc64x32_x8:1.0 axis_tproc64x32_x8_0 ] - - # Create instance: clk_adc0_x2, and set properties - set clk_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_adc0_x2 ] - set_property -dict [ list \ - CONFIG.CLKOUT1_JITTER {79.964} \ - CONFIG.CLKOUT1_PHASE_ERROR {81.720} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {409.6} \ - CONFIG.MMCM_CLKFBOUT_MULT_F {5.750} \ - CONFIG.MMCM_CLKOUT0_DIVIDE_F {2.875} \ - CONFIG.MMCM_DIVCLK_DIVIDE {1} \ - CONFIG.RESET_PORT {resetn} \ - CONFIG.RESET_TYPE {ACTIVE_LOW} \ - ] $clk_adc0_x2 - - # Create instance: mr_buffer_et_0, and set properties - set mr_buffer_et_0 [ create_bd_cell -type ip -vlnv user.org:user:mr_buffer_et:1.0 mr_buffer_et_0 ] - set_property -dict [ list \ - CONFIG.B {32} \ - ] $mr_buffer_et_0 - - # Create instance: ps8_0_axi_periph, and set properties - set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] - set_property -dict [ list \ - CONFIG.NUM_MI {19} \ - ] $ps8_0_axi_periph - - # Create instance: rst_100, and set properties - set rst_100 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_100 ] - - # Create instance: rst_adc0, and set properties - set rst_adc0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0 ] - - # Create instance: rst_adc0_x2, and set properties - set rst_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0_x2 ] - - # Create instance: rst_dac0, and set properties - set rst_dac0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac0 ] - - # Create instance: rst_dac1, and set properties - set rst_dac1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac1 ] - - # Create instance: usp_rf_data_converter_0, and set properties - set usp_rf_data_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.4 usp_rf_data_converter_0 ] - set_property -dict [ list \ - CONFIG.ADC0_Fabric_Freq {409.600} \ - CONFIG.ADC0_Outclk_Freq {204.800} \ - CONFIG.ADC0_PLL_Enable {true} \ - CONFIG.ADC0_Refclk_Freq {409.600} \ - CONFIG.ADC0_Sampling_Rate {3.2768} \ - CONFIG.ADC_Coarse_Mixer_Freq02 {3} \ - CONFIG.ADC_Coarse_Mixer_Freq03 {3} \ - CONFIG.ADC_Data_Width00 {8} \ - CONFIG.ADC_Data_Width01 {8} \ - CONFIG.ADC_Data_Width02 {8} \ - CONFIG.ADC_Data_Width03 {8} \ - CONFIG.ADC_Decimation_Mode02 {1} \ - CONFIG.ADC_Decimation_Mode03 {1} \ - CONFIG.ADC_Mixer_Type02 {1} \ - CONFIG.ADC_Mixer_Type03 {1} \ - CONFIG.ADC_RESERVED_1_00 {false} \ - CONFIG.ADC_RESERVED_1_02 {false} \ - CONFIG.ADC_Slice02_Enable {true} \ - CONFIG.ADC_Slice03_Enable {true} \ - CONFIG.DAC0_Enable {1} \ - CONFIG.DAC0_Fabric_Freq {409.600} \ - CONFIG.DAC0_Outclk_Freq {409.600} \ - CONFIG.DAC0_PLL_Enable {true} \ - CONFIG.DAC0_Refclk_Freq {409.600} \ - CONFIG.DAC0_Sampling_Rate {6.5536} \ - CONFIG.DAC2_Enable {1} \ - CONFIG.DAC2_Fabric_Freq {409.600} \ - CONFIG.DAC2_Outclk_Freq {409.600} \ - CONFIG.DAC2_PLL_Enable {true} \ - CONFIG.DAC2_Refclk_Freq {409.600} \ - CONFIG.DAC2_Sampling_Rate {6.5536} \ - CONFIG.DAC_Coarse_Mixer_Freq00 {3} \ - CONFIG.DAC_Coarse_Mixer_Freq20 {3} \ - CONFIG.DAC_Interpolation_Mode00 {1} \ - CONFIG.DAC_Interpolation_Mode20 {1} \ - CONFIG.DAC_Mixer_Type00 {1} \ - CONFIG.DAC_Mixer_Type20 {1} \ - CONFIG.DAC_Mode00 {3} \ - CONFIG.DAC_Mode20 {3} \ - CONFIG.DAC_RESERVED_1_00 {false} \ - CONFIG.DAC_RESERVED_1_01 {false} \ - CONFIG.DAC_RESERVED_1_02 {false} \ - CONFIG.DAC_RESERVED_1_03 {false} \ - CONFIG.DAC_RESERVED_1_20 {false} \ - CONFIG.DAC_RESERVED_1_21 {false} \ - CONFIG.DAC_RESERVED_1_22 {false} \ - CONFIG.DAC_RESERVED_1_23 {false} \ - CONFIG.DAC_Slice00_Enable {true} \ - CONFIG.DAC_Slice20_Enable {true} \ - ] $usp_rf_data_converter_0 - - # Create instance: vect2bits_16_0, and set properties - set block_name vect2bits_16 - set block_cell_name vect2bits_16_0 - if { [catch {set vect2bits_16_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } elseif { $vect2bits_16_0 eq "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} - return 1 - } - - # Create instance: xlconstant_0, and set properties - set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {64} \ - ] $xlconstant_0 - - # Create instance: xlconstant_1, and set properties - set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {1} \ - CONFIG.CONST_WIDTH {1} \ - ] $xlconstant_1 - - # Create instance: xlconstant_2, and set properties - set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {1} \ - ] $xlconstant_2 - - # Create instance: xlconstant_3, and set properties - set xlconstant_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_3 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {8} \ - ] $xlconstant_3 - - # Create instance: zynq_ultra_ps_e_0, and set properties - set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ] - set_property -dict [ list \ - CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS33} \ - CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ - CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ - CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ - CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \ - CONFIG.PSU_MIO_0_DIRECTION {inout} \ - CONFIG.PSU_MIO_0_POLARITY {Default} \ - CONFIG.PSU_MIO_10_DIRECTION {inout} \ - CONFIG.PSU_MIO_10_POLARITY {Default} \ - CONFIG.PSU_MIO_11_DIRECTION {inout} \ - CONFIG.PSU_MIO_11_POLARITY {Default} \ - CONFIG.PSU_MIO_12_DIRECTION {inout} \ - CONFIG.PSU_MIO_12_POLARITY {Default} \ - CONFIG.PSU_MIO_13_DIRECTION {inout} \ - CONFIG.PSU_MIO_13_POLARITY {Default} \ - CONFIG.PSU_MIO_14_DIRECTION {inout} \ - CONFIG.PSU_MIO_14_POLARITY {Default} \ - CONFIG.PSU_MIO_15_DIRECTION {inout} \ - CONFIG.PSU_MIO_15_POLARITY {Default} \ - CONFIG.PSU_MIO_16_DIRECTION {inout} \ - CONFIG.PSU_MIO_16_POLARITY {Default} \ - CONFIG.PSU_MIO_17_DIRECTION {inout} \ - CONFIG.PSU_MIO_17_POLARITY {Default} \ - CONFIG.PSU_MIO_18_DIRECTION {inout} \ - CONFIG.PSU_MIO_18_POLARITY {Default} \ - CONFIG.PSU_MIO_19_DIRECTION {inout} \ - CONFIG.PSU_MIO_19_POLARITY {Default} \ - CONFIG.PSU_MIO_1_DIRECTION {out} \ - CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_1_POLARITY {Default} \ - CONFIG.PSU_MIO_20_DIRECTION {inout} \ - CONFIG.PSU_MIO_20_POLARITY {Default} \ - CONFIG.PSU_MIO_21_DIRECTION {inout} \ - CONFIG.PSU_MIO_21_POLARITY {Default} \ - CONFIG.PSU_MIO_22_DIRECTION {out} \ - CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_22_POLARITY {Default} \ - CONFIG.PSU_MIO_23_DIRECTION {inout} \ - CONFIG.PSU_MIO_23_POLARITY {Default} \ - CONFIG.PSU_MIO_24_DIRECTION {in} \ - CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_24_POLARITY {Default} \ - CONFIG.PSU_MIO_24_SLEW {fast} \ - CONFIG.PSU_MIO_25_DIRECTION {in} \ - CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_25_POLARITY {Default} \ - CONFIG.PSU_MIO_25_SLEW {fast} \ - CONFIG.PSU_MIO_26_DIRECTION {inout} \ - CONFIG.PSU_MIO_26_POLARITY {Default} \ - CONFIG.PSU_MIO_27_DIRECTION {out} \ - CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_27_POLARITY {Default} \ - CONFIG.PSU_MIO_28_DIRECTION {in} \ - CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_28_POLARITY {Default} \ - CONFIG.PSU_MIO_28_SLEW {fast} \ - CONFIG.PSU_MIO_29_DIRECTION {out} \ - CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_29_POLARITY {Default} \ - CONFIG.PSU_MIO_2_DIRECTION {out} \ - CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_2_POLARITY {Default} \ - CONFIG.PSU_MIO_30_DIRECTION {in} \ - CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_30_POLARITY {Default} \ - CONFIG.PSU_MIO_30_SLEW {fast} \ - CONFIG.PSU_MIO_31_DIRECTION {inout} \ - CONFIG.PSU_MIO_31_POLARITY {Default} \ - CONFIG.PSU_MIO_32_DIRECTION {out} \ - CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_32_POLARITY {Default} \ - CONFIG.PSU_MIO_33_DIRECTION {in} \ - CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_33_POLARITY {Default} \ - CONFIG.PSU_MIO_33_SLEW {fast} \ - CONFIG.PSU_MIO_34_DIRECTION {inout} \ - CONFIG.PSU_MIO_34_POLARITY {Default} \ - CONFIG.PSU_MIO_35_DIRECTION {inout} \ - CONFIG.PSU_MIO_35_POLARITY {Default} \ - CONFIG.PSU_MIO_36_DIRECTION {inout} \ - CONFIG.PSU_MIO_36_POLARITY {Default} \ - CONFIG.PSU_MIO_37_DIRECTION {inout} \ - CONFIG.PSU_MIO_37_POLARITY {Default} \ - CONFIG.PSU_MIO_38_DIRECTION {out} \ - CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_38_POLARITY {Default} \ - CONFIG.PSU_MIO_39_DIRECTION {out} \ - CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_39_POLARITY {Default} \ - CONFIG.PSU_MIO_3_DIRECTION {inout} \ - CONFIG.PSU_MIO_3_POLARITY {Default} \ - CONFIG.PSU_MIO_40_DIRECTION {out} \ - CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_40_POLARITY {Default} \ - CONFIG.PSU_MIO_41_DIRECTION {out} \ - CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_41_POLARITY {Default} \ - CONFIG.PSU_MIO_42_DIRECTION {out} \ - CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_42_POLARITY {Default} \ - CONFIG.PSU_MIO_43_DIRECTION {out} \ - CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_43_POLARITY {Default} \ - CONFIG.PSU_MIO_44_DIRECTION {in} \ - CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_44_POLARITY {Default} \ - CONFIG.PSU_MIO_44_SLEW {fast} \ - CONFIG.PSU_MIO_45_DIRECTION {in} \ - CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_45_POLARITY {Default} \ - CONFIG.PSU_MIO_45_SLEW {fast} \ - CONFIG.PSU_MIO_46_DIRECTION {in} \ - CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_46_POLARITY {Default} \ - CONFIG.PSU_MIO_46_SLEW {fast} \ - CONFIG.PSU_MIO_47_DIRECTION {in} \ - CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_47_POLARITY {Default} \ - CONFIG.PSU_MIO_47_SLEW {fast} \ - CONFIG.PSU_MIO_48_DIRECTION {in} \ - CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_48_POLARITY {Default} \ - CONFIG.PSU_MIO_48_SLEW {fast} \ - CONFIG.PSU_MIO_49_DIRECTION {in} \ - CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_49_POLARITY {Default} \ - CONFIG.PSU_MIO_49_SLEW {fast} \ - CONFIG.PSU_MIO_4_DIRECTION {inout} \ - CONFIG.PSU_MIO_4_POLARITY {Default} \ - CONFIG.PSU_MIO_50_DIRECTION {out} \ - CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_50_POLARITY {Default} \ - CONFIG.PSU_MIO_51_DIRECTION {inout} \ - CONFIG.PSU_MIO_51_POLARITY {Default} \ - CONFIG.PSU_MIO_52_DIRECTION {in} \ - CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_52_POLARITY {Default} \ - CONFIG.PSU_MIO_52_SLEW {fast} \ - CONFIG.PSU_MIO_53_DIRECTION {in} \ - CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_53_POLARITY {Default} \ - CONFIG.PSU_MIO_53_SLEW {fast} \ - CONFIG.PSU_MIO_54_DIRECTION {inout} \ - CONFIG.PSU_MIO_54_POLARITY {Default} \ - CONFIG.PSU_MIO_55_DIRECTION {in} \ - CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_55_POLARITY {Default} \ - CONFIG.PSU_MIO_55_SLEW {fast} \ - CONFIG.PSU_MIO_56_DIRECTION {inout} \ - CONFIG.PSU_MIO_56_POLARITY {Default} \ - CONFIG.PSU_MIO_57_DIRECTION {inout} \ - CONFIG.PSU_MIO_57_POLARITY {Default} \ - CONFIG.PSU_MIO_58_DIRECTION {out} \ - CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_58_POLARITY {Default} \ - CONFIG.PSU_MIO_59_DIRECTION {inout} \ - CONFIG.PSU_MIO_59_POLARITY {Default} \ - CONFIG.PSU_MIO_5_DIRECTION {inout} \ - CONFIG.PSU_MIO_5_POLARITY {Default} \ - CONFIG.PSU_MIO_60_DIRECTION {inout} \ - CONFIG.PSU_MIO_60_POLARITY {Default} \ - CONFIG.PSU_MIO_61_DIRECTION {inout} \ - CONFIG.PSU_MIO_61_POLARITY {Default} \ - CONFIG.PSU_MIO_62_DIRECTION {inout} \ - CONFIG.PSU_MIO_62_POLARITY {Default} \ - CONFIG.PSU_MIO_63_DIRECTION {inout} \ - CONFIG.PSU_MIO_63_POLARITY {Default} \ - CONFIG.PSU_MIO_64_DIRECTION {in} \ - CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_64_POLARITY {Default} \ - CONFIG.PSU_MIO_64_SLEW {fast} \ - CONFIG.PSU_MIO_65_DIRECTION {in} \ - CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_65_POLARITY {Default} \ - CONFIG.PSU_MIO_65_SLEW {fast} \ - CONFIG.PSU_MIO_66_DIRECTION {inout} \ - CONFIG.PSU_MIO_66_POLARITY {Default} \ - CONFIG.PSU_MIO_67_DIRECTION {in} \ - CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_67_POLARITY {Default} \ - CONFIG.PSU_MIO_67_SLEW {fast} \ - CONFIG.PSU_MIO_68_DIRECTION {inout} \ - CONFIG.PSU_MIO_68_POLARITY {Default} \ - CONFIG.PSU_MIO_69_DIRECTION {inout} \ - CONFIG.PSU_MIO_69_POLARITY {Default} \ - CONFIG.PSU_MIO_6_DIRECTION {inout} \ - CONFIG.PSU_MIO_6_POLARITY {Default} \ - CONFIG.PSU_MIO_70_DIRECTION {out} \ - CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_70_POLARITY {Default} \ - CONFIG.PSU_MIO_71_DIRECTION {inout} \ - CONFIG.PSU_MIO_71_POLARITY {Default} \ - CONFIG.PSU_MIO_72_DIRECTION {inout} \ - CONFIG.PSU_MIO_72_POLARITY {Default} \ - CONFIG.PSU_MIO_73_DIRECTION {inout} \ - CONFIG.PSU_MIO_73_POLARITY {Default} \ - CONFIG.PSU_MIO_74_DIRECTION {inout} \ - CONFIG.PSU_MIO_74_POLARITY {Default} \ - CONFIG.PSU_MIO_75_DIRECTION {inout} \ - CONFIG.PSU_MIO_75_POLARITY {Default} \ - CONFIG.PSU_MIO_76_DIRECTION {inout} \ - CONFIG.PSU_MIO_76_POLARITY {Default} \ - CONFIG.PSU_MIO_77_DIRECTION {inout} \ - CONFIG.PSU_MIO_77_POLARITY {Default} \ - CONFIG.PSU_MIO_7_DIRECTION {inout} \ - CONFIG.PSU_MIO_7_POLARITY {Default} \ - CONFIG.PSU_MIO_8_DIRECTION {inout} \ - CONFIG.PSU_MIO_8_POLARITY {Default} \ - CONFIG.PSU_MIO_9_DIRECTION {inout} \ - CONFIG.PSU_MIO_9_POLARITY {Default} \ - CONFIG.PSU_MIO_TREE_PERIPHERALS {SPI 0#SPI 0#SPI 0#SPI 0#SPI 0#SPI 0#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#I2C 0#I2C 0#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#SD 0#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#UART 1#UART 1#GPIO1 MIO#GPIO1 MIO#I2C 1#I2C 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#Gem 1#MDIO 1#MDIO 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \ - CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#n_ss_out[2]#n_ss_out[1]#n_ss_out[0]#miso#mosi#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#scl_out#sda_out#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#sdio0_wp#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#txd#rxd#gpio1[34]#gpio1[35]#scl_out#sda_out#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem1_mdc#gem1_mdio_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \ - CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \ - CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ - CONFIG.PSU__ACT_DDR_FREQ_MHZ {1199.999756} \ - CONFIG.PSU__AFI0_COHERENCY {0} \ - CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ - CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.999756} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {599.999878} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1200} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.999878} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {72} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.999996} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {21} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.249996} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {20} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {299.999939} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.999878} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {399.999908} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {524.999939} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {533.333} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999992} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.999908} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.999756} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {124.999977} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {262.499969} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {267} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {524.999939} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {533.333} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.499969} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {63} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.499969} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {7} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.499969} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.499969} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {33.333328} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999985} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {249.999954} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999996} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ - CONFIG.PSU__DDRC__ADDR_MIRROR {0} \ - CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \ - CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ - CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ - CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ - CONFIG.PSU__DDRC__CL {16} \ - CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ - CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ - CONFIG.PSU__DDRC__COMPONENTS {Components} \ - CONFIG.PSU__DDRC__CWL {12} \ - CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {1} \ - CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ - CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ - CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ - CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ - CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ - CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ - CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ - CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ - CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ - CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ - CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ - CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ - CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ - CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ - CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ - CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ - CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ - CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ - CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ - CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ - CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ - CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ - CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ - CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ - CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ - CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ - CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ - CONFIG.PSU__DDRC__ECC {Disabled} \ - CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ - CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ - CONFIG.PSU__DDRC__FGRM {1X} \ - CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__LP_ASR {manual normal} \ - CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ - CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ - CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ - CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ - CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ - CONFIG.PSU__DDRC__ROW_ADDR_COUNT {17} \ - CONFIG.PSU__DDRC__SB_TARGET {16-16-16} \ - CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ - CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2400R} \ - CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ - CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ - CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ - CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ - CONFIG.PSU__DDRC__T_FAW {30.0} \ - CONFIG.PSU__DDRC__T_RAS_MIN {32.0} \ - CONFIG.PSU__DDRC__T_RC {45.32} \ - CONFIG.PSU__DDRC__T_RCD {16} \ - CONFIG.PSU__DDRC__T_RP {16} \ - CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ - CONFIG.PSU__DDRC__VREF {1} \ - CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ - CONFIG.PSU__DDR__INTERFACE__FREQMHZ {600.000} \ - CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ - CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ - CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \ - CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \ - CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__DLL__ISUSED {1} \ - CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ - CONFIG.PSU__DP__LANE_SEL {Dual Lower} \ - CONFIG.PSU__DP__REF_CLK_FREQ {27} \ - CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk0} \ - CONFIG.PSU__ENET1__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {1} \ - CONFIG.PSU__ENET1__GRP_MDIO__IO {MIO 50 .. 51} \ - CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__ENET1__PERIPHERAL__IO {MIO 38 .. 49} \ - CONFIG.PSU__ENET1__PTP__ENABLE {0} \ - CONFIG.PSU__ENET1__TSU__ENABLE {0} \ - CONFIG.PSU__FPGA_PL0_ENABLE {1} \ - CONFIG.PSU__GEM1_COHERENCY {0} \ - CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__GEM__TSU__ENABLE {0} \ - CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ - CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ - CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \ - CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO_EMIO_WIDTH {41} \ - CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {41} \ - CONFIG.PSU__GT__LINK_SPEED {HBR} \ - CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ - CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ - CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \ - CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 18 .. 19} \ - CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 36 .. 37} \ - CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \ - CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \ - CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ - CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ - CONFIG.PSU__PL_CLK0_BUF {TRUE} \ - CONFIG.PSU__PMU_COHERENCY {0} \ - CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ - CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ - CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ - CONFIG.PSU__PMU__GPI0__ENABLE {0} \ - CONFIG.PSU__PMU__GPI1__ENABLE {0} \ - CONFIG.PSU__PMU__GPI2__ENABLE {0} \ - CONFIG.PSU__PMU__GPI3__ENABLE {0} \ - CONFIG.PSU__PMU__GPI4__ENABLE {0} \ - CONFIG.PSU__PMU__GPI5__ENABLE {0} \ - CONFIG.PSU__PMU__GPO0__ENABLE {0} \ - CONFIG.PSU__PMU__GPO1__ENABLE {0} \ - CONFIG.PSU__PMU__GPO2__ENABLE {0} \ - CONFIG.PSU__PMU__GPO3__ENABLE {0} \ - CONFIG.PSU__PMU__GPO4__ENABLE {0} \ - CONFIG.PSU__PMU__GPO5__ENABLE {0} \ - CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ - CONFIG.PSU__PRESET_APPLIED {1} \ - CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;0|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;1|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ - CONFIG.PSU__PROTECTION__SLAVES { \ - LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;0|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;0|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;1|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1 \ - } \ - CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.33333} \ - CONFIG.PSU__QSPI_COHERENCY {0} \ - CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \ - CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \ - CONFIG.PSU__SD0_COHERENCY {0} \ - CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \ - CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \ - CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \ - CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \ - CONFIG.PSU__SD0__GRP_WP__ENABLE {1} \ - CONFIG.PSU__SD0__GRP_WP__IO {MIO 25} \ - CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \ - CONFIG.PSU__SD0__RESET__ENABLE {0} \ - CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \ - CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \ - CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 3} \ - CONFIG.PSU__SPI0__GRP_SS1__ENABLE {1} \ - CONFIG.PSU__SPI0__GRP_SS1__IO {MIO 2} \ - CONFIG.PSU__SPI0__GRP_SS2__ENABLE {1} \ - CONFIG.PSU__SPI0__GRP_SS2__IO {MIO 1} \ - CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 0 .. 5} \ - CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \ - CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \ - CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \ - CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \ - CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \ - CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ - CONFIG.PSU__UART0__MODEM__ENABLE {0} \ - CONFIG.PSU__UART0__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__UART1__BAUD_RATE {115200} \ - CONFIG.PSU__UART1__MODEM__ENABLE {0} \ - CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 32 .. 33} \ - CONFIG.PSU__USB0_COHERENCY {0} \ - CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ - CONFIG.PSU__USB0__REF_CLK_FREQ {100} \ - CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk1} \ - CONFIG.PSU__USB0__RESET__ENABLE {0} \ - CONFIG.PSU__USB1_COHERENCY {0} \ - CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \ - CONFIG.PSU__USB1__REF_CLK_FREQ {100} \ - CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk1} \ - CONFIG.PSU__USB1__RESET__ENABLE {0} \ - CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ - CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ - CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \ - CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ - CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ - CONFIG.PSU__USE__IRQ0 {1} \ - CONFIG.PSU__USE__IRQ1 {1} \ - CONFIG.PSU__USE__M_AXI_GP0 {1} \ - CONFIG.PSU__USE__M_AXI_GP1 {0} \ - CONFIG.PSU__USE__M_AXI_GP2 {0} \ - CONFIG.PSU__USE__S_AXI_GP0 {1} \ - CONFIG.SUBPRESET1 {Custom} \ - ] $zynq_ultra_ps_e_0 - - # Create interface connections - connect_bd_intf_net -intf_net adc0_clk_1 [get_bd_intf_ports adc0_clk] [get_bd_intf_pins usp_rf_data_converter_0/adc0_clk] - connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTA] - connect_bd_intf_net -intf_net axi_dma_avg_M_AXI_S2MM [get_bd_intf_pins axi_dma_avg/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S00_AXI] - connect_bd_intf_net -intf_net axi_dma_buf_M_AXI_S2MM [get_bd_intf_pins axi_dma_buf/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S01_AXI] - connect_bd_intf_net -intf_net axi_dma_gen_M_AXIS_MM2S [get_bd_intf_pins axi_dma_gen/M_AXIS_MM2S] [get_bd_intf_pins axis_switch_gen/S00_AXIS] - connect_bd_intf_net -intf_net axi_dma_gen_M_AXI_MM2S [get_bd_intf_pins axi_dma_gen/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S03_AXI] - connect_bd_intf_net -intf_net axi_dma_readout_M_AXI_S2MM [get_bd_intf_pins axi_dma_readout/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S02_AXI] - connect_bd_intf_net -intf_net axi_dma_tproc_M_AXIS_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXIS_MM2S] [get_bd_intf_pins axis_tproc64x32_x8_0/s0_axis] - connect_bd_intf_net -intf_net axi_dma_tproc_M_AXI_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S04_AXI] - connect_bd_intf_net -intf_net axi_dma_tproc_M_AXI_S2MM [get_bd_intf_pins axi_dma_tproc/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S05_AXI] - connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HPC0_FPD] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m0_axis [get_bd_intf_pins axis_avg_buffer_0/m0_axis] [get_bd_intf_pins axis_switch_avg/S00_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/m1_axis] [get_bd_intf_pins axis_switch_buf/S00_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_0_m2_axis [get_bd_intf_pins axis_avg_buffer_0/m2_axis] [get_bd_intf_pins axis_cc_avg_0/S_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m0_axis [get_bd_intf_pins axis_avg_buffer_1/m0_axis] [get_bd_intf_pins axis_switch_avg/S01_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/m1_axis] [get_bd_intf_pins axis_switch_buf/S01_AXIS] - connect_bd_intf_net -intf_net axis_avg_buffer_1_m2_axis [get_bd_intf_pins axis_avg_buffer_1/m2_axis] [get_bd_intf_pins axis_cc_avg_1/S_AXIS] - connect_bd_intf_net -intf_net axis_cc_avg_0_M_AXIS [get_bd_intf_pins axis_cc_avg_0/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s1_axis] - connect_bd_intf_net -intf_net axis_cc_avg_1_M_AXIS [get_bd_intf_pins axis_cc_avg_1/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s2_axis] - connect_bd_intf_net -intf_net axis_cc_sg_0_M_AXIS [get_bd_intf_pins axis_cc_sg_0/M_AXIS] [get_bd_intf_pins axis_signal_gen_v6_0/s1_axis] - connect_bd_intf_net -intf_net axis_cc_sg_1_M_AXIS [get_bd_intf_pins axis_cc_sg_1/M_AXIS] [get_bd_intf_pins axis_signal_gen_v6_1/s1_axis] - connect_bd_intf_net -intf_net axis_constant_0_m_axis [get_bd_intf_pins axis_constant_0/m_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/s3_axis] - connect_bd_intf_net -intf_net axis_constant_1_m_axis [get_bd_intf_pins axis_constant_1/m_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/s4_axis] - connect_bd_intf_net -intf_net axis_readout_v2_0_m0_axis [get_bd_intf_pins axis_readout_v2_0/m0_axis] [get_bd_intf_pins axis_switch_readout/S00_AXIS] - connect_bd_intf_net -intf_net axis_readout_v2_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/s_axis] [get_bd_intf_pins axis_readout_v2_0/m1_axis] - connect_bd_intf_net -intf_net axis_readout_v2_1_m0_axis [get_bd_intf_pins axis_readout_v2_1/m0_axis] [get_bd_intf_pins axis_switch_readout/S01_AXIS] - connect_bd_intf_net -intf_net axis_readout_v2_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/s_axis] [get_bd_intf_pins axis_readout_v2_1/m1_axis] - connect_bd_intf_net -intf_net axis_register_slice_2_M_AXIS [get_bd_intf_pins axis_readout_v2_0/s_axis] [get_bd_intf_pins axis_register_slice_2/M_AXIS] - connect_bd_intf_net -intf_net axis_register_slice_3_M_AXIS [get_bd_intf_pins axis_readout_v2_1/s_axis] [get_bd_intf_pins axis_register_slice_3/M_AXIS] - connect_bd_intf_net -intf_net axis_register_slice_4_m_axis [get_bd_intf_pins axis_register_slice_1/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s20_axis] - connect_bd_intf_net -intf_net axis_register_slice_6_m_axis [get_bd_intf_pins axis_register_slice_0/m_axis] [get_bd_intf_pins usp_rf_data_converter_0/s00_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_0_m_axis [get_bd_intf_pins axis_register_slice_0/s_axis] [get_bd_intf_pins axis_signal_gen_v6_0/m_axis] - connect_bd_intf_net -intf_net axis_signal_gen_v6_1_m_axis [get_bd_intf_pins axis_register_slice_1/s_axis] [get_bd_intf_pins axis_signal_gen_v6_1/m_axis] - connect_bd_intf_net -intf_net axis_switch_0_M00_AXIS [get_bd_intf_pins axis_switch_readout/M00_AXIS] [get_bd_intf_pins mr_buffer_et_0/s00_axis] - connect_bd_intf_net -intf_net axis_switch_avg_M00_AXIS [get_bd_intf_pins axi_dma_avg/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_avg/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_buf_M00_AXIS [get_bd_intf_pins axi_dma_buf/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_buf/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_gen_M00_AXIS [get_bd_intf_pins axis_signal_gen_v6_0/s0_axis] [get_bd_intf_pins axis_switch_gen/M00_AXIS] - connect_bd_intf_net -intf_net axis_switch_gen_M01_AXIS [get_bd_intf_pins axis_signal_gen_v6_1/s0_axis] [get_bd_intf_pins axis_switch_gen/M01_AXIS] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m0_axis [get_bd_intf_pins axi_dma_tproc/S_AXIS_S2MM] [get_bd_intf_pins axis_tproc64x32_x8_0/m0_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m1_axis [get_bd_intf_pins axis_cc_sg_0/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m1_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m2_axis [get_bd_intf_pins axis_cc_sg_1/S_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/m2_axis] - connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m8_axis [get_bd_intf_pins axis_set_reg_0/s_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m8_axis] - connect_bd_intf_net -intf_net dac0_clk_1 [get_bd_intf_ports dac0_clk] [get_bd_intf_pins usp_rf_data_converter_0/dac0_clk] - connect_bd_intf_net -intf_net dac2_clk_1 [get_bd_intf_ports dac2_clk] [get_bd_intf_pins usp_rf_data_converter_0/dac2_clk] - connect_bd_intf_net -intf_net mr_buffer_et_0_m00_axis [get_bd_intf_pins axi_dma_readout/S_AXIS_S2MM] [get_bd_intf_pins mr_buffer_et_0/m00_axis] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_dma_avg/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins axi_dma_buf/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M02_AXI [get_bd_intf_pins axi_dma_readout/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M02_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M03_AXI [get_bd_intf_pins axis_avg_buffer_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M03_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M04_AXI [get_bd_intf_pins axis_readout_v2_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M04_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M05_AXI [get_bd_intf_pins axis_readout_v2_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M05_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M06_AXI [get_bd_intf_pins axis_switch_avg/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M06_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M07_AXI [get_bd_intf_pins axis_switch_buf/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M07_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M08_AXI [get_bd_intf_pins axis_switch_readout/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M08_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M09_AXI [get_bd_intf_pins axis_tproc64x32_x8_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M09_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M10_AXI [get_bd_intf_pins mr_buffer_et_0/s00_axi] [get_bd_intf_pins ps8_0_axi_periph/M10_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M11_AXI [get_bd_intf_pins ps8_0_axi_periph/M11_AXI] [get_bd_intf_pins usp_rf_data_converter_0/s_axi] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M12_AXI [get_bd_intf_pins axis_avg_buffer_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M12_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M13_AXI [get_bd_intf_pins axis_signal_gen_v6_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M13_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M14_AXI [get_bd_intf_pins axis_signal_gen_v6_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M14_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M15_AXI [get_bd_intf_pins axi_dma_gen/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M15_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M16_AXI [get_bd_intf_pins axis_switch_gen/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M16_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M17_AXI [get_bd_intf_pins axi_dma_tproc/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M17_AXI] - connect_bd_intf_net -intf_net ps8_0_axi_periph_M18_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M18_AXI] - connect_bd_intf_net -intf_net sysref_in_1 [get_bd_intf_ports sysref_in] [get_bd_intf_pins usp_rf_data_converter_0/sysref_in] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_m00_axis [get_bd_intf_pins axis_register_slice_2/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m00_axis] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_m02_axis [get_bd_intf_pins axis_register_slice_3/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m02_axis] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout00 [get_bd_intf_ports vout00] [get_bd_intf_pins usp_rf_data_converter_0/vout00] - connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout20 [get_bd_intf_ports vout20] [get_bd_intf_pins usp_rf_data_converter_0/vout20] - connect_bd_intf_net -intf_net vin0_01_1 [get_bd_intf_ports vin0_01] [get_bd_intf_pins usp_rf_data_converter_0/vin0_01] - connect_bd_intf_net -intf_net vin0_23_1 [get_bd_intf_ports vin0_23] [get_bd_intf_pins usp_rf_data_converter_0/vin0_23] - connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD] - - # Create port connections - connect_bd_net -net axi_bram_ctrl_0_bram_doutb [get_bd_pins axi_bram_ctrl_0_bram/doutb] [get_bd_pins axis_tproc64x32_x8_0/pmem_do] - connect_bd_net -net axis_set_reg_0_dout [get_bd_pins axis_set_reg_0/dout] [get_bd_pins vect2bits_16_0/din] - connect_bd_net -net axis_tproc64x32_x8_0_pmem_addr [get_bd_pins axi_bram_ctrl_0_bram/addrb] [get_bd_pins axis_tproc64x32_x8_0/pmem_addr] - connect_bd_net -net clk_adc0_x2_clk_out1 [get_bd_pins axis_avg_buffer_0/s_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/aclk] [get_bd_pins axis_readout_v2_1/aclk] [get_bd_pins axis_register_slice_2/aclk] [get_bd_pins axis_register_slice_3/aclk] [get_bd_pins axis_switch_readout/aclk] [get_bd_pins clk_adc0_x2/clk_out1] [get_bd_pins mr_buffer_et_0/s00_axis_aclk] [get_bd_pins rst_adc0_x2/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/m0_axis_aclk] - connect_bd_net -net clk_adc0_x2_locked [get_bd_pins clk_adc0_x2/locked] [get_bd_pins rst_adc0_x2/dcm_locked] - connect_bd_net -net rst_adc0_peripheral_aresetn [get_bd_pins clk_adc0_x2/resetn] [get_bd_pins rst_adc0/peripheral_aresetn] - connect_bd_net -net rst_adc0_x2_peripheral_aresetn [get_bd_pins axis_avg_buffer_0/s_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/aresetn] [get_bd_pins axis_readout_v2_1/aresetn] [get_bd_pins axis_register_slice_2/aresetn] [get_bd_pins axis_register_slice_3/aresetn] [get_bd_pins axis_switch_readout/aresetn] [get_bd_pins mr_buffer_et_0/s00_axis_aresetn] [get_bd_pins rst_adc0_x2/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/m0_axis_aresetn] - connect_bd_net -net rst_dac0_peripheral_aresetn [get_bd_pins axis_cc_avg_0/m_axis_aresetn] [get_bd_pins axis_cc_avg_1/m_axis_aresetn] [get_bd_pins axis_cc_sg_0/m_axis_aresetn] [get_bd_pins axis_cc_sg_0/s_axis_aresetn] [get_bd_pins axis_cc_sg_1/s_axis_aresetn] [get_bd_pins axis_constant_0/m_axis_aresetn] [get_bd_pins axis_constant_1/m_axis_aresetn] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins axis_set_reg_0/s_axis_aresetn] [get_bd_pins axis_signal_gen_v6_0/aresetn] [get_bd_pins axis_tproc64x32_x8_0/aresetn] [get_bd_pins rst_dac0/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s0_axis_aresetn] - connect_bd_net -net rst_dac1_peripheral_aresetn [get_bd_pins axis_cc_sg_1/m_axis_aresetn] [get_bd_pins axis_register_slice_1/aresetn] [get_bd_pins axis_signal_gen_v6_1/aresetn] [get_bd_pins rst_dac1/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s2_axis_aresetn] - connect_bd_net -net rst_ps8_0_99M_peripheral_aresetn [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_dma_avg/axi_resetn] [get_bd_pins axi_dma_buf/axi_resetn] [get_bd_pins axi_dma_gen/axi_resetn] [get_bd_pins axi_dma_readout/axi_resetn] [get_bd_pins axi_dma_tproc/axi_resetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins axis_avg_buffer_0/m_axis_aresetn] [get_bd_pins axis_avg_buffer_0/s_axi_aresetn] [get_bd_pins axis_avg_buffer_1/m_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axi_aresetn] [get_bd_pins axis_cc_avg_0/s_axis_aresetn] [get_bd_pins axis_cc_avg_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/s_axi_aresetn] [get_bd_pins axis_readout_v2_1/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_0/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_0/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_1/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_1/s_axi_aresetn] [get_bd_pins axis_switch_avg/aresetn] [get_bd_pins axis_switch_avg/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_buf/aresetn] [get_bd_pins axis_switch_buf/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_gen/aresetn] [get_bd_pins axis_switch_gen/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_readout/s_axi_ctrl_aresetn] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aresetn] [get_bd_pins mr_buffer_et_0/m00_axis_aresetn] [get_bd_pins mr_buffer_et_0/s00_axi_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/M02_ARESETN] [get_bd_pins ps8_0_axi_periph/M03_ARESETN] [get_bd_pins ps8_0_axi_periph/M04_ARESETN] [get_bd_pins ps8_0_axi_periph/M05_ARESETN] [get_bd_pins ps8_0_axi_periph/M06_ARESETN] [get_bd_pins ps8_0_axi_periph/M07_ARESETN] [get_bd_pins ps8_0_axi_periph/M08_ARESETN] [get_bd_pins ps8_0_axi_periph/M09_ARESETN] [get_bd_pins ps8_0_axi_periph/M10_ARESETN] [get_bd_pins ps8_0_axi_periph/M11_ARESETN] [get_bd_pins ps8_0_axi_periph/M12_ARESETN] [get_bd_pins ps8_0_axi_periph/M13_ARESETN] [get_bd_pins ps8_0_axi_periph/M14_ARESETN] [get_bd_pins ps8_0_axi_periph/M15_ARESETN] [get_bd_pins ps8_0_axi_periph/M16_ARESETN] [get_bd_pins ps8_0_axi_periph/M17_ARESETN] [get_bd_pins ps8_0_axi_periph/M18_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_100/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s_axi_aresetn] - connect_bd_net -net usp_rf_data_converter_0_clk_adc0 [get_bd_pins clk_adc0_x2/clk_in1] [get_bd_pins rst_adc0/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_adc0] - connect_bd_net -net usp_rf_data_converter_0_clk_dac0 [get_bd_pins axi_bram_ctrl_0_bram/clkb] [get_bd_pins axis_cc_avg_0/m_axis_aclk] [get_bd_pins axis_cc_avg_1/m_axis_aclk] [get_bd_pins axis_cc_sg_0/m_axis_aclk] [get_bd_pins axis_cc_sg_0/s_axis_aclk] [get_bd_pins axis_cc_sg_1/s_axis_aclk] [get_bd_pins axis_constant_0/m_axis_aclk] [get_bd_pins axis_constant_1/m_axis_aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_set_reg_0/s_axis_aclk] [get_bd_pins axis_signal_gen_v6_0/aclk] [get_bd_pins axis_tproc64x32_x8_0/aclk] [get_bd_pins rst_dac0/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_dac0] [get_bd_pins usp_rf_data_converter_0/s0_axis_aclk] - connect_bd_net -net usp_rf_data_converter_0_clk_dac2 [get_bd_pins axis_cc_sg_1/m_axis_aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins axis_signal_gen_v6_1/aclk] [get_bd_pins rst_dac1/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_dac2] [get_bd_pins usp_rf_data_converter_0/s2_axis_aclk] - connect_bd_net -net vect2bits_16_0_dout0 [get_bd_ports PMOD0_0] [get_bd_pins vect2bits_16_0/dout0] - connect_bd_net -net vect2bits_16_0_dout1 [get_bd_ports PMOD0_1] [get_bd_pins vect2bits_16_0/dout1] - connect_bd_net -net vect2bits_16_0_dout2 [get_bd_ports PMOD0_2] [get_bd_pins vect2bits_16_0/dout2] - connect_bd_net -net vect2bits_16_0_dout3 [get_bd_ports PMOD0_3] [get_bd_pins vect2bits_16_0/dout3] - connect_bd_net -net vect2bits_16_0_dout4 [get_bd_pins axis_avg_buffer_0/trigger] [get_bd_pins vect2bits_16_0/dout4] - connect_bd_net -net vect2bits_16_0_dout5 [get_bd_pins axis_avg_buffer_1/trigger] [get_bd_pins vect2bits_16_0/dout5] - connect_bd_net -net vect2bits_16_0_dout6 [get_bd_pins mr_buffer_et_0/trigger] [get_bd_pins vect2bits_16_0/dout6] - connect_bd_net -net xlconstant_0_dout [get_bd_pins axi_bram_ctrl_0_bram/dinb] [get_bd_pins xlconstant_0/dout] - connect_bd_net -net xlconstant_1_dout [get_bd_pins axi_bram_ctrl_0_bram/enb] [get_bd_pins axis_tproc64x32_x8_0/start] [get_bd_pins xlconstant_1/dout] - connect_bd_net -net xlconstant_2_dout [get_bd_pins axi_bram_ctrl_0_bram/rstb] [get_bd_pins xlconstant_2/dout] - connect_bd_net -net xlconstant_3_dout [get_bd_pins axi_bram_ctrl_0_bram/web] [get_bd_pins xlconstant_3/dout] - connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_dma_avg/m_axi_s2mm_aclk] [get_bd_pins axi_dma_avg/s_axi_lite_aclk] [get_bd_pins axi_dma_buf/m_axi_s2mm_aclk] [get_bd_pins axi_dma_buf/s_axi_lite_aclk] [get_bd_pins axi_dma_gen/m_axi_mm2s_aclk] [get_bd_pins axi_dma_gen/s_axi_lite_aclk] [get_bd_pins axi_dma_readout/m_axi_s2mm_aclk] [get_bd_pins axi_dma_readout/s_axi_lite_aclk] [get_bd_pins axi_dma_tproc/m_axi_mm2s_aclk] [get_bd_pins axi_dma_tproc/m_axi_s2mm_aclk] [get_bd_pins axi_dma_tproc/s_axi_lite_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins axis_avg_buffer_0/m_axis_aclk] [get_bd_pins axis_avg_buffer_0/s_axi_aclk] [get_bd_pins axis_avg_buffer_1/m_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axi_aclk] [get_bd_pins axis_cc_avg_0/s_axis_aclk] [get_bd_pins axis_cc_avg_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/s_axi_aclk] [get_bd_pins axis_readout_v2_1/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_0/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_0/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_1/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_1/s_axi_aclk] [get_bd_pins axis_switch_avg/aclk] [get_bd_pins axis_switch_avg/s_axi_ctrl_aclk] [get_bd_pins axis_switch_buf/aclk] [get_bd_pins axis_switch_buf/s_axi_ctrl_aclk] [get_bd_pins axis_switch_gen/aclk] [get_bd_pins axis_switch_gen/s_axi_ctrl_aclk] [get_bd_pins axis_switch_readout/s_axi_ctrl_aclk] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aclk] [get_bd_pins mr_buffer_et_0/m00_axis_aclk] [get_bd_pins mr_buffer_et_0/s00_axi_aclk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/M02_ACLK] [get_bd_pins ps8_0_axi_periph/M03_ACLK] [get_bd_pins ps8_0_axi_periph/M04_ACLK] [get_bd_pins ps8_0_axi_periph/M05_ACLK] [get_bd_pins ps8_0_axi_periph/M06_ACLK] [get_bd_pins ps8_0_axi_periph/M07_ACLK] [get_bd_pins ps8_0_axi_periph/M08_ACLK] [get_bd_pins ps8_0_axi_periph/M09_ACLK] [get_bd_pins ps8_0_axi_periph/M10_ACLK] [get_bd_pins ps8_0_axi_periph/M11_ACLK] [get_bd_pins ps8_0_axi_periph/M12_ACLK] [get_bd_pins ps8_0_axi_periph/M13_ACLK] [get_bd_pins ps8_0_axi_periph/M14_ACLK] [get_bd_pins ps8_0_axi_periph/M15_ACLK] [get_bd_pins ps8_0_axi_periph/M16_ACLK] [get_bd_pins ps8_0_axi_periph/M17_ACLK] [get_bd_pins ps8_0_axi_periph/M18_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_100/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/s_axi_aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihpc0_fpd_aclk] - connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_100/ext_reset_in] [get_bd_pins rst_adc0/ext_reset_in] [get_bd_pins rst_adc0_x2/ext_reset_in] [get_bd_pins rst_dac0/ext_reset_in] [get_bd_pins rst_dac1/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] - - # Create address segments - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_readout/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force - assign_bd_address -offset 0xA0140000 -range 0x00002000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_avg/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_buf/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0110000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_gen/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_readout/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA0130000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_tproc/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0xA00A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_1/s_axi/reg0] -force - assign_bd_address -offset 0xA0040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_1/s_axi/reg0] -force - assign_bd_address -offset 0xA00B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_1/s_axi/reg0] -force - assign_bd_address -offset 0xA0060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_avg/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0xA0070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_buf/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0xA0120000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_gen/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0xA0080000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_readout/S_AXI_CTRL/Reg] -force - assign_bd_address -offset 0x000400000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_tproc64x32_x8_0/s_axi/reg0] -force - assign_bd_address -offset 0xA0090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mr_buffer_et_0/s00_axi/reg0] -force - assign_bd_address -offset 0xA00C0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs usp_rf_data_converter_0/s_axi/Reg] -force - - # Exclude Address Segments - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_readout/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_readout/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] - exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] - - # Perform GUI Layout - regenerate_bd_layout -layout_string { - "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"0.530464", - "Default View_TopLeft":"-632,0", - "ExpandedHierarchyInLayout":"", - "guistr":"# # String gsaved with Nlview 7.0r4 2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS -# -string -flagsOSRD -preplace port adc0_clk -pg 1 -lvl 0 -x -10 -y 2500 -defaultsOSRD -preplace port dac0_clk -pg 1 -lvl 0 -x -10 -y 2520 -defaultsOSRD -preplace port dac2_clk -pg 1 -lvl 0 -x -10 -y 2540 -defaultsOSRD -preplace port sysref_in -pg 1 -lvl 0 -x -10 -y 2600 -defaultsOSRD -preplace port vin0_01 -pg 1 -lvl 0 -x -10 -y 2560 -defaultsOSRD -preplace port vin0_23 -pg 1 -lvl 0 -x -10 -y 2580 -defaultsOSRD -preplace port vout00 -pg 1 -lvl 11 -x 4610 -y 2620 -defaultsOSRD -preplace port vout20 -pg 1 -lvl 11 -x 4610 -y 2640 -defaultsOSRD -preplace port PMOD0_0 -pg 1 -lvl 11 -x 4610 -y 2660 -defaultsOSRD -preplace port PMOD0_1 -pg 1 -lvl 11 -x 4610 -y 2680 -defaultsOSRD -preplace port PMOD0_2 -pg 1 -lvl 11 -x 4610 -y 2700 -defaultsOSRD -preplace port PMOD0_3 -pg 1 -lvl 11 -x 4610 -y 2720 -defaultsOSRD -preplace inst axi_bram_ctrl_0 -pg 1 -lvl 1 -x 180 -y 2010 -defaultsOSRD -preplace inst axi_bram_ctrl_0_bram -pg 1 -lvl 2 -x 620 -y 2250 -defaultsOSRD -preplace inst axi_dma_avg -pg 1 -lvl 10 -x 4390 -y 1960 -defaultsOSRD -preplace inst axi_dma_buf -pg 1 -lvl 10 -x 4390 -y 2140 -defaultsOSRD -resize 320 156 -preplace inst axi_dma_gen -pg 1 -lvl 2 -x 620 -y 1290 -defaultsOSRD -preplace inst axi_dma_readout -pg 1 -lvl 10 -x 4390 -y 2320 -defaultsOSRD -resize 320 156 -preplace inst axi_dma_tproc -pg 1 -lvl 2 -x 620 -y 1520 -defaultsOSRD -preplace inst axi_smc -pg 1 -lvl 5 -x 1770 -y 1040 -defaultsOSRD -preplace inst axis_avg_buffer_0 -pg 1 -lvl 8 -x 3600 -y 1690 -defaultsOSRD -preplace inst axis_avg_buffer_1 -pg 1 -lvl 8 -x 3600 -y 2020 -defaultsOSRD -resize 220 236 -preplace inst axis_cc_avg_0 -pg 1 -lvl 9 -x 4010 -y 1560 -defaultsOSRD -preplace inst axis_cc_avg_1 -pg 1 -lvl 9 -x 4010 -y 1740 -defaultsOSRD -resize 220 156 -preplace inst axis_cc_sg_0 -pg 1 -lvl 3 -x 1040 -y 1620 -defaultsOSRD -preplace inst axis_cc_sg_1 -pg 1 -lvl 3 -x 1040 -y 1840 -defaultsOSRD -resize 220 156 -preplace inst axis_constant_0 -pg 1 -lvl 1 -x 180 -y 1730 -defaultsOSRD -preplace inst axis_constant_1 -pg 1 -lvl 1 -x 180 -y 1850 -defaultsOSRD -resize 220 96 -preplace inst axis_register_slice_2 -pg 1 -lvl 6 -x 2440 -y 1770 -defaultsOSRD -resize 180 116 -preplace inst axis_register_slice_3 -pg 1 -lvl 6 -x 2440 -y 2010 -defaultsOSRD -resize 180 116 -preplace inst axis_set_reg_0 -pg 1 -lvl 6 -x 2440 -y 2870 -defaultsOSRD -preplace inst axis_signal_gen_v6_0 -pg 1 -lvl 4 -x 1450 -y 2100 -defaultsOSRD -preplace inst axis_signal_gen_v6_1 -pg 1 -lvl 4 -x 1450 -y 2390 -defaultsOSRD -resize 220 236 -preplace inst axis_switch_avg -pg 1 -lvl 9 -x 4010 -y 1980 -defaultsOSRD -resize 240 196 -preplace inst axis_switch_buf -pg 1 -lvl 9 -x 4010 -y 2250 -defaultsOSRD -resize 240 196 -preplace inst axis_switch_gen -pg 1 -lvl 3 -x 1040 -y 1430 -defaultsOSRD -preplace inst axis_switch_readout -pg 1 -lvl 8 -x 3600 -y 2320 -defaultsOSRD -preplace inst axis_tproc64x32_x8_0 -pg 1 -lvl 2 -x 620 -y 1880 -defaultsOSRD -preplace inst clk_adc0_x2 -pg 1 -lvl 6 -x 2440 -y 690 -defaultsOSRD -preplace inst mr_buffer_et_0 -pg 1 -lvl 9 -x 4010 -y 2490 -defaultsOSRD -preplace inst ps8_0_axi_periph -pg 1 -lvl 7 -x 3110 -y 1090 -defaultsOSRD -preplace inst rst_100 -pg 1 -lvl 6 -x 2440 -y 290 -defaultsOSRD -preplace inst rst_adc0 -pg 1 -lvl 6 -x 2440 -y 490 -defaultsOSRD -preplace inst rst_adc0_x2 -pg 1 -lvl 6 -x 2440 -y 840 -defaultsOSRD -resize 320 156 -preplace inst rst_dac0 -pg 1 -lvl 6 -x 2440 -y 1060 -defaultsOSRD -resize 320 156 -preplace inst rst_dac1 -pg 1 -lvl 6 -x 2440 -y 1240 -defaultsOSRD -resize 320 156 -preplace inst usp_rf_data_converter_0 -pg 1 -lvl 6 -x 2440 -y 2560 -defaultsOSRD -preplace inst xlconstant_0 -pg 1 -lvl 1 -x 180 -y 2130 -defaultsOSRD -preplace inst xlconstant_1 -pg 1 -lvl 1 -x 180 -y 2240 -defaultsOSRD -resize 140 88 -preplace inst xlconstant_2 -pg 1 -lvl 1 -x 180 -y 2350 -defaultsOSRD -resize 140 88 -preplace inst xlconstant_3 -pg 1 -lvl 1 -x 180 -y 2460 -defaultsOSRD -resize 140 88 -preplace inst zynq_ultra_ps_e_0 -pg 1 -lvl 6 -x 2440 -y 110 -defaultsOSRD -preplace inst axis_register_slice_0 -pg 1 -lvl 5 -x 1770 -y 2120 -defaultsOSRD -preplace inst axis_register_slice_1 -pg 1 -lvl 5 -x 1770 -y 2440 -defaultsOSRD -preplace inst vect2bits_16_0 -pg 1 -lvl 7 -x 3110 -y 2810 -defaultsOSRD -preplace inst axis_readout_v2_0 -pg 1 -lvl 7 -x 3110 -y 1730 -defaultsOSRD -preplace inst axis_readout_v2_1 -pg 1 -lvl 7 -x 3110 -y 2050 -defaultsOSRD -resize 200 176 -preplace netloc axi_bram_ctrl_0_bram_doutb 1 1 1 400 2030n -preplace netloc axis_set_reg_0_dout 1 6 1 2790 2810n -preplace netloc axis_tproc64x32_x8_0_pmem_addr 1 1 2 420 2110 800 -preplace netloc clk_adc0_x2_clk_out1 1 5 4 2050 950 2830 1880 3440 2440 3740 -preplace netloc clk_adc0_x2_locked 1 5 2 2080 940 2760 -preplace netloc rst_adc0_peripheral_aresetn 1 5 2 2080 610 2760 -preplace netloc rst_adc0_x2_peripheral_aresetn 1 5 4 2060 1870 2800 1890 3450 2530 N -preplace netloc rst_dac0_peripheral_aresetn 1 0 9 10 1640 360 1640 840 1740 1220 1940 1590J 2200 1940J 2200 2810 1870 N 1870 3770 -preplace netloc rst_dac1_peripheral_aresetn 1 2 5 860 2470 1280 2560 1620J 2560 1920J 2330 2770 -preplace netloc rst_ps8_0_99M_peripheral_aresetn 1 0 10 30 1920 370 1380 840 1320 1230 1320 1580 1170 1960 1340 2860 1900 3420 1840 3830J 2120 4170 -preplace netloc usp_rf_data_converter_0_clk_adc0 1 5 2 2070 620 2780 -preplace netloc usp_rf_data_converter_0_clk_dac0 1 0 9 40 1660 340 1660 850 1960 1270 1960 1620 1960 1970 2210 2870 2180 3380 1830 3780 -preplace netloc usp_rf_data_converter_0_clk_dac2 1 2 5 870 2450 1240 2590 1590 2360 2000 2340 2770 -preplace netloc vect2bits_16_0_dout0 1 7 4 N 2660 NJ 2660 NJ 2660 NJ -preplace netloc vect2bits_16_0_dout1 1 7 4 N 2680 NJ 2680 NJ 2680 NJ -preplace netloc vect2bits_16_0_dout2 1 7 4 N 2700 NJ 2700 NJ 2700 NJ -preplace netloc vect2bits_16_0_dout3 1 7 4 N 2720 NJ 2720 NJ 2720 NJ -preplace netloc vect2bits_16_0_dout4 1 7 1 3370 1690n -preplace netloc vect2bits_16_0_dout5 1 7 1 3430 2020n -preplace netloc vect2bits_16_0_dout6 1 7 2 3460 2450 NJ -preplace netloc xlconstant_0_dout 1 1 1 320 2130n -preplace netloc xlconstant_1_dout 1 1 1 380 2010n -preplace netloc xlconstant_2_dout 1 1 1 350 2310n -preplace netloc xlconstant_3_dout 1 1 1 410 2330n -preplace netloc zynq_ultra_ps_e_0_pl_clk0 1 0 10 40 1930 330 1200 860 1200 1250 1090 1580 910 2020 1350 2790 1620 3410 1540 3760J 2130 4200 -preplace netloc zynq_ultra_ps_e_0_pl_resetn0 1 5 2 2060 600 2780 -preplace netloc adc0_clk_1 1 0 6 40 2530 N 2530 N 2530 N 2530 N 2530 1950 -preplace netloc axis_avg_buffer_1_m2_axis 1 8 1 3810 1700n -preplace netloc axi_dma_readout_M_AXI_S2MM 1 4 7 1620J 1180 2010 1560 2850J 1850 3340J 1860 NJ 1860 NJ 1860 4580 -preplace netloc axi_dma_tproc_M_AXI_MM2S 1 2 3 820 1050 NJ 1050 N -preplace netloc axi_dma_gen_M_AXIS_MM2S 1 2 1 850 1280n -preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 1 1 330 2010n -preplace netloc axi_dma_buf_M_AXI_S2MM 1 4 7 1610J 1190 1980 1570 NJ 1570 3320J 1550 3850J 1840 NJ 1840 4590 -preplace netloc axi_dma_tproc_M_AXI_S2MM 1 2 3 830 1070 NJ 1070 N -preplace netloc axi_smc_M00_AXI 1 5 1 1960 70n -preplace netloc axi_dma_tproc_M_AXIS_MM2S 1 1 2 390 1390 810 -preplace netloc axi_dma_gen_M_AXI_MM2S 1 2 3 800 1030 N 1030 N -preplace netloc axi_dma_avg_M_AXI_S2MM 1 4 7 1590 1600 N 1600 N 1600 3360 1850 N 1850 N 1850 4570 -preplace netloc ps8_0_axi_periph_M07_AXI 1 7 2 3410 1520 3740 -preplace netloc ps8_0_axi_periph_M05_AXI 1 6 2 2880 600 3270J -preplace netloc axis_tproc64x32_x8_0_m8_axis 1 2 4 NJ 1950 NJ 1950 NJ 1950 1910 -preplace netloc axis_switch_avg_M00_AXIS 1 9 1 4170 1940n -preplace netloc ps8_0_axi_periph_M00_AXI 1 7 3 3460 1430 3860 1440 4200J -preplace netloc ps8_0_axi_periph_M06_AXI 1 7 2 3420 1510 3860 -preplace netloc axis_register_slice_4_m_axis 1 5 1 NJ 2440 -preplace netloc axis_register_slice_6_m_axis 1 5 1 1950 2120n -preplace netloc axis_signal_gen_v6_1_m_axis 1 4 1 1580 2390n -preplace netloc sysref_in_1 1 0 6 NJ 2600 NJ 2600 NJ 2600 NJ 2600 NJ 2600 1930 -preplace netloc usp_rf_data_converter_0_m02_axis 1 5 2 2080 1930 2750 -preplace netloc ps8_0_axi_periph_M17_AXI 1 1 7 380 390 NJ 390 NJ 390 NJ 390 NJ 390 NJ 390 3320 -preplace netloc ps8_0_axi_periph_M13_AXI 1 3 5 1290 1610 NJ 1610 NJ 1610 NJ 1610 3280 -preplace netloc ps8_0_axi_periph_M11_AXI 1 5 3 2070 1860 NJ 1860 3300J -preplace netloc ps8_0_axi_periph_M15_AXI 1 1 7 390 590 N 590 N 590 NJ 590 NJ 590 NJ 590 3290 -preplace netloc usp_rf_data_converter_0_vout20 1 6 5 N 2550 3270 2640 N 2640 N 2640 N -preplace netloc vin0_23_1 1 0 6 N 2580 N 2580 N 2580 N 2580 1610 2550 2040 -preplace netloc ps8_0_axi_periph_M09_AXI 1 1 7 400 1670 810 1730 N 1730 NJ 1730 1910 1850 2840J 1840 3310J -preplace netloc ps8_0_axi_periph_M08_AXI 1 7 1 3350 1070n -preplace netloc usp_rf_data_converter_0_vout00 1 6 5 N 2530 3270 2540 3740 2630 4180 2620 N -preplace netloc vin0_01_1 1 0 6 N 2560 N 2560 N 2560 1190 2570 N 2570 2030 -preplace netloc ps8_0_axi_periph_M12_AXI 1 7 1 3370 1150n -preplace netloc ps8_0_axi_periph_M10_AXI 1 7 2 3380 1530 3800 -preplace netloc ps8_0_axi_periph_M14_AXI 1 3 5 1280 1580 NJ 1580 NJ 1580 NJ 1580 3270 -preplace netloc ps8_0_axi_periph_M18_AXI 1 0 8 20 1650 NJ 1650 820J 1720 1220J 1590 NJ 1590 NJ 1590 NJ 1590 3260 -preplace netloc zynq_ultra_ps_e_0_M_AXI_HPM0_FPD 1 6 1 2870J 80n -preplace netloc ps8_0_axi_periph_M16_AXI 1 2 6 870 10 N 10 N 10 NJ 10 NJ 10 3330 -preplace netloc usp_rf_data_converter_0_m00_axis 1 5 2 2080 1690 2760 -preplace netloc axis_signal_gen_v6_0_m_axis 1 4 1 N 2100 -preplace netloc axis_avg_buffer_0_m2_axis 1 8 1 3750 1520n -preplace netloc axis_readout_v2_0_m0_axis 1 7 1 3330 1720n -preplace netloc axis_register_slice_2_M_AXIS 1 6 1 2820 1680n -preplace netloc axis_switch_buf_M00_AXIS 1 9 1 4190 2120n -preplace netloc axis_switch_gen_M01_AXIS 1 3 1 1210 1440n -preplace netloc axis_constant_0_m_axis 1 1 1 350 1730n -preplace netloc axis_avg_buffer_1_m0_axis 1 8 1 3820 1940n -preplace netloc axis_avg_buffer_1_m1_axis 1 8 1 3750 2020n -preplace netloc axis_switch_gen_M00_AXIS 1 3 1 1260 1420n -preplace netloc dac0_clk_1 1 0 6 30 2540 N 2540 N 2540 N 2540 N 2540 1990 -preplace netloc mr_buffer_et_0_m00_axis 1 9 1 4210 2300n -preplace netloc axis_cc_sg_0_M_AXIS 1 3 1 1240 1620n -preplace netloc axis_avg_buffer_0_m1_axis 1 8 1 3790 1690n -preplace netloc axis_readout_v2_1_m1_axis 1 7 1 3390 1940n -preplace netloc ps8_0_axi_periph_M01_AXI 1 7 3 3450 1450 N 1450 4190J -preplace netloc ps8_0_axi_periph_M03_AXI 1 7 1 3400 970n -preplace netloc dac2_clk_1 1 0 6 10 2550 N 2550 N 2550 N 2550 1600 2520 1980 -preplace netloc axis_switch_0_M00_AXIS 1 8 1 3740 2320n -preplace netloc axis_tproc64x32_x8_0_m0_axis 1 1 2 400 1400 800 -preplace netloc axis_tproc64x32_x8_0_m1_axis 1 2 1 830 1580n -preplace netloc axis_tproc64x32_x8_0_m2_axis 1 2 1 870 1800n -preplace netloc axis_avg_buffer_0_m0_axis 1 8 1 3840 1670n -preplace netloc axis_constant_1_m_axis 1 1 1 320 1810n -preplace netloc axis_cc_sg_1_M_AXIS 1 3 1 1190 1840n -preplace netloc axis_cc_avg_1_M_AXIS 1 1 9 420 2100 N 2100 1180 2250 NJ 2250 1930 2170 NJ 2170 NJ 2170 3860J 2110 4150 -preplace netloc axis_readout_v2_0_m1_axis 1 7 1 3320 1610n -preplace netloc ps8_0_axi_periph_M04_AXI 1 6 2 2890 610 3260J -preplace netloc axis_register_slice_3_M_AXIS 1 6 1 2840 2000n -preplace netloc ps8_0_axi_periph_M02_AXI 1 7 3 3440 1460 N 1460 4180J -preplace netloc axis_readout_v2_1_m0_axis 1 7 1 3260 2040n -preplace netloc axis_cc_avg_0_M_AXIS 1 1 9 410 2090 N 2090 1200 2240 NJ 2240 1920 2160 NJ 2160 NJ 2160 3850J 2100 4160 -levelinfo -pg 1 -10 180 620 1040 1450 1770 2440 3110 3600 4010 4390 4610 -pagesize -pg 1 -db -bbox -sgen -130 0 4730 3020 -" -} - - # Restore current instance - current_bd_instance $oldCurInst - - validate_bd_design - save_bd_design -} -# End of create_root_design() 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/firmware/common_clock/timing_4x2.xdc b/firmware/common_clock/timing_4x2.xdc deleted file mode 100644 index b637544..0000000 --- a/firmware/common_clock/timing_4x2.xdc +++ /dev/null @@ -1,34 +0,0 @@ -set clk_axi [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/zynq_ultra_ps_e_0/pl_clk0]]] -set clk_adc0 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_adc0]]] -set clk_dac0 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac0]]] -set clk_dac2 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/usp_rf_data_converter_0/clk_dac2]]] -set clk_adc0_x2 [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/clk_adc0_x2/clk_out1]]] -#set clk_tproc [get_clocks -of_objects [get_nets -of_objects [get_pins d_1_i/clk_tproc/clk_out1]]] - -set_clock_group -name clk_axi_to_adc0_x2 -asynchronous \ - -group [get_clocks $clk_axi] \ - -group [get_clocks $clk_adc0_x2] - -set_clock_group -name clk_axi_to_dac0 -asynchronous \ - -group [get_clocks $clk_axi] \ - -group [get_clocks $clk_dac0] - -set_clock_group -name clk_axi_to_dac2 -asynchronous \ - -group [get_clocks $clk_axi] \ - -group [get_clocks $clk_dac2] - -#set_clock_group -name clk_axi_to_tproc -asynchronous \ -# -group [get_clocks $clk_axi] \ -# -group [get_clocks $clk_tproc] - -#set_clock_group -name clk_tproc_to_dac0 -asynchronous \ -# -group [get_clocks $clk_tproc] \ -# -group [get_clocks $clk_dac0] - -set_clock_group -name clk_tproc_to_dac2 -asynchronous \ - -group [get_clocks $clk_dac0] \ - -group [get_clocks $clk_dac2] - -set_clock_group -name clk_tproc_to_adc0_x2 -asynchronous \ - -group [get_clocks $clk_dac0] \ - -group [get_clocks $clk_adc0_x2] \ No newline at end of file diff --git a/firmware/ip/README.md b/firmware/ip/README.md new file mode 100644 index 0000000..523b577 --- /dev/null +++ b/firmware/ip/README.md @@ -0,0 +1,2 @@ +# ip +Various ip blocks for ASIC/FPGA. diff --git a/firmware/ip/axis_avg_buffer/component.xml b/firmware/ip/axis_avg_buffer/component.xml new file mode 100644 index 0000000..db7a965 --- /dev/null +++ b/firmware/ip/axis_avg_buffer/component.xml @@ -0,0 +1,1493 @@ + + + user.org + user + axis_avg_buffer + 1.1 + + + m0_axis + + + + + + + TDATA + + + m0_axis_tdata + + + + + TLAST + + + m0_axis_tlast + + + + + TVALID + + + m0_axis_tvalid + + + + + TREADY + + + m0_axis_tready + + + + + + m1_axis + + + + + + + TDATA + + + m1_axis_tdata + + + + + TLAST + + + m1_axis_tlast + + + + + TVALID + + + m1_axis_tvalid + + + + + TREADY + + + m1_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axis_aclk + + + + + + + CLK + + + s_axis_aclk + + + + + + ASSOCIATED_BUSIF + s_axis + + + ASSOCIATED_RESET + s_axis_aresetn + + + + + s_axis_aresetn + + + + + + + RST + + + s_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m_axis_aclk + + + + + + + CLK + + + m_axis_aclk + + + + + + ASSOCIATED_RESET + m_axis_aresetn + + + ASSOCIATED_BUSIF + m0_axis:m1_axis:m2_axis + + + + + m_axis_aresetn + + + + + + + RST + + + m_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m2_axis + + + + + + + TDATA + + + m2_axis_tdata + + + + + TVALID + + + m2_axis_tvalid + + + + + TREADY + + + m2_axis_tready + + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_avg_buffer + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 46ab5641 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_avg_buffer + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 46ab5641 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 330b59e5 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + trigger + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m0_axis_tdata + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m1_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m2_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m2_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m2_axis_tdata + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N_AVG + N Avg + 10 + + + N_BUF + N Buf + 10 + + + B + B + 16 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/avg_buffer.v + verilogSource + + + src/avg_top.v + verilogSource + + + src/buffer_top.v + verilogSource + + + src/avg.sv + systemVerilogSource + + + src/buffer.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bin2gray.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/data_reader.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/fifo/fifo_dc.vhd + vhdlSource + + + src/fifo/fifo_dc_axi.vhd + vhdlSource + + + src/fifo/gray2bin.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/fifo/synchronizer_vect.vhd + vhdlSource + + + src/axis_avg_buffer.v + verilogSource + CHECKSUM_067dce18 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/avg_buffer.v + verilogSource + + + src/avg_top.v + verilogSource + + + src/buffer_top.v + verilogSource + + + src/avg.sv + systemVerilogSource + + + src/buffer.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bin2gray.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/data_reader.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/fifo/fifo_dc.vhd + vhdlSource + + + src/fifo/fifo_dc_axi.vhd + vhdlSource + + + src/fifo/gray2bin.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/fifo/synchronizer_vect.vhd + vhdlSource + + + src/axis_avg_buffer.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_avg_buffer_v1_1.tcl + tclSource + CHECKSUM_330b59e5 + XGUI_VERSION_2 + + + + AXIS Average + Buffer block with external trigger. + + + N_AVG + N Avg + 10 + + + N_BUF + N Buf + 10 + + + B + B + 16 + + + Component_Name + axis_avg_buffer_v1_0 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + kintexuplus + kintexu + + + /UserIP + + AXIS Average + Buffer + package_project + 2 + + user.org:user:axis_avg_buffer:1.0 + + 2023-11-30T19:05:34Z + + /home/lstefana/v19.1/ip/axis_avg_buffer + /home/lstefana/v19.1/ip/axis_avg_buffer + /home/lstefana/v19.1/ip/axis_avg_buffer + /home/lstefana/v19.1/ip/axis_avg_buffer + /home/lstefana/v19.1/ip/axis_avg_buffer + /home/lstefana/v19.1/ip/axis_avg_buffer + /home/lstefana/v19.1/ip/axis_avg_buffer + /home/lstefana/v19.1/ip/axis_avg_buffer + /home/lstefana/v19.1/ip/axis_avg_buffer + /home/lstefana/v19.1/ip/axis_avg_buffer + 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c:/Users/rcdansr/Documents/FPGA_work/firmware/ip/axis_avg_buffer + c:/Users/rcdansr/Documents/FPGA_work/firmware/ip/axis_avg_buffer + c:/Users/rcdansr/Documents/FPGA_work/firmware/ip/axis_avg_buffer + c:/Users/rcdansr/Documents/FPGA_work/firmware/ip/axis_avg_buffer + c:/Users/rcdansr/Documents/FPGA_work/firmware/ip/axis_avg_buffer + c:/Users/rcdansr/Documents/FPGA_work/firmware/ip/axis_avg_buffer + c:/Users/rcdansr/Documents/FPGA_work/firmware/ip/axis_avg_buffer + c:/Users/rcdansr/Documents/FPGA_work/firmware/ip/axis_avg_buffer + c:/Users/rcdansr/Documents/FPGA_work/firmware/ip/axis_avg_buffer + c:/Users/rcdansr/Documents/FPGA_work/firmware/ip/axis_avg_buffer + c:/Users/rcdansr/Documents/FPGA_work/firmware/ip/axis_avg_buffer + c:/Users/rcdansr/Documents/FPGA_work/firmware/ip/axis_avg_buffer + c:/Users/rcdansr/Documents/FPGA_work/firmware/ip/axis_avg_buffer + + + + 2020.2 + + + + + + + + + diff --git a/firmware/ip/axis_avg_buffer/src/avg.sv b/firmware/ip/axis_avg_buffer/src/avg.sv new file mode 100644 index 0000000..f4e5b6a --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/avg.sv @@ -0,0 +1,276 @@ +// Data is I,Q. +// I: lower B bits. +// Q: upper B bits. +module avg ( + // Reset and clock. + rstn , + clk , + + // Trigger input. + trigger_i , + + // Data input. + din_i , + + // Memory interface. + mem_we_o , + mem_addr_o , + mem_di_o , + + // Registers. + START_REG , + ADDR_REG , + LEN_REG , + PHOTON_MODE_REG, + H_THRSH_REG , + L_THRSH_REG + ); + +//////////////// +// Parameters // +//////////////// +// Memory depth. +parameter N = 10; + +// Number of bits. +parameter B = 16; + +/////////// +// Ports // +/////////// +input rstn; +input clk; + +input trigger_i; + +input [2*B-1:0] din_i; + +output mem_we_o; +output [N-1:0] mem_addr_o; +output [4*B-1:0] mem_di_o; + +input START_REG; +input [N-1:0] ADDR_REG; +input [31:0] LEN_REG; +input PHOTON_MODE_REG; +input [B-1:0] H_THRSH_REG; +input [B-1:0] L_THRSH_REG; + +////////////////////// +// Internal signals // +////////////////////// +// States. +typedef enum { INIT_ST , + START_ST , + TRIGGER_ST , + AVG_ST , + QOUT_ST , + WRITE_MEM_ST , + WAIT_TRIGGER_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +reg start_state; +reg trigger_state; +reg avg_state; +reg qout_state; +reg write_mem_state; + +// Edge counter states. +reg high_state; +reg high_state_reg; + +// Counter. +reg [31:0] cnt; + +// Registers. +reg [N-1:0] addr_r; +reg [31:0] len_r; +reg [2*B-1:0] din_r; +reg photon_mode_r; +reg signed [B-1:0] h_thrsh_r; +reg signed [B-1:0] l_thrsh_r; + +// Input data. +wire signed [B-1:0] din_ii, din_qq; + +// Accumulators. +reg signed [2*B-1:0] acc_i, acc_q; +reg [4*B-1:0] acc_photon; + +// Quantized outputs. +reg signed [2*B-1:0] out_i_r, out_q_r; +reg [4*B-1:0] out_result_r; + + +////////////////// +// Architecture // +////////////////// + +assign din_ii = $signed(din_i[B-1:0]); +assign din_qq = $signed(din_i[2*B-1:B]); + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= INIT_ST; + + // Counter. + cnt <= 0; + + // Registers. + addr_r <= 0; + len_r <= 0; + din_r <= 0; + photon_mode_r <= 1'b0; + h_thrsh_r <= 0; + l_thrsh_r <= 0; + high_state <= 1'b0; + high_state_reg <= 1'b0; + + // Accumulators. + acc_i <= 0; + acc_q <= 0; + acc_photon <= 0; + + // Quantized outputs. + out_i_r <= 0; + out_q_r <= 0; + out_result_r <= 0; + + end + else begin + // State register. + case (state) + INIT_ST: + state <= START_ST; + + START_ST: + if ( START_REG == 1'b1) + state <= TRIGGER_ST; + + TRIGGER_ST: + if ( START_REG == 1'b0 ) + state <= START_ST; + else if ( trigger_i == 1'b1 ) + state <= AVG_ST; + + AVG_ST: + if ( cnt == len_r-1 ) + state <= QOUT_ST; + + QOUT_ST: + state <= WRITE_MEM_ST; + + WRITE_MEM_ST: + state <= WAIT_TRIGGER_ST; + + WAIT_TRIGGER_ST: + if ( START_REG == 1'b0 ) + state <= START_ST; + else if ( trigger_i == 1'b0 ) begin + state <= TRIGGER_ST; + end + endcase + + // Counter. + if ( avg_state == 1'b1 ) + cnt <= cnt + 1; + else + cnt <= 0; + + // Registers. + if ( start_state == 1'b1 ) begin + addr_r <= ADDR_REG; + len_r <= LEN_REG; + photon_mode_r <= PHOTON_MODE_REG; + h_thrsh_r <= $signed(H_THRSH_REG); + l_thrsh_r <= $signed(L_THRSH_REG); + end + else if ( write_mem_state == 1'b1 ) begin + addr_r <= addr_r + 1; + end + + // Accumulators. + if ( trigger_state == 1'b1 ) begin + acc_i <= 0; + acc_q <= 0; + acc_photon <= 0; + if (din_ii > h_thrsh_r) begin + high_state <= 1'b1; + high_state_reg <= 1'b1; + end + else begin + high_state <= 1'b0; + high_state_reg <= 1'b0; + end + end + else if ( avg_state == 1'b1 ) begin + // Accumulator counter. + if ( photon_mode_r == 1'b0 ) begin + acc_i <= acc_i + din_ii; + acc_q <= acc_q + din_qq; + end + // Rising edge counter. + else if ( high_state == 1'b1 && high_state_reg == 1'b0) + acc_photon <= acc_photon + 1; + // Edge counter detect. + high_state_reg <= high_state; + if ( din_ii > h_thrsh_r ) + high_state <= 1'b1; + else if ( din_ii < l_thrsh_r ) + high_state <= 1'b0; + end + + + // Quantized outputs. + if ( qout_state == 1'b1 ) begin + if ( photon_mode_r == 1'b0 ) + out_result_r <= {acc_q,acc_i}; + else + out_result_r <= acc_photon; + end + end +end + +// FSM outputs. +always_comb begin + // Default. + start_state = 0; + trigger_state = 0; + avg_state = 0; + qout_state = 0; + write_mem_state = 0; + + case (state) + //INIT_ST: + + START_ST: + start_state = 1'b1; + + TRIGGER_ST: + trigger_state = 1'b1; + + AVG_ST: + avg_state = 1'b1; + + QOUT_ST: + qout_state = 1'b1; + + WRITE_MEM_ST: + write_mem_state = 1'b1; + + //WAIT_TRIGGER_ST: + endcase +end + +// Assign outputs. +assign mem_we_o = write_mem_state; +assign mem_addr_o = addr_r; +assign mem_di_o = out_result_r; //{out_q_r,out_i_r}; + +endmodule + diff --git a/firmware/ip/axis_avg_buffer/src/avg_buffer.v b/firmware/ip/axis_avg_buffer/src/avg_buffer.v new file mode 100644 index 0000000..ba93b51 --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/avg_buffer.v @@ -0,0 +1,217 @@ +// Data is I,Q. +// I: lower B bits. +// Q: upper B bits. +module avg_buffer ( + // Reset and clock for s. + s_axis_aclk , + s_axis_aresetn , + + // Trigger input. + trigger , + + // AXIS Slave for input data. + s_axis_tvalid , + s_axis_tready , + s_axis_tdata , + + // Reset and clock for m0, m1 and m2. + m_axis_aclk , + m_axis_aresetn , + + // AXIS Master for averaged output. + m0_axis_tvalid , + m0_axis_tready , + m0_axis_tdata , + m0_axis_tlast , + + // AXIS Master for raw output. + m1_axis_tvalid , + m1_axis_tready , + m1_axis_tdata , + m1_axis_tlast , + + // AXIS Master for register output. + m2_axis_tvalid , + m2_axis_tready , + m2_axis_tdata , + + // Registers. + AVG_START_REG , + AVG_ADDR_REG , + AVG_LEN_REG , + AVG_PHOTON_MODE_REG , + AVG_H_THRSH_REG , + AVG_L_THRSH_REG , + AVG_DR_START_REG , + AVG_DR_ADDR_REG , + AVG_DR_LEN_REG , + BUF_START_REG , + BUF_ADDR_REG , + BUF_LEN_REG , + BUF_DR_START_REG , + BUF_DR_ADDR_REG , + BUF_DR_LEN_REG + ); + +//////////////// +// Parameters // +//////////////// +// Memory depth. +parameter N_AVG = 10; +parameter N_BUF = 10; + +// Number of bits. +parameter B = 16; + +/////////// +// Ports // +/////////// +input s_axis_aclk; +input s_axis_aresetn; + +input trigger; + +input s_axis_tvalid; +output s_axis_tready; +input [2*B-1:0] s_axis_tdata; + +input m_axis_aclk; +input m_axis_aresetn; + +output m0_axis_tvalid; +input m0_axis_tready; +output [4*B-1:0] m0_axis_tdata; +output m0_axis_tlast; + +output m1_axis_tvalid; +input m1_axis_tready; +output [2*B-1:0] m1_axis_tdata; +output m1_axis_tlast; + +output m2_axis_tvalid; +input m2_axis_tready; +output [4*B-1:0] m2_axis_tdata; + +input AVG_START_REG; +input [N_AVG-1:0] AVG_ADDR_REG; +input [31:0] AVG_LEN_REG; +input AVG_PHOTON_MODE_REG; +input [B-1:0] AVG_H_THRSH_REG; +input [B-1:0] AVG_L_THRSH_REG; +input AVG_DR_START_REG; +input [N_AVG-1:0] AVG_DR_ADDR_REG; +input [N_AVG-1:0] AVG_DR_LEN_REG; +input BUF_START_REG; +input [N_BUF-1:0] BUF_ADDR_REG; +input [N_BUF-1:0] BUF_LEN_REG; +input BUF_DR_START_REG; +input [N_BUF-1:0] BUF_DR_ADDR_REG; +input [N_BUF-1:0] BUF_DR_LEN_REG; + +////////////////////// +// Internal signals // +////////////////////// + +wire trigger_resync; + +////////////////// +// Architecture // +////////////////// + +// trigger_resync +synchronizer_n + #( + .N (2) + ) + trigger_resync_i ( + .rstn (s_axis_aresetn ), + .clk (s_axis_aclk ), + .data_in (trigger ), + .data_out (trigger_resync ) + ); + +// Average block. +avg_top + #( + .N (N_AVG ), + .B (B ) + ) + avg_top_i + ( + // Reset and clock. + .rstn (s_axis_aresetn ), + .clk (s_axis_aclk ), + + // Trigger input. + .trigger_i (trigger_resync ), + + // Data input. + .din_i (s_axis_tdata ), + + // Reset and clock for M_AXIS_* + .m_axis_aclk (m_axis_aclk ), + .m_axis_aresetn (m_axis_aresetn ), + + // AXIS Master for output. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tready (m0_axis_tready ), + .m0_axis_tdata (m0_axis_tdata ), + .m0_axis_tlast (m0_axis_tlast ), + + // AXIS Master for register output. + .m1_axis_tvalid (m2_axis_tvalid ), + .m1_axis_tready (m2_axis_tready ), + .m1_axis_tdata (m2_axis_tdata ), + + // Registers. + .AVG_START_REG (AVG_START_REG ), + .AVG_ADDR_REG (AVG_ADDR_REG ), + .AVG_LEN_REG (AVG_LEN_REG ), + .DR_START_REG (AVG_DR_START_REG ), + .DR_ADDR_REG (AVG_DR_ADDR_REG ), + .DR_LEN_REG (AVG_DR_LEN_REG ), + .AVG_PHOTON_MODE_REG (AVG_PHOTON_MODE_REG), + .AVG_H_THRSH_REG (AVG_H_THRSH_REG ), + .AVG_L_THRSH_REG (AVG_L_THRSH_REG ) + ); + +// Buffer block. +buffer_top + #( + .N (N_BUF ), + .B (B ) + ) + buffer_top_i + ( + // Reset and clock. + .rstn (s_axis_aresetn ), + .clk (s_axis_aclk ), + + // Trigger input. + .trigger_i (trigger_resync ), + + // Data input. + .din_i (s_axis_tdata ), + + // AXIS Master for output. + .m_axis_aclk (m_axis_aclk ), + .m_axis_aresetn (m_axis_aresetn ), + .m_axis_tvalid (m1_axis_tvalid ), + .m_axis_tready (m1_axis_tready ), + .m_axis_tdata (m1_axis_tdata ), + .m_axis_tlast (m1_axis_tlast ), + + // Registers. + .BUF_START_REG (BUF_START_REG ), + .BUF_ADDR_REG (BUF_ADDR_REG ), + .BUF_LEN_REG (BUF_LEN_REG ), + .DR_START_REG (BUF_DR_START_REG ), + .DR_ADDR_REG (BUF_DR_ADDR_REG ), + .DR_LEN_REG (BUF_DR_LEN_REG ) + ); + +// Assign outputs. +assign s_axis_tready = 1'b1; + +endmodule + diff --git a/firmware/ip/axis_avg_buffer/src/avg_top.v b/firmware/ip/axis_avg_buffer/src/avg_top.v new file mode 100644 index 0000000..ebf4677 --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/avg_top.v @@ -0,0 +1,238 @@ +module avg_top ( + // Reset and clock. + rstn , + clk , + + // Trigger input. + trigger_i , + + // Data input. + din_i , + + // Reset and clock for M_AXIS_* + m_axis_aclk , + m_axis_aresetn , + + // AXIS Master for output. + m0_axis_tvalid , + m0_axis_tready , + m0_axis_tdata , + m0_axis_tlast , + + // AXIS Master for register output. + m1_axis_tvalid , + m1_axis_tready , + m1_axis_tdata , + + // Registers. + AVG_START_REG , + AVG_ADDR_REG , + AVG_LEN_REG , + DR_START_REG , + DR_ADDR_REG , + DR_LEN_REG , + AVG_PHOTON_MODE_REG , + AVG_H_THRSH_REG , + AVG_L_THRSH_REG + ); + +//////////////// +// Parameters // +//////////////// +// Memory depth. +parameter N = 10; + +// Number of bits. +parameter B = 16; + +/////////// +// Ports // +/////////// +input rstn; +input clk; + +input trigger_i; + +input [2*B-1:0] din_i; + +input m_axis_aclk; +input m_axis_aresetn; + +output m0_axis_tvalid; +input m0_axis_tready; +output [4*B-1:0] m0_axis_tdata; +output m0_axis_tlast; + +output m1_axis_tvalid; +input m1_axis_tready; +output [4*B-1:0] m1_axis_tdata; + +input AVG_START_REG; +input [N-1:0] AVG_ADDR_REG; +input [31:0] AVG_LEN_REG; +input DR_START_REG; +input [N-1:0] DR_ADDR_REG; +input [N-1:0] DR_LEN_REG; +input AVG_PHOTON_MODE_REG; +input [B-1:0] AVG_H_THRSH_REG; +input [B-1:0] AVG_L_THRSH_REG; + +////////////////////// +// Internal signals // +////////////////////// +wire mem_we_int; +wire [N-1:0] mem_addra_int, mem_addrb_int; +wire [4*B-1:0] mem_di_int, mem_do_int; + +wire AVG_START_REG_resync; +wire DR_START_REG_resync; + +wire fifo_empty; + +////////////////// +// Architecture // +////////////////// + +// AVG_START_REG_resync +synchronizer_n + #( + .N (2) + ) + AVG_START_REG_resync_i ( + .rstn (rstn ), + .clk (clk ), + .data_in (AVG_START_REG ), + .data_out (AVG_START_REG_resync ) + ); + +// DR_START_REG_resync +synchronizer_n + #( + .N (2) + ) + DR_START_REG_resync_i ( + .rstn (m_axis_aresetn ), + .clk (m_axis_aclk ), + .data_in (DR_START_REG ), + .data_out (DR_START_REG_resync ) + ); + +// Average block. +avg + #( + .N (N), + .B (B) + ) + avg_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Trigger input. + .trigger_i (trigger_i ), + + // Data input. + .din_i (din_i ), + + // Memory interface. + .mem_we_o (mem_we_int ), + .mem_addr_o (mem_addra_int ), + .mem_di_o (mem_di_int ), + + // Registers. + .START_REG (AVG_START_REG_resync ), + .ADDR_REG (AVG_ADDR_REG ), + .LEN_REG (AVG_LEN_REG ), + .PHOTON_MODE_REG (AVG_PHOTON_MODE_REG), + .H_THRSH_REG (AVG_H_THRSH_REG ), + .L_THRSH_REG (AVG_L_THRSH_REG ) + ); + +// Dual port BRAM. +bram_dp + #( + .N (N ), + .B (4*B) + ) + bram_i + ( + .clka (clk ), + .clkb (m_axis_aclk ), + .ena (1'b1 ), + .enb (1'b1 ), + .wea (mem_we_int ), + .web (1'b0 ), + .addra (mem_addra_int ), + .addrb (mem_addrb_int ), + .dia (mem_di_int ), + .dib ({4*B{1'b0}} ), + .doa ( ), + .dob (mem_do_int ) + ); + +// Data reader. +data_reader + #( + .N (N ), + .B (4*B) + ) + data_reader_i + ( + // Reset and clock. + .rstn (m_axis_aresetn ), + .clk (m_axis_aclk ), + + // Memory I/F. + .mem_en ( ), + .mem_we ( ), + .mem_addr (mem_addrb_int ), + .mem_dout (mem_do_int ), + + // Data out. + .dout (m0_axis_tdata ), + .dready (m0_axis_tready ), + .dvalid (m0_axis_tvalid ), + .dlast (m0_axis_tlast ), + + // Registers. + .START_REG (DR_START_REG_resync ), + .ADDR_REG (DR_ADDR_REG ), + .LEN_REG (DR_LEN_REG ) + ); + +// Output data register (dc fifo to cross domain). +fifo_dc_axi + #( + // Data width. + .B (4*B ), + + // Fifo depth. + .N (4 ) + ) + fifo_i + ( + .wr_rstn (rstn ), + .wr_clk (clk ), + + .rd_rstn (m_axis_aresetn ), + .rd_clk (m_axis_aclk ), + + // Write I/F. + .wr_en (mem_we_int ), + .din (mem_di_int ), + + // Read I/F. + .rd_en (m1_axis_tready ), + .dout (m1_axis_tdata ), + + // Flags. + .full ( ), + .empty (fifo_empty ) + ); + +// Assign outputs. +assign m1_axis_tvalid = ~fifo_empty; + +endmodule + diff --git a/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 0000000..5f33135 --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 5 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 0000000..5c4d9a9 --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 5 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..34f0b12 --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,187 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + virtex7 + + + xc7vx485t + ffg1157 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 0000000..58db142 --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4751 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + ARSIZE + + + m_axi_arsize + + + + + ARUSER + + + m_axi_aruser + + + + + ARVALID + + + m_axi_arvalid + + + + + AWADDR + + + m_axi_awaddr + + + + + AWBURST + + + m_axi_awburst + + + + + AWCACHE + + + m_axi_awcache + + + + + AWID + + + m_axi_awid + + + + + AWLEN + + + m_axi_awlen + + + + + AWLOCK + + + m_axi_awlock + + + + + AWPROT + + + m_axi_awprot + + + + + AWQOS + + + m_axi_awqos + + + + + AWREADY + + + m_axi_awready + + + + + AWREGION + + + m_axi_awregion + + + + + AWSIZE + + + m_axi_awsize + + + + + AWUSER + + + m_axi_awuser + + + + + AWVALID + + + m_axi_awvalid + + + + + BID + + + m_axi_bid + + + + + BREADY + + + m_axi_bready + + + + + BRESP + + + m_axi_bresp + + + + + BUSER + + + m_axi_buser + + + + + BVALID + + + m_axi_bvalid + + + + + RDATA + + + m_axi_rdata + + + + + RID + + + m_axi_rid + + + + + RLAST + + + m_axi_rlast + + + + + RREADY + + + m_axi_rready + + + + + RRESP + + + m_axi_rresp + + + + + RUSER + + + m_axi_ruser + + + + + RVALID + + + m_axi_rvalid + + + + + WDATA + + + m_axi_wdata + + + + + WID + + + m_axi_wid + + + + + WLAST + + + m_axi_wlast + + + + + WREADY + + + m_axi_wready + + + + + WSTRB + + + m_axi_wstrb + + + + + WUSER + + + m_axi_wuser + + + + + WVALID + + + m_axi_wvalid + + + + + + DATA_WIDTH + 32 + + + simulation.tlm + + + + + PROTOCOL + AXI4LITE + + + simulation.tlm + + + + + FREQ_HZ + 100000000 + + + simulation.tlm + + + + + ID_WIDTH + 0 + + + simulation.tlm + + + + + ADDR_WIDTH + 32 + + + simulation.tlm + + + + + AWUSER_WIDTH + 0 + + + simulation.tlm + + + + + ARUSER_WIDTH + 0 + + + simulation.tlm + + + + + WUSER_WIDTH + 0 + + + simulation.tlm + + + + + RUSER_WIDTH + 0 + + + simulation.tlm + + + + + BUSER_WIDTH + 0 + + + simulation.tlm + + + + + READ_WRITE_MODE + READ_WRITE + + + simulation.tlm + + + + + HAS_BURST + 0 + + + simulation.tlm + + + + + HAS_LOCK + 0 + + + simulation.tlm + + + + + HAS_PROT + 1 + + + simulation.tlm + + + + + HAS_CACHE + 0 + + + simulation.tlm + + + + + HAS_QOS + 0 + + + simulation.tlm + + + + + HAS_REGION + 0 + + + simulation.tlm + + + + + HAS_WSTRB + 1 + + + simulation.tlm + + + + + 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xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_aruser + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arvalid + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_arready + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rid + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_rdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rresp + + in + + 1 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rlast + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_ruser + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_rvalid + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rready + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + M_INITIATOR_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + wr_socket + + + width + 32 + + + + + + + 1 + + + + + M_INITIATOR_rd_socket + AXIMM Read Socket + AXIMM Socket for Read + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + rd_socket + + + width + 32 + + + + + + + 1 + + + + + S_TARGET_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + + + + + 1 + + + + + S_TARGET_rd_socket + AXIMM Read Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + + + + + 1 + + + + + + + C_AXI_PROTOCOL + 2 + + + C_AXI_INTERFACE_MODE + 0 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_WDATA_WIDTH + 32 + + + C_AXI_RDATA_WIDTH + 32 + + + C_AXI_WID_WIDTH + 0 + + + C_AXI_RID_WIDTH + 0 + + + C_AXI_AWUSER_WIDTH + 0 + + + C_AXI_ARUSER_WIDTH + 0 + + + C_AXI_WUSER_WIDTH + 0 + + + C_AXI_RUSER_WIDTH + 0 + + + C_AXI_BUSER_WIDTH + 0 + + + C_AXI_SUPPORTS_NARROW + 0 + + + C_AXI_HAS_BURST + 0 + + + C_AXI_HAS_LOCK + 0 + + + C_AXI_HAS_CACHE + 0 + + + C_AXI_HAS_REGION + 0 + + + C_AXI_HAS_PROT + 1 + + + C_AXI_HAS_QOS + 0 + + + C_AXI_HAS_WSTRB + 1 + + + C_AXI_HAS_BRESP + 1 + + + C_AXI_HAS_RRESP + 1 + + + C_AXI_HAS_ARESETN + 1 + + + + + + choice_list_04fafd91 + AXI3 + AXI4 + AXI4LITE + + + choice_list_6240decd + READ_ONLY + READ_WRITE + WRITE_ONLY + + + choice_list_642e7122 + MASTER + PASS_THROUGH + SLAVE + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_0fc128e8 + 0 + 0 + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi_mst_0.vho + vhdlTemplate + + + axi_mst_0.veo + verilogTemplate + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_5 + + + + xilinx_synthesisconstraints_view_fileset + + axi_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_5 + + + + xilinx_externalfiles_view_fileset + + axi_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axi_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axi_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_5 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_5 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_5 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 5 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.1 + + + + + + + + + + diff --git a/firmware/ip/axis_avg_buffer/src/axi_slv.vhd b/firmware/ip/axis_avg_buffer/src/axi_slv.vhd new file mode 100644 index 0000000..350d9a4 --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/axi_slv.vhd @@ -0,0 +1,540 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + AVG_START_REG : out std_logic; + AVG_ADDR_REG : out std_logic_vector (31 downto 0); + AVG_LEN_REG : out std_logic_vector (31 downto 0); + AVG_PHOTON_MODE_REG : out std_logic; + AVG_H_THRSH_REG : out std_logic_vector (31 downto 0); + AVG_L_THRSH_REG : out std_logic_vector (31 downto 0); + AVG_DR_START_REG: out std_logic; + AVG_DR_ADDR_REG : out std_logic_vector (31 downto 0); + AVG_DR_LEN_REG : out std_logic_vector (31 downto 0); + BUF_START_REG : out std_logic; + BUF_ADDR_REG : out std_logic_vector (31 downto 0); + BUF_LEN_REG : out std_logic_vector (31 downto 0); + BUF_DR_START_REG: out std_logic; + BUF_DR_ADDR_REG : out std_logic_vector (31 downto 0); + BUF_DR_LEN_REG : out std_logic_vector (31 downto 0) + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + + -- Output Registers. + AVG_START_REG <= slv_reg0(0); + AVG_ADDR_REG <= slv_reg1; + AVG_LEN_REG <= slv_reg2; + AVG_DR_START_REG <= slv_reg3(0); + AVG_DR_ADDR_REG <= slv_reg4; + AVG_DR_LEN_REG <= slv_reg5; + BUF_START_REG <= slv_reg6(0); + BUF_ADDR_REG <= slv_reg7; + BUF_LEN_REG <= slv_reg8; + BUF_DR_START_REG <= slv_reg9(0); + BUF_DR_ADDR_REG <= slv_reg10; + BUF_DR_LEN_REG <= slv_reg11; + AVG_PHOTON_MODE_REG <= slv_reg12(0); + AVG_H_THRSH_REG <= slv_reg13; + AVG_L_THRSH_REG <= slv_reg14; + +end rtl; + diff --git a/firmware/ip/axis_avg_buffer/src/axis_avg_buffer.v b/firmware/ip/axis_avg_buffer/src/axis_avg_buffer.v new file mode 100644 index 0000000..8c70265 --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/axis_avg_buffer.v @@ -0,0 +1,272 @@ +// AXIS AVG BUFFER. +// s_axi_aclk : clock for s_axi_* +// s_axis_aclk : clock for s_axis_* +// m_axis_aclk : clock for m0_axis_* and m1_axis_* +// +module axis_avg_buffer + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // Trigger input. + trigger , + + // AXIS Slave for input data. + s_axis_aclk , + s_axis_aresetn , + s_axis_tvalid , + s_axis_tready , + s_axis_tdata , + + // Reset and clock for m0 and m1. + m_axis_aclk , + m_axis_aresetn , + + // AXIS Master for averaged output. + m0_axis_tvalid , + m0_axis_tready , + m0_axis_tdata , + m0_axis_tlast , + + // AXIS Master for raw output. + m1_axis_tvalid , + m1_axis_tready , + m1_axis_tdata , + m1_axis_tlast , + + // AXIS Master for register output. + m2_axis_tvalid , + m2_axis_tready , + m2_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Memory depth. +parameter N_AVG = 10; +parameter N_BUF = 10; + +// Number of bits. +parameter B = 16; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input trigger; + +input s_axis_aclk; +input s_axis_aresetn; +input s_axis_tvalid; +output s_axis_tready; +input [2*B-1:0] s_axis_tdata; + +input m_axis_aclk; +input m_axis_aresetn; + +output m0_axis_tvalid; +input m0_axis_tready; +output [4*B-1:0] m0_axis_tdata; +output m0_axis_tlast; + +output m1_axis_tvalid; +input m1_axis_tready; +output [2*B-1:0] m1_axis_tdata; +output m1_axis_tlast; + +output m2_axis_tvalid; +input m2_axis_tready; +output [4*B-1:0] m2_axis_tdata; + + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire AVG_START_REG; +wire [N_AVG-1:0] AVG_ADDR_REG; +wire [31:0] AVG_LEN_REG; +wire AVG_PHOTON_MODE_REG; +wire [B-1:0] AVG_H_THRSH_REG; +wire [B-1:0] AVG_L_THRSH_REG; +wire AVG_DR_START_REG; +wire [N_AVG-1:0] AVG_DR_ADDR_REG; +wire [N_AVG-1:0] AVG_DR_LEN_REG; +wire BUF_START_REG; +wire [N_BUF-1:0] BUF_ADDR_REG; +wire [N_BUF-1:0] BUF_LEN_REG; +wire BUF_DR_START_REG; +wire [N_BUF-1:0] BUF_DR_ADDR_REG; +wire [N_BUF-1:0] BUF_DR_LEN_REG; + + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .AVG_START_REG (AVG_START_REG ), + .AVG_ADDR_REG (AVG_ADDR_REG ), + .AVG_LEN_REG (AVG_LEN_REG ), + .AVG_PHOTON_MODE_REG (AVG_PHOTON_MODE_REG), + .AVG_H_THRSH_REG (AVG_H_THRSH_REG ), + .AVG_L_THRSH_REG (AVG_L_THRSH_REG ), + .AVG_DR_START_REG (AVG_DR_START_REG ), + .AVG_DR_ADDR_REG (AVG_DR_ADDR_REG ), + .AVG_DR_LEN_REG (AVG_DR_LEN_REG ), + .BUF_START_REG (BUF_START_REG ), + .BUF_ADDR_REG (BUF_ADDR_REG ), + .BUF_LEN_REG (BUF_LEN_REG ), + .BUF_DR_START_REG (BUF_DR_START_REG ), + .BUF_DR_ADDR_REG (BUF_DR_ADDR_REG ), + .BUF_DR_LEN_REG (BUF_DR_LEN_REG ) + ); + +// Averager + Buffer Top. +avg_buffer + #( + .N_AVG (N_AVG ), + .N_BUF (N_BUF ), + .B (B ) + ) + avg_buffer_i + ( + // Reset and clock for s. + .s_axis_aclk (s_axis_aclk ), + .s_axis_aresetn (s_axis_aresetn ), + + // Trigger input. + .trigger (trigger ), + + // AXIS Slave for input data. + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tready (s_axis_tready ), + .s_axis_tdata (s_axis_tdata ), + + // Reset and clock for m0 and m1. + .m_axis_aclk (m_axis_aclk ), + .m_axis_aresetn (m_axis_aresetn ), + + // AXIS Master for averaged output. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tready (m0_axis_tready ), + .m0_axis_tdata (m0_axis_tdata ), + .m0_axis_tlast (m0_axis_tlast ), + + // AXIS Master for raw output. + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tready (m1_axis_tready ), + .m1_axis_tdata (m1_axis_tdata ), + .m1_axis_tlast (m1_axis_tlast ), + + // AXIS Master for register output. + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tready (m2_axis_tready ), + .m2_axis_tdata (m2_axis_tdata ), + + // Registers. + .AVG_START_REG (AVG_START_REG ), + .AVG_ADDR_REG (AVG_ADDR_REG ), + .AVG_LEN_REG (AVG_LEN_REG ), + .AVG_PHOTON_MODE_REG (AVG_PHOTON_MODE_REG), + .AVG_H_THRSH_REG (AVG_H_THRSH_REG ), + .AVG_L_THRSH_REG (AVG_L_THRSH_REG ), + .AVG_DR_START_REG (AVG_DR_START_REG ), + .AVG_DR_ADDR_REG (AVG_DR_ADDR_REG ), + .AVG_DR_LEN_REG (AVG_DR_LEN_REG ), + .BUF_START_REG (BUF_START_REG ), + .BUF_ADDR_REG (BUF_ADDR_REG ), + .BUF_LEN_REG (BUF_LEN_REG ), + .BUF_DR_START_REG (BUF_DR_START_REG ), + .BUF_DR_ADDR_REG (BUF_DR_ADDR_REG ), + .BUF_DR_LEN_REG (BUF_DR_LEN_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_avg_buffer/src/buffer.sv b/firmware/ip/axis_avg_buffer/src/buffer.sv new file mode 100644 index 0000000..6606de7 --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/buffer.sv @@ -0,0 +1,169 @@ +// Data is I,Q. +// I: lower B bits. +// Q: upper B bits. +module buffer ( + // Reset and clock. + rstn , + clk , + + // Trigger input. + trigger_i , + + // Data input. + din_i , + + // Memory interface. + mem_we_o , + mem_addr_o , + mem_di_o , + + // Registers. + START_REG , + ADDR_REG , + LEN_REG + ); + +//////////////// +// Parameters // +//////////////// +// Memory depth. +parameter N = 10; + +// Number of bits. +parameter B = 16; + +/////////// +// Ports // +/////////// +input rstn; +input clk; + +input trigger_i; + +input [2*B-1:0] din_i; + +output mem_we_o; +output [N-1:0] mem_addr_o; +output [2*B-1:0] mem_di_o; + +input START_REG; +input [N-1:0] ADDR_REG; +input [N-1:0] LEN_REG; + +////////////////////// +// Internal signals // +////////////////////// +// States. +typedef enum { INIT_ST , + START_ST , + TRIGGER_ST , + MEMW_ST , + WAIT_TRIGGER_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +reg start_state; +reg trigger_state; +reg memw_state; + +// Counter. +reg [N-1:0] cnt; + +// Registers. +reg [N-1:0] addr_r; +reg [N-1:0] len_r; + +////////////////// +// Architecture // +////////////////// + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= INIT_ST; + + // Counter. + cnt <= 0; + + // Registers. + addr_r <= 0; + len_r <= 0; + end + else begin + // State register. + case (state) + INIT_ST: + state <= START_ST; + + START_ST: + if ( START_REG == 1'b1) + state <= TRIGGER_ST; + + TRIGGER_ST: + if ( START_REG == 1'b0 ) + state <= START_ST; + else if ( trigger_i == 1'b1 ) + state <= MEMW_ST; + + MEMW_ST: + if ( cnt == len_r-1 ) + state <= WAIT_TRIGGER_ST; + + WAIT_TRIGGER_ST: + if ( START_REG == 1'b0 ) + state <= START_ST; + else if ( trigger_i == 1'b0 ) begin + state <= TRIGGER_ST; + end + endcase + + // Counter. + if ( memw_state == 1'b1 ) + cnt <= cnt + 1; + else + cnt <= 0; + + // Registers. + if ( start_state == 1'b1 ) begin + addr_r <= ADDR_REG; + len_r <= LEN_REG; + end + else if ( memw_state == 1'b1 ) begin + addr_r <= addr_r + 1; + end + end +end + +// FSM outputs. +always_comb begin + // Default. + start_state = 0; + trigger_state = 0; + memw_state = 0; + + case (state) + //INIT_ST: + + START_ST: + start_state = 1'b1; + + TRIGGER_ST: + trigger_state = 1'b1; + + MEMW_ST: + memw_state = 1'b1; + + //WAIT_TRIGGER_ST: + endcase +end + +// Assign outputs. +assign mem_we_o = memw_state; +assign mem_addr_o = addr_r; +assign mem_di_o = din_i; + +endmodule + diff --git a/firmware/ip/axis_avg_buffer/src/buffer_top.v b/firmware/ip/axis_avg_buffer/src/buffer_top.v new file mode 100644 index 0000000..b9af09f --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/buffer_top.v @@ -0,0 +1,182 @@ +module buffer_top ( + // Reset and clock. + rstn , + clk , + + // Trigger input. + trigger_i , + + // Data input. + din_i , + + // AXIS Master for output. + m_axis_aclk , + m_axis_aresetn , + m_axis_tvalid , + m_axis_tready , + m_axis_tdata , + m_axis_tlast , + + // Registers. + BUF_START_REG , + BUF_ADDR_REG , + BUF_LEN_REG , + DR_START_REG , + DR_ADDR_REG , + DR_LEN_REG + ); + +//////////////// +// Parameters // +//////////////// +// Memory depth. +parameter N = 10; + +// Number of bits. +parameter B = 16; + +/////////// +// Ports // +/////////// +input rstn; +input clk; + +input trigger_i; + +input [2*B-1:0] din_i; + +input m_axis_aclk; +input m_axis_aresetn; +output m_axis_tvalid; +input m_axis_tready; +output [2*B-1:0] m_axis_tdata; +output m_axis_tlast; + +input BUF_START_REG; +input [N-1:0] BUF_ADDR_REG; +input [N-1:0] BUF_LEN_REG; +input DR_START_REG; +input [N-1:0] DR_ADDR_REG; +input [N-1:0] DR_LEN_REG; + +////////////////////// +// Internal signals // +////////////////////// +wire mem_we_int; +wire [N-1:0] mem_addra_int, mem_addrb_int; +wire [2*B-1:0] mem_di_int, mem_do_int; + +wire BUF_START_REG_resync; +wire DR_START_REG_resync; + +////////////////// +// Architecture // +////////////////// + +// BUF_START_REG_resync +synchronizer_n + #( + .N (2) + ) + BUF_START_REG_resync_i ( + .rstn (rstn ), + .clk (clk ), + .data_in (BUF_START_REG ), + .data_out (BUF_START_REG_resync ) + ); + +//DR_START_REG_resync +synchronizer_n + #( + .N (2) + ) + DR_START_REG_resync_i ( + .rstn (m_axis_aresetn ), + .clk (m_axis_aclk ), + .data_in (DR_START_REG ), + .data_out (DR_START_REG_resync ) + ); + +// Buffer block. +buffer + #( + .N (N), + .B (B) + ) + buffer_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Trigger input. + .trigger_i (trigger_i ), + + // Data input. + .din_i (din_i ), + + // Memory interface. + .mem_we_o (mem_we_int ), + .mem_addr_o (mem_addra_int ), + .mem_di_o (mem_di_int ), + + // Registers. + .START_REG (BUF_START_REG_resync ), + .ADDR_REG (BUF_ADDR_REG ), + .LEN_REG (BUF_LEN_REG ) + ); + +// Dual port BRAM. +bram_dp + #( + .N (N ), + .B (2*B) + ) + bram_i + ( + .clka (clk ), + .clkb (m_axis_aclk ), + .ena (1'b1 ), + .enb (1'b1 ), + .wea (mem_we_int ), + .web (1'b0 ), + .addra (mem_addra_int ), + .addrb (mem_addrb_int ), + .dia (mem_di_int ), + .dib ({4*B{1'b0}} ), + .doa ( ), + .dob (mem_do_int ) + ); + +// Data reader. +data_reader + #( + .N (N ), + .B (2*B) + ) + data_reader_i + ( + // Reset and clock. + .rstn (m_axis_aresetn ), + .clk (m_axis_aclk ), + + // Memory I/F. + .mem_en ( ), + .mem_we ( ), + .mem_addr (mem_addrb_int ), + .mem_dout (mem_do_int ), + + // Data out. + .dout (m_axis_tdata ), + .dready (m_axis_tready ), + .dvalid (m_axis_tvalid ), + .dlast (m_axis_tlast ), + + // Registers. + .START_REG (DR_START_REG_resync ), + .ADDR_REG (DR_ADDR_REG ), + .LEN_REG (DR_LEN_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_avg_buffer/src/data_reader.vhd b/firmware/ip/axis_avg_buffer/src/data_reader.vhd new file mode 100644 index 0000000..a566ef5 --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/data_reader.vhd @@ -0,0 +1,300 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity data_reader is + Generic + ( + -- Address map of memory. + N : Integer := 8; + -- Data width. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Memory I/F. + mem_en : out std_logic; + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_dout : in std_logic_vector (B-1 downto 0); + + -- Data out. + dout : out std_logic_vector (B-1 downto 0); + dready : in std_logic; + dvalid : out std_logic; + dlast : out std_logic; + + -- Registers. + START_REG : in std_logic; + ADDR_REG : in std_logic_vector (N-1 downto 0); + LEN_REG : in std_logic_vector (N-1 downto 0) + ); +end entity; + +architecture rtl of data_reader is + +constant NPOW : Integer := 2**N; + +-- Fifo to drive AXI Stream Master I/F. +component fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +type fsm_state is ( INIT_ST, + REGS_ST, + READ_ST, + WRITE_ST, + READ_LAST_ST, + WRITE_LAST_ST, + FIFO_ST, + END_ST); +signal current_state, next_state : fsm_state; + +signal init_state : std_logic; +signal regs_state : std_logic; +signal read_state : std_logic; +signal write_state : std_logic; +signal fifo_state : std_logic; +signal read_en : std_logic; + +-- Counter for memory address and samples. +signal cnt : unsigned(N-1 downto 0); +signal addr_cnt : unsigned(N-1 downto 0); + +-- Length register. +signal len_r : unsigned(N-1 downto 0); + +-- Fifo signals. +signal fifo_wr_en : std_logic; +signal fifo_rd_en : std_logic; +signal fifo_din : std_logic_vector (B-1 downto 0); +signal fifo_dout : std_logic_vector (B-1 downto 0); +signal fifo_full : std_logic; +signal fifo_empty : std_logic; + +-- Fifof pipeline. +signal fifo_dout_r : std_logic_vector (B-1 downto 0); +signal fifo_empty_r : std_logic; + +signal mem_dout_r : std_logic_vector (B-1 downto 0); + +signal dlast_i : std_logic; + +begin + +-- Fifo to drive AXI Stream Master I/F. +fifo_i : fifo_axi + Generic map + ( + -- Data width. + B => B , + + -- Fifo depth. + N => 4 + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => fifo_wr_en , + din => fifo_din , + + -- Read I/F. + rd_en => fifo_rd_en , + dout => fifo_dout , + + -- Flags. + full => fifo_full , + empty => fifo_empty + ); + +-- Fifo connections. +fifo_wr_en <= write_state; +fifo_din <= mem_dout_r; +fifo_rd_en <= dready when read_en = '1' else + '0'; + +-- dlast generation. +dlast_i <= fifo_state and fifo_empty; + +process(clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + -- State register. + current_state <= INIT_ST; + + -- Counter for memory address and samples. + cnt <= (others => '0'); + addr_cnt <= (others => '0'); + mem_dout_r <= (others => '0'); + + -- Length register. + len_r <= (others => '0'); + + -- Fifo pipeline. + fifo_dout_r <= (others => '0'); + fifo_empty_r <= '1'; + else + -- State register. + current_state <= next_state; + + -- Memory address and data. + if ( init_state = '1' ) then + mem_dout_r <= (others => '0'); + cnt <= (others => '0'); + addr_cnt <= (others => '0'); + len_r <= (others => '0'); + elsif ( regs_state = '1' ) then + cnt <= (others => '0'); + addr_cnt <= unsigned(ADDR_REG); + len_r <= unsigned(LEN_REG); + elsif ( read_state = '1' ) then + mem_dout_r <= mem_dout; + cnt <= cnt + 1; + addr_cnt <= addr_cnt + 1; + end if; + + -- Fifo pipeline. + if ( dready = '1' ) then + fifo_dout_r <= fifo_dout; + fifo_empty_r <= fifo_empty; + end if; + end if; + end if; +end process; + +-- Next state logic. +process (current_state, START_REG, len_r, cnt, addr_cnt, fifo_full, fifo_empty, dready) +begin + case current_state is + when INIT_ST => + if (START_REG = '0') then + next_state <= INIT_ST; + else + next_state <= REGS_ST; + end if; + + when REGS_ST => + next_state <= READ_ST; + + when READ_ST => + next_state <= WRITE_ST; + + when WRITE_ST => + if ( fifo_full = '1' ) then + next_state <= WRITE_ST; + elsif ( cnt < len_r-1 ) then + next_state <= READ_ST; + else + next_state <= READ_LAST_ST; + end if; + + when READ_LAST_ST => + next_state <= WRITE_LAST_ST; + + when WRITE_LAST_ST => + if ( fifo_full = '1' ) then + next_state <= WRITE_LAST_ST; + else + next_state <= FIFO_ST; + end if; + + when FIFO_ST => + if ( fifo_empty = '1' and dready = '1' ) then + next_state <= END_ST; + else + next_state <= FIFO_ST; + end if; + + when END_ST => + if ( START_REG = '1' ) then + next_state <= END_ST; + else + next_state <= INIT_ST; + end if; + end case; +end process; + +-- Output logic. +process (current_state) +begin +init_state <= '0'; +regs_state <= '0'; +read_state <= '0'; +write_state <= '0'; +fifo_state <= '0'; +read_en <= '0'; + case current_state is + when INIT_ST => + init_state <= '1'; + + when REGS_ST => + regs_state <= '1'; + + when READ_ST => + read_state <= '1'; + read_en <= '1'; + + when WRITE_ST => + write_state <= '1'; + read_en <= '1'; + + when READ_LAST_ST => + read_state <= '1'; + read_en <= '1'; + + when WRITE_LAST_ST => + write_state <= '1'; + read_en <= '1'; + + when FIFO_ST => + fifo_state <= '1'; + read_en <= '1'; + + when END_ST => + + end case; +end process; + +-- Assign outputs. +mem_en <= '1'; +mem_we <= '0'; +mem_addr <= std_logic_vector(addr_cnt); + +dout <= fifo_dout_r; +dvalid <= not(fifo_empty_r); +dlast <= dlast_i; + +end rtl; diff --git a/firmware/ip/axis_avg_buffer/src/fifo/bin2gray.vhd b/firmware/ip/axis_avg_buffer/src/fifo/bin2gray.vhd new file mode 100644 index 0000000..4ecc09b --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/fifo/bin2gray.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end bin2gray; + +architecture rtl of bin2gray is + +signal gray : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +gray(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + gray(I) <= din(I+1) xor din(I); +end generate; + +-- Assign output. +dout <= gray; + +end rtl; + diff --git a/firmware/ip/axis_avg_buffer/src/fifo/bram_dp.vhd b/firmware/ip/axis_avg_buffer/src/fifo/bram_dp.vhd new file mode 100644 index 0000000..d57aad1 --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/fifo/bram_dp.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture rtl of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_avg_buffer/src/fifo/bram_simple_dp.vhd b/firmware/ip/axis_avg_buffer/src/fifo/bram_simple_dp.vhd new file mode 100644 index 0000000..1494332 --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/fifo/bram_simple_dp.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_simple_dp; + +architecture rtl of bram_simple_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_avg_buffer/src/fifo/fifo.vhd b/firmware/ip/axis_avg_buffer/src/fifo/fifo.vhd new file mode 100644 index 0000000..957362b --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/fifo/fifo.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture rtl of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Dual port, single clock BRAM. +component bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- FIFO memory. +mem_i : bram_simple_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_avg_buffer/src/fifo/fifo_axi.vhd b/firmware/ip/axis_avg_buffer/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_avg_buffer/src/fifo/fifo_dc.vhd b/firmware/ip/axis_avg_buffer/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_avg_buffer/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_avg_buffer/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_avg_buffer/src/fifo/gray2bin.vhd b/firmware/ip/axis_avg_buffer/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_avg_buffer/src/fifo/rd2axi.vhd b/firmware/ip/axis_avg_buffer/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_avg_buffer/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_avg_buffer/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_avg_buffer/src/outreg.sv b/firmware/ip/axis_avg_buffer/src/outreg.sv new file mode 100644 index 0000000..d35357a --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/outreg.sv @@ -0,0 +1,113 @@ +// Data is I,Q. +// I: lower B bits. +// Q: upper B bits. +module outreg ( + // Reset and clock. + rstn , + clk , + + // Data input. + wen , + din , + + // M_AXIS. + m_axis_tdata , + m_axis_tready , + m_axis_tvalid + ); + +//////////////// +// Parameters // +//////////////// +// Number of bits. +parameter B = 16; + +/////////// +// Ports // +/////////// +input rstn; +input clk; + +input wen; +input [B-1:0] din; + +output [B-1:0] m_axis_tdata; +input m_axis_tready; +output m_axis_tvalid; + +////////////////////// +// Internal signals // +////////////////////// +// States. +typedef enum { WAIT_IN_ST , + READ_IN_ST , + WRITE_OUT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// Data register. +reg [B-1:0] din_r; + +reg din_en_i; +reg valid_i; + +////////////////// +// Architecture // +////////////////// + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= WAIT_IN_ST; + + // Data register. + din_r <= 0; + end + else begin + // State register. + case (state) + WAIT_IN_ST: + if ( wen == 1'b1) + state <= READ_IN_ST; + + READ_IN_ST: + if ( wen == 1'b0 ) + state <= WRITE_OUT_ST; + + WRITE_OUT_ST: + if ( m_axis_tready == 1'b1 ) + state <= WAIT_IN_ST; + endcase + + // Data register. + if (din_en_i == 1'b1) + din_r <= din; + end +end + +// FSM outputs. +always_comb begin + // Default. + din_en_i = 0; + valid_i = 0; + + case (state) + //WAIT_IN_ST: + + READ_IN_ST: + din_en_i = 1'b1; + + WRITE_OUT_ST: + valid_i = 1'b1; + endcase +end + +// Assign outputs. +assign m_axis_tdata = din_r; +assign m_axis_tvalid = valid_i; + +endmodule + diff --git a/firmware/ip/axis_avg_buffer/src/synchronizer_n.vhd b/firmware/ip/axis_avg_buffer/src/synchronizer_n.vhd new file mode 100644 index 0000000..925425d --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/synchronizer_n.vhd @@ -0,0 +1,42 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library common_lib; +use common_lib.all; + +entity synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end synchronizer_n; + +architecture rtl of synchronizer_n is + +-- Internal register. +signal data_int_reg : std_logic_vector (N-1 downto 0); + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git 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a/firmware/ip/axis_avg_buffer/src/tb/tb.sv b/firmware/ip/axis_avg_buffer/src/tb/tb.sv new file mode 100644 index 0000000..be78bac --- /dev/null +++ b/firmware/ip/axis_avg_buffer/src/tb/tb.sv @@ -0,0 +1,382 @@ +// VIP: axi_mst_0 +// DUT: axis_readout_v1 +// IF: s_axi -> axi_mst_0 + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +localparam N_AVG = 10; +localparam N_BUF = 16; +localparam B = 16; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg trigger; + +reg s_axis_aclk; +reg s_axis_aresetn; +reg s_axis_tvalid; +wire s_axis_tready; +reg [2*B-1:0] s_axis_tdata; + +reg m_axis_aclk; +reg m_axis_aresetn; + +wire m0_axis_tvalid; +reg m0_axis_tready; +wire [4*B-1:0] m0_axis_tdata; +wire m0_axis_tlast; + +wire m1_axis_tvalid; +reg m1_axis_tready; +wire [2*B-1:0] m1_axis_tdata; +wire m1_axis_tlast; + +wire m2_axis_tvalid; +reg m2_axis_tready; +wire [4*B-1:0] m2_axis_tdata; + +// AXI VIP master address. +xil_axi_ulong avg_start_reg = 0; +xil_axi_ulong avg_addr_reg = 1; +xil_axi_ulong avg_len_reg = 2; +xil_axi_ulong avg_dr_start_reg = 3; +xil_axi_ulong avg_dr_addr_reg = 4; +xil_axi_ulong avg_dr_len_reg = 5; +xil_axi_ulong buf_start_reg = 6; +xil_axi_ulong buf_addr_reg = 7; +xil_axi_ulong buf_len_reg = 8; +xil_axi_ulong buf_dr_start_reg = 9; +xil_axi_ulong buf_dr_addr_reg = 10; +xil_axi_ulong buf_dr_len_reg = 11; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Test bench control. +reg tb_input = 0; +reg tb_input_done = 0; + +// axi_mst_0. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_avg_buffer + # + ( + .N_AVG (N_AVG ), + .N_BUF (N_BUF ), + .B (B ) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // Trigger input. + .trigger (trigger ), + + // AXIS Slave for input data. + .s_axis_aclk (s_axis_aclk ), + .s_axis_aresetn (s_axis_aresetn ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tready (s_axis_tready ), + .s_axis_tdata (s_axis_tdata ), + + // Reset and clock for m0 and m1. + .m_axis_aclk (m_axis_aclk ), + .m_axis_aresetn (m_axis_aresetn ), + + // AXIS Master for averaged output. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tready (m0_axis_tready ), + .m0_axis_tdata (m0_axis_tdata ), + .m0_axis_tlast (m0_axis_tlast ), + + // AXIS Master for raw output. + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tready (m1_axis_tready ), + .m1_axis_tdata (m1_axis_tdata ), + .m1_axis_tlast (m1_axis_tlast ), + + // AXIS Master for register output. + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tready (m2_axis_tready ), + .m2_axis_tdata (m2_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +// Main TB Control. +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + s_axis_aresetn <= 0; + m_axis_aresetn <= 0; + m0_axis_tready <= 1; + m1_axis_tready <= 1; + m2_axis_tready <= 1; + trigger <= 0; + #500; + s_axi_aresetn <= 1; + s_axis_aresetn <= 1; + m_axis_aresetn <= 1; + + #1000; + + $display("##############"); + $display("### Test 0 ###"); + $display("##############"); + $display("t = %0t", $time); + // Average/buffer: + // * addr = 0. + // * len = 1280. + + // avg_addr_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_addr_reg, prot, data_wr, resp); + #10; + + // avg_len_reg + data_wr = 1280; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_len_reg, prot, data_wr, resp); + #10; + + // buf_addr_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_addr_reg, prot, data_wr, resp); + #10; + + // buf_len_reg + data_wr = 1280; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_len_reg, prot, data_wr, resp); + #10; + + // avg_start_reg + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_start_reg, prot, data_wr, resp); + #10; + + // buf_start_reg + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_start_reg, prot, data_wr, resp); + #10; + + // Start sending input data. + tb_input <= 1; + + trigger_gen(5,1280); + + wait (tb_input_done); + + tb_input <= 0; + + // avg_start_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_start_reg, prot, data_wr, resp); + #10; + + // buf_start_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_start_reg, prot, data_wr, resp); + #10; + + // Average DR. + // * addr = 0. + // * len = 10; + + // avg_dr_addr_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_dr_addr_reg, prot, data_wr, resp); + #10; + + // avg_dr_len_reg + data_wr = 10; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_dr_len_reg, prot, data_wr, resp); + #10; + + // avg_dr_start_reg + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_dr_start_reg, prot, data_wr, resp); + #10; + + // avg_dr_start_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_dr_start_reg, prot, data_wr, resp); + #10; + + #100; + + // Buffer DR. + // * addr = 0. + // * len = 1280*5 = 6400, I use 7000; + + // buf_dr_addr_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_dr_addr_reg, prot, data_wr, resp); + #10; + + // buf_dr_len_reg + data_wr = 7000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_dr_len_reg, prot, data_wr, resp); + #10; + + // buf_dr_start_reg + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_dr_start_reg, prot, data_wr, resp); + #10; + + // buf_dr_start_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_dr_start_reg, prot, data_wr, resp); + #10; + + #20000; +end + +// Input data. +initial begin + int fd; + int vali, valq; + + s_axis_tvalid <= 1; + s_axis_tdata <= 0; + tb_input_done <= 0; + + wait (tb_input); + + fd = $fopen("../../../../../tb/data_iq.txt","r"); + + while ($fscanf(fd,"%d,%d", vali, valq) == 2) begin + $display("Time %t: I = %d, Q = %d", $time, vali, valq); + @(posedge s_axis_aclk); + s_axis_tdata[0 +: 16] <= vali; + s_axis_tdata[16 +: 16] <= valq; + end + + @(posedge s_axis_aclk); + s_axis_tvalid <= 0; + tb_input_done <= 1; + +end + +// s_axi_aclk. +always begin + s_axi_aclk <= 0; + #10; + s_axi_aclk <= 1; + #10; +end + +// s_axis_aclk. +always begin + s_axis_aclk <= 0; + #7; + s_axis_aclk <= 1; + #7; +end + +// m_axis_aclk. +always begin + m_axis_aclk <= 0; + #3; + m_axis_aclk <= 1; + #3; +end + +task trigger_gen (input int cnt, input int waitc); + for (int i=0; i + + user.org + user + axis_buffer_ddr_v1 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TSTRB + + + m_axis_tstrb + + + + + TLAST + + + m_axis_tlast + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TSTRB + + + s_axis_tstrb + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + m_axi + + + + + + + + + AWID + + + m_axi_awid + + + + + AWADDR + + + m_axi_awaddr + + + + + AWLEN + + + m_axi_awlen + + + + + AWSIZE + + + m_axi_awsize + + + + + AWBURST + + + m_axi_awburst + + + + + AWLOCK + + + m_axi_awlock + + + + + AWCACHE + + + m_axi_awcache + + + + + AWPROT + + + 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xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_bid + + in + + 0 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_bresp + + in + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_bvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_bready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arid + + out + + 0 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_araddr + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arlen + + out + + 7 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arsize + + out + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arburst + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arlock + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arcache + + out + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arprot + + out + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arregion + + out + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arqos + + out + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_rid + + in + + 0 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_rdata + + in + + 511 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_rresp + + in + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_rlast + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_rvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_rready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 511 + 0 + + + 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xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + TARGET_SLAVE_BASE_ADDR + Target Slave Base Addr + 0x40000000 + + + ID_WIDTH + Id Width + 1 + + + DATA_WIDTH + Data Width + 512 + + + BURST_SIZE + Burst Size + 15 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/axi_slv.v + verilogSource + + + src/axi_mst/axi_mst.sv + systemVerilogSource + + + src/axi_mst/axi_mst_read.sv + systemVerilogSource + + + src/axi_mst/axi_mst_write.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_buffer_ddr_v1.sv + systemVerilogSource + CHECKSUM_551d2e84 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/axi_slv.v + verilogSource + + + src/axi_mst/axi_mst.sv + systemVerilogSource + + + src/axi_mst/axi_mst_read.sv + systemVerilogSource + + + src/axi_mst/axi_mst_write.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_buffer_ddr_v1.sv + systemVerilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_buffer_ddr_v1_v1_0.tcl + tclSource + CHECKSUM_886bc707 + XGUI_VERSION_2 + + + + AXIS Buffer for DDR4, V1. + + + TARGET_SLAVE_BASE_ADDR + Target Slave Base Addr + 0x40000000 + + + ID_WIDTH + Id Width + 1 + + + DATA_WIDTH + Data Width + 512 + + + Component_Name + axis_buffer_ddr_v1_v1_0 + + + BURST_SIZE + Burst Size + 15 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /UserIP + + AXIS Buffer DDR V1 + package_project + 3 + 2023-06-01T20:29:22Z + + + 2022.1 + + + + + + + + + + diff --git a/firmware/ip/axis_buffer_ddr_v1/src/axi_mst/axi_mst.sv b/firmware/ip/axis_buffer_ddr_v1/src/axi_mst/axi_mst.sv new file mode 100644 index 0000000..2851fa1 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/axi_mst/axi_mst.sv @@ -0,0 +1,208 @@ +module axi_mst + #( + // Parameters of AXI Master I/F. + parameter TARGET_SLAVE_BASE_ADDR = 32'h40000000 , + parameter ID_WIDTH = 1 , + parameter DATA_WIDTH = 512 , + parameter BURST_SIZE = 15 + ) + ( + // Trigger. + input wire trigger , + + /**************/ + /* AXI Master */ + /**************/ + + // Reset and Clock. + input wire m_axi_aclk , + input wire m_axi_aresetn , + + // Write Address Channel. + output wire [ID_WIDTH-1:0] m_axi_awid , + output wire [31:0] m_axi_awaddr , + output wire [7:0] m_axi_awlen , + output wire [2:0] m_axi_awsize , + output wire [1:0] m_axi_awburst , + output wire m_axi_awlock , + output wire [3:0] m_axi_awcache , + output wire [2:0] m_axi_awprot , + output wire [3:0] m_axi_awregion , + output wire [3:0] m_axi_awqos , + output wire m_axi_awvalid , + input wire m_axi_awready , + + // Write Data Channel. + output wire [DATA_WIDTH-1:0] m_axi_wdata , + output wire [DATA_WIDTH/8-1:0] m_axi_wstrb , + output wire m_axi_wlast , + output wire m_axi_wvalid , + input wire m_axi_wready , + + // Write Response Channel. + input wire [ID_WIDTH-1:0] m_axi_bid , + input wire [1:0] m_axi_bresp , + input wire m_axi_bvalid , + output wire m_axi_bready , + + // Read Address Channel. + output wire [ID_WIDTH-1:0] m_axi_arid , + output wire [31:0] m_axi_araddr , + output wire [7:0] m_axi_arlen , + output wire [2:0] m_axi_arsize , + output wire [1:0] m_axi_arburst , + output wire m_axi_arlock , + output wire [3:0] m_axi_arcache , + output wire [2:0] m_axi_arprot , + output wire [3:0] m_axi_arregion , + output wire [3:0] m_axi_arqos , + output wire m_axi_arvalid , + input wire m_axi_arready , + + // Read Data Channel. + input wire [ID_WIDTH-1:0] m_axi_rid , + input wire [DATA_WIDTH-1:0] m_axi_rdata , + input wire [1:0] m_axi_rresp , + input wire m_axi_rlast , + input wire m_axi_rvalid , + output wire m_axi_rready , + + /*************************/ + /* AXIS Master Interfase */ + /*************************/ + output wire m_axis_tvalid , + output wire [DATA_WIDTH-1:0] m_axis_tdata , + output wire [DATA_WIDTH/8-1:0] m_axis_tstrb , + output wire m_axis_tlast , + input wire m_axis_tready , + + /************************/ + /* AXIS Slave Interfase */ + /************************/ + output wire s_axis_tready , + input wire [DATA_WIDTH-1:0] s_axis_tdata , + input wire [DATA_WIDTH/8-1:0] s_axis_tstrb , + input wire s_axis_tlast , + input wire s_axis_tvalid , + + // Registers. + input wire RSTART_REG , + input wire [31:0] RADDR_REG , + input wire [31:0] RLENGTH_REG , + input wire WSTART_REG , + input wire [31:0] WADDR_REG , + input wire [31:0] WNBURST_REG + ); + +/*************/ +/* Internals */ +/*************/ + + +/****************/ +/* Architecture */ +/****************/ + +// AXI Master Read. +axi_mst_read + #( + // Parameters of AXI Master I/F. + .TARGET_SLAVE_BASE_ADDR (TARGET_SLAVE_BASE_ADDR ), + .ID_WIDTH (ID_WIDTH ), + .DATA_WIDTH (DATA_WIDTH ) + ) + axi_mst_read_i + ( + .clk (m_axi_aclk ), + .rstn (m_axi_aresetn ), + + // AXI Master Interface. + .m_axi_arid (m_axi_arid ), + .m_axi_araddr (m_axi_araddr ), + .m_axi_arlen (m_axi_arlen ), + .m_axi_arsize (m_axi_arsize ), + .m_axi_arburst (m_axi_arburst ), + .m_axi_arlock (m_axi_arlock ), + .m_axi_arcache (m_axi_arcache ), + .m_axi_arprot (m_axi_arprot ), + .m_axi_arregion (m_axi_arregion ), + .m_axi_arqos (m_axi_arqos ), + .m_axi_arvalid (m_axi_arvalid ), + .m_axi_arready (m_axi_arready ), + + .m_axi_rid (m_axi_rid ), + .m_axi_rdata (m_axi_rdata ), + .m_axi_rresp (m_axi_rresp ), + .m_axi_rlast (m_axi_rlast ), + .m_axi_rvalid (m_axi_rvalid ), + .m_axi_rready (m_axi_rready ), + + // AXIS Master Interfase. + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ), + .m_axis_tstrb (m_axis_tstrb ), + .m_axis_tlast (m_axis_tlast ), + .m_axis_tready (m_axis_tready ), + + // Registers. + .START_REG (RSTART_REG ), + .ADDR_REG (RADDR_REG ), + .LENGTH_REG (RLENGTH_REG ) + ); + +// AXI Master Write. +axi_mst_write + #( + .TARGET_SLAVE_BASE_ADDR (TARGET_SLAVE_BASE_ADDR ), + .ID_WIDTH (ID_WIDTH ), + .DATA_WIDTH (DATA_WIDTH ), + .BURST_SIZE (BURST_SIZE ) + ) + axi_mst_write_i + ( + .clk (m_axi_aclk ), + .rstn (m_axi_aresetn ), + + // Trigger. + .trigger (trigger ), + + // AXI Master Interface. + .m_axi_awid (m_axi_awid ), + .m_axi_awaddr (m_axi_awaddr ), + .m_axi_awlen (m_axi_awlen ), + .m_axi_awsize (m_axi_awsize ), + .m_axi_awburst (m_axi_awburst ), + .m_axi_awlock (m_axi_awlock ), + .m_axi_awcache (m_axi_awcache ), + .m_axi_awprot (m_axi_awprot ), + .m_axi_awregion (m_axi_awregion ), + .m_axi_awqos (m_axi_awqos ), + .m_axi_awvalid (m_axi_awvalid ), + .m_axi_awready (m_axi_awready ), + + .m_axi_wdata (m_axi_wdata ), + .m_axi_wstrb (m_axi_wstrb ), + .m_axi_wlast (m_axi_wlast ), + .m_axi_wvalid (m_axi_wvalid ), + .m_axi_wready (m_axi_wready ), + + .m_axi_bid (m_axi_bid ), + .m_axi_bresp (m_axi_bresp ), + .m_axi_bvalid (m_axi_bvalid ), + .m_axi_bready (m_axi_bready ), + + // AXIS Slave Interfase. + .s_axis_tready (s_axis_tready ), + .s_axis_tdata (s_axis_tdata ), + .s_axis_tstrb (s_axis_tstrb ), + .s_axis_tlast (s_axis_tlast ), + .s_axis_tvalid (s_axis_tvalid ), + + // Registers. + .START_REG (WSTART_REG ), + .ADDR_REG (WADDR_REG ), + .NBURST_REG (WNBURST_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_buffer_ddr_v1/src/axi_mst/axi_mst_read.sv b/firmware/ip/axis_buffer_ddr_v1/src/axi_mst/axi_mst_read.sv new file mode 100644 index 0000000..bdadb13 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/axi_mst/axi_mst_read.sv @@ -0,0 +1,251 @@ +module axi_mst_read + #( + // Parameters of AXI Master I/F. + parameter TARGET_SLAVE_BASE_ADDR = 32'h40000000 , + parameter ID_WIDTH = 1 , + parameter DATA_WIDTH = 512 + ) + ( + input wire clk , + input wire rstn , + + // AXI Master Interface. + output wire [ID_WIDTH-1:0] m_axi_arid , + output wire [31:0] m_axi_araddr , + output wire [7:0] m_axi_arlen , + output wire [2:0] m_axi_arsize , + output wire [1:0] m_axi_arburst , + output wire m_axi_arlock , + output wire [3:0] m_axi_arcache , + output wire [2:0] m_axi_arprot , + output wire [3:0] m_axi_arregion , + output wire [3:0] m_axi_arqos , + output wire m_axi_arvalid , + input wire m_axi_arready , + + input wire [ID_WIDTH-1:0] m_axi_rid , + input wire [DATA_WIDTH-1:0] m_axi_rdata , + input wire [1:0] m_axi_rresp , + input wire m_axi_rlast , + input wire m_axi_rvalid , + output wire m_axi_rready , + + // AXIS Master Interfase. + output wire m_axis_tvalid , + output wire [DATA_WIDTH-1:0] m_axis_tdata , + output wire [DATA_WIDTH/8-1:0] m_axis_tstrb , + output wire m_axis_tlast , + input wire m_axis_tready , + + // Registers. + input wire START_REG , + input wire [31:0] ADDR_REG , + input wire [31:0] LENGTH_REG + ); + +/*************/ +/* Internals */ +/*************/ + +// Maximum burst size (4kB boundary). +localparam BYTES_PER_AXI_TRANSFER = DATA_WIDTH/8; +localparam MAX_BURST_SIZE = 4096/BYTES_PER_AXI_TRANSFER; + +// States. +typedef enum { INIT_ST , + START_ST , + READ_REGS_ST , + ADDR_ST , + DATA_ST , + END_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// FSM Signals. +reg read_regs_state ; + +// START_REG resync. +wire start_reg_resync ; + +// Registers. +reg [31:0] addr_reg_r ; +reg [31:0] len_reg_r ; + +// Fifo. +wire fifo_full ; +wire fifo_empty ; + +// AXI Master. +reg axi_arvalid_i ; + +// Address. +wire [31:0] addr_base ; + +// Burst length. +wire [7:0] burst_length ; + +/****************/ +/* Architecture */ +/****************/ + +// start_reg_resync. +synchronizer_n start_reg_resync_i + ( + .rstn (rstn ), + .clk (clk ), + .data_in (START_REG ), + .data_out (start_reg_resync ) + ); + +// Single-clock fifo. +fifo_axi + #( + // Data width. + .B(DATA_WIDTH ), + + // Fifo depth. + .N(64 ) + ) + fifo_i + ( + .rstn (rstn ), + .clk (clk ), + + // Write I/F. + .wr_en (m_axi_rvalid ), + .din (m_axi_rdata ), + + // Read I/F. + .rd_en (m_axis_tready ), + .dout (m_axis_tdata ), + + // Flags. + .full (fifo_full ), + .empty (fifo_empty ) + ); + +assign m_axi_rready = ~fifo_full; +assign m_axis_tvalid = ~fifo_empty; + +// Burst lenth. +//assign burst_length = MAX_BURST_SIZE-1; +assign burst_length = len_reg_r - 1; + +// Base address. +assign addr_base = TARGET_SLAVE_BASE_ADDR + addr_reg_r; + +// Registers. +always @(posedge clk) begin + if (rstn == 1'b0) begin + // State register. + state <= INIT_ST; + + // Registers. + addr_reg_r <= 0; + len_reg_r <= 0; + end + else begin + // State register. + case (state) + INIT_ST: + state <= START_ST; + + START_ST: + if (start_reg_resync == 1'b1) + state <= READ_REGS_ST; + + READ_REGS_ST: + state <= ADDR_ST; + + ADDR_ST: + if (m_axi_arready == 1'b1) + state <= DATA_ST; + DATA_ST: + if (m_axi_rvalid == 1'b1 && m_axi_rlast == 1'b1 && fifo_full == 1'b0) + state <= END_ST; + + END_ST: + if (start_reg_resync == 1'b0) + state <= START_ST; + endcase + + // Registers. + if (read_regs_state == 1'b1) begin + addr_reg_r <= ADDR_REG; + len_reg_r <= LENGTH_REG; + end + + end +end + +// Read Address Channel. +// Same ID for all transactions (execute them in order). +assign m_axi_arid = 0; + +// Burst length (must substract 1). +assign m_axi_arlen = burst_length; + +// Size set to transfer complete data bits per beat (64 bytes/transfer). +assign m_axi_arsize = (BYTES_PER_AXI_TRANSFER == 1 )? 3'b000 : + (BYTES_PER_AXI_TRANSFER == 2 )? 3'b001 : + (BYTES_PER_AXI_TRANSFER == 4 )? 3'b010 : + (BYTES_PER_AXI_TRANSFER == 8 )? 3'b011 : + (BYTES_PER_AXI_TRANSFER == 16 )? 3'b100 : + (BYTES_PER_AXI_TRANSFER == 32 )? 3'b101 : + (BYTES_PER_AXI_TRANSFER == 64 )? 3'b110 : + (BYTES_PER_AXI_TRANSFER == 128 )? 3'b111 : + 3'b000 ; + +// Set arburst to INCR type. +assign m_axi_arburst = 2'b01; + +// Normal access. +assign m_axi_arlock = 1'b0; + +// Device Non-bufferable. +assign m_axi_arcache = 4'b0000; + +// Data, non-secure, unprivileged. +assign m_axi_arprot = 3'b010; + +// Not-used. +assign m_axi_arregion = 4'b0000; + +// Not-used qos. +assign m_axi_arqos = 4'b0000; + +// FSM outputs. +always_comb begin + // Default. + read_regs_state = 1'b0; + axi_arvalid_i = 1'b0; + + case (state) + //INIT_ST: + + //START_ST: + + READ_REGS_ST: + read_regs_state = 1'b1; + + ADDR_ST: + axi_arvalid_i = 1'b1; + + //DATA_ST: + + //END_ST: + + endcase +end + +// Assign outputs. +assign m_axi_araddr = addr_base; +assign m_axi_arvalid = axi_arvalid_i; + +assign m_axis_tstrb = '1; +assign m_axis_tlast = 1'b0; + +endmodule + diff --git a/firmware/ip/axis_buffer_ddr_v1/src/axi_mst/axi_mst_write.sv b/firmware/ip/axis_buffer_ddr_v1/src/axi_mst/axi_mst_write.sv new file mode 100644 index 0000000..4d847b6 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/axi_mst/axi_mst_write.sv @@ -0,0 +1,362 @@ +module axi_mst_write + #( + parameter TARGET_SLAVE_BASE_ADDR = 32'h40000000 , + parameter ID_WIDTH = 1 , + parameter DATA_WIDTH = 32 , + parameter BURST_SIZE = 15 + ) + ( + input wire clk , + input wire rstn , + + // Trigger. + input wire trigger , + + // AXI Master Interface. + output wire [ID_WIDTH-1:0] m_axi_awid , + output wire [31:0] m_axi_awaddr , + output wire [7:0] m_axi_awlen , + output wire [2:0] m_axi_awsize , + output wire [1:0] m_axi_awburst , + output wire m_axi_awlock , + output wire [3:0] m_axi_awcache , + output wire [2:0] m_axi_awprot , + output wire [3:0] m_axi_awregion , + output wire [3:0] m_axi_awqos , + output wire m_axi_awvalid , + input wire m_axi_awready , + + output wire [DATA_WIDTH-1:0] m_axi_wdata , + output wire [DATA_WIDTH/8-1:0] m_axi_wstrb , + output wire m_axi_wlast , + output wire m_axi_wvalid , + input wire m_axi_wready , + + input wire [ID_WIDTH-1:0] m_axi_bid , + input wire [1:0] m_axi_bresp , + input wire m_axi_bvalid , + output wire m_axi_bready , + + // AXIS Slave Interfase. + output wire s_axis_tready , + input wire [DATA_WIDTH-1:0] s_axis_tdata , + input wire [DATA_WIDTH/8-1:0] s_axis_tstrb , + input wire s_axis_tlast , + input wire s_axis_tvalid , + + // Registers. + input wire START_REG , + input wire [31:0] ADDR_REG , + input wire [31:0] NBURST_REG + ); + +// Maximum burst size (4kB boundary). +localparam BYTES_PER_AXI_TRANSFER = DATA_WIDTH/8; +localparam MAX_BURST_SIZE = 4096/BYTES_PER_AXI_TRANSFER; +//localparam BURST_SIZE = (MAX_BURST_SIZE >= 256)? 255 : MAX_BURST_SIZE-1; +localparam BYTES_PER_BURST = (BURST_SIZE + 1)*BYTES_PER_AXI_TRANSFER; + +/*************/ +/* Internals */ +/*************/ + +// States. +typedef enum { INIT_ST , + TRIGGER_ST , + READ_REGS_ST , + INIT_ADDR_ST , + INCR_ADDR_ST , + ADDR_ST , + DATA_ST , + RESP_ST , + NBURST_ST , + TRIGGER_END_ST , + END_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// FSM Signals. +reg read_regs_state ; +reg init_addr_state ; +reg incr_addr_state ; +reg addr_state ; +reg data_state ; +reg resp_state ; + +// trigger resync. +wire trigger_resync ; + +// START_REG resync. +wire start_reg_resync ; + +// Registers. +reg [31:0] addr_reg_r ; +reg [31:0] nburst_reg_r ; + +// Fifo signals. +wire fifo_rd_en ; +wire [DATA_WIDTH-1:0] fifo_dout ; +reg [DATA_WIDTH-1:0] fifo_dout_r ; +wire fifo_full ; +wire fifo_empty ; +reg fifo_empty_r ; + +// Address generation. +wire [31:0] addr_base ; +wire [31:0] addr_acc ; +reg [31:0] addr_r ; + +// Burst counter. +reg [7:0] cnt_burst ; +reg [31:0] cnt_nburst ; + +/****************/ +/* Architecture */ +/****************/ + +// trigger_resync. +synchronizer_n trigger_resync_i + ( + .rstn (rstn ), + .clk (clk ), + .data_in (trigger ), + .data_out (trigger_resync ) + ); + +// start_reg_resync. +synchronizer_n start_reg_resync_i + ( + .rstn (rstn ), + .clk (clk ), + .data_in (START_REG ), + .data_out (start_reg_resync ) + ); + +// Single-clock fifo. +fifo_axi + #( + // Data width. + .B(DATA_WIDTH ), + + // Fifo depth. + .N(16 ) + ) + fifo_in_i + ( + .rstn (rstn ), + .clk (clk ), + + // Write I/F. + .wr_en (s_axis_tvalid ), + .din (s_axis_tdata ), + + // Read I/F. + .rd_en (fifo_rd_en ), + .dout (fifo_dout ), + + // Flags. + .full (fifo_full ), + .empty (fifo_empty ) + ); + +// Fifo connections. +assign fifo_rd_en = m_axi_wready & data_state; +assign s_axis_tready = ~fifo_full; + +// Write Address Channel. +// Same ID for all transactions (execute them in order). +assign m_axi_awid = 0; + +// Burst size (transactions). +assign m_axi_awlen = BURST_SIZE; + +// Size set to transfer complete data bits per beat. +assign m_axi_awsize = (BYTES_PER_AXI_TRANSFER == 1 )? 3'b000 : + (BYTES_PER_AXI_TRANSFER == 2 )? 3'b001 : + (BYTES_PER_AXI_TRANSFER == 4 )? 3'b010 : + (BYTES_PER_AXI_TRANSFER == 8 )? 3'b011 : + (BYTES_PER_AXI_TRANSFER == 16 )? 3'b100 : + (BYTES_PER_AXI_TRANSFER == 32 )? 3'b101 : + (BYTES_PER_AXI_TRANSFER == 64 )? 3'b110 : + (BYTES_PER_AXI_TRANSFER == 128 )? 3'b111 : + 3'b000 ; + +// Set arburst to INCR type. +assign m_axi_awburst = 2'b01; + +// Normal access. +assign m_axi_awlock = 1'b0; + +// Device Non-bufferable. +assign m_axi_awcache = 4'b0000; + +// Data, non-secure, unprivileged. +assign m_axi_awprot = 3'b010; + +// Not-used. +assign m_axi_awregion = 4'b0000; + +// Not-used qos. +assign m_axi_awqos = 4'b0000; + +// Write Data Channel. +// All bytes are written. +assign m_axi_wstrb = '1; + +// Address generation. +assign addr_base = TARGET_SLAVE_BASE_ADDR + addr_reg_r; +assign addr_acc = addr_r + BYTES_PER_BURST; + +// Registers. +always @(posedge clk) begin + if (rstn == 1'b0) begin + // State register. + state <= INIT_ST; + + // Registers. + addr_reg_r <= 0; + nburst_reg_r <= 0; + addr_r <= 0; + + // Fifo signals. + fifo_dout_r <= 0; + fifo_empty_r <= 1; + + // Burst counter. + cnt_burst <= 0; + cnt_nburst <= 0; + end + else begin + // State register. + case (state) + INIT_ST: + if (start_reg_resync == 1'b1) + state <= TRIGGER_ST; + + TRIGGER_ST: + if (trigger_resync == 1'b1) + state <= READ_REGS_ST; + + READ_REGS_ST: + state <= INIT_ADDR_ST; + + INIT_ADDR_ST: + state <= ADDR_ST; + + INCR_ADDR_ST: + state <= ADDR_ST; + + ADDR_ST: + if (m_axi_awready == 1'b1) + state <= DATA_ST; + + DATA_ST: + if ( (m_axi_wready == 1'b1) && (m_axi_wvalid == 1'b1) && (cnt_burst == BURST_SIZE) ) + state <= RESP_ST; + + RESP_ST: + if (m_axi_bvalid == 1'b1) + state <= NBURST_ST; + + NBURST_ST: + if (cnt_nburst == nburst_reg_r) + state <= TRIGGER_END_ST; + else + state <= INCR_ADDR_ST; + + TRIGGER_END_ST: + if (trigger_resync == 1'b0) + state <= END_ST; + + END_ST: + if (start_reg_resync == 1'b0) + state <= INIT_ST; + endcase + + // Registers. + if (read_regs_state == 1'b1) begin + addr_reg_r <= ADDR_REG; + nburst_reg_r <= NBURST_REG; + end + + // Address generation. + if (init_addr_state == 1'b1) + addr_r <= addr_base; + else if (incr_addr_state == 1'b1) + addr_r <= addr_acc; + + // Fifo signals. + if (fifo_rd_en == 1'b1) begin + fifo_dout_r <= fifo_dout; + fifo_empty_r <= fifo_empty; + end + + // Burst counter. + if (addr_state == 1'b1) + cnt_burst <= 0; + else if (m_axi_wvalid == 1'b1 && m_axi_wready == 1'b1) + cnt_burst <= cnt_burst + 1; + if (read_regs_state == 1'b1) + cnt_nburst <= 0; + else if (m_axi_bvalid == 1'b1 && m_axi_bready == 1'b1) + cnt_nburst <= cnt_nburst + 1; + end +end + +// FSM outputs. +always_comb begin + // Default. + read_regs_state = 1'b0; + init_addr_state = 1'b0; + incr_addr_state = 1'b0; + addr_state = 1'b0; + data_state = 1'b0; + resp_state = 1'b0; + + case (state) + //INIT_ST: + + //TRIGGER_ST: + + READ_REGS_ST: + read_regs_state = 1'b1; + + INIT_ADDR_ST: + init_addr_state = 1'b1; + + INCR_ADDR_ST: + incr_addr_state = 1'b1; + + ADDR_ST: + addr_state = 1'b1; + + DATA_ST: + data_state = 1'b1; + + RESP_ST: + resp_state = 1'b1; + + //NBURST_ST: + + //TRIGGER_END_ST: + + //END_ST: + + endcase +end + +// Assign outputs. +assign m_axi_awaddr = addr_r; +assign m_axi_awvalid = addr_state; + +assign m_axi_wdata = fifo_dout_r; +assign m_axi_wlast = (cnt_burst == BURST_SIZE)? 1'b1 : 1'b0; +assign m_axi_wvalid = ~fifo_empty_r & data_state; + +assign m_axi_bready = resp_state; + + +endmodule + diff --git a/firmware/ip/axis_buffer_ddr_v1/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_buffer_ddr_v1/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..bf3f000 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,318 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + + 100000000 + 0 + 0 + 0.0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 12 + TRUE + ../project_1/project_1.gen/sources_1/ip/axi_mst_0 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_buffer_ddr_v1/src/axi_slv.v b/firmware/ip/axis_buffer_ddr_v1/src/axi_slv.v new file mode 100644 index 0000000..0aed488 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/axi_slv.v @@ -0,0 +1,1032 @@ +module axi_slv + ( + input wire s_axi_aclk , + input wire s_axi_aresetn , + + // Write Address Channel. + input wire [7:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + + // Write Data Channel. + input wire [31:0] s_axi_wdata , + input wire [3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + + // Write Response Channel. + output wire [1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + + // Read Address Channel. + input wire [7:0] s_axi_araddr , + input wire [2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + + // Read Data Channel. + output wire [31:0] s_axi_rdata , + output wire [1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , + + // Registers. + output wire RSTART_REG , + output wire [31:0] RADDR_REG , + output wire [31:0] RLENGTH_REG , + output wire WSTART_REG , + output wire [31:0] WADDR_REG , + output wire [31:0] WNBURST_REG +); + +// Width of S_AXI data bus +localparam integer C_S_AXI_DATA_WIDTH = 32; +// Width of S_AXI address bus +localparam integer C_S_AXI_ADDR_WIDTH = 8; + +// AXI4LITE signals +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr; +reg axi_awready; +reg axi_wready; +reg [1 : 0] axi_bresp; +reg axi_bvalid; +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr; +reg axi_arready; +reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata; +reg [1 : 0] axi_rresp; +reg axi_rvalid; + +// Example-specific design signals +// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH +// ADDR_LSB is used for addressing 32/64 bit registers/memories +// ADDR_LSB = 2 for 32 bits (n downto 2) +// ADDR_LSB = 3 for 64 bits (n downto 3) +localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1; +localparam integer OPT_MEM_ADDR_BITS = 5; +//---------------------------------------------- +//-- Signals for user logic register space example +//------------------------------------------------ +//-- Number of Slave Registers 64 +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg32; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg33; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg34; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg35; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg36; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg37; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg38; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg39; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg40; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg41; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg42; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg43; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg44; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg45; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg46; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg47; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg48; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg49; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg50; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg51; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg52; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg53; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg54; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg55; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg56; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg57; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg58; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg59; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg60; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg61; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg62; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg63; +wire slv_reg_rden; +wire slv_reg_wren; +reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out; +integer byte_index; +reg aw_en; + +// I/O Connections assignments + +assign s_axi_awready = axi_awready; +assign s_axi_wready = axi_wready; +assign s_axi_bresp = axi_bresp; +assign s_axi_bvalid = axi_bvalid; +assign s_axi_arready = axi_arready; +assign s_axi_rdata = axi_rdata; +assign s_axi_rresp = axi_rresp; +assign s_axi_rvalid = axi_rvalid; +// Implement axi_awready generation +// axi_awready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_awready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awready <= 1'b0; + aw_en <= 1'b1; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // slave is ready to accept write address when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_awready <= 1'b1; + aw_en <= 1'b0; + end + else if (s_axi_bready && axi_bvalid) + begin + aw_en <= 1'b1; + axi_awready <= 1'b0; + end + else + begin + axi_awready <= 1'b0; + end + end +end + +// Implement axi_awaddr latching +// This process is used to latch the address when both +// s_axi_awvalid and s_axi_wvalid are valid. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awaddr <= 0; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // Write Address latching + axi_awaddr <= s_axi_awaddr; + end + end +end + +// Implement axi_wready generation +// axi_wready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_wready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_wready <= 1'b0; + end + else + begin + if (~axi_wready && s_axi_wvalid && s_axi_awvalid && aw_en ) + begin + // slave is ready to accept write data when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_wready <= 1'b1; + end + else + begin + axi_wready <= 1'b0; + end + end +end + +// Implement memory mapped register select and write logic generation +// The write data is accepted and written to memory mapped registers when +// axi_awready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. Write strobes are used to +// select byte enables of slave registers while writing. +// These registers are cleared when reset (active low) is applied. +// Slave register write enable is asserted when valid address and data are available +// and the slave is ready to accept the write address and write data. +assign slv_reg_wren = axi_wready && s_axi_wvalid && axi_awready && s_axi_awvalid; + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + slv_reg0 <= 0; + slv_reg1 <= 0; + slv_reg2 <= 0; + slv_reg3 <= 0; + slv_reg4 <= 0; + slv_reg5 <= 0; + slv_reg6 <= 0; + slv_reg7 <= 0; + slv_reg8 <= 0; + slv_reg9 <= 0; + slv_reg10 <= 0; + slv_reg11 <= 0; + slv_reg12 <= 0; + slv_reg13 <= 0; + slv_reg14 <= 0; + slv_reg15 <= 0; + slv_reg16 <= 0; + slv_reg17 <= 0; + slv_reg18 <= 0; + slv_reg19 <= 0; + slv_reg20 <= 0; + slv_reg21 <= 0; + slv_reg22 <= 0; + slv_reg23 <= 0; + slv_reg24 <= 0; + slv_reg25 <= 0; + slv_reg26 <= 0; + slv_reg27 <= 0; + slv_reg28 <= 0; + slv_reg29 <= 0; + slv_reg30 <= 0; + slv_reg31 <= 0; + slv_reg32 <= 0; + slv_reg33 <= 0; + slv_reg34 <= 0; + slv_reg35 <= 0; + slv_reg36 <= 0; + slv_reg37 <= 0; + slv_reg38 <= 0; + slv_reg39 <= 0; + slv_reg40 <= 0; + slv_reg41 <= 0; + slv_reg42 <= 0; + slv_reg43 <= 0; + slv_reg44 <= 0; + slv_reg45 <= 0; + slv_reg46 <= 0; + slv_reg47 <= 0; + slv_reg48 <= 0; + slv_reg49 <= 0; + slv_reg50 <= 0; + slv_reg51 <= 0; + slv_reg52 <= 0; + slv_reg53 <= 0; + slv_reg54 <= 0; + slv_reg55 <= 0; + slv_reg56 <= 0; + slv_reg57 <= 0; + slv_reg58 <= 0; + slv_reg59 <= 0; + slv_reg60 <= 0; + slv_reg61 <= 0; + slv_reg62 <= 0; + slv_reg63 <= 0; + end + else begin + if (slv_reg_wren) + begin + case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 0 + slv_reg0[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h01: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 1 + slv_reg1[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h02: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 2 + slv_reg2[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h03: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 3 + slv_reg3[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h04: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 4 + slv_reg4[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h05: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 5 + slv_reg5[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h06: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 6 + slv_reg6[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h07: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 7 + slv_reg7[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h08: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 8 + slv_reg8[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h09: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 9 + slv_reg9[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 10 + slv_reg10[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 11 + slv_reg11[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 12 + slv_reg12[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 13 + slv_reg13[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 14 + slv_reg14[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 15 + slv_reg15[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h10: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 16 + slv_reg16[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h11: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 17 + slv_reg17[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h12: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 18 + slv_reg18[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h13: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 19 + slv_reg19[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h14: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 20 + slv_reg20[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h15: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 21 + slv_reg21[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h16: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 22 + slv_reg22[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h17: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 23 + slv_reg23[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h18: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 24 + slv_reg24[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h19: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 25 + slv_reg25[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 26 + slv_reg26[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 27 + slv_reg27[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 28 + slv_reg28[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 29 + slv_reg29[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 30 + slv_reg30[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 31 + slv_reg31[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h20: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 32 + slv_reg32[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h21: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 33 + slv_reg33[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h22: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 34 + slv_reg34[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h23: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 35 + slv_reg35[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h24: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 36 + slv_reg36[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h25: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 37 + slv_reg37[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h26: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 38 + slv_reg38[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h27: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 39 + slv_reg39[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h28: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 40 + slv_reg40[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h29: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 41 + slv_reg41[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 42 + slv_reg42[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 43 + slv_reg43[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 44 + slv_reg44[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 45 + slv_reg45[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 46 + slv_reg46[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 47 + slv_reg47[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h30: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 48 + slv_reg48[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h31: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 49 + slv_reg49[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h32: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 50 + slv_reg50[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h33: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 51 + slv_reg51[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h34: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 52 + slv_reg52[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h35: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 53 + slv_reg53[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h36: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 54 + slv_reg54[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h37: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 55 + slv_reg55[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h38: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 56 + slv_reg56[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h39: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 57 + slv_reg57[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 58 + slv_reg58[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 59 + slv_reg59[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 60 + slv_reg60[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 61 + slv_reg61[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 62 + slv_reg62[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 63 + slv_reg63[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + default : begin + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + slv_reg16 <= slv_reg16; + slv_reg17 <= slv_reg17; + slv_reg18 <= slv_reg18; + slv_reg19 <= slv_reg19; + slv_reg20 <= slv_reg20; + slv_reg21 <= slv_reg21; + slv_reg22 <= slv_reg22; + slv_reg23 <= slv_reg23; + slv_reg24 <= slv_reg24; + slv_reg25 <= slv_reg25; + slv_reg26 <= slv_reg26; + slv_reg27 <= slv_reg27; + slv_reg28 <= slv_reg28; + slv_reg29 <= slv_reg29; + slv_reg30 <= slv_reg30; + slv_reg31 <= slv_reg31; + slv_reg32 <= slv_reg32; + slv_reg33 <= slv_reg33; + slv_reg34 <= slv_reg34; + slv_reg35 <= slv_reg35; + slv_reg36 <= slv_reg36; + slv_reg37 <= slv_reg37; + slv_reg38 <= slv_reg38; + slv_reg39 <= slv_reg39; + slv_reg40 <= slv_reg40; + slv_reg41 <= slv_reg41; + slv_reg42 <= slv_reg42; + slv_reg43 <= slv_reg43; + slv_reg44 <= slv_reg44; + slv_reg45 <= slv_reg45; + slv_reg46 <= slv_reg46; + slv_reg47 <= slv_reg47; + slv_reg48 <= slv_reg48; + slv_reg49 <= slv_reg49; + slv_reg50 <= slv_reg50; + slv_reg51 <= slv_reg51; + slv_reg52 <= slv_reg52; + slv_reg53 <= slv_reg53; + slv_reg54 <= slv_reg54; + slv_reg55 <= slv_reg55; + slv_reg56 <= slv_reg56; + slv_reg57 <= slv_reg57; + slv_reg58 <= slv_reg58; + slv_reg59 <= slv_reg59; + slv_reg60 <= slv_reg60; + slv_reg61 <= slv_reg61; + slv_reg62 <= slv_reg62; + slv_reg63 <= slv_reg63; + end + endcase + end + end +end + +// Implement write response logic generation +// The write response and response valid signals are asserted by the slave +// when axi_wready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. +// This marks the acceptance of address and indicates the status of +// write transaction. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_bvalid <= 0; + axi_bresp <= 2'b0; + end + else + begin + if (axi_awready && s_axi_awvalid && ~axi_bvalid && axi_wready && s_axi_wvalid) + begin + // indicates a valid write response is available + axi_bvalid <= 1'b1; + axi_bresp <= 2'b0; // 'OKAY' response + end // work error responses in future + else + begin + if (s_axi_bready && axi_bvalid) + //check if bready is asserted while bvalid is high) + //(there is a possibility that bready is always asserted high) + begin + axi_bvalid <= 1'b0; + end + end + end +end + +// Implement axi_arready generation +// axi_arready is asserted for one s_axi_aclk clock cycle when +// s_axi_arvalid is asserted. axi_awready is +// de-asserted when reset (active low) is asserted. +// The read address is also latched when s_axi_arvalid is +// asserted. axi_araddr is reset to zero on reset assertion. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_arready <= 1'b0; + axi_araddr <= 32'b0; + end + else + begin + if (~axi_arready && s_axi_arvalid) + begin + // indicates that the slave has acceped the valid read address + axi_arready <= 1'b1; + // Read address latching + axi_araddr <= s_axi_araddr; + end + else + begin + axi_arready <= 1'b0; + end + end +end + +// Implement axi_arvalid generation +// axi_rvalid is asserted for one s_axi_aclk clock cycle when both +// s_axi_arvalid and axi_arready are asserted. The slave registers +// data are available on the axi_rdata bus at this instance. The +// assertion of axi_rvalid marks the validity of read data on the +// bus and axi_rresp indicates the status of read transaction.axi_rvalid +// is deasserted on reset (active low). axi_rresp and axi_rdata are +// cleared to zero on reset (active low). +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rvalid <= 0; + axi_rresp <= 0; + end + else + begin + if (axi_arready && s_axi_arvalid && ~axi_rvalid) + begin + // Valid read data is available at the read data bus + axi_rvalid <= 1'b1; + axi_rresp <= 2'b0; // 'OKAY' response + end + else if (axi_rvalid && s_axi_rready) + begin + // Read data is accepted by the master + axi_rvalid <= 1'b0; + end + end +end + +// Implement memory mapped register select and read logic generation +// Slave register read enable is asserted when valid address is available +// and the slave is ready to accept the read address. +assign slv_reg_rden = axi_arready & s_axi_arvalid & ~axi_rvalid; +always @(*) +begin + // Address decoding for reading registers + case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00 : reg_data_out <= slv_reg0; + 6'h01 : reg_data_out <= slv_reg1; + 6'h02 : reg_data_out <= slv_reg2; + 6'h03 : reg_data_out <= slv_reg3; + 6'h04 : reg_data_out <= slv_reg4; + 6'h05 : reg_data_out <= slv_reg5; + 6'h06 : reg_data_out <= slv_reg6; + 6'h07 : reg_data_out <= slv_reg7; + 6'h08 : reg_data_out <= slv_reg8; + 6'h09 : reg_data_out <= slv_reg9; + 6'h0A : reg_data_out <= slv_reg10; + 6'h0B : reg_data_out <= slv_reg11; + 6'h0C : reg_data_out <= slv_reg12; + 6'h0D : reg_data_out <= slv_reg13; + 6'h0E : reg_data_out <= slv_reg14; + 6'h0F : reg_data_out <= slv_reg15; + 6'h10 : reg_data_out <= slv_reg16; + 6'h11 : reg_data_out <= slv_reg17; + 6'h12 : reg_data_out <= slv_reg18; + 6'h13 : reg_data_out <= slv_reg19; + 6'h14 : reg_data_out <= slv_reg20; + 6'h15 : reg_data_out <= slv_reg21; + 6'h16 : reg_data_out <= slv_reg22; + 6'h17 : reg_data_out <= slv_reg23; + 6'h18 : reg_data_out <= slv_reg24; + 6'h19 : reg_data_out <= slv_reg25; + 6'h1A : reg_data_out <= slv_reg26; + 6'h1B : reg_data_out <= slv_reg27; + 6'h1C : reg_data_out <= slv_reg28; + 6'h1D : reg_data_out <= slv_reg29; + 6'h1E : reg_data_out <= slv_reg30; + 6'h1F : reg_data_out <= slv_reg31; + 6'h20 : reg_data_out <= slv_reg32; + 6'h21 : reg_data_out <= slv_reg33; + 6'h22 : reg_data_out <= slv_reg34; + 6'h23 : reg_data_out <= slv_reg35; + 6'h24 : reg_data_out <= slv_reg36; + 6'h25 : reg_data_out <= slv_reg37; + 6'h26 : reg_data_out <= slv_reg38; + 6'h27 : reg_data_out <= slv_reg39; + 6'h28 : reg_data_out <= slv_reg40; + 6'h29 : reg_data_out <= slv_reg41; + 6'h2A : reg_data_out <= slv_reg42; + 6'h2B : reg_data_out <= slv_reg43; + 6'h2C : reg_data_out <= slv_reg44; + 6'h2D : reg_data_out <= slv_reg45; + 6'h2E : reg_data_out <= slv_reg46; + 6'h2F : reg_data_out <= slv_reg47; + 6'h30 : reg_data_out <= slv_reg48; + 6'h31 : reg_data_out <= slv_reg49; + 6'h32 : reg_data_out <= slv_reg50; + 6'h33 : reg_data_out <= slv_reg51; + 6'h34 : reg_data_out <= slv_reg52; + 6'h35 : reg_data_out <= slv_reg53; + 6'h36 : reg_data_out <= slv_reg54; + 6'h37 : reg_data_out <= slv_reg55; + 6'h38 : reg_data_out <= slv_reg56; + 6'h39 : reg_data_out <= slv_reg57; + 6'h3A : reg_data_out <= slv_reg58; + 6'h3B : reg_data_out <= slv_reg59; + 6'h3C : reg_data_out <= slv_reg60; + 6'h3D : reg_data_out <= slv_reg61; + 6'h3E : reg_data_out <= slv_reg62; + 6'h3F : reg_data_out <= slv_reg63; + default : reg_data_out <= 0; + endcase +end + +// Output register or memory read data +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rdata <= 0; + end + else + begin + // When there is a valid read address (s_axi_arvalid) with + // acceptance of read address by the slave (axi_arready), + // output the read dada + if (slv_reg_rden) + begin + axi_rdata <= reg_data_out; // register read data + end + end +end + +assign RSTART_REG = slv_reg0 [0]; +assign RADDR_REG = slv_reg1 [31:0]; +assign RLENGTH_REG = slv_reg2 [31:0]; +assign WSTART_REG = slv_reg3 [0]; +assign WADDR_REG = slv_reg4 [31:0]; +assign WNBURST_REG = slv_reg5 [31:0]; + +endmodule diff --git a/firmware/ip/axis_buffer_ddr_v1/src/axi_slv_0/axi_slv_0.xcix b/firmware/ip/axis_buffer_ddr_v1/src/axi_slv_0/axi_slv_0.xcix new file mode 100644 index 0000000..5e6a788 Binary files /dev/null and b/firmware/ip/axis_buffer_ddr_v1/src/axi_slv_0/axi_slv_0.xcix differ diff --git a/firmware/ip/axis_buffer_ddr_v1/src/axis_buffer_ddr_v1.sv b/firmware/ip/axis_buffer_ddr_v1/src/axis_buffer_ddr_v1.sv new file mode 100644 index 0000000..7b2efa2 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/axis_buffer_ddr_v1.sv @@ -0,0 +1,275 @@ +module axis_buffer_ddr_v1 + #( + // Parameters of AXI Master I/F. + parameter TARGET_SLAVE_BASE_ADDR = 32'h40000000 , + parameter ID_WIDTH = 1 , + parameter DATA_WIDTH = 512 , + parameter BURST_SIZE = 15 + ) + ( + // Trigger. + input wire trigger , + + /***********************************/ + /* AXI Slave I/F for configuration */ + /***********************************/ + input wire s_axi_aclk , + input wire s_axi_aresetn , + + input wire [7:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + + input wire [31:0] s_axi_wdata , + input wire [3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + + output wire [1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + + input wire [7:0] s_axi_araddr , + input wire [2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + + output wire [31:0] s_axi_rdata , + output wire [1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , + + // Reset and Clock (m_axi, s_axis, m_axis). + input wire aclk , + input wire aresetn , + + /***********************/ + /* AXI Master for DDR4 */ + /***********************/ + + // Write Address Channel. + output wire [ID_WIDTH-1:0] m_axi_awid , + output wire [31:0] m_axi_awaddr , + output wire [7:0] m_axi_awlen , + output wire [2:0] m_axi_awsize , + output wire [1:0] m_axi_awburst , + output wire m_axi_awlock , + output wire [3:0] m_axi_awcache , + output wire [2:0] m_axi_awprot , + output wire [3:0] m_axi_awregion , + output wire [3:0] m_axi_awqos , + output wire m_axi_awvalid , + input wire m_axi_awready , + + // Write Data Channel. + output wire [DATA_WIDTH-1:0] m_axi_wdata , + output wire [DATA_WIDTH/8-1:0] m_axi_wstrb , + output wire m_axi_wlast , + output wire m_axi_wvalid , + input wire m_axi_wready , + + // Write Response Channel. + input wire [ID_WIDTH-1:0] m_axi_bid , + input wire [1:0] m_axi_bresp , + input wire m_axi_bvalid , + output wire m_axi_bready , + + // Read Address Channel. + output wire [ID_WIDTH-1:0] m_axi_arid , + output wire [31:0] m_axi_araddr , + output wire [7:0] m_axi_arlen , + output wire [2:0] m_axi_arsize , + output wire [1:0] m_axi_arburst , + output wire m_axi_arlock , + output wire [3:0] m_axi_arcache , + output wire [2:0] m_axi_arprot , + output wire [3:0] m_axi_arregion , + output wire [3:0] m_axi_arqos , + output wire m_axi_arvalid , + input wire m_axi_arready , + + // Read Data Channel. + input wire [ID_WIDTH-1:0] m_axi_rid , + input wire [DATA_WIDTH-1:0] m_axi_rdata , + input wire [1:0] m_axi_rresp , + input wire m_axi_rlast , + input wire m_axi_rvalid , + output wire m_axi_rready , + + /*************************/ + /* AXIS Master Interfase */ + /*************************/ + output wire m_axis_tvalid , + output wire [DATA_WIDTH-1:0] m_axis_tdata , + output wire [DATA_WIDTH/8-1:0] m_axis_tstrb , + output wire m_axis_tlast , + input wire m_axis_tready , + + /************************/ + /* AXIS Slave Interfase */ + /************************/ + output wire s_axis_tready , + input wire [DATA_WIDTH-1:0] s_axis_tdata , + input wire [DATA_WIDTH/8-1:0] s_axis_tstrb , + input wire s_axis_tlast , + input wire s_axis_tvalid + ); + +/********************/ +/* Internal signals */ +/********************/ + +// Registers. +wire RSTART_REG ; +wire [31:0] RADDR_REG ; +wire [31:0] RLENGTH_REG ; +wire WSTART_REG ; +wire [31:0] WADDR_REG ; +wire [31:0] WNBURST_REG ; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + + // Write Address Channel. + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_awready (s_axi_awready ), + + // Write Data Channel. + .s_axi_wdata (s_axi_wdata ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + .s_axi_wready (s_axi_wready ), + + // Write Response Channel. + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_bready (s_axi_bready ), + + // Read Address Channel. + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_arready (s_axi_arready ), + + // Read Data Channel. + .s_axi_rdata (s_axi_rdata ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_rready (s_axi_rready ), + + // Registers. + .RSTART_REG (RSTART_REG ), + .RADDR_REG (RADDR_REG ), + .RLENGTH_REG (RLENGTH_REG ), + .WSTART_REG (WSTART_REG ), + .WADDR_REG (WADDR_REG ), + .WNBURST_REG (WNBURST_REG ) + ); + +axi_mst + #( + // Parameters of AXI Master I/F. + .TARGET_SLAVE_BASE_ADDR (TARGET_SLAVE_BASE_ADDR ), + .ID_WIDTH (ID_WIDTH ), + .DATA_WIDTH (DATA_WIDTH ), + .BURST_SIZE (BURST_SIZE ) + ) + axi_mst_i + ( + // Trigger. + .trigger (trigger ), + + /**************/ + /* AXI Master */ + /**************/ + + // Reset and Clock. + .m_axi_aclk (aclk ), + .m_axi_aresetn (aresetn ), + + // Write Address Channel. + .m_axi_awid (m_axi_awid ), + .m_axi_awaddr (m_axi_awaddr ), + .m_axi_awlen (m_axi_awlen ), + .m_axi_awsize (m_axi_awsize ), + .m_axi_awburst (m_axi_awburst ), + .m_axi_awlock (m_axi_awlock ), + .m_axi_awcache (m_axi_awcache ), + .m_axi_awprot (m_axi_awprot ), + .m_axi_awregion (m_axi_awregion ), + .m_axi_awqos (m_axi_awqos ), + .m_axi_awvalid (m_axi_awvalid ), + .m_axi_awready (m_axi_awready ), + + // Write Data Channel. + .m_axi_wdata (m_axi_wdata ), + .m_axi_wstrb (m_axi_wstrb ), + .m_axi_wlast (m_axi_wlast ), + .m_axi_wvalid (m_axi_wvalid ), + .m_axi_wready (m_axi_wready ), + + // Write Response Channel. + .m_axi_bid (m_axi_bid ), + .m_axi_bresp (m_axi_bresp ), + .m_axi_bvalid (m_axi_bvalid ), + .m_axi_bready (m_axi_bready ), + + // Read Address Channel. + .m_axi_arid (m_axi_arid ), + .m_axi_araddr (m_axi_araddr ), + .m_axi_arlen (m_axi_arlen ), + .m_axi_arsize (m_axi_arsize ), + .m_axi_arburst (m_axi_arburst ), + .m_axi_arlock (m_axi_arlock ), + .m_axi_arcache (m_axi_arcache ), + .m_axi_arprot (m_axi_arprot ), + .m_axi_arregion (m_axi_arregion ), + .m_axi_arqos (m_axi_arqos ), + .m_axi_arvalid (m_axi_arvalid ), + .m_axi_arready (m_axi_arready ), + + // Read Data Channel. + .m_axi_rid (m_axi_rid ), + .m_axi_rdata (m_axi_rdata ), + .m_axi_rresp (m_axi_rresp ), + .m_axi_rlast (m_axi_rlast ), + .m_axi_rvalid (m_axi_rvalid ), + .m_axi_rready (m_axi_rready ), + + /*************************/ + /* AXIS Master Interfase */ + /*************************/ + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ), + .m_axis_tstrb (m_axis_tstrb ), + .m_axis_tlast (m_axis_tlast ), + .m_axis_tready (m_axis_tready ), + + /************************/ + /* AXIS Slave Interfase */ + /************************/ + .s_axis_tready (s_axis_tready ), + .s_axis_tdata (s_axis_tdata ), + .s_axis_tstrb (s_axis_tstrb ), + .s_axis_tlast (s_axis_tlast ), + .s_axis_tvalid (s_axis_tvalid ), + + // Registers. + .RSTART_REG (RSTART_REG ), + .RADDR_REG (RADDR_REG ), + .RLENGTH_REG (RLENGTH_REG ), + .WSTART_REG (WSTART_REG ), + .WADDR_REG (WADDR_REG ), + .WNBURST_REG (WNBURST_REG ) + ); +endmodule + diff --git a/firmware/ip/axis_buffer_ddr_v1/src/fifo/bin2gray.vhd b/firmware/ip/axis_buffer_ddr_v1/src/fifo/bin2gray.vhd new file mode 100644 index 0000000..4ecc09b --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/fifo/bin2gray.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end bin2gray; + +architecture rtl of bin2gray is + +signal gray : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +gray(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + gray(I) <= din(I+1) xor din(I); +end generate; + +-- Assign output. +dout <= gray; + +end rtl; + diff --git a/firmware/ip/axis_buffer_ddr_v1/src/fifo/bram_dp.vhd b/firmware/ip/axis_buffer_ddr_v1/src/fifo/bram_dp.vhd new file mode 100644 index 0000000..d57aad1 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/fifo/bram_dp.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture rtl of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_buffer_ddr_v1/src/fifo/bram_simple_dp.vhd b/firmware/ip/axis_buffer_ddr_v1/src/fifo/bram_simple_dp.vhd new file mode 100644 index 0000000..1494332 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/fifo/bram_simple_dp.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_simple_dp; + +architecture rtl of bram_simple_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_buffer_ddr_v1/src/fifo/fifo.vhd b/firmware/ip/axis_buffer_ddr_v1/src/fifo/fifo.vhd new file mode 100644 index 0000000..957362b --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/fifo/fifo.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture rtl of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Dual port, single clock BRAM. +component bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- FIFO memory. +mem_i : bram_simple_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_buffer_ddr_v1/src/fifo/fifo_axi.vhd b/firmware/ip/axis_buffer_ddr_v1/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_buffer_ddr_v1/src/fifo/fifo_dc.vhd b/firmware/ip/axis_buffer_ddr_v1/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_buffer_ddr_v1/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_buffer_ddr_v1/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_buffer_ddr_v1/src/fifo/gray2bin.vhd b/firmware/ip/axis_buffer_ddr_v1/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_buffer_ddr_v1/src/fifo/rd2axi.vhd b/firmware/ip/axis_buffer_ddr_v1/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_buffer_ddr_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_buffer_ddr_v1/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_buffer_ddr_v1/src/synchronizer_n.vhd b/firmware/ip/axis_buffer_ddr_v1/src/synchronizer_n.vhd new file mode 100644 index 0000000..925425d --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/synchronizer_n.vhd @@ -0,0 +1,42 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library common_lib; +use common_lib.all; + +entity synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end synchronizer_n; + +architecture rtl of synchronizer_n is + +-- Internal register. +signal data_int_reg : std_logic_vector (N-1 downto 0); + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_buffer_ddr_v1/src/tb/tb.sv b/firmware/ip/axis_buffer_ddr_v1/src/tb/tb.sv new file mode 100644 index 0000000..75a3622 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/tb/tb.sv @@ -0,0 +1,451 @@ +import axi_vip_pkg::*; +import axi_slv_0_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter TARGET_SLAVE_BASE_ADDR = 32'h40000000; +parameter ID_WIDTH = 1; +parameter DATA_WIDTH = 256; + +// Trigger. +reg trigger ; + +/***********************************/ +/* AXI Slave I/F for configuration */ +/***********************************/ +reg s_axi_aclk ; +reg s_axi_aresetn ; + +wire [7:0] s_axi_awaddr ; +wire [2:0] s_axi_awprot ; +wire s_axi_awvalid ; +wire s_axi_awready ; + +wire [31:0] s_axi_wdata ; +wire [3:0] s_axi_wstrb ; +wire s_axi_wvalid ; +wire s_axi_wready ; + +wire [1:0] s_axi_bresp ; +wire s_axi_bvalid ; +wire s_axi_bready ; + +wire [7:0] s_axi_araddr ; +wire [2:0] s_axi_arprot ; +wire s_axi_arvalid ; +wire s_axi_arready ; + +wire [31:0] s_axi_rdata ; +wire [1:0] s_axi_rresp ; +wire s_axi_rvalid ; +wire s_axi_rready ; + +// Reset and Clock (m_axi, s_axis, m_axis). +reg aclk ; +reg aresetn ; + +/***********************/ +/* AXI Master for DDR4 */ +/***********************/ + +// Write Address Channel. +wire [ID_WIDTH-1:0] m_axi_awid ; +wire [31:0] m_axi_awaddr ; +wire [7:0] m_axi_awlen ; +wire [2:0] m_axi_awsize ; +wire [1:0] m_axi_awburst ; +wire m_axi_awlock ; +wire [3:0] m_axi_awcache ; +wire [2:0] m_axi_awprot ; +wire [3:0] m_axi_awregion ; +wire [3:0] m_axi_awqos ; +wire m_axi_awvalid ; +wire m_axi_awready ; + +// Write Data Channel. +wire [DATA_WIDTH-1:0] m_axi_wdata ; +wire [DATA_WIDTH/8-1:0] m_axi_wstrb ; +wire m_axi_wlast ; +wire m_axi_wvalid ; +wire m_axi_wready ; + +// Write Response Channel. +wire [ID_WIDTH-1:0] m_axi_bid ; +wire [1:0] m_axi_bresp ; +wire m_axi_bvalid ; +wire m_axi_bready ; + +// Read Address Channel. +wire [ID_WIDTH-1:0] m_axi_arid ; +wire [31:0] m_axi_araddr ; +wire [7:0] m_axi_arlen ; +wire [2:0] m_axi_arsize ; +wire [1:0] m_axi_arburst ; +wire m_axi_arlock ; +wire [3:0] m_axi_arcache ; +wire [2:0] m_axi_arprot ; +wire [3:0] m_axi_arregion ; +wire [3:0] m_axi_arqos ; +wire m_axi_arvalid ; +wire m_axi_arready ; + +// Read Data Channel. +wire [ID_WIDTH-1:0] m_axi_rid ; +wire [DATA_WIDTH-1:0] m_axi_rdata ; +wire [1:0] m_axi_rresp ; +wire m_axi_rlast ; +wire m_axi_rvalid ; +wire m_axi_rready ; + +/*************************/ +/* AXIS Master Interfase */ +/*************************/ +wire m_axis_tvalid ; +wire [DATA_WIDTH-1:0] m_axis_tdata ; +wire [DATA_WIDTH/8-1:0] m_axis_tstrb ; +wire m_axis_tlast ; +reg m_axis_tready ; + +/************************/ +/* AXIS Slave Interfase */ +/************************/ +wire s_axis_tready ; +reg [DATA_WIDTH-1:0] s_axis_tdata ; +reg [DATA_WIDTH/8-1:0] s_axis_tstrb ; +reg s_axis_tlast ; +reg s_axis_tvalid ; + +xil_axi_prot_t prot = 0; +reg[31:0] data; +reg [DATA_WIDTH-1:0] data_mem; +xil_axi_resp_t resp; + +// TB control. +reg tb_din_start = 0; +reg tb_dout_start = 0; + +// AXI Slave. +axi_slv_0 axi_slv_0_i + ( + .aclk (aclk ), + .aresetn (aresetn ), + + .s_axi_araddr (m_axi_araddr ), + .s_axi_arburst (m_axi_arburst ), + .s_axi_arcache (m_axi_arcache ), + .s_axi_arid (m_axi_arid ), + .s_axi_arlen (m_axi_arlen ), + .s_axi_arlock (m_axi_arlock ), + .s_axi_arprot (m_axi_arprot ), + .s_axi_arqos (m_axi_arqos ), + .s_axi_arready (m_axi_arready ), + .s_axi_arregion (m_axi_arregion ), + .s_axi_arsize (m_axi_arsize ), + .s_axi_arvalid (m_axi_arvalid ), + + .s_axi_awaddr (m_axi_awaddr ), + .s_axi_awburst (m_axi_awburst ), + .s_axi_awcache (m_axi_awcache ), + .s_axi_awid (m_axi_awid ), + .s_axi_awlen (m_axi_awlen ), + .s_axi_awlock (m_axi_awlock ), + .s_axi_awprot (m_axi_awprot ), + .s_axi_awqos (m_axi_awqos ), + .s_axi_awready (m_axi_awready ), + .s_axi_awregion (m_axi_awregion ), + .s_axi_awsize (m_axi_awsize ), + .s_axi_awvalid (m_axi_awvalid ), + + .s_axi_bid (m_axi_bid ), + .s_axi_bready (m_axi_bready ), + .s_axi_bresp (m_axi_bresp ), + .s_axi_bvalid (m_axi_bvalid ), + + .s_axi_rdata (m_axi_rdata ), + .s_axi_rid (m_axi_rid ), + .s_axi_rlast (m_axi_rlast ), + .s_axi_rready (m_axi_rready ), + .s_axi_rresp (m_axi_rresp ), + .s_axi_rvalid (m_axi_rvalid ), + + .s_axi_wdata (m_axi_wdata ), + .s_axi_wlast (m_axi_wlast ), + .s_axi_wready (m_axi_wready ), + .s_axi_wstrb (m_axi_wstrb ), + .s_axi_wvalid (m_axi_wvalid ) + ); + +// AXI Master. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +// DUT. +axis_buffer_ddr_v1 + #( + // Parameters of AXI Master I/F. + .TARGET_SLAVE_BASE_ADDR (TARGET_SLAVE_BASE_ADDR ), + .ID_WIDTH (ID_WIDTH ), + .DATA_WIDTH (DATA_WIDTH ) + ) + DUT + ( + // Trigger. + .trigger , + + /***********************************/ + /* AXI Slave I/F for configuration */ + /***********************************/ + .s_axi_aclk , + .s_axi_aresetn , + + .s_axi_awaddr , + .s_axi_awprot , + .s_axi_awvalid , + .s_axi_awready , + + .s_axi_wdata , + .s_axi_wstrb , + .s_axi_wvalid , + .s_axi_wready , + + .s_axi_bresp , + .s_axi_bvalid , + .s_axi_bready , + + .s_axi_araddr , + .s_axi_arprot , + .s_axi_arvalid , + .s_axi_arready , + + .s_axi_rdata , + .s_axi_rresp , + .s_axi_rvalid , + .s_axi_rready , + + // Reset and Clock (m_axi, s_axis, m_axis). + .aclk , + .aresetn , + + /***********************/ + /* AXI Master for DDR4 */ + /***********************/ + + // Write Address Channel. + .m_axi_awid , + .m_axi_awaddr , + .m_axi_awlen , + .m_axi_awsize , + .m_axi_awburst , + .m_axi_awlock , + .m_axi_awcache , + .m_axi_awprot , + .m_axi_awregion , + .m_axi_awqos , + .m_axi_awvalid , + .m_axi_awready , + + // Write Data Channel. + .m_axi_wdata , + .m_axi_wstrb , + .m_axi_wlast , + .m_axi_wvalid , + .m_axi_wready , + + // Write Response Channel. + .m_axi_bid , + .m_axi_bresp , + .m_axi_bvalid , + .m_axi_bready , + + // Read Address Channel. + .m_axi_arid , + .m_axi_araddr , + .m_axi_arlen , + .m_axi_arsize , + .m_axi_arburst , + .m_axi_arlock , + .m_axi_arcache , + .m_axi_arprot , + .m_axi_arregion , + .m_axi_arqos , + .m_axi_arvalid , + .m_axi_arready , + + // Read Data Channel. + .m_axi_rid , + .m_axi_rdata , + .m_axi_rresp , + .m_axi_rlast , + .m_axi_rvalid , + .m_axi_rready , + + /*************************/ + /* AXIS Master Interfase */ + /*************************/ + .m_axis_tvalid , + .m_axis_tdata , + .m_axis_tstrb , + .m_axis_tlast , + .m_axis_tready , + + /************************/ + /* AXIS Slave Interfase */ + /************************/ + .s_axis_tready , + .s_axis_tdata , + .s_axis_tstrb , + .s_axis_tlast , + .s_axis_tvalid + ); + +// VIP Agents +axi_slv_0_slv_mem_t axi_slv_0_agent; +axi_mst_0_mst_t axi_mst_0_agent; + +// Main TB. +initial begin + // Create agents. + axi_slv_0_agent = new("axi_slv_0 VIP Agent",tb.axi_slv_0_i.inst.IF); + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // AXI Slave (memory model) beat gap. + axi_slv_0_agent.mem_model.set_inter_beat_gap_delay_policy(XIL_AXI_MEMORY_DELAY_RANDOM); + axi_slv_0_agent.mem_model.set_inter_beat_gap_range(10,20); + + // Set tag for agents. + axi_slv_0_agent.set_agent_tag("axi_slv_0 VIP"); + axi_mst_0_agent.set_agent_tag("axi_mst_0 VIP"); + + // Start agents. + axi_slv_0_agent.start_slave(); + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + trigger <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + /**************************/ + /* Write data into memory */ + /**************************/ + // WNBURST_REG. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*5, prot, 10, resp); + + // WSTART_REG. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, 1, resp); + + tb_din_start <= 1; + + #1000; + + trigger <= 1; + + #10000; + + // Backdoor memory read. + for (int addr = TARGET_SLAVE_BASE_ADDR+0; addr < TARGET_SLAVE_BASE_ADDR+0+160; addr = addr + DATA_WIDTH) begin + data_mem = axi_slv_0_agent.mem_model.backdoor_memory_read(addr); + $display("Addr: 0x%04X, Data: 0x%04X", addr, data_mem); + end + + #1000; + + trigger <= 0; + + #1000; + + // WSTART_REG. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, 0, resp); + + #1000; + + /********************/ + /* Read from memory */ + /********************/ + // RLENGTH_REG. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, 10, resp); + + // RSTART_REG. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*0, prot, 1, resp); + + tb_dout_start <= 1; + +end + +// Data input process. +initial begin + s_axis_tdata <= 0; + s_axis_tstrb <= '1; + s_axis_tlast <= 0; + s_axis_tvalid <= 0; + + wait (tb_din_start); + + for (int i=0; i<100; i=i+1) begin + wait (s_axis_tready); + + @(posedge aclk); + @(posedge aclk); + s_axis_tdata <= i; + s_axis_tvalid <= 1; + @(posedge aclk); + //s_axis_tvalid <= 0; + @(posedge aclk); + end +end + +// Data output process. +initial begin + m_axis_tready <= 0; + + wait (tb_dout_start); + + @(posedge aclk); + m_axis_tready <= 1; +end + +always begin + s_axi_aclk <= 0; + #7; + s_axi_aclk <= 1; + #7; +end + +always begin + aclk <= 0; + #5; + aclk <= 1; + #5; +end + +endmodule + diff --git a/firmware/ip/axis_buffer_ddr_v1/src/tb/tb_axi_mst.sv b/firmware/ip/axis_buffer_ddr_v1/src/tb/tb_axi_mst.sv new file mode 100644 index 0000000..6d3cad4 --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/src/tb/tb_axi_mst.sv @@ -0,0 +1,340 @@ +import axi_vip_pkg::*; +import axi_slv_0_pkg::*; + +module tb(); + +// DUT generics. +parameter TARGET_SLAVE_BASE_ADDR = 32'h40000000; +parameter ID_WIDTH = 1; +parameter DATA_WIDTH = 256; + +// Reset and Clock. +reg m_axi_aclk ; +reg m_axi_aresetn ; + +// Write Address Channel. +wire [ID_WIDTH-1:0] m_axi_awid ; +wire [31:0] m_axi_awaddr ; +wire [7:0] m_axi_awlen ; +wire [2:0] m_axi_awsize ; +wire [1:0] m_axi_awburst ; +wire m_axi_awlock ; +wire [3:0] m_axi_awcache ; +wire [2:0] m_axi_awprot ; +wire [3:0] m_axi_awregion ; +wire [3:0] m_axi_awqos ; +wire m_axi_awvalid ; +wire m_axi_awready ; + +// Write Data Channel. +wire [DATA_WIDTH-1:0] m_axi_wdata ; +wire [DATA_WIDTH/8-1:0] m_axi_wstrb ; +wire m_axi_wlast ; +wire m_axi_wvalid ; +wire m_axi_wready ; + +// Write Response Channel. +wire [ID_WIDTH-1:0] m_axi_bid ; +wire [1:0] m_axi_bresp ; +wire m_axi_bvalid ; +wire m_axi_bready ; + +// Read Address Channel. +wire [ID_WIDTH-1:0] m_axi_arid ; +wire [31:0] m_axi_araddr ; +wire [7:0] m_axi_arlen ; +wire [2:0] m_axi_arsize ; +wire [1:0] m_axi_arburst ; +wire m_axi_arlock ; +wire [3:0] m_axi_arcache ; +wire [2:0] m_axi_arprot ; +wire [3:0] m_axi_arregion ; +wire [3:0] m_axi_arqos ; +wire m_axi_arvalid ; +wire m_axi_arready ; + +// Read Data Channel. +wire [ID_WIDTH-1:0] m_axi_rid ; +wire [DATA_WIDTH-1:0] m_axi_rdata ; +wire [1:0] m_axi_rresp ; +wire m_axi_rlast ; +wire m_axi_rvalid ; +wire m_axi_rready ; + +/*************************/ +/* AXIS Master Interfase */ +/*************************/ +wire m_axis_tvalid ; +wire [DATA_WIDTH-1:0] m_axis_tdata ; +wire [DATA_WIDTH/8-1:0] m_axis_tstrb ; +wire m_axis_tlast ; +reg m_axis_tready ; + +/************************/ +/* AXIS Slave Interfase */ +/************************/ +wire s_axis_tready ; +reg [DATA_WIDTH-1:0] s_axis_tdata ; +reg [DATA_WIDTH/8-1:0] s_axis_tstrb ; +reg s_axis_tlast ; +reg s_axis_tvalid ; + +// Registers. +reg RSTART_REG ; +reg [31:0] RADDR_REG ; +reg [31:0] RLENGTH_REG ; +reg WSTART_REG ; +reg [31:0] WADDR_REG ; + +xil_axi_prot_t prot = 0; +reg [31:0] data_wr = 32'h12345678; +reg [31:0] data; +reg [DATA_WIDTH-1:0] data_mem; +xil_axi_resp_t resp; + +reg tb_din_start = 0; +reg tb_dout_start = 0; + +axi_mst + #( + // Parameters of AXI Master I/F. + .TARGET_SLAVE_BASE_ADDR (TARGET_SLAVE_BASE_ADDR ), + .ID_WIDTH (ID_WIDTH ), + .DATA_WIDTH (DATA_WIDTH ) + ) + axi_mst_i + ( + /**************/ + /* AXI Master */ + /**************/ + + // Reset and Clock. + .m_axi_aclk , + .m_axi_aresetn , + + // Write Address Channel. + .m_axi_awid , + .m_axi_awaddr , + .m_axi_awlen , + .m_axi_awsize , + .m_axi_awburst , + .m_axi_awlock , + .m_axi_awcache , + .m_axi_awprot , + .m_axi_awregion , + .m_axi_awqos , + .m_axi_awvalid , + .m_axi_awready , + + // Write Data Channel. + .m_axi_wdata , + .m_axi_wstrb , + .m_axi_wlast , + .m_axi_wvalid , + .m_axi_wready , + + // Write Response Channel. + .m_axi_bid , + .m_axi_bresp , + .m_axi_bvalid , + .m_axi_bready , + + // Read Address Channel. + .m_axi_arid , + .m_axi_araddr , + .m_axi_arlen , + .m_axi_arsize , + .m_axi_arburst , + .m_axi_arlock , + .m_axi_arcache , + .m_axi_arprot , + .m_axi_arregion , + .m_axi_arqos , + .m_axi_arvalid , + .m_axi_arready , + + // Read Data Channel. + .m_axi_rid , + .m_axi_rdata , + .m_axi_rresp , + .m_axi_rlast , + .m_axi_rvalid , + .m_axi_rready , + + /*************************/ + /* AXIS Master Interfase */ + /*************************/ + .m_axis_tvalid , + .m_axis_tdata , + .m_axis_tstrb , + .m_axis_tlast , + .m_axis_tready , + + /************************/ + /* AXIS Slave Interfase */ + /************************/ + .s_axis_tready , + .s_axis_tdata , + .s_axis_tstrb , + .s_axis_tlast , + .s_axis_tvalid , + + // Registers. + .RSTART_REG , + .RADDR_REG , + .RLENGTH_REG , + .WSTART_REG , + .WADDR_REG + ); + +axi_slv_0 axi_slv_0_i + ( + .aclk (m_axi_aclk ), + .aresetn (m_axi_aresetn ), + + .s_axi_araddr (m_axi_araddr ), + .s_axi_arburst (m_axi_arburst ), + .s_axi_arcache (m_axi_arcache ), + .s_axi_arid (m_axi_arid ), + .s_axi_arlen (m_axi_arlen ), + .s_axi_arlock (m_axi_arlock ), + .s_axi_arprot (m_axi_arprot ), + .s_axi_arqos (m_axi_arqos ), + .s_axi_arready (m_axi_arready ), + .s_axi_arregion (m_axi_arregion ), + .s_axi_arsize (m_axi_arsize ), + .s_axi_arvalid (m_axi_arvalid ), + + .s_axi_awaddr (m_axi_awaddr ), + .s_axi_awburst (m_axi_awburst ), + .s_axi_awcache (m_axi_awcache ), + .s_axi_awid (m_axi_awid ), + .s_axi_awlen (m_axi_awlen ), + .s_axi_awlock (m_axi_awlock ), + .s_axi_awprot (m_axi_awprot ), + .s_axi_awqos (m_axi_awqos ), + .s_axi_awready (m_axi_awready ), + .s_axi_awregion (m_axi_awregion ), + .s_axi_awsize (m_axi_awsize ), + .s_axi_awvalid (m_axi_awvalid ), + + .s_axi_bid (m_axi_bid ), + .s_axi_bready (m_axi_bready ), + .s_axi_bresp (m_axi_bresp ), + .s_axi_bvalid (m_axi_bvalid ), + + .s_axi_rdata (m_axi_rdata ), + .s_axi_rid (m_axi_rid ), + .s_axi_rlast (m_axi_rlast ), + .s_axi_rready (m_axi_rready ), + .s_axi_rresp (m_axi_rresp ), + .s_axi_rvalid (m_axi_rvalid ), + + .s_axi_wdata (m_axi_wdata ), + .s_axi_wlast (m_axi_wlast ), + .s_axi_wready (m_axi_wready ), + .s_axi_wstrb (m_axi_wstrb ), + .s_axi_wvalid (m_axi_wvalid ) + ); + +// VIP Agents +axi_slv_0_slv_mem_t axi_slv_0_agent; + +initial begin + // Create agents. + axi_slv_0_agent = new("axi_slv_0 VIP Agent",tb.axi_slv_0_i.inst.IF); + + // AXI Slave (memory model) beat gap. + axi_slv_0_agent.mem_model.set_inter_beat_gap_delay_policy(XIL_AXI_MEMORY_DELAY_RANDOM); + axi_slv_0_agent.mem_model.set_inter_beat_gap_range(10,20); + + // Set tag for agents. + axi_slv_0_agent.set_agent_tag("axi_slv_0 VIP"); + + // Start agents. + axi_slv_0_agent.start_slave(); + + // Reset sequence. + m_axi_aresetn <= 0; + RSTART_REG <= 0; + RADDR_REG <= 0; + RLENGTH_REG <= 10; + WSTART_REG <= 0; + WADDR_REG <= 0; + #5000; + m_axi_aresetn <= 1; + + #1000; + + $display("##############"); + $display("### Test 0 ###"); + $display("##############"); + + #1000; + + // Write data into memory. + WSTART_REG <= 1; + tb_din_start <= 1; + + #1000; + + // Backdoor memory read. + for (int addr = TARGET_SLAVE_BASE_ADDR+0; addr < TARGET_SLAVE_BASE_ADDR+0+160; addr = addr + DATA_WIDTH/8) begin + data_mem = axi_slv_0_agent.mem_model.backdoor_memory_read(addr); + $display("Addr: 0x%04X, Data: 0x%04X", addr, data_mem); + end + + #1000; + + WSTART_REG <= 0; + + #1000; + + // Read from memory. + RSTART_REG <= 1; + tb_dout_start <= 1; +end + +// Data input process. +initial begin + s_axis_tdata <= 0; + s_axis_tstrb <= '1; + s_axis_tlast <= 0; + s_axis_tvalid <= 0; + + wait (tb_din_start); + + for (int i=0; i<1000; i=i+1) begin + wait (s_axis_tready); + + @(posedge m_axi_aclk); + @(posedge m_axi_aclk); + s_axis_tdata <= i; + s_axis_tvalid <= 1; + @(posedge m_axi_aclk); + s_axis_tvalid <= 0; + @(posedge m_axi_aclk); + @(posedge m_axi_aclk); + @(posedge m_axi_aclk); + end +end + +// Data output process. +initial begin + m_axis_tready <= 0; + + wait (tb_dout_start); + + @(posedge m_axi_aclk); + m_axis_tready <= 1; +end + +always begin + m_axi_aclk <= 0; + #1.7; + m_axi_aclk <= 1; + #1.7; +end + +endmodule + diff --git a/firmware/ip/axis_buffer_ddr_v1/xgui/axis_buffer_ddr_v1_v1_0.tcl b/firmware/ip/axis_buffer_ddr_v1/xgui/axis_buffer_ddr_v1_v1_0.tcl new file mode 100644 index 0000000..8284acc --- /dev/null +++ b/firmware/ip/axis_buffer_ddr_v1/xgui/axis_buffer_ddr_v1_v1_0.tcl @@ -0,0 +1,69 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "TARGET_SLAVE_BASE_ADDR" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.BURST_SIZE { PARAM_VALUE.BURST_SIZE } { + # Procedure called to update BURST_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BURST_SIZE { PARAM_VALUE.BURST_SIZE } { + # Procedure called to validate BURST_SIZE + return true +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.ID_WIDTH { PARAM_VALUE.ID_WIDTH } { + # Procedure called to update ID_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID_WIDTH { PARAM_VALUE.ID_WIDTH } { + # Procedure called to validate ID_WIDTH + return true +} + +proc update_PARAM_VALUE.TARGET_SLAVE_BASE_ADDR { PARAM_VALUE.TARGET_SLAVE_BASE_ADDR } { + # Procedure called to update TARGET_SLAVE_BASE_ADDR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TARGET_SLAVE_BASE_ADDR { PARAM_VALUE.TARGET_SLAVE_BASE_ADDR } { + # Procedure called to validate TARGET_SLAVE_BASE_ADDR + return true +} + + +proc update_MODELPARAM_VALUE.TARGET_SLAVE_BASE_ADDR { MODELPARAM_VALUE.TARGET_SLAVE_BASE_ADDR PARAM_VALUE.TARGET_SLAVE_BASE_ADDR } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TARGET_SLAVE_BASE_ADDR}] ${MODELPARAM_VALUE.TARGET_SLAVE_BASE_ADDR} +} + +proc update_MODELPARAM_VALUE.ID_WIDTH { MODELPARAM_VALUE.ID_WIDTH PARAM_VALUE.ID_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID_WIDTH}] ${MODELPARAM_VALUE.ID_WIDTH} +} + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.BURST_SIZE { MODELPARAM_VALUE.BURST_SIZE PARAM_VALUE.BURST_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BURST_SIZE}] ${MODELPARAM_VALUE.BURST_SIZE} +} + diff --git a/firmware/ip/axis_cdcsync_v1/component.xml b/firmware/ip/axis_cdcsync_v1/component.xml new file mode 100644 index 0000000..720ba74 --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/component.xml @@ -0,0 +1,3129 @@ + + + user.org + user + axis_cdcsync_v1 + 1.0 + + + m0_axis + + + + + + + TDATA + + + m0_axis_tdata + + + + + TVALID + + + m0_axis_tvalid + + + + + TREADY + + + m0_axis_tready + + + + + + m1_axis + + + + + + + TDATA + + + m1_axis_tdata + + + + + TVALID + + + m1_axis_tvalid + + + + + TREADY + + + m1_axis_tready + + + + + + + true + + + + + + m2_axis + + + + true + + + + TDATA + + + m2_axis_tdata + + + + + TVALID + + + m2_axis_tvalid + + + + + TREADY + + + m2_axis_tready + + + + + + + false + + + + + + m3_axis + + + + + + + TDATA + + + m3_axis_tdata + + + + + TVALID + + + m3_axis_tvalid + + + + + TREADY + + + m3_axis_tready + + + + + + + false + + + + + + m4_axis + + + + + + + TDATA + + + m4_axis_tdata + + + + + TVALID + + + m4_axis_tvalid + + + + + TREADY + + + m4_axis_tready + + + + + + + false + + + + + + m5_axis + + + + + + + TDATA + + + m5_axis_tdata + + + + + TVALID + + + m5_axis_tvalid + + + + + TREADY + + + m5_axis_tready + + + + + + + false + + + + + + m6_axis + + + + + + + TDATA + + + m6_axis_tdata + + + + + TVALID + + + m6_axis_tvalid + + + + + TREADY + + + m6_axis_tready + + + + + + + false + + + + + + m7_axis + + + + + + + TDATA + + + m7_axis_tdata + + + + + TVALID + + + m7_axis_tvalid + + + + + TREADY + + + m7_axis_tready + + + + + + + false + + + + + + s0_axis + + + + + + + TDATA + + + s0_axis_tdata + + + + + TVALID + + + s0_axis_tvalid + + + + + TREADY + + + s0_axis_tready + + + + + + s1_axis + + + + + + + TDATA + + + s1_axis_tdata + + + + + TVALID + + + s1_axis_tvalid + + + + + TREADY + + + s1_axis_tready + + + + + + + true + + + + + + s2_axis + + + + + + + TDATA + + + s2_axis_tdata + + + + + TVALID + + + s2_axis_tvalid + + + + + TREADY + + + s2_axis_tready + + + + + + + false + + + + + + s3_axis + + + + + + + TDATA + + + s3_axis_tdata + + + + + TVALID + + + s3_axis_tvalid + + + + + TREADY + + + s3_axis_tready + + + + + + + false + + + + + + s4_axis + + + + + + + TDATA + + + s4_axis_tdata + + + + + TVALID + + + s4_axis_tvalid + + + + + TREADY + + + s4_axis_tready + + + + + + + false + + + + + + s5_axis + + + + + + + TDATA + + + s5_axis_tdata + + + + + TVALID + + + s5_axis_tvalid + + + + + TREADY + + + s5_axis_tready + + + + + + + false + + + + + + s6_axis + + + + + + + TDATA + + + s6_axis_tdata + + + + + TVALID + + + s6_axis_tvalid + + + + + TREADY + + + s6_axis_tready + + + + + + + false + + + + + + s7_axis + + + + + + + TDATA + + + s7_axis_tdata + + + + + TVALID + + + s7_axis_tvalid + + + + + TREADY + + + s7_axis_tready + + + + + + + false + + + + + + s_axis_aresetn + + + + + + + RST + + + s_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axis_aclk + + + + + + + CLK + + + s_axis_aclk + + + + + + ASSOCIATED_RESET + s_axis_aresetn + + + ASSOCIATED_BUSIF + s0_axis:s1_axis:s2_axis:s3_axis:s4_axis:s5_axis:s6_axis:s7_axis:s8_axis:s9_axis:s10_axis:s11_axis:s12_axis:s13_axis:s14_axis:s15_axis + + + + + m_axis_aclk + + + + + + + CLK + + + m_axis_aclk + + + + + + ASSOCIATED_RESET + m_axis_aresetn + + + ASSOCIATED_BUSIF + m0_axis:m1_axis:m2_axis:m3_axis:m4_axis:m5_axis:m6_axis:m7_axis:m8_axis:m10_axis:m11_axis:m15_axis:m14_axis:m13_axis:m12_axis:m9_axis + + + + + m_axis_aresetn + + + + + + + RST + + + m_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s8_axis + + + + + + + TDATA + + + s8_axis_tdata + + + + + TVALID + + + s8_axis_tvalid + + + + + TREADY + + + s8_axis_tready + + + + + + + false + + + + + + s9_axis + + + + + + + TDATA + + + s9_axis_tdata + + + + + TVALID + + + s9_axis_tvalid + + + + + TREADY + + + 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/home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + /home/lstefana/v20.2/ip/axis_cdcsync_v1 + + + + 2022.1 + + + + + + + + diff --git a/firmware/ip/axis_cdcsync_v1/src/axis_cdcsync_v1.sv b/firmware/ip/axis_cdcsync_v1/src/axis_cdcsync_v1.sv new file mode 100644 index 0000000..114ca2f --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/src/axis_cdcsync_v1.sv @@ -0,0 +1,298 @@ +module axis_cdcsync_v1 + #( + // Number of inputs/outputs. + parameter N = 2 , + + // Number of data bits. + parameter B = 8 + ) + ( + // S_AXIS for input data. + input wire s_axis_aresetn , + input wire s_axis_aclk , + + output wire s0_axis_tready , + input wire s0_axis_tvalid , + input wire [B-1:0] s0_axis_tdata , + + output wire s1_axis_tready , + input wire s1_axis_tvalid , + input wire [B-1:0] s1_axis_tdata , + + output wire s2_axis_tready , + input wire s2_axis_tvalid , + input wire [B-1:0] s2_axis_tdata , + + output wire s3_axis_tready , + input wire s3_axis_tvalid , + input wire [B-1:0] s3_axis_tdata , + + output wire s4_axis_tready , + input wire s4_axis_tvalid , + input wire [B-1:0] s4_axis_tdata , + + output wire s5_axis_tready , + input wire s5_axis_tvalid , + input wire [B-1:0] s5_axis_tdata , + + output wire s6_axis_tready , + input wire s6_axis_tvalid , + input wire [B-1:0] s6_axis_tdata , + + output wire s7_axis_tready , + input wire s7_axis_tvalid , + input wire [B-1:0] s7_axis_tdata , + + output wire s8_axis_tready , + input wire s8_axis_tvalid , + input wire [B-1:0] s8_axis_tdata , + + output wire s9_axis_tready , + input wire s9_axis_tvalid , + input wire [B-1:0] s9_axis_tdata , + + output wire s10_axis_tready , + input wire s10_axis_tvalid , + input wire [B-1:0] s10_axis_tdata , + + output wire s11_axis_tready , + input wire s11_axis_tvalid , + input wire [B-1:0] s11_axis_tdata , + + output wire s12_axis_tready , + input wire s12_axis_tvalid , + input wire [B-1:0] s12_axis_tdata , + + output wire s13_axis_tready , + input wire s13_axis_tvalid , + input wire [B-1:0] s13_axis_tdata , + + output wire s14_axis_tready , + input wire s14_axis_tvalid , + input wire [B-1:0] s14_axis_tdata , + + output wire s15_axis_tready , + input wire s15_axis_tvalid , + input wire [B-1:0] s15_axis_tdata , + + // M_AXIS for output data. + input wire m_axis_aresetn , + input wire m_axis_aclk , + + input wire m0_axis_tready , + output wire m0_axis_tvalid , + output wire [B-1:0] m0_axis_tdata , + + input wire m1_axis_tready , + output wire m1_axis_tvalid , + output wire [B-1:0] m1_axis_tdata , + + input wire m2_axis_tready , + output wire m2_axis_tvalid , + output wire [B-1:0] m2_axis_tdata , + + input wire m3_axis_tready , + output wire m3_axis_tvalid , + output wire [B-1:0] m3_axis_tdata , + + input wire m4_axis_tready , + output wire m4_axis_tvalid , + output wire [B-1:0] m4_axis_tdata , + + input wire m5_axis_tready , + output wire m5_axis_tvalid , + output wire [B-1:0] m5_axis_tdata , + + input wire m6_axis_tready , + output wire m6_axis_tvalid , + output wire [B-1:0] m6_axis_tdata , + + input wire m7_axis_tready , + output wire m7_axis_tvalid , + output wire [B-1:0] m7_axis_tdata , + + input wire m8_axis_tready , + output wire m8_axis_tvalid , + output wire [B-1:0] m8_axis_tdata , + + input wire m9_axis_tready , + output wire m9_axis_tvalid , + output wire [B-1:0] m9_axis_tdata , + + input wire m10_axis_tready , + output wire m10_axis_tvalid , + output wire [B-1:0] m10_axis_tdata , + + input wire m11_axis_tready , + output wire m11_axis_tvalid , + output wire [B-1:0] m11_axis_tdata , + + input wire m12_axis_tready , + output wire m12_axis_tvalid , + output wire [B-1:0] m12_axis_tdata , + + input wire m13_axis_tready , + output wire m13_axis_tvalid , + output wire [B-1:0] m13_axis_tdata , + + input wire m14_axis_tready , + output wire m14_axis_tvalid , + output wire [B-1:0] m14_axis_tdata , + + input wire m15_axis_tready , + output wire m15_axis_tvalid , + output wire [B-1:0] m15_axis_tdata + ); + +/**********************/ +/* Begin Architecture */ +/**********************/ +cdcsync + #( + // Number of inputs/outputs. + .N(N), + + // Number of data bits. + .B(B) + ) + cdcsync_i + ( + // S_AXIS for input data. + .s_axis_aresetn (s_axis_aresetn ), + .s_axis_aclk (s_axis_aclk ), + + .s0_axis_tready (s0_axis_tready ), + .s0_axis_tvalid (s0_axis_tvalid ), + .s0_axis_tdata (s0_axis_tdata ), + + .s1_axis_tready (s1_axis_tready ), + .s1_axis_tvalid (s1_axis_tvalid ), + .s1_axis_tdata (s1_axis_tdata ), + + .s2_axis_tready (s2_axis_tready ), + .s2_axis_tvalid (s2_axis_tvalid ), + .s2_axis_tdata (s2_axis_tdata ), + + .s3_axis_tready (s3_axis_tready ), + .s3_axis_tvalid (s3_axis_tvalid ), + .s3_axis_tdata (s3_axis_tdata ), + + .s4_axis_tready (s4_axis_tready ), + .s4_axis_tvalid (s4_axis_tvalid ), + .s4_axis_tdata (s4_axis_tdata ), + + .s5_axis_tready (s5_axis_tready ), + .s5_axis_tvalid (s5_axis_tvalid ), + .s5_axis_tdata (s5_axis_tdata ), + + .s6_axis_tready (s6_axis_tready ), + .s6_axis_tvalid (s6_axis_tvalid ), + .s6_axis_tdata (s6_axis_tdata ), + + .s7_axis_tready (s7_axis_tready ), + .s7_axis_tvalid (s7_axis_tvalid ), + .s7_axis_tdata (s7_axis_tdata ), + + .s8_axis_tready (s8_axis_tready ), + .s8_axis_tvalid (s8_axis_tvalid ), + .s8_axis_tdata (s8_axis_tdata ), + + .s9_axis_tready (s9_axis_tready ), + .s9_axis_tvalid (s9_axis_tvalid ), + .s9_axis_tdata (s9_axis_tdata ), + + .s10_axis_tready (s10_axis_tready ), + .s10_axis_tvalid (s10_axis_tvalid ), + .s10_axis_tdata (s10_axis_tdata ), + + .s11_axis_tready (s11_axis_tready ), + .s11_axis_tvalid (s11_axis_tvalid ), + .s11_axis_tdata (s11_axis_tdata ), + + .s12_axis_tready (s12_axis_tready ), + .s12_axis_tvalid (s12_axis_tvalid ), + .s12_axis_tdata (s12_axis_tdata ), + + .s13_axis_tready (s13_axis_tready ), + .s13_axis_tvalid (s13_axis_tvalid ), + .s13_axis_tdata (s13_axis_tdata ), + + .s14_axis_tready (s14_axis_tready ), + .s14_axis_tvalid (s14_axis_tvalid ), + .s14_axis_tdata (s14_axis_tdata ), + + .s15_axis_tready (s15_axis_tready ), + .s15_axis_tvalid (s15_axis_tvalid ), + .s15_axis_tdata (s15_axis_tdata ), + + // M_AXIS for output data. + .m_axis_aresetn (m_axis_aresetn ), + .m_axis_aclk (m_axis_aclk ), + + .m0_axis_tready (m0_axis_tready ), + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + + .m1_axis_tready (m1_axis_tready ), + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tdata (m1_axis_tdata ), + + .m2_axis_tready (m2_axis_tready ), + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tdata (m2_axis_tdata ), + + .m3_axis_tready (m3_axis_tready ), + .m3_axis_tvalid (m3_axis_tvalid ), + .m3_axis_tdata (m3_axis_tdata ), + + .m4_axis_tready (m4_axis_tready ), + .m4_axis_tvalid (m4_axis_tvalid ), + .m4_axis_tdata (m4_axis_tdata ), + + .m5_axis_tready (m5_axis_tready ), + .m5_axis_tvalid (m5_axis_tvalid ), + .m5_axis_tdata (m5_axis_tdata ), + + .m6_axis_tready (m6_axis_tready ), + .m6_axis_tvalid (m6_axis_tvalid ), + .m6_axis_tdata (m6_axis_tdata ), + + .m7_axis_tready (m7_axis_tready ), + .m7_axis_tvalid (m7_axis_tvalid ), + .m7_axis_tdata (m7_axis_tdata ), + + .m8_axis_tready (m8_axis_tready ), + .m8_axis_tvalid (m8_axis_tvalid ), + .m8_axis_tdata (m8_axis_tdata ), + + .m9_axis_tready (m9_axis_tready ), + .m9_axis_tvalid (m9_axis_tvalid ), + .m9_axis_tdata (m9_axis_tdata ), + + .m10_axis_tready (m10_axis_tready ), + .m10_axis_tvalid (m10_axis_tvalid ), + .m10_axis_tdata (m10_axis_tdata ), + + .m11_axis_tready (m11_axis_tready ), + .m11_axis_tvalid (m11_axis_tvalid ), + .m11_axis_tdata (m11_axis_tdata ), + + .m12_axis_tready (m12_axis_tready ), + .m12_axis_tvalid (m12_axis_tvalid ), + .m12_axis_tdata (m12_axis_tdata ), + + .m13_axis_tready (m13_axis_tready ), + .m13_axis_tvalid (m13_axis_tvalid ), + .m13_axis_tdata (m13_axis_tdata ), + + .m14_axis_tready (m14_axis_tready ), + .m14_axis_tvalid (m14_axis_tvalid ), + .m14_axis_tdata (m14_axis_tdata ), + + .m15_axis_tready (m15_axis_tready ), + .m15_axis_tvalid (m15_axis_tvalid ), + .m15_axis_tdata (m15_axis_tdata ) + ); + +endmodule + diff --git a/firmware/ip/axis_cdcsync_v1/src/cdcsync.sv b/firmware/ip/axis_cdcsync_v1/src/cdcsync.sv new file mode 100644 index 0000000..08b6c4a --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/src/cdcsync.sv @@ -0,0 +1,349 @@ +module cdcsync + #( + // Number of inputs/outputs. + parameter N = 2 , + + // Number of data bits. + parameter B = 8 + ) + ( + // S_AXIS for input data. + input wire s_axis_aresetn , + input wire s_axis_aclk , + + output wire s0_axis_tready , + input wire s0_axis_tvalid , + input wire [B-1:0] s0_axis_tdata , + + output wire s1_axis_tready , + input wire s1_axis_tvalid , + input wire [B-1:0] s1_axis_tdata , + + output wire s2_axis_tready , + input wire s2_axis_tvalid , + input wire [B-1:0] s2_axis_tdata , + + output wire s3_axis_tready , + input wire s3_axis_tvalid , + input wire [B-1:0] s3_axis_tdata , + + output wire s4_axis_tready , + input wire s4_axis_tvalid , + input wire [B-1:0] s4_axis_tdata , + + output wire s5_axis_tready , + input wire s5_axis_tvalid , + input wire [B-1:0] s5_axis_tdata , + + output wire s6_axis_tready , + input wire s6_axis_tvalid , + input wire [B-1:0] s6_axis_tdata , + + output wire s7_axis_tready , + input wire s7_axis_tvalid , + input wire [B-1:0] s7_axis_tdata , + + output wire s8_axis_tready , + input wire s8_axis_tvalid , + input wire [B-1:0] s8_axis_tdata , + + output wire s9_axis_tready , + input wire s9_axis_tvalid , + input wire [B-1:0] s9_axis_tdata , + + output wire s10_axis_tready , + input wire s10_axis_tvalid , + input wire [B-1:0] s10_axis_tdata , + + output wire s11_axis_tready , + input wire s11_axis_tvalid , + input wire [B-1:0] s11_axis_tdata , + + output wire s12_axis_tready , + input wire s12_axis_tvalid , + input wire [B-1:0] s12_axis_tdata , + + output wire s13_axis_tready , + input wire s13_axis_tvalid , + input wire [B-1:0] s13_axis_tdata , + + output wire s14_axis_tready , + input wire s14_axis_tvalid , + input wire [B-1:0] s14_axis_tdata , + + output wire s15_axis_tready , + input wire s15_axis_tvalid , + input wire [B-1:0] s15_axis_tdata , + + // M_AXIS for output data. + input wire m_axis_aresetn , + input wire m_axis_aclk , + + input wire m0_axis_tready , + output wire m0_axis_tvalid , + output wire [B-1:0] m0_axis_tdata , + + input wire m1_axis_tready , + output wire m1_axis_tvalid , + output wire [B-1:0] m1_axis_tdata , + + input wire m2_axis_tready , + output wire m2_axis_tvalid , + output wire [B-1:0] m2_axis_tdata , + + input wire m3_axis_tready , + output wire m3_axis_tvalid , + output wire [B-1:0] m3_axis_tdata , + + input wire m4_axis_tready , + output wire m4_axis_tvalid , + output wire [B-1:0] m4_axis_tdata , + + input wire m5_axis_tready , + output wire m5_axis_tvalid , + output wire [B-1:0] m5_axis_tdata , + + input wire m6_axis_tready , + output wire m6_axis_tvalid , + output wire [B-1:0] m6_axis_tdata , + + input wire m7_axis_tready , + output wire m7_axis_tvalid , + output wire [B-1:0] m7_axis_tdata , + + input wire m8_axis_tready , + output wire m8_axis_tvalid , + output wire [B-1:0] m8_axis_tdata , + + input wire m9_axis_tready , + output wire m9_axis_tvalid , + output wire [B-1:0] m9_axis_tdata , + + input wire m10_axis_tready , + output wire m10_axis_tvalid , + output wire [B-1:0] m10_axis_tdata , + + input wire m11_axis_tready , + output wire m11_axis_tvalid , + output wire [B-1:0] m11_axis_tdata , + + input wire m12_axis_tready , + output wire m12_axis_tvalid , + output wire [B-1:0] m12_axis_tdata , + + input wire m13_axis_tready , + output wire m13_axis_tvalid , + output wire [B-1:0] m13_axis_tdata , + + input wire m14_axis_tready , + output wire m14_axis_tvalid , + output wire [B-1:0] m14_axis_tdata , + + input wire m15_axis_tready , + output wire m15_axis_tvalid , + output wire [B-1:0] m15_axis_tdata + ); + +/********************/ +/* Internal signals */ +/********************/ +// Total bits. +localparam BD = B + 1; +localparam BT = N*BD; + +// Input data to vector. +wire [B-1:0] din_data_v [16] ; +wire [15:0] din_valid_v ; +wire [15:0] din_ready_v ; + +// Output vector to data. +wire [B-1:0] dout_data_v [16] ; +wire [15:0] dout_valid_v ; +wire [15:0] dout_ready_v ; + +wire fifo_wr_en ; +wire [BT-1:0] fifo_din ; +wire [BT-1:0] fifo_dout ; +wire fifo_full ; +wire fifo_empty ; + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// Input data to vector. +assign din_data_v [0] = s0_axis_tdata ; +assign din_data_v [1] = s1_axis_tdata ; +assign din_data_v [2] = s2_axis_tdata ; +assign din_data_v [3] = s3_axis_tdata ; +assign din_data_v [4] = s4_axis_tdata ; +assign din_data_v [5] = s5_axis_tdata ; +assign din_data_v [6] = s6_axis_tdata ; +assign din_data_v [7] = s7_axis_tdata ; +assign din_data_v [8] = s8_axis_tdata ; +assign din_data_v [9] = s9_axis_tdata ; +assign din_data_v [10] = s10_axis_tdata ; +assign din_data_v [11] = s11_axis_tdata ; +assign din_data_v [12] = s12_axis_tdata ; +assign din_data_v [13] = s13_axis_tdata ; +assign din_data_v [14] = s14_axis_tdata ; +assign din_data_v [15] = s15_axis_tdata ; + +assign din_valid_v [0] = s0_axis_tvalid ; +assign din_valid_v [1] = s1_axis_tvalid ; +assign din_valid_v [2] = s2_axis_tvalid ; +assign din_valid_v [3] = s3_axis_tvalid ; +assign din_valid_v [4] = s4_axis_tvalid ; +assign din_valid_v [5] = s5_axis_tvalid ; +assign din_valid_v [6] = s6_axis_tvalid ; +assign din_valid_v [7] = s7_axis_tvalid ; +assign din_valid_v [8] = s8_axis_tvalid ; +assign din_valid_v [9] = s9_axis_tvalid ; +assign din_valid_v [10] = s10_axis_tvalid ; +assign din_valid_v [11] = s11_axis_tvalid ; +assign din_valid_v [12] = s12_axis_tvalid ; +assign din_valid_v [13] = s13_axis_tvalid ; +assign din_valid_v [14] = s14_axis_tvalid ; +assign din_valid_v [15] = s15_axis_tvalid ; + +assign din_ready_v [0] = m0_axis_tready ; +assign din_ready_v [1] = m1_axis_tready ; +assign din_ready_v [2] = m2_axis_tready ; +assign din_ready_v [3] = m3_axis_tready ; +assign din_ready_v [4] = m4_axis_tready ; +assign din_ready_v [5] = m5_axis_tready ; +assign din_ready_v [6] = m6_axis_tready ; +assign din_ready_v [7] = m7_axis_tready ; +assign din_ready_v [8] = m8_axis_tready ; +assign din_ready_v [9] = m9_axis_tready ; +assign din_ready_v [10] = m10_axis_tready ; +assign din_ready_v [11] = m11_axis_tready ; +assign din_ready_v [12] = m12_axis_tready ; +assign din_ready_v [13] = m13_axis_tready ; +assign din_ready_v [14] = m14_axis_tready ; +assign din_ready_v [15] = m15_axis_tready ; + +// Output vector to data. +assign m0_axis_tdata = dout_data_v [0] ; +assign m1_axis_tdata = dout_data_v [1] ; +assign m2_axis_tdata = dout_data_v [2] ; +assign m3_axis_tdata = dout_data_v [3] ; +assign m4_axis_tdata = dout_data_v [4] ; +assign m5_axis_tdata = dout_data_v [5] ; +assign m6_axis_tdata = dout_data_v [6] ; +assign m7_axis_tdata = dout_data_v [7] ; +assign m8_axis_tdata = dout_data_v [8] ; +assign m9_axis_tdata = dout_data_v [9] ; +assign m10_axis_tdata = dout_data_v [10] ; +assign m11_axis_tdata = dout_data_v [11] ; +assign m12_axis_tdata = dout_data_v [12] ; +assign m13_axis_tdata = dout_data_v [13] ; +assign m14_axis_tdata = dout_data_v [14] ; +assign m15_axis_tdata = dout_data_v [15] ; + +assign m0_axis_tvalid = dout_valid_v [0] & ~fifo_empty; +assign m1_axis_tvalid = dout_valid_v [1] & ~fifo_empty; +assign m2_axis_tvalid = dout_valid_v [2] & ~fifo_empty; +assign m3_axis_tvalid = dout_valid_v [3] & ~fifo_empty; +assign m4_axis_tvalid = dout_valid_v [4] & ~fifo_empty; +assign m5_axis_tvalid = dout_valid_v [5] & ~fifo_empty; +assign m6_axis_tvalid = dout_valid_v [6] & ~fifo_empty; +assign m7_axis_tvalid = dout_valid_v [7] & ~fifo_empty; +assign m8_axis_tvalid = dout_valid_v [8] & ~fifo_empty; +assign m9_axis_tvalid = dout_valid_v [9] & ~fifo_empty; +assign m10_axis_tvalid = dout_valid_v [10] & ~fifo_empty; +assign m11_axis_tvalid = dout_valid_v [11] & ~fifo_empty; +assign m12_axis_tvalid = dout_valid_v [12] & ~fifo_empty; +assign m13_axis_tvalid = dout_valid_v [13] & ~fifo_empty; +assign m14_axis_tvalid = dout_valid_v [14] & ~fifo_empty; +assign m15_axis_tvalid = dout_valid_v [15] & ~fifo_empty; + +assign s0_axis_tready = dout_ready_v [0]; +assign s1_axis_tready = dout_ready_v [1]; +assign s2_axis_tready = dout_ready_v [2]; +assign s3_axis_tready = dout_ready_v [3]; +assign s4_axis_tready = dout_ready_v [4]; +assign s5_axis_tready = dout_ready_v [5]; +assign s6_axis_tready = dout_ready_v [6]; +assign s7_axis_tready = dout_ready_v [7]; +assign s8_axis_tready = dout_ready_v [8]; +assign s9_axis_tready = dout_ready_v [9]; +assign s10_axis_tready = dout_ready_v [10]; +assign s11_axis_tready = dout_ready_v [11]; +assign s12_axis_tready = dout_ready_v [12]; +assign s13_axis_tready = dout_ready_v [13]; +assign s14_axis_tready = dout_ready_v [14]; +assign s15_axis_tready = dout_ready_v [15]; + +genvar i; +generate + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_axi.vhd b/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_dc.vhd b/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_cdcsync_v1/src/fifo/gray2bin.vhd b/firmware/ip/axis_cdcsync_v1/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_cdcsync_v1/src/fifo/rd2axi.vhd b/firmware/ip/axis_cdcsync_v1/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_cdcsync_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_cdcsync_v1/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_cdcsync_v1/src/tb.sv b/firmware/ip/axis_cdcsync_v1/src/tb.sv new file mode 100644 index 0000000..3a74097 --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/src/tb.sv @@ -0,0 +1,240 @@ +module tb; + +// Number of inputs/outputs. +parameter N = 8 ; + +// Number of data bits. +parameter B = 8 ; + + +// S_AXIS for input data. +reg s_axis_aresetn ; +reg s_axis_aclk ; + +wire s0_axis_tready ; +reg s0_axis_tvalid ; +reg [B-1:0] s0_axis_tdata ; + +wire s1_axis_tready ; +reg s1_axis_tvalid ; +reg [B-1:0] s1_axis_tdata ; + +wire s2_axis_tready ; +reg s2_axis_tvalid ; +reg [B-1:0] s2_axis_tdata ; + +wire s3_axis_tready ; +reg s3_axis_tvalid ; +reg [B-1:0] s3_axis_tdata ; + +wire s4_axis_tready ; +reg s4_axis_tvalid ; +reg [B-1:0] s4_axis_tdata ; + +wire s5_axis_tready ; +reg s5_axis_tvalid ; +reg [B-1:0] s5_axis_tdata ; + +wire s6_axis_tready ; +reg s6_axis_tvalid ; +reg [B-1:0] s6_axis_tdata ; + +wire s7_axis_tready ; +reg s7_axis_tvalid ; +reg [B-1:0] s7_axis_tdata ; + +// M_AXIS for output data. +reg m_axis_aresetn ; +reg m_axis_aclk ; + +wire m0_axis_tvalid ; +wire[B-1:0] m0_axis_tdata ; + +wire m1_axis_tvalid ; +wire[B-1:0] m1_axis_tdata ; + +wire m2_axis_tvalid ; +wire[B-1:0] m2_axis_tdata ; + +wire m3_axis_tvalid ; +wire[B-1:0] m3_axis_tdata ; + +wire m4_axis_tvalid ; +wire[B-1:0] m4_axis_tdata ; + +wire m5_axis_tvalid ; +wire[B-1:0] m5_axis_tdata ; + +wire m6_axis_tvalid ; +wire[B-1:0] m6_axis_tdata ; + +wire m7_axis_tvalid ; +wire[B-1:0] m7_axis_tdata ; + +// DUT. +axis_cdcsync_v1 + #( + // Number of inputs/outputs. + .N(N), + + // Number of data bits. + .B(B) + ) + DUT + ( + // S_AXIS for input data. + .s_axis_aresetn , + .s_axis_aclk , + + .s0_axis_tready , + .s0_axis_tvalid , + .s0_axis_tdata , + + .s1_axis_tready , + .s1_axis_tvalid , + .s1_axis_tdata , + + .s2_axis_tready , + .s2_axis_tvalid , + .s2_axis_tdata , + + .s3_axis_tready , + .s3_axis_tvalid , + .s3_axis_tdata , + + .s4_axis_tready , + .s4_axis_tvalid , + .s4_axis_tdata , + + .s5_axis_tready , + .s5_axis_tvalid , + .s5_axis_tdata , + + .s6_axis_tready , + .s6_axis_tvalid , + .s6_axis_tdata , + + .s7_axis_tready , + .s7_axis_tvalid , + .s7_axis_tdata , + + // M_AXIS for output data. + .m_axis_aresetn , + .m_axis_aclk , + + .m0_axis_tvalid , + .m0_axis_tdata , + + .m1_axis_tvalid , + .m1_axis_tdata , + + .m2_axis_tvalid , + .m2_axis_tdata , + + .m3_axis_tvalid , + .m3_axis_tdata , + + .m4_axis_tvalid , + .m4_axis_tdata , + + .m5_axis_tvalid , + .m5_axis_tdata , + + .m6_axis_tvalid , + .m6_axis_tdata , + + .m7_axis_tvalid , + .m7_axis_tdata + ); + +// Main TB. +initial begin + s_axis_aresetn <= 0; + m_axis_aresetn <= 0; + s0_axis_tvalid <= 0; + s0_axis_tdata <= 0; + s1_axis_tvalid <= 0; + s1_axis_tdata <= 0; + s2_axis_tvalid <= 0; + s2_axis_tdata <= 0; + s3_axis_tvalid <= 0; + s3_axis_tdata <= 0; + s4_axis_tvalid <= 0; + s4_axis_tdata <= 0; + s5_axis_tvalid <= 0; + s5_axis_tdata <= 0; + s6_axis_tvalid <= 0; + s6_axis_tdata <= 0; + s7_axis_tvalid <= 0; + s7_axis_tdata <= 0; + #300; + s_axis_aresetn <= 1; + m_axis_aresetn <= 1; + + #1000; + + @(posedge s_axis_aclk); + s0_axis_tvalid <= 1'b1; + s0_axis_tdata <= $random; + + @(posedge s_axis_aclk); + s0_axis_tvalid <= 1'b0; + + #200; + + @(posedge s_axis_aclk); + s1_axis_tvalid <= 1'b1; + s1_axis_tdata <= $random; + + @(posedge s_axis_aclk); + s1_axis_tvalid <= 1'b0; + + for (int i=0; i<5; i=i+1) begin + @(posedge s_axis_aclk); + s0_axis_tvalid <= 1'b1; + s0_axis_tdata <= $random; + s1_axis_tvalid <= 1'b1; + s1_axis_tdata <= $random; + end + + @(posedge s_axis_aclk); + s1_axis_tvalid <= 1'b0; + + for (int i=0; i<7; i=i+1) begin + @(posedge s_axis_aclk); + s0_axis_tvalid <= 1'b1; + s0_axis_tdata <= $random; + end + + @(posedge s_axis_aclk); + s0_axis_tvalid <= 1'b0; + + #2000; + + @(posedge s_axis_aclk); + s7_axis_tvalid <= 1'b1; + s7_axis_tdata <= $random; + + @(posedge s_axis_aclk); + s7_axis_tvalid <= 1'b0; + +end + +// s_axis_aclk; +always begin + s_axis_aclk <= 0; + #7; + s_axis_aclk <= 1; + #7; +end + +// m_axis_aclk; +always begin + m_axis_aclk <= 0; + #3; + m_axis_aclk <= 1; + #3; +end + +endmodule + diff --git a/firmware/ip/axis_cdcsync_v1/xgui/axis_cdcsync_v1_v1_0.tcl b/firmware/ip/axis_cdcsync_v1/xgui/axis_cdcsync_v1_v1_0.tcl new file mode 100644 index 0000000..f41c028 --- /dev/null +++ b/firmware/ip/axis_cdcsync_v1/xgui/axis_cdcsync_v1_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "B" -parent ${Page_0} + ipgui::add_param $IPINST -name "N" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to update B when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to validate B + return true +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + +proc update_MODELPARAM_VALUE.B { MODELPARAM_VALUE.B PARAM_VALUE.B } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.B}] ${MODELPARAM_VALUE.B} +} + diff --git a/firmware/ip/axis_constant/component.xml b/firmware/ip/axis_constant/component.xml new file mode 100644 index 0000000..7347f1e --- /dev/null +++ b/firmware/ip/axis_constant/component.xml @@ -0,0 +1,364 @@ + + + user.org + user + axis_constant + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TSTRB + + + m_axis_tstrb + + + + + TLAST + + + m_axis_tlast + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + m_axis_aresetn + + + + + + + RST + + + m_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m_axis_aclk + + + + + + + CLK + + + m_axis_aclk + + + + + + ASSOCIATED_BUSIF + m_axis + + + ASSOCIATED_RESET + m_axis_aresetn + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + axis_constant + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 9417364f + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + axis_constant + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 9417364f + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 35ebc586 + + + + + + + m_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tdata + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tstrb + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + DATA_WIDTH + Data Width + 16 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/axis_constant.vhd + vhdlSource + CHECKSUM_9417364f + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/axis_constant.vhd + vhdlSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_constant_v1_0.tcl + tclSource + CHECKSUM_35ebc586 + XGUI_VERSION_2 + + + + AXIS Constant IP to properly terminate inputs. + + + DATA_WIDTH + Data Width + 16 + + + Component_Name + axis_constant_v1_0 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + kintexuplus + kintexu + + + /UserIP + + AXIS Constant + package_project + 2 + 2021-06-10T13:34:21Z + + /home/lstefana/v19.1/ip/axis_constant + /home/lstefana/v19.1/ip/axis_constant + /home/lstefana/v19.1/ip/axis_constant + /home/lstefana/v19.1/ip/axis_constant + /home/lstefana/v19.1/ip/axis_constant + /home/lstefana/v19.1/ip/axis_constant + /home/lstefana/v19.1/ip/axis_constant + /home/lstefana/v19.1/ip/axis_constant + + + + 2019.1 + + + + + + + + diff --git a/firmware/ip/axis_constant/src/axis_constant.vhd b/firmware/ip/axis_constant/src/axis_constant.vhd new file mode 100644 index 0000000..359a234 --- /dev/null +++ b/firmware/ip/axis_constant/src/axis_constant.vhd @@ -0,0 +1,34 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity axis_constant is + generic + ( + -- Data width. + DATA_WIDTH : Integer := 16 + ); + port + ( + -- AXIS Slave I/F. + m_axis_aclk : in std_logic; + m_axis_aresetn : in std_logic; + m_axis_tready : in std_logic; + m_axis_tdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + m_axis_tstrb : out std_logic_vector((DATA_WIDTH/8)-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic + ); +end axis_constant; + +architecture rtl of axis_constant is + +begin + +m_axis_tdata <= (others => '0'); +m_axis_tstrb <= (others => '0'); +m_axis_tlast <= '0'; +m_axis_tvalid <= '0'; + +end rtl; + diff --git a/firmware/ip/axis_constant/xgui/axis_constant_v1_0.tcl b/firmware/ip/axis_constant/xgui/axis_constant_v1_0.tcl new file mode 100644 index 0000000..55a2622 --- /dev/null +++ b/firmware/ip/axis_constant/xgui/axis_constant_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + diff --git a/firmware/ip/axis_constant_iq/component.xml b/firmware/ip/axis_constant_iq/component.xml new file mode 100644 index 0000000..283f0af --- /dev/null +++ b/firmware/ip/axis_constant_iq/component.xml @@ -0,0 +1,886 @@ + + + user.org + user + axis_constant_iq + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + m_axis_aresetn + + + + + + + RST + + + m_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m_axis_aclk + + + + + + + CLK + + + m_axis_aclk + + + + + + ASSOCIATED_BUSIF + m_axis + + + ASSOCIATED_RESET + m_axis_aresetn + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + axis_constant_iq + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 05173ec9 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + axis_constant_iq + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 05173ec9 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 2c3a0701 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + B + B + 16 + + + N + N + 4 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/axi_slv.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_constant_iq.vhd + vhdlSource + CHECKSUM_d08b65cf + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/axi_slv.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_constant_iq.vhd + vhdlSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_constant_iq_v1_0.tcl + tclSource + CHECKSUM_2c3a0701 + XGUI_VERSION_2 + + + + AXIS Constant IQ with parallel outputs for DAC. + + + B + B + 16 + + + N + N + 4 + + + Component_Name + axis_constant_iq_v1_0 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + kintexuplus + kintexu + + + /UserIP + + AXIS Constant IQ + package_project + 2 + 2021-09-02T14:55:11Z + + /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq + /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq + /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq + /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq + /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq + /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq + /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq + /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq + /home/lstefana/v19.1/zcu111/fft_avg_ad_da/ip/axis_constant_iq + + + + 2019.1 + + + + + + + + + diff --git a/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 0000000..5f33135 --- /dev/null +++ b/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 5 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 0000000..5c4d9a9 --- /dev/null +++ b/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 5 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..34f0b12 --- /dev/null +++ b/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,187 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + virtex7 + + + xc7vx485t + ffg1157 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 0000000..0a6987b --- /dev/null +++ b/firmware/ip/axis_constant_iq/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4751 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + ARSIZE + + + m_axi_arsize + + + + + ARUSER + + + m_axi_aruser + + + + + ARVALID + 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xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_5 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_5 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_5 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 5 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.1 + + + + + + + + + + diff --git a/firmware/ip/axis_constant_iq/src/axi_slv.vhd b/firmware/ip/axis_constant_iq/src/axi_slv.vhd new file mode 100644 index 0000000..208a6d4 --- /dev/null +++ b/firmware/ip/axis_constant_iq/src/axi_slv.vhd @@ -0,0 +1,517 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + REAL_REG : out std_logic_vector (31 downto 0); + IMAG_REG : out std_logic_vector (31 downto 0); + WE_REG : out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + -- 4 : TAVG_LOW_REG (r). + -- 5 : TAVG_HIGH_REG(r). + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Output Registers. + REAL_REG <= slv_reg0(31 downto 0); + IMAG_REG <= slv_reg1(31 downto 0); + WE_REG <= slv_reg2(0); + +end rtl; + diff --git a/firmware/ip/axis_constant_iq/src/axis_constant_iq.vhd b/firmware/ip/axis_constant_iq/src/axis_constant_iq.vhd new file mode 100644 index 0000000..616a408 --- /dev/null +++ b/firmware/ip/axis_constant_iq/src/axis_constant_iq.vhd @@ -0,0 +1,219 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity axis_constant_iq is + Generic + ( + -- Number of bits of I/Q. + B : Integer := 16; + -- Number of parallel outputs. + N : Integer := 4 + ); + Port + ( + -- AXI-Lite Slave I/F. + s_axi_aclk : in std_logic; + s_axi_aresetn : in std_logic; + + s_axi_awaddr : in std_logic_vector(5 downto 0); + s_axi_awprot : in std_logic_vector(2 downto 0); + s_axi_awvalid : in std_logic; + s_axi_awready : out std_logic; + + s_axi_wdata : in std_logic_vector(31 downto 0); + s_axi_wstrb : in std_logic_vector(3 downto 0); + s_axi_wvalid : in std_logic; + s_axi_wready : out std_logic; + + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic; + s_axi_bready : in std_logic; + + s_axi_araddr : in std_logic_vector(5 downto 0); + s_axi_arprot : in std_logic_vector(2 downto 0); + s_axi_arvalid : in std_logic; + s_axi_arready : out std_logic; + + s_axi_rdata : out std_logic_vector(31 downto 0); + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_rvalid : out std_logic; + s_axi_rready : in std_logic; + + -- AXIS Master I/F. + m_axis_aclk : in std_logic; + m_axis_aresetn : in std_logic; + m_axis_tdata : out std_logic_vector(2*B*N-1 downto 0); + m_axis_tvalid : out std_logic + ); +end axis_constant_iq; + +architecture rtl of axis_constant_iq is + +-- Synchronizer. +component synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end component; + +-- AXI Slave. +component axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + REAL_REG : out std_logic_vector (31 downto 0); + IMAG_REG : out std_logic_vector (31 downto 0); + WE_REG : out std_logic + ); +end component; + +-- Number of bits of IQ combined. +constant BIQ : Integer := 2*B; + +-- Registers. +signal REAL_REG : std_logic_vector (31 downto 0); +signal IMAG_REG : std_logic_vector (31 downto 0); +signal WE_REG : std_logic; + +-- we. +signal we : std_logic; +signal we_r : std_logic; +signal we_int : std_logic; + +-- i/q. +signal real_r : std_logic_vector (B-1 downto 0); +signal imag_r : std_logic_vector (B-1 downto 0); + +begin + +-- Synchronizer. +WE_REG_resync_i : synchronizer_n + port map ( + rstn => m_axis_aresetn , + clk => m_axis_aclk , + data_in => WE_REG , + data_out => we + ); + +-- AXI Slave. +axi_slv_i : axi_slv + Port map + ( + aclk => s_axi_aclk , + aresetn => s_axi_aresetn , + + -- Write Address Channel. + awaddr => s_axi_awaddr , + awprot => s_axi_awprot , + awvalid => s_axi_awvalid , + awready => s_axi_awready , + + -- Write Data Channel. + wdata => s_axi_wdata , + wstrb => s_axi_wstrb , + wvalid => s_axi_wvalid , + wready => s_axi_wready , + + -- Write Response Channel. + bresp => s_axi_bresp , + bvalid => s_axi_bvalid , + bready => s_axi_bready , + + -- Read Address Channel. + araddr => s_axi_araddr , + arprot => s_axi_arprot , + arvalid => s_axi_arvalid , + arready => s_axi_arready , + + -- Read Data Channel. + rdata => s_axi_rdata , + rresp => s_axi_rresp , + rvalid => s_axi_rvalid , + rready => s_axi_rready , + + -- Registers. + REAL_REG => REAL_REG , + IMAG_REG => IMAG_REG , + WE_REG => WE_REG + ); + +process (m_axis_aclk) +begin + if (rising_edge(m_axis_aclk)) then + if ( m_axis_aresetn = '0' ) then + -- we. + we_r <= '0'; + + -- i/q. + real_r <= (others => '0'); + imag_r <= (others => '0'); + else + -- we. + we_r <= we; + + -- i/q. + if (we_int = '1') then + real_r <= REAL_REG(B-1 downto 0); + imag_r <= IMAG_REG(B-1 downto 0); + end if; + end if; + end if; +end process; + +-- we generation. +we_int <= not(we_r) and we; + +-- Output generation. +GEN_OUT: for I in 0 to N-1 generate + m_axis_tdata ( B + BIQ*I-1 downto BIQ*I ) <= real_r; + m_axis_tdata (2*B + BIQ*I-1 downto BIQ*I + B ) <= imag_r; +end generate GEN_OUT; + +m_axis_tvalid <= '1'; + +end rtl; + diff --git a/firmware/ip/axis_constant_iq/src/synchronizer_n.vhd b/firmware/ip/axis_constant_iq/src/synchronizer_n.vhd new file mode 100644 index 0000000..925425d --- /dev/null +++ b/firmware/ip/axis_constant_iq/src/synchronizer_n.vhd @@ -0,0 +1,42 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library common_lib; +use common_lib.all; + +entity synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end synchronizer_n; + +architecture rtl of synchronizer_n is + +-- Internal register. +signal data_int_reg : std_logic_vector (N-1 downto 0); + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_constant_iq/src/tb.sv b/firmware/ip/axis_constant_iq/src/tb.sv new file mode 100644 index 0000000..9ed93fc --- /dev/null +++ b/firmware/ip/axis_constant_iq/src/tb.sv @@ -0,0 +1,198 @@ +// VIP: axi_mst_0 +// DUT: axis_chsel_pfb +// IF: s_axi -> axi_mst_0 + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter B = 16; +parameter N = 8; + +// s_axi interfase. +reg s_axi_aclk; +wire [5:0] s_axi_araddr; +reg s_axi_aresetn; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +// m_axis interfase. +reg m_axis_aclk; +reg m_axis_aresetn; +wire [2*B*N-1:0] m_axis_tdata; +wire m_axis_tvalid; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data_rd; +reg[31:0] data; +xil_axi_resp_t resp; + +// TB control. +reg tb_start; + +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk), + .aresetn (s_axi_aresetn), + .m_axi_araddr (s_axi_araddr), + .m_axi_arprot (s_axi_arprot), + .m_axi_arready (s_axi_arready), + .m_axi_arvalid (s_axi_arvalid), + .m_axi_awaddr (s_axi_awaddr), + .m_axi_awprot (s_axi_awprot), + .m_axi_awready (s_axi_awready), + .m_axi_awvalid (s_axi_awvalid), + .m_axi_bready (s_axi_bready), + .m_axi_bresp (s_axi_bresp), + .m_axi_bvalid (s_axi_bvalid), + .m_axi_rdata (s_axi_rdata), + .m_axi_rready (s_axi_rready), + .m_axi_rresp (s_axi_rresp), + .m_axi_rvalid (s_axi_rvalid), + .m_axi_wdata (s_axi_wdata), + .m_axi_wready (s_axi_wready), + .m_axi_wstrb (s_axi_wstrb), + .m_axi_wvalid (s_axi_wvalid) + ); + +axis_constant_iq + #( + .B(B), + .N(N) + ) + axis_constant_iq + ( + // s_axi interfase. + .s_axi_aclk (s_axi_aclk), + .s_axi_araddr (s_axi_araddr), + .s_axi_aresetn (s_axi_aresetn), + .s_axi_arprot (s_axi_arprot), + .s_axi_arready (s_axi_arready), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awprot (s_axi_awprot), + .s_axi_awready (s_axi_awready), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_bready (s_axi_bready), + .s_axi_bresp (s_axi_bresp), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_rdata (s_axi_rdata), + .s_axi_rready (s_axi_rready), + .s_axi_rresp (s_axi_rresp), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_wdata (s_axi_wdata), + .s_axi_wready (s_axi_wready), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wvalid (s_axi_wvalid), + + // m_axis interfase. + .m_axis_aclk (m_axis_aclk ), + .m_axis_aresetn (m_axis_aresetn ), + .m_axis_tdata (m_axis_tdata ), + .m_axis_tvalid (m_axis_tvalid ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + /* ************* */ + /* Main TB Start */ + /* ************* */ + + // Reset sequence. + s_axi_aresetn <= 0; + m_axis_aresetn <= 0; + tb_start <= 0; + #500; + s_axi_aresetn <= 1; + m_axis_aresetn <= 1; + + #1000; + + // Start data. + tb_start <= 1; + + // REAL_REG + data_wr = 123; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); + #10; + + // IMAG_REG + data_wr = 14; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(1*4, prot, data_wr, resp); + #10; + + // WE_REG + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(2*4, prot, data_wr, resp); + #10; + + #1000; + + // REAL_REG + data_wr = 55; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); + #10; + + // IMAG_REG + data_wr = 66; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(1*4, prot, data_wr, resp); + #10; + + // WE_REG + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(2*4, prot, data_wr, resp); + #10; + + // WE_REG + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(2*4, prot, data_wr, resp); + #10; + +end + +always begin + s_axi_aclk <= 0; + #10; + s_axi_aclk <= 1; + #10; +end + +always begin + m_axis_aclk <= 0; + #3; + m_axis_aclk <= 1; + #3; +end + +endmodule + diff --git a/firmware/ip/axis_constant_iq/xgui/axis_constant_iq_v1_0.tcl b/firmware/ip/axis_constant_iq/xgui/axis_constant_iq_v1_0.tcl new file mode 100644 index 0000000..1717489 --- /dev/null +++ b/firmware/ip/axis_constant_iq/xgui/axis_constant_iq_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "B" -parent ${Page_0} + ipgui::add_param $IPINST -name "N" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to update B when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to validate B + return true +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + + +proc update_MODELPARAM_VALUE.B { MODELPARAM_VALUE.B PARAM_VALUE.B } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.B}] ${MODELPARAM_VALUE.B} +} + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + diff --git a/firmware/ip/axis_dyn_readout_v1/component.xml b/firmware/ip/axis_dyn_readout_v1/component.xml new file mode 100644 index 0000000..428771a --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/component.xml @@ -0,0 +1,645 @@ + + + user.org + user + axis_dyn_readout_v1 + 1.0 + + + m0_axis + + + + + + + TDATA + + + m0_axis_tdata + + + + + TVALID + + + m0_axis_tvalid + + + + + TREADY + + + m0_axis_tready + + + + + + + true + + + + + + m1_axis + + + + + + + TDATA + + + m1_axis_tdata + + + + + TVALID + + + m1_axis_tvalid + + + + + TREADY + + + m1_axis_tready + + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m0_axis:m1_axis:s0_axis:s1_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s0_axis + + + + + + + TVALID + + + s0_axis_tvalid + + + + + TREADY + + + s0_axis_tready + + + + + TDATA + + + s0_axis_tdata + + + + + + s1_axis + + + + + + + TVALID + + + s1_axis_tvalid + + + + + TREADY + + + s1_axis_tready + + + + + TDATA + + + s1_axis_tdata + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_dyn_readout_v1 + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 098bbdad + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_dyn_readout_v1 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 098bbdad + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f835ce2d + + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_tdata + + in + + 87 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_axis_tdata + + in + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m0_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tdata + + out + + 255 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m1_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/fir.coe + coe + + + src/fir_compiler_0/fir_compiler_0.xci + xci + CELL_NAME_readout_top_i/down_conversion_fir_i/fir_i + + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i + + + src/down_conversion.v + verilogSource + + + src/down_conversion_fir.v + verilogSource + + + src/readout_top.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/axis_dyn_readout_v1.v + verilogSource + CHECKSUM_6896ccdb + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/fir.coe + coe + + + src/fir_compiler_0/fir_compiler_0.xci + xci + CELL_NAME_readout_top_i/down_conversion_fir_i/fir_i + + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i + + + src/down_conversion.v + verilogSource + + + src/down_conversion_fir.v + verilogSource + + + src/readout_top.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/axis_dyn_readout_v1.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_dyn_readout_v1_v1_0.tcl + tclSource + CHECKSUM_f835ce2d + XGUI_VERSION_2 + + + + AXIS readout block with digital down-conversion (32-bit, phase coherent), filtering and 8x decimation, configured through AXIS + + + Component_Name + axis_dyn_readout_v1_v1_0 + + + FULLSPEED_OUTPUT + Fullspeed Output + true + + + + + + zynquplus + + + /UserIP + + AXIS Dynamic Readout V1 + package_project + 3 + 2024-07-08T21:40:58Z + + /home/meeg/Soft/qick/firmware/ip/axis_dyn_readout_v1 + + + + 2022.1 + + + + + + + diff --git a/firmware/ip/axis_dyn_readout_v1/src/axis_dyn_readout_v1.v b/firmware/ip/axis_dyn_readout_v1/src/axis_dyn_readout_v1.v new file mode 100644 index 0000000..3591d58 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/axis_dyn_readout_v1.v @@ -0,0 +1,105 @@ +module axis_dyn_readout_v1 + ( + + // Reset and clock (s_axis, m0_axis, m1_axis). + aresetn , + aclk , + + // s0_axis: for pushing configurations. + s0_axis_tready , + s0_axis_tvalid , + s0_axis_tdata , + + // s0_axis: for input data (8x samples per clock). + s1_axis_tdata , + s1_axis_tvalid , + s1_axis_tready , + + // M0_AXIS: for output data (before filter and decimation, 8x samples + // per clock). + m0_axis_tready , + m0_axis_tvalid , + m0_axis_tdata , + + // M1_AXIS: for output data. + m1_axis_tready , + m1_axis_tvalid , + m1_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +localparam [15:0] N_DDS = 8; + +/*********/ +/* Ports */ +/*********/ + +input aresetn; +input aclk; + +output s0_axis_tready; +input s0_axis_tvalid; +input [87:0] s0_axis_tdata; + +output s1_axis_tready; +input s1_axis_tvalid; +input [N_DDS*16-1:0] s1_axis_tdata; + +input m0_axis_tready; +output m0_axis_tvalid; +output [N_DDS*32-1:0] m0_axis_tdata; + +input m1_axis_tready; +output m1_axis_tvalid; +output [32-1:0] m1_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ + +// Fifo. +wire fifo_wr_en ; +wire [87:0] fifo_din ; +wire fifo_full ; + +// Fifo connections. +assign fifo_wr_en = s0_axis_tvalid; +assign fifo_din = s0_axis_tdata; + +// Readout Top. +readout_top readout_top_i + ( + // Reset and clock (s0_axis, s1_axis, m0_axis, m1_axis). + .aresetn (aresetn ), + .aclk (aclk ), + + // Fifo interface. + .fifo_wr_en (fifo_wr_en ), + .fifo_full (fifo_full ), + .fifo_din (fifo_din ), + + // S_AXIS: for input data (8x samples per clock). + .s_axis_tdata (s1_axis_tdata ), + .s_axis_tvalid (s1_axis_tvalid ), + .s_axis_tready (s1_axis_tready ), + + // M0_AXIS: for output data (before filter and decimation, 8x samples + // per clock). + .m0_axis_tready (m0_axis_tready ), + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + + // M1_AXIS: for output data. + .m1_axis_tready (m1_axis_tready ), + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tdata (m1_axis_tdata ) + ); + +// Assign outputs. +assign s0_axis_tready = ~fifo_full; + +endmodule + diff --git a/firmware/ip/axis_dyn_readout_v1/src/ctrl.sv b/firmware/ip/axis_dyn_readout_v1/src/ctrl.sv new file mode 100644 index 0000000..deede17 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/ctrl.sv @@ -0,0 +1,377 @@ +//Format of waveform interface: +// |----------|-------|------|----------|----------|----------|---------| +// | 87 .. 84 | 83 | 82 | 81 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | +// |----------|-------|------|----------|----------|----------|---------| +// | xxxx | phrst | mode | outsel | nsamp | phase | freq | +// |----------|-------|------|----------|----------|----------|---------| +// freq : 32 bits +// phase : 32 bits +// nsamp : 16 bits +// outsel : 2 bits +// mode : 1 bit +// phrst : 1 bit +module ctrl + #( + parameter N = 4 + ) + ( + // Reset and clock. + input wire aresetn , + input wire aclk , + + // Fifo interface. + output wire fifo_rd_en , + input wire fifo_empty , + input wire [87:0] fifo_dout , + + // dds control. + output wire [N*72-1:0] dds_ctrl , + + // Output source selection. + output wire [1:0] outsel + + // Output enable. +// output wire en + ); + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// Fifo dout register. +reg [87:0] fifo_dout_r; + +// Non-stop counter for time calculation (adds N samples each clock tick). +reg [31:0] cnt_n; +reg [31:0] cnt_n_reg; + +// Pinc/phase. +wire [31:0] pinc_int; +reg [31:0] pinc_r1; +reg [31:0] pinc_r2; +wire [31:0] pinc_N; +reg [31:0] pinc_N_r1; +reg [31:0] pinc_N_r2; +reg [31:0] pinc_N_r3; +reg [31:0] pinc_N_r4; +reg [31:0] pinc_N_r5; +wire [31:0] pinc_Nm; +reg [31:0] pinc_Nm_r1; +reg [31:0] pinc_Nm_r2; +reg [31:0] pinc_Nm_r3; + +wire [31:0] phase_int; +reg [31:0] phase_r1; +reg [31:0] phase_r2; +reg [31:0] phase_r3; +reg [31:0] phase_r4; +reg [31:0] phase_r5; +wire [31:0] phase_0; +reg [31:0] phase_0_r1; + +// Phase vectors. +wire [31:0] phase_v0 [N]; +reg [31:0] phase_v0_r1 [N]; +reg [31:0] phase_v0_r2 [N]; +reg [31:0] phase_v0_r3 [N]; +reg [31:0] phase_v0_r4 [N]; +wire [31:0] phase_v1 [N]; +reg [31:0] phase_v1_r1 [N]; + +// sync. +reg sync_reg; +reg sync_reg_r1; +reg sync_reg_r2; +reg sync_reg_r3; +reg sync_reg_r4; +reg sync_reg_r5; +reg sync_reg_r6; +reg sync_reg_r7; + +// Number of samples. +wire [15:0] nsamp_int; + +// Output selection. +wire [1:0] outsel_int; +reg [1:0] outsel_r1; +reg [1:0] outsel_r2; +reg [1:0] outsel_r3; +reg [1:0] outsel_r4; +reg [1:0] outsel_r5; +reg [1:0] outsel_r6; +reg [1:0] outsel_r7; + +// Mode. +wire mode_int; + +// Phase reset. +wire phrst_int; + +// Load enable flag. +wire load_int; +reg load_r; + +// Fifo Read Enable. +reg rd_en_int; +reg rd_en_r1; +reg rd_en_r2; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +//reg en_reg; +//reg en_reg_r1; +//reg en_reg_r2; +//reg en_reg_r3; +//reg en_reg_r4; +//reg en_reg_r5; +//reg en_reg_r6; +//reg en_reg_r7; +//reg en_reg_r8; + +// Registers. +always @(posedge aclk) begin + if (~aresetn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Non-stop counter for time calculation. + cnt_n <= 0; + cnt_n_reg <= 0; + + // Pinc/phase/sync. + pinc_r1 <= 0; + pinc_r2 <= 0; + pinc_N_r1 <= 0; + pinc_N_r2 <= 0; + pinc_N_r3 <= 0; + pinc_N_r4 <= 0; + pinc_N_r5 <= 0; + pinc_Nm_r1 <= 0; + pinc_Nm_r2 <= 0; + pinc_Nm_r3 <= 0; + + phase_r1 <= 0; + phase_r2 <= 0; + phase_r3 <= 0; + phase_r4 <= 0; + phase_r5 <= 0; + phase_0_r1 <= 0; + + sync_reg <= 0; + sync_reg_r1 <= 0; + sync_reg_r2 <= 0; + sync_reg_r3 <= 0; + sync_reg_r4 <= 0; + sync_reg_r5 <= 0; + sync_reg_r6 <= 0; + sync_reg_r7 <= 0; + + // Output selection. + outsel_r1 <= 0; + outsel_r2 <= 0; + outsel_r3 <= 0; + outsel_r4 <= 0; + outsel_r5 <= 0; + outsel_r6 <= 0; + outsel_r7 <= 0; + + // Load enable flag. + load_r <= 0; + + // Fifo Read Enable. + rd_en_r1 <= 0; + rd_en_r2 <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. +// en_reg <= 0; +// en_reg_r1 <= 0; +// en_reg_r2 <= 0; +// en_reg_r3 <= 0; +// en_reg_r4 <= 0; +// en_reg_r5 <= 0; +// en_reg_r6 <= 0; +// en_reg_r7 <= 0; +// en_reg_r8 <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (mode_int || ~fifo_empty) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout; + + // Non-stop counter for time calculation. + if (sync_reg == 1'b1 && phrst_int == 1'b1) + cnt_n <= 0; + else + cnt_n <= cnt_n + N; + + if (sync_reg_r1 == 1'b1) + cnt_n_reg <= cnt_n; + + // Pinc/phase/sync. + pinc_r1 <= pinc_int; + pinc_r2 <= pinc_r1; + pinc_N_r1 <= pinc_N; + pinc_N_r2 <= pinc_N_r1; + pinc_N_r3 <= pinc_N_r2; + pinc_N_r4 <= pinc_N_r3; + pinc_N_r5 <= pinc_N_r4; + pinc_Nm_r1 <= pinc_Nm; + pinc_Nm_r2 <= pinc_Nm_r1; + pinc_Nm_r3 <= pinc_Nm_r2; + + phase_r1 <= phase_int; + phase_r2 <= phase_r1; + phase_r3 <= phase_r2; + phase_r4 <= phase_r3; + phase_r5 <= phase_r4; + phase_0_r1 <= phase_0; + + sync_reg <= load_r; + sync_reg_r1 <= sync_reg; + sync_reg_r2 <= sync_reg_r1; + sync_reg_r3 <= sync_reg_r2; + sync_reg_r4 <= sync_reg_r3; + sync_reg_r5 <= sync_reg_r4; + sync_reg_r6 <= sync_reg_r5; + sync_reg_r7 <= sync_reg_r6; + + // Output selection. + outsel_r1 <= outsel_int; + outsel_r2 <= outsel_r1; + outsel_r3 <= outsel_r2; + outsel_r4 <= outsel_r3; + outsel_r5 <= outsel_r4; + outsel_r6 <= outsel_r5; + outsel_r7 <= outsel_r6; + + // Load enable flag. + load_r <= load_int; + + // Fifo Read Enable. + rd_en_r1 <= rd_en_int; + rd_en_r2 <= rd_en_r1; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. +// if (~mode_int && rd_en_int) +// if (~fifo_empty) +// en_reg <= 1; +// else +// en_reg <= 0; + +// en_reg_r1 <= en_reg; +// en_reg_r2 <= en_reg_r1; +// en_reg_r3 <= en_reg_r2; +// en_reg_r4 <= en_reg_r3; +// en_reg_r5 <= en_reg_r4; +// en_reg_r6 <= en_reg_r5; +// en_reg_r7 <= en_reg_r6; +// en_reg_r8 <= en_reg_r7; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign pinc_int = fifo_dout_r[31:0]; +assign phase_int = fifo_dout_r[63:32]; +assign nsamp_int = fifo_dout_r[79:64]; +assign outsel_int = fifo_dout_r[81:80]; +assign mode_int = fifo_dout_r[82]; +assign phrst_int = fifo_dout_r[83]; + +// Frequency calculation. +assign pinc_N = pinc_r2*N; + +// Phase calculation. +assign pinc_Nm = pinc_r2*cnt_n_reg; +assign phase_0 = pinc_Nm_r3 + phase_r5; + +// Phase vectors. +generate +genvar i; + for (i=0; i < N; i = i + 1) begin : GEN_phase + // Registers. + always @(posedge aclk) begin + if (~aresetn) begin + // v0. + phase_v0_r1[i] <= 0; + phase_v0_r2[i] <= 0; + phase_v0_r3[i] <= 0; + phase_v0_r4[i] <= 0; + + // v1. + phase_v1_r1[i] <= 0; + end + else begin + // v0. + phase_v0_r1[i] <= phase_v0[i]; + phase_v0_r2[i] <= phase_v0_r1[i]; + phase_v0_r3[i] <= phase_v0_r2[i]; + phase_v0_r4[i] <= phase_v0_r3[i]; + + // v1. + phase_v1_r1[i] <= phase_v1[i]; + end + end + + // v0. + assign phase_v0[i] = pinc_r2*i; + + // v1. + assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; + + // dds_ctrl_o output. + assign dds_ctrl[i*72 +: 72] = {7'h00,sync_reg_r7,phase_v1_r1[i],pinc_N_r5}; + end +endgenerate + +// load_int. +assign load_int = rd_en_int & ~fifo_empty; + +// Assign outputs. +assign fifo_rd_en = rd_en_int; +assign outsel = outsel_r7; +//assign en = en_reg_r8; + +endmodule + diff --git a/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.veo b/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.veo new file mode 100644 index 0000000..7bf3bc5 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.veo @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:dds_compiler:6.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +dds_compiler_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [71 : 0] s_axis_phase_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file dds_compiler_0.v when simulating +// the core, dds_compiler_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.vho b/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.vho new file mode 100644 index 0000000..8bdeb4a --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.vho @@ -0,0 +1,83 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:dds_compiler:6.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT dds_compiler_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : dds_compiler_0 + PORT MAP ( + aclk => aclk, + s_axis_phase_tvalid => s_axis_phase_tvalid, + s_axis_phase_tdata => s_axis_phase_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file dds_compiler_0.vhd when simulating +-- the core, dds_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 0000000..f44852e --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,479 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_compiler_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 9 + 0 + 0 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 8 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 72 + 1 + 1 + zynquplus + Full_Range + 1 + dds_compiler_0 + Not_Required + 256 + Maximal + 0.06 + Coregen + false + false + false + false + 8 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + false + Auto + Twos_Complement + Speed + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 22 + TRUE + ../../../../qick_fw_sho/qick_tprocv2_216_kidsim/top/top.tmp/axis_dyn_readout_v1_v1_0_project/axis_dyn_readout_v1_v1_0_project.gen/sources_1/ip/dds_compiler_0 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.xml b/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.xml new file mode 100644 index 0000000..57bba34 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.xml @@ -0,0 +1,2846 @@ + + + xilinx.com + customized_ip + dds_compiler_0 + 1.0 + + + event_pinc_invalid_intf + + + + + + + INTERRUPT + + + event_pinc_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_poff_invalid_intf + + + + + + + INTERRUPT + + + event_poff_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_phase_in_invalid_intf + + + + + + + INTERRUPT + + + event_phase_in_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_phase_tlast_missing_intf + + + + + + + INTERRUPT + + + event_s_phase_tlast_missing + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_phase_tlast_unexpected_intf + + + + + + + INTERRUPT + + + event_s_phase_tlast_unexpected + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_phase_chanid_incorrect_intf + + + + + + + INTERRUPT + + + event_s_phase_chanid_incorrect + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_config_tlast_missing_intf + + + + + + + INTERRUPT + + + event_s_config_tlast_missing + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_config_tlast_unexpected_intf + + + + + + + INTERRUPT + + + event_s_config_tlast_unexpected + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + S_AXIS_PHASE + S_AXIS_PHASE + + + + + + + TDATA + + + s_axis_phase_tdata + + + + + TLAST + + + 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xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + GENtimestamp + Fri Feb 18 20:02:41 UTC 2022 + + + outputProductCRC + 9:2d00cc37 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + dds_compiler_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Fri Feb 18 20:02:41 UTC 2022 + + + outputProductCRC + 9:2d00cc37 + + + + + + + aclk + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + aclken + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + 0x1 + + + + + + false + + + + + + aresetn + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + 0x1 + + + + + + false + + + + + + s_axis_phase_tvalid + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + s_axis_phase_tready + + out + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + s_axis_phase_tdata + + in + + 71 + 0 + + + + std_logic_vector + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axis_phase_tlast + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + s_axis_phase_tuser + + in + + 0 + 0 + + + + std_logic_vector + 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C_HAS_PHASE_OUT + 0 + + + C_HAS_PHASEGEN + 1 + + + C_HAS_SINCOS + 1 + + + C_LATENCY + 8 + + + C_MEM_TYPE + 1 + + + C_NEGATIVE_COSINE + 0 + + + C_NEGATIVE_SINE + 0 + + + C_NOISE_SHAPING + 1 + + + C_OUTPUTS_REQUIRED + 2 + + + C_OUTPUT_FORM + 0 + + + C_OUTPUT_WIDTH + 16 + + + C_PHASE_ANGLE_WIDTH + 14 + + + C_PHASE_INCREMENT + 3 + + + C_PHASE_INCREMENT_VALUE + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + + + C_RESYNC + 1 + + + C_PHASE_OFFSET + 3 + + + C_PHASE_OFFSET_VALUE + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + + + C_OPTIMISE_GOAL + 1 + + + C_USE_DSP48 + 1 + + + C_POR_MODE + 0 + + + C_AMPLITUDE + 0 + + + C_HAS_ACLKEN + 0 + + + C_HAS_ARESETN + 0 + + + C_HAS_TLAST + 0 + + + C_HAS_TREADY + 0 + + + C_HAS_S_PHASE + 1 + + + C_S_PHASE_TDATA_WIDTH + 72 + + + C_S_PHASE_HAS_TUSER + 0 + + + C_S_PHASE_TUSER_WIDTH + 1 + + + C_HAS_S_CONFIG + 0 + + + C_S_CONFIG_SYNC_MODE + 0 + + + C_S_CONFIG_TDATA_WIDTH + 1 + + + C_HAS_M_DATA + 1 + + + C_M_DATA_TDATA_WIDTH + 32 + + + C_M_DATA_HAS_TUSER + 0 + + + C_M_DATA_TUSER_WIDTH + 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System_Parameters + Hardware_Parameters + + + choice_pairs_75713637 + Packet_Framing + Not_Required + + + choice_pairs_8b9a47c2 + Auto + None + Phase_Dithering + Taylor_Series_Corrected + + + choice_pairs_944fe41d + Phase_Generator_and_SIN_COS_LUT + Phase_Generator_only + SIN_COS_LUT_only + + + choice_pairs_a54f933f + Sine + Cosine + Sine_and_Cosine + + + choice_pairs_d463c5cb + User_Field + Not_Required + + + choice_pairs_dac1efef + Not_Required + + + choice_pairs_f611af79 + On_Vector + On_Packet + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + dds_compiler_0.vho + vhdlTemplate + + + dds_compiler_0.veo + verilogTemplate + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + hdl/xbip_pipe_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_pipe_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + hdl/xbip_bram18k_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_bram18k_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + hdl/mult_gen_v12_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + mult_gen_v12_0_16 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_wrapper_v3_0_4 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_addsub_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_multadd_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/dds_compiler_v6_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + dds_compiler_v6_0_20 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/dds_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. + + + Component_Name + Component Name + dds_compiler_0 + + + PartsPresent + Configuration Options + Phase_Generator_and_SIN_COS_LUT + + + DDS_Clock_Rate + System Clock + 256 + + + Channels + Number of Channels + 1 + + + Mode_of_Operation + Mode Of Operation + Standard + + + Modulus + Modulus + 9 + + + Parameter_Entry + Parameter Selection + System_Parameters + + + Spurious_Free_Dynamic_Range + Spurious Free Dynamic Range + 96 + + + Frequency_Resolution + Frequency Resolution + 0.06 + + + Noise_Shaping + Noise Shaping + Auto + + + Phase_Width + Phase Width + 32 + + + Output_Width + Output Width + 16 + + + Phase_Increment + Phase Increment + Streaming + + + Resync + Resync + true + + + Phase_offset + Phase Offset + Streaming + + + Output_Selection + Output Selection + Sine_and_Cosine + + + Negative_Sine + Negative Sine + false + + + Negative_Cosine + Negative Cosine + false + + + Amplitude_Mode + Amplitude Mode + Full_Range + + + Memory_Type + Memory Type + Auto + + + Optimization_Goal + Optimization Goal + Speed + + + DSP48_Use + DSP48 Use + Maximal + + + Has_Phase_Out + Has Phase Out + false + + + DATA_Has_TLAST + DATA Has TLAST + Not_Required + + + Has_TREADY + Output TREADY + false + + + S_PHASE_Has_TUSER + Input + Not_Required + + + S_PHASE_TUSER_Width + User Field Width + 1 + + + M_DATA_Has_TUSER + DATA Output + Not_Required + + + M_PHASE_Has_TUSER + PHASE Output + Not_Required + + + S_CONFIG_Sync_Mode + Synchronization Mode + On_Vector + + + OUTPUT_FORM + Output Form + Twos_Complement + + + Latency_Configuration + Configurable + + + Latency + 8 + + + Has_ARESETn + ARESETn (active low) + false + + + Has_ACLKEN + ACLKEN + false + + + Output_Frequency1 + 0 + + + PINC1 + 0 + + + Phase_Offset_Angles1 + 0 + + + POFF1 + 0 + + + Output_Frequency2 + 0 + + + PINC2 + 0 + + + Phase_Offset_Angles2 + 0 + + + POFF2 + 0 + + + Output_Frequency3 + 0 + + + PINC3 + 0 + + + Phase_Offset_Angles3 + 0 + + + POFF3 + 0 + + + Output_Frequency4 + 0 + + + PINC4 + 0 + + + Phase_Offset_Angles4 + 0 + + + POFF4 + 0 + + + Output_Frequency5 + 0 + + + PINC5 + 0 + + + Phase_Offset_Angles5 + 0 + + + POFF5 + 0 + + + Output_Frequency6 + 0 + + + PINC6 + 0 + + + Phase_Offset_Angles6 + 0 + + + POFF6 + 0 + + + Output_Frequency7 + 0 + + + PINC7 + 0 + + + Phase_Offset_Angles7 + 0 + + + POFF7 + 0 + + + Output_Frequency8 + 0 + + + PINC8 + 0 + + + Phase_Offset_Angles8 + 0 + + + POFF8 + 0 + + + Output_Frequency9 + 0 + + + PINC9 + 0 + + + Phase_Offset_Angles9 + 0 + + + POFF9 + 0 + + + Output_Frequency10 + 0 + + + PINC10 + 0 + + + Phase_Offset_Angles10 + 0 + + + POFF10 + 0 + + + Output_Frequency11 + 0 + + + PINC11 + 0 + + + Phase_Offset_Angles11 + 0 + + + POFF11 + 0 + + + Output_Frequency12 + 0 + + + PINC12 + 0 + + + Phase_Offset_Angles12 + 0 + + + POFF12 + 0 + + + Output_Frequency13 + 0 + + + PINC13 + 0 + + + Phase_Offset_Angles13 + 0 + + + POFF13 + 0 + + + Output_Frequency14 + 0 + + + PINC14 + 0 + + + Phase_Offset_Angles14 + 0 + + + POFF14 + 0 + + + Output_Frequency15 + 0 + + + PINC15 + 0 + + + Phase_Offset_Angles15 + 0 + + + POFF15 + 0 + + + Output_Frequency16 + 0 + + + PINC16 + 0 + + + Phase_Offset_Angles16 + 0 + + + POFF16 + 0 + + + POR_mode + POR Mode + false + + + GUI_Behaviour + Coregen + + + explicit_period + false + + + period + 1 + + + + + DDS Compiler + 20 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_dyn_readout_v1/src/down_conversion.v b/firmware/ip/axis_dyn_readout_v1/src/down_conversion.v new file mode 100644 index 0000000..104ab9e --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/down_conversion.v @@ -0,0 +1,229 @@ +module down_conversion ( + // Reset and clock. + rstn , + clk , + + // S_AXIS for input. + s_axis_tready_o , + s_axis_tvalid_i , + s_axis_tdata_i , + + // M_AXIS for output. + m_axis_tready_i , + m_axis_tvalid_o , + m_axis_tdata_o , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [15:0] N_DDS = 16; + +// 0.5 for rounding. +localparam [31:0] RND_0P5 = 2**15; + +/*********/ +/* Ports */ +/*********/ +input rstn; +input clk; + +output s_axis_tready_o; +input s_axis_tvalid_i; +input [N_DDS*16-1:0] s_axis_tdata_i; + +input m_axis_tready_i; +output m_axis_tvalid_o; +output [N_DDS*32-1:0] m_axis_tdata_o; + +output fifo_rd_en_o; +input fifo_empty_i; +input [87:0] fifo_dout_i; + +/********************/ +/* Internal signals */ +/********************/ +// DDS input control. +reg dds_tvalid_r; +wire [N_DDS*72-1:0] dds_ctrl_int; +reg [N_DDS*72-1:0] dds_ctrl_int_r; + +// Output selection. +wire [1:0] outsel_int; + +// DDS output. +wire [31:0] dds_dout [0:N_DDS-1]; +reg [31:0] dds_dout_r1 [0:N_DDS-1]; +reg [31:0] dds_dout_r2 [0:N_DDS-1]; +reg [31:0] dds_dout_r3 [0:N_DDS-1]; +reg [31:0] dds_dout_r4 [0:N_DDS-1]; + +// Input data. +reg [15:0] din_r1 [0:N_DDS-1]; +reg signed [15:0] din_r2 [0:N_DDS-1]; +reg [15:0] din_r3 [0:N_DDS-1]; +reg [15:0] din_r4 [0:N_DDS-1]; + +// Product. +wire signed [15:0] pa_real [0:N_DDS-1]; +wire signed [15:0] pa_imag [0:N_DDS-1]; +wire signed [31:0] py_full_real [0:N_DDS-1]; +wire signed [31:0] py_full_imag [0:N_DDS-1]; +reg signed [31:0] py_full_real_r [0:N_DDS-1]; +reg signed [31:0] py_full_imag_r [0:N_DDS-1]; +wire signed [31:0] py_round_real [0:N_DDS-1]; +wire signed [31:0] py_round_imag [0:N_DDS-1]; +wire [15:0] py_real [0:N_DDS-1]; +wire [15:0] py_imag [0:N_DDS-1]; +wire [31:0] py [0:N_DDS-1]; +reg [31:0] py_r [0:N_DDS-1]; + +// Muxed output. +wire [31:0] dout_mux [0:N_DDS-1]; +reg [31:0] dout_mux_r [0:N_DDS-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Control block. +ctrl + #( + .N (N_DDS ) + ) + ctrl_i + ( + // Reset and clock. + .aresetn (rstn ), + .aclk (clk ), + + // Fifo interface. + .fifo_rd_en (fifo_rd_en_o ), + .fifo_empty (fifo_empty_i ), + .fifo_dout (fifo_dout_i ), + + // dds control. + .dds_ctrl (dds_ctrl_int ), + + // Output source selection. + .outsel (outsel_int ) + ); + +generate +genvar i; + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_dyn_readout_v1/src/fifo/fifo_axi.vhd b/firmware/ip/axis_dyn_readout_v1/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_dyn_readout_v1/src/fifo/fifo_dc.vhd b/firmware/ip/axis_dyn_readout_v1/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_dyn_readout_v1/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_dyn_readout_v1/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_dyn_readout_v1/src/fifo/gray2bin.vhd b/firmware/ip/axis_dyn_readout_v1/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_dyn_readout_v1/src/fifo/rd2axi.vhd b/firmware/ip/axis_dyn_readout_v1/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_dyn_readout_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_dyn_readout_v1/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_dyn_readout_v1/src/fir.coe b/firmware/ip/axis_dyn_readout_v1/src/fir.coe new file mode 100644 index 0000000..458482d --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fir.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -56,-4,13,47,97,166,252,353,463,573,674,754,801,804,753,643,473,249,-20,-314,-611,-885,-1107,-1248,-1285,-1201,-989,-651,-206,318,878,1425,1903,2254,2428,2383,2094,1556,786,-172,-1251,-2364,-3408,-4271,-4839,-5010,-4696,-3838,-2410,-422,2076,4993,8205,11560,14889,18012,20758,22971,24523,25322,25322,24523,22971,20758,18012,14889,11560,8205,4993,2076,-422,-2410,-3838,-4696,-5010,-4839,-4271,-3408,-2364,-1251,-172,786,1556,2094,2383,2428,2254,1903,1425,878,318,-206,-651,-989,-1201,-1285,-1248,-1107,-885,-611,-314,-20,249,473,643,753,804,801,754,674,573,463,353,252,166,97,47,13,-4,-56 \ No newline at end of file diff --git a/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0.v b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0.v new file mode 100644 index 0000000..aab1311 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0.v @@ -0,0 +1,15 @@ +module fir_compiler_0 + ( + input aclk , + input s_axis_data_tvalid , + output s_axis_data_tready , + input [255:0] s_axis_data_tdata , + output m_axis_data_tvalid , + output [31:0] m_axis_data_tdata +); + +assign s_axis_data_tready = 1'b1; +assign m_axis_data_tvalid = s_axis_data_tvalid; +assign m_axis_data_tdata = s_axis_data_tdata[31:0]; + +endmodule diff --git a/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.veo b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.veo new file mode 100644 index 0000000..e66a3e8 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fir_compiler:7.2 +// IP Revision: 15 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fir_compiler_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready + .s_axis_data_tdata(s_axis_data_tdata), // input wire [255 : 0] s_axis_data_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fir_compiler_0.v when simulating +// the core, fir_compiler_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.vho b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.vho new file mode 100644 index 0000000..a877167 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fir_compiler:7.2 +-- IP Revision: 15 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT fir_compiler_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_data_tvalid : IN STD_LOGIC; + s_axis_data_tready : OUT STD_LOGIC; + s_axis_data_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : fir_compiler_0 + PORT MAP ( + aclk => aclk, + s_axis_data_tvalid => s_axis_data_tvalid, + s_axis_data_tready => s_axis_data_tready, + s_axis_data_tdata => s_axis_data_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file fir_compiler_0.vhd when simulating +-- the core, fir_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.xci b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.xci new file mode 100644 index 0000000..5863c0c --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.xci @@ -0,0 +1,475 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_compiler_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.0 + 32 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 35,35 + 35,35,35,35,35,35,35,35,35,35,35,35,35,35,35,35 + fixed + fir_compiler_0.mif + 60 + 2 + 0 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 + 0 + 16 + 60 + 1 + 4 + fir_compiler_0 + 0 + 0 + 1 + 2 + 0 + 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 + 0 + 0 + -0,2,4,6,8,10,12,14;-1,3,5,7,9,11,13,15;0,-2,4,6,8,10,12,14;1,-3,5,7,9,11,13,15;0,2,-4,6,8,10,12,14;1,3,-5,7,9,11,13,15;0,2,4,-6,8,10,12,14;1,3,5,-7,9,11,13,15;0,2,4,6,-8,10,12,14;1,3,5,7,-9,11,13,15;0,2,4,6,8,-10,12,14;1,3,5,7,9,-11,13,15;0,2,4,6,8,10,-12,14;1,3,5,7,9,11,-13,15;0,2,4,6,8,10,12,-14;1,3,5,7,9,11,13,-15 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 + 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 + 16 + 1 + ./ + none + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 2 + 67 + 1 + 0 + 0 + 32 + 1 + 1 + 1 + 60 + 1 + 120 + 0 + 0 + none + 0,2,4,6,8,10,12,-14;1,3,5,7,9,11,13,-15 + 16,16 + 1 + 16 + 1 + 14,15,14,15,14,15,14,15,14,15,14,15,14,15,14,15 + 1 + 2 + 1 + 0 + 0 + 256 + 1 + zynquplus + 1 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../fir.coe + 0 + false + 1 + Signed + Inferred + 16 + 60 + fir_compiler_0 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 8 + false + false + Systolic_Multiply_Accumulate + 1 + Decimation + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Output_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + false + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../qick_fw_sho/qick_tprocv2_216_kidsim/top/top.tmp/axis_dyn_readout_v1_v1_0_project/axis_dyn_readout_v1_v1_0_project.gen/sources_1/ip/fir_compiler_0 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.xml b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.xml new file mode 100644 index 0000000..8dedd26 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.xml @@ -0,0 +1,2564 @@ + + + xilinx.com + customized_ip + fir_compiler_0 + 1.0 + + + event_s_data_tlast_missing_intf + + + + + + + INTERRUPT + + + event_s_data_tlast_missing + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_data_tlast_unexpected_intf + + + + + + + INTERRUPT + + + event_s_data_tlast_unexpected + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_data_chanid_incorrect_intf + + + + + + + INTERRUPT + + + event_s_data_chanid_incorrect + + + + + + SENSITIVITY + EDGE_RISING + + + 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Convergent_Rounding_to_Even + Convergent_Rounding_to_Odd + + + choice_pairs_2074757d + None + All + Data_Path_Fanout + Pre-Adder_Pipeline + Coefficient_Fanout + Control_Path_Fanout + Control_Column_Fanout + Control_Broadcast_Fanout + Control_LUT_Pipeline + No_BRAM_Read_First_Mode + Optimal_Column_Lengths + Data_Path_Broadcast + Disable_Half_Band_Centre_Tap + No_SRL_Attributes + Other + + + choice_pairs_2b265cc8 + Frequency_Specification + Input_Sample_Period + Output_Sample_Period + + + choice_pairs_3ab545a3 + Not_Required + Chan_ID_Field + + + choice_pairs_480f8ce0 + Not_Required + Packet_Framing + + + choice_pairs_541959c1 + Inferred + Non_Symmetric + Symmetric + + + choice_pairs_74144f21 + COE_File + Vector + + + choice_pairs_789dfe7d + Single_Rate + Interpolation + Decimation + Hilbert + Interpolated + + + choice_pairs_8e2d2e35 + Not_Required + User_Field + + + choice_pairs_ab4ea833 + Systolic_Multiply_Accumulate + + + choice_pairs_b6c64168 + Single + By_Channel + + + choice_pairs_eb2746f0 + Integer + Fixed_Fractional + + + choice_pairs_f611af79 + On_Vector + On_Packet + + + choice_pairs_fd92e388 + Integer_Coefficients + Quantize_Only + Maximize_Dynamic_Range + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + fir_compiler_0.vho + vhdlTemplate + + + fir_compiler_0.veo + verilogTemplate + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + constraints/fir_compiler_v7_2.xdc + xdc + fir_compiler_v7_2_15 + + + fir_compiler_0.mif + mif + + + hdl/fir_compiler_v7_2_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + fir_compiler_v7_2_15 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/fir_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + The Xilinx FIR Compiler LogiCORE is a module for generation of high speed, compact filter implementations that can be configured to implement many different filtering functions. The core is fully synchronous, using a single clock, and is highly parameterizable, allowing designers to control the filter type, data and coefficient widths, the number of filter taps, the number of channels, etc. Multi-rate operation is supported. The core is delivered through the Xilinx Vivado IP Catalog and integrates seamlessly with the Xilinx design flow. + + + Component_Name + fir_compiler_0 + + + GUI_Behaviour + Coregen + + + CoefficientSource + COE_File + + + CoefficientVector + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + + + Coefficient_File + ../fir.coe + + + Coefficient_Sets + 1 + + + Coefficient_Reload + false + + + Filter_Type + Decimation + + + Rate_Change_Type + Integer + + + Interpolation_Rate + 1 + + + Decimation_Rate + 8 + + + Zero_Pack_Factor + 1 + + + Channel_Sequence + Basic + + + Number_Channels + 1 + + + Select_Pattern + All + + + Pattern_List + P4-0,P4-1,P4-2,P4-3,P4-4 + + + Number_Paths + 2 + + + RateSpecification + Output_Sample_Period + + + HardwareOversamplingRate + 1 + + + SamplePeriod + 1 + + + Sample_Frequency + 0.001 + + + Clock_Frequency + 300.0 + + + Coefficient_Sign + Signed + + + Quantization + Integer_Coefficients + + + Coefficient_Width + 16 + + + BestPrecision + false + + + Coefficient_Fractional_Bits + 0 + + + Coefficient_Structure + Inferred + + + Data_Sign + Signed + + + Data_Width + 16 + + + Data_Fractional_Bits + 0 + + + Output_Rounding_Mode + Symmetric_Rounding_to_Zero + + + Output_Width + 16 + + + Filter_Architecture + Systolic_Multiply_Accumulate + + + Optimization_Goal + Area + + + Optimization_Selection + None + + + Data_Path_Fanout + false + + + Pre_Adder_Pipeline + false + + + Coefficient_Fanout + false + + + Control_Path_Fanout + false + + + Control_Column_Fanout + false + + + Control_Broadcast_Fanout + false + + + Control_LUT_Pipeline + false + + + No_BRAM_Read_First_Mode + false + + + Optimal_Column_Lengths + false + + + Data_Path_Broadcast + false + + + Disable_Half_Band_Centre_Tap + false + + + No_SRL_Attributes + false + + + Other + false + + + Optimization_List + None + + + Data_Buffer_Type + Automatic + + + Coefficient_Buffer_Type + Automatic + + + Input_Buffer_Type + Automatic + + + Output_Buffer_Type + Automatic + + + Preference_For_Other_Storage + Automatic + + + Multi_Column_Support + Automatic + + + Inter_Column_Pipe_Length + 4 + + + ColumnConfig + 60 + + + DATA_Has_TLAST + Not_Required + + + M_DATA_Has_TREADY + false + + + S_DATA_Has_FIFO + false + + + S_DATA_Has_TUSER + Not_Required + + + M_DATA_Has_TUSER + Not_Required + + + DATA_TUSER_Width + 1 + + + S_CONFIG_Sync_Mode + On_Vector + + + S_CONFIG_Method + Single + + + Num_Reload_Slots + 1 + + + Has_ACLKEN + false + + + Has_ARESETn + false + + + Reset_Data_Vector + true + + + Blank_Output + false + + + Gen_MIF_from_Spec + false + + + Gen_MIF_from_COE + false + + + Reload_File + no_coe_file_loaded + + + Gen_MIF_Files + false + + + DisplayReloadOrder + false + + + Passband_Min + 0.0 + + + Passband_Max + 0.5 + + + Stopband_Min + 0.5 + + + Stopband_Max + 1.0 + + + Filter_Selection + 1 + + + + + FIR Compiler + 15 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_dyn_readout_v1/src/readout_top.v b/firmware/ip/axis_dyn_readout_v1/src/readout_top.v new file mode 100644 index 0000000..185b61b --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/readout_top.v @@ -0,0 +1,167 @@ +module readout_top + ( + // Reset and clock. + aresetn , + aclk , + + // Fifo interface. + fifo_wr_en , + fifo_full , + fifo_din , + + // S1_AXIS: for input data (8x samples per clock). + s_axis_tdata , + s_axis_tvalid , + s_axis_tready , + + // M0_AXIS: for output data (before filter and decimation, 8x samples + // per clock). + m0_axis_tready , + m0_axis_tvalid , + m0_axis_tdata , + + // M1_AXIS: for output data. + m1_axis_tready , + m1_axis_tvalid , + m1_axis_tdata + + // Registers. +// FREQ_REG , +// PHASE_REG , +// NSAMP_REG , +// OUTSEL_REG , +// MODE_REG , +// WE_REG + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +localparam [15:0] N_DDS = 8; + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +input fifo_wr_en; +output fifo_full; +input [87:0] fifo_din; + +output s_axis_tready; +input s_axis_tvalid; +input [N_DDS*16-1:0] s_axis_tdata; + +input m0_axis_tready; +output m0_axis_tvalid; +output [N_DDS*32-1:0] m0_axis_tdata; + +input m1_axis_tready; +output m1_axis_tvalid; +output [32-1:0] m1_axis_tdata; + +//input [31:0] FREQ_REG; +//input [31:0] PHASE_REG; +//input [15:0] NSAMP_REG; +//input [1:0] OUTSEL_REG; +//input MODE_REG; +//input WE_REG; + +/********************/ +/* Internal signals */ +/********************/ +//wire we; +//reg we_r; + +wire fifo_wr_en; +wire [87:0] fifo_din; +wire fifo_rd_en; +wire [87:0] fifo_dout; +wire fifo_full; +wire fifo_empty; + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// WE_REG sync. +//synchronizer_n +// WE_REG_resync_i +// ( +// .rstn (aresetn ), +// .clk (aclk ), +// .data_in (WE_REG ), +// .data_out (we ) +// ); + +// Down-conversion + Filter + Decimation. +down_conversion_fir + down_conversion_fir_i + ( + // Reset and clock. + .rstn (aresetn ), + .clk (aclk ), + + // S_AXIS for input. + .s_axis_tready_o (s_axis_tready ), + .s_axis_tvalid_i (s_axis_tvalid ), + .s_axis_tdata_i (s_axis_tdata ), + + // M0_AXIS for output data (before filter and decimation). + .m0_axis_tready_i (m0_axis_tready ), + .m0_axis_tvalid_o (m0_axis_tvalid ), + .m0_axis_tdata_o (m0_axis_tdata ), + + // M1_AXIS for output data. + .m1_axis_tready_i (m1_axis_tready ), + .m1_axis_tvalid_o (m1_axis_tvalid ), + .m1_axis_tdata_o (m1_axis_tdata ), + + // Fifo interface. + .fifo_rd_en_o (fifo_rd_en ), + .fifo_empty_i (fifo_empty ), + .fifo_dout_i (fifo_dout ) + ); + +// Fifo for queuing waveforms. +fifo + #( + // Data width. + .B (88), + + // Fifo depth. + .N (8) + ) + fifo_i + ( + .rstn (aresetn ), + .clk (aclk ), + + // Write I/F. + .wr_en (fifo_wr_en ), + .din (fifo_din ), + + // Read I/F. + .rd_en (fifo_rd_en ), + .dout (fifo_dout ), + + // Flags. + .full (fifo_full ), + .empty (fifo_empty ) + ); + +// Fifo connections. +//assign fifo_wr_en = we & ~we_r; +//assign fifo_din = {MODE_REG,OUTSEL_REG,NSAMP_REG,PHASE_REG,FREQ_REG}; + +//always @(posedge aclk) begin +// if (~aresetn) +// we_r <= 0; +// else +// we_r <= we; +//end + +endmodule + diff --git a/firmware/ip/axis_dyn_readout_v1/src/tb/tb.sv b/firmware/ip/axis_dyn_readout_v1/src/tb/tb.sv new file mode 100644 index 0000000..635fc27 --- /dev/null +++ b/firmware/ip/axis_dyn_readout_v1/src/tb/tb.sv @@ -0,0 +1,265 @@ +module tb(); + +localparam N = 8; + +// Reset and clock. +reg aresetn ; +reg aclk ; + +// s0_axis for pushing waveforms. +wire s0_axis_tready ; +reg s0_axis_tvalid ; +reg [87:0] s0_axis_tdata ; + +// s1_axis for input data (8 real samples per clock). +wire s1_axis_tready ; +reg s1_axis_tvalid ; +wire[N*16-1:0] s1_axis_tdata ; + +// m0_axis for output data (8 complex samples per clock). +reg m0_axis_tready ; +wire m0_axis_tvalid ; +wire[255:0] m0_axis_tdata ; + +// m1_axis for output data (1 complex sample per clock). +reg m1_axis_tready ; +wire m1_axis_tvalid ; +wire[31:0] m1_axis_tdata ; + +// Waveform parameters. +reg [31:0] freq_r ; +reg [31:0] phase_r ; +reg [15:0] nsamp_r ; +reg [1:0] outsel_r ; +reg mode_r ; +reg phrst_r ; +reg [3:0] zero_r ; + +// Input data. +reg [15:0] din_r [N] ; + +// Output full-speed data. +reg [31:0] dout_r_f [N] ; + +// Output data. +wire[15:0] dout_real ; +wire[15:0] dout_imag ; + +// Fast clock for parallel/serial conversion. +reg aclk_f ; +reg [15:0] din_r_f ; +reg [15:0] dout_real_f ; +reg [15:0] dout_imag_f ; + +// Test bench control. +reg tb_wave = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N; ii = ii + 1) begin : GEN_debug + assign s1_axis_tdata [ii*16 +: 16] = din_r[ii]; + assign dout_r_f[ii] = m0_axis_tdata[ii*32 +: 32]; +end +endgenerate + +assign dout_real = m1_axis_tdata[0 +: 16]; +assign dout_imag = m1_axis_tdata[16 +: 16]; + +assign s0_axis_tdata = {zero_r,phrst_r,mode_r,outsel_r,nsamp_r,phase_r,freq_r}; + +// DUT. +axis_dyn_readout_v1 + DUT + ( + // Reset and clock. + .aresetn , + .aclk , + + // s0_axis for pushing waveforms. + .s0_axis_tready , + .s0_axis_tvalid , + .s0_axis_tdata , + + // s1_axis for input data (8 real samples per clock). + .s1_axis_tready , + .s1_axis_tvalid , + .s1_axis_tdata , + + // m0_axis for output data (8 complex samples per clock). + .m0_axis_tready , + .m0_axis_tvalid , + .m0_axis_tdata , + + // m1_axis for output data (1 complex sample per clock). + .m1_axis_tready , + .m1_axis_tvalid , + .m1_axis_tdata + + ); + +initial begin + // Reset sequence. + aresetn <= 0; + m0_axis_tready <= 1; + m1_axis_tready <= 1; + #500; + aresetn <= 1; + + #1000; + + tb_wave <= 1; + +end + +// Input data. +initial begin + int n; + real fs, f, pi, a; + + s1_axis_tvalid <= 1; + + for (int i=0; i + + user.org + user + axis_kidsim_v3 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TLAST + + + m_axis_tlast + + + + + TVALID + + + m_axis_tvalid + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + FREQ_HZ + + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + FREQ_HZ + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + reg0 + 0 + 256 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axis_kidsim_v3 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 5845a86a + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axis_kidsim_v3 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 5845a86a + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + cbeb2227 + + + + + + + trigger + + in + + 7 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 7 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis 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+ + s_axis_tvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 255 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axis_tlast + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 255 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tlast + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + L + L + 8 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/dds/dds_0/dds_0.xci + xci + CELL_NAME_GEN_kidsim[0].kidsim_top_i/kidsim_i/dds_top_i/dds_i + + + src/axi_slv.v + verilogSource + + + src/dds/dds_ctrl.v + verilogSource + + + src/dds/dds_top.v + verilogSource + + + src/mems/latency_reg.v + verilogSource + + + src/iir/iir.sv + systemVerilogSource + + + src/iir/iir_iq.sv + systemVerilogSource + + + src/kidsim.sv + systemVerilogSource + + + src/kidsim_top.sv + systemVerilogSource + + + src/dds/mod_ctrl.sv + systemVerilogSource + + + src/prod.sv + systemVerilogSource + + + src/punct.sv + systemVerilogSource + + + src/mems/synchronizer_n.vhd + vhdlSource + + + src/axis_kidsim_v3.sv + systemVerilogSource + CHECKSUM_935fcf37 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dds/dds_0/dds_0.xci + xci + CELL_NAME_GEN_kidsim[0].kidsim_top_i/kidsim_i/dds_top_i/dds_i + + + src/axi_slv.v + verilogSource + + + src/dds/dds_ctrl.v + verilogSource + + + src/dds/dds_top.v + verilogSource + + + src/mems/latency_reg.v + verilogSource + + + src/iir/iir.sv + systemVerilogSource + + + src/iir/iir_iq.sv + systemVerilogSource + + + src/kidsim.sv + systemVerilogSource + + + src/kidsim_top.sv + systemVerilogSource + + + src/dds/mod_ctrl.sv + systemVerilogSource + + + src/prod.sv + systemVerilogSource + + + src/punct.sv + systemVerilogSource + + + src/mems/synchronizer_n.vhd + vhdlSource + + + src/axis_kidsim_v3.sv + systemVerilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_kidsim_v3_v1_0.tcl + tclSource + CHECKSUM_cbeb2227 + XGUI_VERSION_2 + + + + AXIS KID Simulator V3, with trigger for resonator dynamic shifting. + + + L + L + 8 + + + Component_Name + axis_kidsim_v3_v1_0 + + + + + + zynquplus + + + /UserIP + + AXIS KID Simulator V3 + package_project + 3 + 2023-04-25T16:36:13Z + + /home/lstefana/v20.2/ip/axis_kidsim_v3 + /home/lstefana/v20.2/ip/axis_kidsim_v3 + /home/lstefana/v20.2/ip/axis_kidsim_v3 + /home/lstefana/v20.2/ip/axis_kidsim_v3 + /home/lstefana/v20.2/ip/axis_kidsim_v3 + /home/lstefana/v20.2/ip/axis_kidsim_v3 + /home/lstefana/v20.2/ip/axis_kidsim_v3 + /home/lstefana/v20.2/ip/axis_kidsim_v3 + /home/lstefana/v20.2/ip/axis_kidsim_v3 + /home/lstefana/v20.2/ip/axis_kidsim_v3 + /home/lstefana/v20.2/ip/axis_kidsim_v3 + /home/lstefana/v20.2/ip/axis_kidsim_v3 + /home/lstefana/v20.2/ip/axis_kidsim_v3 + /home/lstefana/v20.2/ip/axis_kidsim_v3 + + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/axis_kidsim_v3/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_kidsim_v3/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..bf3f000 --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,318 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + + 100000000 + 0 + 0 + 0.0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 12 + TRUE + ../project_1/project_1.gen/sources_1/ip/axi_mst_0 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_kidsim_v3/src/axi_slv.v b/firmware/ip/axis_kidsim_v3/src/axi_slv.v new file mode 100644 index 0000000..2d899c2 --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/axi_slv.v @@ -0,0 +1,1046 @@ +`timescale 1 ns / 1 ps + +module axi_slv + ( + input wire s_axi_aclk , + input wire s_axi_aresetn , + + // Write Address Channel. + input wire [7:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + + // Write Data Channel. + input wire [31:0] s_axi_wdata , + input wire [3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + + // Write Response Channel. + output wire [1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + + // Read Address Channel. + input wire [7:0] s_axi_araddr , + input wire [2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + + // Read Data Channel. + output wire [31:0] s_axi_rdata , + output wire [1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , + + // Registers. + output wire [15:0] DDS_BVAL_REG , + output wire [15:0] DDS_SLOPE_REG , + output wire [15:0] DDS_STEPS_REG , + output wire [15:0] DDS_WAIT_REG , + output wire [15:0] DDS_FREQ_REG , + output wire [15:0] IIR_C0_REG , + output wire [15:0] IIR_C1_REG , + output wire [15:0] IIR_G_REG , + output wire [ 1:0] OUTSEL_REG , + output wire [15:0] PUNCT_ID_REG , + output wire [ 7:0] ADDR_REG , + output wire WE_REG +); + +// Width of S_AXI data bus +localparam integer C_S_AXI_DATA_WIDTH = 32; +// Width of S_AXI address bus +localparam integer C_S_AXI_ADDR_WIDTH = 8; + +// AXI4LITE signals +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr; +reg axi_awready; +reg axi_wready; +reg [1 : 0] axi_bresp; +reg axi_bvalid; +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr; +reg axi_arready; +reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata; +reg [1 : 0] axi_rresp; +reg axi_rvalid; + +// Example-specific design signals +// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH +// ADDR_LSB is used for addressing 32/64 bit registers/memories +// ADDR_LSB = 2 for 32 bits (n downto 2) +// ADDR_LSB = 3 for 64 bits (n downto 3) +localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1; +localparam integer OPT_MEM_ADDR_BITS = 5; +//---------------------------------------------- +//-- Signals for user logic register space example +//------------------------------------------------ +//-- Number of Slave Registers 64 +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg32; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg33; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg34; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg35; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg36; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg37; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg38; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg39; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg40; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg41; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg42; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg43; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg44; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg45; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg46; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg47; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg48; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg49; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg50; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg51; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg52; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg53; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg54; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg55; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg56; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg57; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg58; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg59; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg60; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg61; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg62; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg63; +wire slv_reg_rden; +wire slv_reg_wren; +reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out; +integer byte_index; +reg aw_en; + +// I/O Connections assignments + +assign s_axi_awready = axi_awready; +assign s_axi_wready = axi_wready; +assign s_axi_bresp = axi_bresp; +assign s_axi_bvalid = axi_bvalid; +assign s_axi_arready = axi_arready; +assign s_axi_rdata = axi_rdata; +assign s_axi_rresp = axi_rresp; +assign s_axi_rvalid = axi_rvalid; +// Implement axi_awready generation +// axi_awready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_awready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awready <= 1'b0; + aw_en <= 1'b1; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // slave is ready to accept write address when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_awready <= 1'b1; + aw_en <= 1'b0; + end + else if (s_axi_bready && axi_bvalid) + begin + aw_en <= 1'b1; + axi_awready <= 1'b0; + end + else + begin + axi_awready <= 1'b0; + end + end +end + +// Implement axi_awaddr latching +// This process is used to latch the address when both +// s_axi_awvalid and s_axi_wvalid are valid. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awaddr <= 0; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // Write Address latching + axi_awaddr <= s_axi_awaddr; + end + end +end + +// Implement axi_wready generation +// axi_wready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_wready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_wready <= 1'b0; + end + else + begin + if (~axi_wready && s_axi_wvalid && s_axi_awvalid && aw_en ) + begin + // slave is ready to accept write data when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_wready <= 1'b1; + end + else + begin + axi_wready <= 1'b0; + end + end +end + +// Implement memory mapped register select and write logic generation +// The write data is accepted and written to memory mapped registers when +// axi_awready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. Write strobes are used to +// select byte enables of slave registers while writing. +// These registers are cleared when reset (active low) is applied. +// Slave register write enable is asserted when valid address and data are available +// and the slave is ready to accept the write address and write data. +assign slv_reg_wren = axi_wready && s_axi_wvalid && axi_awready && s_axi_awvalid; + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + slv_reg0 <= 0; + slv_reg1 <= 0; + slv_reg2 <= 0; + slv_reg3 <= 0; + slv_reg4 <= 0; + slv_reg5 <= 0; + slv_reg6 <= 0; + slv_reg7 <= 0; + slv_reg8 <= 0; + slv_reg9 <= 0; + slv_reg10 <= 0; + slv_reg11 <= 0; + slv_reg12 <= 0; + slv_reg13 <= 0; + slv_reg14 <= 0; + slv_reg15 <= 0; + slv_reg16 <= 0; + slv_reg17 <= 0; + slv_reg18 <= 0; + slv_reg19 <= 0; + slv_reg20 <= 0; + slv_reg21 <= 0; + slv_reg22 <= 0; + slv_reg23 <= 0; + slv_reg24 <= 0; + slv_reg25 <= 0; + slv_reg26 <= 0; + slv_reg27 <= 0; + slv_reg28 <= 0; + slv_reg29 <= 0; + slv_reg30 <= 0; + slv_reg31 <= 0; + slv_reg32 <= 0; + slv_reg33 <= 0; + slv_reg34 <= 0; + slv_reg35 <= 0; + slv_reg36 <= 0; + slv_reg37 <= 0; + slv_reg38 <= 0; + slv_reg39 <= 0; + slv_reg40 <= 0; + slv_reg41 <= 0; + slv_reg42 <= 0; + slv_reg43 <= 0; + slv_reg44 <= 0; + slv_reg45 <= 0; + slv_reg46 <= 0; + slv_reg47 <= 0; + slv_reg48 <= 0; + slv_reg49 <= 0; + slv_reg50 <= 0; + slv_reg51 <= 0; + slv_reg52 <= 0; + slv_reg53 <= 0; + slv_reg54 <= 0; + slv_reg55 <= 0; + slv_reg56 <= 0; + slv_reg57 <= 0; + slv_reg58 <= 0; + slv_reg59 <= 0; + slv_reg60 <= 0; + slv_reg61 <= 0; + slv_reg62 <= 0; + slv_reg63 <= 0; + end + else begin + if (slv_reg_wren) + begin + case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 0 + slv_reg0[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h01: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 1 + slv_reg1[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h02: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 2 + slv_reg2[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h03: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 3 + slv_reg3[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h04: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 4 + slv_reg4[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h05: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 5 + slv_reg5[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h06: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 6 + slv_reg6[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h07: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 7 + slv_reg7[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h08: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 8 + slv_reg8[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h09: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 9 + slv_reg9[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 10 + slv_reg10[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 11 + slv_reg11[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 12 + slv_reg12[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 13 + slv_reg13[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 14 + slv_reg14[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 15 + slv_reg15[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h10: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 16 + slv_reg16[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h11: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 17 + slv_reg17[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h12: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 18 + slv_reg18[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h13: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 19 + slv_reg19[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h14: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 20 + slv_reg20[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h15: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 21 + slv_reg21[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h16: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 22 + slv_reg22[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h17: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 23 + slv_reg23[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h18: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 24 + slv_reg24[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h19: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 25 + slv_reg25[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 26 + slv_reg26[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 27 + slv_reg27[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 28 + slv_reg28[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 29 + slv_reg29[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 30 + slv_reg30[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 31 + slv_reg31[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h20: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 32 + slv_reg32[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h21: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 33 + slv_reg33[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h22: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 34 + slv_reg34[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h23: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 35 + slv_reg35[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h24: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 36 + slv_reg36[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h25: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 37 + slv_reg37[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h26: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 38 + slv_reg38[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h27: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 39 + slv_reg39[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h28: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 40 + slv_reg40[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h29: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 41 + slv_reg41[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 42 + slv_reg42[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 43 + slv_reg43[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 44 + slv_reg44[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 45 + slv_reg45[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 46 + slv_reg46[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 47 + slv_reg47[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h30: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 48 + slv_reg48[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h31: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 49 + slv_reg49[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h32: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 50 + slv_reg50[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h33: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 51 + slv_reg51[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h34: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 52 + slv_reg52[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h35: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 53 + slv_reg53[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h36: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 54 + slv_reg54[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h37: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 55 + slv_reg55[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h38: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 56 + slv_reg56[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h39: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 57 + slv_reg57[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 58 + slv_reg58[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 59 + slv_reg59[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 60 + slv_reg60[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 61 + slv_reg61[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 62 + slv_reg62[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 63 + slv_reg63[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + default : begin + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + slv_reg16 <= slv_reg16; + slv_reg17 <= slv_reg17; + slv_reg18 <= slv_reg18; + slv_reg19 <= slv_reg19; + slv_reg20 <= slv_reg20; + slv_reg21 <= slv_reg21; + slv_reg22 <= slv_reg22; + slv_reg23 <= slv_reg23; + slv_reg24 <= slv_reg24; + slv_reg25 <= slv_reg25; + slv_reg26 <= slv_reg26; + slv_reg27 <= slv_reg27; + slv_reg28 <= slv_reg28; + slv_reg29 <= slv_reg29; + slv_reg30 <= slv_reg30; + slv_reg31 <= slv_reg31; + slv_reg32 <= slv_reg32; + slv_reg33 <= slv_reg33; + slv_reg34 <= slv_reg34; + slv_reg35 <= slv_reg35; + slv_reg36 <= slv_reg36; + slv_reg37 <= slv_reg37; + slv_reg38 <= slv_reg38; + slv_reg39 <= slv_reg39; + slv_reg40 <= slv_reg40; + slv_reg41 <= slv_reg41; + slv_reg42 <= slv_reg42; + slv_reg43 <= slv_reg43; + slv_reg44 <= slv_reg44; + slv_reg45 <= slv_reg45; + slv_reg46 <= slv_reg46; + slv_reg47 <= slv_reg47; + slv_reg48 <= slv_reg48; + slv_reg49 <= slv_reg49; + slv_reg50 <= slv_reg50; + slv_reg51 <= slv_reg51; + slv_reg52 <= slv_reg52; + slv_reg53 <= slv_reg53; + slv_reg54 <= slv_reg54; + slv_reg55 <= slv_reg55; + slv_reg56 <= slv_reg56; + slv_reg57 <= slv_reg57; + slv_reg58 <= slv_reg58; + slv_reg59 <= slv_reg59; + slv_reg60 <= slv_reg60; + slv_reg61 <= slv_reg61; + slv_reg62 <= slv_reg62; + slv_reg63 <= slv_reg63; + end + endcase + end + end +end + +// Implement write response logic generation +// The write response and response valid signals are asserted by the slave +// when axi_wready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. +// This marks the acceptance of address and indicates the status of +// write transaction. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_bvalid <= 0; + axi_bresp <= 2'b0; + end + else + begin + if (axi_awready && s_axi_awvalid && ~axi_bvalid && axi_wready && s_axi_wvalid) + begin + // indicates a valid write response is available + axi_bvalid <= 1'b1; + axi_bresp <= 2'b0; // 'OKAY' response + end // work error responses in future + else + begin + if (s_axi_bready && axi_bvalid) + //check if bready is asserted while bvalid is high) + //(there is a possibility that bready is always asserted high) + begin + axi_bvalid <= 1'b0; + end + end + end +end + +// Implement axi_arready generation +// axi_arready is asserted for one s_axi_aclk clock cycle when +// s_axi_arvalid is asserted. axi_awready is +// de-asserted when reset (active low) is asserted. +// The read address is also latched when s_axi_arvalid is +// asserted. axi_araddr is reset to zero on reset assertion. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_arready <= 1'b0; + axi_araddr <= 32'b0; + end + else + begin + if (~axi_arready && s_axi_arvalid) + begin + // indicates that the slave has acceped the valid read address + axi_arready <= 1'b1; + // Read address latching + axi_araddr <= s_axi_araddr; + end + else + begin + axi_arready <= 1'b0; + end + end +end + +// Implement axi_arvalid generation +// axi_rvalid is asserted for one s_axi_aclk clock cycle when both +// s_axi_arvalid and axi_arready are asserted. The slave registers +// data are available on the axi_rdata bus at this instance. The +// assertion of axi_rvalid marks the validity of read data on the +// bus and axi_rresp indicates the status of read transaction.axi_rvalid +// is deasserted on reset (active low). axi_rresp and axi_rdata are +// cleared to zero on reset (active low). +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rvalid <= 0; + axi_rresp <= 0; + end + else + begin + if (axi_arready && s_axi_arvalid && ~axi_rvalid) + begin + // Valid read data is available at the read data bus + axi_rvalid <= 1'b1; + axi_rresp <= 2'b0; // 'OKAY' response + end + else if (axi_rvalid && s_axi_rready) + begin + // Read data is accepted by the master + axi_rvalid <= 1'b0; + end + end +end + +// Implement memory mapped register select and read logic generation +// Slave register read enable is asserted when valid address is available +// and the slave is ready to accept the read address. +assign slv_reg_rden = axi_arready & s_axi_arvalid & ~axi_rvalid; +always @(*) +begin + // Address decoding for reading registers + case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00 : reg_data_out <= slv_reg0; + 6'h01 : reg_data_out <= slv_reg1; + 6'h02 : reg_data_out <= slv_reg2; + 6'h03 : reg_data_out <= slv_reg3; + 6'h04 : reg_data_out <= slv_reg4; + 6'h05 : reg_data_out <= slv_reg5; + 6'h06 : reg_data_out <= slv_reg6; + 6'h07 : reg_data_out <= slv_reg7; + 6'h08 : reg_data_out <= slv_reg8; + 6'h09 : reg_data_out <= slv_reg9; + 6'h0A : reg_data_out <= slv_reg10; + 6'h0B : reg_data_out <= slv_reg11; + 6'h0C : reg_data_out <= slv_reg12; + 6'h0D : reg_data_out <= slv_reg13; + 6'h0E : reg_data_out <= slv_reg14; + 6'h0F : reg_data_out <= slv_reg15; + 6'h10 : reg_data_out <= slv_reg16; + 6'h11 : reg_data_out <= slv_reg17; + 6'h12 : reg_data_out <= slv_reg18; + 6'h13 : reg_data_out <= slv_reg19; + 6'h14 : reg_data_out <= slv_reg20; + 6'h15 : reg_data_out <= slv_reg21; + 6'h16 : reg_data_out <= slv_reg22; + 6'h17 : reg_data_out <= slv_reg23; + 6'h18 : reg_data_out <= slv_reg24; + 6'h19 : reg_data_out <= slv_reg25; + 6'h1A : reg_data_out <= slv_reg26; + 6'h1B : reg_data_out <= slv_reg27; + 6'h1C : reg_data_out <= slv_reg28; + 6'h1D : reg_data_out <= slv_reg29; + 6'h1E : reg_data_out <= slv_reg30; + 6'h1F : reg_data_out <= slv_reg31; + 6'h20 : reg_data_out <= slv_reg32; + 6'h21 : reg_data_out <= slv_reg33; + 6'h22 : reg_data_out <= slv_reg34; + 6'h23 : reg_data_out <= slv_reg35; + 6'h24 : reg_data_out <= slv_reg36; + 6'h25 : reg_data_out <= slv_reg37; + 6'h26 : reg_data_out <= slv_reg38; + 6'h27 : reg_data_out <= slv_reg39; + 6'h28 : reg_data_out <= slv_reg40; + 6'h29 : reg_data_out <= slv_reg41; + 6'h2A : reg_data_out <= slv_reg42; + 6'h2B : reg_data_out <= slv_reg43; + 6'h2C : reg_data_out <= slv_reg44; + 6'h2D : reg_data_out <= slv_reg45; + 6'h2E : reg_data_out <= slv_reg46; + 6'h2F : reg_data_out <= slv_reg47; + 6'h30 : reg_data_out <= slv_reg48; + 6'h31 : reg_data_out <= slv_reg49; + 6'h32 : reg_data_out <= slv_reg50; + 6'h33 : reg_data_out <= slv_reg51; + 6'h34 : reg_data_out <= slv_reg52; + 6'h35 : reg_data_out <= slv_reg53; + 6'h36 : reg_data_out <= slv_reg54; + 6'h37 : reg_data_out <= slv_reg55; + 6'h38 : reg_data_out <= slv_reg56; + 6'h39 : reg_data_out <= slv_reg57; + 6'h3A : reg_data_out <= slv_reg58; + 6'h3B : reg_data_out <= slv_reg59; + 6'h3C : reg_data_out <= slv_reg60; + 6'h3D : reg_data_out <= slv_reg61; + 6'h3E : reg_data_out <= slv_reg62; + 6'h3F : reg_data_out <= slv_reg63; + default : reg_data_out <= 0; + endcase +end + +// Output register or memory read data +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rdata <= 0; + end + else + begin + // When there is a valid read address (s_axi_arvalid) with + // acceptance of read address by the slave (axi_arready), + // output the read dada + if (slv_reg_rden) + begin + axi_rdata <= reg_data_out; // register read data + end + end +end + +assign DDS_BVAL_REG = slv_reg0 [15:0]; +assign DDS_SLOPE_REG = slv_reg1 [15:0]; +assign DDS_STEPS_REG = slv_reg2 [15:0]; +assign DDS_WAIT_REG = slv_reg3 [15:0]; +assign DDS_FREQ_REG = slv_reg4 [15:0]; +assign IIR_C0_REG = slv_reg5 [15:0]; +assign IIR_C1_REG = slv_reg6 [15:0]; +assign IIR_G_REG = slv_reg7 [15:0]; +assign OUTSEL_REG = slv_reg8 [ 1:0]; +assign PUNCT_ID_REG = slv_reg9 [15:0]; +assign ADDR_REG = slv_reg10 [ 7:0]; +assign WE_REG = slv_reg11 [ 0]; + +endmodule diff --git a/firmware/ip/axis_kidsim_v3/src/axis_kidsim_v3.sv b/firmware/ip/axis_kidsim_v3/src/axis_kidsim_v3.sv new file mode 100644 index 0000000..45c779e --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/axis_kidsim_v3.sv @@ -0,0 +1,192 @@ +module axis_kidsim_v3 + #( + // Number of lanes. + parameter L = 8 + ) + ( + // Modulation trigger. + input wire [L-1:0] trigger , + + // AXI Slave I/F for configuration. + input wire s_axi_aclk , + input wire s_axi_aresetn , + + input wire [7:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + + input wire [31:0] s_axi_wdata , + input wire [3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + + output wire [1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + + input wire [7:0] s_axi_araddr , + input wire [2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + + output wire [31:0] s_axi_rdata , + output wire [1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , + + // Reset and clock for axis_*. + input wire aresetn , + input wire aclk , + + // s_axis_* for input. + input wire s_axis_tvalid , + input wire [32*L-1:0] s_axis_tdata , + input wire s_axis_tlast , + + // m_axis_* for output. + output wire m_axis_tvalid , + output wire [32*L-1:0] m_axis_tdata , + output wire m_axis_tlast + ); + +/********************/ +/* Internal signals */ +/********************/ + +// WE vector. +wire [L-1:0] enable_v ; +wire [L-1:0] WE_REG_v ; + +// Data input vector. +wire [31:0] din_v [L] ; + +// Data output vector. +wire [L-1:0] dout_valid ; +wire [31:0] dout_v [L] ; +wire [L-1:0] dout_last ; + +// Registers. +wire [15:0] DDS_BVAL_REG ; +wire [15:0] DDS_SLOPE_REG ; +wire [15:0] DDS_STEPS_REG ; +wire [15:0] DDS_WAIT_REG ; +wire [15:0] DDS_FREQ_REG ; +wire [15:0] IIR_C0_REG ; +wire [15:0] IIR_C1_REG ; +wire [15:0] IIR_G_REG ; +wire [ 1:0] OUTSEL_REG ; +wire [15:0] PUNCT_ID_REG ; +wire [ 7:0] ADDR_REG ; +wire WE_REG ; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + + // Write Address Channel. + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_awready (s_axi_awready ), + + // Write Data Channel. + .s_axi_wdata (s_axi_wdata ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + .s_axi_wready (s_axi_wready ), + + // Write Response Channel. + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_bready (s_axi_bready ), + + // Read Address Channel. + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_arready (s_axi_arready ), + + // Read Data Channel. + .s_axi_rdata (s_axi_rdata ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_rready (s_axi_rready ), + + // Registers. + .DDS_BVAL_REG (DDS_BVAL_REG ), + .DDS_SLOPE_REG (DDS_SLOPE_REG ), + .DDS_STEPS_REG (DDS_STEPS_REG ), + .DDS_WAIT_REG (DDS_WAIT_REG ), + .DDS_FREQ_REG (DDS_FREQ_REG ), + .IIR_C0_REG (IIR_C0_REG ), + .IIR_C1_REG (IIR_C1_REG ), + .IIR_G_REG (IIR_G_REG ), + .OUTSEL_REG (OUTSEL_REG ), + .PUNCT_ID_REG (PUNCT_ID_REG ), + .ADDR_REG (ADDR_REG ), + .WE_REG (WE_REG ) + ); + +genvar i; +generate + for (i=0; i + + xilinx.com + xci + unknown + 1.0 + + + dds_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + 16 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 8 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 0 + 0 + 1 + 0 + 32 + 1 + 0 + zynquplus + Full_Range + 1 + dds_0 + Not_Required + 256 + Minimal + 3906.25 + Coregen + false + false + false + false + 8 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + false + Phase_Dithering + Twos_Complement + Auto + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 16 + Streaming + false + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 22 + TRUE + ../../../../../zcu216/qick_training/top/top.tmp/axis_kidsim_v3_v1_0_project/axis_kidsim_v3_v1_0_project.gen/sources_1/ip/dds_0 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_kidsim_v3/src/dds/dds_ctrl.v b/firmware/ip/axis_kidsim_v3/src/dds/dds_ctrl.v new file mode 100644 index 0000000..01c2bac --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/dds/dds_ctrl.v @@ -0,0 +1,125 @@ +/* + * DDS Control input format: + * + * |----------|---------| + * | 31 .. 16 | 15 .. 0 | + * |----------|---------| + * | phase | pinc | + * |----------|---------| + * + */ +module dds_ctrl + ( + // Reset and clock. + input wire rstn , + input wire clk , + + // Modulation trigger. + input wire trigger , + + // Data input. + input wire din_valid , + + // DDS control output. + output wire dout_valid , + output wire [31:0] dout , + + // Registers. + input wire [15:0] BVAL_REG , + input wire [15:0] SLOPE_REG , + input wire [15:0] STEPS_REG , + input wire [15:0] WAIT_REG , + input wire [15:0] FREQ_REG + ); + +/*************/ +/* Internals */ +/*************/ + +// Modulation output. +wire [15:0] mod_out ; +reg [15:0] mod_out_r1 ; + +// Frequency addition. +wire [15:0] freq ; +reg [15:0] freq_r1 ; + +// Valid pipeline. +reg valid_r1 ; +reg valid_r2 ; + +// Registers. +reg [15:0] FREQ_REG_r ; + +/****************/ +/* Architecture */ +/****************/ + +// Modulation control. +// Latency : 0. +mod_ctrl + #( + .B(16) + ) + mod_ctrl_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Trigger. + .trigger (trigger ), + + // Enable. + .en (din_valid ), + + // Modulation Output. + .y (mod_out ), + + // Registers. + .B_REG (BVAL_REG ), + .M_REG (SLOPE_REG ), + .N_REG (STEPS_REG ), + .W_REG (WAIT_REG ) + ); + +// Frequency addition. +assign freq = FREQ_REG_r - mod_out_r1; + +always @(posedge clk) begin + if (rstn == 1'b0) begin + // Modulation output. + mod_out_r1 <= 0; + + // Frequency addition. + freq_r1 <= 0; + + // Valid pipeline. + valid_r1 <= 0; + valid_r2 <= 0; + + // Registers. + FREQ_REG_r <= 0; + end + else begin + // Modulation output. + mod_out_r1 <= mod_out; + + // Frequency addition. + freq_r1 <= freq; + + // Valid pipeline. + valid_r1 <= din_valid; + valid_r2 <= valid_r1; + + // Registers. + FREQ_REG_r <= FREQ_REG; + end +end + +// Assign outputs. +assign dout = {{16{1'b0}},freq_r1}; +assign dout_valid = valid_r2; + +endmodule + diff --git a/firmware/ip/axis_kidsim_v3/src/dds/dds_top.v b/firmware/ip/axis_kidsim_v3/src/dds/dds_top.v new file mode 100644 index 0000000..9e3d453 --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/dds/dds_top.v @@ -0,0 +1,95 @@ +/* + * DDS Control input format: + * + * |----------|---------| + * | 31 .. 16 | 15 .. 0 | + * |----------|---------| + * | phase | pinc | + * |----------|---------| + * + */ +module dds_top + ( + // Reset and clock. + input wire rstn , + input wire clk , + + // Modulation trigger. + input wire trigger , + + // Data input. + input wire din_valid , + + // Data output. + output wire dout_valid , + output wire [31:0] dout , + + // Registers. + input wire [15:0] BVAL_REG , + input wire [15:0] SLOPE_REG , + input wire [15:0] STEPS_REG , + input wire [15:0] WAIT_REG , + input wire [15:0] FREQ_REG + ); + +/*************/ +/* Internals */ +/*************/ +// DDS control outputs. +wire dds_ctrl_valid; +wire [31:0] dds_ctrl_dout; + +// DDS outputs. +wire dds_valid; +wire [31:0] dds_dout; + +/****************/ +/* Architecture */ +/****************/ + +// DDS control block. +// Latency = 2. +dds_ctrl + dds_ctrl_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Modulation trigger. + .trigger (trigger ), + + // Data input. + .din_valid (din_valid ), + + // DDS control output. + .dout_valid (dds_ctrl_valid ), + .dout (dds_ctrl_dout ), + + // Registers. + .BVAL_REG (BVAL_REG ), + .SLOPE_REG (SLOPE_REG ), + .STEPS_REG (STEPS_REG ), + .WAIT_REG (WAIT_REG ), + .FREQ_REG (FREQ_REG ) + ); + +// DDS IP. +// Latency = 8. +// The block will generate e^jw. +dds_0 + dds_i + ( + .aclk (clk ), + .s_axis_phase_tvalid (dds_ctrl_valid ), + .s_axis_phase_tdata (dds_ctrl_dout ), + .m_axis_data_tvalid (dds_valid ), + .m_axis_data_tdata (dds_dout ) + ); + +// Assign outputs. +assign dout_valid = dds_valid; +assign dout = dds_dout; + +endmodule + diff --git a/firmware/ip/axis_kidsim_v3/src/dds/mod_ctrl.sv b/firmware/ip/axis_kidsim_v3/src/dds/mod_ctrl.sv new file mode 100644 index 0000000..2bee962 --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/dds/mod_ctrl.sv @@ -0,0 +1,218 @@ +// This block implements a linear function. When the trigger +// is received, the block starts creating a function like: +// +// y = -m*n + b +// +// where M_REG is the slope and B_REG the starting value. The +// number of n steps is given by N_REG. One step is taken every +// W_REG cycles. +// Once the function is completed, the output goes to 0. +module mod_ctrl + #( + parameter B = 8 + ) + ( + // Reset and clock. + input wire rstn , + input wire clk , + + // Trigger. + input wire trigger , + + // Enable. + input wire en , + + // Modulation Output. + output wire [B-1:0] y , + + // Registers. + input wire [B-1:0] B_REG , + input wire [B-1:0] M_REG , + input wire [B-1:0] N_REG , + input wire [B-1:0] W_REG + ); + +/*************/ +/* Internals */ +/*************/ + +// States. +typedef enum { INIT_ST , + CNT_ST , + WAIT_ST , + END_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +reg init_state ; +reg cnt_state ; +reg wait_state ; +reg end_state ; + +// Re-synced signals. +wire trigger_resync ; + +// Registers. +reg signed [B-1:0] B_REG_r ; +reg signed [B-1:0] M_REG_r ; +reg [B-1:0] N_REG_r ; +reg [B-1:0] W_REG_r ; + +// Counter. +reg [B-1:0] cnt ; + +// Wait counter. +reg [B-1:0] wcnt ; + +// B. +wire signed [B-1:0] bs ; +reg [B-1:0] bs_r ; + +// M. +wire signed [B-1:0] ms ; +reg signed [B-1:0] ms_r ; + +/****************/ +/* Architecture */ +/****************/ + +// trigger_resync. +synchronizer_n trigger_resync_i + ( + .rstn (rstn ), + .clk (clk ), + .data_in (trigger ), + .data_out (trigger_resync ) + ); + +// B. +assign bs = B_REG_r - ms_r; + +// M. +assign ms = M_REG_r + ms_r; + +// Registers. +always @(posedge clk) begin + if (rstn == 1'b0) begin + // State register. + state <= INIT_ST; + + // Registers. + B_REG_r <= 0; + M_REG_r <= 0; + N_REG_r <= 0; + W_REG_r <= 0; + + // Counter. + cnt <= 0; + + // Wait counter. + wcnt <= 0; + + // B. + bs_r <= 0; + + // M. + ms_r <= 0; + end + else begin + // State register. + case (state) + INIT_ST: + if (trigger_resync == 1'b1) + state <= CNT_ST; + + CNT_ST: + if ( en == 1'b1) begin + if (cnt == N_REG_r) + state <= END_ST; + else if (W_REG_r != '0) + state <= WAIT_ST; + end + + WAIT_ST: + if ( en == 1'b1 ) begin + if (wcnt == W_REG_r-1) + state <= CNT_ST; + end + + END_ST: + if (trigger_resync == 1'b0) + state <= INIT_ST; + endcase + + // Registers. + if ( init_state == 1'b1) begin + B_REG_r <= B_REG ; + M_REG_r <= M_REG ; + N_REG_r <= N_REG ; + W_REG_r <= W_REG ; + end + + // Counter. + if ( init_state == 1'b1 ) begin + cnt <= 0; + end + else if ( cnt_state == 1'b1 ) begin + if (en == 1'b1) begin + cnt <= cnt + 1; + end + end + + // Wait counter. + if ( wait_state == 1'b1 ) begin + if (en == 1'b1) begin + wcnt <= wcnt + 1; + end + end + else begin + wcnt <= 0; + end + + if ( init_state == 1'b1 ) begin + // B. + bs_r <= 0; + + // M. + ms_r <= 0; + end + else if ( (cnt_state == 1'b1) && (en == 1'b1) ) begin + // B. + bs_r <= bs; + + // M. + ms_r <= ms; + end + end +end + +// FSM outputs. +always_comb begin + // Default. + init_state = 0; + cnt_state = 0; + wait_state = 0; + end_state = 0; + + case (state) + INIT_ST: + init_state = 1'b1; + + CNT_ST: + cnt_state = 1'b1; + + WAIT_ST: + wait_state = 1'b1; + + END_ST: + end_state = 1'b1; + endcase +end + +// Assign outputs. +assign y = (init_state == 1'b1 || end_state == 1'b1)? 0 : bs_r; + +endmodule + diff --git a/firmware/ip/axis_kidsim_v3/src/dds/tb/tb_dds_top.sv b/firmware/ip/axis_kidsim_v3/src/dds/tb/tb_dds_top.sv new file mode 100644 index 0000000..040e3bb --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/dds/tb/tb_dds_top.sv @@ -0,0 +1,120 @@ +module tb; + +// Reset and clock. +reg rstn ; +reg clk ; + +// Modulation trigger. +reg trigger ; + +// Data input. +reg din_valid ; + +// Data output. +wire[31:0] dout ; + +// Registers. +reg [15:0] BVAL_REG ; +reg [15:0] SLOPE_REG ; +reg [15:0] STEPS_REG ; +reg [15:0] WAIT_REG ; +reg [15:0] FREQ_REG ; + +// DUT. +dds_top + DUT + ( + // Reset and clock. + .rstn , + .clk , + + // Modulation trigger. + .trigger , + + // Data input. + .din_valid , + + // Data output. + .dout , + + // Registers. + .BVAL_REG , + .SLOPE_REG , + .STEPS_REG , + .WAIT_REG , + .FREQ_REG + ); + +// Main TB. +initial begin + real b, m, n; + + rstn <= 0; + trigger <= 0; + BVAL_REG <= 0; + SLOPE_REG <= 0; + STEPS_REG <= 0; + WAIT_REG <= 0; + FREQ_REG <= 0; + @(posedge clk); + rstn <= 1; + + #300; + + // Configure block. + b = 4000; + m = 10; + n = b/m; + @(posedge clk); + BVAL_REG <= integer'(b); + SLOPE_REG <= integer'(m); + STEPS_REG <= integer'(n); + WAIT_REG <= 50; + FREQ_REG <= freq_calc(100, 10.1); + + #3000; + + for (int i=0; i<10; i=i+1) begin + @(posedge clk); + trigger <= 1; + @(posedge clk); + trigger <= 0; + #1000000; + end +end + +// din_valid. +initial begin + din_valid <= 1; + + #4000; + + @(posedge clk); + din_valid <= 0; + + #400; + + @(posedge clk); + din_valid <= 1; +end + +always begin + clk <= 0; + #5; + clk <= 1; + #5; +end + +// Function to compute frequency register. +function [15:0] freq_calc; + input real fclk; + input real f; + + // All input frequencies are in MHz. + real temp; + temp = f/fclk*2**16; + freq_calc = int'(temp); +endfunction + +endmodule + diff --git a/firmware/ip/axis_kidsim_v3/src/dds/tb/tb_mod_ctrl.sv b/firmware/ip/axis_kidsim_v3/src/dds/tb/tb_mod_ctrl.sv new file mode 100644 index 0000000..1cd4af8 --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/dds/tb/tb_mod_ctrl.sv @@ -0,0 +1,90 @@ +module tb; + +parameter B = 8; + +// Reset and clock. +reg rstn ; +reg clk ; + +// Trigger. +reg trigger ; + +// Modulation Output. +wire [B-1:0] y ; + +// Registers. + reg [B-1:0] B_REG ; + reg [B-1:0] M_REG ; + reg [B-1:0] N_REG ; + +// DUT. +mod_ctrl + #( + .B(B) + ) + DUT + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Trigger. + .trigger (trigger ), + + // Modulation Output. + .y (y ), + + // Registers. + .B_REG , + .M_REG , + .N_REG + ); + +// Main TB. +initial begin + real b, m, n; + + rstn <= 0; + trigger <= 0; + B_REG <= 0; + M_REG <= 0; + N_REG <= 0; + @(posedge clk); + rstn <= 1; + + #300; + + // Configure block. + b = 77; + m = 3; + n = b/m; + @(posedge clk); + B_REG <= integer'(b); + M_REG <= integer'(m); + N_REG <= integer'(n); + + #300; + + for (int i=0; i<10; i=i+1) begin + @(posedge clk); + trigger <= 1; + #1000; + @(posedge clk); + trigger <= 0; + #1000; + end + + + + +end + +always begin + clk <= 0; + #5; + clk <= 1; + #5; +end + +endmodule + diff --git a/firmware/ip/axis_kidsim_v3/src/iir/iir.sv b/firmware/ip/axis_kidsim_v3/src/iir/iir.sv new file mode 100644 index 0000000..dcb5a1c --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/iir/iir.sv @@ -0,0 +1,160 @@ +module iir + #( + parameter B = 16, + parameter BA = 20 + ) + ( + // Reset and clock. + input wire rstn , + input wire clk , + + // Input data. + input wire din_valid , + input wire [B-1:0] din , + + // Output data. + output wire dout_valid , + output wire [B-1:0] dout , + + // Registers. + input wire [B-1:0] C0_REG , + input wire [B-1:0] C1_REG , + input wire [B-1:0] G_REG + ); + +/*************/ +/* Internals */ +/*************/ +// Number of bits of product. +localparam BP = BA + B; + +// Input registers. +reg [B-1:0] din_r1 ; +reg [B-1:0] C0_REG_r1 ; +reg [B-1:0] C1_REG_r1 ; +reg [B-1:0] G_REG_r1 ; + +// Valid pipeline. +reg valid_r1 ; +reg valid_r2 ; +reg valid_r3 ; +reg valid_r4 ; + +// Sign-extended input. +wire signed [BA-1:0] xn ; + +// Feed-forward filter. +reg signed [BA-1:0] xn_r1 ; +wire signed [BP-1:0] p0 ; +wire signed [BA-1:0] p0_q ; +wire signed [BA-1:0] y0 ; +reg signed [BA-1:0] y0_r1 ; + +// Feed-back filter. +wire signed [BP-1:0] p1 ; +wire signed [BA-1:0] p1_q ; +wire signed [BA-1:0] y1 ; +reg signed [BA-1:0] y1_r1a ; +reg signed [BA-1:0] y1_r1b ; + +// Product with gain. +wire signed [BP-1:0] yg ; +wire signed [B-1:0] yg_q ; +reg [B-1:0] yg_q_r1 ; + +// Coefficients. +wire signed [B-1:0] c0 ; +wire signed [B-1:0] c1 ; + +// Gain. +wire signed [B-1:0] g ; + +/****************/ +/* Architecture */ +/****************/ + +// Sign-extended input. +assign xn = {{(BA-B){din_r1[B-1]}},din_r1}; + +// Feed-forward filter. +assign p0 = c0*xn_r1; +assign p0_q = p0[BP-2 -: BA]; +assign y0 = xn - p0_q; + +// Feed-back filter. +assign p1 = c1*y1_r1a; +assign p1_q = p1[BP-2 -: BA]; +assign y1 = y0_r1 + p1_q; + +// Product with gain. +assign yg = g*y1_r1b; +assign yg_q = yg[BP-2-(BA-B) -: B]; + +// Coefficients. +assign c0 = C0_REG_r1; +assign c1 = C1_REG_r1; + +// Gain. +assign g = G_REG_r1; + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // Input registers. + din_r1 <= 0; + C0_REG_r1 <= 0; + C1_REG_r1 <= 0; + G_REG_r1 <= 0; + + // Valid pipeline. + valid_r1 <= 0; + valid_r2 <= 0; + valid_r3 <= 0; + valid_r4 <= 0; + + // Feed-forward filter. + xn_r1 <= 0; + y0_r1 <= 0; + + // Feed-back filter. + y1_r1a <= 0; + y1_r1b <= 0; + + // Product with gain. + yg_q_r1 <= 0; + end + else begin + // Input registers. + din_r1 <= din; + C0_REG_r1 <= C0_REG; + C1_REG_r1 <= C1_REG; + G_REG_r1 <= G_REG; + + // Valid pipeline. + valid_r1 <= din_valid; + valid_r2 <= valid_r1; + valid_r3 <= valid_r2; + valid_r4 <= valid_r3; + + // Feed-forward filter. + if ( valid_r1 == 1'b1 ) + xn_r1 <= xn; + y0_r1 <= y0; + + // Feed-back filter. + if ( valid_r2 == 1'b1 ) + y1_r1a <= y1; + y1_r1b <= y1; + + // Product with gain. + yg_q_r1 <= yg_q; + end +end + + +// Assign outputs. +assign dout = yg_q_r1; +assign dout_valid = valid_r4; + +endmodule + diff --git a/firmware/ip/axis_kidsim_v3/src/iir/iir_iq.sv b/firmware/ip/axis_kidsim_v3/src/iir/iir_iq.sv new file mode 100644 index 0000000..f98e4a5 --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/iir/iir_iq.sv @@ -0,0 +1,95 @@ +module iir_iq + #( + parameter B = 16, + parameter BA = 20 + ) + ( + // Reset and clock. + input wire rstn , + input wire clk , + + // Input data. + input wire din_valid , + input wire [2*B-1:0] din , + + // Output data. + output wire dout_valid , + output wire [2*B-1:0] dout , + + // Registers. + input wire [B-1:0] C0_REG , + input wire [B-1:0] C1_REG , + input wire [B-1:0] G_REG + ); + +/*************/ +/* Internals */ +/*************/ +wire [B-1:0] din_real; +wire [B-1:0] din_imag; +wire [B-1:0] dout_real; +wire [B-1:0] dout_imag; + +/****************/ +/* Architecture */ +/****************/ +assign din_real = din[0 +: B]; +assign din_imag = din[B +: B]; + +// IIR for real part. +iir + #( + .B (B ), + .BA (BA ) + ) + iir_real_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Input data. + .din_valid (din_valid ), + .din (din_real ), + + // Output data. + .dout_valid (dout_valid ), + .dout (dout_real ), + + // Registers. + .C0_REG (C0_REG ), + .C1_REG (C1_REG ), + .G_REG (G_REG ) + ); + +// IIR for imaginary part. +iir + #( + .B (B ), + .BA (BA ) + ) + iir_imag_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Input data. + .din_valid (din_valid ), + .din (din_imag ), + + // Output data. + .dout_valid ( ), + .dout (dout_imag ), + + // Registers. + .C0_REG (C0_REG ), + .C1_REG (C1_REG ), + .G_REG (G_REG ) + ); + +// Assign outputs. +assign dout = {dout_imag,dout_real}; + +endmodule + diff --git a/firmware/ip/axis_kidsim_v3/src/iir/tb/tb_iir.sv b/firmware/ip/axis_kidsim_v3/src/iir/tb/tb_iir.sv new file mode 100644 index 0000000..04a51ea --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/iir/tb/tb_iir.sv @@ -0,0 +1,131 @@ +module tb; + +parameter B = 8; +parameter BA = B + 4; + +// Reset and clock. +reg rstn ; +reg clk ; + +// Input data. +reg din_valid ; +wire [2*B-1:0] din ; + +// Output data. +wire dout_valid ; +wire [2*B-1:0] dout ; + +// Registers. +reg [B-1:0] C0_REG ; +reg [B-1:0] C1_REG ; +reg [B-1:0] G_REG ; + +// Variables. +real c0, c1, g, a; + +// Debug. +reg [B-1:0] din_real; +reg [B-1:0] din_imag; +wire [B-1:0] dout_real; +wire [B-1:0] dout_imag; + +// Test bench control. +reg tb_data = 0; + +assign din = {din_imag, din_real}; +assign dout_real = dout[0 +: B]; +assign dout_imag = dout[B +: B]; + +// IIR +iir_iq + #( + .B (B ), + .BA (BA ) + ) + DUT + ( + // Reset and clock. + .rstn , + .clk , + + // Input data. + .din_valid , + .din , + + // Output data. + .dout_valid , + .dout , + + // Registers. + .C0_REG , + .C1_REG , + .G_REG + ); + +// Main TB. +initial begin + rstn <= 0; + + #300; + + @(posedge clk); + rstn <= 1; + + #200; + + @(posedge clk); + tb_data <= 1; + +end + +// Initialize memory contents. +initial begin + int n; + + // Data. + din_real <= 0; + din_imag <= 0; + din_valid <= 1; + + c0 = 0; + c1 = 0; + g = 0; + a = 0.9; + + // Set resonator. + c0 = 0.95; + c1 = 0.8; + g = (1+c1)/(1+c0); + + // Set registers. + C0_REG = c0*(2**(B-1)); + C1_REG = c1*(2**(B-1)); + G_REG = g*(2**(B-1)); + + wait(tb_data); + + // Load memory with frequencies. + while (1) begin + for (int i=0; i<100; i=i+1) begin + @(posedge clk); + din_real <= a*(2**(B-1))*$cos(2*3.14*0.018*n); + din_valid <= 1; + n = n + 1; + end + for (int i=0; i<10; i=i+1) begin + @(posedge clk); + din_real <= $random; + din_valid <= 0; + end + end +end + +always begin + clk <= 0; + #5; + clk <= 1; + #5; +end + +endmodule + diff --git a/firmware/ip/axis_kidsim_v3/src/kidsim.sv b/firmware/ip/axis_kidsim_v3/src/kidsim.sv new file mode 100644 index 0000000..a3d1132 --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/kidsim.sv @@ -0,0 +1,263 @@ +module kidsim + ( + // Reset and clock. + input wire rstn , + input wire clk , + + // Modulation trigger. + input wire trigger , + + // Input data. + input wire [31:0] din , + input wire din_valid , + + // Output data. + output wire [31:0] dout , + output wire dout_valid , + + // Registers. + input wire [15:0] DDS_BVAL_REG , + input wire [15:0] DDS_SLOPE_REG , + input wire [15:0] DDS_STEPS_REG , + input wire [15:0] DDS_WAIT_REG , + input wire [15:0] DDS_FREQ_REG , + input wire [15:0] IIR_C0_REG , + input wire [15:0] IIR_C1_REG , + input wire [15:0] IIR_G_REG , + input wire [ 1:0] OUTSEL_REG + ); + +/*************/ +/* Internals */ +/*************/ +// Data input latency. +wire [31:0] din_la ; +wire [31:0] din_la_mux ; + +// DDS output. +wire dds_valid ; +wire [31:0] dds_dout ; +wire [31:0] dds_dout_la ; +wire [31:0] dds_dout_la_mux ; + + +// Product 0 output. +wire prod0_valid ; +wire [31:0] prod0_dout ; + +// IIR output. +wire iir_valid ; +wire [31:0] iir_dout ; + +// Product 1 output. +wire prod1_valid ; +wire [31:0] prod1_dout ; + +// Muxed output. +wire [31:0] dout_mux ; + +/****************/ +/* Architecture */ +/****************/ + +// DDS Block. +// Latency = 2. +dds_top + dds_top_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Modulation trigger. + .trigger (trigger ), + + // Data input. + .din_valid (din_valid ), + + // Data output. + .dout_valid (dds_valid ), + .dout (dds_dout ), + + // Registers. + .BVAL_REG (DDS_BVAL_REG ), + .SLOPE_REG (DDS_SLOPE_REG ), + .STEPS_REG (DDS_STEPS_REG ), + .WAIT_REG (DDS_WAIT_REG ), + .FREQ_REG (DDS_FREQ_REG ) + ); + +// Product by e^-jw. +// Latency = 4. +prod + #( + .CONJA (0 ), + .CONJB (1 ), + .B (16 ) + ) + prod0_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Input data. + .din_valid (dds_valid ), + .dina (din_la ), + .dinb (dds_dout ), + + // Output data. + .dout_valid (prod0_valid ), + .dout (prod0_dout ) + ); + +// IIR. +// Latency = 4. +iir_iq + #( + .B (16 ), + .BA (20 ) + ) + iir_iq_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Input data. + .din_valid (prod0_valid ), + .din (prod0_dout ), + + // Output data. + .dout_valid (iir_valid ), + .dout (iir_dout ), + + // Registers. + .C0_REG (IIR_C0_REG ), + .C1_REG (IIR_C1_REG ), + .G_REG (IIR_G_REG ) + ); + +// Product by e^jw. +// Latency = 4. +prod + #( + .CONJA (0 ), + .CONJB (0 ), + .B (16 ) + ) + prod1_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Input data. + .din_valid (iir_valid ), + .dina (iir_dout ), + .dinb (dds_dout_la ), + + // Output data. + .dout_valid (prod1_valid ), + .dout (prod1_dout ) + ); + +// din latency. +latency_reg + #( + // Latency. + .N(2), + + // Data width. + .B(32) + ) + latency_reg_din_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Data input. + .din (din ), + + // Data output. + .dout (din_la ) + ); + +// din latency (mux output). +latency_reg + #( + // Latency. + .N(12), + + // Data width. + .B(32) + ) + latency_reg_din_mux_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Data input. + .din (din_la ), + + // Data output. + .dout (din_la_mux ) + ); + +// dds_dout latency. +latency_reg + #( + // Latency. + .N(8), + + // Data width. + .B(32) + ) + latency_reg_dds_dout_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Data input. + .din (dds_dout ), + + // Data output. + .dout (dds_dout_la ) + ); + +// dds_dout latency (mux output). +latency_reg + #( + // Latency. + .N(4), + + // Data width. + .B(32) + ) + latency_reg_dds_dout_mux_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Data input. + .din (dds_dout_la ), + + // Data output. + .dout (dds_dout_la_mux ) + ); + +// Muxed output. +assign dout_mux = (OUTSEL_REG == 0)? prod1_dout : + (OUTSEL_REG == 1)? dds_dout_la_mux : + (OUTSEL_REG == 2)? din_la_mux : + 32'h0000_0000; + +// Assign outputs. +assign dout = dout_mux; +assign dout_valid = prod1_valid; + +endmodule diff --git a/firmware/ip/axis_kidsim_v3/src/kidsim_top.sv b/firmware/ip/axis_kidsim_v3/src/kidsim_top.sv new file mode 100644 index 0000000..765f434 --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/kidsim_top.sv @@ -0,0 +1,269 @@ +module kidsim_top + ( + // Reset and clock. + input wire rstn , + input wire clk , + + // Modulation trigger. + input wire trigger , + + // Input data. + input wire din_valid , + input wire [31:0] din , + input wire din_last , + + // Output data. + output wire dout_valid , + output wire [31:0] dout , + output wire dout_last , + + // Registers. + input wire [15:0] DDS_BVAL_REG , + input wire [15:0] DDS_SLOPE_REG , + input wire [15:0] DDS_STEPS_REG , + input wire [15:0] DDS_WAIT_REG , + input wire [15:0] DDS_FREQ_REG , + input wire [15:0] IIR_C0_REG , + input wire [15:0] IIR_C1_REG , + input wire [15:0] IIR_G_REG , + input wire [ 1:0] OUTSEL_REG , + input wire [15:0] PUNCT_ID_REG , + input wire WE_REG + ); + +/*************/ +/* Internals */ +/*************/ + +// din latency. +wire [31:0] din_la0 ; +wire [31:0] din_la1 ; + +// Punct. +wire punct_valid ; +wire punct_last ; +wire punct_en ; + +// punct_valid latency. +wire punct_valid_la ; + +// punct_last latency. +wire punct_last_la ; + +// Kidsim. +wire kidsim_din_valid ; +wire [31:0] kidsim_dout ; +wire kidsim_dout_valid ; + +// Muxed output. +wire [31:0] dout_mux ; + +// Registers. +reg [15:0] DDS_BVAL_REG_r ; +reg [15:0] DDS_SLOPE_REG_r ; +reg [15:0] DDS_STEPS_REG_r ; +reg [15:0] DDS_WAIT_REG_r ; +reg [15:0] DDS_FREQ_REG_r ; +reg [15:0] IIR_C0_REG_r ; +reg [15:0] IIR_C1_REG_r ; +reg [15:0] IIR_G_REG_r ; +reg [ 1:0] OUTSEL_REG_r ; +reg [15:0] PUNCT_ID_REG_r ; +reg WE_REG_resync ; + + +/****************/ +/* Architecture */ +/****************/ + +// WE_REG_resync. +synchronizer_n WE_REG_resync_i + ( + .rstn (rstn ), + .clk (clk ), + .data_in (WE_REG ), + .data_out (WE_REG_resync ) + ); + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + DDS_BVAL_REG_r <= 0; + DDS_SLOPE_REG_r <= 0; + DDS_STEPS_REG_r <= 0; + DDS_WAIT_REG_r <= 0; + DDS_FREQ_REG_r <= 0; + IIR_C0_REG_r <= 0; + IIR_C1_REG_r <= 0; + IIR_G_REG_r <= 0; + OUTSEL_REG_r <= 2; // By-pass by default. + PUNCT_ID_REG_r <= 0; + end + else begin + if ( WE_REG_resync == 1'b1) begin + DDS_BVAL_REG_r <= DDS_BVAL_REG ; + DDS_SLOPE_REG_r <= DDS_SLOPE_REG; + DDS_STEPS_REG_r <= DDS_STEPS_REG; + DDS_WAIT_REG_r <= DDS_WAIT_REG ; + DDS_FREQ_REG_r <= DDS_FREQ_REG ; + IIR_C0_REG_r <= IIR_C0_REG ; + IIR_C1_REG_r <= IIR_C1_REG ; + IIR_G_REG_r <= IIR_G_REG ; + OUTSEL_REG_r <= OUTSEL_REG ; + PUNCT_ID_REG_r <= PUNCT_ID_REG ; + end + end +end + +// Puncturing block. +// Latency : 2. +punct + punct_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Input data. + .din_valid (din_valid ), + .din_last (din_last ), + + // Output data. + .dout_valid (punct_valid ), + .dout_last (punct_last ), + .dout_en (punct_en ), + + // Registers. + .ID_REG (PUNCT_ID_REG_r ) + ); + +assign kidsim_din_valid = punct_valid & punct_en; + +// KID Simulator. +// Latency : 14. +kidsim + kidsim_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Modulation trigger. + .trigger (trigger ), + + // Input data. + .din (din_la0 ), + .din_valid (kidsim_din_valid ), + + // Output data. + .dout (kidsim_dout ), + .dout_valid (kidsim_dout_valid ), + + // Registers. + .DDS_BVAL_REG (DDS_BVAL_REG_r ), + .DDS_SLOPE_REG (DDS_SLOPE_REG_r ), + .DDS_STEPS_REG (DDS_STEPS_REG_r ), + .DDS_WAIT_REG (DDS_WAIT_REG_r ), + .DDS_FREQ_REG (DDS_FREQ_REG_r ), + .IIR_C0_REG (IIR_C0_REG_r ), + .IIR_C1_REG (IIR_C1_REG_r ), + .IIR_G_REG (IIR_G_REG_r ), + .OUTSEL_REG (OUTSEL_REG_r ) + ); + +// din latency. +latency_reg + #( + // Latency. + .N(2), + + // Data width. + .B(32) + ) + latency_reg_din_0i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Data input. + .din (din ), + + // Data output. + .dout (din_la0 ) + ); + +latency_reg + #( + // Latency. + .N(14), + + // Data width. + .B(32) + ) + latency_reg_din_1i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Data input. + .din (din_la0 ), + + // Data output. + .dout (din_la1 ) + ); + +// punct_valid latency. +latency_reg + #( + // Latency. + .N(14), + + // Data width. + .B(1) + ) + latency_reg_punct_valid_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Data input. + .din (punct_valid ), + + // Data output. + .dout (punct_valid_la ) + ); + +// punct_last latency. +latency_reg + #( + // Latency. + .N(14), + + // Data width. + .B(1) + ) + latency_reg_punct_last_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Data input. + .din (punct_last ), + + // Data output. + .dout (punct_last_la ) + ); + +// Muxed output. +assign dout_mux = (kidsim_dout_valid == 1'b1)? kidsim_dout : din_la1; + +// Assign outputs. +assign dout_valid = punct_valid_la; +assign dout = dout_mux; +assign dout_last = punct_last_la; + +endmodule diff --git a/firmware/ip/axis_kidsim_v3/src/mems/latency_reg.v b/firmware/ip/axis_kidsim_v3/src/mems/latency_reg.v new file mode 100644 index 0000000..0db831a --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/mems/latency_reg.v @@ -0,0 +1,54 @@ +module latency_reg + #( + // Latency. + parameter N = 2, + + // Data width. + parameter B = 8 + ) + ( + // Reset and clock. + input wire rstn , + input wire clk , + + // Data input. + input wire [B-1:0] din , + + // Data output. + output wire [B-1:0] dout + ); + + +// Shift register. +reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=0; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_kidsim_v3/src/prod.sv b/firmware/ip/axis_kidsim_v3/src/prod.sv new file mode 100644 index 0000000..7de7b32 --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/prod.sv @@ -0,0 +1,141 @@ +module prod + #( + parameter CONJA = 0 , + parameter CONJB = 0 , + parameter B = 16 + ) + ( + // Reset and clock. + input wire rstn , + input wire clk , + + // Input data. + input wire din_valid , + input wire [2*B-1:0] dina , + input wire [2*B-1:0] dinb , + + // Output data. + output wire dout_valid , + output wire [2*B-1:0] dout + ); + +/*************/ +/* Internals */ +/*************/ +// Valid pipeline. +reg valid_r1; +reg valid_r2; +reg valid_r3; +reg valid_r4; + +// Input registers. +reg [2*B-1:0] dina_r; +reg [2*B-1:0] dinb_r; + +// Partial products. +wire signed [B-1:0] dina_real; +wire signed [B-1:0] dina_imag; +wire signed [B-1:0] dinb_real; +wire signed [B-1:0] dinb_imag; +wire signed [2*B-1:0] prod_real_a; +wire signed [2*B-1:0] prod_real_b; +wire signed [2*B-1:0] prod_imag_a; +wire signed [2*B-1:0] prod_imag_b; +reg signed [2*B-1:0] prod_real_a_r; +reg signed [2*B-1:0] prod_real_b_r; +reg signed [2*B-1:0] prod_imag_a_r; +reg signed [2*B-1:0] prod_imag_b_r; + +// Full product. +wire signed [2*B-1:0] prod_real; +wire signed [2*B-1:0] prod_imag; +reg signed [2*B-1:0] prod_real_r; +reg signed [2*B-1:0] prod_imag_r; + +// Rounding. +wire signed [B-1:0] prod_real_round; +wire signed [B-1:0] prod_imag_round; +wire [2*B-1:0] prod; +reg [2*B-1:0] prod_r; + +/****************/ +/* Architecture */ +/****************/ +// Partial products. +assign dina_real = dina_r[0 +: B]; +assign dina_imag = (CONJA == 1)? -dina_r[B +: B] : dina_r[B +: B]; +assign dinb_real = dinb_r[0 +: B]; +assign dinb_imag = (CONJB == 1)? -dinb_r[B +: B] : dinb_r[B +: B]; +assign prod_real_a = dina_real*dinb_real; +assign prod_real_b = dina_imag*dinb_imag; +assign prod_imag_a = dina_real*dinb_imag; +assign prod_imag_b = dina_imag*dinb_real; + +// Full product. +assign prod_real = prod_real_a_r - prod_real_b_r; +assign prod_imag = prod_imag_a_r + prod_imag_b_r; + +// Rounding. +assign prod_real_round = prod_real_r [2*B-2 -: B]; +assign prod_imag_round = prod_imag_r [2*B-2 -: B]; +assign prod = {prod_imag_round,prod_real_round}; + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // Valid pipeline. + valid_r1 <= 0; + valid_r2 <= 0; + valid_r3 <= 0; + valid_r4 <= 0; + + // Input registers. + dina_r <= 0; + dinb_r <= 0; + + // Partial products. + prod_real_a_r <= 0; + prod_real_b_r <= 0; + prod_imag_a_r <= 0; + prod_imag_b_r <= 0; + + // Full product. + prod_real_r <= 0; + prod_imag_r <= 0; + + // Rounding. + prod_r <= 0; + end + else begin + // Valid pipeline. + valid_r1 <= din_valid; + valid_r2 <= valid_r1; + valid_r3 <= valid_r2; + valid_r4 <= valid_r3; + + // Input registers. + dina_r <= dina; + dinb_r <= dinb; + + // Partial products. + prod_real_a_r <= prod_real_a; + prod_real_b_r <= prod_real_b; + prod_imag_a_r <= prod_imag_a; + prod_imag_b_r <= prod_imag_b; + + // Full product. + prod_real_r <= prod_real; + prod_imag_r <= prod_imag; + + // Rounding. + prod_r <= prod; + + end +end + +// Assign outputs. +assign dout_valid = valid_r4; +assign dout = prod_r; + +endmodule + diff --git a/firmware/ip/axis_kidsim_v3/src/punct.sv b/firmware/ip/axis_kidsim_v3/src/punct.sv new file mode 100644 index 0000000..d7d37ad --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/punct.sv @@ -0,0 +1,86 @@ +module punct + ( + // Reset and clock. + input wire rstn , + input wire clk , + + // Input data. + input wire din_valid , + input wire din_last , + + // Output data. + output wire dout_valid , + output wire dout_last , + output wire dout_en , + + // Registers. + input wire [15:0] ID_REG + ); + +/*************/ +/* Internals */ +/*************/; + +// Pipeline registers. +reg valid_r1 ; +reg valid_r2 ; +reg last_r1 ; +reg last_r2 ; + +// Counter. +reg [15:0] cnt ; + +// Flag. +wire flag ; + +// Registers. +reg [15:0] ID_REG_r ; + +/****************/ +/* Architecture */ +/****************/ + +// Flag. +assign flag = (ID_REG_r == cnt); + +always @(posedge clk) begin + if (~rstn) begin + // Pipeline registers. + valid_r1 <= 0; + valid_r2 <= 0; + last_r1 <= 0; + last_r2 <= 0; + + // Counter. + cnt <= 0; + + // Registers. + ID_REG_r <= 0; + end + else begin + // Pipeline registers. + valid_r1 <= din_valid; + valid_r2 <= valid_r1; + last_r1 <= din_last; + last_r2 <= last_r1; + + // Counter. + if ( valid_r2 == 1'b1 ) + if ( last_r2 == 1'b1 ) + cnt <= 0; + else + cnt <= cnt + 1; + + // Registers. + ID_REG_r <= ID_REG; + + end +end + +// Assign outputs. +assign dout_valid = valid_r2; +assign dout_last = last_r2; +assign dout_en = flag; + + +endmodule diff --git a/firmware/ip/axis_kidsim_v3/src/tb/tb.sv b/firmware/ip/axis_kidsim_v3/src/tb/tb.sv new file mode 100644 index 0000000..fd53c27 --- /dev/null +++ b/firmware/ip/axis_kidsim_v3/src/tb/tb.sv @@ -0,0 +1,415 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// Number of lanes. +parameter L = 8; + +// Number of bits. +localparam B = 16; +localparam NLAST = 4; +//localparam PUNCT_ID = NLAST-1; +localparam PUNCT_ID = 0; + +// Modulation trigger. +reg [L-1:0] trigger ; + +// AXI Slave I/F for configuration. +reg s_axi_aclk ; +reg s_axi_aresetn ; + +wire [7:0] s_axi_awaddr ; +wire [2:0] s_axi_awprot ; +wire s_axi_awvalid ; +wire s_axi_awready ; + +wire [31:0] s_axi_wdata ; +wire [3:0] s_axi_wstrb ; +wire s_axi_wvalid ; +wire s_axi_wready ; + +wire [1:0] s_axi_bresp ; +wire s_axi_bvalid ; +wire s_axi_bready ; + +wire [7:0] s_axi_araddr ; +wire [2:0] s_axi_arprot ; +wire s_axi_arvalid ; +wire s_axi_arready ; + +wire [31:0] s_axi_rdata ; +wire [1:0] s_axi_rresp ; +wire s_axi_rvalid ; +wire s_axi_rready ; + +// Reset and clock for axis_*. +reg aresetn ; +reg aclk ; + +reg s_axis_tvalid ; +wire [32*L-1:0] s_axis_tdata ; +reg s_axis_tlast ; + +// m_axis_* for output. +wire m_axis_tvalid ; +wire [32*L-1:0] m_axis_tdata ; +wire m_axis_tlast ; + +// Input/output data vectors. +reg [15:0] din_real_v [L] ; +reg [15:0] din_imag_v [L] ; +wire [15:0] dout_real_v [L] ; +wire [15:0] dout_imag_v [L] ; +wire [31:0] dout_v [L] ; + +// TDM. +reg tdm_sync ; +wire [32*NLAST-1:0] dout_tdm_demux_v [L] ; +wire [L-1:0] dout_valid_tdm_demux ; + +// TDM-demuxed data. +wire [31:0] dout_tdm_v [L][NLAST] ; +wire [15:0] dout_tdm_real_v [L][NLAST]; +wire [15:0] dout_tdm_imag_v [L][NLAST]; + +xil_axi_prot_t prot = 0; +reg[31:0] data; +xil_axi_resp_t resp; + +// TB control. +reg tb_trigger = 0; + +genvar i,j; +generate + for (i=0; i NLAST, so none resonator will be used. + for (int i=0; i + + user.org + user + axis_pfb_readout_v2 + 1.0 + + + m0_axis + + + + + + + TDATA + + + m0_axis_tdata + + + + + TVALID + + + m0_axis_tvalid + + + + + + m1_axis + + + + + + + TDATA + + + m1_axis_tdata + + + + + TVALID + + + m1_axis_tvalid + + + + + + m2_axis + + + + + + + TDATA + + + m2_axis_tdata + + + + + TVALID + + + m2_axis_tvalid + + + + + + m3_axis + + + + + + + TDATA + + + m3_axis_tdata + + + + + TVALID + + + m3_axis_tvalid + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m0_axis:m1_axis:m2_axis:m3_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_pfb_readout_v2 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + b7fc229d + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_pfb_readout_v2 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + b7fc229d + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + cb6eaf6e + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m0_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + 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CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir6_i/fir_5 + + + src/fir/fir_3/fir_3.xci + xci + CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir5_i/fir_3 + + + src/fir/fir_1/fir_1.xci + xci + CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir4_i/fir_1 + + + src/fir/fir_6/fir_6.xci + xci + CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir3_i/fir_6 + + + src/fir/fir_4/fir_4.xci + xci + CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir2_i/fir_4 + + + src/fir/fir_2/fir_2.xci + xci + CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir1_i/fir_2 + + + src/fir/fir_0/fir_0.xci + xci + CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir0_i/fir_0 + + + src/fir/coef/fir_7.coe + coe + + + src/fir/coef/fir_5.coe + coe + + + src/fir/coef/fir_3.coe + coe + + + src/fir/coef/fir_1.coe + coe + + + src/fir/coef/fir_6.coe + coe + + + src/fir/coef/fir_4.coe + coe + + + src/fir/coef/fir_2.coe + coe + + + src/fir/coef/fir_0.coe + coe + + + src/ddsprod.sv + systemVerilogSource + + + src/ddsprod_v.sv + systemVerilogSource + + + src/firs.sv + systemVerilogSource + + + src/pfb.sv + systemVerilogSource + + + src/pfb_dds_mux.sv + systemVerilogSource + + + src/pfb_mux.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/ssrfft_8x8/ssr_fft_8x8/conv_pkg.vhd + vhdlSource + + + src/pimod.vhd + vhdlSource + + + src/ssrfft_8x8/ssr_fft_8x8/single_reg_w_init.vhd + vhdlSource + + + src/ssrfft_8x8/ssr_fft_8x8/srl33e.vhd + vhdlSource + + + src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8_entity_declarations.vhd + vhdlSource + + + src/ssrfft_8x8/ssr_fft_8x8/xlclockdriver_rd.vhd + vhdlSource + + + src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8.vhd + vhdlSource + + + src/ssrfft_8x8/ssrfft_8x8.vhd + vhdlSource + + + src/ssrfft_8x8/ssr_fft_8x8/synth_reg.vhd + vhdlSource + + + src/ssrfft_8x8/ssr_fft_8x8/synth_reg_reg.vhd + vhdlSource + + + src/ssrfft_8x8/ssr_fft_8x8/synth_reg_w_init.vhd + vhdlSource + + + src/axis_pfb_readout_v2.v + verilogSource + CHECKSUM_197f4331 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dds_0/dds_0.xci + xci + CELL_NAME_pfb_dds_mux_i/ddsprod_v_i/genblk1[0].ddsprod_i/dds_i/dds_0 + + + src/fir/fir_7/fir_7.xci + xci + CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir7_i/fir_7 + + + src/fir/fir_5/fir_5.xci + xci + CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir6_i/fir_5 + + + src/fir/fir_3/fir_3.xci + xci + CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir5_i/fir_3 + + + src/fir/fir_1/fir_1.xci + xci + CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir4_i/fir_1 + + + src/fir/fir_6/fir_6.xci + xci + CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir3_i/fir_6 + + + src/fir/fir_4/fir_4.xci + xci + CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir2_i/fir_4 + + + src/fir/fir_2/fir_2.xci + xci + CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir1_i/fir_2 + + + src/fir/fir_0/fir_0.xci + xci + CELL_NAME_pfb_dds_mux_i/pfb_i/firs_i/fir0_i/fir_0 + + + src/fir/coef/fir_7.coe + coe + + + src/fir/coef/fir_5.coe + coe + + + src/fir/coef/fir_3.coe + coe + + + src/fir/coef/fir_1.coe + coe + + + src/fir/coef/fir_6.coe + coe + + + src/fir/coef/fir_4.coe + coe + + + src/fir/coef/fir_2.coe + coe + + + src/fir/coef/fir_0.coe + coe + + + src/ddsprod.sv + systemVerilogSource + + + src/ddsprod_v.sv + systemVerilogSource + + + src/firs.sv + systemVerilogSource + + + src/pfb.sv + systemVerilogSource + + + src/pfb_dds_mux.sv + systemVerilogSource + + + src/pfb_mux.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/ssrfft_8x8/ssr_fft_8x8/conv_pkg.vhd + vhdlSource + + + src/pimod.vhd + vhdlSource + + + src/ssrfft_8x8/ssr_fft_8x8/single_reg_w_init.vhd + vhdlSource + + + src/ssrfft_8x8/ssr_fft_8x8/srl33e.vhd + vhdlSource + + + src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8_entity_declarations.vhd + vhdlSource + + + src/ssrfft_8x8/ssr_fft_8x8/xlclockdriver_rd.vhd + vhdlSource + + + src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8.vhd + vhdlSource + + + src/ssrfft_8x8/ssrfft_8x8.vhd + vhdlSource + + + src/ssrfft_8x8/ssr_fft_8x8/synth_reg.vhd + vhdlSource + + + src/ssrfft_8x8/ssr_fft_8x8/synth_reg_reg.vhd + vhdlSource + + + src/ssrfft_8x8/ssr_fft_8x8/synth_reg_w_init.vhd + vhdlSource + + + src/axis_pfb_readout_v2.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_pfb_readout_v2_v1_0.tcl + tclSource + CHECKSUM_cb6eaf6e + XGUI_VERSION_2 + + + + AXIS PFB Readout, 8 Channels (4 outputs), Overlap 50%, 32-bit DDS per channel. + + + Component_Name + axis_pfb_readout_v2_v1_0 + + + INTERLEAVED_INPUT + Interleaved Input + true + + + + + + zynquplus + + + /UserIP + + AXIS PFB Readout x8 V2 + package_project + 4 + 2022-08-19T21:02:47Z + + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + /home/lstefana/v20.2/ip/axis_pfb_readout_v2 + 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/home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_pfb_readout_v2 + + + + 2020.2 + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 0000000..7cfbd51 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 8 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 0000000..a53be60 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 8 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..ac9cf04 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,200 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 0000000..491fd33 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4760 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + ARSIZE + + + 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std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rlast + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_ruser + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_rvalid + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rready + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + M_INITIATOR_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + wr_socket + + + width + 32 + + + + + + + 1 + + + + + M_INITIATOR_rd_socket + AXIMM Read Socket + AXIMM Socket for Read + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + rd_socket + + + width + 32 + + + + + + + 1 + + + + + S_TARGET_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + + + + + 1 + + + + + S_TARGET_rd_socket + AXIMM Read Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + + + + + 1 + + + + + + + C_AXI_PROTOCOL + 2 + + + C_AXI_INTERFACE_MODE + 0 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_WDATA_WIDTH + 32 + + + C_AXI_RDATA_WIDTH + 32 + + + C_AXI_WID_WIDTH + 0 + + + C_AXI_RID_WIDTH + 0 + + + C_AXI_AWUSER_WIDTH + 0 + + + C_AXI_ARUSER_WIDTH + 0 + + + C_AXI_WUSER_WIDTH + 0 + + + C_AXI_RUSER_WIDTH + 0 + + + C_AXI_BUSER_WIDTH + 0 + + + C_AXI_SUPPORTS_NARROW + 0 + + + C_AXI_HAS_BURST + 0 + + + C_AXI_HAS_LOCK + 0 + + + C_AXI_HAS_CACHE + 0 + + + C_AXI_HAS_REGION + 0 + + + C_AXI_HAS_PROT + 1 + + + C_AXI_HAS_QOS + 0 + + + C_AXI_HAS_WSTRB + 1 + + + C_AXI_HAS_BRESP + 1 + + + C_AXI_HAS_RRESP + 1 + + + C_AXI_HAS_ARESETN + 1 + + + + + + choice_list_04fafd91 + AXI3 + AXI4 + AXI4LITE + + + choice_list_6240decd + READ_ONLY + READ_WRITE + WRITE_ONLY + + + choice_list_642e7122 + MASTER + PASS_THROUGH + SLAVE + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_0fc128e8 + 0 + 0 + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi_mst_0.vho + vhdlTemplate + + + axi_mst_0.veo + verilogTemplate + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_8 + + + + xilinx_synthesisconstraints_view_fileset + + axi_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_8 + + + + xilinx_externalfiles_view_fileset + + axi_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axi_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axi_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_8 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_8 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_8 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 8 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/axi_slv.vhd b/firmware/ip/axis_pfb_readout_v2/src/axi_slv.vhd new file mode 100644 index 0000000..abafe46 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/axi_slv.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + FREQ0_REG : out std_logic_vector (31 downto 0); + FREQ1_REG : out std_logic_vector (31 downto 0); + FREQ2_REG : out std_logic_vector (31 downto 0); + FREQ3_REG : out std_logic_vector (31 downto 0); + FREQ4_REG : out std_logic_vector (31 downto 0); + FREQ5_REG : out std_logic_vector (31 downto 0); + FREQ6_REG : out std_logic_vector (31 downto 0); + FREQ7_REG : out std_logic_vector (31 downto 0); + OUTSEL_REG : out std_logic_vector (1 downto 0); + CH0SEL_REG : out std_logic_vector (2 downto 0); + CH1SEL_REG : out std_logic_vector (2 downto 0); + CH2SEL_REG : out std_logic_vector (2 downto 0); + CH3SEL_REG : out std_logic_vector (2 downto 0) + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Output Registers. + FREQ0_REG <= slv_reg0; + FREQ1_REG <= slv_reg1; + FREQ2_REG <= slv_reg2; + FREQ3_REG <= slv_reg3; + FREQ4_REG <= slv_reg4; + FREQ5_REG <= slv_reg5; + FREQ6_REG <= slv_reg6; + FREQ7_REG <= slv_reg7; + OUTSEL_REG <= slv_reg8(1 downto 0); + CH0SEL_REG <= slv_reg9(2 downto 0); + CH1SEL_REG <= slv_reg10(2 downto 0); + CH2SEL_REG <= slv_reg11(2 downto 0); + CH3SEL_REG <= slv_reg12(2 downto 0); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v2/src/axis_pfb_readout_v2.v b/firmware/ip/axis_pfb_readout_v2/src/axis_pfb_readout_v2.v new file mode 100644 index 0000000..e7977bb --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/axis_pfb_readout_v2.v @@ -0,0 +1,234 @@ +module axis_pfb_readout_v2 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // s_* and m_* reset/clock. + aclk , + aresetn , + + // S_AXIS for input samples + s_axis_tvalid , + s_axis_tready , + s_axis_tdata , + + // M_AXIS for CH0 output. + m0_axis_tvalid , + m0_axis_tdata , + + // M_AXIS for CH1 output. + m1_axis_tvalid , + m1_axis_tdata , + + // M_AXIS for CH2 output. + m2_axis_tvalid , + m2_axis_tdata , + + // M_AXIS for CH3 output. + m3_axis_tvalid , + m3_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Input is interleaved I+Q, compatible with quad ADC (if false, input is not interleaved - compatible with dual ADC + combiner) +parameter INTERLEAVED_INPUT = 1; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input aresetn; +input aclk; + +input s_axis_tvalid; +output s_axis_tready; +input [4*32-1:0] s_axis_tdata; + +output m0_axis_tvalid; +output [31:0] m0_axis_tdata; + +output m1_axis_tvalid; +output [31:0] m1_axis_tdata; + +output m2_axis_tvalid; +output [31:0] m2_axis_tdata; + +output m3_axis_tvalid; +output [31:0] m3_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] FREQ0_REG; +wire [31:0] FREQ1_REG; +wire [31:0] FREQ2_REG; +wire [31:0] FREQ3_REG; +wire [31:0] FREQ4_REG; +wire [31:0] FREQ5_REG; +wire [31:0] FREQ6_REG; +wire [31:0] FREQ7_REG; +wire [1:0] OUTSEL_REG; +wire [2:0] CH0SEL_REG; +wire [2:0] CH1SEL_REG; +wire [2:0] CH2SEL_REG; +wire [2:0] CH3SEL_REG; + + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .FREQ0_REG (FREQ0_REG ), + .FREQ1_REG (FREQ1_REG ), + .FREQ2_REG (FREQ2_REG ), + .FREQ3_REG (FREQ3_REG ), + .FREQ4_REG (FREQ4_REG ), + .FREQ5_REG (FREQ5_REG ), + .FREQ6_REG (FREQ6_REG ), + .FREQ7_REG (FREQ7_REG ), + .OUTSEL_REG (OUTSEL_REG ), + .CH0SEL_REG (CH0SEL_REG ), + .CH1SEL_REG (CH1SEL_REG ), + .CH2SEL_REG (CH2SEL_REG ), + .CH3SEL_REG (CH3SEL_REG ) + ); + +// PFB with DDS product. +pfb_dds_mux + #( + .INTERLEAVED_INPUT(INTERLEAVED_INPUT) + ) + pfb_dds_mux_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input data. + .s_axis_tready (s_axis_tready ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for CH0 output. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + + // M_AXIS for CH1 output. + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tdata (m1_axis_tdata ), + + // M_AXIS for CH2 output. + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tdata (m2_axis_tdata ), + + // M_AXIS for CH3 output. + .m3_axis_tvalid (m3_axis_tvalid ), + .m3_axis_tdata (m3_axis_tdata ), + + // Registers. + .FREQ0_REG (FREQ0_REG ), + .FREQ1_REG (FREQ1_REG ), + .FREQ2_REG (FREQ2_REG ), + .FREQ3_REG (FREQ3_REG ), + .FREQ4_REG (FREQ4_REG ), + .FREQ5_REG (FREQ5_REG ), + .FREQ6_REG (FREQ6_REG ), + .FREQ7_REG (FREQ7_REG ), + .OUTSEL_REG (OUTSEL_REG ), + .CH0SEL_REG (CH0SEL_REG ), + .CH1SEL_REG (CH1SEL_REG ), + .CH2SEL_REG (CH2SEL_REG ), + .CH3SEL_REG (CH3SEL_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.veo b/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.veo new file mode 100644 index 0000000..2aa6467 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.veo @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:dds_compiler:6.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +dds_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [31 : 0] s_axis_phase_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file dds_0.v when simulating +// the core, dds_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.xci b/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.xci new file mode 100644 index 0000000..f65db0d --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.xci @@ -0,0 +1,312 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 4 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 0 + 0 + 1 + 0 + 32 + 1 + 0 + zynquplus + Full_Range + 1 + dds_0 + Not_Required + 256 + Minimal + 0.06 + Coregen + false + false + false + false + 4 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + true + Auto + Twos_Complement + Auto + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32 + None + false + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 20 + TRUE + ../../../../project_1.gen/sources_1/ip/dds_0 + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ddsprod.sv b/firmware/ip/axis_pfb_readout_v2/src/ddsprod.sv new file mode 100644 index 0000000..985c391 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ddsprod.sv @@ -0,0 +1,183 @@ +module ddsprod + ( + // Reset and clock. + aresetn , + aclk , + + // S_AXIS for input data. + s_axis_tvalid , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tdata , + + // Registers. + FREQ_REG , + OUTSEL_REG + ); + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +input s_axis_tvalid; +input [31:0] s_axis_tdata; + +output m_axis_tvalid; +output [31:0] m_axis_tdata; + +input [31:0] FREQ_REG; +input [1:0] OUTSEL_REG; + +/********************/ +/* Internal signals */ +/********************/ +// Input valid. +reg tvalid_r1; +reg tvalid_r2; +reg tvalid_r3; + +// DDS valid input. +reg dds_valid_r; + +// Input data. +reg [31:0] di_r1; +reg [31:0] di_r2; +reg [31:0] di_r3; +wire signed [15:0] di_real; +wire signed [15:0] di_imag; + +// DDS output. +wire [31:0] dds_dout; +reg [31:0] dds_dout_r1; +reg [31:0] dds_dout_r2; +reg [31:0] dds_dout_r3; +wire signed [15:0] dds_real; +wire signed [15:0] dds_imag; + +// Partial products. +wire signed [31:0] do_real_a; +wire signed [31:0] do_real_b; +reg signed [31:0] do_real_a_r1; +reg signed [31:0] do_real_b_r1; +wire signed [31:0] do_imag_a; +wire signed [31:0] do_imag_b; +reg signed [31:0] do_imag_a_r1; +reg signed [31:0] do_imag_b_r1; + +// Full out. +wire signed [31:0] do_real; +reg signed [15:0] do_real_r1; +wire signed [31:0] do_imag; +reg signed [15:0] do_imag_r1; + +// Muxed output. +wire [31:0] do_mux; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// DDS instance. +dds_0 dds_i + ( + .aclk (aclk ), + .s_axis_phase_tvalid(dds_valid_r ), + .s_axis_phase_tdata (FREQ_REG ), + .m_axis_data_tvalid ( ), + .m_axis_data_tdata (dds_dout ) + ); + +// Input data. +assign di_real = di_r1[15:0]; +assign di_imag = di_r1[31:16]; + +// DDS output. +assign dds_real = dds_dout_r1[15:0]; +assign dds_imag = dds_dout_r1[31:16]; + +// Partial products. +assign do_real_a = di_real*dds_real; +assign do_real_b = di_imag*dds_imag; +assign do_imag_a = di_real*dds_imag; +assign do_imag_b = di_imag*dds_real; + +// Full out. +assign do_real = do_real_a_r1 - do_real_b_r1; +assign do_imag = do_imag_a_r1 + do_imag_b_r1; + +// Muxed output. +assign do_mux = (OUTSEL_REG == 0)? {do_imag_r1,do_real_r1} : + (OUTSEL_REG == 1)? di_r3 : + (OUTSEL_REG == 2)? dds_dout_r3 : 32'h0000_0000; + +// Registers. +always @(posedge aclk) begin + if (~aresetn) begin + // Input valid. + tvalid_r1 <= 0; + tvalid_r2 <= 0; + tvalid_r3 <= 0; + + // DDS valid input. + dds_valid_r <= 0; + + // Input data. + di_r1 <= 0; + di_r2 <= 0; + di_r3 <= 0; + + // DDS output. + dds_dout_r1 <= 0; + dds_dout_r2 <= 0; + dds_dout_r3 <= 0; + + // Partial products. + do_real_a_r1 <= 0; + do_real_b_r1 <= 0; + do_imag_a_r1 <= 0; + do_imag_b_r1 <= 0; + + // Full out. + do_real_r1 <= 0; + do_imag_r1 <= 0; + end + else begin + // Input valid. + tvalid_r1 <= s_axis_tvalid; + tvalid_r2 <= tvalid_r1; + tvalid_r3 <= tvalid_r2; + + // DDS valid input. + dds_valid_r <= 1; + + // Input data. + di_r1 <= s_axis_tdata; + di_r2 <= di_r1; + di_r3 <= di_r2; + + // DDS output. + dds_dout_r1 <= dds_dout; + dds_dout_r2 <= dds_dout_r1; + dds_dout_r3 <= dds_dout_r2; + + // Partial products. + do_real_a_r1 <= do_real_a; + do_real_b_r1 <= do_real_b; + do_imag_a_r1 <= do_imag_a; + do_imag_b_r1 <= do_imag_b; + + // Full out. + do_real_r1 <= do_real[30:15]; + do_imag_r1 <= do_imag[30:15]; + end +end + +// Assign outputs. +assign m_axis_tvalid = tvalid_r3; +assign m_axis_tdata = do_mux; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ddsprod_v.sv b/firmware/ip/axis_pfb_readout_v2/src/ddsprod_v.sv new file mode 100644 index 0000000..64ba5e6 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ddsprod_v.sv @@ -0,0 +1,116 @@ +module ddsprod_v + ( + // Reset and clock. + aresetn , + aclk , + + // S_AXIS for input data. + s_axis_tvalid , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tdata , + + // Registers. + FREQ0_REG , + FREQ1_REG , + FREQ2_REG , + FREQ3_REG , + FREQ4_REG , + FREQ5_REG , + FREQ6_REG , + FREQ7_REG , + OUTSEL_REG + ); + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +input s_axis_tvalid; +input [8*32-1:0] s_axis_tdata; + +output m_axis_tvalid; +output [8*32-1:0] m_axis_tdata; + +input [31:0] FREQ0_REG; +input [31:0] FREQ1_REG; +input [31:0] FREQ2_REG; +input [31:0] FREQ3_REG; +input [31:0] FREQ4_REG; +input [31:0] FREQ5_REG; +input [31:0] FREQ6_REG; +input [31:0] FREQ7_REG; +input [1:0] OUTSEL_REG; + +/********************/ +/* Internal signals */ +/********************/ +localparam L = 8; + +// Input data vector. +wire [31:0] din_v [0:L-1]; + +// Frequency registers. +wire [31:0] freq_reg_v [0:7]; + +// Output data vector. +wire [31:0] dout_v [0:L-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Frequency registers. +assign freq_reg_v[0] = FREQ0_REG; +assign freq_reg_v[1] = FREQ1_REG; +assign freq_reg_v[2] = FREQ2_REG; +assign freq_reg_v[3] = FREQ3_REG; +assign freq_reg_v[4] = FREQ4_REG; +assign freq_reg_v[5] = FREQ5_REG; +assign freq_reg_v[6] = FREQ6_REG; +assign freq_reg_v[7] = FREQ7_REG; + +genvar i; +generate + for (i=0; i + + xilinx.com + xci + unknown + 1.0 + + + fir_0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_0.mif + 7 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_0 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 13 + 2 + 0 + 0 + 32 + 1 + 1 + 1 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_0.coe + 0 + false + 1 + Signed + Non_Symmetric + 16 + 7 + fir_0 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../ipgen.gen/sources_1/ip/fir_0 + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_1/fir_1.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_1/fir_1.xci new file mode 100644 index 0000000..1db52de --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_1/fir_1.xci @@ -0,0 +1,312 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_1 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_1.mif + 7 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_1 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 13 + 2 + 0 + 0 + 32 + 1 + 1 + 1 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_1.coe + 0 + false + 1 + Signed + Non_Symmetric + 16 + 7 + fir_1 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../ipgen.gen/sources_1/ip/fir_1 + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_2/fir_2.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_2/fir_2.xci new file mode 100644 index 0000000..0f0a644 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_2/fir_2.xci @@ -0,0 +1,312 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_2 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_2.mif + 7 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_2 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 13 + 2 + 0 + 0 + 32 + 1 + 1 + 1 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_2.coe + 0 + false + 1 + Signed + Non_Symmetric + 16 + 7 + fir_2 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../ipgen.gen/sources_1/ip/fir_2 + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_3/fir_3.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_3/fir_3.xci new file mode 100644 index 0000000..d0fd7e8 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_3/fir_3.xci @@ -0,0 +1,312 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_3 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_3.mif + 7 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_3 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 13 + 2 + 0 + 0 + 32 + 1 + 1 + 1 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_3.coe + 0 + false + 1 + Signed + Non_Symmetric + 16 + 7 + fir_3 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../ipgen.gen/sources_1/ip/fir_3 + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_4/fir_4.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_4/fir_4.xci new file mode 100644 index 0000000..48cef3a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_4/fir_4.xci @@ -0,0 +1,312 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_4 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_4.mif + 7 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_4 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 13 + 2 + 0 + 0 + 32 + 1 + 1 + 1 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_4.coe + 0 + false + 1 + Signed + Non_Symmetric + 16 + 7 + fir_4 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../ipgen.gen/sources_1/ip/fir_4 + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_5/fir_5.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_5/fir_5.xci new file mode 100644 index 0000000..be396b4 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_5/fir_5.xci @@ -0,0 +1,312 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_5 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_5.mif + 7 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_5 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 13 + 2 + 0 + 0 + 32 + 1 + 1 + 1 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_5.coe + 0 + false + 1 + Signed + Non_Symmetric + 16 + 7 + fir_5 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../ipgen.gen/sources_1/ip/fir_5 + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_6/fir_6.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_6/fir_6.xci new file mode 100644 index 0000000..fb143ce --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_6/fir_6.xci @@ -0,0 +1,312 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_6 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_6.mif + 7 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_6 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 13 + 2 + 0 + 0 + 32 + 1 + 1 + 1 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_6.coe + 0 + false + 1 + Signed + Non_Symmetric + 16 + 7 + fir_6 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../ipgen.gen/sources_1/ip/fir_6 + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_7/fir_7.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_7/fir_7.xci new file mode 100644 index 0000000..bcf4c74 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_7/fir_7.xci @@ -0,0 +1,312 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_7 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_7.mif + 7 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_7 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 13 + 2 + 0 + 0 + 32 + 1 + 1 + 1 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_7.coe + 0 + false + 1 + Signed + Non_Symmetric + 16 + 7 + fir_7 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../ipgen.gen/sources_1/ip/fir_7 + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/gen.pl b/firmware/ip/axis_pfb_readout_v2/src/fir/gen.pl new file mode 100644 index 0000000..deba046 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/gen.pl @@ -0,0 +1,30 @@ +#!/usr/bin/perl +# This file generates the fir.tcl file to be run from vivado. +# Copy fir coefficient files. One IP per .coe file will be created. +# Copy generated .xci files to avoid generating FIR cores every time. + +open(my $file, "$ARGV[0]") or die "Could not open file '$ARGV[0]' $!"; +my @lines = <$file>; + +open(my $out_tcl, ">", "fir.tcl") or die "Could not open file fir.tcl $!"; +open(my $out_add, ">", "add.tcl") or die "Could not open file fir.tcl $!"; + +@out = `ls coef/*.coe`; +foreach (@out) +{ + chomp($_); + $fir = $_; + $fir =~ s/coef\///g; + $fir =~ s/.coe//g; + + print $out_add ("add_files ./fir/$fir/$fir.xci\n"); + + foreach my $line (@lines) + { + my $temp = $line; + chomp($temp); + $temp =~ s//$fir/g; + print $out_tcl ("$temp\n"); + } +} + diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/tcl/fir.tcl.template b/firmware/ip/axis_pfb_readout_v2/src/fir/tcl/fir.tcl.template new file mode 100644 index 0000000..0264c07 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/tcl/fir.tcl.template @@ -0,0 +1,26 @@ +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/v20.2/ip/axis_pfb_readout/src/fir/coef/.coe} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Coefficient_Structure {Non_Symmetric} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.Coefficient_Sets {1} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Number_Channels {1} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7}] \ +[get_ips ] diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/tcl/ipgen.tcl b/firmware/ip/axis_pfb_readout_v2/src/fir/tcl/ipgen.tcl new file mode 100644 index 0000000..e1a3705 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/fir/tcl/ipgen.tcl @@ -0,0 +1,13 @@ +# Create project. +create_project ipgen ./ipgen -part xczu49dr-ffvf1760-2-e + +# Set language options. +set_property simulator_language Mixed [current_project] +set_property target_language Verilog [current_project] + +# Create IPs. +source fir.tcl + +# Generate instantiation templates. +generate_target instantiation_template [get_ips *] + diff --git a/firmware/ip/axis_pfb_readout_v2/src/firs.sv b/firmware/ip/axis_pfb_readout_v2/src/firs.sv new file mode 100644 index 0000000..c602e2b --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/firs.sv @@ -0,0 +1,196 @@ +module firs + ( + // Reset and clock. + aresetn , + aclk , + + // S_AXIS for input data. + s_axis_tready , + s_axis_tvalid , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of Lanes (Input). +parameter L = 4; + +// Input is interleaved I+Q, compatible with quad ADC (if false, input is not interleaved - compatible with dual ADC + combiner) +parameter INTERLEAVED_INPUT = 1; + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [L*32-1:0] s_axis_tdata; + +output m_axis_tvalid; +output [2*L*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Input delay. +wire[31:0] data_v [0:L-1]; +reg [31:0] data_r1 [0:L-1]; +reg [31:0] data_r2 [0:L-1]; + +// Valid input. +reg valid_r; + +// FIR outputs. +wire[2*L-1:0] valid_v; +wire[31:0] dout_v [0:2*L-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i '0'); + + -- sel register. + sel <= (others => '0'); + + -- Pipeline registers. + din_r <= (others => '0'); + din_rr <= (others => '0'); + valid_r <= '0'; + valid_rr <= '0'; + else + -- Signals combined after pm. + d_pm_r <= d_pm; + + -- sel register. + if (valid_r = '1') then + sel <= sel + 1; + end if; + + -- Pipeline registers. + din_r <= s_axis_tdata; + din_rr <= din_r; + valid_r <= s_axis_tvalid; + valid_rr <= valid_r; + end if; + end if; +end process; + +-- Slice input. +GEN_SLICE_IN: for I in 0 to N-1 generate + dv_i(I) <= signed(din_r ( (I+1)*B-1 downto I*B)); + dv_q(I) <= signed(din_r ( N*B+ (I+1)*B-1 downto N*B+ I*B)); +end generate GEN_SLICE_IN; + +-- Multiply by -1 only odd samples. +GEN_PM: for I in 0 to N/2-1 generate + -- Even samples: multiply always by 1. + dv_i_pm(2*I) <= dv_i(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_i_pm(2*I+1) <= to_signed(MAX_P,B) when dv_i(2*I+1) = to_signed(MIN_N,B) else + -dv_i(2*I+1); + + -- Even samples: multiply always by 1. + dv_q_pm(2*I) <= dv_q(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_q_pm(2*I+1) <= to_signed(MAX_P,B) when dv_q(2*I+1) = to_signed(MIN_N,B) else + -dv_q(2*I+1); +end generate GEN_PM; + +-- Combine signals back. +GEN_COMBINE_PM: for I in 0 to N-1 generate + d_pm ( (I+1)*B-1 downto I*B) <= std_logic_vector(dv_i_pm(I)); + d_pm ( N*B+ (I+1)*B-1 downto N*B+I*B) <= std_logic_vector(dv_q_pm(I)); +end generate GEN_COMBINE_PM; + +-- Data mux. +dout_mux <= din_rr when sel = to_unsigned(0,sel'length) else + d_pm_r; + + +-- Assign outputs. +m_axis_tdata <= dout_mux; +m_axis_tvalid <= valid_rr; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/conv_pkg.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/conv_pkg.vhd new file mode 100644 index 0000000..b8f1a8f --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/conv_pkg.vhd @@ -0,0 +1,1922 @@ +--------------------------------------------------------------------- +-- +-- Package : conv_pkg +-- +-- Filename : conv_pkg.vhd +-- +-- Date : 8/16/99 +-- +-- Description : Package that defines constant values that is used in the +-- XBS and functions that convert one type to another. +-- +-- Note : This package uses a VHDL 93 constructs therefore when +-- compiling with ModelTech use: vcom -93 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package conv_pkg is + --------------------------------------------------------------------------- + -- Constant that tells whether we're simulating + --------------------------------------------------------------------------- + constant simulating : boolean := false + -- synthesis translate_off + or true + -- synthesis translate_on + ; + + --------------------------------------------------------------------------- + -- Constants for XBS + --------------------------------------------------------------------------- + -- Arithmetic types + constant xlUnsigned : integer := 1; + constant xlSigned : integer := 2; + constant xlFloat : integer := 3; + + -- Constants for Quantization and Overflow + constant xlWrap : integer := 1; + constant xlSaturate : integer := 2; + constant xlTruncate : integer := 1; + constant xlRound : integer := 2; + constant xlRoundBanker : integer := 3; + + -- Constants for xladdsub s-function + constant xlAddMode : integer := 1; + constant xlSubMode : integer := 2; + + --------------------------------------------------------------------------- + -- Black Box Attributes + --------------------------------------------------------------------------- + attribute black_box : boolean; -- for Synplicity (obsolete) + attribute syn_black_box : boolean; -- for Synplicity Version 6.0 + attribute fpga_dont_touch: string; -- for FPGA Express + attribute box_type : string; -- for XST + + --------------------------------------------------------------------------- + -- Attributes to keep clock enable signals + --------------------------------------------------------------------------- + attribute keep : string; + attribute syn_keep : boolean; + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type and vice versa + function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; + function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; + + -- convert a std_logic_vector to a signed type and vice versa + function std_logic_vector_to_signed(inp : std_logic_vector) return signed; + function signed_to_std_logic_vector(inp : signed) return std_logic_vector; + -- convert signed to unsigned and vice versa + function unsigned_to_signed(inp : unsigned) return signed; + function signed_to_unsigned(inp : signed) return unsigned; + -- Tests used in convert_type + function pos(inp : std_logic_vector; arith : INTEGER) return boolean; + function all_same(inp: std_logic_vector) return boolean; + function all_zeros(inp: std_logic_vector) return boolean; + function is_point_five(inp: std_logic_vector) return boolean; + function all_ones(inp: std_logic_vector) return boolean; + + + + -- Convert a fixed point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + -- slice a vector + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector; + + -- slice a signed + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned; + + -- slice a unsigned + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Quantization Functions + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + + -- Overflow functions + function max_signed(width : INTEGER) return std_logic_vector; + function min_signed(width : INTEGER) return std_logic_vector; + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) return std_logic_vector; + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + --------------------------------------------------------------------------- + -- Binary point alignment functions + --------------------------------------------------------------------------- + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; + + -- Returns the number of integer bits after alignment of fixed point num. + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector; + + -- Pad LSB with zeros + function pad_LSB(inp : std_logic_vector; new_width: integer) + return std_logic_vector; + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith : integer) + return std_logic_vector; + + -- Find the max & min integer. + function max(L, R: INTEGER) return INTEGER; + function min(L, R: INTEGER) return INTEGER; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean; + + -- convert a boolean into a signed + function boolean_to_signed (inp : boolean; width: integer) + return signed; + -- convert a boolean into an unsigned + function boolean_to_unsigned (inp : boolean; width: integer) + return unsigned; + -- convert a boolean into std_logic_vector + function boolean_to_vector (inp : boolean) + return std_logic_vector; + -- convert a std_logic into std_logic_vector + function std_logic_to_vector (inp : std_logic) + return std_logic_vector; + -- convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector; + + -- Convert std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer; + function std_logic_to_integer(constant inp : std_logic := '0') + return integer; + + -- Convert a binary string array element into a std_logic_vector + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector; + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector; + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector (inp : string; width : integer) + return std_logic_vector; + + -- Make a binary string that represents zero + function makeZeroBinStr (width : integer) return STRING; + + + --------------------------------------------------------------------------- + -- Debugging functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's (i.e., 0bXX.X) + function is_binary_string_invalid (inp : string) + return boolean; + -- Check for all U's (i.e., 0bUU.U) + function is_binary_string_undefined (inp : string) + return boolean; + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean; + + + -- convert a std_logic_vector to a real type and vice versa + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real; + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real; + + + -- convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector; + -- convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector; + + -- display_precision is the number of digits to display in ModelTech's + -- waveform viewer ( used in to_string(inp : real) ) + constant display_precision : integer := 20; + -- convert a real into a string type + function real_to_string (inp : real) return string; + + -- Check of 0b and the beginning of a string + function valid_bin_string(inp : string) return boolean; + + -- Convert a std_logic_vector to a binary string + function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; + -- Convert a std_logic to a binary string + function std_logic_to_bin_string(inp : std_logic) return string; + -- convert a std_logic_vector to a binary string and add a binary point + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string; + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string; + + -- convert a std_logic_vector value to a character + type stdlogic_to_char_t is array(std_logic) of character; + constant to_char : stdlogic_to_char_t := ( + 'U' => 'U', + 'X' => 'X', + '0' => '0', + '1' => '1', + 'Z' => 'Z', + 'W' => 'W', + 'L' => 'L', + 'H' => 'H', + '-' => '-'); + + -- synthesis translate_on + +end conv_pkg; + +package body conv_pkg is + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type + function std_logic_vector_to_unsigned(inp : std_logic_vector) + return unsigned + is + begin + return unsigned (inp); + end; + + -- convert an unsigend to a std_logic_vector + function unsigned_to_std_logic_vector(inp : unsigned) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert an std_logic_vector to a signed + function std_logic_vector_to_signed(inp : std_logic_vector) + return signed + is + begin + return signed (inp); + end; + + -- convert an std_logic_vector to a sigend + function signed_to_std_logic_vector(inp : signed) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert unsigned to signed + function unsigned_to_signed (inp : unsigned) + return signed + is + begin -- unsigned_to_signed + return signed(std_logic_vector(inp)); + end; + + + -- convert signed to unsigned + function signed_to_unsigned (inp : signed) + return unsigned + is + begin -- signed_to_unsigned + return unsigned(std_logic_vector(inp)); + end; + + -- Test if a number is positive + function pos(inp : std_logic_vector; arith : INTEGER) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := inp; + if arith = xlUnsigned then + return true; + else + if vec(width-1) = '0' then + return true; + else + return false; + end if; + end if; + + -- Error + return true; + end; + + function max_signed(width : INTEGER) + return std_logic_vector + is + variable ones : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + ones := (others => '1'); + result(width-1) := '0'; + result(width-2 downto 0) := ones; + return result; + end; + + function min_signed(width : INTEGER) + return std_logic_vector + is + variable zeros : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + zeros := (others => '0'); + result(width-1) := '1'; + result(width-2 downto 0) := zeros; + return result; + end; + + -- Check if all the bits are the same + function all_same(inp: std_logic_vector) return boolean + is + variable result: boolean; + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + begin + vec := inp; + result := true; + if width > 0 then + for i in 1 to width-1 loop + if vec(i) /= vec(0) then + result := false; + end if; + end loop; + end if; + return result; + end; + + + -- Check if a number is all zeros + function all_zeros(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable zero : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + zero := (others => '0'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Check if a number is point five + function is_point_five(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (width > 1) then + if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then + result := true; + else + result := false; + end if; + else + if (vec(width-1) = '1') then + result := true; + else + result := false; + end if; + end if; + + return result; + end; + + -- Check if a number is all ones + function all_ones(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable one : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + one := (others => '1'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then + result := true; + else + result := false; + end if; + return result; + end; + + + --------------------------------------------------------------------------- + -- Type conersion functions + --------------------------------------------------------------------------- + + + -- Calculate the width of the temp. full precision representation + function full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return integer + is + variable result : integer; + begin + result := old_width + 2; + return result; + end; + + -- Calculate the width of the temp. quantized representation + -- ASSUMES POSITIVE BIN_PT + function quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return integer + is + variable right_of_dp, left_of_dp, result : integer; + begin + + right_of_dp := max(new_bin_pt, old_bin_pt); + left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); + + result := (old_width + 2) + (new_bin_pt - old_bin_pt); + return result; + end; + + + + -- Convert one Fix point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector + is + constant fp_width : integer := + full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, new_width, + new_bin_pt, new_arith); + constant fp_bin_pt : integer := old_bin_pt; + constant fp_arith : integer := old_arith; + variable full_precision_result : std_logic_vector(fp_width-1 downto 0); + + constant q_width : integer := + quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith); + constant q_bin_pt : integer := new_bin_pt; + constant q_arith : integer := old_arith; + variable quantized_result : std_logic_vector(q_width-1 downto 0); + + variable result : std_logic_vector(new_width-1 downto 0); + begin + result := (others => '0'); + + full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, + fp_arith); + + -- Apply quantization functions. This will remove LSB bits. + if (quantization = xlRound) then + + quantized_result := round_towards_inf(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + elsif (quantization = xlRoundBanker) then + quantized_result := round_towards_even(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + else + quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, q_arith); + end if; + + + -- Apply overflow function. This will remove MSB bits. + if (overflow = xlSaturate) then + result := saturation_arith(quantized_result, q_width, q_bin_pt, + q_arith, new_width, new_bin_pt, new_arith); + else + result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, + new_width, new_bin_pt, new_arith); + end if; + + + return result; + end; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, new_width, + new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (new_width - new_bin_pt) + - (old_width - old_bin_pt); + -- Number of digits to add/subract to the right of the decimal point + constant right_of_dp : integer := (new_bin_pt - old_bin_pt); + + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable j : integer; + + begin + vec := inp; + for i in new_width-1 downto 0 loop + j := i - right_of_dp; + if ( j > old_width-1) then + -- Bits to the left of the decimal point + if (new_arith = xlUnsigned) then + -- If unsigned zero pad MSB + result(i) := '0'; + else + -- If signed, sign extend MSB + result(i) := vec(old_width-1); + end if; + elsif ( j >= 0) then + -- Copy bits from input + result(i) := vec(j); + else + -- zero pad LSB + result(i) := '0'; + end if; + end loop; + + return result; + end; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant q_width : integer := quotient'length; + constant f_width : integer := fraction'length; + constant vec_MSB : integer := q_width+f_width-1; + constant result_MSB : integer := q_width+fraction_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := ( quotient & fraction ); + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant inp_width : integer := inp'length; + constant vec_MSB : integer := inp_width-1; + constant result_MSB : integer := result_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := inp; + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + -- vector slice + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector + is + begin + return inp(upper downto lower); + end; + + -- signed slice + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- unsigned slice + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); + end; + + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); + end; + + function boolean_to_signed (inp : boolean; width : integer) + return signed + is + variable result : signed(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_unsigned (inp : boolean; width : integer) + return unsigned + is + variable result : unsigned(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_vector (inp : boolean) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function std_logic_to_vector (inp : std_logic) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result(0) := inp; + return result; + end; + + --------------------------------------------------------------------------- + -- Quantization Functions + --------------------------------------------------------------------------- + + -- Truncate LSB bits + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign Extent or zero extend if necessary + if new_arith = xlUnsigned then + result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); + else + result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + result := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + result := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + return result; + end; + + + -- Round towards infinity + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + if (new_arith = xlSigned) then + -- Roundeing logic for signed numbers + -- Example: + -- Fix(5,-2) = 101.11 (bin) -2.25 (dec) + -- Converted to: Fix(4,-1) = 101.1 (bin) -2.5 (dec) + -- Note: same algorithm used for unsigned numbers can't be used. + + -- 1st check the sign bit of the input to see if it is a positive + -- number + if (vec(old_width-1) = '0') then + one_or_zero(0) := '1'; + end if; + + -- 2nd check if digits being truncated are all zeros + -- (in example it is bit zero) + if (right_of_dp >= 2) and (right_of_dp <= old_width) then + if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then + one_or_zero(0) := '1'; + end if; + end if; + + -- 3rd check if the bit right before the truncation point is '1' + -- or '0' (in example it is bit one) + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if vec(right_of_dp-1) = '0' then + one_or_zero(0) := '0'; + end if; + else + -- No rounding to be performed + one_or_zero(0) := '0'; + end if; + else + -- For an unsigned number just check if the bit right before the + -- truncation point is '1' or '0' + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + one_or_zero(0) := vec(right_of_dp-1); + end if; + end if; + + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + -- Round towards even values + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + -- For the truncated bits just check if the bits after the + -- truncation point are 0.5 + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then + one_or_zero(0) := vec(right_of_dp-1); + else + one_or_zero(0) := vec(right_of_dp); + end if; + end if; + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + --------------------------------------------------------------------------- + -- Overflow Functions + --------------------------------------------------------------------------- + + -- Apply Saturation arithmetic. The new_bin_pt and old bin_pt should be + -- equal. The function chops bits off MSB bits. + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (old_width - old_bin_pt) - + (new_width - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable overflow : boolean; + begin + vec := inp; + overflow := true; + result := (others => '0'); + + ----------------------------------------------------------------------- + -- Check for cases when overflow does not occur + ----------------------------------------------------------------------- + + -- Output width is >= input width + if (new_width >= old_width) then + overflow := false; + end if; + + -- Case #1: + -- Both the input and output are signed and the bits that will + -- be truncated plus the sign bit are all the same + -- (i.e., number has been sign extended) + if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + -- Case #2: + -- If the input is converted to a unsigned from an signed then only + -- check the bits that will be truncated are all zero + if (old_arith = xlSigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + -- Check if input is positive + if (vec(new_width-1) = '0') then + overflow := false; + end if; + end if; + end if; + end if; + + -- Case #3: + -- Input is unsigned and the bits that will be truncated are all zero + if (old_arith = xlUnsigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + overflow := false; + end if; + end if; + end if; + + -- Case #4: + -- Input is unsigned but output signed and the bits that will be + -- truncated are all zero + if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + + if overflow then + -- Overflow occured + if new_arith = xlSigned then + -- Check sign bit and set to max signed or min signed value + if vec(old_width-1) = '0' then + result := max_signed(new_width); + else + result := min_signed(new_width); + end if; + else + -- Check sign bit and set to zero if negative + if ((old_arith = xlSigned) and vec(old_width-1) = '1') then + result := (others => '0'); + else + -- Set to max unsigned positive value + result := (others => '1'); + end if; + end if; + else + -- Overflow did not occur + + -- Check for case when input type is signed and output type + -- unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + -- if negative number set vec to zero + if (vec(old_width-1) = '1') then + vec := (others => '0'); + end if; + end if; + + if new_width <= old_width then + result := vec(new_width-1 downto 0); + else + -- Sign or zero extend number depending on arith of new number + if new_arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + end if; + end if; + + return result; + end; + + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + variable result_arith : integer; + begin + -- Check for case when input type is signed and output type unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + result_arith := xlSigned; + end if; + + result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); + + return result; + end; + + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is + begin + return max(a_bin_pt, b_bin_pt); + end; + + -- Returns the number of integer bits after alignment of fixed point num + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER is + begin + return max(a_width - a_bin_pt, b_width - b_bin_pt); + end; + + function pad_LSB(inp : std_logic_vector; new_width: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + -- Added for XST + constant pad_pos : integer := new_width - orig_width - 1; + + begin + vec := inp; + pos := new_width-1; + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pad_pos >= 0 then + for i in pad_pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + -- sign extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := vec(old_width-1); + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + -- zero extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := '0'; + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + begin + result(0) := inp; + for i in new_width-1 downto 1 loop + result(i) := '0'; + end loop; + + return result; + end; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + return result; + end; + + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + begin + vec := inp; + pos := new_width-1; + + if (arith = xlUnsigned) then + -- set MSB to zero + result(pos) := '0'; + pos := pos - 1; + else + -- sign extend + result(pos) := vec(orig_width-1); + pos := pos - 1; + end if; + + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pos >= 0 then + for i in pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector + is + variable vec : std_logic_vector(old_width-1 downto 0); + variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if delta > 0 then + padded_inp := pad_LSB(vec, old_width+delta); + + -- sign or zero extend zero padded input depending on arith type + result := extend_MSB(padded_inp, new_width, new_arith); + else + -- sign or zero extend input depending on arith type + result := extend_MSB(vec, new_width, new_arith); + end if; + + return result; + end; + + function max(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + function min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean is +-- constant NULL_Str : string := ""; + begin + if (left'length /= right'length) then + return false; + else + -- Check for NULL string + -- FPGA Express does not like empty strings +-- if (left'length = NULL_Str'length) or +-- (right'length = NULL_Str'length) then +-- return true; +-- end if; + test : for i in 1 to left'length loop + if left(i) /= right(i) then + return false; + end if; + end loop test; + return true; + end if; + end; + + + --------------------------------------------------------------------------- + -- Debugging and Simulation only functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's + function is_binary_string_invalid (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'X' ) then + result := true; + end if; + end loop; + return result; + end; + + -- Check for all U's + function is_binary_string_undefined (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'U' ) then + result := true; + end if; + end loop; + return result; + end; + + + + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + result := false; + for i in 0 to width-1 loop + if (vec(i) = 'U') or (vec(i) = 'X') then + result := true; + end if; + end loop; + return result; + end; + + -- Converts a std_logic_vector to a real + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real + is + variable vec : std_logic_vector(inp'length-1 downto 0); + variable result, shift_val, undefined_real : real; + variable neg_num : boolean; + begin + vec := inp; + result := 0.0; + neg_num := false; + if vec(inp'length-1) = '1' then + neg_num := true; + end if; + + for i in 0 to inp'length-1 loop + if vec(i) = 'U' or vec(i) = 'X' then + return undefined_real; + end if; + if arith = xlSigned then + if neg_num then + -- Perform 1's count if negative number + if vec(i) = '0' then + result := result + 2.0**i; + end if; + else + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + else + -- Unsigned numbers + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + end loop; + + if arith = xlSigned then + if neg_num then + -- Add one to 1's comp number to make 2's comp number + result := result + 1.0; + result := result * (-1.0); + end if; + end if; + -- Realign based on binary point + shift_val := 2.0**(-1*bin_pt); + result := result * shift_val; + return result; + end; + + -- This function is just for consistancy + -- bin_pt and arith not used. + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real + is + variable result : real := 0.0; + begin + if inp = '1' then + result := 1.0; + end if; + + if arith = xlSigned then + assert false + report "It doesn't make sense to convert a 1 bit number to a signed real."; + end if; + return result; + end; + + -- synthesis translate_on + -- Convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + begin + + if (arith = xlSigned) then + signed_val := to_signed(inp, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(inp, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- Convert an std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer + is + constant width : integer := inp'length; + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + variable result : integer; + begin + + if (arith = xlSigned) then + signed_val := std_logic_vector_to_signed(inp); + result := to_integer(signed_val); + else + unsigned_val := std_logic_vector_to_unsigned(inp); + result := to_integer(unsigned_val); + end if; + + return result; + end; + + function std_logic_to_integer(constant inp : std_logic := '0') + return integer + is + begin + if inp = '1' then + return 1; + else + return 0; + end if; + end; + + + function makeZeroBinStr (width : integer) return STRING is + variable result : string(1 to width+3); + begin + result(1) := '0'; + result(2) := 'b'; + for i in 3 to width+2 loop + result(i) := '0'; + end loop; -- i + result(width+3) := '.'; + + return result; + end; + + + + -- synthesis translate_off + -- Convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + begin + --result := to_std_logic_vector(real'value(inp), width, bin_pt, arith); + result := (others => '0'); + return result; + end; + + -- Convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector + is + variable real_val : real; + variable int_val : integer; + variable result : std_logic_vector(width-1 downto 0) := (others => '0'); + variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); + variable signed_val : signed(width-1 downto 0) := (others => '0'); + begin + + real_val := inp; + + -- Scale double and make it an integer + int_val := integer(real_val * 2.0**(bin_pt)); + + if (arith = xlSigned) then + signed_val := to_signed(int_val, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(int_val, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- synthesis translate_on + -- Check of 0b and the beginning of a string + function valid_bin_string (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + begin + vec := inp; + if (vec(1) = '0' and vec(2) = 'b') then + return true; + else + return false; + end if; + end; + + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector(inp: string; width : integer) + return std_logic_vector is + + constant strlen : integer := inp'LENGTH; + variable result : std_logic_vector(width-1 downto 0); + variable bitval : std_logic_vector((strlen*4)-1 downto 0); + variable posn : integer; + variable ch : character; + variable vec : string(1 to strlen); + begin + vec := inp; + + -- default value is zero + result := (others => '0'); + posn := (strlen*4)-1; + + for i in 1 to strlen loop + ch := vec(i); + case ch is + when '0' => bitval(posn downto posn-3) := "0000"; + when '1' => bitval(posn downto posn-3) := "0001"; + when '2' => bitval(posn downto posn-3) := "0010"; + when '3' => bitval(posn downto posn-3) := "0011"; + when '4' => bitval(posn downto posn-3) := "0100"; + when '5' => bitval(posn downto posn-3) := "0101"; + when '6' => bitval(posn downto posn-3) := "0110"; + when '7' => bitval(posn downto posn-3) := "0111"; + when '8' => bitval(posn downto posn-3) := "1000"; + when '9' => bitval(posn downto posn-3) := "1001"; + when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; + when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; + when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; + when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; + when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; + when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; + when others => bitval(posn downto posn-3) := "XXXX"; + -- synthesis translate_off + ASSERT false + REPORT "Invalid hex value" SEVERITY ERROR; + -- synthesis translate_on + end case; + posn := posn - 4; + end loop; + + if (width <= strlen*4) then + -- bitval larger than desired width + result := bitval(width-1 downto 0); + else + -- bitval smaller than desired width + -- MSB is padded with zeros since default value for result is all 0s + result((strlen*4)-1 downto 0) := bitval; + end if; + return result; + end; + + + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector + is + variable pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(inp'length-1 downto 0); + begin + vec := inp; + pos := inp'length-1; + -- Set default value + result := (others => '0'); + + for i in 1 to vec'length loop + -- synthesis translate_off + if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then + assert false + report "Input string is larger than output std_logic_vector. Truncating output."; + return result; + end if; + -- synthesis translate_on + + if vec(i) = '0' then + result(pos) := '0'; + pos := pos - 1; + end if; + if vec(i) = '1' then + result(pos) := '1'; + pos := pos - 1; + end if; + -- synthesis translate_off + if (vec(i) = 'X' or vec(i) = 'U') then + result(pos) := 'U'; + pos := pos - 1; + end if; + -- synthesis translate_on + end loop; + return result; + end; + + + -- Convert a binary string array element into a std_logic_vector + -- Example "0b000.0000000 0b001.0000000" + -- string_pos: 123456789111111111122222222 + -- 012345678901234567 + -- + -- "0b000.0000000" = inp(0) + -- "0b001.0000000" = inp(1) + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector + is + constant str_width : integer := width + 4; -- +4 for '0b' '.' & ' ' + constant inp_len : integer := inp'length; + constant num_elements : integer := (inp_len + 1)/str_width; + constant reverse_index : integer := (num_elements-1) - index; + + -- Calc position of desired str + variable left_pos : integer; + variable right_pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(width-1 downto 0); + begin + -- Can't pad input with a space (Synplicity crashes) + vec := inp; + + -- Set default value + result := (others => '0'); + + -- Special Case for string like "0b01.0" without extra ' ' after string + if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := 1; + right_pos := width + 3; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := (reverse_index * str_width) + 1; + right_pos := left_pos + width + 2; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + return result; + end; + -- synthesis translate_off + + -- + -- convert a std_logic_vector to a string + -- + function std_logic_vector_to_bin_string(inp : std_logic_vector) + return string + is + variable vec : std_logic_vector(1 to inp'length); + variable result : string(vec'range); + begin + vec := inp; + for i in vec'range loop + result(i) := to_char(vec(i)); + end loop; + return result; + end; + + -- + -- convert a std_logic to a string + -- + function std_logic_to_bin_string(inp : std_logic) + return string + is + variable result : string(1 to 3); + begin + -- Add 0b prefix + result(1) := '0'; + result(2) := 'b'; + result(3) := to_char(inp); + return result; + end; + + -- + -- convert a std_logic_vector to a string and add a binary point + -- + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string + is + variable width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable str_pos : integer; + variable result : string(1 to width+3); + begin + vec := inp; + -- Add 0b prefeix + str_pos := 1; + result(str_pos) := '0'; + str_pos := 2; + result(str_pos) := 'b'; + str_pos := 3; + for i in width-1 downto 0 loop + -- Insert decimal point + -- if i = (width - bin_pt + 1) then + if (((width+3) - bin_pt) = str_pos) then + result(str_pos) := '.'; + str_pos := str_pos + 1; + end if; + result(str_pos) := to_char(vec(i)); + str_pos := str_pos + 1; + end loop; + -- Add binary point at end of string when bin_pt = 0 + if (bin_pt = 0) then + result(str_pos) := '.'; + end if; + + return result; + end; + + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string + is + variable result : string(1 to width); + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := real_to_std_logic_vector(inp, width, bin_pt, arith); + result := std_logic_vector_to_bin_string(vec); + + return result; + end; + + + -- Convert a real to string + -- Note: the size of the string returned is 'display_precision' chars long + function real_to_string (inp : real) return string + is + variable result : string(1 to display_precision) := (others => ' '); + begin + result(real'image(inp)'range) := real'image(inp); + return result; + end; + + -- synthesis translate_on + + +end conv_pkg; + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/single_reg_w_init.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/single_reg_w_init.vhd new file mode 100644 index 0000000..26af1d6 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/single_reg_w_init.vhd @@ -0,0 +1,109 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : single_reg_w_init.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg_w_init.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity single_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end single_reg_w_init; + +architecture structural of single_reg_w_init is + function build_init_const(width: integer; + init_index: integer; + init_value: bit_vector) + return std_logic_vector + is + variable result: std_logic_vector(width - 1 downto 0); + begin + if init_index = 0 then + result := (others => '0'); + elsif init_index = 1 then + result := (others => '0'); + result(0) := '1'; + else + result := to_stdlogicvector(init_value); + end if; + return result; + end; + + component fdre + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + r: in std_ulogic + ); + end component; -- end fdre + attribute syn_black_box of fdre: component is true; + attribute fpga_dont_touch of fdre: component is "true"; + + component fdse + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + s: in std_ulogic + ); + end component; -- end fdse + attribute syn_black_box of fdse: component is true; + attribute fpga_dont_touch of fdse: component is "true"; + + constant init_const: std_logic_vector(width - 1 downto 0) + := build_init_const(width, init_index, init_value); +begin + fd_prim_array: for index in 0 to width - 1 generate + + bit_is_0: if (init_const(index) = '0') generate + fdre_comp: fdre + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + r => clr + ); + end generate; -- end bit_is_0 + + bit_is_1: if (init_const(index) = '1') generate + fdse_comp: fdse + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + s => clr + ); + end generate; -- end bit_is_1 + end generate; -- end fd_prim_array +end architecture structural; + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/srl17e.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/srl17e.vhd new file mode 100644 index 0000000..8ec9c8d --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/srl17e.vhd @@ -0,0 +1,93 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srl17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srl17e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srl17e; + +architecture structural of srl17e is + + component SRL16E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRL16E : component is true; + attribute fpga_dont_touch of SRL16E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srl16_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srl16_used: if latency > 1 generate + u1 : srl16e port map(clk => clk, + d => d_delayed(i), + q => srl16_out(i), + ce => ce, + a0 => a(0), + a1 => a(1), + a2 => a(2), + a3 => a(3)); + end generate; + srl16_not_used: if latency <= 1 generate + srl16_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srl16_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srl16_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/srl33e.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/srl33e.vhd new file mode 100644 index 0000000..c943462 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/srl33e.vhd @@ -0,0 +1,87 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srlc17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srlc33e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srlc33e; + +architecture structural of srlc33e is + + component SRLC32E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A : in std_logic_vector(4 downto 0); + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRLC32E : component is true; + attribute fpga_dont_touch of SRLC32E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srlc32_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srlc32_used: if latency > 1 generate + u1 : srlc32e port map(clk => clk, + d => d_delayed(i), + q => srlc32_out(i), + ce => ce, + a => a); + end generate; + srlc32_not_used: if latency <= 1 generate + srlc32_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srlc32_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srlc32_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8.vhd new file mode 100644 index 0000000..47cdad1 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8.vhd @@ -0,0 +1,2133 @@ +-- Generated from Simulink block ssr_8x8/Vector FFT/Scalar2Vector +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_scalar2vector is + port ( + i : in std_logic_vector( 432-1 downto 0 ); + o_1 : out std_logic_vector( 54-1 downto 0 ); + o_2 : out std_logic_vector( 54-1 downto 0 ); + o_3 : out std_logic_vector( 54-1 downto 0 ); + o_4 : out std_logic_vector( 54-1 downto 0 ); + o_5 : out std_logic_vector( 54-1 downto 0 ); + o_6 : out std_logic_vector( 54-1 downto 0 ); + o_7 : out std_logic_vector( 54-1 downto 0 ); + o_8 : out std_logic_vector( 54-1 downto 0 ) + ); +end ssr_8x8_scalar2vector; +architecture structural of ssr_8x8_scalar2vector is + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); +begin + o_1 <= slice0_y_net; + o_2 <= slice1_y_net; + o_3 <= slice2_y_net; + o_4 <= slice3_y_net; + o_5 <= slice4_y_net; + o_6 <= slice5_y_net; + o_7 <= slice6_y_net; + o_8 <= slice7_y_net; + test_systolicfft_vhdl_black_box_o_net <= i; + slice0 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 0, + new_msb => 53, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice0_y_net + ); + slice1 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 54, + new_msb => 107, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice1_y_net + ); + slice2 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 108, + new_msb => 161, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice2_y_net + ); + slice3 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 162, + new_msb => 215, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice3_y_net + ); + slice4 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 216, + new_msb => 269, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice4_y_net + ); + slice5 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 270, + new_msb => 323, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice5_y_net + ); + slice6 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 324, + new_msb => 377, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice6_y_net + ); + slice7 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 378, + new_msb => 431, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT/Vector Concat +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector_concat is + port ( + hi_1 : in std_logic_vector( 16-1 downto 0 ); + lo_1 : in std_logic_vector( 16-1 downto 0 ); + hi_2 : in std_logic_vector( 16-1 downto 0 ); + hi_3 : in std_logic_vector( 16-1 downto 0 ); + hi_4 : in std_logic_vector( 16-1 downto 0 ); + hi_5 : in std_logic_vector( 16-1 downto 0 ); + hi_6 : in std_logic_vector( 16-1 downto 0 ); + hi_7 : in std_logic_vector( 16-1 downto 0 ); + hi_8 : in std_logic_vector( 16-1 downto 0 ); + lo_2 : in std_logic_vector( 16-1 downto 0 ); + lo_3 : in std_logic_vector( 16-1 downto 0 ); + lo_4 : in std_logic_vector( 16-1 downto 0 ); + lo_5 : in std_logic_vector( 16-1 downto 0 ); + lo_6 : in std_logic_vector( 16-1 downto 0 ); + lo_7 : in std_logic_vector( 16-1 downto 0 ); + lo_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 32-1 downto 0 ); + out_2 : out std_logic_vector( 32-1 downto 0 ); + out_3 : out std_logic_vector( 32-1 downto 0 ); + out_4 : out std_logic_vector( 32-1 downto 0 ); + out_5 : out std_logic_vector( 32-1 downto 0 ); + out_6 : out std_logic_vector( 32-1 downto 0 ); + out_7 : out std_logic_vector( 32-1 downto 0 ); + out_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x8_vector_concat; +architecture structural of ssr_8x8_vector_concat is + signal reinterpret6_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= concat0_y_net; + out_2 <= concat1_y_net; + out_3 <= concat2_y_net; + out_4 <= concat3_y_net; + out_5 <= concat4_y_net; + out_6 <= concat5_y_net; + out_7 <= concat6_y_net; + out_8 <= concat7_y_net; + reinterpret0_output_port_net_x0 <= hi_1; + reinterpret0_output_port_net <= lo_1; + reinterpret1_output_port_net_x0 <= hi_2; + reinterpret2_output_port_net_x0 <= hi_3; + reinterpret3_output_port_net_x0 <= hi_4; + reinterpret4_output_port_net_x0 <= hi_5; + reinterpret5_output_port_net_x0 <= hi_6; + reinterpret6_output_port_net_x0 <= hi_7; + reinterpret7_output_port_net_x0 <= hi_8; + reinterpret1_output_port_net <= lo_2; + reinterpret2_output_port_net <= lo_3; + reinterpret3_output_port_net <= lo_4; + reinterpret4_output_port_net <= lo_5; + reinterpret5_output_port_net <= lo_6; + reinterpret6_output_port_net <= lo_7; + reinterpret7_output_port_net <= lo_8; + concat0 : entity xil_defaultlib.sysgen_concat_965a32611a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret0_output_port_net_x0, + in1 => reinterpret0_output_port_net, + y => concat0_y_net + ); + concat1 : entity xil_defaultlib.sysgen_concat_965a32611a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret1_output_port_net_x0, + in1 => reinterpret1_output_port_net, + y => concat1_y_net + ); + concat2 : entity xil_defaultlib.sysgen_concat_965a32611a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret2_output_port_net_x0, + in1 => reinterpret2_output_port_net, + y => concat2_y_net + ); + concat3 : entity xil_defaultlib.sysgen_concat_965a32611a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret3_output_port_net_x0, + in1 => reinterpret3_output_port_net, + y => concat3_y_net + ); + concat4 : entity xil_defaultlib.sysgen_concat_965a32611a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret4_output_port_net_x0, + in1 => reinterpret4_output_port_net, + y => concat4_y_net + ); + concat5 : entity xil_defaultlib.sysgen_concat_965a32611a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret5_output_port_net_x0, + in1 => reinterpret5_output_port_net, + y => concat5_y_net + ); + concat6 : entity xil_defaultlib.sysgen_concat_965a32611a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret6_output_port_net_x0, + in1 => reinterpret6_output_port_net, + y => concat6_y_net + ); + concat7 : entity xil_defaultlib.sysgen_concat_965a32611a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret7_output_port_net_x0, + in1 => reinterpret7_output_port_net, + y => concat7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT/Vector Delay +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector_delay is + port ( + d_1 : in std_logic_vector( 32-1 downto 0 ); + d_2 : in std_logic_vector( 32-1 downto 0 ); + d_3 : in std_logic_vector( 32-1 downto 0 ); + d_4 : in std_logic_vector( 32-1 downto 0 ); + d_5 : in std_logic_vector( 32-1 downto 0 ); + d_6 : in std_logic_vector( 32-1 downto 0 ); + d_7 : in std_logic_vector( 32-1 downto 0 ); + d_8 : in std_logic_vector( 32-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + q_1 : out std_logic_vector( 32-1 downto 0 ); + q_2 : out std_logic_vector( 32-1 downto 0 ); + q_3 : out std_logic_vector( 32-1 downto 0 ); + q_4 : out std_logic_vector( 32-1 downto 0 ); + q_5 : out std_logic_vector( 32-1 downto 0 ); + q_6 : out std_logic_vector( 32-1 downto 0 ); + q_7 : out std_logic_vector( 32-1 downto 0 ); + q_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x8_vector_delay; +architecture structural of ssr_8x8_vector_delay is + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal ce_net : std_logic; + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal clk_net : std_logic; + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); +begin + q_1 <= delay0_q_net; + q_2 <= delay1_q_net; + q_3 <= delay2_q_net; + q_4 <= delay3_q_net; + q_5 <= delay4_q_net; + q_6 <= delay5_q_net; + q_7 <= delay6_q_net; + q_8 <= delay7_q_net; + concat0_y_net <= d_1; + concat1_y_net <= d_2; + concat2_y_net <= d_3; + concat3_y_net <= d_4; + concat4_y_net <= d_5; + concat5_y_net <= d_6; + concat6_y_net <= d_7; + concat7_y_net <= d_8; + clk_net <= clk_1; + ce_net <= ce_1; + delay0 : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat0_y_net, + clk => clk_net, + ce => ce_net, + q => delay0_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat1_y_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net + ); + delay2 : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat2_y_net, + clk => clk_net, + ce => ce_net, + q => delay2_q_net + ); + delay3 : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat3_y_net, + clk => clk_net, + ce => ce_net, + q => delay3_q_net + ); + delay4 : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat4_y_net, + clk => clk_net, + ce => ce_net, + q => delay4_q_net + ); + delay5 : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat5_y_net, + clk => clk_net, + ce => ce_net, + q => delay5_q_net + ); + delay6 : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat6_y_net, + clk => clk_net, + ce => ce_net, + q => delay6_q_net + ); + delay7 : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat7_y_net, + clk => clk_net, + ce => ce_net, + q => delay7_q_net + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT/Vector Reinterpret +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector_reinterpret is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x8_vector_reinterpret; +architecture structural of ssr_8x8_vector_reinterpret is + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_re_0_net <= in_1; + i_re_1_net <= in_2; + i_re_2_net <= in_3; + i_re_3_net <= in_4; + i_re_4_net <= in_5; + i_re_5_net <= in_6; + i_re_6_net <= in_7; + i_re_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT/Vector Reinterpret1 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector_reinterpret1 is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x8_vector_reinterpret1; +architecture structural of ssr_8x8_vector_reinterpret1 is + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_im_0_net <= in_1; + i_im_1_net <= in_2; + i_im_2_net <= in_3; + i_im_3_net <= in_4; + i_im_4_net <= in_5; + i_im_5_net <= in_6; + i_im_6_net <= in_7; + i_im_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_d1aaeed629 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT/Vector Reinterpret2 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector_reinterpret2 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x8_vector_reinterpret2; +architecture structural of ssr_8x8_vector_reinterpret2 is + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT/Vector Reinterpret3 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector_reinterpret3 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x8_vector_reinterpret3; +architecture structural of ssr_8x8_vector_reinterpret3 is + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_4035468568 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT/Vector Slice Im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector_slice_im is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x8_vector_slice_im; +architecture structural of ssr_8x8_vector_slice_im is + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT/Vector Slice Re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector_slice_re is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x8_vector_slice_re; +architecture structural of ssr_8x8_vector_slice_re is + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x8_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT/Vector2Scalar +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector2scalar is + port ( + i_1 : in std_logic_vector( 32-1 downto 0 ); + i_2 : in std_logic_vector( 32-1 downto 0 ); + i_3 : in std_logic_vector( 32-1 downto 0 ); + i_4 : in std_logic_vector( 32-1 downto 0 ); + i_5 : in std_logic_vector( 32-1 downto 0 ); + i_6 : in std_logic_vector( 32-1 downto 0 ); + i_7 : in std_logic_vector( 32-1 downto 0 ); + i_8 : in std_logic_vector( 32-1 downto 0 ); + o : out std_logic_vector( 256-1 downto 0 ) + ); +end ssr_8x8_vector2scalar; +architecture structural of ssr_8x8_vector2scalar is + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); +begin + o <= concat1_y_net; + delay0_q_net <= i_1; + delay1_q_net <= i_2; + delay2_q_net <= i_3; + delay3_q_net <= i_4; + delay4_q_net <= i_5; + delay5_q_net <= i_6; + delay6_q_net <= i_7; + delay7_q_net <= i_8; + concat1 : entity xil_defaultlib.sysgen_concat_7ca5184bef + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => delay7_q_net, + in1 => delay6_q_net, + in2 => delay5_q_net, + in3 => delay4_q_net, + in4 => delay3_q_net, + in5 => delay2_q_net, + in6 => delay1_q_net, + in7 => delay0_q_net, + y => concat1_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x8/Vector FFT +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_vector_fft is + port ( + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + vi : in std_logic_vector( 1-1 downto 0 ); + si : in std_logic_vector( 3-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_8 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_8 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + vo : out std_logic; + so : out std_logic_vector( 3-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_8 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x8_vector_fft; +architecture structural of ssr_8x8_vector_fft is + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret4_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal delay_q_net : std_logic_vector( 1-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice2_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal reinterpret7_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret6_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret1_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice3_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal reinterpret6_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice7_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal concat1_y_net_x0 : std_logic_vector( 32-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret3_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal delay1_q_net_x0 : std_logic_vector( 3-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_vo_net : std_logic; + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 3-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal clk_net : std_logic; + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal slice0_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal slice1_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_scale_net : std_logic_vector( 3-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal ce_net : std_logic; + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); +begin + o_re_1 <= reinterpret0_output_port_net_x0; + o_im_1 <= reinterpret0_output_port_net; + vo <= test_systolicfft_vhdl_black_box_vo_net; + so <= test_systolicfft_vhdl_black_box_so_net; + o_re_2 <= reinterpret1_output_port_net_x0; + o_re_3 <= reinterpret2_output_port_net_x0; + o_re_4 <= reinterpret3_output_port_net_x0; + o_re_5 <= reinterpret4_output_port_net_x0; + o_re_6 <= reinterpret5_output_port_net_x0; + o_re_7 <= reinterpret6_output_port_net_x0; + o_re_8 <= reinterpret7_output_port_net_x0; + o_im_2 <= reinterpret1_output_port_net; + o_im_3 <= reinterpret2_output_port_net; + o_im_4 <= reinterpret3_output_port_net; + o_im_5 <= reinterpret4_output_port_net; + o_im_6 <= reinterpret5_output_port_net; + o_im_7 <= reinterpret6_output_port_net; + o_im_8 <= reinterpret7_output_port_net; + i_re_0_net <= i_re_1; + i_im_0_net <= i_im_1; + i_valid_net <= vi; + i_scale_net <= si; + i_re_1_net <= i_re_2; + i_re_2_net <= i_re_3; + i_re_3_net <= i_re_4; + i_re_4_net <= i_re_5; + i_re_5_net <= i_re_6; + i_re_6_net <= i_re_7; + i_re_7_net <= i_re_8; + i_im_1_net <= i_im_2; + i_im_2_net <= i_im_3; + i_im_3_net <= i_im_4; + i_im_4_net <= i_im_5; + i_im_5_net <= i_im_6; + i_im_6_net <= i_im_7; + i_im_7_net <= i_im_8; + clk_net <= clk_1; + ce_net <= ce_1; + scalar2vector : entity xil_defaultlib.ssr_8x8_scalar2vector + port map ( + i => test_systolicfft_vhdl_black_box_o_net, + o_1 => slice0_y_net_x1, + o_2 => slice1_y_net_x1, + o_3 => slice2_y_net_x1, + o_4 => slice3_y_net_x1, + o_5 => slice4_y_net_x1, + o_6 => slice5_y_net_x1, + o_7 => slice6_y_net_x1, + o_8 => slice7_y_net_x1 + ); + vector_concat : entity xil_defaultlib.ssr_8x8_vector_concat + port map ( + hi_1 => reinterpret0_output_port_net_x1, + lo_1 => reinterpret0_output_port_net_x2, + hi_2 => reinterpret1_output_port_net_x1, + hi_3 => reinterpret2_output_port_net_x1, + hi_4 => reinterpret3_output_port_net_x1, + hi_5 => reinterpret4_output_port_net_x1, + hi_6 => reinterpret5_output_port_net_x1, + hi_7 => reinterpret6_output_port_net_x1, + hi_8 => reinterpret7_output_port_net_x1, + lo_2 => reinterpret1_output_port_net_x2, + lo_3 => reinterpret2_output_port_net_x2, + lo_4 => reinterpret3_output_port_net_x2, + lo_5 => reinterpret4_output_port_net_x2, + lo_6 => reinterpret5_output_port_net_x2, + lo_7 => reinterpret6_output_port_net_x2, + lo_8 => reinterpret7_output_port_net_x2, + out_1 => concat0_y_net, + out_2 => concat1_y_net_x0, + out_3 => concat2_y_net, + out_4 => concat3_y_net, + out_5 => concat4_y_net, + out_6 => concat5_y_net, + out_7 => concat6_y_net, + out_8 => concat7_y_net + ); + vector_delay : entity xil_defaultlib.ssr_8x8_vector_delay + port map ( + d_1 => concat0_y_net, + d_2 => concat1_y_net_x0, + d_3 => concat2_y_net, + d_4 => concat3_y_net, + d_5 => concat4_y_net, + d_6 => concat5_y_net, + d_7 => concat6_y_net, + d_8 => concat7_y_net, + clk_1 => clk_net, + ce_1 => ce_net, + q_1 => delay0_q_net, + q_2 => delay1_q_net, + q_3 => delay2_q_net, + q_4 => delay3_q_net, + q_5 => delay4_q_net, + q_6 => delay5_q_net, + q_7 => delay6_q_net, + q_8 => delay7_q_net + ); + vector_reinterpret : entity xil_defaultlib.ssr_8x8_vector_reinterpret + port map ( + in_1 => i_re_0_net, + in_2 => i_re_1_net, + in_3 => i_re_2_net, + in_4 => i_re_3_net, + in_5 => i_re_4_net, + in_6 => i_re_5_net, + in_7 => i_re_6_net, + in_8 => i_re_7_net, + out_1 => reinterpret0_output_port_net_x2, + out_2 => reinterpret1_output_port_net_x2, + out_3 => reinterpret2_output_port_net_x2, + out_4 => reinterpret3_output_port_net_x2, + out_5 => reinterpret4_output_port_net_x2, + out_6 => reinterpret5_output_port_net_x2, + out_7 => reinterpret6_output_port_net_x2, + out_8 => reinterpret7_output_port_net_x2 + ); + vector_reinterpret1 : entity xil_defaultlib.ssr_8x8_vector_reinterpret1 + port map ( + in_1 => i_im_0_net, + in_2 => i_im_1_net, + in_3 => i_im_2_net, + in_4 => i_im_3_net, + in_5 => i_im_4_net, + in_6 => i_im_5_net, + in_7 => i_im_6_net, + in_8 => i_im_7_net, + out_1 => reinterpret0_output_port_net_x1, + out_2 => reinterpret1_output_port_net_x1, + out_3 => reinterpret2_output_port_net_x1, + out_4 => reinterpret3_output_port_net_x1, + out_5 => reinterpret4_output_port_net_x1, + out_6 => reinterpret5_output_port_net_x1, + out_7 => reinterpret6_output_port_net_x1, + out_8 => reinterpret7_output_port_net_x1 + ); + vector_reinterpret2 : entity xil_defaultlib.ssr_8x8_vector_reinterpret2 + port map ( + in_1 => slice0_y_net, + in_2 => slice1_y_net, + in_3 => slice2_y_net, + in_4 => slice3_y_net, + in_5 => slice4_y_net, + in_6 => slice5_y_net, + in_7 => slice6_y_net, + in_8 => slice7_y_net, + out_1 => reinterpret0_output_port_net_x0, + out_2 => reinterpret1_output_port_net_x0, + out_3 => reinterpret2_output_port_net_x0, + out_4 => reinterpret3_output_port_net_x0, + out_5 => reinterpret4_output_port_net_x0, + out_6 => reinterpret5_output_port_net_x0, + out_7 => reinterpret6_output_port_net_x0, + out_8 => reinterpret7_output_port_net_x0 + ); + vector_reinterpret3 : entity xil_defaultlib.ssr_8x8_vector_reinterpret3 + port map ( + in_1 => slice0_y_net_x0, + in_2 => slice1_y_net_x0, + in_3 => slice2_y_net_x0, + in_4 => slice3_y_net_x0, + in_5 => slice4_y_net_x0, + in_6 => slice5_y_net_x0, + in_7 => slice6_y_net_x0, + in_8 => slice7_y_net_x0, + out_1 => reinterpret0_output_port_net, + out_2 => reinterpret1_output_port_net, + out_3 => reinterpret2_output_port_net, + out_4 => reinterpret3_output_port_net, + out_5 => reinterpret4_output_port_net, + out_6 => reinterpret5_output_port_net, + out_7 => reinterpret6_output_port_net, + out_8 => reinterpret7_output_port_net + ); + vector_slice_im : entity xil_defaultlib.ssr_8x8_vector_slice_im + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net_x0, + out_2 => slice1_y_net_x0, + out_3 => slice2_y_net_x0, + out_4 => slice3_y_net_x0, + out_5 => slice4_y_net_x0, + out_6 => slice5_y_net_x0, + out_7 => slice6_y_net_x0, + out_8 => slice7_y_net_x0 + ); + vector_slice_re : entity xil_defaultlib.ssr_8x8_vector_slice_re + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net, + out_2 => slice1_y_net, + out_3 => slice2_y_net, + out_4 => slice3_y_net, + out_5 => slice4_y_net, + out_6 => slice5_y_net, + out_7 => slice6_y_net, + out_8 => slice7_y_net + ); + vector2scalar : entity xil_defaultlib.ssr_8x8_vector2scalar + port map ( + i_1 => delay0_q_net, + i_2 => delay1_q_net, + i_3 => delay2_q_net, + i_4 => delay3_q_net, + i_5 => delay4_q_net, + i_6 => delay5_q_net, + i_7 => delay6_q_net, + i_8 => delay7_q_net, + o => concat1_y_net + ); + delay : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 1 + ) + port map ( + en => '1', + rst => '0', + d => i_valid_net, + clk => clk_net, + ce => ce_net, + q => delay_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x8_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 3 + ) + port map ( + en => '1', + rst => '0', + d => i_scale_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net_x0 + ); + test_systolicfft_vhdl_black_box : entity xil_defaultlib.WRAPPER_VECTOR_FFT_29450ae4dbd3eb51515dab58c9ac6776 + generic map ( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 3, + N => 8, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map ( + i => concat1_y_net, + vi => delay_q_net(0), + si => delay1_q_net_x0, + CLK => clk_net, + CE => ce_net, + o => test_systolicfft_vhdl_black_box_o_net, + vo => test_systolicfft_vhdl_black_box_vo_net, + so => test_systolicfft_vhdl_black_box_so_net + ); +end structural; +-- Generated from Simulink block ssr_8x8/i_im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_i_im is + port ( + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x8_i_im; +architecture structural of ssr_8x8_i_im is + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); +begin + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; +end structural; +-- Generated from Simulink block ssr_8x8/i_re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_i_re is + port ( + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x8_i_re; +architecture structural of ssr_8x8_i_re is + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); +begin + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; +end structural; +-- Generated from Simulink block ssr_8x8_struct +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_struct is + port ( + i_scale : in std_logic_vector( 3-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_scale : out std_logic_vector( 3-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x8_struct; +architecture structural of ssr_8x8_struct is + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal ce_net : std_logic; + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal clk_net : std_logic; + signal i_scale_net : std_logic_vector( 3-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_vo_net : std_logic_vector( 1-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 3-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); +begin + i_scale_net <= i_scale; + i_valid_net <= i_valid; + o_scale <= test_systolicfft_vhdl_black_box_so_net; + o_valid <= test_systolicfft_vhdl_black_box_vo_net; + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; + o_im_0 <= reinterpret0_output_port_net; + o_im_1 <= reinterpret1_output_port_net; + o_im_2 <= reinterpret2_output_port_net; + o_im_3 <= reinterpret3_output_port_net; + o_im_4 <= reinterpret4_output_port_net_x0; + o_im_5 <= reinterpret5_output_port_net; + o_im_6 <= reinterpret6_output_port_net; + o_im_7 <= reinterpret7_output_port_net; + o_re_0 <= reinterpret0_output_port_net_x0; + o_re_1 <= reinterpret1_output_port_net_x0; + o_re_2 <= reinterpret2_output_port_net_x0; + o_re_3 <= reinterpret3_output_port_net_x0; + o_re_4 <= reinterpret4_output_port_net; + o_re_5 <= reinterpret5_output_port_net_x0; + o_re_6 <= reinterpret6_output_port_net_x0; + o_re_7 <= reinterpret7_output_port_net_x0; + clk_net <= clk_1; + ce_net <= ce_1; + vector_fft : entity xil_defaultlib.ssr_8x8_vector_fft + port map ( + i_re_1 => i_re_0_net, + i_im_1 => i_im_0_net, + vi => i_valid_net, + si => i_scale_net, + i_re_2 => i_re_1_net, + i_re_3 => i_re_2_net, + i_re_4 => i_re_3_net, + i_re_5 => i_re_4_net, + i_re_6 => i_re_5_net, + i_re_7 => i_re_6_net, + i_re_8 => i_re_7_net, + i_im_2 => i_im_1_net, + i_im_3 => i_im_2_net, + i_im_4 => i_im_3_net, + i_im_5 => i_im_4_net, + i_im_6 => i_im_5_net, + i_im_7 => i_im_6_net, + i_im_8 => i_im_7_net, + clk_1 => clk_net, + ce_1 => ce_net, + o_re_1 => reinterpret0_output_port_net_x0, + o_im_1 => reinterpret0_output_port_net, + vo => test_systolicfft_vhdl_black_box_vo_net(0), + so => test_systolicfft_vhdl_black_box_so_net, + o_re_2 => reinterpret1_output_port_net_x0, + o_re_3 => reinterpret2_output_port_net_x0, + o_re_4 => reinterpret3_output_port_net_x0, + o_re_5 => reinterpret4_output_port_net, + o_re_6 => reinterpret5_output_port_net_x0, + o_re_7 => reinterpret6_output_port_net_x0, + o_re_8 => reinterpret7_output_port_net_x0, + o_im_2 => reinterpret1_output_port_net, + o_im_3 => reinterpret2_output_port_net, + o_im_4 => reinterpret3_output_port_net, + o_im_5 => reinterpret4_output_port_net_x0, + o_im_6 => reinterpret5_output_port_net, + o_im_7 => reinterpret6_output_port_net, + o_im_8 => reinterpret7_output_port_net + ); + i_im : entity xil_defaultlib.ssr_8x8_i_im + port map ( + i_im_0 => i_im_0_net, + i_im_1 => i_im_1_net, + i_im_2 => i_im_2_net, + i_im_3 => i_im_3_net, + i_im_4 => i_im_4_net, + i_im_5 => i_im_5_net, + i_im_6 => i_im_6_net, + i_im_7 => i_im_7_net + ); + i_re : entity xil_defaultlib.ssr_8x8_i_re + port map ( + i_re_0 => i_re_0_net, + i_re_1 => i_re_1_net, + i_re_2 => i_re_2_net, + i_re_3 => i_re_3_net, + i_re_4 => i_re_4_net, + i_re_5 => i_re_5_net, + i_re_6 => i_re_6_net, + i_re_7 => i_re_7_net + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8_default_clock_driver is + port ( + ssr_8x8_sysclk : in std_logic; + ssr_8x8_sysce : in std_logic; + ssr_8x8_sysclr : in std_logic; + ssr_8x8_clk1 : out std_logic; + ssr_8x8_ce1 : out std_logic + ); +end ssr_8x8_default_clock_driver; +architecture structural of ssr_8x8_default_clock_driver is +begin + clockdriver : entity xil_defaultlib.xlclockdriver + generic map ( + period => 1, + log_2_period => 1 + ) + port map ( + sysclk => ssr_8x8_sysclk, + sysce => ssr_8x8_sysce, + sysclr => ssr_8x8_sysclr, + clk => ssr_8x8_clk1, + ce => ssr_8x8_ce1 + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x8 is + port ( + i_scale : in std_logic_vector( 3-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk : in std_logic; + o_scale : out std_logic_vector( 3-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x8; +architecture structural of ssr_8x8 is + attribute core_generation_info : string; + attribute core_generation_info of structural : architecture is "ssr_8x8,sysgen_core_2019_2,{,compilation=HDL Netlist,block_icon_display=Default,family=zynquplusRFSOC,part=xczu28dr,speed=-2-e,package=ffvg1517,synthesis_language=vhdl,hdl_library=xil_defaultlib,synthesis_strategy=Vivado Synthesis Defaults,implementation_strategy=Vivado Implementation Defaults,testbench=0,interface_doc=0,ce_clr=0,clock_period=10,system_simulink_period=1,waveform_viewer=0,axilite_interface=0,ip_catalog_plugin=0,hwcosim_burst_mode=0,simulation_time=10,blackbox2=1,concat=9,delay=10,reinterpret=32,slice=24,}"; + signal ce_1_net : std_logic; + signal clk_1_net : std_logic; +begin + ssr_8x8_default_clock_driver : entity xil_defaultlib.ssr_8x8_default_clock_driver + port map ( + ssr_8x8_sysclk => clk, + ssr_8x8_sysce => '1', + ssr_8x8_sysclr => '0', + ssr_8x8_clk1 => clk_1_net, + ssr_8x8_ce1 => ce_1_net + ); + ssr_8x8_struct : entity xil_defaultlib.ssr_8x8_struct + port map ( + i_scale => i_scale, + i_valid => i_valid, + i_im_0 => i_im_0, + i_im_1 => i_im_1, + i_im_2 => i_im_2, + i_im_3 => i_im_3, + i_im_4 => i_im_4, + i_im_5 => i_im_5, + i_im_6 => i_im_6, + i_im_7 => i_im_7, + i_re_0 => i_re_0, + i_re_1 => i_re_1, + i_re_2 => i_re_2, + i_re_3 => i_re_3, + i_re_4 => i_re_4, + i_re_5 => i_re_5, + i_re_6 => i_re_6, + i_re_7 => i_re_7, + clk_1 => clk_1_net, + ce_1 => ce_1_net, + o_scale => o_scale, + o_valid => o_valid, + o_im_0 => o_im_0, + o_im_1 => o_im_1, + o_im_2 => o_im_2, + o_im_3 => o_im_3, + o_im_4 => o_im_4, + o_im_5 => o_im_5, + o_im_6 => o_im_6, + o_im_7 => o_im_7, + o_re_0 => o_re_0, + o_re_1 => o_re_1, + o_re_2 => o_re_2, + o_re_3 => o_re_3, + o_re_4 => o_re_4, + o_re_5 => o_re_5, + o_re_6 => o_re_6, + o_re_7 => o_re_7 + ); +end structural; diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8_entity_declarations.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8_entity_declarations.vhd new file mode 100644 index 0000000..2d133a7 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/ssr_8x8_entity_declarations.vhd @@ -0,0 +1,6159 @@ +------------------------------------------------------------------- +-- System Generator version 2019.2 VHDL source file. +-- +-- Copyright(C) 2019 by Xilinx, Inc. All rights reserved. This +-- text/file contains proprietary, confidential information of Xilinx, +-- Inc., is distributed under license from Xilinx, Inc., and may be used, +-- copied and/or disclosed only pursuant to the terms of a valid license +-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use +-- this text/file solely for design, simulation, implementation and +-- creation of design files limited to Xilinx devices or technologies. +-- Use with non-Xilinx devices or technologies is expressly prohibited +-- and immediately terminates your license unless covered by a separate +-- agreement. +-- +-- Xilinx is providing this design, code, or information "as is" solely +-- for use in developing programs and solutions for Xilinx devices. By +-- providing this design, code, or information as one possible +-- implementation of this feature, application or standard, Xilinx is +-- making no representation that this implementation is free from any +-- claims of infringement. You are responsible for obtaining any rights +-- you may require for your implementation. Xilinx expressly disclaims +-- any warranty whatsoever with respect to the adequacy of the +-- implementation, including but not limited to warranties of +-- merchantability or fitness for a particular purpose. +-- +-- Xilinx products are not intended for use in life support appliances, +-- devices, or systems. Use in such applications is expressly prohibited. +-- +-- Any modifications that are made to the source code are done at the user's +-- sole risk and will be unsupported. +-- +-- This copyright and support notice must be retained as part of this +-- text at all times. (c) Copyright 1995-2019 Xilinx, Inc. All rights +-- reserved. +------------------------------------------------------------------- + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x8_xldelay is + generic(width : integer := -1; + latency : integer := -1; + reg_retiming : integer := 0; + reset : integer := 0); + port(d : in std_logic_vector (width-1 downto 0); + ce : in std_logic; + clk : in std_logic; + en : in std_logic; + rst : in std_logic; + q : out std_logic_vector (width-1 downto 0)); + +end ssr_8x8_xldelay; + +architecture behavior of ssr_8x8_xldelay is + component synth_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; -- end component synth_reg + + component synth_reg_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; + + signal internal_ce : std_logic; + +begin + internal_ce <= ce and en; + + srl_delay: if ((reg_retiming = 0) and (reset = 0)) or (latency < 1) generate + synth_reg_srl_inst : synth_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => '0', + clk => clk, + o => q); + end generate srl_delay; + + reg_delay: if ((reg_retiming = 1) or (reset = 1)) and (latency >= 1) generate + synth_reg_reg_inst : synth_reg_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => rst, + clk => clk, + o => q); + end generate reg_delay; +end architecture behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: COMPLEX_FIXED_PKG.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Package Name: COMPLEX_FIXED_PKG +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Unconstrained Size Vectors and Matrices of Complex Arbitrary Precision Fixed Point Numbers +-- +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +package COMPLEX_FIXED_PKG is + type BOOLEAN_VECTOR is array(NATURAL range <>) of BOOLEAN; + type INTEGER_VECTOR is array(NATURAL range <>) of INTEGER; + type REAL_VECTOR is array(NATURAL range <>) of REAL; +--2008 type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED; + type COMPLEX_VECTOR is array(INTEGER range <>) of COMPLEX; + + type SFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point signed number, like SIGNED but lower bound can be negative +--2008 type SFIXED_VECTOR is array(INTEGER range <>) of SFIXED; -- unconstrained array of SFIXED +--2008 type CFIXED is record RE,IM:SFIXED; end record; -- arbitrary precision fixed point complex signed number +--2008 type CFIXED_VECTOR is array(INTEGER range <>) of CFIXED; -- unconstrained array of CFIXED +--2008 type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR; -- unconstrained array of CFIXED_VECTOR + type SFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of SFIXED, vector size must be given by a separate generic + type CFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point complex signed number, CFIXED'low is always even and CFIXED'high is always odd + type CFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of CFIXED, vector size must be given by a separate generic + +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED; -- returns the CFIXED range for X(K) +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).RE +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).IM + + function MIN(A,B:INTEGER) return INTEGER; + function MIN(A,B,C:INTEGER) return INTEGER; + function MIN(A,B,C,D:INTEGER) return INTEGER; + function MED(A,B,C:INTEGER) return INTEGER; + function MAX(A,B:INTEGER) return INTEGER; + function MAX(A,B,C:INTEGER) return INTEGER; + function MAX(A,B,C,D:INTEGER) return INTEGER; + function "+"(X,Y:SFIXED) return SFIXED; -- full precision add with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X,Y:SFIXED) return SFIXED; -- full precision subtract with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X:SFIXED) return SFIXED; -- full precision negate with SFIXED(X'high+1 downto X'low) result + function "*"(X,Y:SFIXED) return SFIXED; -- full precision multiply with SFIXED(X'high+Y'high+1 downto X'low+Y'low) result + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED; -- multiply by 0 or 1 with SFIXED(X'high downto X'low) result + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED; -- resizes X and returns SFIXED(H downto L) + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED; -- resizes X to match HL and returns SFIXED(HL'high downto HL'low) + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high+N downto X'low+N) result + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED; -- returns SFIXED(H downto L) result + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED; -- returns SFIXED(HL'high downto HL'low) result + function TO_REAL(S:SFIXED) return REAL; -- returns REAL result +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED; -- returns element K out of an N-size array X + + function RE(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vRE(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure RE(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function IM(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vIM(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure IM(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function "+"(X,Y:CFIXED) return CFIXED; -- full precision add with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "-"(X,Y:CFIXED) return CFIXED; -- full precision subtract with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "*"(X,Y:CFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high+2 downto X'low+Y'low) result + function "*"(X:CFIXED;Y:SFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high downto X'low+Y'low) result + function "*"(X:SFIXED;Y:CFIXED) return CFIXED; + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED; -- resizes X and returns CFIXED(H downto L) + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED; -- resizes X to match HL and returns CFIXED(HL'high downto HL'low) + function PLUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function "-"(X:CFIXED) return CFIXED; -- full precision negate with CFIXED(X'high+2 downto X'low) result + function MINUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function SWAP(X:CFIXED) return CFIXED; -- returns CFIXED(X'high downto X'low) result + function CONJ(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high+N downto X'low+N) result + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED; -- returns CFIXED(H downto L) result + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED; -- returns CFIXED(HL'high downto HL'low) result + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED; -- returns CFIXED(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_CFIXED(R,I:SFIXED) return CFIXED; -- returns CFIXED(2*MAX(R'high,I'high)+1 downto 2*MIN(R'low,I'low)) result + function TO_COMPLEX(C:CFIXED) return COMPLEX; -- returns COMPLEX result + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR; -- returns CFIXED_VECTOR(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR; -- returns COMPLEX_VECTOR result + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR; -- returns R*C + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED; -- returns element K out of an N-size array X + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a variable, set element K out of an N-size array X to C + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a signal, set element K out of an N-size array X to C + + function LOG2(N:INTEGER) return INTEGER; -- returns ceil(log2(N)) +end COMPLEX_FIXED_PKG; + +package body COMPLEX_FIXED_PKG is +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED is -- returns the CFIXED range for X(K) +-- variable O:CFIXED(X'length/N*(K+1)-1+X'low/N downto X'length/N*K+X'low/N); +-- begin +-- return O; +-- end; + +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).RE +-- begin +-- return RE(ELEMENT(X,K,N)); +-- end; + +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).IM +-- begin +-- return IM(ELEMENT(X,K,N)); +-- end; + + function MIN(A,B:INTEGER) return INTEGER is + begin + if AB then + return A; + else + return B; + end if; + end; + + function MAX(A,B,C:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),C); + end; + + function MAX(A,B,C,D:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),MAX(C,D)); + end; + + function "+"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX+SY; -- SIGNED addition + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX-SY; -- SIGNED subtraction + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SR:SIGNED(X'high-X'low+1 downto 0); + variable R:SFIXED(X'high+1 downto X'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + SR:=-RESIZE(SX,SR'length); -- SIGNED negation + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X,Y:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SY:SIGNED(Y'high-Y'low downto 0); + variable SR:SIGNED(SX'high+SY'high+1 downto 0); + variable R:SFIXED(X'high+Y'high+1 downto X'low+Y'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + for K in SY'range loop + SY(K):=Y(Y'low+K); + end loop; + SR:=SX*SY; -- SIGNED multiplication + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED is + begin + if Y='1' then + return X; + else + return TO_SFIXED(0.0,X); + end if; + end; + + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED is + variable R:SFIXED(H downto L); + begin + for K in R'range loop + if KX'high then + R(K):=X(X'high); -- sign extend X MSBs + else + R(K):=X(K); + end if; + end loop; + return R; + end; + + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED is + begin + return RESIZE(X,HL'high,HL'low); + end; + + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high-N downto X'low-N); + begin + for K in R'range loop + R(K):=X(K+N); + end loop; + return R; + end; + + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high+N downto X'low+N); + begin + for K in R'range loop + R(K):=X(K-N); + end loop; + return R; + end; + + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED is + variable RR:REAL; + variable V:SFIXED(H downto L); + begin + assert (R<2.0**H) and (R>=-2.0**H) report "TO_SFIXED vector truncation!" severity warning; + if R<0.0 then + V(V'high):='1'; + RR:=R+2.0**V'high; + else + V(V'high):='0'; + RR:=R; + end if; + for K in V'high-1 downto V'low loop + if RR>=2.0**K then + V(K):='1'; + RR:=RR-2.0**K; + else + V(K):='0'; + end if; + end loop; + return V; + end; + + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED is + begin + return TO_SFIXED(R,HL'high,HL'low); + end; + + function TO_REAL(S:SFIXED) return REAL is + variable R:REAL; + begin + R:=0.0; + for K in S'range loop + if K=S'high then + if S(K)='1' then + R:=R-2.0**K; + end if; + else + if S(K)='1' then + R:=R+2.0**K; + end if; + end if; + end loop; + return R; + end; + +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED is -- X'low and X'length are always multiples of N +-- variable R:SFIXED(X'length/N-1+X'low/N downto X'low/N); +-- begin +-- R:=SFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); +-- return R; -- element K out of N of X +-- end; + + function RE(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(R'length-1+X'low downto X'low)); + return R; --lower half of X + end; + +-- procedure vRE(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low):=CFIXED(S); -- set lower half of X +-- end; + +-- procedure RE(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low)<=CFIXED(S); -- set lower half of X +-- end; + + function IM(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(X'high downto R'length+X'low)); + return R; --upper half of X + end; + +-- procedure vIM(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low):=CFIXED(S); -- set upper half of X +-- end; + +-- procedure IM(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low)<=CFIXED(S); -- set upper half of X +-- end; + + function "+"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+RE(Y),IM(X)+IM(Y)); + end; + + function "-"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-RE(Y),IM(X)-IM(Y)); + end; + + function "*"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*RE(Y)-IM(X)*IM(Y),RE(X)*IM(Y)+IM(X)*RE(Y)); + end; + + function "*"(X:CFIXED;Y:SFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*Y,IM(X)*Y); + end; + + function "*"(X:SFIXED;Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(X*RE(Y),X*IM(Y)); + end; + + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(RESIZE(RE(X),H,L),RESIZE(IM(X),H,L)); + end; + + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED is + begin + return RESIZE(X,HL'high/2,HL'low/2); + end; + + function PLUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-IM(X),RE(X)); + end; + + function "-"(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-RE(X),-IM(X)); + end; + + function MINUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),-RE(X)); + end; + + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-IM(Y)+RE(RND),IM(X)+RE(Y)+IM(RND)); + end; + + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+IM(Y)+RE(RND),IM(X)-RE(Y)+IM(RND)); + end; + + function SWAP(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),RE(X)); + end; + + function CONJ(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X),-IM(X)); + end; + + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_RIGHT(RE(X),N),SHIFT_RIGHT(IM(X),N)); + end; + + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_LEFT(RE(X),N),SHIFT_LEFT(IM(X),N)); + end; + + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(TO_SFIXED(R,H,L),TO_SFIXED(I,H,L)); + end; + + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(R,I,HL'high/2,HL'low/2); + end; + + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(C.RE,C.IM,HL); + end; + + function TO_CFIXED(R,I:SFIXED) return CFIXED is + constant H:INTEGER:=MAX(R'high,I'high); + constant L:INTEGER:=MIN(R'low,I'low); + variable C:CFIXED(2*H+1 downto 2*L); + begin + C:=CFIXED(RESIZE(I,H,L))&CFIXED(RESIZE(R,H,L)); + return C; -- I&R + end; + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED is -- X'low and X'length are always multiples of N + variable R:CFIXED(X'length/N-1+X'low/N downto X'low/N); + begin + R:=CFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); + return R; -- element K out of N of X + end; + + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low):=CFIXED_VECTOR(C); -- element K out of N of X + end; + + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low)<=CFIXED_VECTOR(C); -- element K out of N of X + end; + + function TO_COMPLEX(C:CFIXED) return COMPLEX is + variable R:COMPLEX; + begin + R.RE:=TO_REAL(RE(C)); + R.IM:=TO_REAL(IM(C)); + return R; + end; + + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR is + variable R:CFIXED_VECTOR(C'length*(HL'high+1)-1 downto C'length*HL'low); + begin + for K in C'range loop + R((K-C'low+1)*HL'length-1+R'low downto (K-C'low)*HL'length+R'low):=CFIXED_VECTOR(TO_CFIXED(C(K),HL)); + end loop; + return R; + end; + + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR is + variable R:COMPLEX_VECTOR(0 to N-1); + begin + for K in 0 to N-1 loop + R(K):=TO_COMPLEX(ELEMENT(C,K,N)); + end loop; + return R; + end; + + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR is + variable X:COMPLEX_VECTOR(C'range); + begin + for K in C'range loop + X(K):=R*C(K); + end loop; + return X; + end; + + function LOG2(N:INTEGER) return INTEGER is + variable TEMP:INTEGER; + variable RESULT:INTEGER; + begin + TEMP:=N; + RESULT:=0; + while TEMP>1 loop + RESULT:=RESULT+1; + TEMP:=(TEMP+1)/2; + end loop; + return RESULT; + end; +end COMPLEX_FIXED_PKG; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic BOOLEAN Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); +end BDELAY; + +architecture TEST of BDELAY is + attribute rloc:STRING; + + component BDELAY + generic(SIZE:INTEGER:=1); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); + end component; + +begin + l0:if SIZE=0 generate + begin + O<=I; + end generate l0; + -- end; + + l1:if SIZE=1 generate + signal iO:BOOLEAN:=FALSE; + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; + end generate l1; + -- end; + + l17: if SIZE>=2 and SIZE<18 generate + signal A:UNSIGNED(3 downto 0); + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + D<='1' when I else '0'; + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>D, + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l17; + -- end; + + l33: if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + D<='1' when I else '0'; + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>D, + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l33; + -- end; + + l257: if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.BDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + -- end; + end generate l257; + + ln: if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + type TUV is array(0 to SIZE-3) of UNSIGNED(0 downto 0); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(0 downto 0):=(others=>(others=>'0')); + signal MEM:TUV:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(0 downto 0):=(others=>'0'); + signal D,Q:UNSIGNED(0 downto 0); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + D<="1" when I else "0"; + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=D; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO="1"; + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: UDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: UDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic UNSIGNED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity UDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in UNSIGNED; + O:out UNSIGNED); +end UDELAY; + +architecture TEST of UDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin + assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=I; +-- end; + end generate; +-- elsif l1: SIZE=1 generate + l1:if SIZE=1 generate + signal iO:UNSIGNED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; +-- end; + end generate; +-- elsif l17: SIZE>=2 and SIZE<18 generate + l17:if SIZE>=2 and SIZE<18 generate + lk:for K in 0 to O'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l33: SIZE>=18 and SIZE<34 generate + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l257: SIZE>=34 and SIZE=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.UDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); +-- end; + end generate; +-- elsif ln: SIZE>=BRAM_THRESHOLD generate + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of UNSIGNED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO; + end if; + end process; +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic SFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity SDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in SFIXED; + O:out SFIXED); +end SDELAY; + +architecture TEST of SDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin +-- assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=RESIZE(I,O'high,O'low); + end generate l0; + --end; + + l1:if SIZE=1 generate + signal iO:SFIXED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=RESIZE(I,iO); + end if; + end process; + O<=iO; + end generate l1; + --end; + + l17:if SIZE>=2 and SIZE<18 generate +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); + begin + lk:for K in 0 to I'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l17; + --end; + + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- iO<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l33; + --end; + + l257:if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.SDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + --end; + end generate l257; + + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:SFIXED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of SFIXED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:SFIXED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=RESIZE(iO,O'high,O'low); + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic CFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CDELAY; + +architecture TEST of CDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; + signal IRE,IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); +begin + IRE<=RE(I); + IIM<=IM(I); + dr:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.RE); + I=>IRE, + O=>ORE); + di:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.IM); + I=>IIM, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CB.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CB +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Matrix Transposer (Corner Bender) Module Stage +-- It does an RxR matrix transposition where R=I'length +-- and each matrix element is a group of PACKING_FACTOR consecutive samples +-- LATENCY=(I'length-1)*PACKING_FACTOR+1 when I'length>1 or 0 when I'length=1 +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CB is + generic(SSR:INTEGER:=4; --93 + F:INTEGER:=0; + PACKING_FACTOR:INTEGER:=1; + INPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + OUTPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + SHORTEN_VO_BY:INTEGER:=0; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CB; + +architecture TEST of CB is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(LOG2(SSR)-1 downto 0); --93 local constrained UNSIGNED_VECTOR type + type iCFIXED_VECTOR is array(NATURAL range <>) of CFIXED((I'high+1)/SSR-1 downto I'low/SSR); --93 local constrained CFIXED_VECTOR type + + signal CNTP:UNSIGNED(LOG2(PACKING_FACTOR) downto 0):=(others=>'0'); + signal CNT:UNSIGNED(LOG2(SSR)-1 downto 0):=(others=>'0'); +--2008 signal A:UNSIGNED_VECTOR(0 to I'length):=(others=>(others=>'0')); +--2008 signal EN:BOOLEAN_VECTOR(0 to I'length):=(others=>FALSE); +--2008 signal DI:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal DO:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(0 to I'length-1=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).IM'range=>'0'))); + signal A:UNSIGNED_VECTOR(0 to SSR):=(others=>(others=>'0')); + signal EN:BOOLEAN_VECTOR(0 to SSR):=(others=>FALSE); + signal II,DI,OO:iCFIXED_VECTOR(0 to SSR-1); + signal DO:iCFIXED_VECTOR(0 to SSR-1):=(others=>(others=>'0')); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity error; + + f0:if F=0 generate + begin +--2008 i0:if I'length=1 generate + i0:if SSR=1 generate + O<=I; + VO<=VI; + SO<=SI; + end generate; +--2008 else generate +--2008 i1:if I'length>1 generate + i1:if SSR>1 generate + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if CNTP=PACKING_FACTOR-1 then + CNTP<=(others=>'0'); + CNT<=CNT+1; + else + CNTP<=CNTP+1; + end if; + else + CNTP<=(others=>'0'); + CNT<=(others=>'0'); + end if; + end if; + end process; + + A(0)<=CNT; + EN(0)<=CNTP=PACKING_FACTOR-1; +--2008 lk:for K in 0 to I'length-1 generate + lk:for K in 0 to SSR-1 generate + begin + II(K)<=CFIXED(I(I'length/SSR*(K+1)-1+I'low downto I'length/SSR*K+I'low)); --93 + i1:entity work.CDELAY generic map(SIZE=>K*(PACKING_FACTOR+INPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II(K), --93 I(I'low+K), + O=>DI(K)); + process(CLK) + begin + if rising_edge(CLK) then + DO(K)<=DI(TO_INTEGER(A(K))); + if EN(K) then + A(K+1)<=A(K); + end if; + end if; + end process; + bd:entity work.BDELAY generic map(SIZE=>PACKING_FACTOR) + port map(CLK=>CLK, + I=>EN(K), + O=>EN(K+1)); + o1:entity work.CDELAY generic map(SIZE=>(SSR-1-K)*(PACKING_FACTOR+OUTPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DO(K), + O=>OO(K)); --93 O(O'low+K)); + O(O'length/SSR*(K+1)-1+O'low downto O'length/SSR*K+O'low)<=CFIXED_VECTOR(OO(K)); --93 + end generate; + + bd:entity work.BDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY) + port map(CLK=>CLK, + I=>VI, + O=>VO); + + ud:entity work.UDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +-- end; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=SSR/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.CB generic map(SSR=>G, + F=>0, + PACKING_FACTOR=>PACKING_FACTOR, + INPUT_PACKING_FACTOR_ADJUST=>INPUT_PACKING_FACTOR_ADJUST, + OUTPUT_PACKING_FACTOR_ADJUST=>OUTPUT_PACKING_FACTOR_ADJUST, + SHORTEN_VO_BY=>SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Real Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BFS is + generic(PIPELINE:BOOLEAN:=TRUE; + SUB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SCALE:in STD_LOGIC; +-- P:out SIGNED); -- O=A±B + P:out SFIXED; -- O=A±B + OVR:out STD_LOGIC); +end BFS; + +architecture FAST of BFS is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH+1 downto SM-1); +-- signal S:SIGNED(SH+1 downto SL); + signal SA,SB:SFIXED(SH+1 downto SM-1); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM+1 downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1)/8*8+8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1)/8*8+7 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH+1 generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (((I0 and not I4) or (I2 and I4)) xor ((I1 and not I4) or (I3 and I4)))) or (not I5 and ((I1 and not I4) or (I3 and I4)))) + port map(I0=>SB(K-1),I1=>SA(K-1),I2=>SB(K),I3=>SA(K),I4=>SCALE,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM+1)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM+1); + end generate; + S(SH+1)<=O(O'high); + + ia:if A'low'0'); + signal iOVR:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + iOVR<=S(S'high) xor S(S'high-1); + end if; + end process; + P<=iP; + OVR<=iOVR; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CBFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CBFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Complex Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CBFS is -- O0=I0+I1, O1=I0-I1 + generic(ROUNDING:BOOLEAN:=TRUE; + PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC; + I0,I1:in CFIXED; + SCALE:in STD_LOGIC; + O0,O1:out CFIXED; + OVR:out STD_LOGIC); +end CBFS; + +architecture TEST of CBFS is + signal I0RE,I0IM,I1RE,I1IM:SFIXED(I0'high/2 downto I0'low/2); + signal O0RE,O0IM,O1RE,O1IM:SFIXED(O0'high/2 downto O0'low/2); + signal OVR4:STD_LOGIC_VECTOR(3 downto 0); +begin + I0RE<=RE(I0); + I0IM<=IM(I0); + I1RE<=RE(I1); + I1IM<=IM(I1); + + u0:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0RE=I0RE+I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O0RE, + OVR=>OVR4(0)); + + u1:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0IM=I0IM+I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O0IM, + OVR=>OVR4(1)); + + u2:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1RE=I0RE-I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O1RE, + OVR=>OVR4(2)); + + u3:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1IM=I0IM-I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O1IM, + OVR=>OVR4(3)); + + O0<=TO_CFIXED(O0RE,O0IM); + O1<=TO_CFIXED(O1RE,O1IM); + OVR<=OVR4(0) or OVR4(1) or OVR4(2) or OVR4(3); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CSA3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CSA3 +-- Purpose: Generic 3-input Add/Sub Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Carry Save 3-input Adder/Subtracter +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CSA3 is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + NEGATIVE_A:BOOLEAN:=FALSE; + NEGATIVE_B:BOOLEAN:=FALSE; + EXTRA_MSBs:INTEGER:=2); + port(CLK:in STD_LOGIC:='0'; +-- A,B,C:in SIGNED; -- if SIGNED, A, B, C and P must be LSB aligned + A,B,C:in SFIXED; -- if SFIXED, A, B, C and P can be any size + CY1,CY2:in BOOLEAN:=FALSE; -- the number of CYs TRUE must equal the number of negative A and B terms +-- P:out SIGNED); -- O=C±A±B + P:out SFIXED); -- O=C±A±B +end CSA3; + +architecture FAST of CSA3 is + constant SH:INTEGER:=MAX(A'high,B'high,C'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MED(A'low,B'low,C'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low,C'low); +-- signal SA,SB,SC,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB,SC:SFIXED(SH downto SM); + signal S:SFIXED(SH downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + SC<=RESIZE(C,SC); + O5(0)<='1' when CY1 else '0'; + CY(0)<='1' when CY2 else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_B))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_A))); + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (I1 xor I2 xor I3 xor I4)) or (not I5 and ((I2 and I3) or (I3 and I1) or (I1 and I2)))) + port map(I0=>'0',I1=>SC(K),I2=>SB(K),I3=>SA(K),I4=>O5(K-SM),I5=>'1',O5=>O5(K+1-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM); + end generate; + + ia:if (A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +--***************************************************************************** +-- © Copyright 2008 - 2018 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +--***************************************************************************** +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : v1.2 +-- \ \ Application : DSP48E2 generic wrapper +-- / / Filename : DSP48E2GW.vhd +-- /___/ /\ Date Last Modified : Oct 11 2017 +-- \ \ / \ Date Created : Nov 14 2014 +-- \___\/\___\ +-- +--Device : UltraScale and UltraScale+ +--Design Name : DSP48E2GW +--Purpose : DSP48E2 Generic Wrapper makes DSP48E2 primitive instantiation easier +--Reference : +--Revision History : v1.0 - original version +--Revision History : v1.1 - smart SFIXED resizing +--Revision History : v1.2 - fix for output resizing +--***************************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +--use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity DSP48E2GW is + generic(X,Y:INTEGER:=-1; + DSP48E:INTEGER:=2; -- use 1 for DSP48E1 and 2 for DSP48E2 + -- Feature Control Attributes: Data Path Selection + AMULTSEL:STRING:="A"; -- Selects A input to multiplier (A, AD) + A_INPUT:STRING:="DIRECT"; -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL:STRING:="B"; -- Selects B input to multiplier (AD, B) + B_INPUT:STRING:="DIRECT"; -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL:STRING:="A"; -- Selects input to preadder (A, B) + RND:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- Rounding Constant + USE_MULT:STRING:="MULTIPLY"; -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD:STRING:="ONE48"; -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR:STRING:="FALSE"; -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD:STRING:="XOR24_48_96"; -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET:STRING:="NO_RESET"; -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY:STRING:="RESET"; -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK:STD_LOGIC_VECTOR(47 downto 0):=X"3fffffffffff"; -- 48-bit mask value for pattern detect (1=ignore) + PATTERN:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- 48-bit pattern match for pattern detect + SEL_MASK:STRING:="MASK"; -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN:STRING:="PATTERN"; -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT:STRING:="NO_PATDET"; -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED:STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED:BIT:='0'; -- Optional inversion for CARRYIN + IS_CLK_INVERTED:BIT:='0'; -- Optional inversion for CLK + IS_INMODE_INVERTED:STD_LOGIC_VECTOR(4 downto 0):="00000"; -- Optional inversion for INMODE + IS_OPMODE_INVERTED:STD_LOGIC_VECTOR(8 downto 0):="000000000"; -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED:BIT:='0'; -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED:BIT:='0'; -- Optional inversion for RSTA + IS_RSTB_INVERTED:BIT:='0'; -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED:BIT:='0'; -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED:BIT:='0'; -- Optional inversion for RSTC + IS_RSTD_INVERTED:BIT:='0'; -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED:BIT:='0'; -- Optional inversion for RSTM + IS_RSTP_INVERTED:BIT:='0'; -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG:INTEGER:=1; -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG:INTEGER:=1; -- Pipeline stages for pre-adder (0-1) + ALUMODEREG:INTEGER:=1; -- Pipeline stages for ALUMODE (0-1) + AREG:INTEGER:=1; -- Pipeline stages for A (0-2) + BCASCREG:INTEGER:=1; -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG:INTEGER:=1; -- Pipeline stages for B (0-2) + CARRYINREG:INTEGER:=1; -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG:INTEGER:=1; -- Pipeline stages for CARRYINSEL (0-1) + CREG:INTEGER:=1; -- Pipeline stages for C (0-1) + DREG:INTEGER:=1; -- Pipeline stages for D (0-1) + INMODEREG:INTEGER:=1; -- Pipeline stages for INMODE (0-1) + MREG:INTEGER:=1; -- Multiplier pipeline stages (0-1) + OPMODEREG:INTEGER:=1; -- Pipeline stages for OPMODE (0-1) + PREG:INTEGER:=1); -- Number of pipeline stages for P (0-1) + port(-- Cascade inputs: Cascade Ports + ACIN:in STD_LOGIC_VECTOR(29 downto 0):=(others=>'0'); -- 30-bit input: A cascade data + BCIN:in STD_LOGIC_VECTOR(17 downto 0):=(others=>'0'); -- 18-bit input: B cascade + CARRYCASCIN:in STD_LOGIC:='0'; -- 1-bit input: Cascade carry + MULTSIGNIN:in STD_LOGIC:='0'; -- 1-bit input: Multiplier sign cascade + PCIN:in STD_LOGIC_VECTOR(47 downto 0):=(others=>'0'); -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE:in STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- 4-bit input: ALU control + CARRYINSEL:in STD_LOGIC_VECTOR(2 downto 0):="000"; -- 3-bit input: Carry select + CLK:in STD_LOGIC:='0'; -- 1-bit input: Clock + INMODE:in STD_LOGIC_VECTOR(4 downto 0):="00000"; -- 5-bit input: INMODE control + OPMODE:in STD_LOGIC_VECTOR(8 downto 0):="000110101"; -- 9-bit input: Operation mode - default is P<=C+A*B + -- Data inputs: Data Ports + A:in SFIXED;--(Ahi downto Alo):=(others=>'0'); -- 30-bit input: A data + B:in SFIXED;--(Bhi downto Blo):=(others=>'0'); -- 18-bit input: B data + C:in SFIXED;--(Chi downto Clo):=(others=>'0'); -- 48-bit input: C data + CARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Carry-in + D:in SFIXED;--(Dhi downto Dlo):=(others=>'0'); -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage AREG + CEA2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage AREG + CEAD:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ADREG + CEALUMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ALUMODE + CEB1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage BREG + CEB2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage BREG + CEC:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CREG + CECARRYIN:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CARRYINREG + CECTRL:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for DREG + CEINMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for INMODEREG + CEM:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for MREG + CEP:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for PREG + RSTA:in STD_LOGIC:='0'; -- 1-bit input: Reset for AREG + RSTALLCARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Reset for CARRYINREG + RSTALUMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for ALUMODEREG + RSTB:in STD_LOGIC:='0'; -- 1-bit input: Reset for BREG + RSTC:in STD_LOGIC:='0'; -- 1-bit input: Reset for CREG + RSTCTRL:in STD_LOGIC:='0'; -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD:in STD_LOGIC:='0'; -- 1-bit input: Reset for DREG and ADREG + RSTINMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for INMODEREG + RSTM:in STD_LOGIC:='0'; -- 1-bit input: Reset for MREG + RSTP:in STD_LOGIC:='0'; -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT:out STD_LOGIC_VECTOR(29 downto 0); -- 30-bit output: A port cascade + BCOUT:out STD_LOGIC_VECTOR(17 downto 0); -- 18-bit output: B cascade + CARRYCASCOUT:out STD_LOGIC; -- 1-bit output: Cascade carry + MULTSIGNOUT:out STD_LOGIC; -- 1-bit output: Multiplier sign cascade + PCOUT:out STD_LOGIC_VECTOR(47 downto 0); -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW:out STD_LOGIC; -- 1-bit output: Overflow in add/acc + PATTERNBDETECT:out STD_LOGIC; -- 1-bit output: Pattern bar detect + PATTERNDETECT:out STD_LOGIC; -- 1-bit output: Pattern detect + UNDERFLOW:out STD_LOGIC; -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT:out STD_LOGIC_VECTOR(3 downto 0); -- 4-bit output: Carry + P:out SFIXED;--(Phi downto Plo); -- 48-bit output: Primary data + XOROUT:out STD_LOGIC_VECTOR(7 downto 0)); -- 8-bit output: XOR data +end entity; + +architecture WRAPPER of DSP48E2GW is + signal slvA:STD_LOGIC_VECTOR(29 downto 0); + signal slvB:STD_LOGIC_VECTOR(17 downto 0); + signal slvD:STD_LOGIC_VECTOR(26 downto 0); + signal slvC,slvP:STD_LOGIC_VECTOR(47 downto 0); +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if K=0) and (Y>=0) generate + begin + i1:if DSP48E=1 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; +-- else generate + i2:if (X<0) or (Y<0) generate + begin + i1:if DSP48E=1 generate + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; + P<=SLV_TO_SFIXED_RESIZE(slvP,P'high,P'low,A'low+B'low-P'low); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CKCM.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CKCM +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Constant Coeficient Complex Multiplier +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CKCM is -- LATENCY=3 + generic(M:INTEGER:=1; -- must be 0, 1, 2 or 3 to multiply I by (1.0,0.0), (Sqrt(0.5),-Sqrt(0.5)), (0.0,-1.0), (-Sqrt(0.5),-Sqrt(0.5)) + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + ROUNDING:BOOLEAN:=FALSE; -- set to TRUE to round the result + CONJUGATE:BOOLEAN:=FALSE); -- set to TRUE for IFFT + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CKCM; + +architecture TEST of CKCM is + attribute use_dsp48:STRING; + attribute use_dsp48 of TEST:architecture is "no"; +--2008 signal RND:SFIXED(O.RE'high downto O.RE'low-1); + signal RND:SFIXED((O'high+1)/2-1 downto O'low/2-1); + constant nCONJUGATE:BOOLEAN:=not CONJUGATE; +begin + i0:if M=0 generate + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>I, + O=>O); + end generate; +--elsif i1: M=2 generate + i1:if M=2 generate + ic:if CONJUGATE generate +--2008 signal NIIM1D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal NIIM1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IRE:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIIM1D<=RESIZE(-I.IM,I.IM); + NIIM1D<=RESIZE(-IM(I),NIIM1D); + end if; + end process; + r2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIIM1D, +--2008 O=>O.RE); + O=>ORE); + IRE<=RE(I); + i3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.IM); + I=>IRE, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + ---else generate + nc:if not CONJUGATE generate +--2008 signal NIRE1D:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal NIRE1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + IIM<=IM(I); + r3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.RE); + I=>IIM, + O=>ORE); + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIRE1D<=RESIZE(-I.RE,I.RE); + NIRE1D<=RESIZE(-RE(I),RE(I)); + end if; + end process; + i2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIRE1D, +--2008 O=>O.IM); + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + end generate; +-- else generate -- M=1 or 3 + i2:if (M=1) or (M=3) generate -- M=1 or 3 + constant K:SFIXED(0 downto -18):="0101101010000010100"; -- SQRT(0.5) + +--2008 signal X1,Y1:SFIXED(I.RE'high downto I.RE'low-14); +--2008 signal X2,Y2:SFIXED(I.RE'range); +--2008 signal KIRE,KIIM:SFIXED(I.RE'range); + + + + signal X1,Y1:SFIXED((I'high+1)/2-1 downto I'low/2-14); + signal X2,Y2:SFIXED((I'high+1)/2-1 downto I'low/2):=(others=>'0'); + signal KIRE,KIIM:SFIXED((I'high+1)/2-1 downto I'low/2); +--2008 signal I_1:CFIXED(RE(I.RE'high-1 downto I.RE'low-1),IM(I.IM'high-1 downto I.IM'low-1)); +--2008 signal I_6:CFIXED(RE(I.RE'high-6 downto I.RE'low-6),IM(I.IM'high-6 downto I.IM'low-6)); +--2008 signal I_14:CFIXED(RE(I.RE'high-14 downto I.RE'low-14),IM(I.IM'high-14 downto I.IM'low-14)); + signal I_1:CFIXED(I'high-2*1 downto I'low-2*1); + signal I_6:CFIXED(I'high-2*6 downto I'low-2*6); + signal I_14:CFIXED(I'high-2*14 downto I'low-2*14); + signal I_1RE,I_1IM:SFIXED((I_1'high+1)/2-1 downto I_1'low/2); + signal I_6RE,I_6IM:SFIXED((I_6'high+1)/2-1 downto I_6'low/2); + signal I_14RE,I_14IM:SFIXED((I_14'high+1)/2-1 downto I_14'low/2); + signal X1_2:SFIXED(X1'high-2 downto X1'low-2); + signal X2_4:SFIXED(X2'high-4 downto X2'low-4); + signal Y1_2:SFIXED(Y1'high-2 downto Y1'low-2); + signal Y2_4:SFIXED(Y2'high-4 downto Y2'low-4); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + constant MEQ3:BOOLEAN:=M=3; + begin +--2008 RND<=TO_SFIXED(2.0**(O.RE'low-1),RND) when ROUNDING else (others=>'0'); + RND<=TO_SFIXED(2.0**(O'low/2-1),RND) when ROUNDING else (others=>'0'); + process(CLK) + begin + if rising_edge(CLK) then +--2008 X2<=I.RE; +--2008 Y2<=I.IM; + X2<=RE(I); + Y2<=IM(I); + end if; + end process; + + I_1<=SHIFT_RIGHT(I,1); + I_6<=SHIFT_RIGHT(I,6); + I_14<=SHIFT_RIGHT(I,14); + X1_2<=SHIFT_RIGHT(X1,2); + X2_4<=SHIFT_RIGHT(X2,4); + Y1_2<=SHIFT_RIGHT(Y1,2); + Y2_4<=SHIFT_RIGHT(Y2,4); + I_1RE<=RE(I_1); + I_6RE<=RE(I_6); + I_14RE<=RE(I_14); + + a1:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.RE, +--2008 B=>I_6.RE, +--2008 C=>I_14.RE, + A=>I_1RE, + B=>I_6RE, + C=>I_14RE, + P=>X1); -- P=C+A+B + + a2:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>X1, + B=>X1_2, + C=>X2_4, + P=>KIRE); -- P=C+A+B + + I_1IM<=IM(I_1); + I_6IM<=IM(I_6); + I_14IM<=IM(I_14); + a3:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.IM, +--2008 B=>I_6.IM, +--2008 C=>I_14.IM, + A=>I_1IM, + B=>I_6IM, + C=>I_14IM, + P=>Y1); -- P=C+A+B + + a4:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>Y1, + B=>Y1_2, + C=>Y2_4, + P=>KIIM); -- P=C+A+B + + a5:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>MEQ3, --2008 M=3, + NEGATIVE_B=>CONJUGATE, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>MEQ3, --2008 M=3, + CY2=>CONJUGATE, +--2008 P=>O.RE); -- P=C+A+B + P=>ORE); -- P=C+A+B + + a6:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>nCONJUGATE, + NEGATIVE_B=>MEQ3, --2008 M=3, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>nCONJUGATE, + CY2=>MEQ3, --2008 M=3, +--2008 P=>O.IM); -- P=C+A+B + P=>OIM); -- P=C+A+B + O<=TO_CFIXED(ORE,OIM); + --end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: ADDSUB.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity ADDSUB is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SUB:in BOOLEAN:=FALSE; +-- P:out SIGNED); -- O=A±B + P:out SFIXED); -- O=A±B +end ADDSUB; + +architecture FAST of ADDSUB is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB:SFIXED(SH downto SM); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0"; + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + signal I_4:STD_LOGIC; + begin + I_4<='1' when SUB else '0'; + l6:LUT6_2 generic map(INIT=>(I5 and (I2 xor I3 xor I4)) or (not I5 and ((I2 xor I4) and I3))) + port map(I0=>'0',I1=>'0',I2=>SB(K),I3=>SA(K),I4=>I_4,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + +-- ll:for L in SM to SH+1 generate + ll:for L in SM to SH generate +-- S(L)<=O(L-SM+1); + S(L)<=O(L-SM); + end generate; + S(SH+1)<=S(SH); + + ia:if A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: TABLE.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: TABLE +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, SinCos Table Module +-- +-- Latency is always 2 +-- when INV_FFT=FALSE W=exp(-2.0*PI*i*JK/N) and when INV_FFT=TRUE W=exp(2.0*PI*i*JK/N) +-- to maximize W output bit size utilization W.RE and W.IM are always negative (MSB='1') and that bit could be ignored, this is why W.RE'length can be 19 bits but a single BRAM would still be used +-- when W.RE or W.IM need to be positive CS respectively SS are TRUE, same thing when they are 0.0 CZ respectively SZ are TRUE - the complex multiplier has to use CS, SS, CZ and SZ, not just W to produce the correct result +-- the SIN and COS ROM table sizes are N/4 deep and W.RE'length-1 wide (it is implictly assumed that W.RE and W.IM always have the same range) +-- if STYLE="block" a single dual port BRAM is used for both tables +-- if STYLE="distributed" then two fabric LUT based ROMs are used +-- as a general rule for N<2048 "distributed" should be used, otherwise "block" makes more sense but this is not a hard rule +-- W range is unconstrained but W.RE'high and W.IM'high really have to be 0 all the time, do not use other values +-- the maximum SNR without using extra BRAMs is achieved when W.RE'low and W.IM'low are -18 so W.RE'length and W.IM'length are 19 bits but they can be less than that - this would reduce SNR and save resources only when STYLE="distributed" +-- TABLE.VHD also works with more than 19 bits but the current complex multiplier implementation does not support that - this would essentially double the number of BRAMs and DSP48s used and seems too high a price to pay for a few extra dB of SNR +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use IEEE.MATH_REAL.all; + +use work.COMPLEX_FIXED_PKG.all; + +--!! entity TABLE is -- LATENCY=3 (2 if SEPARATE_SIGN is TRUE) +entity TABLE is -- LATENCY=4 (3 if SEPARATE_SIGN is TRUE) when SPLIT_RADIX=0 else LATENCY=0 + generic(N:INTEGER:=1024; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and J*1 or J*3 with J>0 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + SEPARATE_SIGN:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + STYLE:STRING:="block"); -- use only "block" or "distributed" + port(CLK:in STD_LOGIC; + JK:in UNSIGNED; + VI:in BOOLEAN; + W:out CFIXED; + CS,SS,CZ,SZ:out BOOLEAN; + VO:out BOOLEAN); +end TABLE; + +architecture TEST of TABLE is +--2008 constant WH:INTEGER:=W.RE'high-1+BOOLEAN'pos(SEPARATE_SIGN); +--2008 constant WL:INTEGER:=W.RE'low; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 + constant WH:INTEGER:=(W'high+1)/2-1-1+BOOLEAN'pos(SEPARATE_SIGN); + constant WL:INTEGER:=W'low/2; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 +begin + i0:if SPLIT_RADIX=0 generate + type wSFIXED_VECTOR is array(INTEGER range <>) of SFIXED(WH-1 downto WL); -- local constrained array of SFIXED type +--2008 function LUT_VALUE(N,WH,WL:INTEGER) return SFIXED_VECTOR is +--2008 variable RESULT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL); + function LUT_VALUE(N,WH,WL:INTEGER) return wSFIXED_VECTOR is + variable RESULT:wSFIXED_VECTOR(0 to N/4-1); + begin + RESULT(0):=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + for J in 1 to N/4-1 loop + RESULT(J):=TO_SFIXED(-COS(-2.0*MATH_PI*REAL(J)/REAL(N))+2.0**(WL-1),WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + if RESULT(J)=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL) then + RESULT(J):=TO_SFIXED(-1.0+2.0**WL,WH,WL)(WH-1 downto WL); + end if; + end loop; + return RESULT; + end; + + signal JKD:UNSIGNED(JK'range):=(others=>'0'); + signal KC,KS:UNSIGNED(JK'range):=(others=>'0');--!! + signal DC,C,DS,S:SFIXED(WH-1 downto WL):=(others=>'0'); +--2008 signal LUT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL):=LUT_VALUE(N,WH,WL); + signal LUT:wSFIXED_VECTOR(0 to N/4-1):=LUT_VALUE(N,WH,WL); + attribute rom_style:STRING; + attribute rom_style of LUT:signal is STYLE; + signal RC,RS:BOOLEAN:=FALSE; + signal MC,MS:STD_LOGIC:='0'; + signal CS1,SS1,CS2,SS2:BOOLEAN:=FALSE; + signal W_RE,W_IM:SFIXED((W'high+1)/2-1 downto W'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--!! +--2008 KC<=JK when JK(JK'high-1)='0' else (not JK)+1; +--2008 KS<=(not JK)+1 when JK(JK'high-1)='0' else JK; + if JK(JK'high-1)='0' then + KC<=JK; + KS<=(not JK)+1; + else + KC<=(not JK)+1; + KS<=JK; + end if; + JKD<=JK; + if (JKD and TO_UNSIGNED(2**(JK'length-2)-1,JK'length))=0 then --mask first two MSBs of JK + RC<=JKD(JK'high-1)='1'; + RS<=JKD(JK'high-1)='0'; + else + RC<=FALSE; + RS<=FALSE; + end if; + DC<=LUT(TO_INTEGER(KC and TO_UNSIGNED(2**(KC'length-2)-1,KC'length))); + DS<=LUT(TO_INTEGER(KS and TO_UNSIGNED(2**(KS'length-2)-1,KS'length))); + if RC then + C<=(others=>'0'); + MC<='0'; + else + C<=DC; + MC<='1'; + end if; + if RS then + S<=(others=>'0'); + MS<='0'; + else + S<=DS; + MS<='1'; + end if; + CS1<=JKD(JK'high)=JKD(JK'high-1); + SS1<=(JKD(JK'high)='1') xor INV_FFT; + CS2<=CS1; + SS2<=SS1; + end if; + end process; + + i0:if SEPARATE_SIGN generate +--2008 W.RE<=MC&C; +--2008 W.IM<=MS&S; + W(W'length/2-1+W'low downto W'low)<=CFIXED(MC&C); + W(W'high downto W'length/2+W'low)<=CFIXED(MS&S); + CS<=CS2; + SS<=SS2; +-- else generate + end generate; + i1:if not SEPARATE_SIGN generate + signal WRE,WIM:SFIXED(WH downto WL):=(others=>'0'); + attribute keep:STRING; + attribute keep of WRE:signal is "yes"; + attribute keep of WIM:signal is "yes"; + signal ZERO:SFIXED(WH downto WL):=TO_SFIXED(0.0,WH,WL); + begin + WRE<=MC&C; + WIM<=MS&S; + + process(CLK) + begin + if rising_edge(CLK) then + CS<=CS2; + SS<=SS2; + CZ<=WRE(WRE'high)='0'; + SZ<=WIM(WIM'high)='0'; + end if; + end process; + ar:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WRE, + SUB=>CS2, +--2008 P=>W.RE); -- P=±B + P=>W_RE); -- P=±B + ai:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WIM, + SUB=>SS2, +--2008 P=>W.IM); -- P=±B + P=>W_IM); -- P=±B + W(W'length/2-1+W'low downto W'low)<=CFIXED(W_RE); + W(W'high downto W'length/2+W'low)<=CFIXED(W_IM); +-- end; + end generate; + +--!! b2:entity work.BDELAY generic map(SIZE=>3-BOOLEAN'pos(SEPARATE_SIGN)) + b2:entity work.BDELAY generic map(SIZE=>4-BOOLEAN'pos(SEPARATE_SIGN)) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- else generate + i1:if SPLIT_RADIX>0 generate + begin + i0:if SEPARATE_SIGN generate +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + end generate; +-- else generate + ii:if not SEPARATE_SIGN generate + begin +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + CZ<=(SPLIT_RADIX=N/4) or (SPLIT_RADIX=3*N/4); + SZ<=(SPLIT_RADIX=0) or (SPLIT_RADIX=N/2); +-- end; + end generate; + VO<=VI; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3 +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Complex Multiplier Using 3 DSP48E2s +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3 is -- LATENCY=6 + generic(ROUNDING:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED; -- I.RE'length and I.IM'length<27 + W:in CFIXED; -- W must be (1 downto -16) or (1 downto -17) + CS,SS,CZ,SZ:in BOOLEAN:=FALSE; + VI:in BOOLEAN; + O:out CFIXED; + VO:out BOOLEAN); +end CM3; + +architecture TEST of CM3 is + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute loc:STRING; + +--2008 constant HMAX:INTEGER:=MAX(I.RE'high,I.IM'high)+MAX(W.RE'high,W.IM'high)+3; +--2008 constant LMIN:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(I.RE'low,I.IM'low)+work.COMPLEX_FIXED_PKG.MIN(W.RE'low,W.IM'low); + constant HMAX:INTEGER:=(I'high+1)/2-1+(W'high+1)/2-1+3; + constant LMIN:INTEGER:=I'low/2+W'low/2; + +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,1) downto MAX(W.RE'low,-16)); +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,0) downto MAX(W.RE'low,-17)); +--2008 signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'low+17,1) downto W.RE'low); -- we only have 18 bits max to work with +--2008 signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); +--2008 signal IRE1D,IRE2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); +--2008 signal IIM1D,IIM2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W'low/2+17,1) downto W'low/2); -- we only have 18 bits max to work with + signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal IRE,IRE1D,IRE2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM,IIM1D,IIM2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal CS2D,SS2D:BOOLEAN; + signal C0S1:BOOLEAN:=FALSE; + signal P1,P2,P3:SFIXED(HMAX downto LMIN); + signal P2D:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal C1,C2,C3:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal AC1,AC2:STD_LOGIC_VECTOR(29 downto 0); + signal BC1:STD_LOGIC_VECTOR(17 downto 0); + signal PC1,PC2:STD_LOGIC_VECTOR(47 downto 0); +--2008 signal A_ZERO:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal A_ZERO:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal B_ZERO:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal C_ZERO:SFIXED(HMAX downto LMIN):=TO_SFIXED(0.0,HMAX,LMIN); + signal BR,BI:BOOLEAN; + signal iO:CFIXED(O'range); +begin +--!! +--2008 WRE<=RESIZE(W.RE,WRE); + WRE<=RESIZE(RE(W),WRE); +--!! WRE<=TO_SFIXED(1.0-2.0**WRE'low,WRE) when W.RE=TO_SFIXED(1.0,W.RE) else RESIZE(W.RE,WRE); +--!! +--2008 WIM<=RESIZE(W.IM,WIM); + WIM<=RESIZE(IM(W),WIM); + process(CLK) + begin + if rising_edge(CLK) then + WRE1D<=WRE; +--2008 IRE1D<=I.RE; +--2008 IIM1D<=I.IM; + IRE1D<=RE(I); + IIM1D<=IM(I); +--2008 C0S1<=CZ and (W.IM(W.IM'high)='0'); + C0S1<=CZ and (W(W'high)='0'); +--!! + NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! if WRE1D=TO_SFIXED(-1.0,WRE1D) then +--!! for K in NWRE2D'range loop +--!! NWRE2D(K)<=not WRE1D(K); +--!! end loop; +--!! else +--!! NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! end if; +--!! + IRE2D<=IRE1D; + IIM2D<=IIM1D; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and C0S1 then + if (W'low/2=-17) and C0S1 then + C1<=RESIZE(SHIFT_LEFT(IRE1D+IIM1D,1),C1); + else + C1<=TO_SFIXED(0.0,C1); + end if; + end if; + end process; + + IRE<=RE(I); + IIM<=IM(I); + dsp1:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"00101", -- (D+A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110000101", -- PCOUT=-C-(D+A1)*B2 +--2008 A=>I.RE, + A=>IRE, + B=>WIM, + C=>C1, +--2008 D=>I.IM, + D=>IIM, + ACOUT=>AC1, + BCOUT=>BC1, + P=>P1, + PCOUT=>PC1); + +-- C2<=TO_SFIXED(2.0**(O.RE'low-1),C2) when ROUNDING else TO_SFIXED(0.0,C2); + BR<=W(W'length/2-1+W'low)='0'; + BI<=W(W'high)='0'; + cd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.RE(W.RE'high)='0', + I=>BR, + O=>CS2D); + sd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.IM(W.IM'high)='0', + I=>BI, + O=>SS2D); + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and CS2D=SS2D then + if (W'low/2=-17) and CS2D=SS2D then + if CS2D then + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(I.RE,C2); + C2<=RESIZE(SHIFT_LEFT(IRE2D,1),C2); + end if; + else + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(-I.RE,C2); + C2<=RESIZE(-SHIFT_LEFT(IRE2D,1),C2); + end if; + end if; + else + if ROUNDING then +--2008 C2<=TO_SFIXED(2.0**(O.RE'low-1),C2); + C2<=TO_SFIXED(2.0**(O'low/2-1),C2); + else + C2<=TO_SFIXED(0.0,C2); + end if; + end if; + end if; + end process; + + dsp2:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL=>"AD", -- Selects B input to multiplier (AD, B) + B_INPUT=>"CASCADE", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL=>"B", -- Selects input to preadder (A, B) + AREG=>2) -- Pipeline stages for A (0-2) + port map(CLK=>CLK, + INMODE=>"10100", -- (D+B1)*A2 + ALUMODE=>"0000", -- Z+W+X+Y + OPMODE=>"110010101", -- PCOUT=PCIN+C+(D+B1)*A2 + A=>A_ZERO, + B=>B_ZERO, + C=>C2, + D=>WRE1D, + ACIN=>AC1, + BCIN=>BC1, + PCIN=>PC1, + ACOUT=>AC2, + P=>P2, + PCOUT=>PC2); + +-- C3<=RESIZE(SHIFT_RIGHT(P1,-16-W.RE'low),P1); + C3<=P1; + dsp3:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"01101", --5x"0C", -- (D-A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110010101", -- PCOUT=PCIN-C-(D-A1)*B2 + A=>A_ZERO, + B=>NWRE2D, + C=>C3, + D=>IIM2D, + ACIN=>AC2, + PCIN=>PC2, + P=>P3); + + process(CLK) + begin + if rising_edge(CLK) then +--2008 O.RE<=RESIZE(P2,O.RE); + P2D<=P2; + end if; + end process; +--2008 O.IM<=RESIZE(P3,O.IM); +-- O<=RESIZE(TO_CFIXED(P2D,P3),O); + O<=RESIZE(TO_CFIXED(P2D,P3),iO); + + bd:entity work.BDELAY generic map(SIZE=>6) + port map(CLK=>CLK, + I=>VI, + O=>VO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. 3 +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3FFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic Complex Multiplier Stage Module - uses 3 DSP48s/complex multiplication +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3FFT is -- LATENCY=10 + generic(N:INTEGER; + RADIX:INTEGER; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and 1 or 3 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CM3FFT; + +architecture TEST of CM3FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + function STYLE(N:INTEGER) return STRING is + begin + if N>BRAM_THRESHOLD then + return "block"; + else + return "distributed"; + end if; + end; + + function TABLE_LATENCY(SPLIT_RADIX:INTEGER) return INTEGER is + begin + if SPLIT_RADIX=0 then + return 4; + else + return 0; + end if; + end; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + signal CNT:UNSIGNED(L2N-L2R-1 downto 0):=(others=>'0'); + signal I0:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal O0:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + +--!! cd:entity work.CDELAY generic map(SIZE=>3+6) + I0<=ELEMENT(I,0,RADIX); + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, +--2008 I=>I(I'low), +--2008 O=>O(O'low)); + I=>I0, + O=>O0); + O(O'length/RADIX-1+O'low downto O'low)<=CFIXED_VECTOR(O0); + + process(CLK) + begin + if rising_edge(CLK) then + if not VI or (SPLIT_RADIX/=0) then + CNT<=(others=>'0'); + else + CNT<=CNT+1; + end if; + end if; + end process; + +--2008 lk:for J in 1 to I'length-1 generate + lk:for J in 1 to RADIX-1 generate + signal JK:UNSIGNED(L2N-1 downto 0):=(others=>'0'); +--2008 signal W:CFIXED(RE(W_high downto W_low),IM(W_high downto W_low)); + signal W:CFIXED(2*(W_high+1)-1 downto 2*W_low); + signal V,CZ:BOOLEAN; +--2008 signal ID:CFIXED(RE(I(I'low).RE'high downto I(I'low).RE'low),IM(I(I'low).IM'high downto I(I'low).IM'low)); + signal ID:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal IJ:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal OJ:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if SPLIT_RADIX=0 then + if not VI or (CNT=N/RADIX-1) then + JK<=(others=>'0'); + else + JK<=JK+J; + end if; + else + JK<=TO_UNSIGNED(J*SPLIT_RADIX,JK'length); + end if; + end if; + end process; + + ut:entity work.TABLE generic map(N=>N, + INV_FFT=>INV_FFT, + DSP48E=>DSP48E, + STYLE=>STYLE(N/4)) + port map(CLK=>CLK, + JK=>JK, + VI=>VI, + CZ=>CZ, + W=>W, + VO=>V); + + IJ<=ELEMENT(I,J,RADIX); +--!! cd:entity work.CDELAY generic map(SIZE=>3) + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)) + port map(CLK=>CLK, +--2008 I=>I(I'low+J), + I=>IJ, + O=>ID); + + u1:entity work.CM3 generic map(ROUNDING=>ROUNDING, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ID, + W=>W, + CZ=>CZ, + VI=>V, +--2008 O=>O(O'low+J), + O=>OJ, + VO=>open); + O((J+1)*O'length/RADIX-1+O'low downto J*O'length/RADIX+O'low)<=CFIXED_VECTOR(OJ); + end generate; + +--!! bd:entity work.BDELAY generic map(SIZE=>3+6) + bd:entity work.BDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>VI, + O=>VO); + +--!! ud:entity work.UDELAY generic map(SIZE=>3+6) + ud:entity work.UDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>SI, + O=>SO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: PARFFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity PARFFT is + generic(N:INTEGER:=4; + F:INTEGER:=0; + INV_FFT:BOOLEAN:=FALSE; + ROUNDING:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-16; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end PARFFT; + +architecture TEST of PARFFT is + constant I_low:INTEGER:=I'low/2/N; + constant I_high:INTEGER:=I'length/2/N-1+I_low; + constant O_low:INTEGER:=O'low/2/N; + constant O_high:INTEGER:=O'length/2/N-1+O_low; + + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + constant L2N:INTEGER:=LOG2(N); +begin +--2008 assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + + f0:if F=0 generate + begin + l2:if N=2 generate -- FFT2 case + signal I0,I1:CFIXED(2*I_high+1 downto 2*I_low); + signal O0,O1:CFIXED(2*O_high+1 downto 2*O_low); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,2); + I1<=ELEMENT(I,1,2); +-- complex add/sub butterfly with scaling and overflow detection + bf:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I1, + SCALE=>SI(SI'low), + O0=>O0, + O1=>O1, + OVR=>SO(SO'high)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/2-1+O'low downto 0*O'length/2+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/2-1+O'low downto 1*O'length/2+O'low)<=CFIXED_VECTOR(O1); + + process(CLK) + begin + if rising_edge(CLK) then + iSO<=SI(SI'high downto SI'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>1) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=4 generate -- FFT4 case + l4:if N=4 generate -- FFT4 case + signal I0,I1,I2,I3:CFIXED(2*I_high+1 downto 2*I_low); + signal P0,P1,P2,P3,P3S:CFIXED(2*I_high+3 downto 2*I_low); + signal O0,O1,O2,O3,O1S,O3S:CFIXED(2*O_high+1 downto 2*O_low); + signal S:UNSIGNED(SI'range):=(others=>'0'); + signal OVR1,OVR2:UNSIGNED(1 downto 0); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,4); + I1<=ELEMENT(I,1,4); + I2<=ELEMENT(I,2,4); + I3<=ELEMENT(I,3,4); +-- complex add/sub butterflies with scaling and overflow detection + u0:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I2, + SCALE=>SI(SI'low), + O0=>P0, + O1=>P1, + OVR=>OVR1(0)); + + u1:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I1, + I1=>I3, + SCALE=>SI(SI'low), + O0=>P2, + O1=>P3, + OVR=>OVR1(1)); + + process(CLK) + begin + if rising_edge(CLK) then + S<=(OVR1(0) or OVR1(1))&SI(SI'high downto SI'low+1); + end if; + end process; + + u2:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P0, + I1=>P2, + SCALE=>S(S'low), + O0=>O0, + O1=>O2, + OVR=>OVR2(0)); + + P3S<=SWAP(P3); + u3:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P1, + I1=>P3S, + SCALE=>S(S'low), + O0=>O1S, + O1=>O3S, + OVR=>OVR2(1)); + O1<=TO_CFIXED(RE(O1S),IM(O3S)); + O3<=TO_CFIXED(RE(O3S),IM(O1S)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/4-1+O'low downto 0*O'length/4+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/4-1+O'low downto 1*O'length/4+O'low)<=CFIXED_VECTOR(O1); + O((2+1)*O'length/4-1+O'low downto 2*O'length/4+O'low)<=CFIXED_VECTOR(O2); + O((3+1)*O'length/4-1+O'low downto 3*O'length/4+O'low)<=CFIXED_VECTOR(O3); + + SO(SO'high)<=(OVR2(0) or OVR2(1)); + process(CLK) + begin + if rising_edge(CLK) then + iSO<=S(S'high downto S'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=8 generate -- FFT8 case + l8:if N=8 generate -- FFT8 case +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/8/2-(I'high+1)/8/2; + constant X:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,1); -- ModelSim workaround + signal iV:BOOLEAN_VECTOR(0 to 3); +--2008 signal S:UNSIGNED_VECTOR(0 to 3)(SI'range); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:TUV(0 to 3); + signal SS:UNSIGNED(SI'range); + signal P:CFIXED_VECTOR(I'high+8*2*X downto I'low); + signal VP:BOOLEAN; + signal SP:UNSIGNED(SI'range); + signal oV:BOOLEAN_VECTOR(0 to 1); +--2008 signal oS:UNSIGNED_VECTOR(0 to 1)(SO'range); + signal oS:TUV(0 to 1); + begin + s1:for K in 0 to 3 generate +--2008 signal II:CFIXED_VECTOR(0 to 1)(RE(I(0).RE'high downto I(0).RE'low),IM(I(0).IM'high downto I(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 1)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); + signal II:CFIXED_VECTOR(4*(I_high+1)-1 downto 4*I_low); + signal OO:CFIXED_VECTOR(4*(I_high+1+2*X)-1 downto 4*I_low); + signal OO0,OO1:CFIXED(2*(I_high+1+2*X)-1 downto 2*I_low); + signal P0,P1:CFIXED(I'length/8+2*X-1+I'low/8 downto I'low/8); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=I(K); +--2008 II(1)<=I(K+4); + II((0+1)*II'length/2-1+II'low downto 0*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K,8)); + II((1+1)*II'length/2-1+II'low downto 1*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K+4,8)); + p2:entity work.PARFFT generic map(N=>2, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>iV(K), + SO=>S(K)); + OO0<=ELEMENT(OO,0,2); + OO1<=ELEMENT(OO,1,2); + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>OO(0), +--2008 O=>P(2*K+0)); + I=>OO0, + O=>P0); + ck:entity work.CKCM generic map(DSP48E=>DSP48E, + M=>K, + ROUNDING=>ROUNDING, + CONJUGATE=>INV_FFT) + port map(CLK=>CLK, +--2008 I=>OO(1), +--2008 O=>P(2*K+1)); + I=>OO1, + O=>P1); + P((2*K+1)*P'length/8-1+P'low downto (2*K+0)*P'length/8+P'low)<=CFIXED_VECTOR(P0); + P((2*K+2)*P'length/8-1+P'low downto (2*K+1)*P'length/8+P'low)<=CFIXED_VECTOR(P1); + end generate; + SS(SI'high)<=S(0)(SI'high) or S(1)(SI'high) or S(2)(SI'high) or S(3)(SI'high) when iV(0) else '0'; + SS(SI'high-1 downto SI'low)<=S(0)(SI'high-1 downto SI'low); + ud:entity work.UDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>SS, + O=>SP); + bd:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>iV(0), + O=>VP); + s2:for K in 0 to 1 generate +--2008 signal II:CFIXED_VECTOR(0 to 3)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 3)(RE(O(0).RE'high downto O(0).RE'low),IM(O(0).IM'high downto O(0).IM'low)); + signal II:CFIXED_VECTOR((P'high+1)/2-1 downto P'low/2); + signal OO:CFIXED_VECTOR((O'high+1)/2-1 downto O'low/2); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=P(K+0); +--2008 II(1)<=P(K+2); +--2008 II(2)<=P(K+4); +--2008 II(3)<=P(K+6); + II((0+1)*II'length/4-1+II'low downto 0*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+0,8)); + II((1+1)*II'length/4-1+II'low downto 1*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+2,8)); + II((2+1)*II'length/4-1+II'low downto 2*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+4,8)); + II((3+1)*II'length/4-1+II'low downto 3*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+6,8)); + p2:entity work.PARFFT generic map(N=>4, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VP, + SI=>SP, + O=>OO, + VO=>oV(K), + SO=>oS(K)); +--2008 O(K+0)<=OO(0); +--2008 O(K+2)<=OO(1); +--2008 O(K+4)<=OO(2); +--2008 O(K+6)<=OO(3); + O((K+0+1)*O'length/8-1+O'low downto (K+0)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,0,4)); + O((K+2+1)*O'length/8-1+O'low downto (K+2)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,1,4)); + O((K+4+1)*O'length/8-1+O'low downto (K+4)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,2,4)); + O((K+6+1)*O'length/8-1+O'low downto (K+6)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,3,4)); + end generate; + VO<=oV(0); + SO(SO'high downto SO'high-1)<=oS(0)(SO'high downto SO'high-1) or oS(1)(SO'high downto SO'high-1) when oV(0) else "00"; + SO(SO'high-2 downto SO'low)<=oS(0)(SO'high-2 downto SO'low); +-- end; + end generate; +-- elsif N=2**L2N generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation + ln:if (N>8) and (N=2**L2N) generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/N/2-(I'high+1)/N/2; + constant X1:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-2); -- ModelSim workaround + constant X2:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-1); -- ModelSim workaround + function MUL_LATENCY(N:INTEGER) return INTEGER is + begin + return 6; + end; + function LATENCY(N:INTEGER) return INTEGER is + begin + return LOG2(N)*4-6; + end; +--2008 signal IU:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal U,UD:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); + signal IU:CFIXED_VECTOR((I'high+1)/2-1 downto I'low/2); + signal U,UD:CFIXED_VECTOR((I'high+1)/2-1+N/2*2*X2 downto I'low/2); + signal SU,SUD:UNSIGNED(SI'range); + signal VU,VU4D:BOOLEAN; +--2008 signal ZO:CFIXED_MATRIX(0 to N/4-1)(0 to 1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(2*2*(I_high+X1+1)-1 downto 2*2*I_low); -- unconstrained array of CFIXED_VECTOR + signal ZO:CFIXED_MATRIX(0 to N/4-1); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); +--2008 signal S1:UNSIGNED_VECTOR(0 to 1)(SI'range); + signal S1:TUV(0 to 1); + signal S1I:UNSIGNED(SI'range); +--2008 signal S2:UNSIGNED_VECTOR(0 to N/4-1)(SI'range); + signal S2:TUV(0 to N/4-1); + signal S2I:UNSIGNED(SI'range):=(others=>'0'); +--2008 signal S:UNSIGNED_VECTOR(0 to N/2-1)(SI'range); + signal S:TUV(0 to N/2-1); + begin + lk:for K in 0 to N/2-1 generate +--2008 IU(K)<=I(I'low+2*K); + IU((K+1)*IU'length/N*2-1+IU'low downto K*IU'length/N*2+IU'low)<=CFIXED_VECTOR(ELEMENT(I,2*K,N)); + end generate; + pu:entity work.PARFFT generic map(N=>N/2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IU, + VI=>VI, + SI=>SI, + O=>U, + VO=>VU, + SO=>SU); + du:for K in 0 to N/2-1 generate + signal UK,UDK:CFIXED((UD'high+1)/N*2-1 downto UD'low/N*2); + begin + UK<=ELEMENT(U,K,N/2); + cd:entity work.CDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+1-LATENCY(N/2))--3) -- when CMUL latency is 6 + port map(CLK=>CLK, +--2008 I=>U(K), +--2008 O=>UD(K)); + I=>UK, + O=>UDK); + UD((K+1)*UD'length/N*2-1+UD'low downto K*UD'length/N*2+UD'low)<=CFIXED_VECTOR(UDK); + end generate; + u4:entity work.UDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>SU, + O=>SUD); + b5:entity work.BDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>VU, + O=>VO); + ll:for L in 0 to 1 generate +--2008 signal IZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal Z,OZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + signal IZ:CFIXED_VECTOR((I'high+1)/4-1 downto I'low/4); + signal Z,OZ:CFIXED_VECTOR((I'high+1)/4-1+N/4*2*X1 downto I'low/4); + signal SZ:UNSIGNED(SI'range); + signal SM:UNSIGNED(SI'range); + signal VZ:BOOLEAN; + begin + li:for J in 0 to N/4-1 generate +--2008 IZ(J)<=I(I'low+4*J+2*L+1); + IZ(2*(J+1)*(I_high-I_low+1)-1+IZ'low downto 2*J*(I_high-I_low+1)+IZ'low)<=CFIXED_VECTOR(ELEMENT(I,4*J+2*L+1,N)); + end generate; + pe:entity work.PARFFT generic map(N=>N/4, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IZ, + VI=>VI, + SI=>SI, + O=>Z, + VO=>VZ, + SO=>SZ); + me:entity work.CM3FFT generic map(N=>N, + RADIX=>N/4, + SPLIT_RADIX=>2*L+1, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>Z, + VI=>VZ, + SI=>SZ, + O=>OZ, + VO=>open, + SO=>S1(L)); + lo:for J in 0 to N/4-1 generate +--2008 ZO(J)(L)<=OZ(J); + ZO(J)((L+1)*ZO(J)'length/2-1+ZO(J)'low downto L*ZO(J)'length/2+ZO(J)'low)<=CFIXED_VECTOR(ELEMENT(OZ,J,N/4)); + end generate; + end generate; + S1I<=S1(0) or S1(1); + l2:for J in 0 to N/4-1 generate +--2008 signal O2:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal IE,IO:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal OE,OO:CFIXED_VECTOR(0 to 1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal O2:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal IE,IO:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal OE,OO:CFIXED_VECTOR(2*2*(O_high+1)-1 downto 2*2*O_low); + begin + p2:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ZO(J), + VI=>TRUE, + SI=>S1I, + O=>O2, + VO=>open, + SO=>S2(J)); +--2008 IE(0)<=UD(J); +--2008 IE(1)<=O2(0); + IE((0+1)*IE'length/2-1+IE'low downto 0*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(UD,J,N/2)); + IE((1+1)*IE'length/2-1+IE'low downto 1*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(O2,0,2)); + pe:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IE, + VI=>TRUE, + SI=>S2I, + O=>OE, + VO=>open, + SO=>S(2*J)); +--2008 O(O'low+J)<=OE(0); +--2008 O(O'low+J+N/2)<=OE(1); +--2008 IO(0)<=UD(J+N/4); +--2008 IO(1).RE<=O2(1).IM; +--2008 IO(1).IM<=O2(1).RE; +-- O((J+1)*O'length/N-1+O'low downto J*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); +-- O((J+N/2+1)*O'length/N-1+O'low downto (J+N/2)*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + O(2*(J+1)*(O_high-O_low+1)-1+O'low downto 2*J*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); + O(2*(J+N/2+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/2)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + IO((0+1)*IO'length/2-1+IO'low downto 0*IO'length/2+IO'low)<=CFIXED_VECTOR(ELEMENT(UD,J+N/4,N/2)); + IO((1+1)*IO'length/2-1+IO'low downto 1*IO'length/2+IO'low)<=CFIXED_VECTOR(TO_CFIXED(IM(ELEMENT(O2,1,2)),RE(ELEMENT(O2,1,2)))); + po:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IO, + VI=>TRUE, + SI=>S2I, + O=>OO, + VO=>open, + SO=>S(2*J+1)); + ii:if INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(1).RE; +--2008 O(O'low+J+N/4).IM<=OO(0).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(0).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(1).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- end; + end generate; +-- else generate + id:if not INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(0).RE; +--2008 O(O'low+J+N/4).IM<=OO(1).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(1).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(0).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- end; + end generate; + end generate; + process(S2) + variable vS2:UNSIGNED(SI'range); + begin + vS2:=SUD; + for K in S2'range loop + vS2:=vS2 or S2(K); + end loop; + S2I<=vS2; + end process; + process(S) + variable vS:UNSIGNED(SI'range); + begin + vS:=(others=>'0'); + for K in S'range loop + vS:=vS or S(K); + end loop; + SO<=vS; + end process; +-- end; + end generate; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=N/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.PARFFT generic map(N=>G, + F=>0, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ?? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: INPUT_SWAP.vhd +-- / / Date Last Modified: 14 February 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: INPUT_SWAP +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Input Order Swap Module for Systolic FFT +-- The module takes N samples, I'length per clock, in natural input order +-- and outputs them in natural transposed order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity INPUT_SWAP is + generic(N:INTEGER; -- N must be a power of 2 + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + USE_CB:BOOLEAN:=TRUE); -- if FALSE use alternate architecture + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; -- I'length must be a divisor of N, so it is also a power of 2 + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end INPUT_SWAP; + +architecture TEST of INPUT_SWAP is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs in last stage + + function RS(K:INTEGER) return STRING is + begin + if K) of CFIXED_VECTOR(I'range); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + + i0:if USE_CB or (L2N<=2*L2R) generate + constant SIZE:INTEGER:=L2N/L2R; -- floor(LOG2(N)/LOG2(RADIX)) + + signal V:BOOLEAN_VECTOR(0 to SIZE-1); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE-1)(SI'range); +--2008 signal D:CFIXED_MATRIX(0 to SIZE-1)(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:UNSIGNED_VECTOR(0 to SIZE-1); + signal D:iCFIXED_MATRIX(0 to SIZE-1); + begin + D(D'low)<=I; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-2 generate + bc:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>RADIX**K, + INPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K/RADIX), -- this helps reduce + OUTPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K mod RADIX**(SIZE-2)), -- RAM count and + SHORTEN_VO_BY=>(RADIX-1)*RADIX**K mod ((RADIX-1)*RADIX**(SIZE-2))) -- latency by N/RADIX/RADIX-1 clocks + port map(CLK=>CLK, + I=>D(K), + VI=>V(K), + SI=>S(K), + O=>D(K+1), + VO=>V(K+1), + SO=>S(K+1)); + end generate; +--Last stage, it becomes a trivial assignment if F=0 + bl:block + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SI'range); + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + lj:for J in OV'range generate +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin + bc:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>RADIX**(SIZE-1)) + port map(CLK=>CLK, +--2008 I=>D(D'high)(I'low+G*J+0 to I'low+G*J+G-1), + I=>D(D'high)(I'length/H*(J+1)-1+I'low downto I'length/H*J+I'low), + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>OV(J), + SO=>OS(J)); + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(K); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+1)-1+OO'low downto O'length/SSR*K+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); + end block; +--2008 end; + end generate; +--2008 else generate + i1:if (not USE_CB) and (L2N>2*L2R) generate + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + signal WSEL:UNSIGNED(LOG2(WCNT'length)-1 downto 0):=TO_UNSIGNED(0,LOG2(RCNT'length)); + signal RSEL:UNSIGNED(LOG2(RCNT'length)-1 downto 0):=TO_UNSIGNED(L2N-2*L2R,LOG2(RCNT'length)); +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal OV:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + if RSEL'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + WA<=ROTATE_LEFT(WCNT,TO_INTEGER(WSEL)); + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + RA<=ROTATE_LEFT(RCNT,TO_INTEGER(RSEL)); + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); + IO<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>OV); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+5) + port map(CLK=>CLK, + I=>SI, + O=>S); + + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>IO, + VI=>OV, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SYSTOLIC_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SYSTOLIC_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Systolic FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity SYSTOLIC_FFT is + generic(N:INTEGER; + SSR:INTEGER; --93 + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end SYSTOLIC_FFT; + +architecture TEST of SYSTOLIC_FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB and PARFFT in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs and PARFFTsin last stage + constant SIZE:INTEGER:=(L2N-1)/L2R; -- ceil(LOG2(N)/LOG2(RADIX)), number of stages +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/2/SSR-(I'high+1)/2/SSR; + +-- constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((SIZE-1)*L2R,BIT_GROWTH); + constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); +--2008 signal D:CFIXED_MATRIX(0 to SIZE)(I'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(O'range); -- unconstrained array of CFIXED_VECTOR + signal D:CFIXED_MATRIX(0 to SIZE); + signal V:BOOLEAN_VECTOR(0 to SIZE); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE)(SI'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); --93 + signal S:UNSIGNED_VECTOR(0 to SIZE); + +-- constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(L2N,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal OO:CFIXED_VECTOR(O'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal OO:CFIXED_VECTOR(O'range); +begin +--2008 lj:for J in I'range generate +--2008 D(D'low)(J)<=RESIZE(I(J),D(D'low)(J)); + lj:for J in 0 to SSR-1 generate + D(D'low)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(I,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-1 generate + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(K*L2R,BIT_GROWTH); + constant XO:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((K+1)*L2R,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal DM,DB,DO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XO downto I(I'low).RE'low),IM(I(I'low).IM'high+XO downto I(I'low).IM'low)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal DM,DB,DO:CFIXED_VECTOR(I'high+2*SSR*XO downto I'low); + signal VM,VB:BOOLEAN; + signal SM,SB:UNSIGNED(SI'range); + begin +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(K)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(K),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, --93 + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(K), + SI=>S(K), + O=>DM, + VO=>VM, + SO=>SM); + cm:entity work.CM3FFT generic map(N=>N/(RADIX**K), + RADIX=>RADIX, --93 + INV_FFT=>FALSE, + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DM, + VI=>VM, + SI=>SM, + O=>DB, + VO=>VB, + SO=>SB); + + bc:entity work.CB generic map(SSR=>RADIX, --93 + F=>F*BOOLEAN'pos(K=SIZE-1), + PACKING_FACTOR=>N/(RADIX**(K+2))*BOOLEAN'pos(KBRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DB, + VI=>VB, + SI=>SB, + O=>DO, + VO=>V(K+1), + SO=>S(K+1)); +--2008 lo:for J in 0 to I'length-1 generate +--2008 D(K+1)(J)<=RESIZE(DO(DO'low+J),D(K+1)(J)); + lo:for J in 0 to SSR-1 generate + D(K+1)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(DO,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + end generate; +--last PARFFT stage +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(D'high)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(D'high),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, + F=>F, + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>VO, + SO=>SO); + lo:for J in 0 to H-1 generate + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(OO'low+K+G*J); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+G*J+1)-1+OO'low downto O'length/SSR*(K+G*J)+OO'low); + end generate; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DS.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DS +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Transposed Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DS is -- LATENCY=0 when N=2*SSR else LATENCY=N/SSR+1 + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DS; + +architecture TEST of DS is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + + function RS(K:INTEGER) return STRING is + begin + if K) of UNSIGNED(RCNT'range); --93 + function IDENTITY(K:INTEGER) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(0 to K-1);--93 (LOG2(K)-1 downto 0); + begin + for J in RESULT'range loop + RESULT(J):=TO_UNSIGNED(J,RESULT(J)'length); + end loop; + return RESULT; + end; + + function PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT((A'length/L2R-1-J)*L2R+K+F):=A(J*L2R+K); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(K):=A(A'length/L2R*L2R+K); + end loop; + end loop; + return RESULT; + end; + + function INVERSE_PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT(J*L2R+K):=A((A'length/L2R-1-J)*L2R+K+F); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(A'length/L2R*L2R+K):=A(K); + end loop; + end loop; + return RESULT; + end; + +--2008 signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1)(LOG2(WCNT'length)-1 downto 0):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); +--2008 signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1)(LOG2(RCNT'length)-1 downto 0):=IDENTITY(RCNT'length); + signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); + signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1):=IDENTITY(RCNT'length); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i0:if L2N-L2R<2 generate + O<=I; + VO<=VI; + SO<=SI; +--2008 else generate + end generate; + i1:if L2N-L2R>=2 generate + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + RSEL<=PERMUTE(WSEL); + end if; + RCNT<=RCNT+1; + else + RCNT<=(others=>'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in WCNT'range loop + WA(K)<=WCNT(TO_INTEGER(WSEL(K))); + end loop; + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in RCNT'range loop + RA(K)<=RCNT(TO_INTEGER(RSEL(K))); + end loop; + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + type iCFIXED_MATRIX is array(NATURAL range <>) of CFIXED_VECTOR(I'range); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); +--2008 O(K)<=Q; + O<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>VO); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX+1) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DSN.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DSN +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Natural Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DSN is + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DSN; + +architecture TEST of DSN is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + constant H:INTEGER:=RADIX/G; +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i1:if L2N<2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SI'range); + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SO'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SO'range); --93 + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + sd:entity work.DS generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + lk:for K in 0 to H-1 generate +----2008 signal II,OO:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal II,OO:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + begin + li:for J in 0 to G-1 generate +--2008 II(J)<=IO(IO'low+K+H*J); + II(I'length/SSR*(J+1)-1+II'low downto I'length/SSR*J+II'low)<=IO(I'length/SSR*(K+H*J+1)-1+I'low downto I'length/SSR*(K+H*J)+I'low); + end generate; + ci:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OO, + VO=>OV(K), + SO=>OS(K)); + lo:for J in 0 to G-1 generate +----2008 O(O'low+K*G+J)<=OO(J); + O(O'length/SSR*(K*G+J+1)-1+O'low downto O'length/SSR*(K*G+J)+O'low)<=OO(O'length/SSR*(J+1)-1+OO'low downto O'length/SSR*J+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); +--2008 end; + end generate; +--2008 elsif L2N=2*L2R generate + i2:if L2N=2*L2R generate + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>O, + VO=>VO, + SO=>SO); +--2008 else generate + end generate; + i3:if L2N>2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>N/RADIX/RADIX, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + + sd:entity work.DS generic map(N=>N/RADIX, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>IO, + VI=>V, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: VECTOR_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: VECTOR_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Top Level Test Module for SYSTOLIC_FFT +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity VECTOR_FFT is + generic(SSR:INTEGER:=8;--4; + N:INTEGER:=16384;--8192;--4096;--1024; + I_high:INTEGER:=0; + I_low:INTEGER:=-17; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; +--2008 I:in CFIXED_VECTOR(0 to RADIX-1)(RE(I_high downto I_low),IM(I_high downto I_low)); + I:in CFIXED_VECTOR(SSR*2*(I_high-I_low+1)-1 downto 0); + VI:in BOOLEAN; + SI:in UNSIGNED(LOG2(N)-1 downto 0); +--2008 O:out CFIXED_VECTOR(0 to RADIX-1)(RE(O_high downto O_low),IM(O_high downto O_low)); + O:out CFIXED_VECTOR(SSR*2*(O_high-O_low+1)-1 downto 0); + VO:out BOOLEAN; + SO:out UNSIGNED(LOG2(N)-1 downto 0)); +end VECTOR_FFT; + +architecture TEST of VECTOR_FFT is + function TO_SFIXED(S:STD_LOGIC_VECTOR;I:SFIXED) return SFIXED is + variable R:SFIXED(I'range); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + + function TO_STD_LOGIC_VECTOR(S:SFIXED) return STD_LOGIC_VECTOR is + variable R:STD_LOGIC_VECTOR(S'length-1 downto 0); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + +--2008 signal II:CFIXED_VECTOR(I'range)(RE(I_high downto I_low),IM(I_high downto I_low)); + signal II:CFIXED_VECTOR(I'range); + signal V,VOFFT,VODS:BOOLEAN; + signal S,SFFT,SODS:UNSIGNED(SI'range); +--2008 signal OFFT,ODS:CFIXED_VECTOR(O'range)(RE(O_high downto O_low),IM(O_high downto O_low)); + signal OFFT,ODS:CFIXED_VECTOR(O'range); +begin + u0:entity work.INPUT_SWAP generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>II, + VO=>V, + SO=>S); + + u1:entity work.SYSTOLIC_FFT generic map(N=>N, + SSR=>SSR, --93 + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OFFT, + VO=>VOFFT, + SO=>SFFT); + + u2:entity work.DSN generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>OFFT, + VI=>VOFFT, + SI=>SFFT, + O=>O, + VO=>VO, + SO=>SO); +-- O<=OFFT; +-- VO<=VOFFT; +-- SO<=SFFT; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.COMPLEX_FIXED_PKG.all; + +entity WRAPPER_VECTOR_FFT is + generic(SSR:INTEGER:=8; + N:INTEGER:=512; + L2N:INTEGER:=9; -- L2N must be set equal to log2(N)!!! + I_high:INTEGER:=0; + I_low:INTEGER:=-15; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-15; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + CE:in STD_LOGIC:='1'; -- not used, for SysGen only + I:in STD_LOGIC_VECTOR(2*SSR*(I_high-I_low+1)-1 downto 0); + VI:in STD_LOGIC; + SI:in STD_LOGIC_VECTOR(L2N-1 downto 0):=(L2N-1 downto 0=>'0'); -- can be left unconnected if internal scaling is not used, must be a (LOG2(N)-1 downto 0) port + O:out STD_LOGIC_VECTOR(2*SSR*(O_high-O_low+1)-1 downto 0); + VO:out STD_LOGIC; + SO:out STD_LOGIC_VECTOR(L2N-1 downto 0)); -- can be left unconnected if internal overflow is not possible, must be a (LOG2(N)-1 downto 0) port +end WRAPPER_VECTOR_FFT; + +architecture WRAPPER of WRAPPER_VECTOR_FFT is +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if KSSR, + N=>N, + I_high=>I_high, + I_low=>I_low, + W_high=>W_high, + W_low=>W_low, + O_high=>O_high, + O_low=>O_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB, + DSP48E=>DSP48E) -- 1 for DSP48E1, 2 for DSP48E2 + port map(CLK=>CLK, + I=>II, + VI=>VII, + SI=>SII, + O=>OO, + VO=>VOO, + SO=>SOO); + O<=STD_LOGIC_VECTOR(OO); + VO<='1' when VOO else '0'; + SO<=STD_LOGIC_VECTOR(SOO); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity WRAPPER_VECTOR_FFT_29450ae4dbd3eb51515dab58c9ac6776 is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 3; + N : integer := 8; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(2 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(2 downto 0); + CLK : in std_logic; + CE : in std_logic + ); +end WRAPPER_VECTOR_FFT_29450ae4dbd3eb51515dab58c9ac6776; +architecture structural of WRAPPER_VECTOR_FFT_29450ae4dbd3eb51515dab58c9ac6776 is + signal I_net : std_logic_vector(255 downto 0); + signal VI_net : std_logic; + signal SI_net : std_logic_vector(2 downto 0); + signal O_net : std_logic_vector(431 downto 0); + signal VO_net : std_logic; + signal SO_net : std_logic_vector(2 downto 0); + signal CLK_net : std_logic; + signal CE_net : std_logic; + component WRAPPER_VECTOR_FFT is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 3; + N : integer := 8; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(2 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(2 downto 0); + CLK : in std_logic; + CE : in std_logic + ); + end component; +begin + I_net <= I; + VI_net <= VI; + SI_net <= SI; + O <= O_net; + VO <= VO_net; + SO <= SO_net; + CLK_net <= CLK; + CE_net <= CE; + WRAPPER_VECTOR_FFT_inst : WRAPPER_VECTOR_FFT + generic map( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 3, + N => 8, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map( + I => I_net, + VI => VI_net, + SI => SI_net, + O => O_net, + VO => VO_net, + SO => SO_net, + CLK => CLK_net, + CE => CE_net + ); +end structural; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlslice.vhd +-- +-- Description : VHDL description of a block that sets the output to a +-- specified range of the input bits. The output is always +-- set to an unsigned type with it's binary point at zero. +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x8_xlslice is + generic ( + new_msb : integer := 9; -- position of new msb + new_lsb : integer := 1; -- position of new lsb + x_width : integer := 16; -- Width of x input + y_width : integer := 8); -- Width of y output + port ( + x : in std_logic_vector (x_width-1 downto 0); + y : out std_logic_vector (y_width-1 downto 0)); +end ssr_8x8_xlslice; + +architecture behavior of ssr_8x8_xlslice is +begin + y <= x(new_msb downto new_lsb); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_965a32611a is + port ( + in0 : in std_logic_vector((16 - 1) downto 0); + in1 : in std_logic_vector((16 - 1) downto 0); + y : out std_logic_vector((32 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_965a32611a; +architecture behavior of sysgen_concat_965a32611a +is + signal in0_1_23: unsigned((16 - 1) downto 0); + signal in1_1_27: unsigned((16 - 1) downto 0); + signal y_2_1_concat: unsigned((32 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_d1aaeed629 is + port ( + input_port : in std_logic_vector((16 - 1) downto 0); + output_port : out std_logic_vector((16 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_d1aaeed629; +architecture behavior of sysgen_reinterpret_d1aaeed629 +is + signal input_port_1_40: signed((16 - 1) downto 0); + signal output_port_5_5_force: unsigned((16 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_signed(input_port); + output_port_5_5_force <= signed_to_unsigned(input_port_1_40); + output_port <= unsigned_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_4035468568 is + port ( + input_port : in std_logic_vector((27 - 1) downto 0); + output_port : out std_logic_vector((27 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_4035468568; +architecture behavior of sysgen_reinterpret_4035468568 +is + signal input_port_1_40: unsigned((27 - 1) downto 0); + signal output_port_5_5_force: signed((27 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_unsigned(input_port); + output_port_5_5_force <= unsigned_to_signed(input_port_1_40); + output_port <= signed_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_7ca5184bef is + port ( + in0 : in std_logic_vector((32 - 1) downto 0); + in1 : in std_logic_vector((32 - 1) downto 0); + in2 : in std_logic_vector((32 - 1) downto 0); + in3 : in std_logic_vector((32 - 1) downto 0); + in4 : in std_logic_vector((32 - 1) downto 0); + in5 : in std_logic_vector((32 - 1) downto 0); + in6 : in std_logic_vector((32 - 1) downto 0); + in7 : in std_logic_vector((32 - 1) downto 0); + y : out std_logic_vector((256 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_7ca5184bef; +architecture behavior of sysgen_concat_7ca5184bef +is + signal in0_1_23: unsigned((32 - 1) downto 0); + signal in1_1_27: unsigned((32 - 1) downto 0); + signal in2_1_31: unsigned((32 - 1) downto 0); + signal in3_1_35: unsigned((32 - 1) downto 0); + signal in4_1_39: unsigned((32 - 1) downto 0); + signal in5_1_43: unsigned((32 - 1) downto 0); + signal in6_1_47: unsigned((32 - 1) downto 0); + signal in7_1_51: unsigned((32 - 1) downto 0); + signal y_2_1_concat: unsigned((256 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + in2_1_31 <= std_logic_vector_to_unsigned(in2); + in3_1_35 <= std_logic_vector_to_unsigned(in3); + in4_1_39 <= std_logic_vector_to_unsigned(in4); + in5_1_43 <= std_logic_vector_to_unsigned(in5); + in6_1_47 <= std_logic_vector_to_unsigned(in6); + in7_1_51 <= std_logic_vector_to_unsigned(in7); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39) & unsigned_to_std_logic_vector(in5_1_43) & unsigned_to_std_logic_vector(in6_1_47) & unsigned_to_std_logic_vector(in7_1_51)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg.vhd new file mode 100644 index 0000000..770ff70 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg.vhd @@ -0,0 +1,95 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register without +-- an init value and a clear. SRLC32E components are used. The +-- initial value is always 0 +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRLC32s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg; + +architecture structural of synth_reg is + component srlc33e + generic (width : integer:=16; + latency : integer :=8); + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); + end component; + + function calc_num_srlc33es (latency : integer) + return integer + is + variable remaining_latency : integer; + variable result : integer; + begin + result := latency / 33; + + remaining_latency := latency - (result * 33); + -- If latency is not an even multiple of 33 then add one more + -- srlc33e to the pipeline + if (remaining_latency /= 0) then + result := result + 1; + end if; + + return result; + end; + + + constant complete_num_srlc33es : integer := latency / 33; + constant num_srlc33es : integer := calc_num_srlc33es(latency); + constant remaining_latency : integer := latency - (complete_num_srlc33es * 33); + -- Array for std_logic_vectors + type register_array is array (num_srlc33es downto 0) of + std_logic_vector(width-1 downto 0); + signal z : register_array; + +begin + + z(0) <= i; + complete_ones : if complete_num_srlc33es > 0 generate + srlc33e_array: for i in 0 to complete_num_srlc33es-1 generate + delay_comp : srlc33e + generic map (width => width, + latency => 33) + port map (clk => clk, + ce => ce, + d => z(i), + q => z(i+1)); + + end generate; + end generate; + + partial_one : if remaining_latency > 0 generate + last_srlc33e : srlc33e + generic map (width => width, + latency => remaining_latency) + port map (clk => clk, + ce => ce, + d => z(num_srlc33es-1), + q => z(num_srlc33es)); + end generate; + o <= z(num_srlc33es); +end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg_reg.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg_reg.vhd new file mode 100644 index 0000000..5d837de --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg_reg.vhd @@ -0,0 +1,64 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_reg.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRL16s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg_reg; + +architecture behav of synth_reg_reg is + type reg_array_type is array (latency downto 0) of std_logic_vector(width -1 downto 0); + signal reg_bank : reg_array_type := (others => (others => '0')); + signal reg_bank_in : reg_array_type := (others => (others => '0')); + attribute syn_allow_retiming : boolean; + attribute syn_srlstyle : string; + attribute syn_allow_retiming of reg_bank : signal is true; + attribute syn_allow_retiming of reg_bank_in : signal is true; + attribute syn_srlstyle of reg_bank : signal is "registers"; + attribute syn_srlstyle of reg_bank_in : signal is "registers"; +begin -- behav + + latency_eq_0: if latency = 0 generate + o <= i; + end generate latency_eq_0; + + latency_gt_0: if latency >= 1 generate + o <= reg_bank(latency); + reg_bank(0) <= i; + + sync_loop: for sync_idx in latency downto 1 generate + sync_proc: process (clk) + begin -- process sync_proc + if clk'event and clk = '1' then -- rising clock edge + if clr = '1' then + reg_bank(sync_idx) <= (others => '0'); + elsif ce = '1' then + reg_bank(sync_idx) <= reg_bank(sync_idx-1); + end if; + end if; + end process sync_proc; + end generate sync_loop; + end generate latency_gt_0; + end behav; + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg_w_init.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg_w_init.vhd new file mode 100644 index 0000000..34bfa2e --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/synth_reg_w_init.vhd @@ -0,0 +1,98 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_w_init.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register with +-- an initial value. The register has clr and ce pins and +-- is implemented using flip-flops (i.e., not SRL16s). +-- +-- Mod. History : Delayed input .1 ns so that there isn't a setup +-- violation in the fdse or fdre Unisim models. +-- : Changed VHDL so that initial register is passed as a bit +-- vector generic value, instead of the const_pkg. +-- +-- Mod. Dates : 8/10/2001 +-- 3/19/2003 +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000"; + latency: integer := 1 + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end synth_reg_w_init; + +architecture structural of synth_reg_w_init is + component single_reg_w_init + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; -- end single_reg_w_init + + -- 1D array used to connect all the register together + signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); + signal dly_clr: std_logic; +begin + latency_eq_0: if (latency = 0) generate + o <= i; + end generate; -- end latency_eq_0 + + latency_gt_0: if (latency >= 1) generate + -- Delayed input 200 ps so that there isn't a setup violation in the + -- fdse or fdre Unisim models + dly_i((latency + 1) * width - 1 downto latency * width) <= i + after 200 ps; + dly_clr <= clr after 200 ps; + + fd_array: for index in latency downto 1 generate + reg_comp: single_reg_w_init + generic map ( + width => width, + init_index => init_index, + init_value => init_value + ) + port map ( + clk => clk, + i => dly_i((index + 1) * width - 1 downto index * width), + o => dly_i(index * width - 1 downto (index - 1) * width), + ce => ce, + clr => dly_clr + ); + end generate; -- end fd_array + + o <= dly_i(width - 1 downto 0); + end generate; -- end latency_gt_0 +end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/xlclockdriver_rd.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/xlclockdriver_rd.vhd new file mode 100644 index 0000000..92017d4 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssr_fft_8x8/xlclockdriver_rd.vhd @@ -0,0 +1,338 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlclockdriver.vhd +-- +-- Date : 10/1/99 +-- +-- Description : VHDL description of a clock enable generator block. +-- This code is synthesizable. +-- +-- Assumptions : period >= 1 +-- +-- Mod. History : Removed one shot & OR gate +-- If period is power of 2 a 1-bit smaller counter +-- is used and no sync clear +-- : Logic needed for use_bufg generic added +-- : Initial ce output is now 0 instead of 1 +-- Enable pulse now occurs at the end of the sample +-- period, instead of at the start +-- : Added pipeline registers +-- : added OR gate for sysclr to work properly +-- +-- Mod. Dates : 7/26/2001 +-- : 8/05/2001 +-- : 1/02/2002 +-- : 11/30/2004 +-- : 4/11/2005 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +entity xlclockdriver is + generic ( + period: integer := 2; + log_2_period: integer := 0; + pipeline_regs: integer := 5; + use_bufg: integer := 0 + ); + port ( + sysclk: in std_logic; + sysclr: in std_logic; + sysce: in std_logic; + clk: out std_logic; + clr: out std_logic; + ce: out std_logic; + ce_logic: out std_logic + ); +end xlclockdriver; + +architecture behavior of xlclockdriver is + component bufg + port ( + i: in std_logic; + o: out std_logic + ); + end component; + + component synth_reg_w_init + generic ( + width: integer; + init_index: integer; + init_value: bit_vector; + latency: integer + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; + + -- Returns the size of an unsigned integer + -- if power_of_2 is true return value is one less + function size_of_uint(inp: integer; power_of_2: boolean) + return integer + is + constant inp_vec: std_logic_vector(31 downto 0) := + integer_to_std_logic_vector(inp,32, xlUnsigned); + variable result: integer; + begin + result := 32; + for i in 0 to 31 loop + if inp_vec(i) = '1' then + result := i; + end if; + end loop; + if power_of_2 then + return result; + else + return result+1; + end if; + end; + + -- Returns boolean which says if 'inp' is a power of two + function is_power_of_2(inp: std_logic_vector) + return boolean + is + constant width: integer := inp'length; + variable vec: std_logic_vector(width - 1 downto 0); + variable single_bit_set: boolean; + variable more_than_one_bit_set: boolean; + variable result: boolean; + begin + vec := inp; + single_bit_set := false; + more_than_one_bit_set := false; + + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if width > 0 then + for i in 0 to width - 1 loop + if vec(i) = '1' then + if single_bit_set then + more_than_one_bit_set := true; + end if; + single_bit_set := true; + end if; + end loop; + end if; + if (single_bit_set and not(more_than_one_bit_set)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Returns initial value for pipeline registers + function ce_reg_init_val(index, period : integer) + return integer + is + variable result: integer; + begin + result := 0; + if ((index mod period) = 0) then + result := 1; + end if; + return result; + end; + + -- Returns the remainder(num_pipeline_regs/period) + 1 + function remaining_pipe_regs(num_pipeline_regs, period : integer) + return integer + is + variable factor, result: integer; + begin + factor := (num_pipeline_regs / period); + result := num_pipeline_regs - (period * factor) + 1; + return result; + end; + + -- Calculate the min + function sg_min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + constant max_pipeline_regs : integer := 8; + constant pipe_regs : integer := 5; + + -- Check if requested pipeline regs are greater than the max amount + constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); + constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); + + constant period_floor: integer := max(2, period); + constant power_of_2_counter: boolean := + is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); + constant cnt_width: integer := + size_of_uint(period_floor, power_of_2_counter); + constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); + + signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); + signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); + signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0); + signal internal_ce: std_logic_vector(0 downto 0); + signal internal_ce_logic: std_logic_vector(0 downto 0); + signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); +begin + -- Pass through the system clock and clear + clk <= sysclk; + clr <= sysclr; + + -- Clock Number Counter + cntr_gen: process(sysclk) + begin + if sysclk'event and sysclk = '1' then + if (sysce = '1') then + if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then + clk_num <= (others => '0'); + else + clk_num <= clk_num + 1; + end if; + end if; + end if; + end process; + + -- Clear logic for counter + clr_gen: process(clk_num, sysclr) + begin + if power_of_2_counter then + cnt_clr(0) <= sysclr; + else + -- Counter does not reset when clk_num = a power of 2 + if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 + or sysclr = '1') then + cnt_clr(0) <= '1'; + else + cnt_clr(0) <= '0'; + end if; + end if; + end process; + + clr_reg: synth_reg_w_init + generic map ( + width => 1, + init_index => 0, + init_value => b"0000", + latency => 1 + ) + port map ( + i => cnt_clr, + ce => sysce, + clr => sysclr, + clk => sysclk, + o => cnt_clr_dly + ); + + -- Clock enable generation + pipelined_ce : if period > 1 generate + ce_gen: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec(num_pipeline_regs) <= '1'; + else + ce_vec(num_pipeline_regs) <= '0'; + end if; + end process; + ce_pipeline: for index in num_pipeline_regs downto 1 generate + ce_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec(index-1 downto index-1) + ); + end generate; -- i + internal_ce <= ce_vec(0 downto 0); + end generate; + + -- Clock enable generation + pipelined_ce_logic: if period > 1 generate + ce_gen_logic: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec_logic(num_pipeline_regs) <= '1'; + else + ce_vec_logic(num_pipeline_regs) <= '0'; + end if; + end process; + ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate + ce_logic_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec_logic(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec_logic(index-1 downto index-1) + ); + end generate; -- i + internal_ce_logic <= ce_vec_logic(0 downto 0); + end generate; + + + use_bufg_true: if period > 1 and use_bufg = 1 generate + -- Clock enable with bufg + ce_bufg_inst: bufg + port map ( + i => internal_ce(0), + o => ce + ); + ce_bufg_inst_logic: bufg + port map ( + i => internal_ce_logic(0), + o => ce_logic + ); + end generate; + + use_bufg_false: if period > 1 and (use_bufg = 0) generate + -- Clock enable without bufg + ce <= internal_ce(0) and sysce; + ce_logic <= internal_ce_logic(0) and sysce; + end generate; + + generate_system_clk: if period = 1 generate + ce <= sysce; + ce_logic <= sysce; + end generate; +end architecture behavior; + + + + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssrfft_8x8.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssrfft_8x8.vhd new file mode 100644 index 0000000..b788869 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/ssrfft_8x8.vhd @@ -0,0 +1,196 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity ssrfft_8x8 is + Generic + ( + NFFT : Integer := 8; + SSR : Integer := 8; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (SSR*2*B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (SSR*2*B-1 downto 0); + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end entity; + +architecture rtl of ssrfft_8x8 is + +-- SSR FFT 8x8. +component ssr_8x8 is + port ( + -- Clock signal. + clk : in std_logic; + + -- Input data. + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_scale : in std_logic_vector( 3-1 downto 0 ); + + -- Output data. + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0); + o_scale : out std_logic_vector( 3-1 downto 0 ) + ); +end component; + +-- Vectors with individual I,Q samples. +type data_v is array (SSR-1 downto 0) of std_logic_vector (B-1 downto 0); +signal din_iv : data_v; +signal din_qv : data_v; +signal dout_iv : data_v; +signal dout_qv : data_v; + +-- Vector with individual I,Q samples (fft out full precision). +type data_vf is array (SSR-1 downto 0) of std_logic_vector (27-1 downto 0); +signal dout_ivf : data_vf; +signal dout_qvf : data_vf; + +-- I,Q parts of input and output. +signal din_i : std_logic_vector (SSR*B-1 downto 0); +signal din_q : std_logic_vector (SSR*B-1 downto 0); +signal dout_i : std_logic_vector (SSR*B-1 downto 0); +signal dout_q : std_logic_vector (SSR*B-1 downto 0); + +-- FFT scale. +signal o_scale : std_logic_vector (2 downto 0); + +-- FFT output valid. +signal o_axis_tvalid : std_logic; + +-- FFT data output. +signal o_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); + +-- Registers. +signal scale_reg_i : std_logic_vector (2 downto 0); +signal qout_reg_i : unsigned (2 downto 0); + +begin + +-- Registers. +scale_reg_i <= SCALE_REG (2 downto 0); + +-- Full-precision output: 27 bits. Required output: 16 bits. +-- Quantization selection from 0 to 11. +qout_reg_i <= (others => '0') when ( unsigned(QOUT_REG) > to_unsigned(11,QOUT_REG'length) ) else + unsigned(QOUT_REG(2 downto 0)); + +-- Input/output data. +din_i <= s_axis_tdata (SSR*B-1 downto 0); +din_q <= s_axis_tdata (2*SSR*B-1 downto SSR*B); +o_axis_tdata(SSR*B-1 downto 0) <= dout_i; +o_axis_tdata(2*SSR*B-1 downto SSR*B) <= dout_q; + +-- Input/output data to vector. +GEN: for I in 0 to SSR-1 generate + -- Input data to vector. + din_iv(I) <= din_i((I+1)*B-1 downto I*B); + din_qv(I) <= din_q((I+1)*B-1 downto I*B); + + -- Quantization selection. + dout_iv(I) <= dout_ivf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + dout_qv(I) <= dout_qvf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + + -- Output data to vector. + dout_i((I+1)*B-1 downto I*B) <= dout_iv(I); + dout_q((I+1)*B-1 downto I*B) <= dout_qv(I); +end generate GEN; + +-- SSR FFT 8x8. +ssr_8x8_i : ssr_8x8 + port map ( + -- Clock signal. + clk => aclk , + + -- Input data. + i_re_0 => din_iv(0) , + i_re_1 => din_iv(1) , + i_re_2 => din_iv(2) , + i_re_3 => din_iv(3) , + i_re_4 => din_iv(4) , + i_re_5 => din_iv(5) , + i_re_6 => din_iv(6) , + i_re_7 => din_iv(7) , + i_im_0 => din_qv(0) , + i_im_1 => din_qv(1) , + i_im_2 => din_qv(2) , + i_im_3 => din_qv(3) , + i_im_4 => din_qv(4) , + i_im_5 => din_qv(5) , + i_im_6 => din_qv(6) , + i_im_7 => din_qv(7) , + i_valid(0) => s_axis_tvalid , + i_scale => scale_reg_i , + + -- Output data. + o_re_0 => dout_ivf(0) , + o_re_1 => dout_ivf(1) , + o_re_2 => dout_ivf(2) , + o_re_3 => dout_ivf(3) , + o_re_4 => dout_ivf(4) , + o_re_5 => dout_ivf(5) , + o_re_6 => dout_ivf(6) , + o_re_7 => dout_ivf(7) , + o_im_0 => dout_qvf(0) , + o_im_1 => dout_qvf(1) , + o_im_2 => dout_qvf(2) , + o_im_3 => dout_qvf(3) , + o_im_4 => dout_qvf(4) , + o_im_5 => dout_qvf(5) , + o_im_6 => dout_qvf(6) , + o_im_7 => dout_qvf(7) , + o_valid(0) => o_axis_tvalid , + o_scale => o_scale + ); + +-- Assign outputs. +m_axis_tdata <= o_axis_tdata; +m_axis_tvalid <= o_axis_tvalid; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/tb.vhd b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/tb.vhd new file mode 100644 index 0000000..c2445f1 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/ssrfft_8x8/tb.vhd @@ -0,0 +1,224 @@ +-- %%%%%%%%%%%%%%%%%%% Test Description %%%%%%%%%%%%%%%%%%%%% +-- +-- This test is for understanding if moving tvalid makes the +-- block to generate incorrect tlast at the output. +-- +-- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_TEXTIO.ALL; +use STD.TEXTIO.ALL; + +entity tb is +end tb; + +architecture rtl of tb is + +-- DUT. +component ssrfft_8x8 is + Generic + ( + NFFT : Integer := 8; + SSR : Integer := 8; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (SSR*2*B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (SSR*2*B-1 downto 0); + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end component; + +constant NFFT : Integer := 8; +constant SSR : Integer := 8; +constant B : Integer := 16; + +signal aresetn : std_logic; +signal aclk : std_logic; +signal s_axis_tdata : std_logic_vector (SSR*2*B-1 downto 0) := (others => '0'); +signal s_axis_tvalid : std_logic := '0'; + +signal m_axis_tdata : std_logic_vector (SSR*2*B-1 downto 0); +signal m_axis_tvalid : std_logic; + +signal SCALE_REG : std_logic_vector (31 downto 0) := (others => '0'); +signal QOUT_REG : std_logic_vector (31 downto 0) := std_logic_vector(to_unsigned(0,32)); + +-- TB control. +signal rd_start : std_logic := '0'; + +signal i_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); + +signal o_re_0 : std_logic_vector( 16-1 downto 0 ); +signal o_re_1 : std_logic_vector( 16-1 downto 0 ); +signal o_re_2 : std_logic_vector( 16-1 downto 0 ); +signal o_re_3 : std_logic_vector( 16-1 downto 0 ); +signal o_re_4 : std_logic_vector( 16-1 downto 0 ); +signal o_re_5 : std_logic_vector( 16-1 downto 0 ); +signal o_re_6 : std_logic_vector( 16-1 downto 0 ); +signal o_re_7 : std_logic_vector( 16-1 downto 0 ); +signal o_im_0 : std_logic_vector( 16-1 downto 0 ); +signal o_im_1 : std_logic_vector( 16-1 downto 0 ); +signal o_im_2 : std_logic_vector( 16-1 downto 0 ); +signal o_im_3 : std_logic_vector( 16-1 downto 0 ); +signal o_im_4 : std_logic_vector( 16-1 downto 0 ); +signal o_im_5 : std_logic_vector( 16-1 downto 0 ); +signal o_im_6 : std_logic_vector( 16-1 downto 0 ); +signal o_im_7 : std_logic_vector( 16-1 downto 0 ); + +begin + +-- DUT. +DUT : ssrfft_8x8 + Generic map + ( + NFFT => NFFT , + SSR => SSR , + B => B + ) + Port map + ( + -- Reset and clock. + aresetn => aresetn , + aclk => aclk , + + -- AXIS Slave. + s_axis_tdata => s_axis_tdata , + s_axis_tvalid => s_axis_tvalid , + + -- AXIS Master. + m_axis_tdata => m_axis_tdata , + m_axis_tvalid => m_axis_tvalid , + + -- Registers. + SCALE_REG => SCALE_REG , + QOUT_REG => QOUT_REG + ); + +-- Input data. +s_axis_tdata <= i_im_7 & i_im_6 & i_im_5 & i_im_4 & i_im_3 & i_im_2 & i_im_1 & i_im_0 & + i_re_7 & i_re_6 & i_re_5 & i_re_4 & i_re_3 & i_re_2 & i_re_1 & i_re_0; + +-- Output data. +o_re_0 <= m_axis_tdata (1*B-1 downto 0*B); +o_re_1 <= m_axis_tdata (2*B-1 downto 1*B); +o_re_2 <= m_axis_tdata (3*B-1 downto 2*B); +o_re_3 <= m_axis_tdata (4*B-1 downto 3*B); +o_re_4 <= m_axis_tdata (5*B-1 downto 4*B); +o_re_5 <= m_axis_tdata (6*B-1 downto 5*B); +o_re_6 <= m_axis_tdata (7*B-1 downto 6*B); +o_re_7 <= m_axis_tdata (8*B-1 downto 7*B); +o_im_0 <= m_axis_tdata (9*B-1 downto 8*B); +o_im_1 <= m_axis_tdata (10*B-1 downto 9*B); +o_im_2 <= m_axis_tdata (11*B-1 downto 10*B); +o_im_3 <= m_axis_tdata (12*B-1 downto 11*B); +o_im_4 <= m_axis_tdata (13*B-1 downto 12*B); +o_im_5 <= m_axis_tdata (14*B-1 downto 13*B); +o_im_6 <= m_axis_tdata (15*B-1 downto 14*B); +o_im_7 <= m_axis_tdata (16*B-1 downto 15*B); + +-- Main TB. +process +begin + aresetn <= '0'; + wait for 250 ns; + aresetn <= '1'; + + wait for 300 ns; + + rd_start <= '1'; + wait for 110 ns; + rd_start <= '0'; + wait for 220 ns; + rd_start <= '1'; + wait for 490 ns; + rd_start <= '0'; + wait for 100 ns; + rd_start <= '1'; + + wait for 20 us; + +end process; + +-- Data process. +process + variable I : Integer := 0; + + begin + + for K in 0 to 200 loop + for J in 0 to 0 loop + while rd_start = '0' loop + wait until rising_edge(aclk); + s_axis_tvalid <= '0'; + end loop; + wait until rising_edge(aclk); + s_axis_tvalid <= '1'; + i_re_0 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_1 <= std_logic_vector(to_signed(20000,i_re_0'length)); + i_re_2 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_3 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_4 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_5 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_6 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_7 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_0 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_1 <= std_logic_vector(to_signed(20000,i_re_0'length)); + i_im_2 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_3 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_4 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_5 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_6 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_7 <= std_logic_vector(to_signed(0,i_re_0'length)); + + I := I + 1; + end loop; + + while rd_start = '0' loop + wait until rising_edge(aclk); + s_axis_tvalid <= '0'; + end loop; + end loop; + +end process; + +-- Clock. +process +begin + aclk <= '0'; + wait for 5 ns; + aclk <= '1'; + wait for 5 ns; +end process; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v2/src/tb/tb.sv b/firmware/ip/axis_pfb_readout_v2/src/tb/tb.sv new file mode 100644 index 0000000..47777ab --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/src/tb/tb.sv @@ -0,0 +1,361 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +wire s_axis_tready; +reg s_axis_tvalid; +reg [4*32-1:0] s_axis_tdata; + +wire m0_axis_tvalid; +reg [31:0] m0_axis_tdata; +wire m1_axis_tvalid; +reg [31:0] m1_axis_tdata; +wire m2_axis_tvalid; +reg [31:0] m2_axis_tdata; +wire m3_axis_tvalid; +reg [31:0] m3_axis_tdata; + + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Input data. +reg [31:0] din_ii [0:7]; + +// Test bench control. +reg tb_data = 0; +reg tb_data_done= 0; +reg tb_write_out= 0; + + +generate +genvar ii; +for (ii = 0; ii < 8; ii = ii + 1) begin + assign s_axis_tdata[32*ii +: 32] = din_ii[ii]; +end +endgenerate + +// axi_mst_0. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_pfb_readout_v2 + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // s_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input samples. + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tready (s_axis_tready ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for CH0 output. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + + // M_AXIS for CH1 output. + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tdata (m1_axis_tdata ), + + // M_AXIS for CH2 output. + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tdata (m2_axis_tdata ), + + // M_AXIS for CH3 output. + .m3_axis_tvalid (m3_axis_tvalid ), + .m3_axis_tdata (m3_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("###################"); + $display("### Program DDS ###"); + $display("###################"); + $display("t = %0t", $time); + + // FREQ. + //for (int i=0; i<8; i = i+1) begin + // data_wr = freq_calc(100, i+10); + // axi_mst_0_agent.AXI4LITE_WRITE_BURST(i*4, prot, data_wr, resp); + // #10; + //end + + // FREQ0. + data_wr = freq_calc(100, 3.8); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); + #10; + + // FREQ1. + data_wr = freq_calc(100, 92); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(1*4, prot, data_wr, resp); + #10; + + // FREQ2. + data_wr = freq_calc(100, 13.5); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(2*4, prot, data_wr, resp); + #10; + + // FREQ3. + data_wr = freq_calc(100, 12.2); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(3*4, prot, data_wr, resp); + #10; + + // FREQ4. + data_wr = freq_calc(100, 87); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); + #10; + + // FREQ5. + data_wr = freq_calc(100, 95); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); + #10; + + // FREQ6. + data_wr = freq_calc(100, 92); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(6*4, prot, data_wr, resp); + #10; + + // FREQ7. + data_wr = freq_calc(100, 93); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(7*4, prot, data_wr, resp); + #10; + + // OUTSEL. + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(8*4, prot, data_wr, resp); + #10; + + // CH0SEL. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(9*4, prot, data_wr, resp); + #10; + + // CH1SEL. + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(10*4, prot, data_wr, resp); + #10; + + // CH2SEL. + data_wr = 4; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(11*4, prot, data_wr, resp); + #10; + + // CH3SEL. + data_wr = 7; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(12*4, prot, data_wr, resp); + #10; + + $display("###############################"); + $display("### Start Recording Outputs ###"); + $display("###############################"); + $display("t = %0t", $time); + + tb_data <= 1; + tb_write_out <= 1; + wait (tb_data_done); + tb_write_out <= 0; + +end + +// Input data. +initial begin + int fd; + int i; + bit signed [15:0] vali, valq; + s_axis_tvalid <= 0; + s_axis_tdata <= 0; + + // Open file with Coefficients. + fd = $fopen("../../../../../tb/data_iq.txt","r"); + + wait(tb_data); + @(posedge aclk); + + i = 0; + while ($fscanf(fd,"%d,%d", vali, valq) == 2) begin + //$display("T = %d, i = %d, I = %d, Q = %d", $time, i, vali, valq); + din_ii[i] <= {valq,vali}; + i = i + 1; + if (i == 4) begin + i = 0; + @(posedge aclk); + s_axis_tvalid <= 1; + end + end + + @(posedge aclk); + s_axis_tvalid <= 0; + tb_data_done <= 1; + +end + +// Write output into file. +initial begin + int fd0, fd1, fd2, fd3; + int i; + shortint real_d0, imag_d0; + shortint real_d1, imag_d1; + shortint real_d2, imag_d2; + shortint real_d3, imag_d3; + + // Output file. + fd0 = $fopen("../../../../../tb/dout_0.csv","w"); + fd1 = $fopen("../../../../../tb/dout_1.csv","w"); + fd2 = $fopen("../../../../../tb/dout_2.csv","w"); + fd3 = $fopen("../../../../../tb/dout_3.csv","w"); + + // Data format. + $fdisplay(fd0, "valid, real, imag"); + $fdisplay(fd1, "valid, real, imag"); + $fdisplay(fd2, "valid, real, imag"); + $fdisplay(fd3, "valid, real, imag"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + real_d0 = m0_axis_tdata[15:0]; + imag_d0 = m0_axis_tdata[31:16]; + real_d1 = m1_axis_tdata[15:0]; + imag_d1 = m1_axis_tdata[31:16]; + real_d2 = m2_axis_tdata[15:0]; + imag_d2 = m2_axis_tdata[31:16]; + real_d3 = m3_axis_tdata[15:0]; + imag_d3 = m3_axis_tdata[31:16]; + $fdisplay(fd0,"%d,%d,%d",m0_axis_tvalid,real_d0,imag_d0); + $fdisplay(fd1,"%d,%d,%d",m1_axis_tvalid,real_d1,imag_d1); + $fdisplay(fd2,"%d,%d,%d",m2_axis_tvalid,real_d2,imag_d2); + $fdisplay(fd3,"%d,%d,%d",m3_axis_tvalid,real_d3,imag_d3); + end + + $display("Closing file, t = %0t", $time); + $fclose(fd0); + $fclose(fd1); + $fclose(fd2); + $fclose(fd3); +end + +always begin + s_axi_aclk <= 0; + #10; + s_axi_aclk <= 1; + #10; +end + +always begin + aclk <= 0; + #5; + aclk <= 1; + #5; +end + +// Function to compute frequency register. +function [31:0] freq_calc; + input int fclk; + input real f; + + // All input frequencies are in MHz. + real fs,temp; + fs = fclk; + temp = f/fs*2**30; + freq_calc = {int'(temp),2'b00}; +endfunction + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v2/xgui/axis_pfb_readout_v2_v1_0.tcl b/firmware/ip/axis_pfb_readout_v2/xgui/axis_pfb_readout_v2_v1_0.tcl new file mode 100644 index 0000000..9eea8a8 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v2/xgui/axis_pfb_readout_v2_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + ipgui::add_param $IPINST -name "INTERLEAVED_INPUT" + +} + +proc update_PARAM_VALUE.INTERLEAVED_INPUT { PARAM_VALUE.INTERLEAVED_INPUT } { + # Procedure called to update INTERLEAVED_INPUT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.INTERLEAVED_INPUT { PARAM_VALUE.INTERLEAVED_INPUT } { + # Procedure called to validate INTERLEAVED_INPUT + return true +} + + +proc update_MODELPARAM_VALUE.INTERLEAVED_INPUT { MODELPARAM_VALUE.INTERLEAVED_INPUT PARAM_VALUE.INTERLEAVED_INPUT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.INTERLEAVED_INPUT}] ${MODELPARAM_VALUE.INTERLEAVED_INPUT} +} + diff --git a/firmware/ip/axis_pfb_readout_v3/README b/firmware/ip/axis_pfb_readout_v3/README new file mode 100644 index 0000000..3d574ed --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/README @@ -0,0 +1,9 @@ +This block has 3 main components: +* Polyphse Filter Bank with 64 channels, 50 % overlap, x32 decimation. +* Channel selector to grab 4 channels from the PFB. +* Four phase-coherent DDSs with frequency/phase settings. + +The 4 outputs are independent from each other. The same PFB channels can +be routed multiple times to individual outputs, and apply a different +DDS down-conversion frequency. + diff --git a/firmware/ip/axis_pfb_readout_v3/component.xml b/firmware/ip/axis_pfb_readout_v3/component.xml new file mode 100644 index 0000000..1b723ac --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/component.xml @@ -0,0 +1,1567 @@ + + + user.org + user + axis_pfb_readout_v3 + 1.0 + + + m0_axis + + + + + + + TDATA + + + m0_axis_tdata + + + + + TVALID + + + m0_axis_tvalid + + + + + + m1_axis + + + + + + + TDATA + + + m1_axis_tdata + + + + + TVALID + + + m1_axis_tvalid + + + + + + m2_axis + + + + + + + TDATA + + + m2_axis_tdata + + + + + TVALID + + + m2_axis_tvalid + + + + + + m3_axis + + + + + + + TDATA + + + m3_axis_tdata + + + + + TVALID + + + m3_axis_tvalid + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m0_axis:m1_axis:m2_axis:m3_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_pfb_readout_v3 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 9bf5fb0e + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_pfb_readout_v3 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 9bf5fb0e + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 0891018f + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m0_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m2_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m2_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m3_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m3_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N + N + 64 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/pfb/fir/coef/fir_7.coe + coe + + + src/pfb/fir/coef/fir_6.coe + coe + + + src/pfb/fir/coef/fir_5.coe + coe + + + src/pfb/fir/coef/fir_4.coe + coe + + + src/pfb/fir/coef/fir_3.coe + coe + + + src/pfb/fir/coef/fir_2.coe + coe + + + src/pfb/fir/coef/fir_1.coe + coe + + + src/pfb/fir/coef/fir_0.coe + coe + + + src/dds/dds_0/dds_0.xci + xci + CELL_NAME_pfb_readout_i/ddsprod_v_i/GEN_ddsprod[0].ddsprod_i/dds_top_i/dds_i + + + src/pfb/fir/fir_7/fir_7.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir7_i + + + src/pfb/fir/fir_6/fir_6.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir6_i + + + src/pfb/fir/fir_5/fir_5.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir5_i + + + src/pfb/fir/fir_4/fir_4.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir4_i + + + src/pfb/fir/fir_3/fir_3.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir3_i + + + src/pfb/fir/fir_2/fir_2.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir2_i + + + src/pfb/fir/fir_1/fir_1.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir1_i + + + src/pfb/fir/fir_0/fir_0.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir0_i + + + src/dds/cmult_16x16.v + verilogSource + + + src/dds/cmult_sub.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/dds/mult_32x32.v + verilogSource + + + src/pfb_readout.v + verilogSource + + + src/pfb/pfb_switch.v + verilogSource + + + src/dds/dds_ctrl.sv + systemVerilogSource + + + src/dds/dds_top.sv + systemVerilogSource + + + src/ddsprod.sv + systemVerilogSource + + + src/ddsprod_v.sv + systemVerilogSource + + + src/pfb/firs.sv + systemVerilogSource + + + src/pfb/pfb.sv + systemVerilogSource + + + src/pfb/pfb_chsel.sv + systemVerilogSource + + + src/pfb/pfb_reorder.sv + systemVerilogSource + + + src/pfb/pfb_swap.sv + systemVerilogSource + + + src/pfb/pfb_top.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/conv_pkg.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/pfb/fft/framing.vhd + vhdlSource + + + src/pfb/pfb_ctrl_pkg.vhd + vhdlSource + + + src/pfb/pfb_cfg.vhd + vhdlSource + + + src/pfb/pfb_ctrl.vhd + vhdlSource + + + src/pfb/pfb_framing.vhd + vhdlSource + + + src/pfb/pimod_pfb.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/single_reg_w_init.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/srl33e.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/ssr_8x64_entity_declarations.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/xlclockdriver_rd.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/ssr_8x64.vhd + vhdlSource + + + src/pfb/fft/ssrfft_8x64_sync.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/synth_reg.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/synth_reg_reg.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/synth_reg_w_init.vhd + vhdlSource + + + src/pfb/fft/tlast_gen.vhd + vhdlSource + + + src/pfb/zn_nb.vhd + vhdlSource + + + src/axis_pfb_readout_v3.v + verilogSource + CHECKSUM_dbf48f9f + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/pfb/fir/coef/fir_7.coe + coe + + + src/pfb/fir/coef/fir_6.coe + coe + + + src/pfb/fir/coef/fir_5.coe + coe + + + src/pfb/fir/coef/fir_4.coe + coe + + + src/pfb/fir/coef/fir_3.coe + coe + + + src/pfb/fir/coef/fir_2.coe + coe + + + src/pfb/fir/coef/fir_1.coe + coe + + + src/pfb/fir/coef/fir_0.coe + coe + + + src/dds/dds_0/dds_0.xci + xci + CELL_NAME_pfb_readout_i/ddsprod_v_i/GEN_ddsprod[0].ddsprod_i/dds_top_i/dds_i + + + src/pfb/fir/fir_7/fir_7.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir7_i + + + src/pfb/fir/fir_6/fir_6.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir6_i + + + src/pfb/fir/fir_5/fir_5.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir5_i + + + src/pfb/fir/fir_4/fir_4.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir4_i + + + src/pfb/fir/fir_3/fir_3.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir3_i + + + src/pfb/fir/fir_2/fir_2.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir2_i + + + src/pfb/fir/fir_1/fir_1.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir1_i + + + src/pfb/fir/fir_0/fir_0.xci + xci + CELL_NAME_pfb_readout_i/pfb_top_i/pfb_i/firs_i/fir0_i + + + src/dds/cmult_16x16.v + verilogSource + + + src/dds/cmult_sub.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/dds/mult_32x32.v + verilogSource + + + src/pfb_readout.v + verilogSource + + + src/pfb/pfb_switch.v + verilogSource + + + src/dds/dds_ctrl.sv + systemVerilogSource + + + src/dds/dds_top.sv + systemVerilogSource + + + src/ddsprod.sv + systemVerilogSource + + + src/ddsprod_v.sv + systemVerilogSource + + + src/pfb/firs.sv + systemVerilogSource + + + src/pfb/pfb.sv + systemVerilogSource + + + src/pfb/pfb_chsel.sv + systemVerilogSource + + + src/pfb/pfb_reorder.sv + systemVerilogSource + + + src/pfb/pfb_swap.sv + systemVerilogSource + + + src/pfb/pfb_top.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/conv_pkg.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/pfb/fft/framing.vhd + vhdlSource + + + src/pfb/pfb_ctrl_pkg.vhd + vhdlSource + + + src/pfb/pfb_cfg.vhd + vhdlSource + + + src/pfb/pfb_ctrl.vhd + vhdlSource + + + src/pfb/pfb_framing.vhd + vhdlSource + + + src/pfb/pimod_pfb.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/single_reg_w_init.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/srl33e.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/ssr_8x64_entity_declarations.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/xlclockdriver_rd.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/ssr_8x64.vhd + vhdlSource + + + src/pfb/fft/ssrfft_8x64_sync.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/synth_reg.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/synth_reg_reg.vhd + vhdlSource + + + src/pfb/fft/ssr_fft_8x64/synth_reg_w_init.vhd + vhdlSource + + + src/pfb/fft/tlast_gen.vhd + vhdlSource + + + src/pfb/zn_nb.vhd + vhdlSource + + + src/axis_pfb_readout_v3.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_pfb_readout_v3_v1_0.tcl + tclSource + CHECKSUM_0891018f + XGUI_VERSION_2 + + + + AXIS PFB Readout, 64 Channels, 4 outputs, V3. + + + N + N + 64 + + + Component_Name + axis_pfb_readout_v3_v1_0 + + + + + + zynquplus + + + /UserIP + + AXIS PFB Readout V3 + package_project + 3 + 2024-03-06T15:43:08Z + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_pfb_readout_v3/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..88ccced --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,215 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "axi_mst_0", + "component_reference": "xilinx.com:ip:axi_vip:1.1", + "ip_revision": "14", + "gen_directory": "../project_1/project_1.gen/sources_1/ip/axi_mst_0", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "axi_mst_0", "resolve_type": "user", "usage": "all" } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ], + "INTERFACE_MODE": [ { "value": "MASTER", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "AWUSER_WIDTH": [ { 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b/firmware/ip/axis_pfb_readout_v3/src/axi_slv.vhd new file mode 100644 index 0000000..fc0856d --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/axi_slv.vhd @@ -0,0 +1,532 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + ID0_REG : out std_logic_vector (15 downto 0); + ID1_REG : out std_logic_vector (15 downto 0); + ID2_REG : out std_logic_vector (15 downto 0); + ID3_REG : out std_logic_vector (15 downto 0); + PINC0_REG : out std_logic_vector (31 downto 0); + POFF0_REG : out std_logic_vector (31 downto 0); + PINC1_REG : out std_logic_vector (31 downto 0); + POFF1_REG : out std_logic_vector (31 downto 0); + PINC2_REG : out std_logic_vector (31 downto 0); + POFF2_REG : out std_logic_vector (31 downto 0); + PINC3_REG : out std_logic_vector (31 downto 0); + POFF3_REG : out std_logic_vector (31 downto 0) + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Output Registers. + ID0_REG <= slv_reg0 (15 downto 0); + ID1_REG <= slv_reg1 (15 downto 0); + ID2_REG <= slv_reg2 (15 downto 0); + ID3_REG <= slv_reg3 (15 downto 0); + PINC0_REG <= slv_reg4; + POFF0_REG <= slv_reg5; + PINC1_REG <= slv_reg6; + POFF1_REG <= slv_reg7; + PINC2_REG <= slv_reg8; + POFF2_REG <= slv_reg9; + PINC3_REG <= slv_reg10; + POFF3_REG <= slv_reg11; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/axis_pfb_readout_v3.v b/firmware/ip/axis_pfb_readout_v3/src/axis_pfb_readout_v3.v new file mode 100644 index 0000000..03dc29f --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/axis_pfb_readout_v3.v @@ -0,0 +1,181 @@ +module axis_pfb_readout_v3 + #( + // Number of channels. + parameter N = 64 + ) + ( + // AXI Slave I/F for configuration. + input s_axi_aclk , + input s_axi_aresetn , + + input [5:0] s_axi_awaddr , + input [2:0] s_axi_awprot , + input s_axi_awvalid , + output s_axi_awready , + + input [31:0] s_axi_wdata , + input [3:0] s_axi_wstrb , + input s_axi_wvalid , + output s_axi_wready , + + output [1:0] s_axi_bresp , + output s_axi_bvalid , + input s_axi_bready , + + input [5:0] s_axi_araddr , + input [2:0] s_axi_arprot , + input s_axi_arvalid , + output s_axi_arready , + + output [31:0] s_axi_rdata , + output [1:0] s_axi_rresp , + output s_axi_rvalid , + input s_axi_rready , + + // s_* and m_* reset/clock. + input aresetn , + input aclk , + + // S_AXIS for input samples + input s_axis_tvalid , + input [4*32-1:0] s_axis_tdata , + + // M_AXIS for CH0 output. + output m0_axis_tvalid , + output [31:0] m0_axis_tdata , + + // M_AXIS for CH1 output. + output m1_axis_tvalid , + output [31:0] m1_axis_tdata , + + // M_AXIS for CH2 output. + output m2_axis_tvalid , + output [31:0] m2_axis_tdata , + + // M_AXIS for CH3 output. + output m3_axis_tvalid , + output [31:0] m3_axis_tdata + ); + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [15:0] ID0_REG ; +wire [15:0] ID1_REG ; +wire [15:0] ID2_REG ; +wire [15:0] ID3_REG ; +wire [31:0] PINC0_REG ; +wire [31:0] POFF0_REG ; +wire [31:0] PINC1_REG ; +wire [31:0] POFF1_REG ; +wire [31:0] PINC2_REG ; +wire [31:0] POFF2_REG ; +wire [31:0] PINC3_REG ; +wire [31:0] POFF3_REG ; + +// Internal valid. +wire valid_int ; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .ID0_REG (ID0_REG ), + .ID1_REG (ID1_REG ), + .ID2_REG (ID2_REG ), + .ID3_REG (ID3_REG ), + .PINC0_REG (PINC0_REG ), + .POFF0_REG (POFF0_REG ), + .PINC1_REG (PINC1_REG ), + .POFF1_REG (POFF1_REG ), + .PINC2_REG (PINC2_REG ), + .POFF2_REG (POFF2_REG ), + .PINC3_REG (PINC3_REG ), + .POFF3_REG (POFF3_REG ) + ); + +// PFB with DDS product. +pfb_readout + #( + // Number of channels. + .N(N), + + // Number of Lanes (Input). + .L(4) + ) + pfb_readout_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input data. + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for output data. + .m_axis_tvalid (valid_int ), + .m0_axis_tdata (m0_axis_tdata ), + .m1_axis_tdata (m1_axis_tdata ), + .m2_axis_tdata (m2_axis_tdata ), + .m3_axis_tdata (m3_axis_tdata ), + + // Registers. + .ID0_REG (ID0_REG ), + .ID1_REG (ID1_REG ), + .ID2_REG (ID2_REG ), + .ID3_REG (ID3_REG ), + .PINC0_REG (PINC0_REG ), + .POFF0_REG (POFF0_REG ), + .PINC1_REG (PINC1_REG ), + .POFF1_REG (POFF1_REG ), + .PINC2_REG (PINC2_REG ), + .POFF2_REG (POFF2_REG ), + .PINC3_REG (PINC3_REG ), + .POFF3_REG (POFF3_REG ) + ); + +// Assign outputs. +assign m0_axis_tvalid = valid_int; +assign m1_axis_tvalid = valid_int; +assign m2_axis_tvalid = valid_int; +assign m3_axis_tvalid = valid_int; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/dds/cmult_16x16.v b/firmware/ip/axis_pfb_readout_v3/src/dds/cmult_16x16.v new file mode 100644 index 0000000..c57b2ba --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/dds/cmult_16x16.v @@ -0,0 +1,46 @@ +module cmult_16x16 + ( + input wire clk , + input wire [15:0] din_i0 , + input wire [15:0] din_q0 , + input wire [15:0] din_i1 , + input wire [15:0] din_q1 , + output wire [31:0] dout_i , + output wire [31:0] dout_q + ); + +/****************/ +/* Architecture */ +/****************/ + +// Real part. +cmult_sub + #( + .op("sub") + ) + cmult_real_i + ( + .clk (clk ), + .a (din_i0 ), + .b (din_i1 ), + .c (din_q0 ), + .d (din_q1 ), + .x (dout_i ) + ); + +// Imaginary part. +cmult_sub + #( + .op("add") + ) + cmult_imag_i + ( + .clk (clk ), + .a (din_i0 ), + .b (din_q1 ), + .c (din_q0 ), + .d (din_i1 ), + .x (dout_q ) + ); + +endmodule diff --git a/firmware/ip/axis_pfb_readout_v3/src/dds/cmult_sub.v b/firmware/ip/axis_pfb_readout_v3/src/dds/cmult_sub.v new file mode 100644 index 0000000..8b4ffe6 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/dds/cmult_sub.v @@ -0,0 +1,82 @@ +module cmult_sub + #( + parameter op = "sub" + ) + ( + input wire clk , + input wire [15:0] a , + input wire [15:0] b , + input wire [15:0] c , + input wire [15:0] d , + output wire [31:0] x + ); + +/***********/ +/* Signals */ +/***********/ +// Input pipeline. +reg signed [15:0] a_r1; +reg signed [15:0] b_r1; +reg signed [15:0] c_r1; +reg signed [15:0] c_r2; +reg signed [15:0] d_r1; +reg signed [15:0] d_r2; + +// Partial products. +wire signed [31:0] ab; +wire signed [31:0] cd; + +// Pipeline of partial products. +reg signed [31:0] ab_r1; +reg signed [31:0] ab_r2; +reg signed [31:0] cd_r1; + +// Combined result. +wire signed [31:0] res; + +// Pipelined result. +reg signed [31:0] res_r1; + +/****************/ +/* Architecture */ +/****************/ + +// Partial products. +assign ab = a_r1*b_r1; +assign cd = c_r2*d_r2; + +// Combined result. +generate + if (op == "sub") begin + assign res = ab_r2 - cd_r1; + end + else if (op == "add") begin + assign res = ab_r2 + cd_r1; + end +endgenerate + +// Registers. +always @(posedge clk) begin + // Input pipeline. + a_r1 <= a; + b_r1 <= b; + c_r1 <= c; + c_r2 <= c_r1; + d_r1 <= d; + d_r2 <= d_r1; + + // Pipeline of partial products. + ab_r1 <= ab; + ab_r2 <= ab_r1; + cd_r1 <= cd; + + // Pipelined result. + res_r1 <= res; +end + +/***********/ +/* Outputs */ +/***********/ +assign x = res_r1; + +endmodule diff --git a/firmware/ip/axis_pfb_readout_v3/src/dds/dds_0/dds_0.xci b/firmware/ip/axis_pfb_readout_v3/src/dds/dds_0/dds_0.xci new file mode 100644 index 0000000..b6e5eac --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/dds/dds_0/dds_0.xci @@ -0,0 +1,476 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 9 + 0 + 0 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 10 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 72 + 1 + 1 + zynquplus + Full_Range + 1 + dds_0 + Not_Required + 256 + Maximal + 0.06 + Coregen + false + false + false + false + 10 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + true + Auto + Twos_Complement + Speed + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 22 + TRUE + ../../../../project_1.gen/sources_1/ip/dds_0 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/dds/dds_ctrl.sv b/firmware/ip/axis_pfb_readout_v3/src/dds/dds_ctrl.sv new file mode 100644 index 0000000..c3c02b3 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/dds/dds_ctrl.sv @@ -0,0 +1,110 @@ +/* + * DDS Control input: + * + * |----------|--------|----------|--------| + * | 71 .. 65 | 64 | 63 .. 32 | 31 .. 0| + * |----------|--------|----------|--------| + * | not used | resync | poff | pinc | + * |----------|--------|----------|--------| + * +*/ + +module dds_ctrl + ( + // Clock. + input wire aclk , + + // Enable input. + input wire en , + + // Output data. + output wire dout_valid , + output wire [71:0] dout , + + // Registers. + input wire [31:0] PINC_REG , + input wire [31:0] POFF_REG + ); + +/********************/ +/* Internal signals */ +/********************/ +// Time counter. +reg [31:0] cnt = 0; +reg [31:0] cnt_r1 = 0; + +// Registers. +reg [31:0] pinc_r1 = 0; +reg [31:0] pinc_r2 = 0; +reg [31:0] poff_r1 = 0; + +// Multiplier output (modulo arithmetic, keep lower bits). +wire [31:0] mult_int; + +// Final phase. +wire [31:0] poff_out; +reg [31:0] poff_out_r1; + +// Output control word. +wire [71:0] dds_ctrl_out; + +// latency for en. +wire en_la; + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// Final phase. +assign poff_out = poff_r1 + mult_int; + +// Output control word. +assign dds_ctrl_out = {7'b0000000,1'b1,poff_out_r1,pinc_r2}; + +// Multiplier: 32x32, unsigned, optimized for speed. +// Latency: 6. +(* keep_hierarchy = "true" *) mult_32x32 mult_i + ( + .clk (aclk ), + .din_a (pinc_r1 ), + .din_b (cnt_r1 ), + .dout (mult_int ) + ); + +// Latency for en (valid). +// Latency = 2 (cnt) + 6 (mult_32x32) + 1 (poff_out) = 9. +latency_reg + #( + .N(9), + .B(1) + ) + latency_reg_en_i + ( + .clk (aclk ), + .din (en ), + .dout (en_la ) + ); + + +// Registers. +always @(posedge aclk) begin + // Time counter. + if (en == 1'b1) + cnt <= cnt + 1; + cnt_r1 <= cnt; + + // Registers. + pinc_r1 <= PINC_REG; + pinc_r2 <= pinc_r1; + poff_r1 <= POFF_REG; + + // Final phase. + poff_out_r1 <= poff_out; +end + +// Assign outputs. +assign dout_valid = en_la ; +assign dout = dds_ctrl_out ; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/dds/dds_top.sv b/firmware/ip/axis_pfb_readout_v3/src/dds/dds_top.sv new file mode 100644 index 0000000..e2a7365 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/dds/dds_top.sv @@ -0,0 +1,68 @@ +module dds_top + ( + // Clock. + input wire aclk , + + // Input valid. + input wire din_valid , + + // Output data. + output wire dout_valid , + output wire [31:0] dout , + + // Registers. + input wire [31:0] PINC_REG , + input wire [31:0] POFF_REG + ); + +/********************/ +/* Internal signals */ +/********************/ + +// DDS control. +wire ctrl_dout_valid ; +wire [71:0] ctrl_dout ; + +// DDS. +wire dds_dout_valid ; +wire [31:0] dds_dout ; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// DDS control. +// Latency: 9. +dds_ctrl dds_ctrl_i + ( + // Clock. + .aclk (aclk ), + + // Enable input. + .en (din_valid ), + + // Output data. + .dout_valid (ctrl_dout_valid ), + .dout (ctrl_dout ), + + // Registers. + .PINC_REG (PINC_REG ), + .POFF_REG (POFF_REG ) + ); + +// DDS instance. +// Latency: 10. +dds_0 dds_i + ( + .aclk (aclk ), + .s_axis_phase_tvalid(ctrl_dout_valid ), + .s_axis_phase_tdata (ctrl_dout ), + .m_axis_data_tvalid (dds_dout_valid ), + .m_axis_data_tdata (dds_dout ) + ); + +// Assign outputs. +assign dout_valid = dds_dout_valid ; +assign dout = dds_dout ; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/dds/mult_32x32.v b/firmware/ip/axis_pfb_readout_v3/src/dds/mult_32x32.v new file mode 100644 index 0000000..f2edc2b --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/dds/mult_32x32.v @@ -0,0 +1,57 @@ +/* + * This multiplier is optimized for 32x32 unsigned, so both of the + * operands are wider than the 27 (or 26 for unsigned) and then + * 4 DSPs are used. Pipeline is such that full-speed is achieved. + * + * Optimal pipeline: 6. + * + */ +module mult_32x32 + ( + input wire clk , + input wire [31:0] din_a , + input wire [31:0] din_b , + output wire [63:0] dout + ); + +/***********/ +/* Signals */ +/***********/ +// Input pipeline. +reg [31:0] din_a_r1 ; +reg [31:0] din_b_r1 ; + +// Product. +wire [63:0] p ; + +// Output pipeline. +reg [63:0] p_r1 ; +reg [63:0] p_r2 ; +reg [63:0] p_r3 ; +reg [63:0] p_r4 ; +reg [63:0] p_r5 ; + +/****************/ +/* Architecture */ +/****************/ + +// Partial products. +assign p = din_a_r1*din_b_r1; + +// Registers. +always @(posedge clk) begin + // Input pipeline. + din_a_r1 <= din_a ; + din_b_r1 <= din_b ; + + // Output pipeline. + p_r1 <= p ; + p_r2 <= p_r1 ; + p_r3 <= p_r2 ; + p_r4 <= p_r3 ; + p_r5 <= p_r4 ; +end + +assign dout = p_r5; + +endmodule diff --git a/firmware/ip/axis_pfb_readout_v3/src/ddsprod.sv b/firmware/ip/axis_pfb_readout_v3/src/ddsprod.sv new file mode 100644 index 0000000..fd39b3d --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/ddsprod.sv @@ -0,0 +1,135 @@ +module ddsprod + ( + // Clock. + input wire aclk , + + // S_AXIS for input data. + input wire s_axis_tvalid , + input wire [31:0] s_axis_tdata , + + // M_AXIS for output data. + output wire m_axis_tvalid , + output wire [31:0] m_axis_tdata , + + // Registers. + input wire [31:0] PINC_REG , + input wire [31:0] POFF_REG + ); + +/********************/ +/* Internal signals */ +/********************/ +// Data input latency. +wire [31:0] din_la ; + +// DDS output. +wire dds_dout_valid ; +wire [31:0] dds_dout ; + +// Real/Imaginary parts of product. +wire [15:0] din_real ; +wire [15:0] din_imag ; +wire [15:0] dds_real ; +wire [15:0] dds_imag ; + +// Full-precision product output. +wire [31:0] prod_real ; +wire [31:0] prod_imag ; + +// Quantized product. +wire [15:0] prod_real_q ; +wire [15:0] prod_imag_q ; +wire [31:0] prod ; +reg [31:0] prod_r1 ; + +// Latency for output valid. +wire valid_la ; + + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// DDS block. +// Latency: 19. +dds_top dds_top_i + ( + // Clock. + .aclk (aclk ), + + // Input valid. + .din_valid (s_axis_tvalid ), + + // Output data. + .dout_valid (dds_dout_valid ), + .dout (dds_dout ), + + // Registers. + .PINC_REG , + .POFF_REG + ); + +// Latency for input data. +// Latency = 19 (dds top). +latency_reg + #( + .N(19), + .B(32) + ) + latency_reg_din_i + ( + .clk (aclk ), + .din (s_axis_tdata ), + .dout (din_la ) + ); + +// Real/Imaginary parts of product. +assign din_real = din_la [15:0] ; +assign din_imag = din_la [31:16] ; +assign dds_real = dds_dout [15:0] ; +assign dds_imag = dds_dout [31:16] ; + +// Full-speed, 16x16 complex product. +// Latency: 4. +cmult_16x16 cmult_i + ( + .clk (aclk ), + .din_i0 (din_real ), + .din_q0 (din_imag ), + .din_i1 (dds_real ), + .din_q1 (dds_imag ), + .dout_i (prod_real ), + .dout_q (prod_imag ) + ); + +// Quantized prodoct. +assign prod_real_q = prod_real [30 -: 16]; +assign prod_imag_q = prod_imag [30 -: 16]; +assign prod = {prod_imag_q, prod_real_q}; + +// Latency for output valid. +// Latency = 4 (cmult) + 1 (output register). +latency_reg + #( + .N(5), + .B(1) + ) + latency_reg_valid_i + ( + .clk (aclk ), + .din (dds_dout_valid ), + .dout (valid_la ) + ); + +// Registers. +always @(posedge aclk) begin + // Quantized product. + prod_r1 <= prod; +end + +// Assign outputs. +assign m_axis_tvalid = valid_la ; +assign m_axis_tdata = prod_r1 ; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/ddsprod_v.sv b/firmware/ip/axis_pfb_readout_v3/src/ddsprod_v.sv new file mode 100644 index 0000000..6ca0d42 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/ddsprod_v.sv @@ -0,0 +1,129 @@ +/* + * This block instantiates 4 ddsprod blocks to apply + * the dds product to 4 independent inputs, with 4 + * independent DDS blocks. + */ +module ddsprod_v + ( + // Clock. + input wire aclk , + + // S_AXIS for input data. + input wire s_axis_tvalid , + input wire [31:0] s0_axis_tdata , + input wire [31:0] s1_axis_tdata , + input wire [31:0] s2_axis_tdata , + input wire [31:0] s3_axis_tdata , + + // M_AXIS for output data. + output wire m_axis_tvalid , + output wire [31:0] m0_axis_tdata , + output wire [31:0] m1_axis_tdata , + output wire [31:0] m2_axis_tdata , + output wire [31:0] m3_axis_tdata , + + // Registers. + input wire [31:0] PINC0_REG , + input wire [31:0] POFF0_REG , + input wire [31:0] PINC1_REG , + input wire [31:0] POFF1_REG , + input wire [31:0] PINC2_REG , + input wire [31:0] POFF2_REG , + input wire [31:0] PINC3_REG , + input wire [31:0] POFF3_REG + ); + +/********************/ +/* Internal signals */ +/********************/ +// Number of inputs/outputs. +localparam N = 4; + +// Input valid. +reg vin_r ; + +// Output valid. +wire [N-1:0] vout_v ; +reg vout_r ; + +// Vectorized inputs. +wire [31:0] din_v [N] ; +reg [31:0] din_r [N] ; + +// Vectorized outputs. +wire [31:0] dout_v [N] ; +reg [31:0] dout_r [N] ; + +// Vectorized registers. +reg [31:0] pinc_v [N] ; +reg [31:0] poff_v [N] ; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Vectorized inputs. +assign din_v [0] = s0_axis_tdata ; +assign din_v [1] = s1_axis_tdata ; +assign din_v [2] = s2_axis_tdata ; +assign din_v [3] = s3_axis_tdata ; + +// Vectorized registers. +assign pinc_v [0] = PINC0_REG ; +assign pinc_v [1] = PINC1_REG ; +assign pinc_v [2] = PINC2_REG ; +assign pinc_v [3] = PINC3_REG ; +assign poff_v [0] = POFF0_REG ; +assign poff_v [1] = POFF1_REG ; +assign poff_v [2] = POFF2_REG ; +assign poff_v [3] = POFF3_REG ; + +genvar i; +generate + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/fifo/fifo_axi.vhd b/firmware/ip/axis_pfb_readout_v3/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/fifo/fifo_dc.vhd b/firmware/ip/axis_pfb_readout_v3/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_pfb_readout_v3/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_pfb_readout_v3/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/fifo/gray2bin.vhd b/firmware/ip/axis_pfb_readout_v3/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/fifo/rd2axi.vhd b/firmware/ip/axis_pfb_readout_v3/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_pfb_readout_v3/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/latency_reg.v b/firmware/ip/axis_pfb_readout_v3/src/latency_reg.v new file mode 100644 index 0000000..b18c039 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/latency_reg.v @@ -0,0 +1,53 @@ +module latency_reg + ( + clk , + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +reg [B-1:0] shift_r [0:N-1]; + +// Array initialization. +integer i; +initial begin + for (i=0; i '0'); + data_rr <= (others => '0'); + valid_r <= '0'; + valid_rr <= '0'; + + -- Counters. + cnt_nwait <= (others => '0'); + cnt <= (others => '0'); + else + -- State register. + current_state <= next_state; + + -- Pipeline registers. + data_r <= s_axis_tdata; + data_rr <= data_r; + valid_r <= valid_i; + valid_rr <= valid_r; + + -- Counters. + if ( rst_state = '1' ) then + cnt_nwait <= cnt_nwait + 1; + end if; + + if ( valid_i = '1' ) then + if ( cnt < to_unsigned(CYCLES-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + end if; + end if; + end if; + end if; +end process; + +-- Next state logic. +process (current_state, cnt_nwait, s_axis_tlast, cnt) +begin + case (current_state) is + when INIT_ST => + next_state <= RST_ST; + + when RST_ST => + if ( cnt_nwait < to_unsigned(NWAIT-1,cnt_nwait'length) ) then + next_state <= RST_ST; + else + next_state <= S0_ST; + end if; + + when S0_ST => + if ( s_axis_tlast = '1' ) then + -- Check if tlast is in the right position. + if ( cnt = to_unsigned(CYCLES-1,cnt'length) ) then + next_state <= S0_ST; + else + -- tlast in the wrong position. + next_state <= S1_ST; + end if; + else + next_state <= S0_ST; + end if; + + when S1_ST => + -- Wait until a frame is completed. + if ( cnt = to_unsigned(CYCLES-1,cnt'length) ) then + next_state <= S2_ST; + else + next_state <= S1_ST; + end if; + + when S2_ST => + -- Wait for the next tlast. + if ( s_axis_tlast = '1' ) then + next_state <= S0_ST; + else + next_state <= S2_ST; + end if; + + end case; +end process; + +-- Output logic. +process (current_state) +begin +rst_state <= '0'; +valid_i <= '0'; + case (current_state) is + when INIT_ST => + + when RST_ST => + rst_state <= '1'; + + when S0_ST => + valid_i <= '1'; + + when S1_ST => + valid_i <= '1'; + + when S2_ST => + + end case; +end process; + +-- Assign outputs. +tdata <= data_rr; +tvalid <= valid_rr; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/conv_pkg.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/conv_pkg.vhd new file mode 100644 index 0000000..b8f1a8f --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/conv_pkg.vhd @@ -0,0 +1,1922 @@ +--------------------------------------------------------------------- +-- +-- Package : conv_pkg +-- +-- Filename : conv_pkg.vhd +-- +-- Date : 8/16/99 +-- +-- Description : Package that defines constant values that is used in the +-- XBS and functions that convert one type to another. +-- +-- Note : This package uses a VHDL 93 constructs therefore when +-- compiling with ModelTech use: vcom -93 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package conv_pkg is + --------------------------------------------------------------------------- + -- Constant that tells whether we're simulating + --------------------------------------------------------------------------- + constant simulating : boolean := false + -- synthesis translate_off + or true + -- synthesis translate_on + ; + + --------------------------------------------------------------------------- + -- Constants for XBS + --------------------------------------------------------------------------- + -- Arithmetic types + constant xlUnsigned : integer := 1; + constant xlSigned : integer := 2; + constant xlFloat : integer := 3; + + -- Constants for Quantization and Overflow + constant xlWrap : integer := 1; + constant xlSaturate : integer := 2; + constant xlTruncate : integer := 1; + constant xlRound : integer := 2; + constant xlRoundBanker : integer := 3; + + -- Constants for xladdsub s-function + constant xlAddMode : integer := 1; + constant xlSubMode : integer := 2; + + --------------------------------------------------------------------------- + -- Black Box Attributes + --------------------------------------------------------------------------- + attribute black_box : boolean; -- for Synplicity (obsolete) + attribute syn_black_box : boolean; -- for Synplicity Version 6.0 + attribute fpga_dont_touch: string; -- for FPGA Express + attribute box_type : string; -- for XST + + --------------------------------------------------------------------------- + -- Attributes to keep clock enable signals + --------------------------------------------------------------------------- + attribute keep : string; + attribute syn_keep : boolean; + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type and vice versa + function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; + function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; + + -- convert a std_logic_vector to a signed type and vice versa + function std_logic_vector_to_signed(inp : std_logic_vector) return signed; + function signed_to_std_logic_vector(inp : signed) return std_logic_vector; + -- convert signed to unsigned and vice versa + function unsigned_to_signed(inp : unsigned) return signed; + function signed_to_unsigned(inp : signed) return unsigned; + -- Tests used in convert_type + function pos(inp : std_logic_vector; arith : INTEGER) return boolean; + function all_same(inp: std_logic_vector) return boolean; + function all_zeros(inp: std_logic_vector) return boolean; + function is_point_five(inp: std_logic_vector) return boolean; + function all_ones(inp: std_logic_vector) return boolean; + + + + -- Convert a fixed point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + -- slice a vector + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector; + + -- slice a signed + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned; + + -- slice a unsigned + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Quantization Functions + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + + -- Overflow functions + function max_signed(width : INTEGER) return std_logic_vector; + function min_signed(width : INTEGER) return std_logic_vector; + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) return std_logic_vector; + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + --------------------------------------------------------------------------- + -- Binary point alignment functions + --------------------------------------------------------------------------- + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; + + -- Returns the number of integer bits after alignment of fixed point num. + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector; + + -- Pad LSB with zeros + function pad_LSB(inp : std_logic_vector; new_width: integer) + return std_logic_vector; + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith : integer) + return std_logic_vector; + + -- Find the max & min integer. + function max(L, R: INTEGER) return INTEGER; + function min(L, R: INTEGER) return INTEGER; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean; + + -- convert a boolean into a signed + function boolean_to_signed (inp : boolean; width: integer) + return signed; + -- convert a boolean into an unsigned + function boolean_to_unsigned (inp : boolean; width: integer) + return unsigned; + -- convert a boolean into std_logic_vector + function boolean_to_vector (inp : boolean) + return std_logic_vector; + -- convert a std_logic into std_logic_vector + function std_logic_to_vector (inp : std_logic) + return std_logic_vector; + -- convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector; + + -- Convert std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer; + function std_logic_to_integer(constant inp : std_logic := '0') + return integer; + + -- Convert a binary string array element into a std_logic_vector + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector; + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector; + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector (inp : string; width : integer) + return std_logic_vector; + + -- Make a binary string that represents zero + function makeZeroBinStr (width : integer) return STRING; + + + --------------------------------------------------------------------------- + -- Debugging functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's (i.e., 0bXX.X) + function is_binary_string_invalid (inp : string) + return boolean; + -- Check for all U's (i.e., 0bUU.U) + function is_binary_string_undefined (inp : string) + return boolean; + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean; + + + -- convert a std_logic_vector to a real type and vice versa + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real; + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real; + + + -- convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector; + -- convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector; + + -- display_precision is the number of digits to display in ModelTech's + -- waveform viewer ( used in to_string(inp : real) ) + constant display_precision : integer := 20; + -- convert a real into a string type + function real_to_string (inp : real) return string; + + -- Check of 0b and the beginning of a string + function valid_bin_string(inp : string) return boolean; + + -- Convert a std_logic_vector to a binary string + function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; + -- Convert a std_logic to a binary string + function std_logic_to_bin_string(inp : std_logic) return string; + -- convert a std_logic_vector to a binary string and add a binary point + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string; + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string; + + -- convert a std_logic_vector value to a character + type stdlogic_to_char_t is array(std_logic) of character; + constant to_char : stdlogic_to_char_t := ( + 'U' => 'U', + 'X' => 'X', + '0' => '0', + '1' => '1', + 'Z' => 'Z', + 'W' => 'W', + 'L' => 'L', + 'H' => 'H', + '-' => '-'); + + -- synthesis translate_on + +end conv_pkg; + +package body conv_pkg is + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type + function std_logic_vector_to_unsigned(inp : std_logic_vector) + return unsigned + is + begin + return unsigned (inp); + end; + + -- convert an unsigend to a std_logic_vector + function unsigned_to_std_logic_vector(inp : unsigned) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert an std_logic_vector to a signed + function std_logic_vector_to_signed(inp : std_logic_vector) + return signed + is + begin + return signed (inp); + end; + + -- convert an std_logic_vector to a sigend + function signed_to_std_logic_vector(inp : signed) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert unsigned to signed + function unsigned_to_signed (inp : unsigned) + return signed + is + begin -- unsigned_to_signed + return signed(std_logic_vector(inp)); + end; + + + -- convert signed to unsigned + function signed_to_unsigned (inp : signed) + return unsigned + is + begin -- signed_to_unsigned + return unsigned(std_logic_vector(inp)); + end; + + -- Test if a number is positive + function pos(inp : std_logic_vector; arith : INTEGER) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := inp; + if arith = xlUnsigned then + return true; + else + if vec(width-1) = '0' then + return true; + else + return false; + end if; + end if; + + -- Error + return true; + end; + + function max_signed(width : INTEGER) + return std_logic_vector + is + variable ones : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + ones := (others => '1'); + result(width-1) := '0'; + result(width-2 downto 0) := ones; + return result; + end; + + function min_signed(width : INTEGER) + return std_logic_vector + is + variable zeros : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + zeros := (others => '0'); + result(width-1) := '1'; + result(width-2 downto 0) := zeros; + return result; + end; + + -- Check if all the bits are the same + function all_same(inp: std_logic_vector) return boolean + is + variable result: boolean; + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + begin + vec := inp; + result := true; + if width > 0 then + for i in 1 to width-1 loop + if vec(i) /= vec(0) then + result := false; + end if; + end loop; + end if; + return result; + end; + + + -- Check if a number is all zeros + function all_zeros(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable zero : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + zero := (others => '0'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Check if a number is point five + function is_point_five(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (width > 1) then + if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then + result := true; + else + result := false; + end if; + else + if (vec(width-1) = '1') then + result := true; + else + result := false; + end if; + end if; + + return result; + end; + + -- Check if a number is all ones + function all_ones(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable one : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + one := (others => '1'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then + result := true; + else + result := false; + end if; + return result; + end; + + + --------------------------------------------------------------------------- + -- Type conersion functions + --------------------------------------------------------------------------- + + + -- Calculate the width of the temp. full precision representation + function full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return integer + is + variable result : integer; + begin + result := old_width + 2; + return result; + end; + + -- Calculate the width of the temp. quantized representation + -- ASSUMES POSITIVE BIN_PT + function quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return integer + is + variable right_of_dp, left_of_dp, result : integer; + begin + + right_of_dp := max(new_bin_pt, old_bin_pt); + left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); + + result := (old_width + 2) + (new_bin_pt - old_bin_pt); + return result; + end; + + + + -- Convert one Fix point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector + is + constant fp_width : integer := + full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, new_width, + new_bin_pt, new_arith); + constant fp_bin_pt : integer := old_bin_pt; + constant fp_arith : integer := old_arith; + variable full_precision_result : std_logic_vector(fp_width-1 downto 0); + + constant q_width : integer := + quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith); + constant q_bin_pt : integer := new_bin_pt; + constant q_arith : integer := old_arith; + variable quantized_result : std_logic_vector(q_width-1 downto 0); + + variable result : std_logic_vector(new_width-1 downto 0); + begin + result := (others => '0'); + + full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, + fp_arith); + + -- Apply quantization functions. This will remove LSB bits. + if (quantization = xlRound) then + + quantized_result := round_towards_inf(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + elsif (quantization = xlRoundBanker) then + quantized_result := round_towards_even(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + else + quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, q_arith); + end if; + + + -- Apply overflow function. This will remove MSB bits. + if (overflow = xlSaturate) then + result := saturation_arith(quantized_result, q_width, q_bin_pt, + q_arith, new_width, new_bin_pt, new_arith); + else + result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, + new_width, new_bin_pt, new_arith); + end if; + + + return result; + end; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, new_width, + new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (new_width - new_bin_pt) + - (old_width - old_bin_pt); + -- Number of digits to add/subract to the right of the decimal point + constant right_of_dp : integer := (new_bin_pt - old_bin_pt); + + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable j : integer; + + begin + vec := inp; + for i in new_width-1 downto 0 loop + j := i - right_of_dp; + if ( j > old_width-1) then + -- Bits to the left of the decimal point + if (new_arith = xlUnsigned) then + -- If unsigned zero pad MSB + result(i) := '0'; + else + -- If signed, sign extend MSB + result(i) := vec(old_width-1); + end if; + elsif ( j >= 0) then + -- Copy bits from input + result(i) := vec(j); + else + -- zero pad LSB + result(i) := '0'; + end if; + end loop; + + return result; + end; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant q_width : integer := quotient'length; + constant f_width : integer := fraction'length; + constant vec_MSB : integer := q_width+f_width-1; + constant result_MSB : integer := q_width+fraction_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := ( quotient & fraction ); + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant inp_width : integer := inp'length; + constant vec_MSB : integer := inp_width-1; + constant result_MSB : integer := result_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := inp; + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + -- vector slice + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector + is + begin + return inp(upper downto lower); + end; + + -- signed slice + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- unsigned slice + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); + end; + + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); + end; + + function boolean_to_signed (inp : boolean; width : integer) + return signed + is + variable result : signed(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_unsigned (inp : boolean; width : integer) + return unsigned + is + variable result : unsigned(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_vector (inp : boolean) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function std_logic_to_vector (inp : std_logic) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result(0) := inp; + return result; + end; + + --------------------------------------------------------------------------- + -- Quantization Functions + --------------------------------------------------------------------------- + + -- Truncate LSB bits + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign Extent or zero extend if necessary + if new_arith = xlUnsigned then + result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); + else + result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + result := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + result := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + return result; + end; + + + -- Round towards infinity + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + if (new_arith = xlSigned) then + -- Roundeing logic for signed numbers + -- Example: + -- Fix(5,-2) = 101.11 (bin) -2.25 (dec) + -- Converted to: Fix(4,-1) = 101.1 (bin) -2.5 (dec) + -- Note: same algorithm used for unsigned numbers can't be used. + + -- 1st check the sign bit of the input to see if it is a positive + -- number + if (vec(old_width-1) = '0') then + one_or_zero(0) := '1'; + end if; + + -- 2nd check if digits being truncated are all zeros + -- (in example it is bit zero) + if (right_of_dp >= 2) and (right_of_dp <= old_width) then + if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then + one_or_zero(0) := '1'; + end if; + end if; + + -- 3rd check if the bit right before the truncation point is '1' + -- or '0' (in example it is bit one) + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if vec(right_of_dp-1) = '0' then + one_or_zero(0) := '0'; + end if; + else + -- No rounding to be performed + one_or_zero(0) := '0'; + end if; + else + -- For an unsigned number just check if the bit right before the + -- truncation point is '1' or '0' + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + one_or_zero(0) := vec(right_of_dp-1); + end if; + end if; + + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + -- Round towards even values + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + -- For the truncated bits just check if the bits after the + -- truncation point are 0.5 + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then + one_or_zero(0) := vec(right_of_dp-1); + else + one_or_zero(0) := vec(right_of_dp); + end if; + end if; + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + --------------------------------------------------------------------------- + -- Overflow Functions + --------------------------------------------------------------------------- + + -- Apply Saturation arithmetic. The new_bin_pt and old bin_pt should be + -- equal. The function chops bits off MSB bits. + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (old_width - old_bin_pt) - + (new_width - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable overflow : boolean; + begin + vec := inp; + overflow := true; + result := (others => '0'); + + ----------------------------------------------------------------------- + -- Check for cases when overflow does not occur + ----------------------------------------------------------------------- + + -- Output width is >= input width + if (new_width >= old_width) then + overflow := false; + end if; + + -- Case #1: + -- Both the input and output are signed and the bits that will + -- be truncated plus the sign bit are all the same + -- (i.e., number has been sign extended) + if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + -- Case #2: + -- If the input is converted to a unsigned from an signed then only + -- check the bits that will be truncated are all zero + if (old_arith = xlSigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + -- Check if input is positive + if (vec(new_width-1) = '0') then + overflow := false; + end if; + end if; + end if; + end if; + + -- Case #3: + -- Input is unsigned and the bits that will be truncated are all zero + if (old_arith = xlUnsigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + overflow := false; + end if; + end if; + end if; + + -- Case #4: + -- Input is unsigned but output signed and the bits that will be + -- truncated are all zero + if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + + if overflow then + -- Overflow occured + if new_arith = xlSigned then + -- Check sign bit and set to max signed or min signed value + if vec(old_width-1) = '0' then + result := max_signed(new_width); + else + result := min_signed(new_width); + end if; + else + -- Check sign bit and set to zero if negative + if ((old_arith = xlSigned) and vec(old_width-1) = '1') then + result := (others => '0'); + else + -- Set to max unsigned positive value + result := (others => '1'); + end if; + end if; + else + -- Overflow did not occur + + -- Check for case when input type is signed and output type + -- unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + -- if negative number set vec to zero + if (vec(old_width-1) = '1') then + vec := (others => '0'); + end if; + end if; + + if new_width <= old_width then + result := vec(new_width-1 downto 0); + else + -- Sign or zero extend number depending on arith of new number + if new_arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + end if; + end if; + + return result; + end; + + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + variable result_arith : integer; + begin + -- Check for case when input type is signed and output type unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + result_arith := xlSigned; + end if; + + result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); + + return result; + end; + + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is + begin + return max(a_bin_pt, b_bin_pt); + end; + + -- Returns the number of integer bits after alignment of fixed point num + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER is + begin + return max(a_width - a_bin_pt, b_width - b_bin_pt); + end; + + function pad_LSB(inp : std_logic_vector; new_width: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + -- Added for XST + constant pad_pos : integer := new_width - orig_width - 1; + + begin + vec := inp; + pos := new_width-1; + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pad_pos >= 0 then + for i in pad_pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + -- sign extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := vec(old_width-1); + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + -- zero extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := '0'; + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + begin + result(0) := inp; + for i in new_width-1 downto 1 loop + result(i) := '0'; + end loop; + + return result; + end; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + return result; + end; + + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + begin + vec := inp; + pos := new_width-1; + + if (arith = xlUnsigned) then + -- set MSB to zero + result(pos) := '0'; + pos := pos - 1; + else + -- sign extend + result(pos) := vec(orig_width-1); + pos := pos - 1; + end if; + + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pos >= 0 then + for i in pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector + is + variable vec : std_logic_vector(old_width-1 downto 0); + variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if delta > 0 then + padded_inp := pad_LSB(vec, old_width+delta); + + -- sign or zero extend zero padded input depending on arith type + result := extend_MSB(padded_inp, new_width, new_arith); + else + -- sign or zero extend input depending on arith type + result := extend_MSB(vec, new_width, new_arith); + end if; + + return result; + end; + + function max(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + function min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean is +-- constant NULL_Str : string := ""; + begin + if (left'length /= right'length) then + return false; + else + -- Check for NULL string + -- FPGA Express does not like empty strings +-- if (left'length = NULL_Str'length) or +-- (right'length = NULL_Str'length) then +-- return true; +-- end if; + test : for i in 1 to left'length loop + if left(i) /= right(i) then + return false; + end if; + end loop test; + return true; + end if; + end; + + + --------------------------------------------------------------------------- + -- Debugging and Simulation only functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's + function is_binary_string_invalid (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'X' ) then + result := true; + end if; + end loop; + return result; + end; + + -- Check for all U's + function is_binary_string_undefined (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'U' ) then + result := true; + end if; + end loop; + return result; + end; + + + + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + result := false; + for i in 0 to width-1 loop + if (vec(i) = 'U') or (vec(i) = 'X') then + result := true; + end if; + end loop; + return result; + end; + + -- Converts a std_logic_vector to a real + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real + is + variable vec : std_logic_vector(inp'length-1 downto 0); + variable result, shift_val, undefined_real : real; + variable neg_num : boolean; + begin + vec := inp; + result := 0.0; + neg_num := false; + if vec(inp'length-1) = '1' then + neg_num := true; + end if; + + for i in 0 to inp'length-1 loop + if vec(i) = 'U' or vec(i) = 'X' then + return undefined_real; + end if; + if arith = xlSigned then + if neg_num then + -- Perform 1's count if negative number + if vec(i) = '0' then + result := result + 2.0**i; + end if; + else + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + else + -- Unsigned numbers + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + end loop; + + if arith = xlSigned then + if neg_num then + -- Add one to 1's comp number to make 2's comp number + result := result + 1.0; + result := result * (-1.0); + end if; + end if; + -- Realign based on binary point + shift_val := 2.0**(-1*bin_pt); + result := result * shift_val; + return result; + end; + + -- This function is just for consistancy + -- bin_pt and arith not used. + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real + is + variable result : real := 0.0; + begin + if inp = '1' then + result := 1.0; + end if; + + if arith = xlSigned then + assert false + report "It doesn't make sense to convert a 1 bit number to a signed real."; + end if; + return result; + end; + + -- synthesis translate_on + -- Convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + begin + + if (arith = xlSigned) then + signed_val := to_signed(inp, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(inp, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- Convert an std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer + is + constant width : integer := inp'length; + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + variable result : integer; + begin + + if (arith = xlSigned) then + signed_val := std_logic_vector_to_signed(inp); + result := to_integer(signed_val); + else + unsigned_val := std_logic_vector_to_unsigned(inp); + result := to_integer(unsigned_val); + end if; + + return result; + end; + + function std_logic_to_integer(constant inp : std_logic := '0') + return integer + is + begin + if inp = '1' then + return 1; + else + return 0; + end if; + end; + + + function makeZeroBinStr (width : integer) return STRING is + variable result : string(1 to width+3); + begin + result(1) := '0'; + result(2) := 'b'; + for i in 3 to width+2 loop + result(i) := '0'; + end loop; -- i + result(width+3) := '.'; + + return result; + end; + + + + -- synthesis translate_off + -- Convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + begin + --result := to_std_logic_vector(real'value(inp), width, bin_pt, arith); + result := (others => '0'); + return result; + end; + + -- Convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector + is + variable real_val : real; + variable int_val : integer; + variable result : std_logic_vector(width-1 downto 0) := (others => '0'); + variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); + variable signed_val : signed(width-1 downto 0) := (others => '0'); + begin + + real_val := inp; + + -- Scale double and make it an integer + int_val := integer(real_val * 2.0**(bin_pt)); + + if (arith = xlSigned) then + signed_val := to_signed(int_val, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(int_val, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- synthesis translate_on + -- Check of 0b and the beginning of a string + function valid_bin_string (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + begin + vec := inp; + if (vec(1) = '0' and vec(2) = 'b') then + return true; + else + return false; + end if; + end; + + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector(inp: string; width : integer) + return std_logic_vector is + + constant strlen : integer := inp'LENGTH; + variable result : std_logic_vector(width-1 downto 0); + variable bitval : std_logic_vector((strlen*4)-1 downto 0); + variable posn : integer; + variable ch : character; + variable vec : string(1 to strlen); + begin + vec := inp; + + -- default value is zero + result := (others => '0'); + posn := (strlen*4)-1; + + for i in 1 to strlen loop + ch := vec(i); + case ch is + when '0' => bitval(posn downto posn-3) := "0000"; + when '1' => bitval(posn downto posn-3) := "0001"; + when '2' => bitval(posn downto posn-3) := "0010"; + when '3' => bitval(posn downto posn-3) := "0011"; + when '4' => bitval(posn downto posn-3) := "0100"; + when '5' => bitval(posn downto posn-3) := "0101"; + when '6' => bitval(posn downto posn-3) := "0110"; + when '7' => bitval(posn downto posn-3) := "0111"; + when '8' => bitval(posn downto posn-3) := "1000"; + when '9' => bitval(posn downto posn-3) := "1001"; + when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; + when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; + when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; + when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; + when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; + when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; + when others => bitval(posn downto posn-3) := "XXXX"; + -- synthesis translate_off + ASSERT false + REPORT "Invalid hex value" SEVERITY ERROR; + -- synthesis translate_on + end case; + posn := posn - 4; + end loop; + + if (width <= strlen*4) then + -- bitval larger than desired width + result := bitval(width-1 downto 0); + else + -- bitval smaller than desired width + -- MSB is padded with zeros since default value for result is all 0s + result((strlen*4)-1 downto 0) := bitval; + end if; + return result; + end; + + + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector + is + variable pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(inp'length-1 downto 0); + begin + vec := inp; + pos := inp'length-1; + -- Set default value + result := (others => '0'); + + for i in 1 to vec'length loop + -- synthesis translate_off + if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then + assert false + report "Input string is larger than output std_logic_vector. Truncating output."; + return result; + end if; + -- synthesis translate_on + + if vec(i) = '0' then + result(pos) := '0'; + pos := pos - 1; + end if; + if vec(i) = '1' then + result(pos) := '1'; + pos := pos - 1; + end if; + -- synthesis translate_off + if (vec(i) = 'X' or vec(i) = 'U') then + result(pos) := 'U'; + pos := pos - 1; + end if; + -- synthesis translate_on + end loop; + return result; + end; + + + -- Convert a binary string array element into a std_logic_vector + -- Example "0b000.0000000 0b001.0000000" + -- string_pos: 123456789111111111122222222 + -- 012345678901234567 + -- + -- "0b000.0000000" = inp(0) + -- "0b001.0000000" = inp(1) + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector + is + constant str_width : integer := width + 4; -- +4 for '0b' '.' & ' ' + constant inp_len : integer := inp'length; + constant num_elements : integer := (inp_len + 1)/str_width; + constant reverse_index : integer := (num_elements-1) - index; + + -- Calc position of desired str + variable left_pos : integer; + variable right_pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(width-1 downto 0); + begin + -- Can't pad input with a space (Synplicity crashes) + vec := inp; + + -- Set default value + result := (others => '0'); + + -- Special Case for string like "0b01.0" without extra ' ' after string + if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := 1; + right_pos := width + 3; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := (reverse_index * str_width) + 1; + right_pos := left_pos + width + 2; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + return result; + end; + -- synthesis translate_off + + -- + -- convert a std_logic_vector to a string + -- + function std_logic_vector_to_bin_string(inp : std_logic_vector) + return string + is + variable vec : std_logic_vector(1 to inp'length); + variable result : string(vec'range); + begin + vec := inp; + for i in vec'range loop + result(i) := to_char(vec(i)); + end loop; + return result; + end; + + -- + -- convert a std_logic to a string + -- + function std_logic_to_bin_string(inp : std_logic) + return string + is + variable result : string(1 to 3); + begin + -- Add 0b prefix + result(1) := '0'; + result(2) := 'b'; + result(3) := to_char(inp); + return result; + end; + + -- + -- convert a std_logic_vector to a string and add a binary point + -- + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string + is + variable width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable str_pos : integer; + variable result : string(1 to width+3); + begin + vec := inp; + -- Add 0b prefeix + str_pos := 1; + result(str_pos) := '0'; + str_pos := 2; + result(str_pos) := 'b'; + str_pos := 3; + for i in width-1 downto 0 loop + -- Insert decimal point + -- if i = (width - bin_pt + 1) then + if (((width+3) - bin_pt) = str_pos) then + result(str_pos) := '.'; + str_pos := str_pos + 1; + end if; + result(str_pos) := to_char(vec(i)); + str_pos := str_pos + 1; + end loop; + -- Add binary point at end of string when bin_pt = 0 + if (bin_pt = 0) then + result(str_pos) := '.'; + end if; + + return result; + end; + + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string + is + variable result : string(1 to width); + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := real_to_std_logic_vector(inp, width, bin_pt, arith); + result := std_logic_vector_to_bin_string(vec); + + return result; + end; + + + -- Convert a real to string + -- Note: the size of the string returned is 'display_precision' chars long + function real_to_string (inp : real) return string + is + variable result : string(1 to display_precision) := (others => ' '); + begin + result(real'image(inp)'range) := real'image(inp); + return result; + end; + + -- synthesis translate_on + + +end conv_pkg; + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/single_reg_w_init.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/single_reg_w_init.vhd new file mode 100644 index 0000000..26af1d6 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/single_reg_w_init.vhd @@ -0,0 +1,109 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : single_reg_w_init.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg_w_init.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity single_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end single_reg_w_init; + +architecture structural of single_reg_w_init is + function build_init_const(width: integer; + init_index: integer; + init_value: bit_vector) + return std_logic_vector + is + variable result: std_logic_vector(width - 1 downto 0); + begin + if init_index = 0 then + result := (others => '0'); + elsif init_index = 1 then + result := (others => '0'); + result(0) := '1'; + else + result := to_stdlogicvector(init_value); + end if; + return result; + end; + + component fdre + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + r: in std_ulogic + ); + end component; -- end fdre + attribute syn_black_box of fdre: component is true; + attribute fpga_dont_touch of fdre: component is "true"; + + component fdse + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + s: in std_ulogic + ); + end component; -- end fdse + attribute syn_black_box of fdse: component is true; + attribute fpga_dont_touch of fdse: component is "true"; + + constant init_const: std_logic_vector(width - 1 downto 0) + := build_init_const(width, init_index, init_value); +begin + fd_prim_array: for index in 0 to width - 1 generate + + bit_is_0: if (init_const(index) = '0') generate + fdre_comp: fdre + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + r => clr + ); + end generate; -- end bit_is_0 + + bit_is_1: if (init_const(index) = '1') generate + fdse_comp: fdse + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + s => clr + ); + end generate; -- end bit_is_1 + end generate; -- end fd_prim_array +end architecture structural; + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/srl17e.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/srl17e.vhd new file mode 100644 index 0000000..8ec9c8d --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/srl17e.vhd @@ -0,0 +1,93 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srl17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srl17e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srl17e; + +architecture structural of srl17e is + + component SRL16E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRL16E : component is true; + attribute fpga_dont_touch of SRL16E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srl16_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srl16_used: if latency > 1 generate + u1 : srl16e port map(clk => clk, + d => d_delayed(i), + q => srl16_out(i), + ce => ce, + a0 => a(0), + a1 => a(1), + a2 => a(2), + a3 => a(3)); + end generate; + srl16_not_used: if latency <= 1 generate + srl16_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srl16_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srl16_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/srl33e.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/srl33e.vhd new file mode 100644 index 0000000..c943462 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/srl33e.vhd @@ -0,0 +1,87 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srlc17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srlc33e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srlc33e; + +architecture structural of srlc33e is + + component SRLC32E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A : in std_logic_vector(4 downto 0); + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRLC32E : component is true; + attribute fpga_dont_touch of SRLC32E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srlc32_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srlc32_used: if latency > 1 generate + u1 : srlc32e port map(clk => clk, + d => d_delayed(i), + q => srlc32_out(i), + ce => ce, + a => a); + end generate; + srlc32_not_used: if latency <= 1 generate + srlc32_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srlc32_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srlc32_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/ssr_8x64.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/ssr_8x64.vhd new file mode 100644 index 0000000..9828dff --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/ssr_8x64.vhd @@ -0,0 +1,2133 @@ +-- Generated from Simulink block ssr_8x64/Vector FFT/Scalar2Vector +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_scalar2vector is + port ( + i : in std_logic_vector( 432-1 downto 0 ); + o_1 : out std_logic_vector( 54-1 downto 0 ); + o_2 : out std_logic_vector( 54-1 downto 0 ); + o_3 : out std_logic_vector( 54-1 downto 0 ); + o_4 : out std_logic_vector( 54-1 downto 0 ); + o_5 : out std_logic_vector( 54-1 downto 0 ); + o_6 : out std_logic_vector( 54-1 downto 0 ); + o_7 : out std_logic_vector( 54-1 downto 0 ); + o_8 : out std_logic_vector( 54-1 downto 0 ) + ); +end ssr_8x64_scalar2vector; +architecture structural of ssr_8x64_scalar2vector is + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); +begin + o_1 <= slice0_y_net; + o_2 <= slice1_y_net; + o_3 <= slice2_y_net; + o_4 <= slice3_y_net; + o_5 <= slice4_y_net; + o_6 <= slice5_y_net; + o_7 <= slice6_y_net; + o_8 <= slice7_y_net; + test_systolicfft_vhdl_black_box_o_net <= i; + slice0 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 53, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice0_y_net + ); + slice1 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 54, + new_msb => 107, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice1_y_net + ); + slice2 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 108, + new_msb => 161, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice2_y_net + ); + slice3 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 162, + new_msb => 215, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice3_y_net + ); + slice4 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 216, + new_msb => 269, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice4_y_net + ); + slice5 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 270, + new_msb => 323, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice5_y_net + ); + slice6 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 324, + new_msb => 377, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice6_y_net + ); + slice7 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 378, + new_msb => 431, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Concat +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_concat is + port ( + hi_1 : in std_logic_vector( 16-1 downto 0 ); + lo_1 : in std_logic_vector( 16-1 downto 0 ); + hi_2 : in std_logic_vector( 16-1 downto 0 ); + hi_3 : in std_logic_vector( 16-1 downto 0 ); + hi_4 : in std_logic_vector( 16-1 downto 0 ); + hi_5 : in std_logic_vector( 16-1 downto 0 ); + hi_6 : in std_logic_vector( 16-1 downto 0 ); + hi_7 : in std_logic_vector( 16-1 downto 0 ); + hi_8 : in std_logic_vector( 16-1 downto 0 ); + lo_2 : in std_logic_vector( 16-1 downto 0 ); + lo_3 : in std_logic_vector( 16-1 downto 0 ); + lo_4 : in std_logic_vector( 16-1 downto 0 ); + lo_5 : in std_logic_vector( 16-1 downto 0 ); + lo_6 : in std_logic_vector( 16-1 downto 0 ); + lo_7 : in std_logic_vector( 16-1 downto 0 ); + lo_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 32-1 downto 0 ); + out_2 : out std_logic_vector( 32-1 downto 0 ); + out_3 : out std_logic_vector( 32-1 downto 0 ); + out_4 : out std_logic_vector( 32-1 downto 0 ); + out_5 : out std_logic_vector( 32-1 downto 0 ); + out_6 : out std_logic_vector( 32-1 downto 0 ); + out_7 : out std_logic_vector( 32-1 downto 0 ); + out_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x64_vector_concat; +architecture structural of ssr_8x64_vector_concat is + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= concat0_y_net; + out_2 <= concat1_y_net; + out_3 <= concat2_y_net; + out_4 <= concat3_y_net; + out_5 <= concat4_y_net; + out_6 <= concat5_y_net; + out_7 <= concat6_y_net; + out_8 <= concat7_y_net; + reinterpret0_output_port_net_x0 <= hi_1; + reinterpret0_output_port_net <= lo_1; + reinterpret1_output_port_net_x0 <= hi_2; + reinterpret2_output_port_net_x0 <= hi_3; + reinterpret3_output_port_net_x0 <= hi_4; + reinterpret4_output_port_net_x0 <= hi_5; + reinterpret5_output_port_net_x0 <= hi_6; + reinterpret6_output_port_net_x0 <= hi_7; + reinterpret7_output_port_net_x0 <= hi_8; + reinterpret1_output_port_net <= lo_2; + reinterpret2_output_port_net <= lo_3; + reinterpret3_output_port_net <= lo_4; + reinterpret4_output_port_net <= lo_5; + reinterpret5_output_port_net <= lo_6; + reinterpret6_output_port_net <= lo_7; + reinterpret7_output_port_net <= lo_8; + concat0 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret0_output_port_net_x0, + in1 => reinterpret0_output_port_net, + y => concat0_y_net + ); + concat1 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret1_output_port_net_x0, + in1 => reinterpret1_output_port_net, + y => concat1_y_net + ); + concat2 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret2_output_port_net_x0, + in1 => reinterpret2_output_port_net, + y => concat2_y_net + ); + concat3 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret3_output_port_net_x0, + in1 => reinterpret3_output_port_net, + y => concat3_y_net + ); + concat4 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret4_output_port_net_x0, + in1 => reinterpret4_output_port_net, + y => concat4_y_net + ); + concat5 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret5_output_port_net_x0, + in1 => reinterpret5_output_port_net, + y => concat5_y_net + ); + concat6 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret6_output_port_net_x0, + in1 => reinterpret6_output_port_net, + y => concat6_y_net + ); + concat7 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret7_output_port_net_x0, + in1 => reinterpret7_output_port_net, + y => concat7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Delay +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_delay is + port ( + d_1 : in std_logic_vector( 32-1 downto 0 ); + d_2 : in std_logic_vector( 32-1 downto 0 ); + d_3 : in std_logic_vector( 32-1 downto 0 ); + d_4 : in std_logic_vector( 32-1 downto 0 ); + d_5 : in std_logic_vector( 32-1 downto 0 ); + d_6 : in std_logic_vector( 32-1 downto 0 ); + d_7 : in std_logic_vector( 32-1 downto 0 ); + d_8 : in std_logic_vector( 32-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + q_1 : out std_logic_vector( 32-1 downto 0 ); + q_2 : out std_logic_vector( 32-1 downto 0 ); + q_3 : out std_logic_vector( 32-1 downto 0 ); + q_4 : out std_logic_vector( 32-1 downto 0 ); + q_5 : out std_logic_vector( 32-1 downto 0 ); + q_6 : out std_logic_vector( 32-1 downto 0 ); + q_7 : out std_logic_vector( 32-1 downto 0 ); + q_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x64_vector_delay; +architecture structural of ssr_8x64_vector_delay is + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal clk_net : std_logic; + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal ce_net : std_logic; + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); +begin + q_1 <= delay0_q_net; + q_2 <= delay1_q_net; + q_3 <= delay2_q_net; + q_4 <= delay3_q_net; + q_5 <= delay4_q_net; + q_6 <= delay5_q_net; + q_7 <= delay6_q_net; + q_8 <= delay7_q_net; + concat0_y_net <= d_1; + concat1_y_net <= d_2; + concat2_y_net <= d_3; + concat3_y_net <= d_4; + concat4_y_net <= d_5; + concat5_y_net <= d_6; + concat6_y_net <= d_7; + concat7_y_net <= d_8; + clk_net <= clk_1; + ce_net <= ce_1; + delay0 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat0_y_net, + clk => clk_net, + ce => ce_net, + q => delay0_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat1_y_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net + ); + delay2 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat2_y_net, + clk => clk_net, + ce => ce_net, + q => delay2_q_net + ); + delay3 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat3_y_net, + clk => clk_net, + ce => ce_net, + q => delay3_q_net + ); + delay4 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat4_y_net, + clk => clk_net, + ce => ce_net, + q => delay4_q_net + ); + delay5 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat5_y_net, + clk => clk_net, + ce => ce_net, + q => delay5_q_net + ); + delay6 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat6_y_net, + clk => clk_net, + ce => ce_net, + q => delay6_q_net + ); + delay7 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat7_y_net, + clk => clk_net, + ce => ce_net, + q => delay7_q_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Reinterpret +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_reinterpret is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x64_vector_reinterpret; +architecture structural of ssr_8x64_vector_reinterpret is + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_re_0_net <= in_1; + i_re_1_net <= in_2; + i_re_2_net <= in_3; + i_re_3_net <= in_4; + i_re_4_net <= in_5; + i_re_5_net <= in_6; + i_re_6_net <= in_7; + i_re_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Reinterpret1 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_reinterpret1 is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x64_vector_reinterpret1; +architecture structural of ssr_8x64_vector_reinterpret1 is + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_im_0_net <= in_1; + i_im_1_net <= in_2; + i_im_2_net <= in_3; + i_im_3_net <= in_4; + i_im_4_net <= in_5; + i_im_5_net <= in_6; + i_im_6_net <= in_7; + i_im_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Reinterpret2 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_reinterpret2 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_reinterpret2; +architecture structural of ssr_8x64_vector_reinterpret2 is + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Reinterpret3 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_reinterpret3 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_reinterpret3; +architecture structural of ssr_8x64_vector_reinterpret3 is + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Slice Im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_slice_im is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_slice_im; +architecture structural of ssr_8x64_vector_slice_im is + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Slice Re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_slice_re is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_slice_re; +architecture structural of ssr_8x64_vector_slice_re is + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector2Scalar +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector2scalar is + port ( + i_1 : in std_logic_vector( 32-1 downto 0 ); + i_2 : in std_logic_vector( 32-1 downto 0 ); + i_3 : in std_logic_vector( 32-1 downto 0 ); + i_4 : in std_logic_vector( 32-1 downto 0 ); + i_5 : in std_logic_vector( 32-1 downto 0 ); + i_6 : in std_logic_vector( 32-1 downto 0 ); + i_7 : in std_logic_vector( 32-1 downto 0 ); + i_8 : in std_logic_vector( 32-1 downto 0 ); + o : out std_logic_vector( 256-1 downto 0 ) + ); +end ssr_8x64_vector2scalar; +architecture structural of ssr_8x64_vector2scalar is + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); +begin + o <= concat1_y_net; + delay0_q_net <= i_1; + delay1_q_net <= i_2; + delay2_q_net <= i_3; + delay3_q_net <= i_4; + delay4_q_net <= i_5; + delay5_q_net <= i_6; + delay6_q_net <= i_7; + delay7_q_net <= i_8; + concat1 : entity xil_defaultlib.sysgen_concat_c0fcf025b9 + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => delay7_q_net, + in1 => delay6_q_net, + in2 => delay5_q_net, + in3 => delay4_q_net, + in4 => delay3_q_net, + in5 => delay2_q_net, + in6 => delay1_q_net, + in7 => delay0_q_net, + y => concat1_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_fft is + port ( + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + vi : in std_logic_vector( 1-1 downto 0 ); + si : in std_logic_vector( 6-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_8 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_8 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + vo : out std_logic; + so : out std_logic_vector( 6-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_8 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_fft; +architecture structural of ssr_8x64_vector_fft is + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_vo_net : std_logic; + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 6-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal slice7_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_scale_net : std_logic_vector( 6-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal ce_net : std_logic; + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal slice1_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal clk_net : std_logic; + signal reinterpret6_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret2_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal concat1_y_net_x0 : std_logic_vector( 32-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay_q_net : std_logic_vector( 1-1 downto 0 ); + signal reinterpret4_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret6_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret7_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay1_q_net_x0 : std_logic_vector( 6-1 downto 0 ); + signal reinterpret7_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); +begin + o_re_1 <= reinterpret0_output_port_net_x0; + o_im_1 <= reinterpret0_output_port_net; + vo <= test_systolicfft_vhdl_black_box_vo_net; + so <= test_systolicfft_vhdl_black_box_so_net; + o_re_2 <= reinterpret1_output_port_net_x0; + o_re_3 <= reinterpret2_output_port_net_x0; + o_re_4 <= reinterpret3_output_port_net_x0; + o_re_5 <= reinterpret4_output_port_net_x0; + o_re_6 <= reinterpret5_output_port_net_x0; + o_re_7 <= reinterpret6_output_port_net_x0; + o_re_8 <= reinterpret7_output_port_net_x0; + o_im_2 <= reinterpret1_output_port_net; + o_im_3 <= reinterpret2_output_port_net; + o_im_4 <= reinterpret3_output_port_net; + o_im_5 <= reinterpret4_output_port_net; + o_im_6 <= reinterpret5_output_port_net; + o_im_7 <= reinterpret6_output_port_net; + o_im_8 <= reinterpret7_output_port_net; + i_re_0_net <= i_re_1; + i_im_0_net <= i_im_1; + i_valid_net <= vi; + i_scale_net <= si; + i_re_1_net <= i_re_2; + i_re_2_net <= i_re_3; + i_re_3_net <= i_re_4; + i_re_4_net <= i_re_5; + i_re_5_net <= i_re_6; + i_re_6_net <= i_re_7; + i_re_7_net <= i_re_8; + i_im_1_net <= i_im_2; + i_im_2_net <= i_im_3; + i_im_3_net <= i_im_4; + i_im_4_net <= i_im_5; + i_im_5_net <= i_im_6; + i_im_6_net <= i_im_7; + i_im_7_net <= i_im_8; + clk_net <= clk_1; + ce_net <= ce_1; + scalar2vector : entity xil_defaultlib.ssr_8x64_scalar2vector + port map ( + i => test_systolicfft_vhdl_black_box_o_net, + o_1 => slice0_y_net_x1, + o_2 => slice1_y_net_x1, + o_3 => slice2_y_net_x1, + o_4 => slice3_y_net_x1, + o_5 => slice4_y_net_x1, + o_6 => slice5_y_net_x1, + o_7 => slice6_y_net_x1, + o_8 => slice7_y_net_x1 + ); + vector_concat : entity xil_defaultlib.ssr_8x64_vector_concat + port map ( + hi_1 => reinterpret0_output_port_net_x1, + lo_1 => reinterpret0_output_port_net_x2, + hi_2 => reinterpret1_output_port_net_x1, + hi_3 => reinterpret2_output_port_net_x1, + hi_4 => reinterpret3_output_port_net_x1, + hi_5 => reinterpret4_output_port_net_x1, + hi_6 => reinterpret5_output_port_net_x1, + hi_7 => reinterpret6_output_port_net_x1, + hi_8 => reinterpret7_output_port_net_x1, + lo_2 => reinterpret1_output_port_net_x2, + lo_3 => reinterpret2_output_port_net_x2, + lo_4 => reinterpret3_output_port_net_x2, + lo_5 => reinterpret4_output_port_net_x2, + lo_6 => reinterpret5_output_port_net_x2, + lo_7 => reinterpret6_output_port_net_x2, + lo_8 => reinterpret7_output_port_net_x2, + out_1 => concat0_y_net, + out_2 => concat1_y_net_x0, + out_3 => concat2_y_net, + out_4 => concat3_y_net, + out_5 => concat4_y_net, + out_6 => concat5_y_net, + out_7 => concat6_y_net, + out_8 => concat7_y_net + ); + vector_delay : entity xil_defaultlib.ssr_8x64_vector_delay + port map ( + d_1 => concat0_y_net, + d_2 => concat1_y_net_x0, + d_3 => concat2_y_net, + d_4 => concat3_y_net, + d_5 => concat4_y_net, + d_6 => concat5_y_net, + d_7 => concat6_y_net, + d_8 => concat7_y_net, + clk_1 => clk_net, + ce_1 => ce_net, + q_1 => delay0_q_net, + q_2 => delay1_q_net, + q_3 => delay2_q_net, + q_4 => delay3_q_net, + q_5 => delay4_q_net, + q_6 => delay5_q_net, + q_7 => delay6_q_net, + q_8 => delay7_q_net + ); + vector_reinterpret : entity xil_defaultlib.ssr_8x64_vector_reinterpret + port map ( + in_1 => i_re_0_net, + in_2 => i_re_1_net, + in_3 => i_re_2_net, + in_4 => i_re_3_net, + in_5 => i_re_4_net, + in_6 => i_re_5_net, + in_7 => i_re_6_net, + in_8 => i_re_7_net, + out_1 => reinterpret0_output_port_net_x2, + out_2 => reinterpret1_output_port_net_x2, + out_3 => reinterpret2_output_port_net_x2, + out_4 => reinterpret3_output_port_net_x2, + out_5 => reinterpret4_output_port_net_x2, + out_6 => reinterpret5_output_port_net_x2, + out_7 => reinterpret6_output_port_net_x2, + out_8 => reinterpret7_output_port_net_x2 + ); + vector_reinterpret1 : entity xil_defaultlib.ssr_8x64_vector_reinterpret1 + port map ( + in_1 => i_im_0_net, + in_2 => i_im_1_net, + in_3 => i_im_2_net, + in_4 => i_im_3_net, + in_5 => i_im_4_net, + in_6 => i_im_5_net, + in_7 => i_im_6_net, + in_8 => i_im_7_net, + out_1 => reinterpret0_output_port_net_x1, + out_2 => reinterpret1_output_port_net_x1, + out_3 => reinterpret2_output_port_net_x1, + out_4 => reinterpret3_output_port_net_x1, + out_5 => reinterpret4_output_port_net_x1, + out_6 => reinterpret5_output_port_net_x1, + out_7 => reinterpret6_output_port_net_x1, + out_8 => reinterpret7_output_port_net_x1 + ); + vector_reinterpret2 : entity xil_defaultlib.ssr_8x64_vector_reinterpret2 + port map ( + in_1 => slice0_y_net, + in_2 => slice1_y_net, + in_3 => slice2_y_net, + in_4 => slice3_y_net, + in_5 => slice4_y_net, + in_6 => slice5_y_net, + in_7 => slice6_y_net, + in_8 => slice7_y_net, + out_1 => reinterpret0_output_port_net_x0, + out_2 => reinterpret1_output_port_net_x0, + out_3 => reinterpret2_output_port_net_x0, + out_4 => reinterpret3_output_port_net_x0, + out_5 => reinterpret4_output_port_net_x0, + out_6 => reinterpret5_output_port_net_x0, + out_7 => reinterpret6_output_port_net_x0, + out_8 => reinterpret7_output_port_net_x0 + ); + vector_reinterpret3 : entity xil_defaultlib.ssr_8x64_vector_reinterpret3 + port map ( + in_1 => slice0_y_net_x0, + in_2 => slice1_y_net_x0, + in_3 => slice2_y_net_x0, + in_4 => slice3_y_net_x0, + in_5 => slice4_y_net_x0, + in_6 => slice5_y_net_x0, + in_7 => slice6_y_net_x0, + in_8 => slice7_y_net_x0, + out_1 => reinterpret0_output_port_net, + out_2 => reinterpret1_output_port_net, + out_3 => reinterpret2_output_port_net, + out_4 => reinterpret3_output_port_net, + out_5 => reinterpret4_output_port_net, + out_6 => reinterpret5_output_port_net, + out_7 => reinterpret6_output_port_net, + out_8 => reinterpret7_output_port_net + ); + vector_slice_im : entity xil_defaultlib.ssr_8x64_vector_slice_im + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net_x0, + out_2 => slice1_y_net_x0, + out_3 => slice2_y_net_x0, + out_4 => slice3_y_net_x0, + out_5 => slice4_y_net_x0, + out_6 => slice5_y_net_x0, + out_7 => slice6_y_net_x0, + out_8 => slice7_y_net_x0 + ); + vector_slice_re : entity xil_defaultlib.ssr_8x64_vector_slice_re + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net, + out_2 => slice1_y_net, + out_3 => slice2_y_net, + out_4 => slice3_y_net, + out_5 => slice4_y_net, + out_6 => slice5_y_net, + out_7 => slice6_y_net, + out_8 => slice7_y_net + ); + vector2scalar : entity xil_defaultlib.ssr_8x64_vector2scalar + port map ( + i_1 => delay0_q_net, + i_2 => delay1_q_net, + i_3 => delay2_q_net, + i_4 => delay3_q_net, + i_5 => delay4_q_net, + i_6 => delay5_q_net, + i_7 => delay6_q_net, + i_8 => delay7_q_net, + o => concat1_y_net + ); + delay : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 1 + ) + port map ( + en => '1', + rst => '0', + d => i_valid_net, + clk => clk_net, + ce => ce_net, + q => delay_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 6 + ) + port map ( + en => '1', + rst => '0', + d => i_scale_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net_x0 + ); + test_systolicfft_vhdl_black_box : entity xil_defaultlib.WRAPPER_VECTOR_FFT_c5415935ecc00ff9eff39575a72e6e61 + generic map ( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 6, + N => 64, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map ( + i => concat1_y_net, + vi => delay_q_net(0), + si => delay1_q_net_x0, + CLK => clk_net, + CE => ce_net, + o => test_systolicfft_vhdl_black_box_o_net, + vo => test_systolicfft_vhdl_black_box_vo_net, + so => test_systolicfft_vhdl_black_box_so_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/i_im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_i_im is + port ( + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x64_i_im; +architecture structural of ssr_8x64_i_im is + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); +begin + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; +end structural; +-- Generated from Simulink block ssr_8x64/i_re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_i_re is + port ( + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x64_i_re; +architecture structural of ssr_8x64_i_re is + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); +begin + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; +end structural; +-- Generated from Simulink block ssr_8x64_struct +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_struct is + port ( + i_scale : in std_logic_vector( 6-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_scale : out std_logic_vector( 6-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_struct; +architecture structural of ssr_8x64_struct is + signal test_systolicfft_vhdl_black_box_vo_net : std_logic_vector( 1-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_scale_net : std_logic_vector( 6-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 6-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal ce_net : std_logic; + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal clk_net : std_logic; + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); +begin + i_scale_net <= i_scale; + i_valid_net <= i_valid; + o_scale <= test_systolicfft_vhdl_black_box_so_net; + o_valid <= test_systolicfft_vhdl_black_box_vo_net; + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; + o_im_0 <= reinterpret0_output_port_net; + o_im_1 <= reinterpret1_output_port_net; + o_im_2 <= reinterpret2_output_port_net; + o_im_3 <= reinterpret3_output_port_net; + o_im_4 <= reinterpret4_output_port_net_x0; + o_im_5 <= reinterpret5_output_port_net; + o_im_6 <= reinterpret6_output_port_net; + o_im_7 <= reinterpret7_output_port_net; + o_re_0 <= reinterpret0_output_port_net_x0; + o_re_1 <= reinterpret1_output_port_net_x0; + o_re_2 <= reinterpret2_output_port_net_x0; + o_re_3 <= reinterpret3_output_port_net_x0; + o_re_4 <= reinterpret4_output_port_net; + o_re_5 <= reinterpret5_output_port_net_x0; + o_re_6 <= reinterpret6_output_port_net_x0; + o_re_7 <= reinterpret7_output_port_net_x0; + clk_net <= clk_1; + ce_net <= ce_1; + vector_fft : entity xil_defaultlib.ssr_8x64_vector_fft + port map ( + i_re_1 => i_re_0_net, + i_im_1 => i_im_0_net, + vi => i_valid_net, + si => i_scale_net, + i_re_2 => i_re_1_net, + i_re_3 => i_re_2_net, + i_re_4 => i_re_3_net, + i_re_5 => i_re_4_net, + i_re_6 => i_re_5_net, + i_re_7 => i_re_6_net, + i_re_8 => i_re_7_net, + i_im_2 => i_im_1_net, + i_im_3 => i_im_2_net, + i_im_4 => i_im_3_net, + i_im_5 => i_im_4_net, + i_im_6 => i_im_5_net, + i_im_7 => i_im_6_net, + i_im_8 => i_im_7_net, + clk_1 => clk_net, + ce_1 => ce_net, + o_re_1 => reinterpret0_output_port_net_x0, + o_im_1 => reinterpret0_output_port_net, + vo => test_systolicfft_vhdl_black_box_vo_net(0), + so => test_systolicfft_vhdl_black_box_so_net, + o_re_2 => reinterpret1_output_port_net_x0, + o_re_3 => reinterpret2_output_port_net_x0, + o_re_4 => reinterpret3_output_port_net_x0, + o_re_5 => reinterpret4_output_port_net, + o_re_6 => reinterpret5_output_port_net_x0, + o_re_7 => reinterpret6_output_port_net_x0, + o_re_8 => reinterpret7_output_port_net_x0, + o_im_2 => reinterpret1_output_port_net, + o_im_3 => reinterpret2_output_port_net, + o_im_4 => reinterpret3_output_port_net, + o_im_5 => reinterpret4_output_port_net_x0, + o_im_6 => reinterpret5_output_port_net, + o_im_7 => reinterpret6_output_port_net, + o_im_8 => reinterpret7_output_port_net + ); + i_im : entity xil_defaultlib.ssr_8x64_i_im + port map ( + i_im_0 => i_im_0_net, + i_im_1 => i_im_1_net, + i_im_2 => i_im_2_net, + i_im_3 => i_im_3_net, + i_im_4 => i_im_4_net, + i_im_5 => i_im_5_net, + i_im_6 => i_im_6_net, + i_im_7 => i_im_7_net + ); + i_re : entity xil_defaultlib.ssr_8x64_i_re + port map ( + i_re_0 => i_re_0_net, + i_re_1 => i_re_1_net, + i_re_2 => i_re_2_net, + i_re_3 => i_re_3_net, + i_re_4 => i_re_4_net, + i_re_5 => i_re_5_net, + i_re_6 => i_re_6_net, + i_re_7 => i_re_7_net + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_default_clock_driver is + port ( + ssr_8x64_sysclk : in std_logic; + ssr_8x64_sysce : in std_logic; + ssr_8x64_sysclr : in std_logic; + ssr_8x64_clk1 : out std_logic; + ssr_8x64_ce1 : out std_logic + ); +end ssr_8x64_default_clock_driver; +architecture structural of ssr_8x64_default_clock_driver is +begin + clockdriver : entity xil_defaultlib.xlclockdriver + generic map ( + period => 1, + log_2_period => 1 + ) + port map ( + sysclk => ssr_8x64_sysclk, + sysce => ssr_8x64_sysce, + sysclr => ssr_8x64_sysclr, + clk => ssr_8x64_clk1, + ce => ssr_8x64_ce1 + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64 is + port ( + i_scale : in std_logic_vector( 6-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk : in std_logic; + o_scale : out std_logic_vector( 6-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64; +architecture structural of ssr_8x64 is + attribute core_generation_info : string; + attribute core_generation_info of structural : architecture is "ssr_8x64,sysgen_core_2019_2,{,compilation=HDL Netlist,block_icon_display=Default,family=zynquplusRFSOC,part=xczu28dr,speed=-2-e,package=ffvg1517,synthesis_language=vhdl,hdl_library=xil_defaultlib,synthesis_strategy=Vivado Synthesis Defaults,implementation_strategy=Vivado Implementation Defaults,testbench=0,interface_doc=0,ce_clr=0,clock_period=10,system_simulink_period=1,waveform_viewer=0,axilite_interface=0,ip_catalog_plugin=0,hwcosim_burst_mode=0,simulation_time=10,blackbox2=1,concat=9,delay=10,reinterpret=32,slice=24,}"; + signal ce_1_net : std_logic; + signal clk_1_net : std_logic; +begin + ssr_8x64_default_clock_driver : entity xil_defaultlib.ssr_8x64_default_clock_driver + port map ( + ssr_8x64_sysclk => clk, + ssr_8x64_sysce => '1', + ssr_8x64_sysclr => '0', + ssr_8x64_clk1 => clk_1_net, + ssr_8x64_ce1 => ce_1_net + ); + ssr_8x64_struct : entity xil_defaultlib.ssr_8x64_struct + port map ( + i_scale => i_scale, + i_valid => i_valid, + i_im_0 => i_im_0, + i_im_1 => i_im_1, + i_im_2 => i_im_2, + i_im_3 => i_im_3, + i_im_4 => i_im_4, + i_im_5 => i_im_5, + i_im_6 => i_im_6, + i_im_7 => i_im_7, + i_re_0 => i_re_0, + i_re_1 => i_re_1, + i_re_2 => i_re_2, + i_re_3 => i_re_3, + i_re_4 => i_re_4, + i_re_5 => i_re_5, + i_re_6 => i_re_6, + i_re_7 => i_re_7, + clk_1 => clk_1_net, + ce_1 => ce_1_net, + o_scale => o_scale, + o_valid => o_valid, + o_im_0 => o_im_0, + o_im_1 => o_im_1, + o_im_2 => o_im_2, + o_im_3 => o_im_3, + o_im_4 => o_im_4, + o_im_5 => o_im_5, + o_im_6 => o_im_6, + o_im_7 => o_im_7, + o_re_0 => o_re_0, + o_re_1 => o_re_1, + o_re_2 => o_re_2, + o_re_3 => o_re_3, + o_re_4 => o_re_4, + o_re_5 => o_re_5, + o_re_6 => o_re_6, + o_re_7 => o_re_7 + ); +end structural; diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/ssr_8x64_entity_declarations.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/ssr_8x64_entity_declarations.vhd new file mode 100644 index 0000000..cccfea0 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/ssr_8x64_entity_declarations.vhd @@ -0,0 +1,6159 @@ +------------------------------------------------------------------- +-- System Generator version 2019.2 VHDL source file. +-- +-- Copyright(C) 2019 by Xilinx, Inc. All rights reserved. This +-- text/file contains proprietary, confidential information of Xilinx, +-- Inc., is distributed under license from Xilinx, Inc., and may be used, +-- copied and/or disclosed only pursuant to the terms of a valid license +-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use +-- this text/file solely for design, simulation, implementation and +-- creation of design files limited to Xilinx devices or technologies. +-- Use with non-Xilinx devices or technologies is expressly prohibited +-- and immediately terminates your license unless covered by a separate +-- agreement. +-- +-- Xilinx is providing this design, code, or information "as is" solely +-- for use in developing programs and solutions for Xilinx devices. By +-- providing this design, code, or information as one possible +-- implementation of this feature, application or standard, Xilinx is +-- making no representation that this implementation is free from any +-- claims of infringement. You are responsible for obtaining any rights +-- you may require for your implementation. Xilinx expressly disclaims +-- any warranty whatsoever with respect to the adequacy of the +-- implementation, including but not limited to warranties of +-- merchantability or fitness for a particular purpose. +-- +-- Xilinx products are not intended for use in life support appliances, +-- devices, or systems. Use in such applications is expressly prohibited. +-- +-- Any modifications that are made to the source code are done at the user's +-- sole risk and will be unsupported. +-- +-- This copyright and support notice must be retained as part of this +-- text at all times. (c) Copyright 1995-2019 Xilinx, Inc. All rights +-- reserved. +------------------------------------------------------------------- + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x64_xldelay is + generic(width : integer := -1; + latency : integer := -1; + reg_retiming : integer := 0; + reset : integer := 0); + port(d : in std_logic_vector (width-1 downto 0); + ce : in std_logic; + clk : in std_logic; + en : in std_logic; + rst : in std_logic; + q : out std_logic_vector (width-1 downto 0)); + +end ssr_8x64_xldelay; + +architecture behavior of ssr_8x64_xldelay is + component synth_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; -- end component synth_reg + + component synth_reg_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; + + signal internal_ce : std_logic; + +begin + internal_ce <= ce and en; + + srl_delay: if ((reg_retiming = 0) and (reset = 0)) or (latency < 1) generate + synth_reg_srl_inst : synth_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => '0', + clk => clk, + o => q); + end generate srl_delay; + + reg_delay: if ((reg_retiming = 1) or (reset = 1)) and (latency >= 1) generate + synth_reg_reg_inst : synth_reg_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => rst, + clk => clk, + o => q); + end generate reg_delay; +end architecture behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: COMPLEX_FIXED_PKG.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Package Name: COMPLEX_FIXED_PKG +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Unconstrained Size Vectors and Matrices of Complex Arbitrary Precision Fixed Point Numbers +-- +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +package COMPLEX_FIXED_PKG is + type BOOLEAN_VECTOR is array(NATURAL range <>) of BOOLEAN; + type INTEGER_VECTOR is array(NATURAL range <>) of INTEGER; + type REAL_VECTOR is array(NATURAL range <>) of REAL; +--2008 type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED; + type COMPLEX_VECTOR is array(INTEGER range <>) of COMPLEX; + + type SFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point signed number, like SIGNED but lower bound can be negative +--2008 type SFIXED_VECTOR is array(INTEGER range <>) of SFIXED; -- unconstrained array of SFIXED +--2008 type CFIXED is record RE,IM:SFIXED; end record; -- arbitrary precision fixed point complex signed number +--2008 type CFIXED_VECTOR is array(INTEGER range <>) of CFIXED; -- unconstrained array of CFIXED +--2008 type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR; -- unconstrained array of CFIXED_VECTOR + type SFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of SFIXED, vector size must be given by a separate generic + type CFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point complex signed number, CFIXED'low is always even and CFIXED'high is always odd + type CFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of CFIXED, vector size must be given by a separate generic + +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED; -- returns the CFIXED range for X(K) +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).RE +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).IM + + function MIN(A,B:INTEGER) return INTEGER; + function MIN(A,B,C:INTEGER) return INTEGER; + function MIN(A,B,C,D:INTEGER) return INTEGER; + function MED(A,B,C:INTEGER) return INTEGER; + function MAX(A,B:INTEGER) return INTEGER; + function MAX(A,B,C:INTEGER) return INTEGER; + function MAX(A,B,C,D:INTEGER) return INTEGER; + function "+"(X,Y:SFIXED) return SFIXED; -- full precision add with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X,Y:SFIXED) return SFIXED; -- full precision subtract with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X:SFIXED) return SFIXED; -- full precision negate with SFIXED(X'high+1 downto X'low) result + function "*"(X,Y:SFIXED) return SFIXED; -- full precision multiply with SFIXED(X'high+Y'high+1 downto X'low+Y'low) result + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED; -- multiply by 0 or 1 with SFIXED(X'high downto X'low) result + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED; -- resizes X and returns SFIXED(H downto L) + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED; -- resizes X to match HL and returns SFIXED(HL'high downto HL'low) + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high+N downto X'low+N) result + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED; -- returns SFIXED(H downto L) result + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED; -- returns SFIXED(HL'high downto HL'low) result + function TO_REAL(S:SFIXED) return REAL; -- returns REAL result +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED; -- returns element K out of an N-size array X + + function RE(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vRE(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure RE(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function IM(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vIM(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure IM(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function "+"(X,Y:CFIXED) return CFIXED; -- full precision add with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "-"(X,Y:CFIXED) return CFIXED; -- full precision subtract with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "*"(X,Y:CFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high+2 downto X'low+Y'low) result + function "*"(X:CFIXED;Y:SFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high downto X'low+Y'low) result + function "*"(X:SFIXED;Y:CFIXED) return CFIXED; + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED; -- resizes X and returns CFIXED(H downto L) + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED; -- resizes X to match HL and returns CFIXED(HL'high downto HL'low) + function PLUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function "-"(X:CFIXED) return CFIXED; -- full precision negate with CFIXED(X'high+2 downto X'low) result + function MINUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function SWAP(X:CFIXED) return CFIXED; -- returns CFIXED(X'high downto X'low) result + function CONJ(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high+N downto X'low+N) result + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED; -- returns CFIXED(H downto L) result + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED; -- returns CFIXED(HL'high downto HL'low) result + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED; -- returns CFIXED(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_CFIXED(R,I:SFIXED) return CFIXED; -- returns CFIXED(2*MAX(R'high,I'high)+1 downto 2*MIN(R'low,I'low)) result + function TO_COMPLEX(C:CFIXED) return COMPLEX; -- returns COMPLEX result + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR; -- returns CFIXED_VECTOR(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR; -- returns COMPLEX_VECTOR result + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR; -- returns R*C + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED; -- returns element K out of an N-size array X + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a variable, set element K out of an N-size array X to C + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a signal, set element K out of an N-size array X to C + + function LOG2(N:INTEGER) return INTEGER; -- returns ceil(log2(N)) +end COMPLEX_FIXED_PKG; + +package body COMPLEX_FIXED_PKG is +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED is -- returns the CFIXED range for X(K) +-- variable O:CFIXED(X'length/N*(K+1)-1+X'low/N downto X'length/N*K+X'low/N); +-- begin +-- return O; +-- end; + +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).RE +-- begin +-- return RE(ELEMENT(X,K,N)); +-- end; + +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).IM +-- begin +-- return IM(ELEMENT(X,K,N)); +-- end; + + function MIN(A,B:INTEGER) return INTEGER is + begin + if AB then + return A; + else + return B; + end if; + end; + + function MAX(A,B,C:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),C); + end; + + function MAX(A,B,C,D:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),MAX(C,D)); + end; + + function "+"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX+SY; -- SIGNED addition + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX-SY; -- SIGNED subtraction + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SR:SIGNED(X'high-X'low+1 downto 0); + variable R:SFIXED(X'high+1 downto X'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + SR:=-RESIZE(SX,SR'length); -- SIGNED negation + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X,Y:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SY:SIGNED(Y'high-Y'low downto 0); + variable SR:SIGNED(SX'high+SY'high+1 downto 0); + variable R:SFIXED(X'high+Y'high+1 downto X'low+Y'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + for K in SY'range loop + SY(K):=Y(Y'low+K); + end loop; + SR:=SX*SY; -- SIGNED multiplication + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED is + begin + if Y='1' then + return X; + else + return TO_SFIXED(0.0,X); + end if; + end; + + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED is + variable R:SFIXED(H downto L); + begin + for K in R'range loop + if KX'high then + R(K):=X(X'high); -- sign extend X MSBs + else + R(K):=X(K); + end if; + end loop; + return R; + end; + + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED is + begin + return RESIZE(X,HL'high,HL'low); + end; + + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high-N downto X'low-N); + begin + for K in R'range loop + R(K):=X(K+N); + end loop; + return R; + end; + + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high+N downto X'low+N); + begin + for K in R'range loop + R(K):=X(K-N); + end loop; + return R; + end; + + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED is + variable RR:REAL; + variable V:SFIXED(H downto L); + begin + assert (R<2.0**H) and (R>=-2.0**H) report "TO_SFIXED vector truncation!" severity warning; + if R<0.0 then + V(V'high):='1'; + RR:=R+2.0**V'high; + else + V(V'high):='0'; + RR:=R; + end if; + for K in V'high-1 downto V'low loop + if RR>=2.0**K then + V(K):='1'; + RR:=RR-2.0**K; + else + V(K):='0'; + end if; + end loop; + return V; + end; + + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED is + begin + return TO_SFIXED(R,HL'high,HL'low); + end; + + function TO_REAL(S:SFIXED) return REAL is + variable R:REAL; + begin + R:=0.0; + for K in S'range loop + if K=S'high then + if S(K)='1' then + R:=R-2.0**K; + end if; + else + if S(K)='1' then + R:=R+2.0**K; + end if; + end if; + end loop; + return R; + end; + +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED is -- X'low and X'length are always multiples of N +-- variable R:SFIXED(X'length/N-1+X'low/N downto X'low/N); +-- begin +-- R:=SFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); +-- return R; -- element K out of N of X +-- end; + + function RE(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(R'length-1+X'low downto X'low)); + return R; --lower half of X + end; + +-- procedure vRE(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low):=CFIXED(S); -- set lower half of X +-- end; + +-- procedure RE(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low)<=CFIXED(S); -- set lower half of X +-- end; + + function IM(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(X'high downto R'length+X'low)); + return R; --upper half of X + end; + +-- procedure vIM(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low):=CFIXED(S); -- set upper half of X +-- end; + +-- procedure IM(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low)<=CFIXED(S); -- set upper half of X +-- end; + + function "+"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+RE(Y),IM(X)+IM(Y)); + end; + + function "-"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-RE(Y),IM(X)-IM(Y)); + end; + + function "*"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*RE(Y)-IM(X)*IM(Y),RE(X)*IM(Y)+IM(X)*RE(Y)); + end; + + function "*"(X:CFIXED;Y:SFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*Y,IM(X)*Y); + end; + + function "*"(X:SFIXED;Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(X*RE(Y),X*IM(Y)); + end; + + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(RESIZE(RE(X),H,L),RESIZE(IM(X),H,L)); + end; + + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED is + begin + return RESIZE(X,HL'high/2,HL'low/2); + end; + + function PLUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-IM(X),RE(X)); + end; + + function "-"(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-RE(X),-IM(X)); + end; + + function MINUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),-RE(X)); + end; + + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-IM(Y)+RE(RND),IM(X)+RE(Y)+IM(RND)); + end; + + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+IM(Y)+RE(RND),IM(X)-RE(Y)+IM(RND)); + end; + + function SWAP(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),RE(X)); + end; + + function CONJ(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X),-IM(X)); + end; + + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_RIGHT(RE(X),N),SHIFT_RIGHT(IM(X),N)); + end; + + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_LEFT(RE(X),N),SHIFT_LEFT(IM(X),N)); + end; + + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(TO_SFIXED(R,H,L),TO_SFIXED(I,H,L)); + end; + + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(R,I,HL'high/2,HL'low/2); + end; + + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(C.RE,C.IM,HL); + end; + + function TO_CFIXED(R,I:SFIXED) return CFIXED is + constant H:INTEGER:=MAX(R'high,I'high); + constant L:INTEGER:=MIN(R'low,I'low); + variable C:CFIXED(2*H+1 downto 2*L); + begin + C:=CFIXED(RESIZE(I,H,L))&CFIXED(RESIZE(R,H,L)); + return C; -- I&R + end; + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED is -- X'low and X'length are always multiples of N + variable R:CFIXED(X'length/N-1+X'low/N downto X'low/N); + begin + R:=CFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); + return R; -- element K out of N of X + end; + + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low):=CFIXED_VECTOR(C); -- element K out of N of X + end; + + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low)<=CFIXED_VECTOR(C); -- element K out of N of X + end; + + function TO_COMPLEX(C:CFIXED) return COMPLEX is + variable R:COMPLEX; + begin + R.RE:=TO_REAL(RE(C)); + R.IM:=TO_REAL(IM(C)); + return R; + end; + + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR is + variable R:CFIXED_VECTOR(C'length*(HL'high+1)-1 downto C'length*HL'low); + begin + for K in C'range loop + R((K-C'low+1)*HL'length-1+R'low downto (K-C'low)*HL'length+R'low):=CFIXED_VECTOR(TO_CFIXED(C(K),HL)); + end loop; + return R; + end; + + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR is + variable R:COMPLEX_VECTOR(0 to N-1); + begin + for K in 0 to N-1 loop + R(K):=TO_COMPLEX(ELEMENT(C,K,N)); + end loop; + return R; + end; + + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR is + variable X:COMPLEX_VECTOR(C'range); + begin + for K in C'range loop + X(K):=R*C(K); + end loop; + return X; + end; + + function LOG2(N:INTEGER) return INTEGER is + variable TEMP:INTEGER; + variable RESULT:INTEGER; + begin + TEMP:=N; + RESULT:=0; + while TEMP>1 loop + RESULT:=RESULT+1; + TEMP:=(TEMP+1)/2; + end loop; + return RESULT; + end; +end COMPLEX_FIXED_PKG; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic BOOLEAN Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); +end BDELAY; + +architecture TEST of BDELAY is + attribute rloc:STRING; + + component BDELAY + generic(SIZE:INTEGER:=1); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); + end component; + +begin + l0:if SIZE=0 generate + begin + O<=I; + end generate l0; + -- end; + + l1:if SIZE=1 generate + signal iO:BOOLEAN:=FALSE; + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; + end generate l1; + -- end; + + l17: if SIZE>=2 and SIZE<18 generate + signal A:UNSIGNED(3 downto 0); + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + D<='1' when I else '0'; + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>D, + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l17; + -- end; + + l33: if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + D<='1' when I else '0'; + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>D, + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l33; + -- end; + + l257: if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.BDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + -- end; + end generate l257; + + ln: if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + type TUV is array(0 to SIZE-3) of UNSIGNED(0 downto 0); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(0 downto 0):=(others=>(others=>'0')); + signal MEM:TUV:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(0 downto 0):=(others=>'0'); + signal D,Q:UNSIGNED(0 downto 0); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + D<="1" when I else "0"; + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=D; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO="1"; + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: UDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: UDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic UNSIGNED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity UDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in UNSIGNED; + O:out UNSIGNED); +end UDELAY; + +architecture TEST of UDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin + assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=I; +-- end; + end generate; +-- elsif l1: SIZE=1 generate + l1:if SIZE=1 generate + signal iO:UNSIGNED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; +-- end; + end generate; +-- elsif l17: SIZE>=2 and SIZE<18 generate + l17:if SIZE>=2 and SIZE<18 generate + lk:for K in 0 to O'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l33: SIZE>=18 and SIZE<34 generate + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l257: SIZE>=34 and SIZE=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.UDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); +-- end; + end generate; +-- elsif ln: SIZE>=BRAM_THRESHOLD generate + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of UNSIGNED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO; + end if; + end process; +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic SFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity SDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in SFIXED; + O:out SFIXED); +end SDELAY; + +architecture TEST of SDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin +-- assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=RESIZE(I,O'high,O'low); + end generate l0; + --end; + + l1:if SIZE=1 generate + signal iO:SFIXED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=RESIZE(I,iO); + end if; + end process; + O<=iO; + end generate l1; + --end; + + l17:if SIZE>=2 and SIZE<18 generate +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); + begin + lk:for K in 0 to I'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l17; + --end; + + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- iO<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l33; + --end; + + l257:if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.SDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + --end; + end generate l257; + + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:SFIXED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of SFIXED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:SFIXED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=RESIZE(iO,O'high,O'low); + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic CFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CDELAY; + +architecture TEST of CDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; + signal IRE,IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); +begin + IRE<=RE(I); + IIM<=IM(I); + dr:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.RE); + I=>IRE, + O=>ORE); + di:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.IM); + I=>IIM, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CB.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CB +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Matrix Transposer (Corner Bender) Module Stage +-- It does an RxR matrix transposition where R=I'length +-- and each matrix element is a group of PACKING_FACTOR consecutive samples +-- LATENCY=(I'length-1)*PACKING_FACTOR+1 when I'length>1 or 0 when I'length=1 +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CB is + generic(SSR:INTEGER:=4; --93 + F:INTEGER:=0; + PACKING_FACTOR:INTEGER:=1; + INPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + OUTPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + SHORTEN_VO_BY:INTEGER:=0; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CB; + +architecture TEST of CB is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(LOG2(SSR)-1 downto 0); --93 local constrained UNSIGNED_VECTOR type + type iCFIXED_VECTOR is array(NATURAL range <>) of CFIXED((I'high+1)/SSR-1 downto I'low/SSR); --93 local constrained CFIXED_VECTOR type + + signal CNTP:UNSIGNED(LOG2(PACKING_FACTOR) downto 0):=(others=>'0'); + signal CNT:UNSIGNED(LOG2(SSR)-1 downto 0):=(others=>'0'); +--2008 signal A:UNSIGNED_VECTOR(0 to I'length):=(others=>(others=>'0')); +--2008 signal EN:BOOLEAN_VECTOR(0 to I'length):=(others=>FALSE); +--2008 signal DI:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal DO:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(0 to I'length-1=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).IM'range=>'0'))); + signal A:UNSIGNED_VECTOR(0 to SSR):=(others=>(others=>'0')); + signal EN:BOOLEAN_VECTOR(0 to SSR):=(others=>FALSE); + signal II,DI,OO:iCFIXED_VECTOR(0 to SSR-1); + signal DO:iCFIXED_VECTOR(0 to SSR-1):=(others=>(others=>'0')); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity error; + + f0:if F=0 generate + begin +--2008 i0:if I'length=1 generate + i0:if SSR=1 generate + O<=I; + VO<=VI; + SO<=SI; + end generate; +--2008 else generate +--2008 i1:if I'length>1 generate + i1:if SSR>1 generate + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if CNTP=PACKING_FACTOR-1 then + CNTP<=(others=>'0'); + CNT<=CNT+1; + else + CNTP<=CNTP+1; + end if; + else + CNTP<=(others=>'0'); + CNT<=(others=>'0'); + end if; + end if; + end process; + + A(0)<=CNT; + EN(0)<=CNTP=PACKING_FACTOR-1; +--2008 lk:for K in 0 to I'length-1 generate + lk:for K in 0 to SSR-1 generate + begin + II(K)<=CFIXED(I(I'length/SSR*(K+1)-1+I'low downto I'length/SSR*K+I'low)); --93 + i1:entity work.CDELAY generic map(SIZE=>K*(PACKING_FACTOR+INPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II(K), --93 I(I'low+K), + O=>DI(K)); + process(CLK) + begin + if rising_edge(CLK) then + DO(K)<=DI(TO_INTEGER(A(K))); + if EN(K) then + A(K+1)<=A(K); + end if; + end if; + end process; + bd:entity work.BDELAY generic map(SIZE=>PACKING_FACTOR) + port map(CLK=>CLK, + I=>EN(K), + O=>EN(K+1)); + o1:entity work.CDELAY generic map(SIZE=>(SSR-1-K)*(PACKING_FACTOR+OUTPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DO(K), + O=>OO(K)); --93 O(O'low+K)); + O(O'length/SSR*(K+1)-1+O'low downto O'length/SSR*K+O'low)<=CFIXED_VECTOR(OO(K)); --93 + end generate; + + bd:entity work.BDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY) + port map(CLK=>CLK, + I=>VI, + O=>VO); + + ud:entity work.UDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +-- end; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=SSR/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.CB generic map(SSR=>G, + F=>0, + PACKING_FACTOR=>PACKING_FACTOR, + INPUT_PACKING_FACTOR_ADJUST=>INPUT_PACKING_FACTOR_ADJUST, + OUTPUT_PACKING_FACTOR_ADJUST=>OUTPUT_PACKING_FACTOR_ADJUST, + SHORTEN_VO_BY=>SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Real Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BFS is + generic(PIPELINE:BOOLEAN:=TRUE; + SUB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SCALE:in STD_LOGIC; +-- P:out SIGNED); -- O=A±B + P:out SFIXED; -- O=A±B + OVR:out STD_LOGIC); +end BFS; + +architecture FAST of BFS is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH+1 downto SM-1); +-- signal S:SIGNED(SH+1 downto SL); + signal SA,SB:SFIXED(SH+1 downto SM-1); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM+1 downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1)/8*8+8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1)/8*8+7 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH+1 generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (((I0 and not I4) or (I2 and I4)) xor ((I1 and not I4) or (I3 and I4)))) or (not I5 and ((I1 and not I4) or (I3 and I4)))) + port map(I0=>SB(K-1),I1=>SA(K-1),I2=>SB(K),I3=>SA(K),I4=>SCALE,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM+1)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM+1); + end generate; + S(SH+1)<=O(O'high); + + ia:if A'low'0'); + signal iOVR:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + iOVR<=S(S'high) xor S(S'high-1); + end if; + end process; + P<=iP; + OVR<=iOVR; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CBFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CBFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Complex Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CBFS is -- O0=I0+I1, O1=I0-I1 + generic(ROUNDING:BOOLEAN:=TRUE; + PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC; + I0,I1:in CFIXED; + SCALE:in STD_LOGIC; + O0,O1:out CFIXED; + OVR:out STD_LOGIC); +end CBFS; + +architecture TEST of CBFS is + signal I0RE,I0IM,I1RE,I1IM:SFIXED(I0'high/2 downto I0'low/2); + signal O0RE,O0IM,O1RE,O1IM:SFIXED(O0'high/2 downto O0'low/2); + signal OVR4:STD_LOGIC_VECTOR(3 downto 0); +begin + I0RE<=RE(I0); + I0IM<=IM(I0); + I1RE<=RE(I1); + I1IM<=IM(I1); + + u0:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0RE=I0RE+I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O0RE, + OVR=>OVR4(0)); + + u1:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0IM=I0IM+I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O0IM, + OVR=>OVR4(1)); + + u2:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1RE=I0RE-I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O1RE, + OVR=>OVR4(2)); + + u3:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1IM=I0IM-I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O1IM, + OVR=>OVR4(3)); + + O0<=TO_CFIXED(O0RE,O0IM); + O1<=TO_CFIXED(O1RE,O1IM); + OVR<=OVR4(0) or OVR4(1) or OVR4(2) or OVR4(3); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CSA3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CSA3 +-- Purpose: Generic 3-input Add/Sub Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Carry Save 3-input Adder/Subtracter +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CSA3 is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + NEGATIVE_A:BOOLEAN:=FALSE; + NEGATIVE_B:BOOLEAN:=FALSE; + EXTRA_MSBs:INTEGER:=2); + port(CLK:in STD_LOGIC:='0'; +-- A,B,C:in SIGNED; -- if SIGNED, A, B, C and P must be LSB aligned + A,B,C:in SFIXED; -- if SFIXED, A, B, C and P can be any size + CY1,CY2:in BOOLEAN:=FALSE; -- the number of CYs TRUE must equal the number of negative A and B terms +-- P:out SIGNED); -- O=C±A±B + P:out SFIXED); -- O=C±A±B +end CSA3; + +architecture FAST of CSA3 is + constant SH:INTEGER:=MAX(A'high,B'high,C'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MED(A'low,B'low,C'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low,C'low); +-- signal SA,SB,SC,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB,SC:SFIXED(SH downto SM); + signal S:SFIXED(SH downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + SC<=RESIZE(C,SC); + O5(0)<='1' when CY1 else '0'; + CY(0)<='1' when CY2 else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_B))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_A))); + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (I1 xor I2 xor I3 xor I4)) or (not I5 and ((I2 and I3) or (I3 and I1) or (I1 and I2)))) + port map(I0=>'0',I1=>SC(K),I2=>SB(K),I3=>SA(K),I4=>O5(K-SM),I5=>'1',O5=>O5(K+1-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM); + end generate; + + ia:if (A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +--***************************************************************************** +-- © Copyright 2008 - 2018 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +--***************************************************************************** +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : v1.2 +-- \ \ Application : DSP48E2 generic wrapper +-- / / Filename : DSP48E2GW.vhd +-- /___/ /\ Date Last Modified : Oct 11 2017 +-- \ \ / \ Date Created : Nov 14 2014 +-- \___\/\___\ +-- +--Device : UltraScale and UltraScale+ +--Design Name : DSP48E2GW +--Purpose : DSP48E2 Generic Wrapper makes DSP48E2 primitive instantiation easier +--Reference : +--Revision History : v1.0 - original version +--Revision History : v1.1 - smart SFIXED resizing +--Revision History : v1.2 - fix for output resizing +--***************************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +--use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity DSP48E2GW is + generic(X,Y:INTEGER:=-1; + DSP48E:INTEGER:=2; -- use 1 for DSP48E1 and 2 for DSP48E2 + -- Feature Control Attributes: Data Path Selection + AMULTSEL:STRING:="A"; -- Selects A input to multiplier (A, AD) + A_INPUT:STRING:="DIRECT"; -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL:STRING:="B"; -- Selects B input to multiplier (AD, B) + B_INPUT:STRING:="DIRECT"; -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL:STRING:="A"; -- Selects input to preadder (A, B) + RND:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- Rounding Constant + USE_MULT:STRING:="MULTIPLY"; -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD:STRING:="ONE48"; -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR:STRING:="FALSE"; -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD:STRING:="XOR24_48_96"; -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET:STRING:="NO_RESET"; -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY:STRING:="RESET"; -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK:STD_LOGIC_VECTOR(47 downto 0):=X"3fffffffffff"; -- 48-bit mask value for pattern detect (1=ignore) + PATTERN:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- 48-bit pattern match for pattern detect + SEL_MASK:STRING:="MASK"; -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN:STRING:="PATTERN"; -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT:STRING:="NO_PATDET"; -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED:STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED:BIT:='0'; -- Optional inversion for CARRYIN + IS_CLK_INVERTED:BIT:='0'; -- Optional inversion for CLK + IS_INMODE_INVERTED:STD_LOGIC_VECTOR(4 downto 0):="00000"; -- Optional inversion for INMODE + IS_OPMODE_INVERTED:STD_LOGIC_VECTOR(8 downto 0):="000000000"; -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED:BIT:='0'; -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED:BIT:='0'; -- Optional inversion for RSTA + IS_RSTB_INVERTED:BIT:='0'; -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED:BIT:='0'; -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED:BIT:='0'; -- Optional inversion for RSTC + IS_RSTD_INVERTED:BIT:='0'; -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED:BIT:='0'; -- Optional inversion for RSTM + IS_RSTP_INVERTED:BIT:='0'; -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG:INTEGER:=1; -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG:INTEGER:=1; -- Pipeline stages for pre-adder (0-1) + ALUMODEREG:INTEGER:=1; -- Pipeline stages for ALUMODE (0-1) + AREG:INTEGER:=1; -- Pipeline stages for A (0-2) + BCASCREG:INTEGER:=1; -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG:INTEGER:=1; -- Pipeline stages for B (0-2) + CARRYINREG:INTEGER:=1; -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG:INTEGER:=1; -- Pipeline stages for CARRYINSEL (0-1) + CREG:INTEGER:=1; -- Pipeline stages for C (0-1) + DREG:INTEGER:=1; -- Pipeline stages for D (0-1) + INMODEREG:INTEGER:=1; -- Pipeline stages for INMODE (0-1) + MREG:INTEGER:=1; -- Multiplier pipeline stages (0-1) + OPMODEREG:INTEGER:=1; -- Pipeline stages for OPMODE (0-1) + PREG:INTEGER:=1); -- Number of pipeline stages for P (0-1) + port(-- Cascade inputs: Cascade Ports + ACIN:in STD_LOGIC_VECTOR(29 downto 0):=(others=>'0'); -- 30-bit input: A cascade data + BCIN:in STD_LOGIC_VECTOR(17 downto 0):=(others=>'0'); -- 18-bit input: B cascade + CARRYCASCIN:in STD_LOGIC:='0'; -- 1-bit input: Cascade carry + MULTSIGNIN:in STD_LOGIC:='0'; -- 1-bit input: Multiplier sign cascade + PCIN:in STD_LOGIC_VECTOR(47 downto 0):=(others=>'0'); -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE:in STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- 4-bit input: ALU control + CARRYINSEL:in STD_LOGIC_VECTOR(2 downto 0):="000"; -- 3-bit input: Carry select + CLK:in STD_LOGIC:='0'; -- 1-bit input: Clock + INMODE:in STD_LOGIC_VECTOR(4 downto 0):="00000"; -- 5-bit input: INMODE control + OPMODE:in STD_LOGIC_VECTOR(8 downto 0):="000110101"; -- 9-bit input: Operation mode - default is P<=C+A*B + -- Data inputs: Data Ports + A:in SFIXED;--(Ahi downto Alo):=(others=>'0'); -- 30-bit input: A data + B:in SFIXED;--(Bhi downto Blo):=(others=>'0'); -- 18-bit input: B data + C:in SFIXED;--(Chi downto Clo):=(others=>'0'); -- 48-bit input: C data + CARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Carry-in + D:in SFIXED;--(Dhi downto Dlo):=(others=>'0'); -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage AREG + CEA2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage AREG + CEAD:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ADREG + CEALUMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ALUMODE + CEB1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage BREG + CEB2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage BREG + CEC:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CREG + CECARRYIN:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CARRYINREG + CECTRL:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for DREG + CEINMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for INMODEREG + CEM:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for MREG + CEP:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for PREG + RSTA:in STD_LOGIC:='0'; -- 1-bit input: Reset for AREG + RSTALLCARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Reset for CARRYINREG + RSTALUMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for ALUMODEREG + RSTB:in STD_LOGIC:='0'; -- 1-bit input: Reset for BREG + RSTC:in STD_LOGIC:='0'; -- 1-bit input: Reset for CREG + RSTCTRL:in STD_LOGIC:='0'; -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD:in STD_LOGIC:='0'; -- 1-bit input: Reset for DREG and ADREG + RSTINMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for INMODEREG + RSTM:in STD_LOGIC:='0'; -- 1-bit input: Reset for MREG + RSTP:in STD_LOGIC:='0'; -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT:out STD_LOGIC_VECTOR(29 downto 0); -- 30-bit output: A port cascade + BCOUT:out STD_LOGIC_VECTOR(17 downto 0); -- 18-bit output: B cascade + CARRYCASCOUT:out STD_LOGIC; -- 1-bit output: Cascade carry + MULTSIGNOUT:out STD_LOGIC; -- 1-bit output: Multiplier sign cascade + PCOUT:out STD_LOGIC_VECTOR(47 downto 0); -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW:out STD_LOGIC; -- 1-bit output: Overflow in add/acc + PATTERNBDETECT:out STD_LOGIC; -- 1-bit output: Pattern bar detect + PATTERNDETECT:out STD_LOGIC; -- 1-bit output: Pattern detect + UNDERFLOW:out STD_LOGIC; -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT:out STD_LOGIC_VECTOR(3 downto 0); -- 4-bit output: Carry + P:out SFIXED;--(Phi downto Plo); -- 48-bit output: Primary data + XOROUT:out STD_LOGIC_VECTOR(7 downto 0)); -- 8-bit output: XOR data +end entity; + +architecture WRAPPER of DSP48E2GW is + signal slvA:STD_LOGIC_VECTOR(29 downto 0); + signal slvB:STD_LOGIC_VECTOR(17 downto 0); + signal slvD:STD_LOGIC_VECTOR(26 downto 0); + signal slvC,slvP:STD_LOGIC_VECTOR(47 downto 0); +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if K=0) and (Y>=0) generate + begin + i1:if DSP48E=1 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; +-- else generate + i2:if (X<0) or (Y<0) generate + begin + i1:if DSP48E=1 generate + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; + P<=SLV_TO_SFIXED_RESIZE(slvP,P'high,P'low,A'low+B'low-P'low); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CKCM.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CKCM +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Constant Coeficient Complex Multiplier +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CKCM is -- LATENCY=3 + generic(M:INTEGER:=1; -- must be 0, 1, 2 or 3 to multiply I by (1.0,0.0), (Sqrt(0.5),-Sqrt(0.5)), (0.0,-1.0), (-Sqrt(0.5),-Sqrt(0.5)) + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + ROUNDING:BOOLEAN:=FALSE; -- set to TRUE to round the result + CONJUGATE:BOOLEAN:=FALSE); -- set to TRUE for IFFT + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CKCM; + +architecture TEST of CKCM is + attribute use_dsp48:STRING; + attribute use_dsp48 of TEST:architecture is "no"; +--2008 signal RND:SFIXED(O.RE'high downto O.RE'low-1); + signal RND:SFIXED((O'high+1)/2-1 downto O'low/2-1); + constant nCONJUGATE:BOOLEAN:=not CONJUGATE; +begin + i0:if M=0 generate + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>I, + O=>O); + end generate; +--elsif i1: M=2 generate + i1:if M=2 generate + ic:if CONJUGATE generate +--2008 signal NIIM1D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal NIIM1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IRE:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIIM1D<=RESIZE(-I.IM,I.IM); + NIIM1D<=RESIZE(-IM(I),NIIM1D); + end if; + end process; + r2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIIM1D, +--2008 O=>O.RE); + O=>ORE); + IRE<=RE(I); + i3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.IM); + I=>IRE, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + ---else generate + nc:if not CONJUGATE generate +--2008 signal NIRE1D:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal NIRE1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + IIM<=IM(I); + r3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.RE); + I=>IIM, + O=>ORE); + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIRE1D<=RESIZE(-I.RE,I.RE); + NIRE1D<=RESIZE(-RE(I),RE(I)); + end if; + end process; + i2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIRE1D, +--2008 O=>O.IM); + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + end generate; +-- else generate -- M=1 or 3 + i2:if (M=1) or (M=3) generate -- M=1 or 3 + constant K:SFIXED(0 downto -18):="0101101010000010100"; -- SQRT(0.5) + +--2008 signal X1,Y1:SFIXED(I.RE'high downto I.RE'low-14); +--2008 signal X2,Y2:SFIXED(I.RE'range); +--2008 signal KIRE,KIIM:SFIXED(I.RE'range); + + + + signal X1,Y1:SFIXED((I'high+1)/2-1 downto I'low/2-14); + signal X2,Y2:SFIXED((I'high+1)/2-1 downto I'low/2):=(others=>'0'); + signal KIRE,KIIM:SFIXED((I'high+1)/2-1 downto I'low/2); +--2008 signal I_1:CFIXED(RE(I.RE'high-1 downto I.RE'low-1),IM(I.IM'high-1 downto I.IM'low-1)); +--2008 signal I_6:CFIXED(RE(I.RE'high-6 downto I.RE'low-6),IM(I.IM'high-6 downto I.IM'low-6)); +--2008 signal I_14:CFIXED(RE(I.RE'high-14 downto I.RE'low-14),IM(I.IM'high-14 downto I.IM'low-14)); + signal I_1:CFIXED(I'high-2*1 downto I'low-2*1); + signal I_6:CFIXED(I'high-2*6 downto I'low-2*6); + signal I_14:CFIXED(I'high-2*14 downto I'low-2*14); + signal I_1RE,I_1IM:SFIXED((I_1'high+1)/2-1 downto I_1'low/2); + signal I_6RE,I_6IM:SFIXED((I_6'high+1)/2-1 downto I_6'low/2); + signal I_14RE,I_14IM:SFIXED((I_14'high+1)/2-1 downto I_14'low/2); + signal X1_2:SFIXED(X1'high-2 downto X1'low-2); + signal X2_4:SFIXED(X2'high-4 downto X2'low-4); + signal Y1_2:SFIXED(Y1'high-2 downto Y1'low-2); + signal Y2_4:SFIXED(Y2'high-4 downto Y2'low-4); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + constant MEQ3:BOOLEAN:=M=3; + begin +--2008 RND<=TO_SFIXED(2.0**(O.RE'low-1),RND) when ROUNDING else (others=>'0'); + RND<=TO_SFIXED(2.0**(O'low/2-1),RND) when ROUNDING else (others=>'0'); + process(CLK) + begin + if rising_edge(CLK) then +--2008 X2<=I.RE; +--2008 Y2<=I.IM; + X2<=RE(I); + Y2<=IM(I); + end if; + end process; + + I_1<=SHIFT_RIGHT(I,1); + I_6<=SHIFT_RIGHT(I,6); + I_14<=SHIFT_RIGHT(I,14); + X1_2<=SHIFT_RIGHT(X1,2); + X2_4<=SHIFT_RIGHT(X2,4); + Y1_2<=SHIFT_RIGHT(Y1,2); + Y2_4<=SHIFT_RIGHT(Y2,4); + I_1RE<=RE(I_1); + I_6RE<=RE(I_6); + I_14RE<=RE(I_14); + + a1:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.RE, +--2008 B=>I_6.RE, +--2008 C=>I_14.RE, + A=>I_1RE, + B=>I_6RE, + C=>I_14RE, + P=>X1); -- P=C+A+B + + a2:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>X1, + B=>X1_2, + C=>X2_4, + P=>KIRE); -- P=C+A+B + + I_1IM<=IM(I_1); + I_6IM<=IM(I_6); + I_14IM<=IM(I_14); + a3:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.IM, +--2008 B=>I_6.IM, +--2008 C=>I_14.IM, + A=>I_1IM, + B=>I_6IM, + C=>I_14IM, + P=>Y1); -- P=C+A+B + + a4:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>Y1, + B=>Y1_2, + C=>Y2_4, + P=>KIIM); -- P=C+A+B + + a5:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>MEQ3, --2008 M=3, + NEGATIVE_B=>CONJUGATE, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>MEQ3, --2008 M=3, + CY2=>CONJUGATE, +--2008 P=>O.RE); -- P=C+A+B + P=>ORE); -- P=C+A+B + + a6:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>nCONJUGATE, + NEGATIVE_B=>MEQ3, --2008 M=3, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>nCONJUGATE, + CY2=>MEQ3, --2008 M=3, +--2008 P=>O.IM); -- P=C+A+B + P=>OIM); -- P=C+A+B + O<=TO_CFIXED(ORE,OIM); + --end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: ADDSUB.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity ADDSUB is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SUB:in BOOLEAN:=FALSE; +-- P:out SIGNED); -- O=A±B + P:out SFIXED); -- O=A±B +end ADDSUB; + +architecture FAST of ADDSUB is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB:SFIXED(SH downto SM); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0"; + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + signal I_4:STD_LOGIC; + begin + I_4<='1' when SUB else '0'; + l6:LUT6_2 generic map(INIT=>(I5 and (I2 xor I3 xor I4)) or (not I5 and ((I2 xor I4) and I3))) + port map(I0=>'0',I1=>'0',I2=>SB(K),I3=>SA(K),I4=>I_4,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + +-- ll:for L in SM to SH+1 generate + ll:for L in SM to SH generate +-- S(L)<=O(L-SM+1); + S(L)<=O(L-SM); + end generate; + S(SH+1)<=S(SH); + + ia:if A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: TABLE.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: TABLE +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, SinCos Table Module +-- +-- Latency is always 2 +-- when INV_FFT=FALSE W=exp(-2.0*PI*i*JK/N) and when INV_FFT=TRUE W=exp(2.0*PI*i*JK/N) +-- to maximize W output bit size utilization W.RE and W.IM are always negative (MSB='1') and that bit could be ignored, this is why W.RE'length can be 19 bits but a single BRAM would still be used +-- when W.RE or W.IM need to be positive CS respectively SS are TRUE, same thing when they are 0.0 CZ respectively SZ are TRUE - the complex multiplier has to use CS, SS, CZ and SZ, not just W to produce the correct result +-- the SIN and COS ROM table sizes are N/4 deep and W.RE'length-1 wide (it is implictly assumed that W.RE and W.IM always have the same range) +-- if STYLE="block" a single dual port BRAM is used for both tables +-- if STYLE="distributed" then two fabric LUT based ROMs are used +-- as a general rule for N<2048 "distributed" should be used, otherwise "block" makes more sense but this is not a hard rule +-- W range is unconstrained but W.RE'high and W.IM'high really have to be 0 all the time, do not use other values +-- the maximum SNR without using extra BRAMs is achieved when W.RE'low and W.IM'low are -18 so W.RE'length and W.IM'length are 19 bits but they can be less than that - this would reduce SNR and save resources only when STYLE="distributed" +-- TABLE.VHD also works with more than 19 bits but the current complex multiplier implementation does not support that - this would essentially double the number of BRAMs and DSP48s used and seems too high a price to pay for a few extra dB of SNR +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use IEEE.MATH_REAL.all; + +use work.COMPLEX_FIXED_PKG.all; + +--!! entity TABLE is -- LATENCY=3 (2 if SEPARATE_SIGN is TRUE) +entity TABLE is -- LATENCY=4 (3 if SEPARATE_SIGN is TRUE) when SPLIT_RADIX=0 else LATENCY=0 + generic(N:INTEGER:=1024; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and J*1 or J*3 with J>0 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + SEPARATE_SIGN:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + STYLE:STRING:="block"); -- use only "block" or "distributed" + port(CLK:in STD_LOGIC; + JK:in UNSIGNED; + VI:in BOOLEAN; + W:out CFIXED; + CS,SS,CZ,SZ:out BOOLEAN; + VO:out BOOLEAN); +end TABLE; + +architecture TEST of TABLE is +--2008 constant WH:INTEGER:=W.RE'high-1+BOOLEAN'pos(SEPARATE_SIGN); +--2008 constant WL:INTEGER:=W.RE'low; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 + constant WH:INTEGER:=(W'high+1)/2-1-1+BOOLEAN'pos(SEPARATE_SIGN); + constant WL:INTEGER:=W'low/2; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 +begin + i0:if SPLIT_RADIX=0 generate + type wSFIXED_VECTOR is array(INTEGER range <>) of SFIXED(WH-1 downto WL); -- local constrained array of SFIXED type +--2008 function LUT_VALUE(N,WH,WL:INTEGER) return SFIXED_VECTOR is +--2008 variable RESULT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL); + function LUT_VALUE(N,WH,WL:INTEGER) return wSFIXED_VECTOR is + variable RESULT:wSFIXED_VECTOR(0 to N/4-1); + begin + RESULT(0):=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + for J in 1 to N/4-1 loop + RESULT(J):=TO_SFIXED(-COS(-2.0*MATH_PI*REAL(J)/REAL(N))+2.0**(WL-1),WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + if RESULT(J)=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL) then + RESULT(J):=TO_SFIXED(-1.0+2.0**WL,WH,WL)(WH-1 downto WL); + end if; + end loop; + return RESULT; + end; + + signal JKD:UNSIGNED(JK'range):=(others=>'0'); + signal KC,KS:UNSIGNED(JK'range):=(others=>'0');--!! + signal DC,C,DS,S:SFIXED(WH-1 downto WL):=(others=>'0'); +--2008 signal LUT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL):=LUT_VALUE(N,WH,WL); + signal LUT:wSFIXED_VECTOR(0 to N/4-1):=LUT_VALUE(N,WH,WL); + attribute rom_style:STRING; + attribute rom_style of LUT:signal is STYLE; + signal RC,RS:BOOLEAN:=FALSE; + signal MC,MS:STD_LOGIC:='0'; + signal CS1,SS1,CS2,SS2:BOOLEAN:=FALSE; + signal W_RE,W_IM:SFIXED((W'high+1)/2-1 downto W'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--!! +--2008 KC<=JK when JK(JK'high-1)='0' else (not JK)+1; +--2008 KS<=(not JK)+1 when JK(JK'high-1)='0' else JK; + if JK(JK'high-1)='0' then + KC<=JK; + KS<=(not JK)+1; + else + KC<=(not JK)+1; + KS<=JK; + end if; + JKD<=JK; + if (JKD and TO_UNSIGNED(2**(JK'length-2)-1,JK'length))=0 then --mask first two MSBs of JK + RC<=JKD(JK'high-1)='1'; + RS<=JKD(JK'high-1)='0'; + else + RC<=FALSE; + RS<=FALSE; + end if; + DC<=LUT(TO_INTEGER(KC and TO_UNSIGNED(2**(KC'length-2)-1,KC'length))); + DS<=LUT(TO_INTEGER(KS and TO_UNSIGNED(2**(KS'length-2)-1,KS'length))); + if RC then + C<=(others=>'0'); + MC<='0'; + else + C<=DC; + MC<='1'; + end if; + if RS then + S<=(others=>'0'); + MS<='0'; + else + S<=DS; + MS<='1'; + end if; + CS1<=JKD(JK'high)=JKD(JK'high-1); + SS1<=(JKD(JK'high)='1') xor INV_FFT; + CS2<=CS1; + SS2<=SS1; + end if; + end process; + + i0:if SEPARATE_SIGN generate +--2008 W.RE<=MC&C; +--2008 W.IM<=MS&S; + W(W'length/2-1+W'low downto W'low)<=CFIXED(MC&C); + W(W'high downto W'length/2+W'low)<=CFIXED(MS&S); + CS<=CS2; + SS<=SS2; +-- else generate + end generate; + i1:if not SEPARATE_SIGN generate + signal WRE,WIM:SFIXED(WH downto WL):=(others=>'0'); + attribute keep:STRING; + attribute keep of WRE:signal is "yes"; + attribute keep of WIM:signal is "yes"; + signal ZERO:SFIXED(WH downto WL):=TO_SFIXED(0.0,WH,WL); + begin + WRE<=MC&C; + WIM<=MS&S; + + process(CLK) + begin + if rising_edge(CLK) then + CS<=CS2; + SS<=SS2; + CZ<=WRE(WRE'high)='0'; + SZ<=WIM(WIM'high)='0'; + end if; + end process; + ar:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WRE, + SUB=>CS2, +--2008 P=>W.RE); -- P=±B + P=>W_RE); -- P=±B + ai:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WIM, + SUB=>SS2, +--2008 P=>W.IM); -- P=±B + P=>W_IM); -- P=±B + W(W'length/2-1+W'low downto W'low)<=CFIXED(W_RE); + W(W'high downto W'length/2+W'low)<=CFIXED(W_IM); +-- end; + end generate; + +--!! b2:entity work.BDELAY generic map(SIZE=>3-BOOLEAN'pos(SEPARATE_SIGN)) + b2:entity work.BDELAY generic map(SIZE=>4-BOOLEAN'pos(SEPARATE_SIGN)) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- else generate + i1:if SPLIT_RADIX>0 generate + begin + i0:if SEPARATE_SIGN generate +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + end generate; +-- else generate + ii:if not SEPARATE_SIGN generate + begin +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + CZ<=(SPLIT_RADIX=N/4) or (SPLIT_RADIX=3*N/4); + SZ<=(SPLIT_RADIX=0) or (SPLIT_RADIX=N/2); +-- end; + end generate; + VO<=VI; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3 +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Complex Multiplier Using 3 DSP48E2s +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3 is -- LATENCY=6 + generic(ROUNDING:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED; -- I.RE'length and I.IM'length<27 + W:in CFIXED; -- W must be (1 downto -16) or (1 downto -17) + CS,SS,CZ,SZ:in BOOLEAN:=FALSE; + VI:in BOOLEAN; + O:out CFIXED; + VO:out BOOLEAN); +end CM3; + +architecture TEST of CM3 is + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute loc:STRING; + +--2008 constant HMAX:INTEGER:=MAX(I.RE'high,I.IM'high)+MAX(W.RE'high,W.IM'high)+3; +--2008 constant LMIN:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(I.RE'low,I.IM'low)+work.COMPLEX_FIXED_PKG.MIN(W.RE'low,W.IM'low); + constant HMAX:INTEGER:=(I'high+1)/2-1+(W'high+1)/2-1+3; + constant LMIN:INTEGER:=I'low/2+W'low/2; + +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,1) downto MAX(W.RE'low,-16)); +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,0) downto MAX(W.RE'low,-17)); +--2008 signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'low+17,1) downto W.RE'low); -- we only have 18 bits max to work with +--2008 signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); +--2008 signal IRE1D,IRE2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); +--2008 signal IIM1D,IIM2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W'low/2+17,1) downto W'low/2); -- we only have 18 bits max to work with + signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal IRE,IRE1D,IRE2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM,IIM1D,IIM2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal CS2D,SS2D:BOOLEAN; + signal C0S1:BOOLEAN:=FALSE; + signal P1,P2,P3:SFIXED(HMAX downto LMIN); + signal P2D:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal C1,C2,C3:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal AC1,AC2:STD_LOGIC_VECTOR(29 downto 0); + signal BC1:STD_LOGIC_VECTOR(17 downto 0); + signal PC1,PC2:STD_LOGIC_VECTOR(47 downto 0); +--2008 signal A_ZERO:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal A_ZERO:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal B_ZERO:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal C_ZERO:SFIXED(HMAX downto LMIN):=TO_SFIXED(0.0,HMAX,LMIN); + signal BR,BI:BOOLEAN; + signal iO:CFIXED(O'range); +begin +--!! +--2008 WRE<=RESIZE(W.RE,WRE); + WRE<=RESIZE(RE(W),WRE); +--!! WRE<=TO_SFIXED(1.0-2.0**WRE'low,WRE) when W.RE=TO_SFIXED(1.0,W.RE) else RESIZE(W.RE,WRE); +--!! +--2008 WIM<=RESIZE(W.IM,WIM); + WIM<=RESIZE(IM(W),WIM); + process(CLK) + begin + if rising_edge(CLK) then + WRE1D<=WRE; +--2008 IRE1D<=I.RE; +--2008 IIM1D<=I.IM; + IRE1D<=RE(I); + IIM1D<=IM(I); +--2008 C0S1<=CZ and (W.IM(W.IM'high)='0'); + C0S1<=CZ and (W(W'high)='0'); +--!! + NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! if WRE1D=TO_SFIXED(-1.0,WRE1D) then +--!! for K in NWRE2D'range loop +--!! NWRE2D(K)<=not WRE1D(K); +--!! end loop; +--!! else +--!! NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! end if; +--!! + IRE2D<=IRE1D; + IIM2D<=IIM1D; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and C0S1 then + if (W'low/2=-17) and C0S1 then + C1<=RESIZE(SHIFT_LEFT(IRE1D+IIM1D,1),C1); + else + C1<=TO_SFIXED(0.0,C1); + end if; + end if; + end process; + + IRE<=RE(I); + IIM<=IM(I); + dsp1:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"00101", -- (D+A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110000101", -- PCOUT=-C-(D+A1)*B2 +--2008 A=>I.RE, + A=>IRE, + B=>WIM, + C=>C1, +--2008 D=>I.IM, + D=>IIM, + ACOUT=>AC1, + BCOUT=>BC1, + P=>P1, + PCOUT=>PC1); + +-- C2<=TO_SFIXED(2.0**(O.RE'low-1),C2) when ROUNDING else TO_SFIXED(0.0,C2); + BR<=W(W'length/2-1+W'low)='0'; + BI<=W(W'high)='0'; + cd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.RE(W.RE'high)='0', + I=>BR, + O=>CS2D); + sd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.IM(W.IM'high)='0', + I=>BI, + O=>SS2D); + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and CS2D=SS2D then + if (W'low/2=-17) and CS2D=SS2D then + if CS2D then + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(I.RE,C2); + C2<=RESIZE(SHIFT_LEFT(IRE2D,1),C2); + end if; + else + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(-I.RE,C2); + C2<=RESIZE(-SHIFT_LEFT(IRE2D,1),C2); + end if; + end if; + else + if ROUNDING then +--2008 C2<=TO_SFIXED(2.0**(O.RE'low-1),C2); + C2<=TO_SFIXED(2.0**(O'low/2-1),C2); + else + C2<=TO_SFIXED(0.0,C2); + end if; + end if; + end if; + end process; + + dsp2:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL=>"AD", -- Selects B input to multiplier (AD, B) + B_INPUT=>"CASCADE", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL=>"B", -- Selects input to preadder (A, B) + AREG=>2) -- Pipeline stages for A (0-2) + port map(CLK=>CLK, + INMODE=>"10100", -- (D+B1)*A2 + ALUMODE=>"0000", -- Z+W+X+Y + OPMODE=>"110010101", -- PCOUT=PCIN+C+(D+B1)*A2 + A=>A_ZERO, + B=>B_ZERO, + C=>C2, + D=>WRE1D, + ACIN=>AC1, + BCIN=>BC1, + PCIN=>PC1, + ACOUT=>AC2, + P=>P2, + PCOUT=>PC2); + +-- C3<=RESIZE(SHIFT_RIGHT(P1,-16-W.RE'low),P1); + C3<=P1; + dsp3:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"01101", --5x"0C", -- (D-A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110010101", -- PCOUT=PCIN-C-(D-A1)*B2 + A=>A_ZERO, + B=>NWRE2D, + C=>C3, + D=>IIM2D, + ACIN=>AC2, + PCIN=>PC2, + P=>P3); + + process(CLK) + begin + if rising_edge(CLK) then +--2008 O.RE<=RESIZE(P2,O.RE); + P2D<=P2; + end if; + end process; +--2008 O.IM<=RESIZE(P3,O.IM); +-- O<=RESIZE(TO_CFIXED(P2D,P3),O); + O<=RESIZE(TO_CFIXED(P2D,P3),iO); + + bd:entity work.BDELAY generic map(SIZE=>6) + port map(CLK=>CLK, + I=>VI, + O=>VO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. 3 +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3FFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic Complex Multiplier Stage Module - uses 3 DSP48s/complex multiplication +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3FFT is -- LATENCY=10 + generic(N:INTEGER; + RADIX:INTEGER; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and 1 or 3 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CM3FFT; + +architecture TEST of CM3FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + function STYLE(N:INTEGER) return STRING is + begin + if N>BRAM_THRESHOLD then + return "block"; + else + return "distributed"; + end if; + end; + + function TABLE_LATENCY(SPLIT_RADIX:INTEGER) return INTEGER is + begin + if SPLIT_RADIX=0 then + return 4; + else + return 0; + end if; + end; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + signal CNT:UNSIGNED(L2N-L2R-1 downto 0):=(others=>'0'); + signal I0:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal O0:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + +--!! cd:entity work.CDELAY generic map(SIZE=>3+6) + I0<=ELEMENT(I,0,RADIX); + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, +--2008 I=>I(I'low), +--2008 O=>O(O'low)); + I=>I0, + O=>O0); + O(O'length/RADIX-1+O'low downto O'low)<=CFIXED_VECTOR(O0); + + process(CLK) + begin + if rising_edge(CLK) then + if not VI or (SPLIT_RADIX/=0) then + CNT<=(others=>'0'); + else + CNT<=CNT+1; + end if; + end if; + end process; + +--2008 lk:for J in 1 to I'length-1 generate + lk:for J in 1 to RADIX-1 generate + signal JK:UNSIGNED(L2N-1 downto 0):=(others=>'0'); +--2008 signal W:CFIXED(RE(W_high downto W_low),IM(W_high downto W_low)); + signal W:CFIXED(2*(W_high+1)-1 downto 2*W_low); + signal V,CZ:BOOLEAN; +--2008 signal ID:CFIXED(RE(I(I'low).RE'high downto I(I'low).RE'low),IM(I(I'low).IM'high downto I(I'low).IM'low)); + signal ID:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal IJ:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal OJ:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if SPLIT_RADIX=0 then + if not VI or (CNT=N/RADIX-1) then + JK<=(others=>'0'); + else + JK<=JK+J; + end if; + else + JK<=TO_UNSIGNED(J*SPLIT_RADIX,JK'length); + end if; + end if; + end process; + + ut:entity work.TABLE generic map(N=>N, + INV_FFT=>INV_FFT, + DSP48E=>DSP48E, + STYLE=>STYLE(N/4)) + port map(CLK=>CLK, + JK=>JK, + VI=>VI, + CZ=>CZ, + W=>W, + VO=>V); + + IJ<=ELEMENT(I,J,RADIX); +--!! cd:entity work.CDELAY generic map(SIZE=>3) + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)) + port map(CLK=>CLK, +--2008 I=>I(I'low+J), + I=>IJ, + O=>ID); + + u1:entity work.CM3 generic map(ROUNDING=>ROUNDING, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ID, + W=>W, + CZ=>CZ, + VI=>V, +--2008 O=>O(O'low+J), + O=>OJ, + VO=>open); + O((J+1)*O'length/RADIX-1+O'low downto J*O'length/RADIX+O'low)<=CFIXED_VECTOR(OJ); + end generate; + +--!! bd:entity work.BDELAY generic map(SIZE=>3+6) + bd:entity work.BDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>VI, + O=>VO); + +--!! ud:entity work.UDELAY generic map(SIZE=>3+6) + ud:entity work.UDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>SI, + O=>SO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: PARFFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity PARFFT is + generic(N:INTEGER:=4; + F:INTEGER:=0; + INV_FFT:BOOLEAN:=FALSE; + ROUNDING:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-16; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end PARFFT; + +architecture TEST of PARFFT is + constant I_low:INTEGER:=I'low/2/N; + constant I_high:INTEGER:=I'length/2/N-1+I_low; + constant O_low:INTEGER:=O'low/2/N; + constant O_high:INTEGER:=O'length/2/N-1+O_low; + + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + constant L2N:INTEGER:=LOG2(N); +begin +--2008 assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + + f0:if F=0 generate + begin + l2:if N=2 generate -- FFT2 case + signal I0,I1:CFIXED(2*I_high+1 downto 2*I_low); + signal O0,O1:CFIXED(2*O_high+1 downto 2*O_low); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,2); + I1<=ELEMENT(I,1,2); +-- complex add/sub butterfly with scaling and overflow detection + bf:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I1, + SCALE=>SI(SI'low), + O0=>O0, + O1=>O1, + OVR=>SO(SO'high)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/2-1+O'low downto 0*O'length/2+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/2-1+O'low downto 1*O'length/2+O'low)<=CFIXED_VECTOR(O1); + + process(CLK) + begin + if rising_edge(CLK) then + iSO<=SI(SI'high downto SI'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>1) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=4 generate -- FFT4 case + l4:if N=4 generate -- FFT4 case + signal I0,I1,I2,I3:CFIXED(2*I_high+1 downto 2*I_low); + signal P0,P1,P2,P3,P3S:CFIXED(2*I_high+3 downto 2*I_low); + signal O0,O1,O2,O3,O1S,O3S:CFIXED(2*O_high+1 downto 2*O_low); + signal S:UNSIGNED(SI'range):=(others=>'0'); + signal OVR1,OVR2:UNSIGNED(1 downto 0); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,4); + I1<=ELEMENT(I,1,4); + I2<=ELEMENT(I,2,4); + I3<=ELEMENT(I,3,4); +-- complex add/sub butterflies with scaling and overflow detection + u0:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I2, + SCALE=>SI(SI'low), + O0=>P0, + O1=>P1, + OVR=>OVR1(0)); + + u1:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I1, + I1=>I3, + SCALE=>SI(SI'low), + O0=>P2, + O1=>P3, + OVR=>OVR1(1)); + + process(CLK) + begin + if rising_edge(CLK) then + S<=(OVR1(0) or OVR1(1))&SI(SI'high downto SI'low+1); + end if; + end process; + + u2:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P0, + I1=>P2, + SCALE=>S(S'low), + O0=>O0, + O1=>O2, + OVR=>OVR2(0)); + + P3S<=SWAP(P3); + u3:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P1, + I1=>P3S, + SCALE=>S(S'low), + O0=>O1S, + O1=>O3S, + OVR=>OVR2(1)); + O1<=TO_CFIXED(RE(O1S),IM(O3S)); + O3<=TO_CFIXED(RE(O3S),IM(O1S)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/4-1+O'low downto 0*O'length/4+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/4-1+O'low downto 1*O'length/4+O'low)<=CFIXED_VECTOR(O1); + O((2+1)*O'length/4-1+O'low downto 2*O'length/4+O'low)<=CFIXED_VECTOR(O2); + O((3+1)*O'length/4-1+O'low downto 3*O'length/4+O'low)<=CFIXED_VECTOR(O3); + + SO(SO'high)<=(OVR2(0) or OVR2(1)); + process(CLK) + begin + if rising_edge(CLK) then + iSO<=S(S'high downto S'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=8 generate -- FFT8 case + l8:if N=8 generate -- FFT8 case +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/8/2-(I'high+1)/8/2; + constant X:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,1); -- ModelSim workaround + signal iV:BOOLEAN_VECTOR(0 to 3); +--2008 signal S:UNSIGNED_VECTOR(0 to 3)(SI'range); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:TUV(0 to 3); + signal SS:UNSIGNED(SI'range); + signal P:CFIXED_VECTOR(I'high+8*2*X downto I'low); + signal VP:BOOLEAN; + signal SP:UNSIGNED(SI'range); + signal oV:BOOLEAN_VECTOR(0 to 1); +--2008 signal oS:UNSIGNED_VECTOR(0 to 1)(SO'range); + signal oS:TUV(0 to 1); + begin + s1:for K in 0 to 3 generate +--2008 signal II:CFIXED_VECTOR(0 to 1)(RE(I(0).RE'high downto I(0).RE'low),IM(I(0).IM'high downto I(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 1)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); + signal II:CFIXED_VECTOR(4*(I_high+1)-1 downto 4*I_low); + signal OO:CFIXED_VECTOR(4*(I_high+1+2*X)-1 downto 4*I_low); + signal OO0,OO1:CFIXED(2*(I_high+1+2*X)-1 downto 2*I_low); + signal P0,P1:CFIXED(I'length/8+2*X-1+I'low/8 downto I'low/8); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=I(K); +--2008 II(1)<=I(K+4); + II((0+1)*II'length/2-1+II'low downto 0*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K,8)); + II((1+1)*II'length/2-1+II'low downto 1*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K+4,8)); + p2:entity work.PARFFT generic map(N=>2, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>iV(K), + SO=>S(K)); + OO0<=ELEMENT(OO,0,2); + OO1<=ELEMENT(OO,1,2); + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>OO(0), +--2008 O=>P(2*K+0)); + I=>OO0, + O=>P0); + ck:entity work.CKCM generic map(DSP48E=>DSP48E, + M=>K, + ROUNDING=>ROUNDING, + CONJUGATE=>INV_FFT) + port map(CLK=>CLK, +--2008 I=>OO(1), +--2008 O=>P(2*K+1)); + I=>OO1, + O=>P1); + P((2*K+1)*P'length/8-1+P'low downto (2*K+0)*P'length/8+P'low)<=CFIXED_VECTOR(P0); + P((2*K+2)*P'length/8-1+P'low downto (2*K+1)*P'length/8+P'low)<=CFIXED_VECTOR(P1); + end generate; + SS(SI'high)<=S(0)(SI'high) or S(1)(SI'high) or S(2)(SI'high) or S(3)(SI'high) when iV(0) else '0'; + SS(SI'high-1 downto SI'low)<=S(0)(SI'high-1 downto SI'low); + ud:entity work.UDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>SS, + O=>SP); + bd:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>iV(0), + O=>VP); + s2:for K in 0 to 1 generate +--2008 signal II:CFIXED_VECTOR(0 to 3)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 3)(RE(O(0).RE'high downto O(0).RE'low),IM(O(0).IM'high downto O(0).IM'low)); + signal II:CFIXED_VECTOR((P'high+1)/2-1 downto P'low/2); + signal OO:CFIXED_VECTOR((O'high+1)/2-1 downto O'low/2); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=P(K+0); +--2008 II(1)<=P(K+2); +--2008 II(2)<=P(K+4); +--2008 II(3)<=P(K+6); + II((0+1)*II'length/4-1+II'low downto 0*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+0,8)); + II((1+1)*II'length/4-1+II'low downto 1*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+2,8)); + II((2+1)*II'length/4-1+II'low downto 2*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+4,8)); + II((3+1)*II'length/4-1+II'low downto 3*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+6,8)); + p2:entity work.PARFFT generic map(N=>4, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VP, + SI=>SP, + O=>OO, + VO=>oV(K), + SO=>oS(K)); +--2008 O(K+0)<=OO(0); +--2008 O(K+2)<=OO(1); +--2008 O(K+4)<=OO(2); +--2008 O(K+6)<=OO(3); + O((K+0+1)*O'length/8-1+O'low downto (K+0)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,0,4)); + O((K+2+1)*O'length/8-1+O'low downto (K+2)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,1,4)); + O((K+4+1)*O'length/8-1+O'low downto (K+4)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,2,4)); + O((K+6+1)*O'length/8-1+O'low downto (K+6)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,3,4)); + end generate; + VO<=oV(0); + SO(SO'high downto SO'high-1)<=oS(0)(SO'high downto SO'high-1) or oS(1)(SO'high downto SO'high-1) when oV(0) else "00"; + SO(SO'high-2 downto SO'low)<=oS(0)(SO'high-2 downto SO'low); +-- end; + end generate; +-- elsif N=2**L2N generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation + ln:if (N>8) and (N=2**L2N) generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/N/2-(I'high+1)/N/2; + constant X1:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-2); -- ModelSim workaround + constant X2:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-1); -- ModelSim workaround + function MUL_LATENCY(N:INTEGER) return INTEGER is + begin + return 6; + end; + function LATENCY(N:INTEGER) return INTEGER is + begin + return LOG2(N)*4-6; + end; +--2008 signal IU:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal U,UD:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); + signal IU:CFIXED_VECTOR((I'high+1)/2-1 downto I'low/2); + signal U,UD:CFIXED_VECTOR((I'high+1)/2-1+N/2*2*X2 downto I'low/2); + signal SU,SUD:UNSIGNED(SI'range); + signal VU,VU4D:BOOLEAN; +--2008 signal ZO:CFIXED_MATRIX(0 to N/4-1)(0 to 1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(2*2*(I_high+X1+1)-1 downto 2*2*I_low); -- unconstrained array of CFIXED_VECTOR + signal ZO:CFIXED_MATRIX(0 to N/4-1); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); +--2008 signal S1:UNSIGNED_VECTOR(0 to 1)(SI'range); + signal S1:TUV(0 to 1); + signal S1I:UNSIGNED(SI'range); +--2008 signal S2:UNSIGNED_VECTOR(0 to N/4-1)(SI'range); + signal S2:TUV(0 to N/4-1); + signal S2I:UNSIGNED(SI'range):=(others=>'0'); +--2008 signal S:UNSIGNED_VECTOR(0 to N/2-1)(SI'range); + signal S:TUV(0 to N/2-1); + begin + lk:for K in 0 to N/2-1 generate +--2008 IU(K)<=I(I'low+2*K); + IU((K+1)*IU'length/N*2-1+IU'low downto K*IU'length/N*2+IU'low)<=CFIXED_VECTOR(ELEMENT(I,2*K,N)); + end generate; + pu:entity work.PARFFT generic map(N=>N/2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IU, + VI=>VI, + SI=>SI, + O=>U, + VO=>VU, + SO=>SU); + du:for K in 0 to N/2-1 generate + signal UK,UDK:CFIXED((UD'high+1)/N*2-1 downto UD'low/N*2); + begin + UK<=ELEMENT(U,K,N/2); + cd:entity work.CDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+1-LATENCY(N/2))--3) -- when CMUL latency is 6 + port map(CLK=>CLK, +--2008 I=>U(K), +--2008 O=>UD(K)); + I=>UK, + O=>UDK); + UD((K+1)*UD'length/N*2-1+UD'low downto K*UD'length/N*2+UD'low)<=CFIXED_VECTOR(UDK); + end generate; + u4:entity work.UDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>SU, + O=>SUD); + b5:entity work.BDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>VU, + O=>VO); + ll:for L in 0 to 1 generate +--2008 signal IZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal Z,OZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + signal IZ:CFIXED_VECTOR((I'high+1)/4-1 downto I'low/4); + signal Z,OZ:CFIXED_VECTOR((I'high+1)/4-1+N/4*2*X1 downto I'low/4); + signal SZ:UNSIGNED(SI'range); + signal SM:UNSIGNED(SI'range); + signal VZ:BOOLEAN; + begin + li:for J in 0 to N/4-1 generate +--2008 IZ(J)<=I(I'low+4*J+2*L+1); + IZ(2*(J+1)*(I_high-I_low+1)-1+IZ'low downto 2*J*(I_high-I_low+1)+IZ'low)<=CFIXED_VECTOR(ELEMENT(I,4*J+2*L+1,N)); + end generate; + pe:entity work.PARFFT generic map(N=>N/4, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IZ, + VI=>VI, + SI=>SI, + O=>Z, + VO=>VZ, + SO=>SZ); + me:entity work.CM3FFT generic map(N=>N, + RADIX=>N/4, + SPLIT_RADIX=>2*L+1, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>Z, + VI=>VZ, + SI=>SZ, + O=>OZ, + VO=>open, + SO=>S1(L)); + lo:for J in 0 to N/4-1 generate +--2008 ZO(J)(L)<=OZ(J); + ZO(J)((L+1)*ZO(J)'length/2-1+ZO(J)'low downto L*ZO(J)'length/2+ZO(J)'low)<=CFIXED_VECTOR(ELEMENT(OZ,J,N/4)); + end generate; + end generate; + S1I<=S1(0) or S1(1); + l2:for J in 0 to N/4-1 generate +--2008 signal O2:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal IE,IO:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal OE,OO:CFIXED_VECTOR(0 to 1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal O2:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal IE,IO:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal OE,OO:CFIXED_VECTOR(2*2*(O_high+1)-1 downto 2*2*O_low); + begin + p2:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ZO(J), + VI=>TRUE, + SI=>S1I, + O=>O2, + VO=>open, + SO=>S2(J)); +--2008 IE(0)<=UD(J); +--2008 IE(1)<=O2(0); + IE((0+1)*IE'length/2-1+IE'low downto 0*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(UD,J,N/2)); + IE((1+1)*IE'length/2-1+IE'low downto 1*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(O2,0,2)); + pe:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IE, + VI=>TRUE, + SI=>S2I, + O=>OE, + VO=>open, + SO=>S(2*J)); +--2008 O(O'low+J)<=OE(0); +--2008 O(O'low+J+N/2)<=OE(1); +--2008 IO(0)<=UD(J+N/4); +--2008 IO(1).RE<=O2(1).IM; +--2008 IO(1).IM<=O2(1).RE; +-- O((J+1)*O'length/N-1+O'low downto J*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); +-- O((J+N/2+1)*O'length/N-1+O'low downto (J+N/2)*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + O(2*(J+1)*(O_high-O_low+1)-1+O'low downto 2*J*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); + O(2*(J+N/2+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/2)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + IO((0+1)*IO'length/2-1+IO'low downto 0*IO'length/2+IO'low)<=CFIXED_VECTOR(ELEMENT(UD,J+N/4,N/2)); + IO((1+1)*IO'length/2-1+IO'low downto 1*IO'length/2+IO'low)<=CFIXED_VECTOR(TO_CFIXED(IM(ELEMENT(O2,1,2)),RE(ELEMENT(O2,1,2)))); + po:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IO, + VI=>TRUE, + SI=>S2I, + O=>OO, + VO=>open, + SO=>S(2*J+1)); + ii:if INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(1).RE; +--2008 O(O'low+J+N/4).IM<=OO(0).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(0).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(1).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- end; + end generate; +-- else generate + id:if not INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(0).RE; +--2008 O(O'low+J+N/4).IM<=OO(1).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(1).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(0).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- end; + end generate; + end generate; + process(S2) + variable vS2:UNSIGNED(SI'range); + begin + vS2:=SUD; + for K in S2'range loop + vS2:=vS2 or S2(K); + end loop; + S2I<=vS2; + end process; + process(S) + variable vS:UNSIGNED(SI'range); + begin + vS:=(others=>'0'); + for K in S'range loop + vS:=vS or S(K); + end loop; + SO<=vS; + end process; +-- end; + end generate; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=N/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.PARFFT generic map(N=>G, + F=>0, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ?? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: INPUT_SWAP.vhd +-- / / Date Last Modified: 14 February 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: INPUT_SWAP +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Input Order Swap Module for Systolic FFT +-- The module takes N samples, I'length per clock, in natural input order +-- and outputs them in natural transposed order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity INPUT_SWAP is + generic(N:INTEGER; -- N must be a power of 2 + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + USE_CB:BOOLEAN:=TRUE); -- if FALSE use alternate architecture + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; -- I'length must be a divisor of N, so it is also a power of 2 + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end INPUT_SWAP; + +architecture TEST of INPUT_SWAP is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs in last stage + + function RS(K:INTEGER) return STRING is + begin + if K) of CFIXED_VECTOR(I'range); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + + i0:if USE_CB or (L2N<=2*L2R) generate + constant SIZE:INTEGER:=L2N/L2R; -- floor(LOG2(N)/LOG2(RADIX)) + + signal V:BOOLEAN_VECTOR(0 to SIZE-1); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE-1)(SI'range); +--2008 signal D:CFIXED_MATRIX(0 to SIZE-1)(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:UNSIGNED_VECTOR(0 to SIZE-1); + signal D:iCFIXED_MATRIX(0 to SIZE-1); + begin + D(D'low)<=I; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-2 generate + bc:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>RADIX**K, + INPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K/RADIX), -- this helps reduce + OUTPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K mod RADIX**(SIZE-2)), -- RAM count and + SHORTEN_VO_BY=>(RADIX-1)*RADIX**K mod ((RADIX-1)*RADIX**(SIZE-2))) -- latency by N/RADIX/RADIX-1 clocks + port map(CLK=>CLK, + I=>D(K), + VI=>V(K), + SI=>S(K), + O=>D(K+1), + VO=>V(K+1), + SO=>S(K+1)); + end generate; +--Last stage, it becomes a trivial assignment if F=0 + bl:block + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SI'range); + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + lj:for J in OV'range generate +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin + bc:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>RADIX**(SIZE-1)) + port map(CLK=>CLK, +--2008 I=>D(D'high)(I'low+G*J+0 to I'low+G*J+G-1), + I=>D(D'high)(I'length/H*(J+1)-1+I'low downto I'length/H*J+I'low), + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>OV(J), + SO=>OS(J)); + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(K); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+1)-1+OO'low downto O'length/SSR*K+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); + end block; +--2008 end; + end generate; +--2008 else generate + i1:if (not USE_CB) and (L2N>2*L2R) generate + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + signal WSEL:UNSIGNED(LOG2(WCNT'length)-1 downto 0):=TO_UNSIGNED(0,LOG2(RCNT'length)); + signal RSEL:UNSIGNED(LOG2(RCNT'length)-1 downto 0):=TO_UNSIGNED(L2N-2*L2R,LOG2(RCNT'length)); +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal OV:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + if RSEL'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + WA<=ROTATE_LEFT(WCNT,TO_INTEGER(WSEL)); + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + RA<=ROTATE_LEFT(RCNT,TO_INTEGER(RSEL)); + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); + IO<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>OV); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+5) + port map(CLK=>CLK, + I=>SI, + O=>S); + + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>IO, + VI=>OV, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SYSTOLIC_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SYSTOLIC_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Systolic FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity SYSTOLIC_FFT is + generic(N:INTEGER; + SSR:INTEGER; --93 + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end SYSTOLIC_FFT; + +architecture TEST of SYSTOLIC_FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB and PARFFT in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs and PARFFTsin last stage + constant SIZE:INTEGER:=(L2N-1)/L2R; -- ceil(LOG2(N)/LOG2(RADIX)), number of stages +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/2/SSR-(I'high+1)/2/SSR; + +-- constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((SIZE-1)*L2R,BIT_GROWTH); + constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); +--2008 signal D:CFIXED_MATRIX(0 to SIZE)(I'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(O'range); -- unconstrained array of CFIXED_VECTOR + signal D:CFIXED_MATRIX(0 to SIZE); + signal V:BOOLEAN_VECTOR(0 to SIZE); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE)(SI'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); --93 + signal S:UNSIGNED_VECTOR(0 to SIZE); + +-- constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(L2N,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal OO:CFIXED_VECTOR(O'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal OO:CFIXED_VECTOR(O'range); +begin +--2008 lj:for J in I'range generate +--2008 D(D'low)(J)<=RESIZE(I(J),D(D'low)(J)); + lj:for J in 0 to SSR-1 generate + D(D'low)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(I,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-1 generate + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(K*L2R,BIT_GROWTH); + constant XO:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((K+1)*L2R,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal DM,DB,DO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XO downto I(I'low).RE'low),IM(I(I'low).IM'high+XO downto I(I'low).IM'low)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal DM,DB,DO:CFIXED_VECTOR(I'high+2*SSR*XO downto I'low); + signal VM,VB:BOOLEAN; + signal SM,SB:UNSIGNED(SI'range); + begin +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(K)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(K),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, --93 + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(K), + SI=>S(K), + O=>DM, + VO=>VM, + SO=>SM); + cm:entity work.CM3FFT generic map(N=>N/(RADIX**K), + RADIX=>RADIX, --93 + INV_FFT=>FALSE, + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DM, + VI=>VM, + SI=>SM, + O=>DB, + VO=>VB, + SO=>SB); + + bc:entity work.CB generic map(SSR=>RADIX, --93 + F=>F*BOOLEAN'pos(K=SIZE-1), + PACKING_FACTOR=>N/(RADIX**(K+2))*BOOLEAN'pos(KBRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DB, + VI=>VB, + SI=>SB, + O=>DO, + VO=>V(K+1), + SO=>S(K+1)); +--2008 lo:for J in 0 to I'length-1 generate +--2008 D(K+1)(J)<=RESIZE(DO(DO'low+J),D(K+1)(J)); + lo:for J in 0 to SSR-1 generate + D(K+1)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(DO,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + end generate; +--last PARFFT stage +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(D'high)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(D'high),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, + F=>F, + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>VO, + SO=>SO); + lo:for J in 0 to H-1 generate + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(OO'low+K+G*J); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+G*J+1)-1+OO'low downto O'length/SSR*(K+G*J)+OO'low); + end generate; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DS.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DS +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Transposed Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DS is -- LATENCY=0 when N=2*SSR else LATENCY=N/SSR+1 + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DS; + +architecture TEST of DS is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + + function RS(K:INTEGER) return STRING is + begin + if K) of UNSIGNED(RCNT'range); --93 + function IDENTITY(K:INTEGER) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(0 to K-1);--93 (LOG2(K)-1 downto 0); + begin + for J in RESULT'range loop + RESULT(J):=TO_UNSIGNED(J,RESULT(J)'length); + end loop; + return RESULT; + end; + + function PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT((A'length/L2R-1-J)*L2R+K+F):=A(J*L2R+K); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(K):=A(A'length/L2R*L2R+K); + end loop; + end loop; + return RESULT; + end; + + function INVERSE_PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT(J*L2R+K):=A((A'length/L2R-1-J)*L2R+K+F); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(A'length/L2R*L2R+K):=A(K); + end loop; + end loop; + return RESULT; + end; + +--2008 signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1)(LOG2(WCNT'length)-1 downto 0):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); +--2008 signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1)(LOG2(RCNT'length)-1 downto 0):=IDENTITY(RCNT'length); + signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); + signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1):=IDENTITY(RCNT'length); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i0:if L2N-L2R<2 generate + O<=I; + VO<=VI; + SO<=SI; +--2008 else generate + end generate; + i1:if L2N-L2R>=2 generate + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + RSEL<=PERMUTE(WSEL); + end if; + RCNT<=RCNT+1; + else + RCNT<=(others=>'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in WCNT'range loop + WA(K)<=WCNT(TO_INTEGER(WSEL(K))); + end loop; + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in RCNT'range loop + RA(K)<=RCNT(TO_INTEGER(RSEL(K))); + end loop; + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + type iCFIXED_MATRIX is array(NATURAL range <>) of CFIXED_VECTOR(I'range); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); +--2008 O(K)<=Q; + O<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>VO); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX+1) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DSN.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DSN +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Natural Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DSN is + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DSN; + +architecture TEST of DSN is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + constant H:INTEGER:=RADIX/G; +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i1:if L2N<2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SI'range); + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SO'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SO'range); --93 + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + sd:entity work.DS generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + lk:for K in 0 to H-1 generate +----2008 signal II,OO:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal II,OO:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + begin + li:for J in 0 to G-1 generate +--2008 II(J)<=IO(IO'low+K+H*J); + II(I'length/SSR*(J+1)-1+II'low downto I'length/SSR*J+II'low)<=IO(I'length/SSR*(K+H*J+1)-1+I'low downto I'length/SSR*(K+H*J)+I'low); + end generate; + ci:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OO, + VO=>OV(K), + SO=>OS(K)); + lo:for J in 0 to G-1 generate +----2008 O(O'low+K*G+J)<=OO(J); + O(O'length/SSR*(K*G+J+1)-1+O'low downto O'length/SSR*(K*G+J)+O'low)<=OO(O'length/SSR*(J+1)-1+OO'low downto O'length/SSR*J+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); +--2008 end; + end generate; +--2008 elsif L2N=2*L2R generate + i2:if L2N=2*L2R generate + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>O, + VO=>VO, + SO=>SO); +--2008 else generate + end generate; + i3:if L2N>2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>N/RADIX/RADIX, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + + sd:entity work.DS generic map(N=>N/RADIX, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>IO, + VI=>V, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: VECTOR_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: VECTOR_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Top Level Test Module for SYSTOLIC_FFT +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity VECTOR_FFT is + generic(SSR:INTEGER:=8;--4; + N:INTEGER:=16384;--8192;--4096;--1024; + I_high:INTEGER:=0; + I_low:INTEGER:=-17; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; +--2008 I:in CFIXED_VECTOR(0 to RADIX-1)(RE(I_high downto I_low),IM(I_high downto I_low)); + I:in CFIXED_VECTOR(SSR*2*(I_high-I_low+1)-1 downto 0); + VI:in BOOLEAN; + SI:in UNSIGNED(LOG2(N)-1 downto 0); +--2008 O:out CFIXED_VECTOR(0 to RADIX-1)(RE(O_high downto O_low),IM(O_high downto O_low)); + O:out CFIXED_VECTOR(SSR*2*(O_high-O_low+1)-1 downto 0); + VO:out BOOLEAN; + SO:out UNSIGNED(LOG2(N)-1 downto 0)); +end VECTOR_FFT; + +architecture TEST of VECTOR_FFT is + function TO_SFIXED(S:STD_LOGIC_VECTOR;I:SFIXED) return SFIXED is + variable R:SFIXED(I'range); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + + function TO_STD_LOGIC_VECTOR(S:SFIXED) return STD_LOGIC_VECTOR is + variable R:STD_LOGIC_VECTOR(S'length-1 downto 0); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + +--2008 signal II:CFIXED_VECTOR(I'range)(RE(I_high downto I_low),IM(I_high downto I_low)); + signal II:CFIXED_VECTOR(I'range); + signal V,VOFFT,VODS:BOOLEAN; + signal S,SFFT,SODS:UNSIGNED(SI'range); +--2008 signal OFFT,ODS:CFIXED_VECTOR(O'range)(RE(O_high downto O_low),IM(O_high downto O_low)); + signal OFFT,ODS:CFIXED_VECTOR(O'range); +begin + u0:entity work.INPUT_SWAP generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>II, + VO=>V, + SO=>S); + + u1:entity work.SYSTOLIC_FFT generic map(N=>N, + SSR=>SSR, --93 + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OFFT, + VO=>VOFFT, + SO=>SFFT); + + u2:entity work.DSN generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>OFFT, + VI=>VOFFT, + SI=>SFFT, + O=>O, + VO=>VO, + SO=>SO); +-- O<=OFFT; +-- VO<=VOFFT; +-- SO<=SFFT; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.COMPLEX_FIXED_PKG.all; + +entity WRAPPER_VECTOR_FFT is + generic(SSR:INTEGER:=8; + N:INTEGER:=512; + L2N:INTEGER:=9; -- L2N must be set equal to log2(N)!!! + I_high:INTEGER:=0; + I_low:INTEGER:=-15; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-15; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + CE:in STD_LOGIC:='1'; -- not used, for SysGen only + I:in STD_LOGIC_VECTOR(2*SSR*(I_high-I_low+1)-1 downto 0); + VI:in STD_LOGIC; + SI:in STD_LOGIC_VECTOR(L2N-1 downto 0):=(L2N-1 downto 0=>'0'); -- can be left unconnected if internal scaling is not used, must be a (LOG2(N)-1 downto 0) port + O:out STD_LOGIC_VECTOR(2*SSR*(O_high-O_low+1)-1 downto 0); + VO:out STD_LOGIC; + SO:out STD_LOGIC_VECTOR(L2N-1 downto 0)); -- can be left unconnected if internal overflow is not possible, must be a (LOG2(N)-1 downto 0) port +end WRAPPER_VECTOR_FFT; + +architecture WRAPPER of WRAPPER_VECTOR_FFT is +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if KSSR, + N=>N, + I_high=>I_high, + I_low=>I_low, + W_high=>W_high, + W_low=>W_low, + O_high=>O_high, + O_low=>O_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB, + DSP48E=>DSP48E) -- 1 for DSP48E1, 2 for DSP48E2 + port map(CLK=>CLK, + I=>II, + VI=>VII, + SI=>SII, + O=>OO, + VO=>VOO, + SO=>SOO); + O<=STD_LOGIC_VECTOR(OO); + VO<='1' when VOO else '0'; + SO<=STD_LOGIC_VECTOR(SOO); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity WRAPPER_VECTOR_FFT_c5415935ecc00ff9eff39575a72e6e61 is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 6; + N : integer := 64; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(5 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(5 downto 0); + CLK : in std_logic; + CE : in std_logic + ); +end WRAPPER_VECTOR_FFT_c5415935ecc00ff9eff39575a72e6e61; +architecture structural of WRAPPER_VECTOR_FFT_c5415935ecc00ff9eff39575a72e6e61 is + signal I_net : std_logic_vector(255 downto 0); + signal VI_net : std_logic; + signal SI_net : std_logic_vector(5 downto 0); + signal O_net : std_logic_vector(431 downto 0); + signal VO_net : std_logic; + signal SO_net : std_logic_vector(5 downto 0); + signal CLK_net : std_logic; + signal CE_net : std_logic; + component WRAPPER_VECTOR_FFT is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 6; + N : integer := 64; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(5 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(5 downto 0); + CLK : in std_logic; + CE : in std_logic + ); + end component; +begin + I_net <= I; + VI_net <= VI; + SI_net <= SI; + O <= O_net; + VO <= VO_net; + SO <= SO_net; + CLK_net <= CLK; + CE_net <= CE; + WRAPPER_VECTOR_FFT_inst : WRAPPER_VECTOR_FFT + generic map( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 6, + N => 64, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map( + I => I_net, + VI => VI_net, + SI => SI_net, + O => O_net, + VO => VO_net, + SO => SO_net, + CLK => CLK_net, + CE => CE_net + ); +end structural; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlslice.vhd +-- +-- Description : VHDL description of a block that sets the output to a +-- specified range of the input bits. The output is always +-- set to an unsigned type with it's binary point at zero. +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x64_xlslice is + generic ( + new_msb : integer := 9; -- position of new msb + new_lsb : integer := 1; -- position of new lsb + x_width : integer := 16; -- Width of x input + y_width : integer := 8); -- Width of y output + port ( + x : in std_logic_vector (x_width-1 downto 0); + y : out std_logic_vector (y_width-1 downto 0)); +end ssr_8x64_xlslice; + +architecture behavior of ssr_8x64_xlslice is +begin + y <= x(new_msb downto new_lsb); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_384683215a is + port ( + in0 : in std_logic_vector((16 - 1) downto 0); + in1 : in std_logic_vector((16 - 1) downto 0); + y : out std_logic_vector((32 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_384683215a; +architecture behavior of sysgen_concat_384683215a +is + signal in0_1_23: unsigned((16 - 1) downto 0); + signal in1_1_27: unsigned((16 - 1) downto 0); + signal y_2_1_concat: unsigned((32 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_53c8e6f5a2 is + port ( + input_port : in std_logic_vector((16 - 1) downto 0); + output_port : out std_logic_vector((16 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_53c8e6f5a2; +architecture behavior of sysgen_reinterpret_53c8e6f5a2 +is + signal input_port_1_40: signed((16 - 1) downto 0); + signal output_port_5_5_force: unsigned((16 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_signed(input_port); + output_port_5_5_force <= signed_to_unsigned(input_port_1_40); + output_port <= unsigned_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_d7a483898b is + port ( + input_port : in std_logic_vector((27 - 1) downto 0); + output_port : out std_logic_vector((27 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_d7a483898b; +architecture behavior of sysgen_reinterpret_d7a483898b +is + signal input_port_1_40: unsigned((27 - 1) downto 0); + signal output_port_5_5_force: signed((27 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_unsigned(input_port); + output_port_5_5_force <= unsigned_to_signed(input_port_1_40); + output_port <= signed_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_c0fcf025b9 is + port ( + in0 : in std_logic_vector((32 - 1) downto 0); + in1 : in std_logic_vector((32 - 1) downto 0); + in2 : in std_logic_vector((32 - 1) downto 0); + in3 : in std_logic_vector((32 - 1) downto 0); + in4 : in std_logic_vector((32 - 1) downto 0); + in5 : in std_logic_vector((32 - 1) downto 0); + in6 : in std_logic_vector((32 - 1) downto 0); + in7 : in std_logic_vector((32 - 1) downto 0); + y : out std_logic_vector((256 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_c0fcf025b9; +architecture behavior of sysgen_concat_c0fcf025b9 +is + signal in0_1_23: unsigned((32 - 1) downto 0); + signal in1_1_27: unsigned((32 - 1) downto 0); + signal in2_1_31: unsigned((32 - 1) downto 0); + signal in3_1_35: unsigned((32 - 1) downto 0); + signal in4_1_39: unsigned((32 - 1) downto 0); + signal in5_1_43: unsigned((32 - 1) downto 0); + signal in6_1_47: unsigned((32 - 1) downto 0); + signal in7_1_51: unsigned((32 - 1) downto 0); + signal y_2_1_concat: unsigned((256 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + in2_1_31 <= std_logic_vector_to_unsigned(in2); + in3_1_35 <= std_logic_vector_to_unsigned(in3); + in4_1_39 <= std_logic_vector_to_unsigned(in4); + in5_1_43 <= std_logic_vector_to_unsigned(in5); + in6_1_47 <= std_logic_vector_to_unsigned(in6); + in7_1_51 <= std_logic_vector_to_unsigned(in7); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39) & unsigned_to_std_logic_vector(in5_1_43) & unsigned_to_std_logic_vector(in6_1_47) & unsigned_to_std_logic_vector(in7_1_51)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/synth_reg.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/synth_reg.vhd new file mode 100644 index 0000000..770ff70 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/synth_reg.vhd @@ -0,0 +1,95 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register without +-- an init value and a clear. SRLC32E components are used. The +-- initial value is always 0 +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRLC32s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg; + +architecture structural of synth_reg is + component srlc33e + generic (width : integer:=16; + latency : integer :=8); + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); + end component; + + function calc_num_srlc33es (latency : integer) + return integer + is + variable remaining_latency : integer; + variable result : integer; + begin + result := latency / 33; + + remaining_latency := latency - (result * 33); + -- If latency is not an even multiple of 33 then add one more + -- srlc33e to the pipeline + if (remaining_latency /= 0) then + result := result + 1; + end if; + + return result; + end; + + + constant complete_num_srlc33es : integer := latency / 33; + constant num_srlc33es : integer := calc_num_srlc33es(latency); + constant remaining_latency : integer := latency - (complete_num_srlc33es * 33); + -- Array for std_logic_vectors + type register_array is array (num_srlc33es downto 0) of + std_logic_vector(width-1 downto 0); + signal z : register_array; + +begin + + z(0) <= i; + complete_ones : if complete_num_srlc33es > 0 generate + srlc33e_array: for i in 0 to complete_num_srlc33es-1 generate + delay_comp : srlc33e + generic map (width => width, + latency => 33) + port map (clk => clk, + ce => ce, + d => z(i), + q => z(i+1)); + + end generate; + end generate; + + partial_one : if remaining_latency > 0 generate + last_srlc33e : srlc33e + generic map (width => width, + latency => remaining_latency) + port map (clk => clk, + ce => ce, + d => z(num_srlc33es-1), + q => z(num_srlc33es)); + end generate; + o <= z(num_srlc33es); +end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/synth_reg_reg.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/synth_reg_reg.vhd new file mode 100644 index 0000000..5d837de --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/synth_reg_reg.vhd @@ -0,0 +1,64 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_reg.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRL16s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg_reg; + +architecture behav of synth_reg_reg is + type reg_array_type is array (latency downto 0) of std_logic_vector(width -1 downto 0); + signal reg_bank : reg_array_type := (others => (others => '0')); + signal reg_bank_in : reg_array_type := (others => (others => '0')); + attribute syn_allow_retiming : boolean; + attribute syn_srlstyle : string; + attribute syn_allow_retiming of reg_bank : signal is true; + attribute syn_allow_retiming of reg_bank_in : signal is true; + attribute syn_srlstyle of reg_bank : signal is "registers"; + attribute syn_srlstyle of reg_bank_in : signal is "registers"; +begin -- behav + + latency_eq_0: if latency = 0 generate + o <= i; + end generate latency_eq_0; + + latency_gt_0: if latency >= 1 generate + o <= reg_bank(latency); + reg_bank(0) <= i; + + sync_loop: for sync_idx in latency downto 1 generate + sync_proc: process (clk) + begin -- process sync_proc + if clk'event and clk = '1' then -- rising clock edge + if clr = '1' then + reg_bank(sync_idx) <= (others => '0'); + elsif ce = '1' then + reg_bank(sync_idx) <= reg_bank(sync_idx-1); + end if; + end if; + end process sync_proc; + end generate sync_loop; + end generate latency_gt_0; + end behav; + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/synth_reg_w_init.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/synth_reg_w_init.vhd new file mode 100644 index 0000000..34bfa2e --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/synth_reg_w_init.vhd @@ -0,0 +1,98 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_w_init.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register with +-- an initial value. The register has clr and ce pins and +-- is implemented using flip-flops (i.e., not SRL16s). +-- +-- Mod. History : Delayed input .1 ns so that there isn't a setup +-- violation in the fdse or fdre Unisim models. +-- : Changed VHDL so that initial register is passed as a bit +-- vector generic value, instead of the const_pkg. +-- +-- Mod. Dates : 8/10/2001 +-- 3/19/2003 +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000"; + latency: integer := 1 + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end synth_reg_w_init; + +architecture structural of synth_reg_w_init is + component single_reg_w_init + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; -- end single_reg_w_init + + -- 1D array used to connect all the register together + signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); + signal dly_clr: std_logic; +begin + latency_eq_0: if (latency = 0) generate + o <= i; + end generate; -- end latency_eq_0 + + latency_gt_0: if (latency >= 1) generate + -- Delayed input 200 ps so that there isn't a setup violation in the + -- fdse or fdre Unisim models + dly_i((latency + 1) * width - 1 downto latency * width) <= i + after 200 ps; + dly_clr <= clr after 200 ps; + + fd_array: for index in latency downto 1 generate + reg_comp: single_reg_w_init + generic map ( + width => width, + init_index => init_index, + init_value => init_value + ) + port map ( + clk => clk, + i => dly_i((index + 1) * width - 1 downto index * width), + o => dly_i(index * width - 1 downto (index - 1) * width), + ce => ce, + clr => dly_clr + ); + end generate; -- end fd_array + + o <= dly_i(width - 1 downto 0); + end generate; -- end latency_gt_0 +end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/xlclockdriver_rd.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/xlclockdriver_rd.vhd new file mode 100644 index 0000000..92017d4 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssr_fft_8x64/xlclockdriver_rd.vhd @@ -0,0 +1,338 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlclockdriver.vhd +-- +-- Date : 10/1/99 +-- +-- Description : VHDL description of a clock enable generator block. +-- This code is synthesizable. +-- +-- Assumptions : period >= 1 +-- +-- Mod. History : Removed one shot & OR gate +-- If period is power of 2 a 1-bit smaller counter +-- is used and no sync clear +-- : Logic needed for use_bufg generic added +-- : Initial ce output is now 0 instead of 1 +-- Enable pulse now occurs at the end of the sample +-- period, instead of at the start +-- : Added pipeline registers +-- : added OR gate for sysclr to work properly +-- +-- Mod. Dates : 7/26/2001 +-- : 8/05/2001 +-- : 1/02/2002 +-- : 11/30/2004 +-- : 4/11/2005 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +entity xlclockdriver is + generic ( + period: integer := 2; + log_2_period: integer := 0; + pipeline_regs: integer := 5; + use_bufg: integer := 0 + ); + port ( + sysclk: in std_logic; + sysclr: in std_logic; + sysce: in std_logic; + clk: out std_logic; + clr: out std_logic; + ce: out std_logic; + ce_logic: out std_logic + ); +end xlclockdriver; + +architecture behavior of xlclockdriver is + component bufg + port ( + i: in std_logic; + o: out std_logic + ); + end component; + + component synth_reg_w_init + generic ( + width: integer; + init_index: integer; + init_value: bit_vector; + latency: integer + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; + + -- Returns the size of an unsigned integer + -- if power_of_2 is true return value is one less + function size_of_uint(inp: integer; power_of_2: boolean) + return integer + is + constant inp_vec: std_logic_vector(31 downto 0) := + integer_to_std_logic_vector(inp,32, xlUnsigned); + variable result: integer; + begin + result := 32; + for i in 0 to 31 loop + if inp_vec(i) = '1' then + result := i; + end if; + end loop; + if power_of_2 then + return result; + else + return result+1; + end if; + end; + + -- Returns boolean which says if 'inp' is a power of two + function is_power_of_2(inp: std_logic_vector) + return boolean + is + constant width: integer := inp'length; + variable vec: std_logic_vector(width - 1 downto 0); + variable single_bit_set: boolean; + variable more_than_one_bit_set: boolean; + variable result: boolean; + begin + vec := inp; + single_bit_set := false; + more_than_one_bit_set := false; + + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if width > 0 then + for i in 0 to width - 1 loop + if vec(i) = '1' then + if single_bit_set then + more_than_one_bit_set := true; + end if; + single_bit_set := true; + end if; + end loop; + end if; + if (single_bit_set and not(more_than_one_bit_set)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Returns initial value for pipeline registers + function ce_reg_init_val(index, period : integer) + return integer + is + variable result: integer; + begin + result := 0; + if ((index mod period) = 0) then + result := 1; + end if; + return result; + end; + + -- Returns the remainder(num_pipeline_regs/period) + 1 + function remaining_pipe_regs(num_pipeline_regs, period : integer) + return integer + is + variable factor, result: integer; + begin + factor := (num_pipeline_regs / period); + result := num_pipeline_regs - (period * factor) + 1; + return result; + end; + + -- Calculate the min + function sg_min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + constant max_pipeline_regs : integer := 8; + constant pipe_regs : integer := 5; + + -- Check if requested pipeline regs are greater than the max amount + constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); + constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); + + constant period_floor: integer := max(2, period); + constant power_of_2_counter: boolean := + is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); + constant cnt_width: integer := + size_of_uint(period_floor, power_of_2_counter); + constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); + + signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); + signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); + signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0); + signal internal_ce: std_logic_vector(0 downto 0); + signal internal_ce_logic: std_logic_vector(0 downto 0); + signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); +begin + -- Pass through the system clock and clear + clk <= sysclk; + clr <= sysclr; + + -- Clock Number Counter + cntr_gen: process(sysclk) + begin + if sysclk'event and sysclk = '1' then + if (sysce = '1') then + if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then + clk_num <= (others => '0'); + else + clk_num <= clk_num + 1; + end if; + end if; + end if; + end process; + + -- Clear logic for counter + clr_gen: process(clk_num, sysclr) + begin + if power_of_2_counter then + cnt_clr(0) <= sysclr; + else + -- Counter does not reset when clk_num = a power of 2 + if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 + or sysclr = '1') then + cnt_clr(0) <= '1'; + else + cnt_clr(0) <= '0'; + end if; + end if; + end process; + + clr_reg: synth_reg_w_init + generic map ( + width => 1, + init_index => 0, + init_value => b"0000", + latency => 1 + ) + port map ( + i => cnt_clr, + ce => sysce, + clr => sysclr, + clk => sysclk, + o => cnt_clr_dly + ); + + -- Clock enable generation + pipelined_ce : if period > 1 generate + ce_gen: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec(num_pipeline_regs) <= '1'; + else + ce_vec(num_pipeline_regs) <= '0'; + end if; + end process; + ce_pipeline: for index in num_pipeline_regs downto 1 generate + ce_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec(index-1 downto index-1) + ); + end generate; -- i + internal_ce <= ce_vec(0 downto 0); + end generate; + + -- Clock enable generation + pipelined_ce_logic: if period > 1 generate + ce_gen_logic: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec_logic(num_pipeline_regs) <= '1'; + else + ce_vec_logic(num_pipeline_regs) <= '0'; + end if; + end process; + ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate + ce_logic_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec_logic(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec_logic(index-1 downto index-1) + ); + end generate; -- i + internal_ce_logic <= ce_vec_logic(0 downto 0); + end generate; + + + use_bufg_true: if period > 1 and use_bufg = 1 generate + -- Clock enable with bufg + ce_bufg_inst: bufg + port map ( + i => internal_ce(0), + o => ce + ); + ce_bufg_inst_logic: bufg + port map ( + i => internal_ce_logic(0), + o => ce_logic + ); + end generate; + + use_bufg_false: if period > 1 and (use_bufg = 0) generate + -- Clock enable without bufg + ce <= internal_ce(0) and sysce; + ce_logic <= internal_ce_logic(0) and sysce; + end generate; + + generate_system_clk: if period = 1 generate + ce <= sysce; + ce_logic <= sysce; + end generate; +end architecture behavior; + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssrfft_8x64_sync.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssrfft_8x64_sync.vhd new file mode 100644 index 0000000..606006c --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/ssrfft_8x64_sync.vhd @@ -0,0 +1,294 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity ssrfft_8x64_sync is + Generic + ( + NFFT : Integer := 16; + SSR : Integer := 4; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (2*SSR*B-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end entity; + +architecture rtl of ssrfft_8x64_sync is + +-- Framing. +component framing is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4; + + -- Bits. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- Synced outputs. + tdata : out std_logic_vector (2*SSR*B-1 downto 0); + tvalid : out std_logic + ); +end component; + +-- TLAST Generator. +component tlast_gen is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4 + ); + Port + ( + -- Input reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Input enable. + en : in std_logic; + + -- TLAST input/output. + o_tlast : out std_logic + ); +end component; + +-- SSR FFT 8x64. +component ssr_8x64 is + port ( + -- Clock signal. + clk : in std_logic; + + -- Input data. + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_scale : in std_logic_vector( 6-1 downto 0 ); + + -- Output data. + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_scale : out std_logic_vector( 6-1 downto 0 ) + ); +end component; + +-- Vectors with individual I,Q samples. +type data_v is array (SSR-1 downto 0) of std_logic_vector (B-1 downto 0); +signal din_iv : data_v; +signal din_qv : data_v; +signal dout_iv : data_v; +signal dout_qv : data_v; + +-- Vector with individual I,Q samples (fft out full precision). +type data_vf is array (SSR-1 downto 0) of std_logic_vector (27-1 downto 0); +signal dout_ivf : data_vf; +signal dout_qvf : data_vf; + +-- I,Q parts of input. +signal din_i : std_logic_vector (SSR*B-1 downto 0); +signal din_q : std_logic_vector (SSR*B-1 downto 0); + +-- Framing block signals. +signal framing_tdata : std_logic_vector (2*SSR*B-1 downto 0); +signal framing_tvalid : std_logic; + +-- FFT scale. +signal o_scale : std_logic_vector (5 downto 0); + +-- FFT output valid/last. +signal o_axis_tvalid : std_logic; +signal o_axis_tlast : std_logic; + +-- FFT data output. +signal o_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); + +-- Registers. +signal scale_reg_i : std_logic_vector (5 downto 0); +signal qout_reg_i : unsigned (3 downto 0); + +begin + +-- Registers. +scale_reg_i <= SCALE_REG (5 downto 0); + +-- Full-precision output: 27 bits. Required output: 16 bits. +-- Quantization selection from 0 to 11. +qout_reg_i <= (others => '0') when ( unsigned(QOUT_REG) > to_unsigned(11,QOUT_REG'length) ) else + unsigned(QOUT_REG(3 downto 0)); + +-- Input/output data to vector. +GEN: for I in 0 to SSR-1 generate + -- Input data to vector. + din_iv(I) <= framing_tdata(I*2*B+B-1 downto I*2*B ); + din_qv(I) <= framing_tdata(I*2*B+2*B-1 downto I*2*B+B ); + + -- Quantization selection. + dout_iv(I) <= dout_ivf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + dout_qv(I) <= dout_qvf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + + -- Output data to vector. + o_axis_tdata(I*2*B+B-1 downto I*2*B ) <= dout_iv(I); + o_axis_tdata(I*2*B+2*B-1 downto I*2*B+B ) <= dout_qv(I); +end generate GEN; + +-- Framing. +framing_i : framing + Generic map + ( + -- SSR and FFT Length. + NFFT => NFFT , + SSR => SSR , + + -- Bits. + B => B + ) + Port map + ( + -- Reset and clock. + aresetn => aresetn , + aclk => aclk , + + -- AXIS Slave. + s_axis_tdata => s_axis_tdata , + s_axis_tlast => s_axis_tlast , + s_axis_tvalid => s_axis_tvalid , + + -- Synced outputs. + tdata => framing_tdata , + tvalid => framing_tvalid + ); + +-- TLAST Generator. +tlast_gen_i : tlast_gen + Generic map + ( + -- SSR and FFT Length. + NFFT => NFFT , + SSR => SSR + ) + Port map + ( + -- Input reset and clock. + rstn => aresetn , + clk => aclk , + + -- Input enable. + en => o_axis_tvalid , + + -- TLAST input/output. + o_tlast => o_axis_tlast + ); + +-- SSR FFT 8x1024. +ssr_8x64_i : ssr_8x64 + port map ( + -- Clock signal. + clk => aclk , + + -- Input data. + i_re_0 => din_iv(0) , + i_re_1 => din_iv(1) , + i_re_2 => din_iv(2) , + i_re_3 => din_iv(3) , + i_re_4 => din_iv(4) , + i_re_5 => din_iv(5) , + i_re_6 => din_iv(6) , + i_re_7 => din_iv(7) , + i_im_0 => din_qv(0) , + i_im_1 => din_qv(1) , + i_im_2 => din_qv(2) , + i_im_3 => din_qv(3) , + i_im_4 => din_qv(4) , + i_im_5 => din_qv(5) , + i_im_6 => din_qv(6) , + i_im_7 => din_qv(7) , + i_valid(0) => framing_tvalid , + i_scale => scale_reg_i , + + -- Output data. + o_re_0 => dout_ivf(0) , + o_re_1 => dout_ivf(1) , + o_re_2 => dout_ivf(2) , + o_re_3 => dout_ivf(3) , + o_re_4 => dout_ivf(4) , + o_re_5 => dout_ivf(5) , + o_re_6 => dout_ivf(6) , + o_re_7 => dout_ivf(7) , + o_im_0 => dout_qvf(0) , + o_im_1 => dout_qvf(1) , + o_im_2 => dout_qvf(2) , + o_im_3 => dout_qvf(3) , + o_im_4 => dout_qvf(4) , + o_im_5 => dout_qvf(5) , + o_im_6 => dout_qvf(6) , + o_im_7 => dout_qvf(7) , + o_valid(0) => o_axis_tvalid , + o_scale => o_scale + ); + +-- Assign outputs. +m_axis_tdata <= o_axis_tdata; +m_axis_tlast <= o_axis_tlast; +m_axis_tvalid <= o_axis_tvalid; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/tb.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/tb.vhd new file mode 100644 index 0000000..1303dec --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/tb.vhd @@ -0,0 +1,301 @@ +-- %%%%%%%%%%%%%%%%%%% Test Description %%%%%%%%%%%%%%%%%%%%% +-- +-- This test is for understanding if moving tvalid makes the +-- block to generate incorrect tlast at the output. +-- +-- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_TEXTIO.ALL; +use STD.TEXTIO.ALL; + +entity tb is +end tb; + +architecture rtl of tb is + +-- DUT. +component ssrfft_8x64_sync is + Generic + ( + NFFT : Integer := 16; + SSR : Integer := 4; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (2*SSR*B-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end component; + +constant NFFT : Integer := 64; +constant SSR : Integer := 8; +constant B : Integer := 16; + +signal aresetn : std_logic; +signal aclk : std_logic; +signal s_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0) := (others => '0'); +signal s_axis_tlast : std_logic := '0'; +signal s_axis_tvalid : std_logic := '0'; + +signal m_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); +signal m_axis_tlast : std_logic; +signal m_axis_tvalid : std_logic; + +signal SCALE_REG : std_logic_vector (31 downto 0) := (others => '0'); +signal QOUT_REG : std_logic_vector (31 downto 0) := std_logic_vector(to_unsigned(0,32)); + +-- TB control. +signal rd_start : std_logic := '0'; + +signal i_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); + +signal o_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); + +begin + +-- DUT. +DUT : ssrfft_8x64_sync + Generic map + ( + NFFT => NFFT , + SSR => SSR , + B => B + ) + Port map + ( + -- Reset and clock. + aresetn => aresetn , + aclk => aclk , + + -- AXIS Slave. + s_axis_tdata => s_axis_tdata , + s_axis_tlast => s_axis_tlast , + s_axis_tvalid => s_axis_tvalid , + + -- AXIS Master. + m_axis_tdata => m_axis_tdata , + m_axis_tlast => m_axis_tlast , + m_axis_tvalid => m_axis_tvalid , + + -- Registers. + SCALE_REG => SCALE_REG , + QOUT_REG => QOUT_REG + ); + +-- Input data. +s_axis_tdata <= i_im_7 & i_re_7 & i_im_6 & i_re_6 & i_im_5 & i_re_5 & i_im_4 & i_re_4 & i_im_3 & i_re_3 & i_im_2 & i_re_2 & i_im_1 & i_re_1 & i_im_0 & i_re_0; + +-- Output data. +o_re_0 <= m_axis_tdata (1*B-1 downto 0*B); +o_im_0 <= m_axis_tdata (2*B-1 downto 1*B); +o_re_1 <= m_axis_tdata (3*B-1 downto 2*B); +o_im_1 <= m_axis_tdata (4*B-1 downto 3*B); +o_re_2 <= m_axis_tdata (5*B-1 downto 4*B); +o_im_2 <= m_axis_tdata (6*B-1 downto 5*B); +o_re_3 <= m_axis_tdata (7*B-1 downto 6*B); +o_im_3 <= m_axis_tdata (8*B-1 downto 7*B); +o_re_4 <= m_axis_tdata (9*B-1 downto 8*B); +o_im_4 <= m_axis_tdata (10*B-1 downto 9*B); +o_re_5 <= m_axis_tdata (11*B-1 downto 10*B); +o_im_5 <= m_axis_tdata (12*B-1 downto 11*B); +o_re_6 <= m_axis_tdata (13*B-1 downto 12*B); +o_im_6 <= m_axis_tdata (14*B-1 downto 13*B); +o_re_7 <= m_axis_tdata (15*B-1 downto 14*B); +o_im_7 <= m_axis_tdata (16*B-1 downto 15*B); + +-- Main TB. +process +begin + aresetn <= '0'; + wait for 250 ns; + aresetn <= '1'; + + wait for 3 us; + + rd_start <= '1'; + --wait for 110 ns; + --rd_start <= '0'; + --wait for 220 ns; + --rd_start <= '1'; + --wait for 490 ns; + --rd_start <= '0'; + --wait for 100 ns; + --rd_start <= '1'; + + wait for 20 us; + +end process; + +-- Data process. +process + variable I : Integer := 0; + + begin + + i_re_0 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_1 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_2 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_3 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_4 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_5 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_6 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_7 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_0 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_1 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_2 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_3 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_4 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_5 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_6 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_7 <= std_logic_vector(to_signed(0,i_re_0'length)); + + for K in 0 to 200 loop + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + i_re_1 <= std_logic_vector(to_signed(10000,i_re_0'length)); + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + i_re_1 <= std_logic_vector(to_signed(0,i_re_0'length)); + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '1'; + s_axis_tvalid <= '1'; + --for J in 0 to 2 loop + -- while rd_start = '0' loop + -- wait until rising_edge(aclk); + -- s_axis_tvalid <= '0'; + -- end loop; + -- wait until rising_edge(aclk); + -- s_axis_tlast <= '0'; + -- s_axis_tvalid <= '1'; + -- i_re_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + + -- I := I + 1; + --end loop; + + --while rd_start = '0' loop + -- wait until rising_edge(aclk); + -- s_axis_tvalid <= '0'; + --end loop; + --wait until rising_edge(aclk); + --s_axis_tlast <= '1'; + --s_axis_tvalid <= '1'; + --i_re_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + + --I := I + 1; + end loop; + +end process; + +-- Clock. +process +begin + aclk <= '0'; + wait for 5 ns; + aclk <= '1'; + wait for 5 ns; +end process; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/tlast_gen.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/tlast_gen.vhd new file mode 100644 index 0000000..c07cb2e --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fft/tlast_gen.vhd @@ -0,0 +1,61 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity tlast_gen is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4 + ); + Port + ( + -- Input reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Input enable. + en : in std_logic; + + -- TLAST input/output. + o_tlast : out std_logic + ); +end entity; + +architecture rtl of tlast_gen is + +-- Number of transactions. +constant NTRAN : Integer := NFFT/SSR; +constant NTRAN_LOG2 : Integer := Integer(ceil(log2(real(NTRAN)))); + +-- Counter for transactions. +signal cnt : unsigned (NTRAN_LOG2-1 downto 0); + +begin + +-- Registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + cnt <= (others => '0'); + else + if ( en = '1' ) then + if ( cnt < to_unsigned(NTRAN-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + end if; + end if; + end if; + end if; +end process; + +-- Assign outputs. +o_tlast <= '1' when cnt = to_unsigned(NTRAN-1,cnt'length) else + '0'; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/Makefile b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/Makefile new file mode 100644 index 0000000..df6451c --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/Makefile @@ -0,0 +1,21 @@ +all: ipgen copy sedxci clean_proj + +ipgen: fir.tcl + vivado -mode batch -source tcl/ipgen.tcl + +copy: + cp -r `find ./ipgen/ipgen.srcs -type d -name "fir*"` . + cp -r `find ./ipgen/ipgen.gen -name "fir_0.veo"` . + +sedxci: + sed -i -r 's#(../)+(coef/fir.*.coe)#../\2#' `find . -name "fir*.xci"` + +fir.tcl: tcl/fir.tcl.template + ./gen.pl tcl/fir.tcl.template + +clean: clean_proj + rm -rf `find . -type d -name "fir*"` + rm -rf fir*.veo fir.tcl add.tcl + +clean_proj: + rm -rf ipgen vivado* diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/add.tcl b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/add.tcl new file mode 100644 index 0000000..9523c5d --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/add.tcl @@ -0,0 +1,8 @@ +add_files ./fir/fir_0/fir_0.xci +add_files ./fir/fir_1/fir_1.xci +add_files ./fir/fir_2/fir_2.xci +add_files ./fir/fir_3/fir_3.xci +add_files ./fir/fir_4/fir_4.xci +add_files ./fir/fir_5/fir_5.xci +add_files ./fir/fir_6/fir_6.xci +add_files ./fir/fir_7/fir_7.xci diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_0.coe b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_0.coe new file mode 100644 index 0000000..90cedee --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_0.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -409,-1113,14782,1965,1397,-401,0,-481,-393,12156,4247,1154,-459,0,-509,245,9446,6773,767,-499,0,-499,767,6773,9446,245,-509,0,-459,1154,4247,12156,-393,-481,0,-401,1397,1965,14782,-1113,-409,0,-331,1501,4,17203,-1868,-288,12,-259,1480,-1584,19303,-2600,-116,10 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_1.coe b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_1.coe new file mode 100644 index 0000000..c695165 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_1.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -190,1356,-2768,20978,-3243,101,2,-129,1154,-3547,22144,-3726,353,-14,-79,903,-3937,22742,-3979,627,-41,-41,627,-3979,22742,-3937,903,-79,-14,353,-3726,22144,-3547,1154,-129,2,101,-3243,20978,-2768,1356,-190,10,-116,-2600,19303,-1584,1480,-259,12,-288,-1868,17203,4,1501,-331 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_2.coe b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_2.coe new file mode 100644 index 0000000..8a55eee --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_2.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -432,-928,14140,2508,1349,-417,0,-492,-225,11481,4859,1070,-471,0,-510,387,8770,7431,649,-504,0,-491,877,6123,10125,95,-506,0,-446,1228,3650,12825,-567,-468,0,-384,1435,1442,15411,-1301,-383,90,-313,1507,-430,17763,-2056,-249,12,-241,1458,-1918,19765,-2772,-66,9 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_3.coe b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_3.coe new file mode 100644 index 0000000..a5989f5 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_3.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -174,1312,-3001,21320,-3381,161,-1,-116,1095,-3680,22349,-3813,421,-20,-68,835,-3979,22799,-3999,697,-49,-33,558,-3941,22648,-3874,969,-91,-9,288,-3624,21904,-3390,1211,-143,5,43,-3094,20604,-2511,1396,-206,11,-164,-2423,18814,-1224,1496,-277,12,-323,-1679,16624,461,1487,-349 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_4.coe b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_4.coe new file mode 100644 index 0000000..5c3d7af --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_4.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -451,-746,13487,3070,1293,-432,0,-500,-62,10804,5485,978,-482,0,-508,522,8098,8098,522,-508,0,-482,978,5485,10804,-62,-500,0,-432,1293,3070,13487,-746,-451,0,-367,1466,940,16026,-1490,-355,12,-295,1505,-839,18300,-2241,-208,12,-224,1430,-2227,20199,-2937,-13,7 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_5.coe b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_5.coe new file mode 100644 index 0000000..f5b7af0 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_5.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -158,1263,-3208,21629,-3509,223,-5,-103,1033,-3789,22517,-3885,489,-26,-59,766,-3999,22818,-3999,766,-59,-26,489,-3885,22517,-3789,1033,-103,-5,223,-3509,21629,-3208,1263,-158,7,-13,-2937,20199,-2227,1430,-224,12,-208,-2241,18300,-839,1505,-295,12,-355,-1490,16026,940,1466,-367 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_6.coe b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_6.coe new file mode 100644 index 0000000..5e0828d --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_6.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -468,-567,12825,3650,1228,-446,0,-506,95,10125,6123,877,-491,0,-504,649,7431,8770,387,-510,0,-471,1070,4859,11481,-225,-492,0,-417,1349,2508,14140,-928,-432,0,-349,1487,461,16624,-1679,-323,12,-277,1496,-1224,18814,-2423,-164,11,-206,1396,-2511,20604,-3094,43,5 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_7.coe b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_7.coe new file mode 100644 index 0000000..e67b9d3 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_7.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -143,1211,-3390,21904,-3624,288,-9,-91,969,-3874,22648,-3941,558,-33,-49,697,-3999,22799,-3979,835,-68,-20,421,-3813,22349,-3680,1095,-116,-1,161,-3381,21320,-3001,1312,-174,9,-66,-2772,19765,-1918,1458,-241,12,-249,-2056,17763,-430,1507,-313,90,-383,-1301,15411,1442,1435,-384 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir.tcl b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir.tcl new file mode 100644 index 0000000..df91aaf --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir.tcl @@ -0,0 +1,256 @@ +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_0 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_0.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_0] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_1 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_1.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_1] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_2 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_2.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_2] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_3 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_3.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_3] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_4 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_4.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_4] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_5 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_5.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_5] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_6 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_6.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_6] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_7 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_7.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_7] diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_0.veo b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_0.veo new file mode 100644 index 0000000..b9961ec --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_0.veo @@ -0,0 +1,80 @@ +// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fir_compiler:7.2 +// IP Revision: 18 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fir_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready + .s_axis_data_tlast(s_axis_data_tlast), // input wire s_axis_data_tlast + .s_axis_data_tdata(s_axis_data_tdata), // input wire [31 : 0] s_axis_data_tdata + .s_axis_config_tvalid(s_axis_config_tvalid), // input wire s_axis_config_tvalid + .s_axis_config_tready(s_axis_config_tready), // output wire s_axis_config_tready + .s_axis_config_tlast(s_axis_config_tlast), // input wire s_axis_config_tlast + .s_axis_config_tdata(s_axis_config_tdata), // input wire [7 : 0] s_axis_config_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tlast(m_axis_data_tlast), // output wire m_axis_data_tlast + .m_axis_data_tdata(m_axis_data_tdata), // output wire [31 : 0] m_axis_data_tdata + .event_s_data_tlast_missing(event_s_data_tlast_missing), // output wire event_s_data_tlast_missing + .event_s_data_tlast_unexpected(event_s_data_tlast_unexpected), // output wire event_s_data_tlast_unexpected + .event_s_config_tlast_missing(event_s_config_tlast_missing), // output wire event_s_config_tlast_missing + .event_s_config_tlast_unexpected(event_s_config_tlast_unexpected) // output wire event_s_config_tlast_unexpected +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fir_0.v when simulating +// the core, fir_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_0/fir_0.xci b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_0/fir_0.xci new file mode 100644 index 0000000..6e7f4b1 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_0/fir_0.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_0.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_0 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_0.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_0 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v3/top/top.tmp/axis_pfb_readout_v3_v1_0_project/axis_pfb_readout_v3_v1_0_project.gen/sources_1/ip/fir_0 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_1/fir_1.xci b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_1/fir_1.xci new file mode 100644 index 0000000..b475838 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_1/fir_1.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_1 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_1.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_1 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_1.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_1 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v3/top/top.tmp/axis_pfb_readout_v3_v1_0_project/axis_pfb_readout_v3_v1_0_project.gen/sources_1/ip/fir_1 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_2/fir_2.xci b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_2/fir_2.xci new file mode 100644 index 0000000..3bc1fc6 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_2/fir_2.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_2 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_2.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_2 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_2.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_2 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v3/top/top.tmp/axis_pfb_readout_v3_v1_0_project/axis_pfb_readout_v3_v1_0_project.gen/sources_1/ip/fir_2 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_3/fir_3.xci b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_3/fir_3.xci new file mode 100644 index 0000000..f8e26b3 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_3/fir_3.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_3 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_3.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_3 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_3.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_3 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v3/top/top.tmp/axis_pfb_readout_v3_v1_0_project/axis_pfb_readout_v3_v1_0_project.gen/sources_1/ip/fir_3 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_4/fir_4.xci b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_4/fir_4.xci new file mode 100644 index 0000000..ee9dedc --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_4/fir_4.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_4 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_4.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_4 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_4.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_4 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v3/top/top.tmp/axis_pfb_readout_v3_v1_0_project/axis_pfb_readout_v3_v1_0_project.gen/sources_1/ip/fir_4 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_5/fir_5.xci b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_5/fir_5.xci new file mode 100644 index 0000000..a1288f4 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_5/fir_5.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_5 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_5.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_5 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_5.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_5 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v3/top/top.tmp/axis_pfb_readout_v3_v1_0_project/axis_pfb_readout_v3_v1_0_project.gen/sources_1/ip/fir_5 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_6/fir_6.xci b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_6/fir_6.xci new file mode 100644 index 0000000..c39cf3d --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_6/fir_6.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_6 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_6.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_6 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_6.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_6 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v3/top/top.tmp/axis_pfb_readout_v3_v1_0_project/axis_pfb_readout_v3_v1_0_project.gen/sources_1/ip/fir_6 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_7/fir_7.xci b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_7/fir_7.xci new file mode 100644 index 0000000..3d7985f --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/fir_7/fir_7.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_7 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_7.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_7 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_7.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_7 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v3/top/top.tmp/axis_pfb_readout_v3_v1_0_project/axis_pfb_readout_v3_v1_0_project.gen/sources_1/ip/fir_7 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/gen.pl b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/gen.pl new file mode 100644 index 0000000..deba046 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/gen.pl @@ -0,0 +1,30 @@ +#!/usr/bin/perl +# This file generates the fir.tcl file to be run from vivado. +# Copy fir coefficient files. One IP per .coe file will be created. +# Copy generated .xci files to avoid generating FIR cores every time. + +open(my $file, "$ARGV[0]") or die "Could not open file '$ARGV[0]' $!"; +my @lines = <$file>; + +open(my $out_tcl, ">", "fir.tcl") or die "Could not open file fir.tcl $!"; +open(my $out_add, ">", "add.tcl") or die "Could not open file fir.tcl $!"; + +@out = `ls coef/*.coe`; +foreach (@out) +{ + chomp($_); + $fir = $_; + $fir =~ s/coef\///g; + $fir =~ s/.coe//g; + + print $out_add ("add_files ./fir/$fir/$fir.xci\n"); + + foreach my $line (@lines) + { + my $temp = $line; + chomp($temp); + $temp =~ s//$fir/g; + print $out_tcl ("$temp\n"); + } +} + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/tcl/fir.tcl.template b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/tcl/fir.tcl.template new file mode 100644 index 0000000..264e198 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/tcl/fir.tcl.template @@ -0,0 +1,32 @@ +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips ] diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/tcl/ipgen.tcl b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/tcl/ipgen.tcl new file mode 100644 index 0000000..e1a3705 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/fir/tcl/ipgen.tcl @@ -0,0 +1,13 @@ +# Create project. +create_project ipgen ./ipgen -part xczu49dr-ffvf1760-2-e + +# Set language options. +set_property simulator_language Mixed [current_project] +set_property target_language Verilog [current_project] + +# Create IPs. +source fir.tcl + +# Generate instantiation templates. +generate_target instantiation_template [get_ips *] + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/firs.sv b/firmware/ip/axis_pfb_readout_v3/src/pfb/firs.sv new file mode 100644 index 0000000..195dd2a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/firs.sv @@ -0,0 +1,301 @@ +module firs + ( + // Reset and clock. + aresetn , + aclk , + + // S_AXIS for input data. + s_axis_tvalid , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tlast , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of channels. +parameter N = 32; + +// Number of Lanes (Input). +parameter L = 4; + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +input s_axis_tvalid; +input [L*32-1:0] s_axis_tdata; + +output m_axis_tvalid; +output m_axis_tlast; +output [2*L*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// FIR Configuration interface. +wire config_tvalid; +wire config_tready; +wire config_tlast; +wire[7:0] config_tdata; + +// Framing. +wire fr_sync; +wire fr_out; + +// Input delay. +wire[L*32-1:0] data_d; +reg [31:0] data_r1_v[0:L-1]; +reg [31:0] data_r2_v[0:L-1]; + +// Valid input. +reg valid_r = 1'b0; + +// FIR outputs. +wire[31:0] dout_v [0:2*L-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i '0'); + + else + -- State register. + current_state <= next_state; + + -- Counter for config. + if ( cfg_cnt_en = '1' ) then + cfg_cnt <= cfg_cnt + 1; + end if; + + end if; + end if; +end process; + +-- tlast. +tlast_i <= '1' when cfg_cnt = to_unsigned(N-1,cfg_cnt'length) else + '0'; + +-- Next state logic. +process (current_state, cfg_en, tready, cfg_cnt) +begin + case current_state is + when INIT_ST => + if ( cfg_en = '1' and tready = '1' ) then + next_state <= CNT_ST; + else + next_state <= INIT_ST; + end if; + + when CNT_ST => + if ( cfg_cnt = to_unsigned(N-1,cfg_cnt'length) ) then + next_state <= END_ST; + else + next_state <= CNT_ST; + end if; + + when END_ST => + if ( cfg_en = '1' ) then + next_state <= END_ST; + else + next_state <= INIT_ST; + end if; + + end case; +end process; + +-- Output logic. +process (current_state) +begin +cfg_cnt_en <= '0'; + case current_state is + when INIT_ST => + + when CNT_ST=> + cfg_cnt_en <= '1'; + + when END_ST => + + end case; +end process; + +-- Assign outputs. +tvalid <= cfg_cnt_en; +tlast <= tlast_i; +tdata <= std_logic_vector (cfg_cnt); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_chsel.sv b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_chsel.sv new file mode 100644 index 0000000..ec89d1b --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_chsel.sv @@ -0,0 +1,108 @@ +// This block will extract 1 channel from the TDM-input. +// It uses ID_REG which is as follows: +// ID_REG [7:0] : packet. +// ID_REG [15:8] : index. +// +// Input packets are as follows: +// |-------| |-------| +// | | | | +// tlast --------------| |-------------| | +// +// |-----|-------|-------|-----|-------|-------| +// t | 0 | L | 2*L | 0 | L | 2*L | +// a | 1 | L+1 | 2*L+1 | 1 | L+1 | 2*L+1 | +// d | 2 | L+2 | 2*L+2 | 2 | L+2 | 2*L+2 | +// a | . | . | . | . | . | . | +// t | . | . | . | . | . | . | +// a | . | . | . | . | . | . | +// | L-1 | 2*L-1 | 3*L-1 | L-1 | 2*L-1 | 3*L-1 | +// |-----|-------|-------|-----|-------|-------| +// +// The internal counter counts packets relying on tlast and resets. +// Offset within a packet is given by index. +module pfb_chsel + #( + // Bits. + parameter B = 32, + + // Number of lanes. + parameter L = 8 + ) + ( + // Clock. + input wire aclk , + + // S_AXIS for input data. + input wire [L*B-1:0] s_axis_tdata , + input wire s_axis_tlast , + + // M_AXIS for output data. + output wire m_axis_tvalid , + output wire [B-1:0] m_axis_tdata , + + // Registers. + input wire [15:0] ID_REG + ); + +/********************/ +/* Internal signals */ +/********************/ +// Packet counter. +reg [7:0] cnt = 0; +wire wr_en; + +// Registers. +reg [7:0] packet_reg ; +reg [7:0] index_reg ; + +// Data registers. +reg [L*B-1:0] tdata_r ; +reg [B-1:0] data_mux_r ; + +// Muxed data. +wire [B-1:0] data_mux ; + +// tlast_pipeline (for tvalid). +reg tlast_r1 ; +reg tlast_r2 ; + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// Packet counter. +assign wr_en = (cnt == packet_reg)? 1'b1 : 1'b0; + +// Muxed data. +assign data_mux = tdata_r [index_reg*B +: B]; + +// Registers. +always @(posedge aclk) begin + // Packet counter. + if (s_axis_tlast == 1'b1) + cnt <= 0; + else + cnt <= cnt + 1; + + // Registers. + packet_reg <= ID_REG [7:0]; + index_reg <= ID_REG [15:8]; + + // Data registers. + if (wr_en == 1'b1) + tdata_r <= s_axis_tdata; + + if (tlast_r1 == 1'b1) + data_mux_r <= data_mux; + + // tlast_pipeline (for tvalid). + tlast_r1 <= s_axis_tlast; + tlast_r2 <= tlast_r1; +end + +// Assign outputs. +assign m_axis_tvalid = tlast_r2; +assign m_axis_tdata = data_mux_r; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_ctrl.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_ctrl.vhd new file mode 100644 index 0000000..24bd0a2 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_ctrl.vhd @@ -0,0 +1,113 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use WORK.pfb_ctrl_pkg.ALL; + +entity pfb_ctrl is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + aresetn : in std_logic; + aclk : in std_logic; + + -- M_AXIS for Configuration. + m_axis_config_tvalid : out std_logic; + m_axis_config_tready : in std_logic; + m_axis_config_tlast : out std_logic; + m_axis_config_tdata : out std_logic_vector (7 downto 0); + + -- Filter config. + cfg_en : in std_logic; + + -- Framing. + tready : in std_logic; + tvalid : in std_logic; + fr_sync : in std_logic; + fr_out : out std_logic + ); +end pfb_ctrl; + +architecture rtl of pfb_ctrl is + +-- PFB configuration. +component pfb_cfg is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Filter config. + cfg_en : in std_logic; + tready : in std_logic; + tvalid : out std_logic; + tlast : out std_logic; + tdata : out std_logic_vector (f_nbit_axis(N)-1 downto 0) + ); +end component; + +-- PFB framing. +component pfb_framing is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Framing. + tready : in std_logic; + tvalid : in std_logic; + fr_sync : in std_logic; + fr_out : out std_logic + ); +end component; + +begin + +-- PFB configuration. +cfg_i : pfb_cfg + Generic map ( + -- Number of channels. + N => N + ) + Port map ( + -- Reset and clock. + rstn => aresetn , + clk => aclk , + + -- Filter config. + cfg_en => cfg_en , + tready => m_axis_config_tready , + tvalid => m_axis_config_tvalid , + tlast => m_axis_config_tlast , + tdata => m_axis_config_tdata + ); + +-- PFB framing. +framing_i : pfb_framing + Generic map ( + -- Number of channels. + N => N + ) + Port map ( + -- Reset and clock. + rstn => aresetn , + clk => aclk , + + -- Framing. + tready => tready , + tvalid => tvalid , + fr_sync => fr_sync , + fr_out => fr_out + ); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_ctrl_pkg.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_ctrl_pkg.vhd new file mode 100644 index 0000000..db99fb3 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_ctrl_pkg.vhd @@ -0,0 +1,38 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +package pfb_ctrl_pkg is + + -- Functions. + function f_nbit_axis (ARG: Integer) return Integer; + +end pfb_ctrl_pkg; + +package body pfb_ctrl_pkg is + + function f_nbit_axis (ARG: Integer) return Integer is + -- Function variables. + variable arg_log2 : Integer := Integer(ceil(log2(real(ARG)))); + variable tmp : Integer; + + begin + + if (arg_log2 <= 8 ) then + tmp := 8; + elsif ( arg_log2 <= 16 ) then + tmp := 16; + elsif ( arg_log2 <= 24 ) then + tmp := 24; + elsif ( arg_log2 <= 32 ) then + tmp := 32; + else + tmp := -1; + end if; + + return tmp; + end; + +end package body pfb_ctrl_pkg; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_framing.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_framing.vhd new file mode 100644 index 0000000..5ff7e74 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_framing.vhd @@ -0,0 +1,137 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity pfb_framing is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Framing. + tready : in std_logic; + tvalid : in std_logic; + fr_sync : in std_logic; + fr_out : out std_logic + ); +end pfb_framing; + +architecture rtl of pfb_framing is + +-- Number of bits of N. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Wait value. +constant WAIT_C : Integer := 10*N; +constant WAIT_C_LOG2 : Integer := Integer(ceil(log2(real(WAIT_C)))); + +-- FSM. +type fsm_type is ( INIT_ST , + SHIFT_ST , + WAIT_ST ); + +signal current_state, next_state : fsm_type; + +-- Free running counter for framing. +signal fr_cnt : unsigned (N_LOG2-1 downto 0); +signal fr_cnt_en : std_logic; + +-- Counter for waiting until next calibration. +signal wait_cnt : unsigned (WAIT_C_LOG2-1 downto 0); +signal wait_cnt_en : std_logic; + +-- Framing sync. +signal fr_i : std_logic; + +begin + +-- Registers. +process(clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + -- State register. + current_state <= INIT_ST; + + -- Counters. + fr_cnt <= (others => '0'); + wait_cnt <= (others => '0'); + else + -- State register. + current_state <= next_state; + + -- Counters. + if ( fr_cnt_en = '1' and tready = '1' and tvalid = '1' ) then + if ( fr_cnt < to_unsigned(N-1,fr_cnt'length) ) then + fr_cnt <= fr_cnt + 1; + else + fr_cnt <= (others => '0'); + end if; + end if; + if ( wait_cnt_en = '1' ) then + if ( wait_cnt < to_unsigned(WAIT_C-1,wait_cnt'length) ) then + wait_cnt <= wait_cnt + 1; + else + wait_cnt <= (others => '0'); + end if; + end if; + + end if; + end if; +end process; + +-- Framing sync. +fr_i <= '1' when fr_cnt = to_unsigned(N-1,fr_cnt'length) else + '0'; + +-- Next state logic. +process (current_state, fr_sync, wait_cnt) +begin + case current_state is + when INIT_ST => + if ( fr_sync = '0' ) then + next_state <= INIT_ST; + else + next_state <= SHIFT_ST; + end if; + + when SHIFT_ST => + next_state <= WAIT_ST; + + when WAIT_ST => + if ( wait_cnt = to_unsigned(WAIT_C-1,wait_cnt'length) ) then + next_state <= INIT_ST; + else + next_state <= WAIT_ST; + end if; + end case; +end process; + +-- Output logic. +process (current_state) +begin +fr_cnt_en <= '0'; +wait_cnt_en <= '0'; + case current_state is + when INIT_ST => + fr_cnt_en <= '1'; + + when SHIFT_ST => + + when WAIT_ST => + fr_cnt_en <= '1'; + wait_cnt_en <= '1'; + + end case; +end process; + +-- Assign outputs. +fr_out <= fr_i; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_reorder.sv b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_reorder.sv new file mode 100644 index 0000000..4b57dab --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/pfb_reorder.sv @@ -0,0 +1,113 @@ +// This block reorders PFB output to get it ready for the +// SSR FFT. +module pfb_reorder + ( + // Reset and clock. + aclk , + + // S_AXIS for input data. + s_axis_tvalid , + s_axis_tlast , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tlast , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Bits. +parameter B = 32; + +// Number of Lanes. +parameter L = 4; + +/*********/ +/* Ports */ +/*********/ +input aclk; + +input s_axis_tvalid; +input s_axis_tlast; +input [2*L*B-1:0] s_axis_tdata; + +output m_axis_tvalid; +output m_axis_tlast; +output [2*L*B-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Sorted input data. +wire [2*L*B-1:0] din_sort; + +// Data registers. +reg [2*L*B-1:0] data_r1 = 0; +reg [2*L*B-1:0] data_r2 = 0; +reg [2*L*B-1:0] data_r3 = 0; +reg [2*L*B-1:0] data_r4 = 0; + +// Tlast registers. +reg last_r1 = 0; +reg last_r2 = 0; +reg last_r3 = 0; + +// Low/High data. +wire [2*L*B-1:0] dlow; +wire [2*L*B-1:0] dhigh; + +// Muxed output. +reg sel = 0; +wire [2*L*B-1:0] dmux; + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i NBITS+1 , + + -- Fifo depth. + N => 4 + ) + Port map + ( + rstn => aresetn , + clk => aclk , + + -- Write I/F. + wr_en => s_axis_tvalid , + din => fifo_din , + + -- Read I/F. + rd_en => m_axis_tready , + dout => fifo_dout , + + -- Flags. + full => fifo_full , + empty => fifo_empty + ); + +-- Fifo connections. +fifo_din <= s_axis_tlast & s_axis_tdata; +s_axis_tready <= not(fifo_full); + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( aresetn = '0' ) then + -- Pipeline registers. + d_r <= (others => '0'); + d_rr <= (others => '0'); + empty_r <= '1'; + empty_rr <= '1'; + last_r <= '0'; + last_rr <= '0'; + + -- sel register. + cnt <= (others => '0'); + sel <= (others => '0'); + else + -- Pipeline registers. + d_r <= d_i; + d_rr <= d_mux; + empty_r <= fifo_empty; + empty_rr <= empty_r; + last_r <= last_i; + last_rr <= last_r; + + -- sel register: if reading and not empty, count. + if ( m_axis_tready = '1' and empty_r = '0' ) then + if ( cnt < to_unsigned(T-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + sel <= sel + 1; + end if; + end if; + + end if; + end if; +end process; + +-- Input data/tlast. +d_i <= fifo_dout(NBITS-1 downto 0); +last_i <= fifo_dout(NBITS); + +-- Slice input. +GEN_SLICE_IN: for I in 0 to L-1 generate + dv_i(I) <= signed(d_r ( 2*I*B+B-1 downto 2*I*B)); + dv_q(I) <= signed(d_r ( (2*I+1)*B+B-1 downto (2*I+1)*B)); +end generate GEN_SLICE_IN; + +-- Multiply by -1 only odd samples. +GEN_PM: for I in 0 to L/2-1 generate + -- Even samples: multiply always by 1. + dv_i_pm(2*I) <= dv_i(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_i_pm(2*I+1) <= to_signed(MAX_P,B) when dv_i(2*I+1) = to_signed(MIN_N,B) else + -dv_i(2*I+1); + + -- Even samples: multiply always by 1. + dv_q_pm(2*I) <= dv_q(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_q_pm(2*I+1) <= to_signed(MAX_P,B) when dv_q(2*I+1) = to_signed(MIN_N,B) else + -dv_q(2*I+1); +end generate GEN_PM; + +-- Combine signals back. +GEN_COMBINE_PM: for I in 0 to L-1 generate + d_pm ( 2*I*B+B-1 downto 2*I*B) <= std_logic_vector(dv_i_pm(I)); + d_pm ((2*I+1)*B+B-1 downto (2*I+1)*B) <= std_logic_vector(dv_q_pm(I)); +end generate GEN_COMBINE_PM; + +-- Data mux. +d_mux <= d_r when sel = to_unsigned(0,sel'length) else + d_pm; + + +-- Assign outputs. +m_axis_tdata <= d_rr; +m_axis_tlast <= last_rr; +m_axis_tvalid <= not(empty_rr); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb/zn_nb.vhd b/firmware/ip/axis_pfb_readout_v3/src/pfb/zn_nb.vhd new file mode 100644 index 0000000..2add8e5 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb/zn_nb.vhd @@ -0,0 +1,54 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity zn_nb is + Generic + ( + -- Number of bits. + B : Integer := 16; + + -- Delay. + N : Integer := 4 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- S_AXIS for intput. + s_axis_tvalid : in std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + + -- M_AXIS for output. + m_axis_tvalid : out std_logic; + m_axis_tdata : out std_logic_vector(B-1 downto 0) + + ); +end zn_nb; + +architecture rtl of zn_nb is + +-- Shift register for data. +type reg_v is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal shift_reg_tdata : reg_v; + +begin + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( s_axis_tvalid = '1' ) then + shift_reg_tdata <= shift_reg_tdata (N-2 downto 0) & s_axis_tdata; + end if; + end if; +end process; + +-- Assign outputs. +m_axis_tdata <= shift_reg_tdata (N-1); +m_axis_tvalid <= s_axis_tvalid; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v3/src/pfb_readout.v b/firmware/ip/axis_pfb_readout_v3/src/pfb_readout.v new file mode 100644 index 0000000..acba9e8 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/pfb_readout.v @@ -0,0 +1,124 @@ +/* + * Top-leve block which instantiates the following: + * + * 1) PFB, 50 % Overlap, 64 Channels, 4 selectable outputs. + * 2) DDS, 4 channels, independent freq/phase, phase coherent. + */ +module pfb_readout + #( + // Number of channels. + parameter N = 32, + + // Number of Lanes (Input). + parameter L = 4 + ) + ( + // Reset and clock. + input wire aresetn , + input wire aclk , + + // S_AXIS for input data. + input wire s_axis_tvalid , + input wire [L*32-1:0] s_axis_tdata , + + // M_AXIS for output data. + output wire m_axis_tvalid , + output wire [31:0] m0_axis_tdata , + output wire [31:0] m1_axis_tdata , + output wire [31:0] m2_axis_tdata , + output wire [31:0] m3_axis_tdata , + + // Registers. + input wire [15:0] ID0_REG , + input wire [15:0] ID1_REG , + input wire [15:0] ID2_REG , + input wire [15:0] ID3_REG , + input wire [31:0] PINC0_REG , + input wire [31:0] POFF0_REG , + input wire [31:0] PINC1_REG , + input wire [31:0] POFF1_REG , + input wire [31:0] PINC2_REG , + input wire [31:0] POFF2_REG , + input wire [31:0] PINC3_REG , + input wire [31:0] POFF3_REG + ); + +/********************/ +/* Internal signals */ +/********************/ + +wire tvalid_i; +wire [31:0] tdata0_i; +wire [31:0] tdata1_i; +wire [31:0] tdata2_i; +wire [31:0] tdata3_i; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// PFB. +pfb_top + #( + // Number of channels. + .N(N), + + // Number of Lanes (Input). + .L(L) + ) + pfb_top_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input data. + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for output data. + .m_axis_tvalid (tvalid_i ), + .m0_axis_tdata (tdata0_i ), + .m1_axis_tdata (tdata1_i ), + .m2_axis_tdata (tdata2_i ), + .m3_axis_tdata (tdata3_i ), + + // Registers. + .ID0_REG (ID0_REG ), + .ID1_REG (ID1_REG ), + .ID2_REG (ID2_REG ), + .ID3_REG (ID3_REG ) + ); + +// DDS. +ddsprod_v ddsprod_v_i + ( + // Clock. + .aclk (aclk ), + + // S_AXIS for input data. + .s_axis_tvalid (tvalid_i ), + .s0_axis_tdata (tdata0_i ), + .s1_axis_tdata (tdata1_i ), + .s2_axis_tdata (tdata2_i ), + .s3_axis_tdata (tdata3_i ), + + // M_AXIS for output data. + .m_axis_tvalid (m_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + .m1_axis_tdata (m1_axis_tdata ), + .m2_axis_tdata (m2_axis_tdata ), + .m3_axis_tdata (m3_axis_tdata ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .POFF0_REG (POFF0_REG ), + .PINC1_REG (PINC1_REG ), + .POFF1_REG (POFF1_REG ), + .PINC2_REG (PINC2_REG ), + .POFF2_REG (POFF2_REG ), + .PINC3_REG (PINC3_REG ), + .POFF3_REG (POFF3_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/axis_pfb_readout_v3.xdc b/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/axis_pfb_readout_v3.xdc new file mode 100644 index 0000000..d22e7ee --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/axis_pfb_readout_v3.xdc @@ -0,0 +1,60 @@ +create_clock -period 1.000 -name aclk -waveform {0.000 0.500} [get_ports aclk] +create_clock -period 10.000 -name s_axi_aclk -waveform {0.000 5.000} [get_ports s_axi_aclk] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_araddr[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports {s_axi_araddr[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_awaddr[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports {s_axi_awaddr[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_wdata[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports {s_axi_wdata[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_wstrb[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports {s_axi_wstrb[*]}] +set _xlnx_shared_i0 [get_ports {s_axis_tdata[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 $_xlnx_shared_i0 +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 $_xlnx_shared_i0 +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports aresetn] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports aresetn] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_aresetn] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_aresetn] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_arvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_arvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_awvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_awvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_bready] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_bready] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_rready] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_rready] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_wvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_wvalid] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports s_axis_tvalid] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports s_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {m0_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports {m0_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {m1_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports {m1_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {m2_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports {m2_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {m3_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports {m3_axis_tdata[*]}] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_rdata[*]}] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports {s_axi_rdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports m0_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports m0_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports m1_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports m1_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports m2_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports m2_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports m3_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports m3_axis_tvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_arready] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_arready] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_awready] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_awready] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_bvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_bvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_rvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_rvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_wready] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_wready] +set_clock_groups -asynchronous -group [get_clocks s_axi_aclk] -group [get_clocks aclk] + +set_false_path -to [all_outputs] diff --git a/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/dds_ctrl.xdc b/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/dds_ctrl.xdc new file mode 100644 index 0000000..46515ba --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/dds_ctrl.xdc @@ -0,0 +1,13 @@ +create_clock -period 1.000 -name aclk -waveform {0.000 0.500} [get_ports aclk] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports en] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports en] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {POFF_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {POFF_REG[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports dout_valid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports dout_valid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports {dout[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports {dout[*]}] + +set_false_path -to [get_ports *dout*] diff --git a/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/dds_top.xdc b/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/dds_top.xdc new file mode 100644 index 0000000..8e8a0a2 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/dds_top.xdc @@ -0,0 +1,13 @@ +create_clock -period 1.000 -name aclk -waveform {0.000 0.500} [get_ports aclk] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports din_valid] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports din_valid] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {POFF_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {POFF_REG[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports dout_valid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports dout_valid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports {dout[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports {dout[*]}] + +set_false_path -to [get_ports *dout*] diff --git a/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/ddsprod.xdc b/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/ddsprod.xdc new file mode 100644 index 0000000..5505ca0 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/synth/xdcs/ddsprod.xdc @@ -0,0 +1,15 @@ +create_clock -period 1.000 -name aclk -waveform {0.000 0.500} [get_ports aclk] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports s_axis_tvalid] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports s_axis_tvalid] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {s_axis_tdata[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {s_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports m_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports m_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports {m_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports {m_axis_tdata[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {POFF_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {POFF_REG[*]}] + +set_false_path -to [get_ports *m_axis*] diff --git a/firmware/ip/axis_pfb_readout_v3/src/tb/tb.sv b/firmware/ip/axis_pfb_readout_v3/src/tb/tb.sv new file mode 100644 index 0000000..3665426 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/tb/tb.sv @@ -0,0 +1,339 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// Number of channels. +parameter N = 64; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; + +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +reg s_axis_tvalid; +wire [4*32-1:0] s_axis_tdata; + +wire m0_axis_tvalid; +reg [31:0] m0_axis_tdata; +wire m1_axis_tvalid; +reg [31:0] m1_axis_tdata; +wire m2_axis_tvalid; +reg [31:0] m2_axis_tdata; +wire m3_axis_tvalid; +reg [31:0] m3_axis_tdata; + + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Input data. +reg [31:0] din_ii [0:7]; + +// Output data. +wire [15:0] dout0_real; +wire [15:0] dout0_imag; +wire [15:0] dout1_real; +wire [15:0] dout1_imag; +wire [15:0] dout2_real; +wire [15:0] dout2_imag; +wire [15:0] dout3_real; +wire [15:0] dout3_imag; + +// Test bench control. +reg tb_data = 0; +reg tb_data_done= 0; +reg tb_write_out= 0; + + +generate +genvar ii; +for (ii = 0; ii < 8; ii = ii + 1) begin + assign s_axis_tdata[32*ii +: 32] = din_ii[ii]; +end +endgenerate + +assign dout0_real = m0_axis_tdata [15:0]; +assign dout0_imag = m0_axis_tdata [31:16]; +assign dout1_real = m1_axis_tdata [15:0]; +assign dout1_imag = m1_axis_tdata [31:16]; +assign dout2_real = m2_axis_tdata [15:0]; +assign dout2_imag = m2_axis_tdata [31:16]; +assign dout3_real = m3_axis_tdata [15:0]; +assign dout3_imag = m3_axis_tdata [31:16]; + +// axi_mst_0. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_pfb_readout_v3 + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // s_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input samples. + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for CH0 output. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + + // M_AXIS for CH1 output. + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tdata (m1_axis_tdata ), + + // M_AXIS for CH2 output. + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tdata (m2_axis_tdata ), + + // M_AXIS for CH3 output. + .m3_axis_tvalid (m3_axis_tvalid ), + .m3_axis_tdata (m3_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("###################"); + $display("### Program DDS ###"); + $display("###################"); + $display("t = %0t", $time); + + // ID0/1/2/3. + // ID [7:0]: packet + // ID [15:8]: id + axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, (0 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(1*4, prot, (1 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(2*4, prot, (6 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(3*4, prot, (6 << 8) + 0, resp); + + // FREQ0/PHASE0. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, 0, resp); + + // FREQ1/PHASE1. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(6*4, prot, freq(1,10), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(7*4, prot, 0, resp); + + // FREQ2/PHASE2. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(8*4, prot, freq(1, 33), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(9*4, prot, 0, resp); + + // FREQ3/PHASE3. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(10*4, prot, freq(1, 3), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(11*4, prot, 0, resp); + + $display("###############################"); + $display("### Start Recording Outputs ###"); + $display("###############################"); + $display("t = %0t", $time); + + tb_data <= 1; + tb_write_out <= 1; + wait (tb_data_done); + tb_write_out <= 0; + +end + +// Input data. +initial begin + int fd; + int i; + bit signed [15:0] vali, valq; + s_axis_tvalid <= 0; + + // Open file with Coefficients. + fd = $fopen("../../../../../tb/data_iq.txt","r"); + + wait(tb_data); + @(posedge aclk); + + i = 0; + while ($fscanf(fd,"%d,%d", vali, valq) == 2) begin + //$display("T = %d, i = %d, I = %d, Q = %d", $time, i, vali, valq); + din_ii[i] <= {valq,vali}; + i = i + 1; + if (i == 4) begin + i = 0; + @(posedge aclk); + s_axis_tvalid <= 1; + end + end + + @(posedge aclk); + s_axis_tvalid <= 0; + tb_data_done <= 1; + +end + +// Write output into file. +initial begin + int fd0, fd1, fd2, fd3; + int i; + shortint real_d0, imag_d0; + shortint real_d1, imag_d1; + shortint real_d2, imag_d2; + shortint real_d3, imag_d3; + + // Output file. + fd0 = $fopen("../../../../../tb/dout_0.csv","w"); + fd1 = $fopen("../../../../../tb/dout_1.csv","w"); + fd2 = $fopen("../../../../../tb/dout_2.csv","w"); + fd3 = $fopen("../../../../../tb/dout_3.csv","w"); + + // Data format. + $fdisplay(fd0, "valid, real, imag"); + $fdisplay(fd1, "valid, real, imag"); + $fdisplay(fd2, "valid, real, imag"); + $fdisplay(fd3, "valid, real, imag"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + real_d0 = m0_axis_tdata[15:0]; + imag_d0 = m0_axis_tdata[31:16]; + real_d1 = m1_axis_tdata[15:0]; + imag_d1 = m1_axis_tdata[31:16]; + real_d2 = m2_axis_tdata[15:0]; + imag_d2 = m2_axis_tdata[31:16]; + real_d3 = m3_axis_tdata[15:0]; + imag_d3 = m3_axis_tdata[31:16]; + $fdisplay(fd0,"%d,%d,%d",m0_axis_tvalid,real_d0,imag_d0); + $fdisplay(fd1,"%d,%d,%d",m1_axis_tvalid,real_d1,imag_d1); + $fdisplay(fd2,"%d,%d,%d",m2_axis_tvalid,real_d2,imag_d2); + $fdisplay(fd3,"%d,%d,%d",m3_axis_tvalid,real_d3,imag_d3); + end + + $display("Closing file, t = %0t", $time); + $fclose(fd0); + $fclose(fd1); + $fclose(fd2); + $fclose(fd3); +end + +always begin + s_axi_aclk <= 0; + #10; + s_axi_aclk <= 1; + #10; +end + +always begin + aclk <= 0; + #1; + aclk <= 1; + #1; +end + +function bit [31:0] freq (input real f, fs); + int ret; + + // I use only 16 bits for rounding. Add the remaining later... + ret = 2**16*f/fs; + + return {ret,16'h0000}; +endfunction + +function bit [31:0] phase (input real phi); + int ret; + + // I use only 16 bits for rounding. Add the remaining later... + ret = 2**16*phi/360; + + return {ret,16'h0000}; +endfunction + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/tb/tb_dds_ctrl.sv b/firmware/ip/axis_pfb_readout_v3/src/tb/tb_dds_ctrl.sv new file mode 100644 index 0000000..d272783 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/tb/tb_dds_ctrl.sv @@ -0,0 +1,72 @@ +module tb(); + +// Reset and clock. +reg aclk ; + +// Enable input. +reg en ; + +// Output data. +wire dout_valid ; +wire [71:0] dout ; + +// Registers. +reg [31:0] PINC_REG ; +reg [31:0] POFF_REG ; + +/**************/ +/* Test Bench */ +/**************/ + +/****************/ +/* Architecture */ +/****************/ + +// DUT. +dds_ctrl DUT + ( + // Reset and clock. + .aclk , + + // Enable input. + .en , + + // Output data. + .dout_valid , + .dout , + + // Registers. + .PINC_REG , + .POFF_REG + ); + +// PINC/POFF. +initial begin + PINC_REG <= 1234; + POFF_REG <= 4567; + + #1000; +end + +// en. +initial begin + en <= 0; + while (1) begin + for (int i=0; i<10; i=i+1) begin + @(posedge aclk); + en <= 0; + end + @(posedge aclk); + en <= 1; + end +end + +always begin + aclk <= 0; + #8; + aclk <= 1; + #8; +end + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/tb/tb_dds_top.sv b/firmware/ip/axis_pfb_readout_v3/src/tb/tb_dds_top.sv new file mode 100644 index 0000000..554077e --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/tb/tb_dds_top.sv @@ -0,0 +1,77 @@ +module tb(); + +// Reset and clock. +reg aclk ; + +// Input valid. +reg din_valid ; + +// Output data. +wire dout_valid ; +wire [31:0] dout ; + +// Registers. +reg [31:0] PINC_REG ; +reg [31:0] POFF_REG ; + +/**************/ +/* Test Bench */ +/**************/ +wire [15:0] dout_real ; +wire [15:0] dout_imag ; + +/****************/ +/* Architecture */ +/****************/ + +assign dout_real = dout[15:0]; +assign dout_imag = dout[31:16]; + +// DUT. +dds_top DUT + ( + // Reset and clock. + .aclk , + + // Input valid. + .din_valid , + + // Output data. + .dout_valid , + .dout , + + // Registers. + .PINC_REG , + .POFF_REG + ); + +// PINC/POFF. +initial begin + PINC_REG <= 12345959; + POFF_REG <= 4567; + + #1000; +end + +// din_valid. +initial begin + din_valid <= 0; + while (1) begin + for (int i=0; i<10; i=i+1) begin + @(posedge aclk); + din_valid <= 0; + end + @(posedge aclk); + din_valid <= 1; + end +end + +always begin + aclk <= 0; + #8; + aclk <= 1; + #8; +end + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/tb/tb_ddsprod.sv b/firmware/ip/axis_pfb_readout_v3/src/tb/tb_ddsprod.sv new file mode 100644 index 0000000..86942bd --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/tb/tb_ddsprod.sv @@ -0,0 +1,122 @@ +module tb(); + +// Clock. +reg aclk ; + +// S_AXIS for input data. +reg s_axis_tvalid ; +wire [31:0] s_axis_tdata ; + +// M_AXIS for output data. +wire m_axis_tvalid ; +wire [31:0] m_axis_tdata ; + +// Registers. +reg [31:0] PINC_REG ; +reg [31:0] POFF_REG ; + +/**************/ +/* Test Bench */ +/**************/ +reg [15:0] din_real ; +reg [15:0] din_imag ; +wire [15:0] dout_real ; +wire [15:0] dout_imag ; + +/****************/ +/* Architecture */ +/****************/ + +assign s_axis_tdata = {din_imag, din_real}; +assign dout_real = m_axis_tdata [15:0]; +assign dout_imag = m_axis_tdata [31:16]; + +// DUT. +ddsprod DUT + ( + // Clock. + .aclk , + + // S_AXIS for input data. + .s_axis_tvalid , + .s_axis_tdata , + + // M_AXIS for output data. + .m_axis_tvalid , + .m_axis_tdata , + + // Registers. + .PINC_REG , + .POFF_REG + ); + +// PINC/POFF. +initial begin + PINC_REG <= 0; + POFF_REG <= 0; + + #1000; + + // Set dds frequency/phase. + PINC_REG <= freq(1, 500); + POFF_REG <= phase(90); +end + +// Input data. +initial begin + int n; + real a0, w0, f0, fs; + + s_axis_tvalid <= 0; + din_real <= 0; + din_imag <= 0; + + // Amplitude. + a0 = 0.5; + + // Frequency. + fs = 500; + f0 = 1; + w0 = f0/fs*2*3.14159; + + n = 0; + while (1) begin + for (int i=0; i<10; i=i+1) begin + @(posedge aclk); + s_axis_tvalid <= 0; + end + @(posedge aclk); + s_axis_tvalid <= 1; + din_real <= a0*2**15*$cos(w0*n); + din_imag <= a0*2**15*$sin(w0*n); + n = n+1; + end +end + +always begin + aclk <= 0; + #1; + aclk <= 1; + #1; +end + +function bit [31:0] freq (input real f, fs); + int ret; + + // I use only 16 bits for rounding. Add the remaining later... + ret = 2**16*f/fs; + + return {ret,16'h0000}; +endfunction + +function bit [31:0] phase (input real phi); + int ret; + + // I use only 16 bits for rounding. Add the remaining later... + ret = 2**16*phi/360; + + return {ret,16'h0000}; +endfunction + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v3/src/tb/tb_pfb.sv b/firmware/ip/axis_pfb_readout_v3/src/tb/tb_pfb.sv new file mode 100644 index 0000000..2fa3c88 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v3/src/tb/tb_pfb.sv @@ -0,0 +1,181 @@ +module tb(); + +// Number of channels. +parameter N = 64; + +// Number of Lanes (Input). +parameter L = 4; + +// Reset and clock. +reg aresetn ; +reg aclk ; + +// S_AXIS for input data. +reg s_axis_tvalid ; +wire [L*32-1:0] s_axis_tdata ; + +// M_AXIS for output data. +wire m_axis_tvalid ; +wire m_axis_tlast ; +wire [2*L*32-1:0] m_axis_tdata ; + +// Registers. +reg [7:0] QOUT_REG ; + +/**************/ +/* Test Bench */ +/**************/ +localparam NCH = N/(2*L); +// x4 clock. +reg aclk_x4 ; +reg [15:0] din_real ; +reg [15:0] din_imag ; +reg [31:0] din [L] ; + +// x8 clock. +reg aclk_x8 ; + +// TDM Demux outputs. +reg tdm_sync ; +wire [NCH*32-1:0] tdm_dout [2*L] ; +wire [2*L-1:0] tdm_valid ; +wire signed [15:0] dout_real_ii [2*L][NCH] ; +wire signed [15:0] dout_imag_ii [2*L][NCH] ; + + +/****************/ +/* Architecture */ +/****************/ +genvar i,j; +generate + // Input data. + for (i=0; i parallel. +always @(posedge aclk) begin + for (int i=0; i parallel. +always @(posedge aclk) begin + for (int i=0; i + + user.org + user + axis_pfb_readout_v4 + 1.0 + + + m0_axis + + + + + + + TDATA + + + m0_axis_tdata + + + + + TVALID + + + m0_axis_tvalid + + + + + + m1_axis + + + + + + + TDATA + + + m1_axis_tdata + + + + + TVALID + + + m1_axis_tvalid + + + + + + m2_axis + + + + + + + TDATA + + + m2_axis_tdata + + + + + TVALID + + + m2_axis_tvalid + + + + + + m3_axis + + + + + + + TDATA + + + m3_axis_tdata + + + + + TVALID + + + m3_axis_tvalid + + + + + + m4_axis + + + + + + + TDATA + + + m4_axis_tdata + + + + + TVALID + + + m4_axis_tvalid + + + + + + m5_axis + + + + + + + TDATA + + + m5_axis_tdata + + + + + TVALID + + + m5_axis_tvalid + + + + + + m6_axis + + + + + + + TDATA + + + m6_axis_tdata + + + + + TVALID + + + m6_axis_tvalid + + + + + + m7_axis + + + + + + + TDATA + + + m7_axis_tdata + + + + + TVALID + + + m7_axis_tvalid + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m0_axis:m1_axis:m2_axis:m3_axis:m4_axis:m5_axis:m6_axis:m7_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_pfb_readout_v4 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 9ebcf76d + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_pfb_readout_v4 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 9ebcf76d + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 0891018f + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation 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+ CHECKSUM_0891018f + XGUI_VERSION_2 + + + + AXIS PFB Readout, 64 Channels, 8 outputs, V4. + + + N + N + 64 + + + Component_Name + axis_pfb_readout_v4_v1_0 + + + + + + zynquplus + + + /UserIP + + AXIS PFB Readout V4 + package_project + 3 + 2024-04-12T14:13:36Z + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/axi_slv.v b/firmware/ip/axis_pfb_readout_v4/src/axi_slv.v new file mode 100644 index 0000000..74f5f84 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/axi_slv.v @@ -0,0 +1,1070 @@ +`timescale 1 ns / 1 ps + +module axi_slv + ( + input wire s_axi_aclk , + input wire s_axi_aresetn , + + // Write Address Channel. + input wire [7:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + + // Write Data Channel. + input wire [31:0] s_axi_wdata , + input wire [3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + + // Write Response Channel. + output wire [1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + + // Read Address Channel. + input wire [7:0] s_axi_araddr , + input wire [2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + + // Read Data Channel. + output wire [31:0] s_axi_rdata , + output wire [1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , + + // Registers. + output wire [15:0] ID0_REG , + output wire [15:0] ID1_REG , + output wire [15:0] ID2_REG , + output wire [15:0] ID3_REG , + output wire [15:0] ID4_REG , + output wire [15:0] ID5_REG , + output wire [15:0] ID6_REG , + output wire [15:0] ID7_REG , + output wire [31:0] PINC0_REG , + output wire [31:0] POFF0_REG , + output wire [31:0] PINC1_REG , + output wire [31:0] POFF1_REG , + output wire [31:0] PINC2_REG , + output wire [31:0] POFF2_REG , + output wire [31:0] PINC3_REG , + output wire [31:0] POFF3_REG , + output wire [31:0] PINC4_REG , + output wire [31:0] POFF4_REG , + output wire [31:0] PINC5_REG , + output wire [31:0] POFF5_REG , + output wire [31:0] PINC6_REG , + output wire [31:0] POFF6_REG , + output wire [31:0] PINC7_REG , + output wire [31:0] POFF7_REG +); + +// Width of S_AXI data bus +localparam integer C_S_AXI_DATA_WIDTH = 32; +// Width of S_AXI address bus +localparam integer C_S_AXI_ADDR_WIDTH = 8; + +// AXI4LITE signals +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr; +reg axi_awready; +reg axi_wready; +reg [1 : 0] axi_bresp; +reg axi_bvalid; +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr; +reg axi_arready; +reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata; +reg [1 : 0] axi_rresp; +reg axi_rvalid; + +// Example-specific design signals +// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH +// ADDR_LSB is used for addressing 32/64 bit registers/memories +// ADDR_LSB = 2 for 32 bits (n downto 2) +// ADDR_LSB = 3 for 64 bits (n downto 3) +localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1; +localparam integer OPT_MEM_ADDR_BITS = 5; +//---------------------------------------------- +//-- Signals for user logic register space example +//------------------------------------------------ +//-- Number of Slave Registers 64 +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg32; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg33; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg34; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg35; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg36; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg37; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg38; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg39; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg40; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg41; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg42; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg43; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg44; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg45; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg46; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg47; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg48; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg49; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg50; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg51; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg52; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg53; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg54; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg55; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg56; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg57; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg58; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg59; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg60; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg61; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg62; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg63; +wire slv_reg_rden; +wire slv_reg_wren; +reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out; +integer byte_index; +reg aw_en; + +// I/O Connections assignments + +assign s_axi_awready = axi_awready; +assign s_axi_wready = axi_wready; +assign s_axi_bresp = axi_bresp; +assign s_axi_bvalid = axi_bvalid; +assign s_axi_arready = axi_arready; +assign s_axi_rdata = axi_rdata; +assign s_axi_rresp = axi_rresp; +assign s_axi_rvalid = axi_rvalid; +// Implement axi_awready generation +// axi_awready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_awready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awready <= 1'b0; + aw_en <= 1'b1; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // slave is ready to accept write address when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_awready <= 1'b1; + aw_en <= 1'b0; + end + else if (s_axi_bready && axi_bvalid) + begin + aw_en <= 1'b1; + axi_awready <= 1'b0; + end + else + begin + axi_awready <= 1'b0; + end + end +end + +// Implement axi_awaddr latching +// This process is used to latch the address when both +// s_axi_awvalid and s_axi_wvalid are valid. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awaddr <= 0; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // Write Address latching + axi_awaddr <= s_axi_awaddr; + end + end +end + +// Implement axi_wready generation +// axi_wready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_wready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_wready <= 1'b0; + end + else + begin + if (~axi_wready && s_axi_wvalid && s_axi_awvalid && aw_en ) + begin + // slave is ready to accept write data when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_wready <= 1'b1; + end + else + begin + axi_wready <= 1'b0; + end + end +end + +// Implement memory mapped register select and write logic generation +// The write data is accepted and written to memory mapped registers when +// axi_awready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. Write strobes are used to +// select byte enables of slave registers while writing. +// These registers are cleared when reset (active low) is applied. +// Slave register write enable is asserted when valid address and data are available +// and the slave is ready to accept the write address and write data. +assign slv_reg_wren = axi_wready && s_axi_wvalid && axi_awready && s_axi_awvalid; + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + slv_reg0 <= 0; + slv_reg1 <= 0; + slv_reg2 <= 0; + slv_reg3 <= 0; + slv_reg4 <= 0; + slv_reg5 <= 0; + slv_reg6 <= 0; + slv_reg7 <= 0; + slv_reg8 <= 0; + slv_reg9 <= 0; + slv_reg10 <= 0; + slv_reg11 <= 0; + slv_reg12 <= 0; + slv_reg13 <= 0; + slv_reg14 <= 0; + slv_reg15 <= 0; + slv_reg16 <= 0; + slv_reg17 <= 0; + slv_reg18 <= 0; + slv_reg19 <= 0; + slv_reg20 <= 0; + slv_reg21 <= 0; + slv_reg22 <= 0; + slv_reg23 <= 0; + slv_reg24 <= 0; + slv_reg25 <= 0; + slv_reg26 <= 0; + slv_reg27 <= 0; + slv_reg28 <= 0; + slv_reg29 <= 0; + slv_reg30 <= 0; + slv_reg31 <= 0; + slv_reg32 <= 0; + slv_reg33 <= 0; + slv_reg34 <= 0; + slv_reg35 <= 0; + slv_reg36 <= 0; + slv_reg37 <= 0; + slv_reg38 <= 0; + slv_reg39 <= 0; + slv_reg40 <= 0; + slv_reg41 <= 0; + slv_reg42 <= 0; + slv_reg43 <= 0; + slv_reg44 <= 0; + slv_reg45 <= 0; + slv_reg46 <= 0; + slv_reg47 <= 0; + slv_reg48 <= 0; + slv_reg49 <= 0; + slv_reg50 <= 0; + slv_reg51 <= 0; + slv_reg52 <= 0; + slv_reg53 <= 0; + slv_reg54 <= 0; + slv_reg55 <= 0; + slv_reg56 <= 0; + slv_reg57 <= 0; + slv_reg58 <= 0; + slv_reg59 <= 0; + slv_reg60 <= 0; + slv_reg61 <= 0; + slv_reg62 <= 0; + slv_reg63 <= 0; + end + else begin + if (slv_reg_wren) + begin + case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 0 + slv_reg0[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h01: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 1 + slv_reg1[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h02: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 2 + slv_reg2[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h03: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 3 + slv_reg3[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h04: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 4 + slv_reg4[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h05: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 5 + slv_reg5[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h06: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 6 + slv_reg6[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h07: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 7 + slv_reg7[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h08: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 8 + slv_reg8[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h09: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 9 + slv_reg9[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 10 + slv_reg10[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 11 + slv_reg11[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 12 + slv_reg12[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 13 + slv_reg13[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 14 + slv_reg14[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 15 + slv_reg15[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h10: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 16 + slv_reg16[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h11: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 17 + slv_reg17[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h12: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 18 + slv_reg18[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h13: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 19 + slv_reg19[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h14: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 20 + slv_reg20[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h15: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 21 + slv_reg21[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h16: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 22 + slv_reg22[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h17: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 23 + slv_reg23[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h18: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 24 + slv_reg24[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h19: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 25 + slv_reg25[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 26 + slv_reg26[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 27 + slv_reg27[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 28 + slv_reg28[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 29 + slv_reg29[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 30 + slv_reg30[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 31 + slv_reg31[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h20: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 32 + slv_reg32[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h21: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 33 + slv_reg33[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h22: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 34 + slv_reg34[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h23: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 35 + slv_reg35[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h24: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 36 + slv_reg36[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h25: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 37 + slv_reg37[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h26: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 38 + slv_reg38[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h27: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 39 + slv_reg39[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h28: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 40 + slv_reg40[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h29: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 41 + slv_reg41[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 42 + slv_reg42[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 43 + slv_reg43[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 44 + slv_reg44[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 45 + slv_reg45[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 46 + slv_reg46[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 47 + slv_reg47[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h30: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 48 + slv_reg48[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h31: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 49 + slv_reg49[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h32: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 50 + slv_reg50[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h33: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 51 + slv_reg51[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h34: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 52 + slv_reg52[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h35: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 53 + slv_reg53[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h36: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 54 + slv_reg54[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h37: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 55 + slv_reg55[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h38: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 56 + slv_reg56[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h39: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 57 + slv_reg57[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 58 + slv_reg58[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 59 + slv_reg59[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 60 + slv_reg60[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 61 + slv_reg61[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 62 + slv_reg62[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 63 + slv_reg63[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + default : begin + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + slv_reg16 <= slv_reg16; + slv_reg17 <= slv_reg17; + slv_reg18 <= slv_reg18; + slv_reg19 <= slv_reg19; + slv_reg20 <= slv_reg20; + slv_reg21 <= slv_reg21; + slv_reg22 <= slv_reg22; + slv_reg23 <= slv_reg23; + slv_reg24 <= slv_reg24; + slv_reg25 <= slv_reg25; + slv_reg26 <= slv_reg26; + slv_reg27 <= slv_reg27; + slv_reg28 <= slv_reg28; + slv_reg29 <= slv_reg29; + slv_reg30 <= slv_reg30; + slv_reg31 <= slv_reg31; + slv_reg32 <= slv_reg32; + slv_reg33 <= slv_reg33; + slv_reg34 <= slv_reg34; + slv_reg35 <= slv_reg35; + slv_reg36 <= slv_reg36; + slv_reg37 <= slv_reg37; + slv_reg38 <= slv_reg38; + slv_reg39 <= slv_reg39; + slv_reg40 <= slv_reg40; + slv_reg41 <= slv_reg41; + slv_reg42 <= slv_reg42; + slv_reg43 <= slv_reg43; + slv_reg44 <= slv_reg44; + slv_reg45 <= slv_reg45; + slv_reg46 <= slv_reg46; + slv_reg47 <= slv_reg47; + slv_reg48 <= slv_reg48; + slv_reg49 <= slv_reg49; + slv_reg50 <= slv_reg50; + slv_reg51 <= slv_reg51; + slv_reg52 <= slv_reg52; + slv_reg53 <= slv_reg53; + slv_reg54 <= slv_reg54; + slv_reg55 <= slv_reg55; + slv_reg56 <= slv_reg56; + slv_reg57 <= slv_reg57; + slv_reg58 <= slv_reg58; + slv_reg59 <= slv_reg59; + slv_reg60 <= slv_reg60; + slv_reg61 <= slv_reg61; + slv_reg62 <= slv_reg62; + slv_reg63 <= slv_reg63; + end + endcase + end + end +end + +// Implement write response logic generation +// The write response and response valid signals are asserted by the slave +// when axi_wready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. +// This marks the acceptance of address and indicates the status of +// write transaction. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_bvalid <= 0; + axi_bresp <= 2'b0; + end + else + begin + if (axi_awready && s_axi_awvalid && ~axi_bvalid && axi_wready && s_axi_wvalid) + begin + // indicates a valid write response is available + axi_bvalid <= 1'b1; + axi_bresp <= 2'b0; // 'OKAY' response + end // work error responses in future + else + begin + if (s_axi_bready && axi_bvalid) + //check if bready is asserted while bvalid is high) + //(there is a possibility that bready is always asserted high) + begin + axi_bvalid <= 1'b0; + end + end + end +end + +// Implement axi_arready generation +// axi_arready is asserted for one s_axi_aclk clock cycle when +// s_axi_arvalid is asserted. axi_awready is +// de-asserted when reset (active low) is asserted. +// The read address is also latched when s_axi_arvalid is +// asserted. axi_araddr is reset to zero on reset assertion. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_arready <= 1'b0; + axi_araddr <= 32'b0; + end + else + begin + if (~axi_arready && s_axi_arvalid) + begin + // indicates that the slave has acceped the valid read address + axi_arready <= 1'b1; + // Read address latching + axi_araddr <= s_axi_araddr; + end + else + begin + axi_arready <= 1'b0; + end + end +end + +// Implement axi_arvalid generation +// axi_rvalid is asserted for one s_axi_aclk clock cycle when both +// s_axi_arvalid and axi_arready are asserted. The slave registers +// data are available on the axi_rdata bus at this instance. The +// assertion of axi_rvalid marks the validity of read data on the +// bus and axi_rresp indicates the status of read transaction.axi_rvalid +// is deasserted on reset (active low). axi_rresp and axi_rdata are +// cleared to zero on reset (active low). +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rvalid <= 0; + axi_rresp <= 0; + end + else + begin + if (axi_arready && s_axi_arvalid && ~axi_rvalid) + begin + // Valid read data is available at the read data bus + axi_rvalid <= 1'b1; + axi_rresp <= 2'b0; // 'OKAY' response + end + else if (axi_rvalid && s_axi_rready) + begin + // Read data is accepted by the master + axi_rvalid <= 1'b0; + end + end +end + +// Implement memory mapped register select and read logic generation +// Slave register read enable is asserted when valid address is available +// and the slave is ready to accept the read address. +assign slv_reg_rden = axi_arready & s_axi_arvalid & ~axi_rvalid; +always @(*) +begin + // Address decoding for reading registers + case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00 : reg_data_out <= slv_reg0; + 6'h01 : reg_data_out <= slv_reg1; + 6'h02 : reg_data_out <= slv_reg2; + 6'h03 : reg_data_out <= slv_reg3; + 6'h04 : reg_data_out <= slv_reg4; + 6'h05 : reg_data_out <= slv_reg5; + 6'h06 : reg_data_out <= slv_reg6; + 6'h07 : reg_data_out <= slv_reg7; + 6'h08 : reg_data_out <= slv_reg8; + 6'h09 : reg_data_out <= slv_reg9; + 6'h0A : reg_data_out <= slv_reg10; + 6'h0B : reg_data_out <= slv_reg11; + 6'h0C : reg_data_out <= slv_reg12; + 6'h0D : reg_data_out <= slv_reg13; + 6'h0E : reg_data_out <= slv_reg14; + 6'h0F : reg_data_out <= slv_reg15; + 6'h10 : reg_data_out <= slv_reg16; + 6'h11 : reg_data_out <= slv_reg17; + 6'h12 : reg_data_out <= slv_reg18; + 6'h13 : reg_data_out <= slv_reg19; + 6'h14 : reg_data_out <= slv_reg20; + 6'h15 : reg_data_out <= slv_reg21; + 6'h16 : reg_data_out <= slv_reg22; + 6'h17 : reg_data_out <= slv_reg23; + 6'h18 : reg_data_out <= slv_reg24; + 6'h19 : reg_data_out <= slv_reg25; + 6'h1A : reg_data_out <= slv_reg26; + 6'h1B : reg_data_out <= slv_reg27; + 6'h1C : reg_data_out <= slv_reg28; + 6'h1D : reg_data_out <= slv_reg29; + 6'h1E : reg_data_out <= slv_reg30; + 6'h1F : reg_data_out <= slv_reg31; + 6'h20 : reg_data_out <= slv_reg32; + 6'h21 : reg_data_out <= slv_reg33; + 6'h22 : reg_data_out <= slv_reg34; + 6'h23 : reg_data_out <= slv_reg35; + 6'h24 : reg_data_out <= slv_reg36; + 6'h25 : reg_data_out <= slv_reg37; + 6'h26 : reg_data_out <= slv_reg38; + 6'h27 : reg_data_out <= slv_reg39; + 6'h28 : reg_data_out <= slv_reg40; + 6'h29 : reg_data_out <= slv_reg41; + 6'h2A : reg_data_out <= slv_reg42; + 6'h2B : reg_data_out <= slv_reg43; + 6'h2C : reg_data_out <= slv_reg44; + 6'h2D : reg_data_out <= slv_reg45; + 6'h2E : reg_data_out <= slv_reg46; + 6'h2F : reg_data_out <= slv_reg47; + 6'h30 : reg_data_out <= slv_reg48; + 6'h31 : reg_data_out <= slv_reg49; + 6'h32 : reg_data_out <= slv_reg50; + 6'h33 : reg_data_out <= slv_reg51; + 6'h34 : reg_data_out <= slv_reg52; + 6'h35 : reg_data_out <= slv_reg53; + 6'h36 : reg_data_out <= slv_reg54; + 6'h37 : reg_data_out <= slv_reg55; + 6'h38 : reg_data_out <= slv_reg56; + 6'h39 : reg_data_out <= slv_reg57; + 6'h3A : reg_data_out <= slv_reg58; + 6'h3B : reg_data_out <= slv_reg59; + 6'h3C : reg_data_out <= slv_reg60; + 6'h3D : reg_data_out <= slv_reg61; + 6'h3E : reg_data_out <= slv_reg62; + 6'h3F : reg_data_out <= slv_reg63; + default : reg_data_out <= 0; + endcase +end + +// Output register or memory read data +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rdata <= 0; + end + else + begin + // When there is a valid read address (s_axi_arvalid) with + // acceptance of read address by the slave (axi_arready), + // output the read dada + if (slv_reg_rden) + begin + axi_rdata <= reg_data_out; // register read data + end + end +end + +assign ID0_REG = slv_reg0 [15:0] ; +assign ID1_REG = slv_reg1 [15:0] ; +assign ID2_REG = slv_reg2 [15:0] ; +assign ID3_REG = slv_reg3 [15:0] ; +assign ID4_REG = slv_reg4 [15:0] ; +assign ID5_REG = slv_reg5 [15:0] ; +assign ID6_REG = slv_reg6 [15:0] ; +assign ID7_REG = slv_reg7 [15:0] ; +assign PINC0_REG = slv_reg8 ; +assign POFF0_REG = slv_reg9 ; +assign PINC1_REG = slv_reg10 ; +assign POFF1_REG = slv_reg11 ; +assign PINC2_REG = slv_reg12 ; +assign POFF2_REG = slv_reg13 ; +assign PINC3_REG = slv_reg14 ; +assign POFF3_REG = slv_reg15 ; +assign PINC4_REG = slv_reg16 ; +assign POFF4_REG = slv_reg17 ; +assign PINC5_REG = slv_reg18 ; +assign POFF5_REG = slv_reg19 ; +assign PINC6_REG = slv_reg20 ; +assign POFF6_REG = slv_reg21 ; +assign PINC7_REG = slv_reg22 ; +assign POFF7_REG = slv_reg23 ; + +endmodule diff --git a/firmware/ip/axis_pfb_readout_v4/src/axis_pfb_readout_v4.v b/firmware/ip/axis_pfb_readout_v4/src/axis_pfb_readout_v4.v new file mode 100644 index 0000000..c272e0d --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/axis_pfb_readout_v4.v @@ -0,0 +1,241 @@ +module axis_pfb_readout_v4 + #( + // Number of channels. + parameter N = 64 + ) + ( + // AXI Slave I/F for configuration. + input s_axi_aclk , + input s_axi_aresetn , + + input [7:0] s_axi_awaddr , + input [2:0] s_axi_awprot , + input s_axi_awvalid , + output s_axi_awready , + + input [31:0] s_axi_wdata , + input [3:0] s_axi_wstrb , + input s_axi_wvalid , + output s_axi_wready , + + output [1:0] s_axi_bresp , + output s_axi_bvalid , + input s_axi_bready , + + input [7:0] s_axi_araddr , + input [2:0] s_axi_arprot , + input s_axi_arvalid , + output s_axi_arready , + + output [31:0] s_axi_rdata , + output [1:0] s_axi_rresp , + output s_axi_rvalid , + input s_axi_rready , + + // s_* and m_* reset/clock. + input aresetn , + input aclk , + + // S_AXIS for input samples + input s_axis_tvalid , + input [4*32-1:0] s_axis_tdata , + + // M_AXIS for CH0 output. + output m0_axis_tvalid , + output [31:0] m0_axis_tdata , + + // M_AXIS for CH1 output. + output m1_axis_tvalid , + output [31:0] m1_axis_tdata , + + // M_AXIS for CH2 output. + output m2_axis_tvalid , + output [31:0] m2_axis_tdata , + + // M_AXIS for CH3 output. + output m3_axis_tvalid , + output [31:0] m3_axis_tdata , + + // M_AXIS for CH4 output. + output m4_axis_tvalid , + output [31:0] m4_axis_tdata , + + // M_AXIS for CH5 output. + output m5_axis_tvalid , + output [31:0] m5_axis_tdata , + + // M_AXIS for CH6 output. + output m6_axis_tvalid , + output [31:0] m6_axis_tdata , + + // M_AXIS for CH7 output. + output m7_axis_tvalid , + output [31:0] m7_axis_tdata + ); + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [15:0] ID0_REG ; +wire [15:0] ID1_REG ; +wire [15:0] ID2_REG ; +wire [15:0] ID3_REG ; +wire [15:0] ID4_REG ; +wire [15:0] ID5_REG ; +wire [15:0] ID6_REG ; +wire [15:0] ID7_REG ; +wire [31:0] PINC0_REG ; +wire [31:0] POFF0_REG ; +wire [31:0] PINC1_REG ; +wire [31:0] POFF1_REG ; +wire [31:0] PINC2_REG ; +wire [31:0] POFF2_REG ; +wire [31:0] PINC3_REG ; +wire [31:0] POFF3_REG ; +wire [31:0] PINC4_REG ; +wire [31:0] POFF4_REG ; +wire [31:0] PINC5_REG ; +wire [31:0] POFF5_REG ; +wire [31:0] PINC6_REG ; +wire [31:0] POFF6_REG ; +wire [31:0] PINC7_REG ; +wire [31:0] POFF7_REG ; + +// Internal valid. +wire valid_int ; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + + // Write Address Channel. + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_awready (s_axi_awready ), + + // Write Data Channel. + .s_axi_wdata (s_axi_wdata ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + .s_axi_wready (s_axi_wready ), + + // Write Response Channel. + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_bready (s_axi_bready ), + + // Read Address Channel. + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_arready (s_axi_arready ), + + // Read Data Channel. + .s_axi_rdata (s_axi_rdata ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_rready (s_axi_rready ), + + // Registers. + .ID0_REG (ID0_REG ), + .ID1_REG (ID1_REG ), + .ID2_REG (ID2_REG ), + .ID3_REG (ID3_REG ), + .ID4_REG (ID4_REG ), + .ID5_REG (ID5_REG ), + .ID6_REG (ID6_REG ), + .ID7_REG (ID7_REG ), + .PINC0_REG (PINC0_REG ), + .POFF0_REG (POFF0_REG ), + .PINC1_REG (PINC1_REG ), + .POFF1_REG (POFF1_REG ), + .PINC2_REG (PINC2_REG ), + .POFF2_REG (POFF2_REG ), + .PINC3_REG (PINC3_REG ), + .POFF3_REG (POFF3_REG ), + .PINC4_REG (PINC4_REG ), + .POFF4_REG (POFF4_REG ), + .PINC5_REG (PINC5_REG ), + .POFF5_REG (POFF5_REG ), + .PINC6_REG (PINC6_REG ), + .POFF6_REG (POFF6_REG ), + .PINC7_REG (PINC7_REG ), + .POFF7_REG (POFF7_REG ) + ); + +// PFB with DDS product. +pfb_readout + #( + // Number of channels. + .N(N), + + // Number of Lanes (Input). + .L(4) + ) + pfb_readout_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input data. + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for output data. + .m_axis_tvalid (valid_int ), + .m0_axis_tdata (m0_axis_tdata ), + .m1_axis_tdata (m1_axis_tdata ), + .m2_axis_tdata (m2_axis_tdata ), + .m3_axis_tdata (m3_axis_tdata ), + .m4_axis_tdata (m4_axis_tdata ), + .m5_axis_tdata (m5_axis_tdata ), + .m6_axis_tdata (m6_axis_tdata ), + .m7_axis_tdata (m7_axis_tdata ), + + // Registers. + .ID0_REG (ID0_REG ), + .ID1_REG (ID1_REG ), + .ID2_REG (ID2_REG ), + .ID3_REG (ID3_REG ), + .ID4_REG (ID4_REG ), + .ID5_REG (ID5_REG ), + .ID6_REG (ID6_REG ), + .ID7_REG (ID7_REG ), + .PINC0_REG (PINC0_REG ), + .POFF0_REG (POFF0_REG ), + .PINC1_REG (PINC1_REG ), + .POFF1_REG (POFF1_REG ), + .PINC2_REG (PINC2_REG ), + .POFF2_REG (POFF2_REG ), + .PINC3_REG (PINC3_REG ), + .POFF3_REG (POFF3_REG ), + .PINC4_REG (PINC4_REG ), + .POFF4_REG (POFF4_REG ), + .PINC5_REG (PINC5_REG ), + .POFF5_REG (POFF5_REG ), + .PINC6_REG (PINC6_REG ), + .POFF6_REG (POFF6_REG ), + .PINC7_REG (PINC7_REG ), + .POFF7_REG (POFF7_REG ) + ); + +// Assign outputs. +assign m0_axis_tvalid = valid_int; +assign m1_axis_tvalid = valid_int; +assign m2_axis_tvalid = valid_int; +assign m3_axis_tvalid = valid_int; +assign m4_axis_tvalid = valid_int; +assign m5_axis_tvalid = valid_int; +assign m6_axis_tvalid = valid_int; +assign m7_axis_tvalid = valid_int; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v4/src/dds/cmult_16x16.v b/firmware/ip/axis_pfb_readout_v4/src/dds/cmult_16x16.v new file mode 100644 index 0000000..c57b2ba --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/dds/cmult_16x16.v @@ -0,0 +1,46 @@ +module cmult_16x16 + ( + input wire clk , + input wire [15:0] din_i0 , + input wire [15:0] din_q0 , + input wire [15:0] din_i1 , + input wire [15:0] din_q1 , + output wire [31:0] dout_i , + output wire [31:0] dout_q + ); + +/****************/ +/* Architecture */ +/****************/ + +// Real part. +cmult_sub + #( + .op("sub") + ) + cmult_real_i + ( + .clk (clk ), + .a (din_i0 ), + .b (din_i1 ), + .c (din_q0 ), + .d (din_q1 ), + .x (dout_i ) + ); + +// Imaginary part. +cmult_sub + #( + .op("add") + ) + cmult_imag_i + ( + .clk (clk ), + .a (din_i0 ), + .b (din_q1 ), + .c (din_q0 ), + .d (din_i1 ), + .x (dout_q ) + ); + +endmodule diff --git a/firmware/ip/axis_pfb_readout_v4/src/dds/cmult_sub.v b/firmware/ip/axis_pfb_readout_v4/src/dds/cmult_sub.v new file mode 100644 index 0000000..8b4ffe6 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/dds/cmult_sub.v @@ -0,0 +1,82 @@ +module cmult_sub + #( + parameter op = "sub" + ) + ( + input wire clk , + input wire [15:0] a , + input wire [15:0] b , + input wire [15:0] c , + input wire [15:0] d , + output wire [31:0] x + ); + +/***********/ +/* Signals */ +/***********/ +// Input pipeline. +reg signed [15:0] a_r1; +reg signed [15:0] b_r1; +reg signed [15:0] c_r1; +reg signed [15:0] c_r2; +reg signed [15:0] d_r1; +reg signed [15:0] d_r2; + +// Partial products. +wire signed [31:0] ab; +wire signed [31:0] cd; + +// Pipeline of partial products. +reg signed [31:0] ab_r1; +reg signed [31:0] ab_r2; +reg signed [31:0] cd_r1; + +// Combined result. +wire signed [31:0] res; + +// Pipelined result. +reg signed [31:0] res_r1; + +/****************/ +/* Architecture */ +/****************/ + +// Partial products. +assign ab = a_r1*b_r1; +assign cd = c_r2*d_r2; + +// Combined result. +generate + if (op == "sub") begin + assign res = ab_r2 - cd_r1; + end + else if (op == "add") begin + assign res = ab_r2 + cd_r1; + end +endgenerate + +// Registers. +always @(posedge clk) begin + // Input pipeline. + a_r1 <= a; + b_r1 <= b; + c_r1 <= c; + c_r2 <= c_r1; + d_r1 <= d; + d_r2 <= d_r1; + + // Pipeline of partial products. + ab_r1 <= ab; + ab_r2 <= ab_r1; + cd_r1 <= cd; + + // Pipelined result. + res_r1 <= res; +end + +/***********/ +/* Outputs */ +/***********/ +assign x = res_r1; + +endmodule diff --git a/firmware/ip/axis_pfb_readout_v4/src/dds/dds_0/dds_0.xci b/firmware/ip/axis_pfb_readout_v4/src/dds/dds_0/dds_0.xci new file mode 100644 index 0000000..6ef4c7e --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/dds/dds_0/dds_0.xci @@ -0,0 +1,476 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 9 + 0 + 0 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 10 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 72 + 1 + 1 + zynquplus + Full_Range + 1 + dds_0 + Not_Required + 256 + Maximal + 0.06 + Coregen + false + false + false + false + 10 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + true + Auto + Twos_Complement + Speed + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 22 + TRUE + ../../../../../zcu216/test_pfb_v4/top/top.tmp/axis_pfb_readout_v4_v1_0_project/axis_pfb_readout_v4_v1_0_project.gen/sources_1/ip/dds_0 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/dds/dds_ctrl.sv b/firmware/ip/axis_pfb_readout_v4/src/dds/dds_ctrl.sv new file mode 100644 index 0000000..c3c02b3 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/dds/dds_ctrl.sv @@ -0,0 +1,110 @@ +/* + * DDS Control input: + * + * |----------|--------|----------|--------| + * | 71 .. 65 | 64 | 63 .. 32 | 31 .. 0| + * |----------|--------|----------|--------| + * | not used | resync | poff | pinc | + * |----------|--------|----------|--------| + * +*/ + +module dds_ctrl + ( + // Clock. + input wire aclk , + + // Enable input. + input wire en , + + // Output data. + output wire dout_valid , + output wire [71:0] dout , + + // Registers. + input wire [31:0] PINC_REG , + input wire [31:0] POFF_REG + ); + +/********************/ +/* Internal signals */ +/********************/ +// Time counter. +reg [31:0] cnt = 0; +reg [31:0] cnt_r1 = 0; + +// Registers. +reg [31:0] pinc_r1 = 0; +reg [31:0] pinc_r2 = 0; +reg [31:0] poff_r1 = 0; + +// Multiplier output (modulo arithmetic, keep lower bits). +wire [31:0] mult_int; + +// Final phase. +wire [31:0] poff_out; +reg [31:0] poff_out_r1; + +// Output control word. +wire [71:0] dds_ctrl_out; + +// latency for en. +wire en_la; + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// Final phase. +assign poff_out = poff_r1 + mult_int; + +// Output control word. +assign dds_ctrl_out = {7'b0000000,1'b1,poff_out_r1,pinc_r2}; + +// Multiplier: 32x32, unsigned, optimized for speed. +// Latency: 6. +(* keep_hierarchy = "true" *) mult_32x32 mult_i + ( + .clk (aclk ), + .din_a (pinc_r1 ), + .din_b (cnt_r1 ), + .dout (mult_int ) + ); + +// Latency for en (valid). +// Latency = 2 (cnt) + 6 (mult_32x32) + 1 (poff_out) = 9. +latency_reg + #( + .N(9), + .B(1) + ) + latency_reg_en_i + ( + .clk (aclk ), + .din (en ), + .dout (en_la ) + ); + + +// Registers. +always @(posedge aclk) begin + // Time counter. + if (en == 1'b1) + cnt <= cnt + 1; + cnt_r1 <= cnt; + + // Registers. + pinc_r1 <= PINC_REG; + pinc_r2 <= pinc_r1; + poff_r1 <= POFF_REG; + + // Final phase. + poff_out_r1 <= poff_out; +end + +// Assign outputs. +assign dout_valid = en_la ; +assign dout = dds_ctrl_out ; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v4/src/dds/dds_top.sv b/firmware/ip/axis_pfb_readout_v4/src/dds/dds_top.sv new file mode 100644 index 0000000..e2a7365 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/dds/dds_top.sv @@ -0,0 +1,68 @@ +module dds_top + ( + // Clock. + input wire aclk , + + // Input valid. + input wire din_valid , + + // Output data. + output wire dout_valid , + output wire [31:0] dout , + + // Registers. + input wire [31:0] PINC_REG , + input wire [31:0] POFF_REG + ); + +/********************/ +/* Internal signals */ +/********************/ + +// DDS control. +wire ctrl_dout_valid ; +wire [71:0] ctrl_dout ; + +// DDS. +wire dds_dout_valid ; +wire [31:0] dds_dout ; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// DDS control. +// Latency: 9. +dds_ctrl dds_ctrl_i + ( + // Clock. + .aclk (aclk ), + + // Enable input. + .en (din_valid ), + + // Output data. + .dout_valid (ctrl_dout_valid ), + .dout (ctrl_dout ), + + // Registers. + .PINC_REG (PINC_REG ), + .POFF_REG (POFF_REG ) + ); + +// DDS instance. +// Latency: 10. +dds_0 dds_i + ( + .aclk (aclk ), + .s_axis_phase_tvalid(ctrl_dout_valid ), + .s_axis_phase_tdata (ctrl_dout ), + .m_axis_data_tvalid (dds_dout_valid ), + .m_axis_data_tdata (dds_dout ) + ); + +// Assign outputs. +assign dout_valid = dds_dout_valid ; +assign dout = dds_dout ; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v4/src/dds/mult_32x32.v b/firmware/ip/axis_pfb_readout_v4/src/dds/mult_32x32.v new file mode 100644 index 0000000..f2edc2b --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/dds/mult_32x32.v @@ -0,0 +1,57 @@ +/* + * This multiplier is optimized for 32x32 unsigned, so both of the + * operands are wider than the 27 (or 26 for unsigned) and then + * 4 DSPs are used. Pipeline is such that full-speed is achieved. + * + * Optimal pipeline: 6. + * + */ +module mult_32x32 + ( + input wire clk , + input wire [31:0] din_a , + input wire [31:0] din_b , + output wire [63:0] dout + ); + +/***********/ +/* Signals */ +/***********/ +// Input pipeline. +reg [31:0] din_a_r1 ; +reg [31:0] din_b_r1 ; + +// Product. +wire [63:0] p ; + +// Output pipeline. +reg [63:0] p_r1 ; +reg [63:0] p_r2 ; +reg [63:0] p_r3 ; +reg [63:0] p_r4 ; +reg [63:0] p_r5 ; + +/****************/ +/* Architecture */ +/****************/ + +// Partial products. +assign p = din_a_r1*din_b_r1; + +// Registers. +always @(posedge clk) begin + // Input pipeline. + din_a_r1 <= din_a ; + din_b_r1 <= din_b ; + + // Output pipeline. + p_r1 <= p ; + p_r2 <= p_r1 ; + p_r3 <= p_r2 ; + p_r4 <= p_r3 ; + p_r5 <= p_r4 ; +end + +assign dout = p_r5; + +endmodule diff --git a/firmware/ip/axis_pfb_readout_v4/src/ddsprod.sv b/firmware/ip/axis_pfb_readout_v4/src/ddsprod.sv new file mode 100644 index 0000000..fd39b3d --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/ddsprod.sv @@ -0,0 +1,135 @@ +module ddsprod + ( + // Clock. + input wire aclk , + + // S_AXIS for input data. + input wire s_axis_tvalid , + input wire [31:0] s_axis_tdata , + + // M_AXIS for output data. + output wire m_axis_tvalid , + output wire [31:0] m_axis_tdata , + + // Registers. + input wire [31:0] PINC_REG , + input wire [31:0] POFF_REG + ); + +/********************/ +/* Internal signals */ +/********************/ +// Data input latency. +wire [31:0] din_la ; + +// DDS output. +wire dds_dout_valid ; +wire [31:0] dds_dout ; + +// Real/Imaginary parts of product. +wire [15:0] din_real ; +wire [15:0] din_imag ; +wire [15:0] dds_real ; +wire [15:0] dds_imag ; + +// Full-precision product output. +wire [31:0] prod_real ; +wire [31:0] prod_imag ; + +// Quantized product. +wire [15:0] prod_real_q ; +wire [15:0] prod_imag_q ; +wire [31:0] prod ; +reg [31:0] prod_r1 ; + +// Latency for output valid. +wire valid_la ; + + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// DDS block. +// Latency: 19. +dds_top dds_top_i + ( + // Clock. + .aclk (aclk ), + + // Input valid. + .din_valid (s_axis_tvalid ), + + // Output data. + .dout_valid (dds_dout_valid ), + .dout (dds_dout ), + + // Registers. + .PINC_REG , + .POFF_REG + ); + +// Latency for input data. +// Latency = 19 (dds top). +latency_reg + #( + .N(19), + .B(32) + ) + latency_reg_din_i + ( + .clk (aclk ), + .din (s_axis_tdata ), + .dout (din_la ) + ); + +// Real/Imaginary parts of product. +assign din_real = din_la [15:0] ; +assign din_imag = din_la [31:16] ; +assign dds_real = dds_dout [15:0] ; +assign dds_imag = dds_dout [31:16] ; + +// Full-speed, 16x16 complex product. +// Latency: 4. +cmult_16x16 cmult_i + ( + .clk (aclk ), + .din_i0 (din_real ), + .din_q0 (din_imag ), + .din_i1 (dds_real ), + .din_q1 (dds_imag ), + .dout_i (prod_real ), + .dout_q (prod_imag ) + ); + +// Quantized prodoct. +assign prod_real_q = prod_real [30 -: 16]; +assign prod_imag_q = prod_imag [30 -: 16]; +assign prod = {prod_imag_q, prod_real_q}; + +// Latency for output valid. +// Latency = 4 (cmult) + 1 (output register). +latency_reg + #( + .N(5), + .B(1) + ) + latency_reg_valid_i + ( + .clk (aclk ), + .din (dds_dout_valid ), + .dout (valid_la ) + ); + +// Registers. +always @(posedge aclk) begin + // Quantized product. + prod_r1 <= prod; +end + +// Assign outputs. +assign m_axis_tvalid = valid_la ; +assign m_axis_tdata = prod_r1 ; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v4/src/ddsprod_v.sv b/firmware/ip/axis_pfb_readout_v4/src/ddsprod_v.sv new file mode 100644 index 0000000..134eab8 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/ddsprod_v.sv @@ -0,0 +1,161 @@ +/* + * This block instantiates 4 ddsprod blocks to apply + * the dds product to 4 independent inputs, with 4 + * independent DDS blocks. + */ +module ddsprod_v + ( + // Clock. + input wire aclk , + + // S_AXIS for input data. + input wire s_axis_tvalid , + input wire [31:0] s0_axis_tdata , + input wire [31:0] s1_axis_tdata , + input wire [31:0] s2_axis_tdata , + input wire [31:0] s3_axis_tdata , + input wire [31:0] s4_axis_tdata , + input wire [31:0] s5_axis_tdata , + input wire [31:0] s6_axis_tdata , + input wire [31:0] s7_axis_tdata , + + // M_AXIS for output data. + output wire m_axis_tvalid , + output wire [31:0] m0_axis_tdata , + output wire [31:0] m1_axis_tdata , + output wire [31:0] m2_axis_tdata , + output wire [31:0] m3_axis_tdata , + output wire [31:0] m4_axis_tdata , + output wire [31:0] m5_axis_tdata , + output wire [31:0] m6_axis_tdata , + output wire [31:0] m7_axis_tdata , + + // Registers. + input wire [31:0] PINC0_REG , + input wire [31:0] POFF0_REG , + input wire [31:0] PINC1_REG , + input wire [31:0] POFF1_REG , + input wire [31:0] PINC2_REG , + input wire [31:0] POFF2_REG , + input wire [31:0] PINC3_REG , + input wire [31:0] POFF3_REG , + input wire [31:0] PINC4_REG , + input wire [31:0] POFF4_REG , + input wire [31:0] PINC5_REG , + input wire [31:0] POFF5_REG , + input wire [31:0] PINC6_REG , + input wire [31:0] POFF6_REG , + input wire [31:0] PINC7_REG , + input wire [31:0] POFF7_REG + ); + +/********************/ +/* Internal signals */ +/********************/ +// Number of inputs/outputs. +localparam N = 8; + +// Input valid. +reg vin_r ; + +// Output valid. +wire [N-1:0] vout_v ; +reg vout_r ; + +// Vectorized inputs. +wire [31:0] din_v [N] ; +reg [31:0] din_r [N] ; + +// Vectorized outputs. +wire [31:0] dout_v [N] ; +reg [31:0] dout_r [N] ; + +// Vectorized registers. +reg [31:0] pinc_v [N] ; +reg [31:0] poff_v [N] ; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Vectorized inputs. +assign din_v [0] = s0_axis_tdata ; +assign din_v [1] = s1_axis_tdata ; +assign din_v [2] = s2_axis_tdata ; +assign din_v [3] = s3_axis_tdata ; +assign din_v [4] = s4_axis_tdata ; +assign din_v [5] = s5_axis_tdata ; +assign din_v [6] = s6_axis_tdata ; +assign din_v [7] = s7_axis_tdata ; + +// Vectorized registers. +assign pinc_v [0] = PINC0_REG ; +assign pinc_v [1] = PINC1_REG ; +assign pinc_v [2] = PINC2_REG ; +assign pinc_v [3] = PINC3_REG ; +assign pinc_v [4] = PINC4_REG ; +assign pinc_v [5] = PINC5_REG ; +assign pinc_v [6] = PINC6_REG ; +assign pinc_v [7] = PINC7_REG ; +assign poff_v [0] = POFF0_REG ; +assign poff_v [1] = POFF1_REG ; +assign poff_v [2] = POFF2_REG ; +assign poff_v [3] = POFF3_REG ; +assign poff_v [4] = POFF4_REG ; +assign poff_v [5] = POFF5_REG ; +assign poff_v [6] = POFF6_REG ; +assign poff_v [7] = POFF7_REG ; + +genvar i; +generate + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/fifo/fifo_axi.vhd b/firmware/ip/axis_pfb_readout_v4/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/fifo/fifo_dc.vhd b/firmware/ip/axis_pfb_readout_v4/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_pfb_readout_v4/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_pfb_readout_v4/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/fifo/gray2bin.vhd b/firmware/ip/axis_pfb_readout_v4/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/fifo/rd2axi.vhd b/firmware/ip/axis_pfb_readout_v4/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_pfb_readout_v4/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/latency_reg.v b/firmware/ip/axis_pfb_readout_v4/src/latency_reg.v new file mode 100644 index 0000000..b18c039 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/latency_reg.v @@ -0,0 +1,53 @@ +module latency_reg + ( + clk , + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +reg [B-1:0] shift_r [0:N-1]; + +// Array initialization. +integer i; +initial begin + for (i=0; i '0'); + data_rr <= (others => '0'); + valid_r <= '0'; + valid_rr <= '0'; + + -- Counters. + cnt_nwait <= (others => '0'); + cnt <= (others => '0'); + else + -- State register. + current_state <= next_state; + + -- Pipeline registers. + data_r <= s_axis_tdata; + data_rr <= data_r; + valid_r <= valid_i; + valid_rr <= valid_r; + + -- Counters. + if ( rst_state = '1' ) then + cnt_nwait <= cnt_nwait + 1; + end if; + + if ( valid_i = '1' ) then + if ( cnt < to_unsigned(CYCLES-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + end if; + end if; + end if; + end if; +end process; + +-- Next state logic. +process (current_state, cnt_nwait, s_axis_tlast, cnt) +begin + case (current_state) is + when INIT_ST => + next_state <= RST_ST; + + when RST_ST => + if ( cnt_nwait < to_unsigned(NWAIT-1,cnt_nwait'length) ) then + next_state <= RST_ST; + else + next_state <= S0_ST; + end if; + + when S0_ST => + if ( s_axis_tlast = '1' ) then + -- Check if tlast is in the right position. + if ( cnt = to_unsigned(CYCLES-1,cnt'length) ) then + next_state <= S0_ST; + else + -- tlast in the wrong position. + next_state <= S1_ST; + end if; + else + next_state <= S0_ST; + end if; + + when S1_ST => + -- Wait until a frame is completed. + if ( cnt = to_unsigned(CYCLES-1,cnt'length) ) then + next_state <= S2_ST; + else + next_state <= S1_ST; + end if; + + when S2_ST => + -- Wait for the next tlast. + if ( s_axis_tlast = '1' ) then + next_state <= S0_ST; + else + next_state <= S2_ST; + end if; + + end case; +end process; + +-- Output logic. +process (current_state) +begin +rst_state <= '0'; +valid_i <= '0'; + case (current_state) is + when INIT_ST => + + when RST_ST => + rst_state <= '1'; + + when S0_ST => + valid_i <= '1'; + + when S1_ST => + valid_i <= '1'; + + when S2_ST => + + end case; +end process; + +-- Assign outputs. +tdata <= data_rr; +tvalid <= valid_rr; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/conv_pkg.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/conv_pkg.vhd new file mode 100644 index 0000000..b8f1a8f --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/conv_pkg.vhd @@ -0,0 +1,1922 @@ +--------------------------------------------------------------------- +-- +-- Package : conv_pkg +-- +-- Filename : conv_pkg.vhd +-- +-- Date : 8/16/99 +-- +-- Description : Package that defines constant values that is used in the +-- XBS and functions that convert one type to another. +-- +-- Note : This package uses a VHDL 93 constructs therefore when +-- compiling with ModelTech use: vcom -93 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package conv_pkg is + --------------------------------------------------------------------------- + -- Constant that tells whether we're simulating + --------------------------------------------------------------------------- + constant simulating : boolean := false + -- synthesis translate_off + or true + -- synthesis translate_on + ; + + --------------------------------------------------------------------------- + -- Constants for XBS + --------------------------------------------------------------------------- + -- Arithmetic types + constant xlUnsigned : integer := 1; + constant xlSigned : integer := 2; + constant xlFloat : integer := 3; + + -- Constants for Quantization and Overflow + constant xlWrap : integer := 1; + constant xlSaturate : integer := 2; + constant xlTruncate : integer := 1; + constant xlRound : integer := 2; + constant xlRoundBanker : integer := 3; + + -- Constants for xladdsub s-function + constant xlAddMode : integer := 1; + constant xlSubMode : integer := 2; + + --------------------------------------------------------------------------- + -- Black Box Attributes + --------------------------------------------------------------------------- + attribute black_box : boolean; -- for Synplicity (obsolete) + attribute syn_black_box : boolean; -- for Synplicity Version 6.0 + attribute fpga_dont_touch: string; -- for FPGA Express + attribute box_type : string; -- for XST + + --------------------------------------------------------------------------- + -- Attributes to keep clock enable signals + --------------------------------------------------------------------------- + attribute keep : string; + attribute syn_keep : boolean; + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type and vice versa + function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; + function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; + + -- convert a std_logic_vector to a signed type and vice versa + function std_logic_vector_to_signed(inp : std_logic_vector) return signed; + function signed_to_std_logic_vector(inp : signed) return std_logic_vector; + -- convert signed to unsigned and vice versa + function unsigned_to_signed(inp : unsigned) return signed; + function signed_to_unsigned(inp : signed) return unsigned; + -- Tests used in convert_type + function pos(inp : std_logic_vector; arith : INTEGER) return boolean; + function all_same(inp: std_logic_vector) return boolean; + function all_zeros(inp: std_logic_vector) return boolean; + function is_point_five(inp: std_logic_vector) return boolean; + function all_ones(inp: std_logic_vector) return boolean; + + + + -- Convert a fixed point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + -- slice a vector + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector; + + -- slice a signed + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned; + + -- slice a unsigned + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Quantization Functions + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + + -- Overflow functions + function max_signed(width : INTEGER) return std_logic_vector; + function min_signed(width : INTEGER) return std_logic_vector; + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) return std_logic_vector; + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + --------------------------------------------------------------------------- + -- Binary point alignment functions + --------------------------------------------------------------------------- + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; + + -- Returns the number of integer bits after alignment of fixed point num. + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector; + + -- Pad LSB with zeros + function pad_LSB(inp : std_logic_vector; new_width: integer) + return std_logic_vector; + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith : integer) + return std_logic_vector; + + -- Find the max & min integer. + function max(L, R: INTEGER) return INTEGER; + function min(L, R: INTEGER) return INTEGER; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean; + + -- convert a boolean into a signed + function boolean_to_signed (inp : boolean; width: integer) + return signed; + -- convert a boolean into an unsigned + function boolean_to_unsigned (inp : boolean; width: integer) + return unsigned; + -- convert a boolean into std_logic_vector + function boolean_to_vector (inp : boolean) + return std_logic_vector; + -- convert a std_logic into std_logic_vector + function std_logic_to_vector (inp : std_logic) + return std_logic_vector; + -- convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector; + + -- Convert std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer; + function std_logic_to_integer(constant inp : std_logic := '0') + return integer; + + -- Convert a binary string array element into a std_logic_vector + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector; + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector; + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector (inp : string; width : integer) + return std_logic_vector; + + -- Make a binary string that represents zero + function makeZeroBinStr (width : integer) return STRING; + + + --------------------------------------------------------------------------- + -- Debugging functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's (i.e., 0bXX.X) + function is_binary_string_invalid (inp : string) + return boolean; + -- Check for all U's (i.e., 0bUU.U) + function is_binary_string_undefined (inp : string) + return boolean; + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean; + + + -- convert a std_logic_vector to a real type and vice versa + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real; + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real; + + + -- convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector; + -- convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector; + + -- display_precision is the number of digits to display in ModelTech's + -- waveform viewer ( used in to_string(inp : real) ) + constant display_precision : integer := 20; + -- convert a real into a string type + function real_to_string (inp : real) return string; + + -- Check of 0b and the beginning of a string + function valid_bin_string(inp : string) return boolean; + + -- Convert a std_logic_vector to a binary string + function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; + -- Convert a std_logic to a binary string + function std_logic_to_bin_string(inp : std_logic) return string; + -- convert a std_logic_vector to a binary string and add a binary point + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string; + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string; + + -- convert a std_logic_vector value to a character + type stdlogic_to_char_t is array(std_logic) of character; + constant to_char : stdlogic_to_char_t := ( + 'U' => 'U', + 'X' => 'X', + '0' => '0', + '1' => '1', + 'Z' => 'Z', + 'W' => 'W', + 'L' => 'L', + 'H' => 'H', + '-' => '-'); + + -- synthesis translate_on + +end conv_pkg; + +package body conv_pkg is + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type + function std_logic_vector_to_unsigned(inp : std_logic_vector) + return unsigned + is + begin + return unsigned (inp); + end; + + -- convert an unsigend to a std_logic_vector + function unsigned_to_std_logic_vector(inp : unsigned) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert an std_logic_vector to a signed + function std_logic_vector_to_signed(inp : std_logic_vector) + return signed + is + begin + return signed (inp); + end; + + -- convert an std_logic_vector to a sigend + function signed_to_std_logic_vector(inp : signed) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert unsigned to signed + function unsigned_to_signed (inp : unsigned) + return signed + is + begin -- unsigned_to_signed + return signed(std_logic_vector(inp)); + end; + + + -- convert signed to unsigned + function signed_to_unsigned (inp : signed) + return unsigned + is + begin -- signed_to_unsigned + return unsigned(std_logic_vector(inp)); + end; + + -- Test if a number is positive + function pos(inp : std_logic_vector; arith : INTEGER) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := inp; + if arith = xlUnsigned then + return true; + else + if vec(width-1) = '0' then + return true; + else + return false; + end if; + end if; + + -- Error + return true; + end; + + function max_signed(width : INTEGER) + return std_logic_vector + is + variable ones : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + ones := (others => '1'); + result(width-1) := '0'; + result(width-2 downto 0) := ones; + return result; + end; + + function min_signed(width : INTEGER) + return std_logic_vector + is + variable zeros : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + zeros := (others => '0'); + result(width-1) := '1'; + result(width-2 downto 0) := zeros; + return result; + end; + + -- Check if all the bits are the same + function all_same(inp: std_logic_vector) return boolean + is + variable result: boolean; + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + begin + vec := inp; + result := true; + if width > 0 then + for i in 1 to width-1 loop + if vec(i) /= vec(0) then + result := false; + end if; + end loop; + end if; + return result; + end; + + + -- Check if a number is all zeros + function all_zeros(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable zero : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + zero := (others => '0'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Check if a number is point five + function is_point_five(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (width > 1) then + if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then + result := true; + else + result := false; + end if; + else + if (vec(width-1) = '1') then + result := true; + else + result := false; + end if; + end if; + + return result; + end; + + -- Check if a number is all ones + function all_ones(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable one : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + one := (others => '1'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then + result := true; + else + result := false; + end if; + return result; + end; + + + --------------------------------------------------------------------------- + -- Type conersion functions + --------------------------------------------------------------------------- + + + -- Calculate the width of the temp. full precision representation + function full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return integer + is + variable result : integer; + begin + result := old_width + 2; + return result; + end; + + -- Calculate the width of the temp. quantized representation + -- ASSUMES POSITIVE BIN_PT + function quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return integer + is + variable right_of_dp, left_of_dp, result : integer; + begin + + right_of_dp := max(new_bin_pt, old_bin_pt); + left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); + + result := (old_width + 2) + (new_bin_pt - old_bin_pt); + return result; + end; + + + + -- Convert one Fix point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector + is + constant fp_width : integer := + full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, new_width, + new_bin_pt, new_arith); + constant fp_bin_pt : integer := old_bin_pt; + constant fp_arith : integer := old_arith; + variable full_precision_result : std_logic_vector(fp_width-1 downto 0); + + constant q_width : integer := + quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith); + constant q_bin_pt : integer := new_bin_pt; + constant q_arith : integer := old_arith; + variable quantized_result : std_logic_vector(q_width-1 downto 0); + + variable result : std_logic_vector(new_width-1 downto 0); + begin + result := (others => '0'); + + full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, + fp_arith); + + -- Apply quantization functions. This will remove LSB bits. + if (quantization = xlRound) then + + quantized_result := round_towards_inf(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + elsif (quantization = xlRoundBanker) then + quantized_result := round_towards_even(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + else + quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, q_arith); + end if; + + + -- Apply overflow function. This will remove MSB bits. + if (overflow = xlSaturate) then + result := saturation_arith(quantized_result, q_width, q_bin_pt, + q_arith, new_width, new_bin_pt, new_arith); + else + result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, + new_width, new_bin_pt, new_arith); + end if; + + + return result; + end; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, new_width, + new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (new_width - new_bin_pt) + - (old_width - old_bin_pt); + -- Number of digits to add/subract to the right of the decimal point + constant right_of_dp : integer := (new_bin_pt - old_bin_pt); + + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable j : integer; + + begin + vec := inp; + for i in new_width-1 downto 0 loop + j := i - right_of_dp; + if ( j > old_width-1) then + -- Bits to the left of the decimal point + if (new_arith = xlUnsigned) then + -- If unsigned zero pad MSB + result(i) := '0'; + else + -- If signed, sign extend MSB + result(i) := vec(old_width-1); + end if; + elsif ( j >= 0) then + -- Copy bits from input + result(i) := vec(j); + else + -- zero pad LSB + result(i) := '0'; + end if; + end loop; + + return result; + end; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant q_width : integer := quotient'length; + constant f_width : integer := fraction'length; + constant vec_MSB : integer := q_width+f_width-1; + constant result_MSB : integer := q_width+fraction_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := ( quotient & fraction ); + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant inp_width : integer := inp'length; + constant vec_MSB : integer := inp_width-1; + constant result_MSB : integer := result_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := inp; + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + -- vector slice + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector + is + begin + return inp(upper downto lower); + end; + + -- signed slice + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- unsigned slice + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); + end; + + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); + end; + + function boolean_to_signed (inp : boolean; width : integer) + return signed + is + variable result : signed(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_unsigned (inp : boolean; width : integer) + return unsigned + is + variable result : unsigned(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_vector (inp : boolean) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function std_logic_to_vector (inp : std_logic) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result(0) := inp; + return result; + end; + + --------------------------------------------------------------------------- + -- Quantization Functions + --------------------------------------------------------------------------- + + -- Truncate LSB bits + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign Extent or zero extend if necessary + if new_arith = xlUnsigned then + result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); + else + result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + result := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + result := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + return result; + end; + + + -- Round towards infinity + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + if (new_arith = xlSigned) then + -- Roundeing logic for signed numbers + -- Example: + -- Fix(5,-2) = 101.11 (bin) -2.25 (dec) + -- Converted to: Fix(4,-1) = 101.1 (bin) -2.5 (dec) + -- Note: same algorithm used for unsigned numbers can't be used. + + -- 1st check the sign bit of the input to see if it is a positive + -- number + if (vec(old_width-1) = '0') then + one_or_zero(0) := '1'; + end if; + + -- 2nd check if digits being truncated are all zeros + -- (in example it is bit zero) + if (right_of_dp >= 2) and (right_of_dp <= old_width) then + if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then + one_or_zero(0) := '1'; + end if; + end if; + + -- 3rd check if the bit right before the truncation point is '1' + -- or '0' (in example it is bit one) + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if vec(right_of_dp-1) = '0' then + one_or_zero(0) := '0'; + end if; + else + -- No rounding to be performed + one_or_zero(0) := '0'; + end if; + else + -- For an unsigned number just check if the bit right before the + -- truncation point is '1' or '0' + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + one_or_zero(0) := vec(right_of_dp-1); + end if; + end if; + + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + -- Round towards even values + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + -- For the truncated bits just check if the bits after the + -- truncation point are 0.5 + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then + one_or_zero(0) := vec(right_of_dp-1); + else + one_or_zero(0) := vec(right_of_dp); + end if; + end if; + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + --------------------------------------------------------------------------- + -- Overflow Functions + --------------------------------------------------------------------------- + + -- Apply Saturation arithmetic. The new_bin_pt and old bin_pt should be + -- equal. The function chops bits off MSB bits. + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (old_width - old_bin_pt) - + (new_width - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable overflow : boolean; + begin + vec := inp; + overflow := true; + result := (others => '0'); + + ----------------------------------------------------------------------- + -- Check for cases when overflow does not occur + ----------------------------------------------------------------------- + + -- Output width is >= input width + if (new_width >= old_width) then + overflow := false; + end if; + + -- Case #1: + -- Both the input and output are signed and the bits that will + -- be truncated plus the sign bit are all the same + -- (i.e., number has been sign extended) + if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + -- Case #2: + -- If the input is converted to a unsigned from an signed then only + -- check the bits that will be truncated are all zero + if (old_arith = xlSigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + -- Check if input is positive + if (vec(new_width-1) = '0') then + overflow := false; + end if; + end if; + end if; + end if; + + -- Case #3: + -- Input is unsigned and the bits that will be truncated are all zero + if (old_arith = xlUnsigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + overflow := false; + end if; + end if; + end if; + + -- Case #4: + -- Input is unsigned but output signed and the bits that will be + -- truncated are all zero + if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + + if overflow then + -- Overflow occured + if new_arith = xlSigned then + -- Check sign bit and set to max signed or min signed value + if vec(old_width-1) = '0' then + result := max_signed(new_width); + else + result := min_signed(new_width); + end if; + else + -- Check sign bit and set to zero if negative + if ((old_arith = xlSigned) and vec(old_width-1) = '1') then + result := (others => '0'); + else + -- Set to max unsigned positive value + result := (others => '1'); + end if; + end if; + else + -- Overflow did not occur + + -- Check for case when input type is signed and output type + -- unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + -- if negative number set vec to zero + if (vec(old_width-1) = '1') then + vec := (others => '0'); + end if; + end if; + + if new_width <= old_width then + result := vec(new_width-1 downto 0); + else + -- Sign or zero extend number depending on arith of new number + if new_arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + end if; + end if; + + return result; + end; + + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + variable result_arith : integer; + begin + -- Check for case when input type is signed and output type unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + result_arith := xlSigned; + end if; + + result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); + + return result; + end; + + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is + begin + return max(a_bin_pt, b_bin_pt); + end; + + -- Returns the number of integer bits after alignment of fixed point num + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER is + begin + return max(a_width - a_bin_pt, b_width - b_bin_pt); + end; + + function pad_LSB(inp : std_logic_vector; new_width: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + -- Added for XST + constant pad_pos : integer := new_width - orig_width - 1; + + begin + vec := inp; + pos := new_width-1; + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pad_pos >= 0 then + for i in pad_pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + -- sign extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := vec(old_width-1); + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + -- zero extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := '0'; + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + begin + result(0) := inp; + for i in new_width-1 downto 1 loop + result(i) := '0'; + end loop; + + return result; + end; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + return result; + end; + + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + begin + vec := inp; + pos := new_width-1; + + if (arith = xlUnsigned) then + -- set MSB to zero + result(pos) := '0'; + pos := pos - 1; + else + -- sign extend + result(pos) := vec(orig_width-1); + pos := pos - 1; + end if; + + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pos >= 0 then + for i in pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector + is + variable vec : std_logic_vector(old_width-1 downto 0); + variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if delta > 0 then + padded_inp := pad_LSB(vec, old_width+delta); + + -- sign or zero extend zero padded input depending on arith type + result := extend_MSB(padded_inp, new_width, new_arith); + else + -- sign or zero extend input depending on arith type + result := extend_MSB(vec, new_width, new_arith); + end if; + + return result; + end; + + function max(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + function min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean is +-- constant NULL_Str : string := ""; + begin + if (left'length /= right'length) then + return false; + else + -- Check for NULL string + -- FPGA Express does not like empty strings +-- if (left'length = NULL_Str'length) or +-- (right'length = NULL_Str'length) then +-- return true; +-- end if; + test : for i in 1 to left'length loop + if left(i) /= right(i) then + return false; + end if; + end loop test; + return true; + end if; + end; + + + --------------------------------------------------------------------------- + -- Debugging and Simulation only functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's + function is_binary_string_invalid (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'X' ) then + result := true; + end if; + end loop; + return result; + end; + + -- Check for all U's + function is_binary_string_undefined (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'U' ) then + result := true; + end if; + end loop; + return result; + end; + + + + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + result := false; + for i in 0 to width-1 loop + if (vec(i) = 'U') or (vec(i) = 'X') then + result := true; + end if; + end loop; + return result; + end; + + -- Converts a std_logic_vector to a real + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real + is + variable vec : std_logic_vector(inp'length-1 downto 0); + variable result, shift_val, undefined_real : real; + variable neg_num : boolean; + begin + vec := inp; + result := 0.0; + neg_num := false; + if vec(inp'length-1) = '1' then + neg_num := true; + end if; + + for i in 0 to inp'length-1 loop + if vec(i) = 'U' or vec(i) = 'X' then + return undefined_real; + end if; + if arith = xlSigned then + if neg_num then + -- Perform 1's count if negative number + if vec(i) = '0' then + result := result + 2.0**i; + end if; + else + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + else + -- Unsigned numbers + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + end loop; + + if arith = xlSigned then + if neg_num then + -- Add one to 1's comp number to make 2's comp number + result := result + 1.0; + result := result * (-1.0); + end if; + end if; + -- Realign based on binary point + shift_val := 2.0**(-1*bin_pt); + result := result * shift_val; + return result; + end; + + -- This function is just for consistancy + -- bin_pt and arith not used. + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real + is + variable result : real := 0.0; + begin + if inp = '1' then + result := 1.0; + end if; + + if arith = xlSigned then + assert false + report "It doesn't make sense to convert a 1 bit number to a signed real."; + end if; + return result; + end; + + -- synthesis translate_on + -- Convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + begin + + if (arith = xlSigned) then + signed_val := to_signed(inp, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(inp, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- Convert an std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer + is + constant width : integer := inp'length; + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + variable result : integer; + begin + + if (arith = xlSigned) then + signed_val := std_logic_vector_to_signed(inp); + result := to_integer(signed_val); + else + unsigned_val := std_logic_vector_to_unsigned(inp); + result := to_integer(unsigned_val); + end if; + + return result; + end; + + function std_logic_to_integer(constant inp : std_logic := '0') + return integer + is + begin + if inp = '1' then + return 1; + else + return 0; + end if; + end; + + + function makeZeroBinStr (width : integer) return STRING is + variable result : string(1 to width+3); + begin + result(1) := '0'; + result(2) := 'b'; + for i in 3 to width+2 loop + result(i) := '0'; + end loop; -- i + result(width+3) := '.'; + + return result; + end; + + + + -- synthesis translate_off + -- Convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + begin + --result := to_std_logic_vector(real'value(inp), width, bin_pt, arith); + result := (others => '0'); + return result; + end; + + -- Convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector + is + variable real_val : real; + variable int_val : integer; + variable result : std_logic_vector(width-1 downto 0) := (others => '0'); + variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); + variable signed_val : signed(width-1 downto 0) := (others => '0'); + begin + + real_val := inp; + + -- Scale double and make it an integer + int_val := integer(real_val * 2.0**(bin_pt)); + + if (arith = xlSigned) then + signed_val := to_signed(int_val, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(int_val, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- synthesis translate_on + -- Check of 0b and the beginning of a string + function valid_bin_string (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + begin + vec := inp; + if (vec(1) = '0' and vec(2) = 'b') then + return true; + else + return false; + end if; + end; + + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector(inp: string; width : integer) + return std_logic_vector is + + constant strlen : integer := inp'LENGTH; + variable result : std_logic_vector(width-1 downto 0); + variable bitval : std_logic_vector((strlen*4)-1 downto 0); + variable posn : integer; + variable ch : character; + variable vec : string(1 to strlen); + begin + vec := inp; + + -- default value is zero + result := (others => '0'); + posn := (strlen*4)-1; + + for i in 1 to strlen loop + ch := vec(i); + case ch is + when '0' => bitval(posn downto posn-3) := "0000"; + when '1' => bitval(posn downto posn-3) := "0001"; + when '2' => bitval(posn downto posn-3) := "0010"; + when '3' => bitval(posn downto posn-3) := "0011"; + when '4' => bitval(posn downto posn-3) := "0100"; + when '5' => bitval(posn downto posn-3) := "0101"; + when '6' => bitval(posn downto posn-3) := "0110"; + when '7' => bitval(posn downto posn-3) := "0111"; + when '8' => bitval(posn downto posn-3) := "1000"; + when '9' => bitval(posn downto posn-3) := "1001"; + when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; + when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; + when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; + when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; + when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; + when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; + when others => bitval(posn downto posn-3) := "XXXX"; + -- synthesis translate_off + ASSERT false + REPORT "Invalid hex value" SEVERITY ERROR; + -- synthesis translate_on + end case; + posn := posn - 4; + end loop; + + if (width <= strlen*4) then + -- bitval larger than desired width + result := bitval(width-1 downto 0); + else + -- bitval smaller than desired width + -- MSB is padded with zeros since default value for result is all 0s + result((strlen*4)-1 downto 0) := bitval; + end if; + return result; + end; + + + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector + is + variable pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(inp'length-1 downto 0); + begin + vec := inp; + pos := inp'length-1; + -- Set default value + result := (others => '0'); + + for i in 1 to vec'length loop + -- synthesis translate_off + if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then + assert false + report "Input string is larger than output std_logic_vector. Truncating output."; + return result; + end if; + -- synthesis translate_on + + if vec(i) = '0' then + result(pos) := '0'; + pos := pos - 1; + end if; + if vec(i) = '1' then + result(pos) := '1'; + pos := pos - 1; + end if; + -- synthesis translate_off + if (vec(i) = 'X' or vec(i) = 'U') then + result(pos) := 'U'; + pos := pos - 1; + end if; + -- synthesis translate_on + end loop; + return result; + end; + + + -- Convert a binary string array element into a std_logic_vector + -- Example "0b000.0000000 0b001.0000000" + -- string_pos: 123456789111111111122222222 + -- 012345678901234567 + -- + -- "0b000.0000000" = inp(0) + -- "0b001.0000000" = inp(1) + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector + is + constant str_width : integer := width + 4; -- +4 for '0b' '.' & ' ' + constant inp_len : integer := inp'length; + constant num_elements : integer := (inp_len + 1)/str_width; + constant reverse_index : integer := (num_elements-1) - index; + + -- Calc position of desired str + variable left_pos : integer; + variable right_pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(width-1 downto 0); + begin + -- Can't pad input with a space (Synplicity crashes) + vec := inp; + + -- Set default value + result := (others => '0'); + + -- Special Case for string like "0b01.0" without extra ' ' after string + if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := 1; + right_pos := width + 3; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := (reverse_index * str_width) + 1; + right_pos := left_pos + width + 2; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + return result; + end; + -- synthesis translate_off + + -- + -- convert a std_logic_vector to a string + -- + function std_logic_vector_to_bin_string(inp : std_logic_vector) + return string + is + variable vec : std_logic_vector(1 to inp'length); + variable result : string(vec'range); + begin + vec := inp; + for i in vec'range loop + result(i) := to_char(vec(i)); + end loop; + return result; + end; + + -- + -- convert a std_logic to a string + -- + function std_logic_to_bin_string(inp : std_logic) + return string + is + variable result : string(1 to 3); + begin + -- Add 0b prefix + result(1) := '0'; + result(2) := 'b'; + result(3) := to_char(inp); + return result; + end; + + -- + -- convert a std_logic_vector to a string and add a binary point + -- + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string + is + variable width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable str_pos : integer; + variable result : string(1 to width+3); + begin + vec := inp; + -- Add 0b prefeix + str_pos := 1; + result(str_pos) := '0'; + str_pos := 2; + result(str_pos) := 'b'; + str_pos := 3; + for i in width-1 downto 0 loop + -- Insert decimal point + -- if i = (width - bin_pt + 1) then + if (((width+3) - bin_pt) = str_pos) then + result(str_pos) := '.'; + str_pos := str_pos + 1; + end if; + result(str_pos) := to_char(vec(i)); + str_pos := str_pos + 1; + end loop; + -- Add binary point at end of string when bin_pt = 0 + if (bin_pt = 0) then + result(str_pos) := '.'; + end if; + + return result; + end; + + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string + is + variable result : string(1 to width); + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := real_to_std_logic_vector(inp, width, bin_pt, arith); + result := std_logic_vector_to_bin_string(vec); + + return result; + end; + + + -- Convert a real to string + -- Note: the size of the string returned is 'display_precision' chars long + function real_to_string (inp : real) return string + is + variable result : string(1 to display_precision) := (others => ' '); + begin + result(real'image(inp)'range) := real'image(inp); + return result; + end; + + -- synthesis translate_on + + +end conv_pkg; + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/single_reg_w_init.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/single_reg_w_init.vhd new file mode 100644 index 0000000..26af1d6 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/single_reg_w_init.vhd @@ -0,0 +1,109 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : single_reg_w_init.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg_w_init.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity single_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end single_reg_w_init; + +architecture structural of single_reg_w_init is + function build_init_const(width: integer; + init_index: integer; + init_value: bit_vector) + return std_logic_vector + is + variable result: std_logic_vector(width - 1 downto 0); + begin + if init_index = 0 then + result := (others => '0'); + elsif init_index = 1 then + result := (others => '0'); + result(0) := '1'; + else + result := to_stdlogicvector(init_value); + end if; + return result; + end; + + component fdre + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + r: in std_ulogic + ); + end component; -- end fdre + attribute syn_black_box of fdre: component is true; + attribute fpga_dont_touch of fdre: component is "true"; + + component fdse + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + s: in std_ulogic + ); + end component; -- end fdse + attribute syn_black_box of fdse: component is true; + attribute fpga_dont_touch of fdse: component is "true"; + + constant init_const: std_logic_vector(width - 1 downto 0) + := build_init_const(width, init_index, init_value); +begin + fd_prim_array: for index in 0 to width - 1 generate + + bit_is_0: if (init_const(index) = '0') generate + fdre_comp: fdre + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + r => clr + ); + end generate; -- end bit_is_0 + + bit_is_1: if (init_const(index) = '1') generate + fdse_comp: fdse + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + s => clr + ); + end generate; -- end bit_is_1 + end generate; -- end fd_prim_array +end architecture structural; + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/srl17e.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/srl17e.vhd new file mode 100644 index 0000000..8ec9c8d --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/srl17e.vhd @@ -0,0 +1,93 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srl17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srl17e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srl17e; + +architecture structural of srl17e is + + component SRL16E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRL16E : component is true; + attribute fpga_dont_touch of SRL16E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srl16_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srl16_used: if latency > 1 generate + u1 : srl16e port map(clk => clk, + d => d_delayed(i), + q => srl16_out(i), + ce => ce, + a0 => a(0), + a1 => a(1), + a2 => a(2), + a3 => a(3)); + end generate; + srl16_not_used: if latency <= 1 generate + srl16_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srl16_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srl16_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/srl33e.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/srl33e.vhd new file mode 100644 index 0000000..c943462 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/srl33e.vhd @@ -0,0 +1,87 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srlc17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srlc33e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srlc33e; + +architecture structural of srlc33e is + + component SRLC32E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A : in std_logic_vector(4 downto 0); + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRLC32E : component is true; + attribute fpga_dont_touch of SRLC32E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srlc32_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srlc32_used: if latency > 1 generate + u1 : srlc32e port map(clk => clk, + d => d_delayed(i), + q => srlc32_out(i), + ce => ce, + a => a); + end generate; + srlc32_not_used: if latency <= 1 generate + srlc32_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srlc32_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srlc32_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/ssr_8x64.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/ssr_8x64.vhd new file mode 100644 index 0000000..9828dff --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/ssr_8x64.vhd @@ -0,0 +1,2133 @@ +-- Generated from Simulink block ssr_8x64/Vector FFT/Scalar2Vector +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_scalar2vector is + port ( + i : in std_logic_vector( 432-1 downto 0 ); + o_1 : out std_logic_vector( 54-1 downto 0 ); + o_2 : out std_logic_vector( 54-1 downto 0 ); + o_3 : out std_logic_vector( 54-1 downto 0 ); + o_4 : out std_logic_vector( 54-1 downto 0 ); + o_5 : out std_logic_vector( 54-1 downto 0 ); + o_6 : out std_logic_vector( 54-1 downto 0 ); + o_7 : out std_logic_vector( 54-1 downto 0 ); + o_8 : out std_logic_vector( 54-1 downto 0 ) + ); +end ssr_8x64_scalar2vector; +architecture structural of ssr_8x64_scalar2vector is + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); +begin + o_1 <= slice0_y_net; + o_2 <= slice1_y_net; + o_3 <= slice2_y_net; + o_4 <= slice3_y_net; + o_5 <= slice4_y_net; + o_6 <= slice5_y_net; + o_7 <= slice6_y_net; + o_8 <= slice7_y_net; + test_systolicfft_vhdl_black_box_o_net <= i; + slice0 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 53, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice0_y_net + ); + slice1 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 54, + new_msb => 107, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice1_y_net + ); + slice2 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 108, + new_msb => 161, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice2_y_net + ); + slice3 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 162, + new_msb => 215, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice3_y_net + ); + slice4 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 216, + new_msb => 269, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice4_y_net + ); + slice5 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 270, + new_msb => 323, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice5_y_net + ); + slice6 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 324, + new_msb => 377, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice6_y_net + ); + slice7 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 378, + new_msb => 431, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Concat +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_concat is + port ( + hi_1 : in std_logic_vector( 16-1 downto 0 ); + lo_1 : in std_logic_vector( 16-1 downto 0 ); + hi_2 : in std_logic_vector( 16-1 downto 0 ); + hi_3 : in std_logic_vector( 16-1 downto 0 ); + hi_4 : in std_logic_vector( 16-1 downto 0 ); + hi_5 : in std_logic_vector( 16-1 downto 0 ); + hi_6 : in std_logic_vector( 16-1 downto 0 ); + hi_7 : in std_logic_vector( 16-1 downto 0 ); + hi_8 : in std_logic_vector( 16-1 downto 0 ); + lo_2 : in std_logic_vector( 16-1 downto 0 ); + lo_3 : in std_logic_vector( 16-1 downto 0 ); + lo_4 : in std_logic_vector( 16-1 downto 0 ); + lo_5 : in std_logic_vector( 16-1 downto 0 ); + lo_6 : in std_logic_vector( 16-1 downto 0 ); + lo_7 : in std_logic_vector( 16-1 downto 0 ); + lo_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 32-1 downto 0 ); + out_2 : out std_logic_vector( 32-1 downto 0 ); + out_3 : out std_logic_vector( 32-1 downto 0 ); + out_4 : out std_logic_vector( 32-1 downto 0 ); + out_5 : out std_logic_vector( 32-1 downto 0 ); + out_6 : out std_logic_vector( 32-1 downto 0 ); + out_7 : out std_logic_vector( 32-1 downto 0 ); + out_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x64_vector_concat; +architecture structural of ssr_8x64_vector_concat is + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= concat0_y_net; + out_2 <= concat1_y_net; + out_3 <= concat2_y_net; + out_4 <= concat3_y_net; + out_5 <= concat4_y_net; + out_6 <= concat5_y_net; + out_7 <= concat6_y_net; + out_8 <= concat7_y_net; + reinterpret0_output_port_net_x0 <= hi_1; + reinterpret0_output_port_net <= lo_1; + reinterpret1_output_port_net_x0 <= hi_2; + reinterpret2_output_port_net_x0 <= hi_3; + reinterpret3_output_port_net_x0 <= hi_4; + reinterpret4_output_port_net_x0 <= hi_5; + reinterpret5_output_port_net_x0 <= hi_6; + reinterpret6_output_port_net_x0 <= hi_7; + reinterpret7_output_port_net_x0 <= hi_8; + reinterpret1_output_port_net <= lo_2; + reinterpret2_output_port_net <= lo_3; + reinterpret3_output_port_net <= lo_4; + reinterpret4_output_port_net <= lo_5; + reinterpret5_output_port_net <= lo_6; + reinterpret6_output_port_net <= lo_7; + reinterpret7_output_port_net <= lo_8; + concat0 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret0_output_port_net_x0, + in1 => reinterpret0_output_port_net, + y => concat0_y_net + ); + concat1 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret1_output_port_net_x0, + in1 => reinterpret1_output_port_net, + y => concat1_y_net + ); + concat2 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret2_output_port_net_x0, + in1 => reinterpret2_output_port_net, + y => concat2_y_net + ); + concat3 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret3_output_port_net_x0, + in1 => reinterpret3_output_port_net, + y => concat3_y_net + ); + concat4 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret4_output_port_net_x0, + in1 => reinterpret4_output_port_net, + y => concat4_y_net + ); + concat5 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret5_output_port_net_x0, + in1 => reinterpret5_output_port_net, + y => concat5_y_net + ); + concat6 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret6_output_port_net_x0, + in1 => reinterpret6_output_port_net, + y => concat6_y_net + ); + concat7 : entity xil_defaultlib.sysgen_concat_384683215a + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret7_output_port_net_x0, + in1 => reinterpret7_output_port_net, + y => concat7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Delay +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_delay is + port ( + d_1 : in std_logic_vector( 32-1 downto 0 ); + d_2 : in std_logic_vector( 32-1 downto 0 ); + d_3 : in std_logic_vector( 32-1 downto 0 ); + d_4 : in std_logic_vector( 32-1 downto 0 ); + d_5 : in std_logic_vector( 32-1 downto 0 ); + d_6 : in std_logic_vector( 32-1 downto 0 ); + d_7 : in std_logic_vector( 32-1 downto 0 ); + d_8 : in std_logic_vector( 32-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + q_1 : out std_logic_vector( 32-1 downto 0 ); + q_2 : out std_logic_vector( 32-1 downto 0 ); + q_3 : out std_logic_vector( 32-1 downto 0 ); + q_4 : out std_logic_vector( 32-1 downto 0 ); + q_5 : out std_logic_vector( 32-1 downto 0 ); + q_6 : out std_logic_vector( 32-1 downto 0 ); + q_7 : out std_logic_vector( 32-1 downto 0 ); + q_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x64_vector_delay; +architecture structural of ssr_8x64_vector_delay is + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal clk_net : std_logic; + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal ce_net : std_logic; + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); +begin + q_1 <= delay0_q_net; + q_2 <= delay1_q_net; + q_3 <= delay2_q_net; + q_4 <= delay3_q_net; + q_5 <= delay4_q_net; + q_6 <= delay5_q_net; + q_7 <= delay6_q_net; + q_8 <= delay7_q_net; + concat0_y_net <= d_1; + concat1_y_net <= d_2; + concat2_y_net <= d_3; + concat3_y_net <= d_4; + concat4_y_net <= d_5; + concat5_y_net <= d_6; + concat6_y_net <= d_7; + concat7_y_net <= d_8; + clk_net <= clk_1; + ce_net <= ce_1; + delay0 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat0_y_net, + clk => clk_net, + ce => ce_net, + q => delay0_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat1_y_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net + ); + delay2 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat2_y_net, + clk => clk_net, + ce => ce_net, + q => delay2_q_net + ); + delay3 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat3_y_net, + clk => clk_net, + ce => ce_net, + q => delay3_q_net + ); + delay4 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat4_y_net, + clk => clk_net, + ce => ce_net, + q => delay4_q_net + ); + delay5 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat5_y_net, + clk => clk_net, + ce => ce_net, + q => delay5_q_net + ); + delay6 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat6_y_net, + clk => clk_net, + ce => ce_net, + q => delay6_q_net + ); + delay7 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat7_y_net, + clk => clk_net, + ce => ce_net, + q => delay7_q_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Reinterpret +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_reinterpret is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x64_vector_reinterpret; +architecture structural of ssr_8x64_vector_reinterpret is + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_re_0_net <= in_1; + i_re_1_net <= in_2; + i_re_2_net <= in_3; + i_re_3_net <= in_4; + i_re_4_net <= in_5; + i_re_5_net <= in_6; + i_re_6_net <= in_7; + i_re_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Reinterpret1 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_reinterpret1 is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x64_vector_reinterpret1; +architecture structural of ssr_8x64_vector_reinterpret1 is + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_im_0_net <= in_1; + i_im_1_net <= in_2; + i_im_2_net <= in_3; + i_im_3_net <= in_4; + i_im_4_net <= in_5; + i_im_5_net <= in_6; + i_im_6_net <= in_7; + i_im_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_53c8e6f5a2 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Reinterpret2 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_reinterpret2 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_reinterpret2; +architecture structural of ssr_8x64_vector_reinterpret2 is + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Reinterpret3 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_reinterpret3 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_reinterpret3; +architecture structural of ssr_8x64_vector_reinterpret3 is + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_d7a483898b + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Slice Im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_slice_im is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_slice_im; +architecture structural of ssr_8x64_vector_slice_im is + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector Slice Re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_slice_re is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_slice_re; +architecture structural of ssr_8x64_vector_slice_re is + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x64_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT/Vector2Scalar +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector2scalar is + port ( + i_1 : in std_logic_vector( 32-1 downto 0 ); + i_2 : in std_logic_vector( 32-1 downto 0 ); + i_3 : in std_logic_vector( 32-1 downto 0 ); + i_4 : in std_logic_vector( 32-1 downto 0 ); + i_5 : in std_logic_vector( 32-1 downto 0 ); + i_6 : in std_logic_vector( 32-1 downto 0 ); + i_7 : in std_logic_vector( 32-1 downto 0 ); + i_8 : in std_logic_vector( 32-1 downto 0 ); + o : out std_logic_vector( 256-1 downto 0 ) + ); +end ssr_8x64_vector2scalar; +architecture structural of ssr_8x64_vector2scalar is + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); +begin + o <= concat1_y_net; + delay0_q_net <= i_1; + delay1_q_net <= i_2; + delay2_q_net <= i_3; + delay3_q_net <= i_4; + delay4_q_net <= i_5; + delay5_q_net <= i_6; + delay6_q_net <= i_7; + delay7_q_net <= i_8; + concat1 : entity xil_defaultlib.sysgen_concat_c0fcf025b9 + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => delay7_q_net, + in1 => delay6_q_net, + in2 => delay5_q_net, + in3 => delay4_q_net, + in4 => delay3_q_net, + in5 => delay2_q_net, + in6 => delay1_q_net, + in7 => delay0_q_net, + y => concat1_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/Vector FFT +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_vector_fft is + port ( + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + vi : in std_logic_vector( 1-1 downto 0 ); + si : in std_logic_vector( 6-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_8 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_8 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + vo : out std_logic; + so : out std_logic_vector( 6-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_8 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_vector_fft; +architecture structural of ssr_8x64_vector_fft is + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_vo_net : std_logic; + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 6-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal slice7_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_scale_net : std_logic_vector( 6-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal ce_net : std_logic; + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal slice1_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal clk_net : std_logic; + signal reinterpret6_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret2_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal concat1_y_net_x0 : std_logic_vector( 32-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay_q_net : std_logic_vector( 1-1 downto 0 ); + signal reinterpret4_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret6_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret7_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay1_q_net_x0 : std_logic_vector( 6-1 downto 0 ); + signal reinterpret7_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); +begin + o_re_1 <= reinterpret0_output_port_net_x0; + o_im_1 <= reinterpret0_output_port_net; + vo <= test_systolicfft_vhdl_black_box_vo_net; + so <= test_systolicfft_vhdl_black_box_so_net; + o_re_2 <= reinterpret1_output_port_net_x0; + o_re_3 <= reinterpret2_output_port_net_x0; + o_re_4 <= reinterpret3_output_port_net_x0; + o_re_5 <= reinterpret4_output_port_net_x0; + o_re_6 <= reinterpret5_output_port_net_x0; + o_re_7 <= reinterpret6_output_port_net_x0; + o_re_8 <= reinterpret7_output_port_net_x0; + o_im_2 <= reinterpret1_output_port_net; + o_im_3 <= reinterpret2_output_port_net; + o_im_4 <= reinterpret3_output_port_net; + o_im_5 <= reinterpret4_output_port_net; + o_im_6 <= reinterpret5_output_port_net; + o_im_7 <= reinterpret6_output_port_net; + o_im_8 <= reinterpret7_output_port_net; + i_re_0_net <= i_re_1; + i_im_0_net <= i_im_1; + i_valid_net <= vi; + i_scale_net <= si; + i_re_1_net <= i_re_2; + i_re_2_net <= i_re_3; + i_re_3_net <= i_re_4; + i_re_4_net <= i_re_5; + i_re_5_net <= i_re_6; + i_re_6_net <= i_re_7; + i_re_7_net <= i_re_8; + i_im_1_net <= i_im_2; + i_im_2_net <= i_im_3; + i_im_3_net <= i_im_4; + i_im_4_net <= i_im_5; + i_im_5_net <= i_im_6; + i_im_6_net <= i_im_7; + i_im_7_net <= i_im_8; + clk_net <= clk_1; + ce_net <= ce_1; + scalar2vector : entity xil_defaultlib.ssr_8x64_scalar2vector + port map ( + i => test_systolicfft_vhdl_black_box_o_net, + o_1 => slice0_y_net_x1, + o_2 => slice1_y_net_x1, + o_3 => slice2_y_net_x1, + o_4 => slice3_y_net_x1, + o_5 => slice4_y_net_x1, + o_6 => slice5_y_net_x1, + o_7 => slice6_y_net_x1, + o_8 => slice7_y_net_x1 + ); + vector_concat : entity xil_defaultlib.ssr_8x64_vector_concat + port map ( + hi_1 => reinterpret0_output_port_net_x1, + lo_1 => reinterpret0_output_port_net_x2, + hi_2 => reinterpret1_output_port_net_x1, + hi_3 => reinterpret2_output_port_net_x1, + hi_4 => reinterpret3_output_port_net_x1, + hi_5 => reinterpret4_output_port_net_x1, + hi_6 => reinterpret5_output_port_net_x1, + hi_7 => reinterpret6_output_port_net_x1, + hi_8 => reinterpret7_output_port_net_x1, + lo_2 => reinterpret1_output_port_net_x2, + lo_3 => reinterpret2_output_port_net_x2, + lo_4 => reinterpret3_output_port_net_x2, + lo_5 => reinterpret4_output_port_net_x2, + lo_6 => reinterpret5_output_port_net_x2, + lo_7 => reinterpret6_output_port_net_x2, + lo_8 => reinterpret7_output_port_net_x2, + out_1 => concat0_y_net, + out_2 => concat1_y_net_x0, + out_3 => concat2_y_net, + out_4 => concat3_y_net, + out_5 => concat4_y_net, + out_6 => concat5_y_net, + out_7 => concat6_y_net, + out_8 => concat7_y_net + ); + vector_delay : entity xil_defaultlib.ssr_8x64_vector_delay + port map ( + d_1 => concat0_y_net, + d_2 => concat1_y_net_x0, + d_3 => concat2_y_net, + d_4 => concat3_y_net, + d_5 => concat4_y_net, + d_6 => concat5_y_net, + d_7 => concat6_y_net, + d_8 => concat7_y_net, + clk_1 => clk_net, + ce_1 => ce_net, + q_1 => delay0_q_net, + q_2 => delay1_q_net, + q_3 => delay2_q_net, + q_4 => delay3_q_net, + q_5 => delay4_q_net, + q_6 => delay5_q_net, + q_7 => delay6_q_net, + q_8 => delay7_q_net + ); + vector_reinterpret : entity xil_defaultlib.ssr_8x64_vector_reinterpret + port map ( + in_1 => i_re_0_net, + in_2 => i_re_1_net, + in_3 => i_re_2_net, + in_4 => i_re_3_net, + in_5 => i_re_4_net, + in_6 => i_re_5_net, + in_7 => i_re_6_net, + in_8 => i_re_7_net, + out_1 => reinterpret0_output_port_net_x2, + out_2 => reinterpret1_output_port_net_x2, + out_3 => reinterpret2_output_port_net_x2, + out_4 => reinterpret3_output_port_net_x2, + out_5 => reinterpret4_output_port_net_x2, + out_6 => reinterpret5_output_port_net_x2, + out_7 => reinterpret6_output_port_net_x2, + out_8 => reinterpret7_output_port_net_x2 + ); + vector_reinterpret1 : entity xil_defaultlib.ssr_8x64_vector_reinterpret1 + port map ( + in_1 => i_im_0_net, + in_2 => i_im_1_net, + in_3 => i_im_2_net, + in_4 => i_im_3_net, + in_5 => i_im_4_net, + in_6 => i_im_5_net, + in_7 => i_im_6_net, + in_8 => i_im_7_net, + out_1 => reinterpret0_output_port_net_x1, + out_2 => reinterpret1_output_port_net_x1, + out_3 => reinterpret2_output_port_net_x1, + out_4 => reinterpret3_output_port_net_x1, + out_5 => reinterpret4_output_port_net_x1, + out_6 => reinterpret5_output_port_net_x1, + out_7 => reinterpret6_output_port_net_x1, + out_8 => reinterpret7_output_port_net_x1 + ); + vector_reinterpret2 : entity xil_defaultlib.ssr_8x64_vector_reinterpret2 + port map ( + in_1 => slice0_y_net, + in_2 => slice1_y_net, + in_3 => slice2_y_net, + in_4 => slice3_y_net, + in_5 => slice4_y_net, + in_6 => slice5_y_net, + in_7 => slice6_y_net, + in_8 => slice7_y_net, + out_1 => reinterpret0_output_port_net_x0, + out_2 => reinterpret1_output_port_net_x0, + out_3 => reinterpret2_output_port_net_x0, + out_4 => reinterpret3_output_port_net_x0, + out_5 => reinterpret4_output_port_net_x0, + out_6 => reinterpret5_output_port_net_x0, + out_7 => reinterpret6_output_port_net_x0, + out_8 => reinterpret7_output_port_net_x0 + ); + vector_reinterpret3 : entity xil_defaultlib.ssr_8x64_vector_reinterpret3 + port map ( + in_1 => slice0_y_net_x0, + in_2 => slice1_y_net_x0, + in_3 => slice2_y_net_x0, + in_4 => slice3_y_net_x0, + in_5 => slice4_y_net_x0, + in_6 => slice5_y_net_x0, + in_7 => slice6_y_net_x0, + in_8 => slice7_y_net_x0, + out_1 => reinterpret0_output_port_net, + out_2 => reinterpret1_output_port_net, + out_3 => reinterpret2_output_port_net, + out_4 => reinterpret3_output_port_net, + out_5 => reinterpret4_output_port_net, + out_6 => reinterpret5_output_port_net, + out_7 => reinterpret6_output_port_net, + out_8 => reinterpret7_output_port_net + ); + vector_slice_im : entity xil_defaultlib.ssr_8x64_vector_slice_im + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net_x0, + out_2 => slice1_y_net_x0, + out_3 => slice2_y_net_x0, + out_4 => slice3_y_net_x0, + out_5 => slice4_y_net_x0, + out_6 => slice5_y_net_x0, + out_7 => slice6_y_net_x0, + out_8 => slice7_y_net_x0 + ); + vector_slice_re : entity xil_defaultlib.ssr_8x64_vector_slice_re + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net, + out_2 => slice1_y_net, + out_3 => slice2_y_net, + out_4 => slice3_y_net, + out_5 => slice4_y_net, + out_6 => slice5_y_net, + out_7 => slice6_y_net, + out_8 => slice7_y_net + ); + vector2scalar : entity xil_defaultlib.ssr_8x64_vector2scalar + port map ( + i_1 => delay0_q_net, + i_2 => delay1_q_net, + i_3 => delay2_q_net, + i_4 => delay3_q_net, + i_5 => delay4_q_net, + i_6 => delay5_q_net, + i_7 => delay6_q_net, + i_8 => delay7_q_net, + o => concat1_y_net + ); + delay : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 1 + ) + port map ( + en => '1', + rst => '0', + d => i_valid_net, + clk => clk_net, + ce => ce_net, + q => delay_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x64_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 6 + ) + port map ( + en => '1', + rst => '0', + d => i_scale_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net_x0 + ); + test_systolicfft_vhdl_black_box : entity xil_defaultlib.WRAPPER_VECTOR_FFT_c5415935ecc00ff9eff39575a72e6e61 + generic map ( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 6, + N => 64, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map ( + i => concat1_y_net, + vi => delay_q_net(0), + si => delay1_q_net_x0, + CLK => clk_net, + CE => ce_net, + o => test_systolicfft_vhdl_black_box_o_net, + vo => test_systolicfft_vhdl_black_box_vo_net, + so => test_systolicfft_vhdl_black_box_so_net + ); +end structural; +-- Generated from Simulink block ssr_8x64/i_im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_i_im is + port ( + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x64_i_im; +architecture structural of ssr_8x64_i_im is + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); +begin + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; +end structural; +-- Generated from Simulink block ssr_8x64/i_re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_i_re is + port ( + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x64_i_re; +architecture structural of ssr_8x64_i_re is + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); +begin + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; +end structural; +-- Generated from Simulink block ssr_8x64_struct +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_struct is + port ( + i_scale : in std_logic_vector( 6-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_scale : out std_logic_vector( 6-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64_struct; +architecture structural of ssr_8x64_struct is + signal test_systolicfft_vhdl_black_box_vo_net : std_logic_vector( 1-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_scale_net : std_logic_vector( 6-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 6-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal ce_net : std_logic; + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal clk_net : std_logic; + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); +begin + i_scale_net <= i_scale; + i_valid_net <= i_valid; + o_scale <= test_systolicfft_vhdl_black_box_so_net; + o_valid <= test_systolicfft_vhdl_black_box_vo_net; + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; + o_im_0 <= reinterpret0_output_port_net; + o_im_1 <= reinterpret1_output_port_net; + o_im_2 <= reinterpret2_output_port_net; + o_im_3 <= reinterpret3_output_port_net; + o_im_4 <= reinterpret4_output_port_net_x0; + o_im_5 <= reinterpret5_output_port_net; + o_im_6 <= reinterpret6_output_port_net; + o_im_7 <= reinterpret7_output_port_net; + o_re_0 <= reinterpret0_output_port_net_x0; + o_re_1 <= reinterpret1_output_port_net_x0; + o_re_2 <= reinterpret2_output_port_net_x0; + o_re_3 <= reinterpret3_output_port_net_x0; + o_re_4 <= reinterpret4_output_port_net; + o_re_5 <= reinterpret5_output_port_net_x0; + o_re_6 <= reinterpret6_output_port_net_x0; + o_re_7 <= reinterpret7_output_port_net_x0; + clk_net <= clk_1; + ce_net <= ce_1; + vector_fft : entity xil_defaultlib.ssr_8x64_vector_fft + port map ( + i_re_1 => i_re_0_net, + i_im_1 => i_im_0_net, + vi => i_valid_net, + si => i_scale_net, + i_re_2 => i_re_1_net, + i_re_3 => i_re_2_net, + i_re_4 => i_re_3_net, + i_re_5 => i_re_4_net, + i_re_6 => i_re_5_net, + i_re_7 => i_re_6_net, + i_re_8 => i_re_7_net, + i_im_2 => i_im_1_net, + i_im_3 => i_im_2_net, + i_im_4 => i_im_3_net, + i_im_5 => i_im_4_net, + i_im_6 => i_im_5_net, + i_im_7 => i_im_6_net, + i_im_8 => i_im_7_net, + clk_1 => clk_net, + ce_1 => ce_net, + o_re_1 => reinterpret0_output_port_net_x0, + o_im_1 => reinterpret0_output_port_net, + vo => test_systolicfft_vhdl_black_box_vo_net(0), + so => test_systolicfft_vhdl_black_box_so_net, + o_re_2 => reinterpret1_output_port_net_x0, + o_re_3 => reinterpret2_output_port_net_x0, + o_re_4 => reinterpret3_output_port_net_x0, + o_re_5 => reinterpret4_output_port_net, + o_re_6 => reinterpret5_output_port_net_x0, + o_re_7 => reinterpret6_output_port_net_x0, + o_re_8 => reinterpret7_output_port_net_x0, + o_im_2 => reinterpret1_output_port_net, + o_im_3 => reinterpret2_output_port_net, + o_im_4 => reinterpret3_output_port_net, + o_im_5 => reinterpret4_output_port_net_x0, + o_im_6 => reinterpret5_output_port_net, + o_im_7 => reinterpret6_output_port_net, + o_im_8 => reinterpret7_output_port_net + ); + i_im : entity xil_defaultlib.ssr_8x64_i_im + port map ( + i_im_0 => i_im_0_net, + i_im_1 => i_im_1_net, + i_im_2 => i_im_2_net, + i_im_3 => i_im_3_net, + i_im_4 => i_im_4_net, + i_im_5 => i_im_5_net, + i_im_6 => i_im_6_net, + i_im_7 => i_im_7_net + ); + i_re : entity xil_defaultlib.ssr_8x64_i_re + port map ( + i_re_0 => i_re_0_net, + i_re_1 => i_re_1_net, + i_re_2 => i_re_2_net, + i_re_3 => i_re_3_net, + i_re_4 => i_re_4_net, + i_re_5 => i_re_5_net, + i_re_6 => i_re_6_net, + i_re_7 => i_re_7_net + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64_default_clock_driver is + port ( + ssr_8x64_sysclk : in std_logic; + ssr_8x64_sysce : in std_logic; + ssr_8x64_sysclr : in std_logic; + ssr_8x64_clk1 : out std_logic; + ssr_8x64_ce1 : out std_logic + ); +end ssr_8x64_default_clock_driver; +architecture structural of ssr_8x64_default_clock_driver is +begin + clockdriver : entity xil_defaultlib.xlclockdriver + generic map ( + period => 1, + log_2_period => 1 + ) + port map ( + sysclk => ssr_8x64_sysclk, + sysce => ssr_8x64_sysce, + sysclr => ssr_8x64_sysclr, + clk => ssr_8x64_clk1, + ce => ssr_8x64_ce1 + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x64 is + port ( + i_scale : in std_logic_vector( 6-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk : in std_logic; + o_scale : out std_logic_vector( 6-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x64; +architecture structural of ssr_8x64 is + attribute core_generation_info : string; + attribute core_generation_info of structural : architecture is "ssr_8x64,sysgen_core_2019_2,{,compilation=HDL Netlist,block_icon_display=Default,family=zynquplusRFSOC,part=xczu28dr,speed=-2-e,package=ffvg1517,synthesis_language=vhdl,hdl_library=xil_defaultlib,synthesis_strategy=Vivado Synthesis Defaults,implementation_strategy=Vivado Implementation Defaults,testbench=0,interface_doc=0,ce_clr=0,clock_period=10,system_simulink_period=1,waveform_viewer=0,axilite_interface=0,ip_catalog_plugin=0,hwcosim_burst_mode=0,simulation_time=10,blackbox2=1,concat=9,delay=10,reinterpret=32,slice=24,}"; + signal ce_1_net : std_logic; + signal clk_1_net : std_logic; +begin + ssr_8x64_default_clock_driver : entity xil_defaultlib.ssr_8x64_default_clock_driver + port map ( + ssr_8x64_sysclk => clk, + ssr_8x64_sysce => '1', + ssr_8x64_sysclr => '0', + ssr_8x64_clk1 => clk_1_net, + ssr_8x64_ce1 => ce_1_net + ); + ssr_8x64_struct : entity xil_defaultlib.ssr_8x64_struct + port map ( + i_scale => i_scale, + i_valid => i_valid, + i_im_0 => i_im_0, + i_im_1 => i_im_1, + i_im_2 => i_im_2, + i_im_3 => i_im_3, + i_im_4 => i_im_4, + i_im_5 => i_im_5, + i_im_6 => i_im_6, + i_im_7 => i_im_7, + i_re_0 => i_re_0, + i_re_1 => i_re_1, + i_re_2 => i_re_2, + i_re_3 => i_re_3, + i_re_4 => i_re_4, + i_re_5 => i_re_5, + i_re_6 => i_re_6, + i_re_7 => i_re_7, + clk_1 => clk_1_net, + ce_1 => ce_1_net, + o_scale => o_scale, + o_valid => o_valid, + o_im_0 => o_im_0, + o_im_1 => o_im_1, + o_im_2 => o_im_2, + o_im_3 => o_im_3, + o_im_4 => o_im_4, + o_im_5 => o_im_5, + o_im_6 => o_im_6, + o_im_7 => o_im_7, + o_re_0 => o_re_0, + o_re_1 => o_re_1, + o_re_2 => o_re_2, + o_re_3 => o_re_3, + o_re_4 => o_re_4, + o_re_5 => o_re_5, + o_re_6 => o_re_6, + o_re_7 => o_re_7 + ); +end structural; diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/ssr_8x64_entity_declarations.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/ssr_8x64_entity_declarations.vhd new file mode 100644 index 0000000..cccfea0 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/ssr_8x64_entity_declarations.vhd @@ -0,0 +1,6159 @@ +------------------------------------------------------------------- +-- System Generator version 2019.2 VHDL source file. +-- +-- Copyright(C) 2019 by Xilinx, Inc. All rights reserved. This +-- text/file contains proprietary, confidential information of Xilinx, +-- Inc., is distributed under license from Xilinx, Inc., and may be used, +-- copied and/or disclosed only pursuant to the terms of a valid license +-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use +-- this text/file solely for design, simulation, implementation and +-- creation of design files limited to Xilinx devices or technologies. +-- Use with non-Xilinx devices or technologies is expressly prohibited +-- and immediately terminates your license unless covered by a separate +-- agreement. +-- +-- Xilinx is providing this design, code, or information "as is" solely +-- for use in developing programs and solutions for Xilinx devices. By +-- providing this design, code, or information as one possible +-- implementation of this feature, application or standard, Xilinx is +-- making no representation that this implementation is free from any +-- claims of infringement. You are responsible for obtaining any rights +-- you may require for your implementation. Xilinx expressly disclaims +-- any warranty whatsoever with respect to the adequacy of the +-- implementation, including but not limited to warranties of +-- merchantability or fitness for a particular purpose. +-- +-- Xilinx products are not intended for use in life support appliances, +-- devices, or systems. Use in such applications is expressly prohibited. +-- +-- Any modifications that are made to the source code are done at the user's +-- sole risk and will be unsupported. +-- +-- This copyright and support notice must be retained as part of this +-- text at all times. (c) Copyright 1995-2019 Xilinx, Inc. All rights +-- reserved. +------------------------------------------------------------------- + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x64_xldelay is + generic(width : integer := -1; + latency : integer := -1; + reg_retiming : integer := 0; + reset : integer := 0); + port(d : in std_logic_vector (width-1 downto 0); + ce : in std_logic; + clk : in std_logic; + en : in std_logic; + rst : in std_logic; + q : out std_logic_vector (width-1 downto 0)); + +end ssr_8x64_xldelay; + +architecture behavior of ssr_8x64_xldelay is + component synth_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; -- end component synth_reg + + component synth_reg_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; + + signal internal_ce : std_logic; + +begin + internal_ce <= ce and en; + + srl_delay: if ((reg_retiming = 0) and (reset = 0)) or (latency < 1) generate + synth_reg_srl_inst : synth_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => '0', + clk => clk, + o => q); + end generate srl_delay; + + reg_delay: if ((reg_retiming = 1) or (reset = 1)) and (latency >= 1) generate + synth_reg_reg_inst : synth_reg_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => rst, + clk => clk, + o => q); + end generate reg_delay; +end architecture behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: COMPLEX_FIXED_PKG.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Package Name: COMPLEX_FIXED_PKG +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Unconstrained Size Vectors and Matrices of Complex Arbitrary Precision Fixed Point Numbers +-- +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +package COMPLEX_FIXED_PKG is + type BOOLEAN_VECTOR is array(NATURAL range <>) of BOOLEAN; + type INTEGER_VECTOR is array(NATURAL range <>) of INTEGER; + type REAL_VECTOR is array(NATURAL range <>) of REAL; +--2008 type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED; + type COMPLEX_VECTOR is array(INTEGER range <>) of COMPLEX; + + type SFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point signed number, like SIGNED but lower bound can be negative +--2008 type SFIXED_VECTOR is array(INTEGER range <>) of SFIXED; -- unconstrained array of SFIXED +--2008 type CFIXED is record RE,IM:SFIXED; end record; -- arbitrary precision fixed point complex signed number +--2008 type CFIXED_VECTOR is array(INTEGER range <>) of CFIXED; -- unconstrained array of CFIXED +--2008 type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR; -- unconstrained array of CFIXED_VECTOR + type SFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of SFIXED, vector size must be given by a separate generic + type CFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point complex signed number, CFIXED'low is always even and CFIXED'high is always odd + type CFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of CFIXED, vector size must be given by a separate generic + +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED; -- returns the CFIXED range for X(K) +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).RE +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).IM + + function MIN(A,B:INTEGER) return INTEGER; + function MIN(A,B,C:INTEGER) return INTEGER; + function MIN(A,B,C,D:INTEGER) return INTEGER; + function MED(A,B,C:INTEGER) return INTEGER; + function MAX(A,B:INTEGER) return INTEGER; + function MAX(A,B,C:INTEGER) return INTEGER; + function MAX(A,B,C,D:INTEGER) return INTEGER; + function "+"(X,Y:SFIXED) return SFIXED; -- full precision add with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X,Y:SFIXED) return SFIXED; -- full precision subtract with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X:SFIXED) return SFIXED; -- full precision negate with SFIXED(X'high+1 downto X'low) result + function "*"(X,Y:SFIXED) return SFIXED; -- full precision multiply with SFIXED(X'high+Y'high+1 downto X'low+Y'low) result + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED; -- multiply by 0 or 1 with SFIXED(X'high downto X'low) result + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED; -- resizes X and returns SFIXED(H downto L) + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED; -- resizes X to match HL and returns SFIXED(HL'high downto HL'low) + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high+N downto X'low+N) result + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED; -- returns SFIXED(H downto L) result + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED; -- returns SFIXED(HL'high downto HL'low) result + function TO_REAL(S:SFIXED) return REAL; -- returns REAL result +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED; -- returns element K out of an N-size array X + + function RE(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vRE(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure RE(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function IM(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vIM(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure IM(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function "+"(X,Y:CFIXED) return CFIXED; -- full precision add with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "-"(X,Y:CFIXED) return CFIXED; -- full precision subtract with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "*"(X,Y:CFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high+2 downto X'low+Y'low) result + function "*"(X:CFIXED;Y:SFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high downto X'low+Y'low) result + function "*"(X:SFIXED;Y:CFIXED) return CFIXED; + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED; -- resizes X and returns CFIXED(H downto L) + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED; -- resizes X to match HL and returns CFIXED(HL'high downto HL'low) + function PLUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function "-"(X:CFIXED) return CFIXED; -- full precision negate with CFIXED(X'high+2 downto X'low) result + function MINUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function SWAP(X:CFIXED) return CFIXED; -- returns CFIXED(X'high downto X'low) result + function CONJ(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high+N downto X'low+N) result + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED; -- returns CFIXED(H downto L) result + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED; -- returns CFIXED(HL'high downto HL'low) result + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED; -- returns CFIXED(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_CFIXED(R,I:SFIXED) return CFIXED; -- returns CFIXED(2*MAX(R'high,I'high)+1 downto 2*MIN(R'low,I'low)) result + function TO_COMPLEX(C:CFIXED) return COMPLEX; -- returns COMPLEX result + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR; -- returns CFIXED_VECTOR(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR; -- returns COMPLEX_VECTOR result + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR; -- returns R*C + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED; -- returns element K out of an N-size array X + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a variable, set element K out of an N-size array X to C + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a signal, set element K out of an N-size array X to C + + function LOG2(N:INTEGER) return INTEGER; -- returns ceil(log2(N)) +end COMPLEX_FIXED_PKG; + +package body COMPLEX_FIXED_PKG is +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED is -- returns the CFIXED range for X(K) +-- variable O:CFIXED(X'length/N*(K+1)-1+X'low/N downto X'length/N*K+X'low/N); +-- begin +-- return O; +-- end; + +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).RE +-- begin +-- return RE(ELEMENT(X,K,N)); +-- end; + +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).IM +-- begin +-- return IM(ELEMENT(X,K,N)); +-- end; + + function MIN(A,B:INTEGER) return INTEGER is + begin + if AB then + return A; + else + return B; + end if; + end; + + function MAX(A,B,C:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),C); + end; + + function MAX(A,B,C,D:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),MAX(C,D)); + end; + + function "+"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX+SY; -- SIGNED addition + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX-SY; -- SIGNED subtraction + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SR:SIGNED(X'high-X'low+1 downto 0); + variable R:SFIXED(X'high+1 downto X'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + SR:=-RESIZE(SX,SR'length); -- SIGNED negation + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X,Y:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SY:SIGNED(Y'high-Y'low downto 0); + variable SR:SIGNED(SX'high+SY'high+1 downto 0); + variable R:SFIXED(X'high+Y'high+1 downto X'low+Y'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + for K in SY'range loop + SY(K):=Y(Y'low+K); + end loop; + SR:=SX*SY; -- SIGNED multiplication + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED is + begin + if Y='1' then + return X; + else + return TO_SFIXED(0.0,X); + end if; + end; + + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED is + variable R:SFIXED(H downto L); + begin + for K in R'range loop + if KX'high then + R(K):=X(X'high); -- sign extend X MSBs + else + R(K):=X(K); + end if; + end loop; + return R; + end; + + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED is + begin + return RESIZE(X,HL'high,HL'low); + end; + + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high-N downto X'low-N); + begin + for K in R'range loop + R(K):=X(K+N); + end loop; + return R; + end; + + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high+N downto X'low+N); + begin + for K in R'range loop + R(K):=X(K-N); + end loop; + return R; + end; + + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED is + variable RR:REAL; + variable V:SFIXED(H downto L); + begin + assert (R<2.0**H) and (R>=-2.0**H) report "TO_SFIXED vector truncation!" severity warning; + if R<0.0 then + V(V'high):='1'; + RR:=R+2.0**V'high; + else + V(V'high):='0'; + RR:=R; + end if; + for K in V'high-1 downto V'low loop + if RR>=2.0**K then + V(K):='1'; + RR:=RR-2.0**K; + else + V(K):='0'; + end if; + end loop; + return V; + end; + + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED is + begin + return TO_SFIXED(R,HL'high,HL'low); + end; + + function TO_REAL(S:SFIXED) return REAL is + variable R:REAL; + begin + R:=0.0; + for K in S'range loop + if K=S'high then + if S(K)='1' then + R:=R-2.0**K; + end if; + else + if S(K)='1' then + R:=R+2.0**K; + end if; + end if; + end loop; + return R; + end; + +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED is -- X'low and X'length are always multiples of N +-- variable R:SFIXED(X'length/N-1+X'low/N downto X'low/N); +-- begin +-- R:=SFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); +-- return R; -- element K out of N of X +-- end; + + function RE(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(R'length-1+X'low downto X'low)); + return R; --lower half of X + end; + +-- procedure vRE(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low):=CFIXED(S); -- set lower half of X +-- end; + +-- procedure RE(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low)<=CFIXED(S); -- set lower half of X +-- end; + + function IM(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(X'high downto R'length+X'low)); + return R; --upper half of X + end; + +-- procedure vIM(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low):=CFIXED(S); -- set upper half of X +-- end; + +-- procedure IM(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low)<=CFIXED(S); -- set upper half of X +-- end; + + function "+"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+RE(Y),IM(X)+IM(Y)); + end; + + function "-"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-RE(Y),IM(X)-IM(Y)); + end; + + function "*"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*RE(Y)-IM(X)*IM(Y),RE(X)*IM(Y)+IM(X)*RE(Y)); + end; + + function "*"(X:CFIXED;Y:SFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*Y,IM(X)*Y); + end; + + function "*"(X:SFIXED;Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(X*RE(Y),X*IM(Y)); + end; + + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(RESIZE(RE(X),H,L),RESIZE(IM(X),H,L)); + end; + + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED is + begin + return RESIZE(X,HL'high/2,HL'low/2); + end; + + function PLUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-IM(X),RE(X)); + end; + + function "-"(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-RE(X),-IM(X)); + end; + + function MINUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),-RE(X)); + end; + + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-IM(Y)+RE(RND),IM(X)+RE(Y)+IM(RND)); + end; + + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+IM(Y)+RE(RND),IM(X)-RE(Y)+IM(RND)); + end; + + function SWAP(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),RE(X)); + end; + + function CONJ(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X),-IM(X)); + end; + + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_RIGHT(RE(X),N),SHIFT_RIGHT(IM(X),N)); + end; + + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_LEFT(RE(X),N),SHIFT_LEFT(IM(X),N)); + end; + + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(TO_SFIXED(R,H,L),TO_SFIXED(I,H,L)); + end; + + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(R,I,HL'high/2,HL'low/2); + end; + + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(C.RE,C.IM,HL); + end; + + function TO_CFIXED(R,I:SFIXED) return CFIXED is + constant H:INTEGER:=MAX(R'high,I'high); + constant L:INTEGER:=MIN(R'low,I'low); + variable C:CFIXED(2*H+1 downto 2*L); + begin + C:=CFIXED(RESIZE(I,H,L))&CFIXED(RESIZE(R,H,L)); + return C; -- I&R + end; + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED is -- X'low and X'length are always multiples of N + variable R:CFIXED(X'length/N-1+X'low/N downto X'low/N); + begin + R:=CFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); + return R; -- element K out of N of X + end; + + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low):=CFIXED_VECTOR(C); -- element K out of N of X + end; + + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low)<=CFIXED_VECTOR(C); -- element K out of N of X + end; + + function TO_COMPLEX(C:CFIXED) return COMPLEX is + variable R:COMPLEX; + begin + R.RE:=TO_REAL(RE(C)); + R.IM:=TO_REAL(IM(C)); + return R; + end; + + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR is + variable R:CFIXED_VECTOR(C'length*(HL'high+1)-1 downto C'length*HL'low); + begin + for K in C'range loop + R((K-C'low+1)*HL'length-1+R'low downto (K-C'low)*HL'length+R'low):=CFIXED_VECTOR(TO_CFIXED(C(K),HL)); + end loop; + return R; + end; + + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR is + variable R:COMPLEX_VECTOR(0 to N-1); + begin + for K in 0 to N-1 loop + R(K):=TO_COMPLEX(ELEMENT(C,K,N)); + end loop; + return R; + end; + + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR is + variable X:COMPLEX_VECTOR(C'range); + begin + for K in C'range loop + X(K):=R*C(K); + end loop; + return X; + end; + + function LOG2(N:INTEGER) return INTEGER is + variable TEMP:INTEGER; + variable RESULT:INTEGER; + begin + TEMP:=N; + RESULT:=0; + while TEMP>1 loop + RESULT:=RESULT+1; + TEMP:=(TEMP+1)/2; + end loop; + return RESULT; + end; +end COMPLEX_FIXED_PKG; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic BOOLEAN Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); +end BDELAY; + +architecture TEST of BDELAY is + attribute rloc:STRING; + + component BDELAY + generic(SIZE:INTEGER:=1); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); + end component; + +begin + l0:if SIZE=0 generate + begin + O<=I; + end generate l0; + -- end; + + l1:if SIZE=1 generate + signal iO:BOOLEAN:=FALSE; + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; + end generate l1; + -- end; + + l17: if SIZE>=2 and SIZE<18 generate + signal A:UNSIGNED(3 downto 0); + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + D<='1' when I else '0'; + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>D, + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l17; + -- end; + + l33: if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + D<='1' when I else '0'; + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>D, + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l33; + -- end; + + l257: if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.BDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + -- end; + end generate l257; + + ln: if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + type TUV is array(0 to SIZE-3) of UNSIGNED(0 downto 0); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(0 downto 0):=(others=>(others=>'0')); + signal MEM:TUV:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(0 downto 0):=(others=>'0'); + signal D,Q:UNSIGNED(0 downto 0); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + D<="1" when I else "0"; + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=D; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO="1"; + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: UDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: UDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic UNSIGNED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity UDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in UNSIGNED; + O:out UNSIGNED); +end UDELAY; + +architecture TEST of UDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin + assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=I; +-- end; + end generate; +-- elsif l1: SIZE=1 generate + l1:if SIZE=1 generate + signal iO:UNSIGNED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; +-- end; + end generate; +-- elsif l17: SIZE>=2 and SIZE<18 generate + l17:if SIZE>=2 and SIZE<18 generate + lk:for K in 0 to O'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l33: SIZE>=18 and SIZE<34 generate + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l257: SIZE>=34 and SIZE=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.UDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); +-- end; + end generate; +-- elsif ln: SIZE>=BRAM_THRESHOLD generate + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of UNSIGNED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO; + end if; + end process; +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic SFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity SDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in SFIXED; + O:out SFIXED); +end SDELAY; + +architecture TEST of SDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin +-- assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=RESIZE(I,O'high,O'low); + end generate l0; + --end; + + l1:if SIZE=1 generate + signal iO:SFIXED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=RESIZE(I,iO); + end if; + end process; + O<=iO; + end generate l1; + --end; + + l17:if SIZE>=2 and SIZE<18 generate +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); + begin + lk:for K in 0 to I'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l17; + --end; + + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- iO<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l33; + --end; + + l257:if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.SDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + --end; + end generate l257; + + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:SFIXED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of SFIXED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:SFIXED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=RESIZE(iO,O'high,O'low); + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic CFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CDELAY; + +architecture TEST of CDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; + signal IRE,IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); +begin + IRE<=RE(I); + IIM<=IM(I); + dr:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.RE); + I=>IRE, + O=>ORE); + di:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.IM); + I=>IIM, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CB.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CB +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Matrix Transposer (Corner Bender) Module Stage +-- It does an RxR matrix transposition where R=I'length +-- and each matrix element is a group of PACKING_FACTOR consecutive samples +-- LATENCY=(I'length-1)*PACKING_FACTOR+1 when I'length>1 or 0 when I'length=1 +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CB is + generic(SSR:INTEGER:=4; --93 + F:INTEGER:=0; + PACKING_FACTOR:INTEGER:=1; + INPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + OUTPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + SHORTEN_VO_BY:INTEGER:=0; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CB; + +architecture TEST of CB is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(LOG2(SSR)-1 downto 0); --93 local constrained UNSIGNED_VECTOR type + type iCFIXED_VECTOR is array(NATURAL range <>) of CFIXED((I'high+1)/SSR-1 downto I'low/SSR); --93 local constrained CFIXED_VECTOR type + + signal CNTP:UNSIGNED(LOG2(PACKING_FACTOR) downto 0):=(others=>'0'); + signal CNT:UNSIGNED(LOG2(SSR)-1 downto 0):=(others=>'0'); +--2008 signal A:UNSIGNED_VECTOR(0 to I'length):=(others=>(others=>'0')); +--2008 signal EN:BOOLEAN_VECTOR(0 to I'length):=(others=>FALSE); +--2008 signal DI:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal DO:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(0 to I'length-1=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).IM'range=>'0'))); + signal A:UNSIGNED_VECTOR(0 to SSR):=(others=>(others=>'0')); + signal EN:BOOLEAN_VECTOR(0 to SSR):=(others=>FALSE); + signal II,DI,OO:iCFIXED_VECTOR(0 to SSR-1); + signal DO:iCFIXED_VECTOR(0 to SSR-1):=(others=>(others=>'0')); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity error; + + f0:if F=0 generate + begin +--2008 i0:if I'length=1 generate + i0:if SSR=1 generate + O<=I; + VO<=VI; + SO<=SI; + end generate; +--2008 else generate +--2008 i1:if I'length>1 generate + i1:if SSR>1 generate + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if CNTP=PACKING_FACTOR-1 then + CNTP<=(others=>'0'); + CNT<=CNT+1; + else + CNTP<=CNTP+1; + end if; + else + CNTP<=(others=>'0'); + CNT<=(others=>'0'); + end if; + end if; + end process; + + A(0)<=CNT; + EN(0)<=CNTP=PACKING_FACTOR-1; +--2008 lk:for K in 0 to I'length-1 generate + lk:for K in 0 to SSR-1 generate + begin + II(K)<=CFIXED(I(I'length/SSR*(K+1)-1+I'low downto I'length/SSR*K+I'low)); --93 + i1:entity work.CDELAY generic map(SIZE=>K*(PACKING_FACTOR+INPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II(K), --93 I(I'low+K), + O=>DI(K)); + process(CLK) + begin + if rising_edge(CLK) then + DO(K)<=DI(TO_INTEGER(A(K))); + if EN(K) then + A(K+1)<=A(K); + end if; + end if; + end process; + bd:entity work.BDELAY generic map(SIZE=>PACKING_FACTOR) + port map(CLK=>CLK, + I=>EN(K), + O=>EN(K+1)); + o1:entity work.CDELAY generic map(SIZE=>(SSR-1-K)*(PACKING_FACTOR+OUTPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DO(K), + O=>OO(K)); --93 O(O'low+K)); + O(O'length/SSR*(K+1)-1+O'low downto O'length/SSR*K+O'low)<=CFIXED_VECTOR(OO(K)); --93 + end generate; + + bd:entity work.BDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY) + port map(CLK=>CLK, + I=>VI, + O=>VO); + + ud:entity work.UDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +-- end; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=SSR/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.CB generic map(SSR=>G, + F=>0, + PACKING_FACTOR=>PACKING_FACTOR, + INPUT_PACKING_FACTOR_ADJUST=>INPUT_PACKING_FACTOR_ADJUST, + OUTPUT_PACKING_FACTOR_ADJUST=>OUTPUT_PACKING_FACTOR_ADJUST, + SHORTEN_VO_BY=>SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Real Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BFS is + generic(PIPELINE:BOOLEAN:=TRUE; + SUB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SCALE:in STD_LOGIC; +-- P:out SIGNED); -- O=A±B + P:out SFIXED; -- O=A±B + OVR:out STD_LOGIC); +end BFS; + +architecture FAST of BFS is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH+1 downto SM-1); +-- signal S:SIGNED(SH+1 downto SL); + signal SA,SB:SFIXED(SH+1 downto SM-1); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM+1 downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1)/8*8+8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1)/8*8+7 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH+1 generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (((I0 and not I4) or (I2 and I4)) xor ((I1 and not I4) or (I3 and I4)))) or (not I5 and ((I1 and not I4) or (I3 and I4)))) + port map(I0=>SB(K-1),I1=>SA(K-1),I2=>SB(K),I3=>SA(K),I4=>SCALE,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM+1)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM+1); + end generate; + S(SH+1)<=O(O'high); + + ia:if A'low'0'); + signal iOVR:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + iOVR<=S(S'high) xor S(S'high-1); + end if; + end process; + P<=iP; + OVR<=iOVR; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CBFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CBFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Complex Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CBFS is -- O0=I0+I1, O1=I0-I1 + generic(ROUNDING:BOOLEAN:=TRUE; + PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC; + I0,I1:in CFIXED; + SCALE:in STD_LOGIC; + O0,O1:out CFIXED; + OVR:out STD_LOGIC); +end CBFS; + +architecture TEST of CBFS is + signal I0RE,I0IM,I1RE,I1IM:SFIXED(I0'high/2 downto I0'low/2); + signal O0RE,O0IM,O1RE,O1IM:SFIXED(O0'high/2 downto O0'low/2); + signal OVR4:STD_LOGIC_VECTOR(3 downto 0); +begin + I0RE<=RE(I0); + I0IM<=IM(I0); + I1RE<=RE(I1); + I1IM<=IM(I1); + + u0:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0RE=I0RE+I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O0RE, + OVR=>OVR4(0)); + + u1:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0IM=I0IM+I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O0IM, + OVR=>OVR4(1)); + + u2:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1RE=I0RE-I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O1RE, + OVR=>OVR4(2)); + + u3:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1IM=I0IM-I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O1IM, + OVR=>OVR4(3)); + + O0<=TO_CFIXED(O0RE,O0IM); + O1<=TO_CFIXED(O1RE,O1IM); + OVR<=OVR4(0) or OVR4(1) or OVR4(2) or OVR4(3); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CSA3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CSA3 +-- Purpose: Generic 3-input Add/Sub Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Carry Save 3-input Adder/Subtracter +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CSA3 is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + NEGATIVE_A:BOOLEAN:=FALSE; + NEGATIVE_B:BOOLEAN:=FALSE; + EXTRA_MSBs:INTEGER:=2); + port(CLK:in STD_LOGIC:='0'; +-- A,B,C:in SIGNED; -- if SIGNED, A, B, C and P must be LSB aligned + A,B,C:in SFIXED; -- if SFIXED, A, B, C and P can be any size + CY1,CY2:in BOOLEAN:=FALSE; -- the number of CYs TRUE must equal the number of negative A and B terms +-- P:out SIGNED); -- O=C±A±B + P:out SFIXED); -- O=C±A±B +end CSA3; + +architecture FAST of CSA3 is + constant SH:INTEGER:=MAX(A'high,B'high,C'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MED(A'low,B'low,C'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low,C'low); +-- signal SA,SB,SC,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB,SC:SFIXED(SH downto SM); + signal S:SFIXED(SH downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + SC<=RESIZE(C,SC); + O5(0)<='1' when CY1 else '0'; + CY(0)<='1' when CY2 else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_B))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_A))); + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (I1 xor I2 xor I3 xor I4)) or (not I5 and ((I2 and I3) or (I3 and I1) or (I1 and I2)))) + port map(I0=>'0',I1=>SC(K),I2=>SB(K),I3=>SA(K),I4=>O5(K-SM),I5=>'1',O5=>O5(K+1-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM); + end generate; + + ia:if (A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +--***************************************************************************** +-- © Copyright 2008 - 2018 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +--***************************************************************************** +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : v1.2 +-- \ \ Application : DSP48E2 generic wrapper +-- / / Filename : DSP48E2GW.vhd +-- /___/ /\ Date Last Modified : Oct 11 2017 +-- \ \ / \ Date Created : Nov 14 2014 +-- \___\/\___\ +-- +--Device : UltraScale and UltraScale+ +--Design Name : DSP48E2GW +--Purpose : DSP48E2 Generic Wrapper makes DSP48E2 primitive instantiation easier +--Reference : +--Revision History : v1.0 - original version +--Revision History : v1.1 - smart SFIXED resizing +--Revision History : v1.2 - fix for output resizing +--***************************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +--use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity DSP48E2GW is + generic(X,Y:INTEGER:=-1; + DSP48E:INTEGER:=2; -- use 1 for DSP48E1 and 2 for DSP48E2 + -- Feature Control Attributes: Data Path Selection + AMULTSEL:STRING:="A"; -- Selects A input to multiplier (A, AD) + A_INPUT:STRING:="DIRECT"; -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL:STRING:="B"; -- Selects B input to multiplier (AD, B) + B_INPUT:STRING:="DIRECT"; -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL:STRING:="A"; -- Selects input to preadder (A, B) + RND:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- Rounding Constant + USE_MULT:STRING:="MULTIPLY"; -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD:STRING:="ONE48"; -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR:STRING:="FALSE"; -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD:STRING:="XOR24_48_96"; -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET:STRING:="NO_RESET"; -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY:STRING:="RESET"; -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK:STD_LOGIC_VECTOR(47 downto 0):=X"3fffffffffff"; -- 48-bit mask value for pattern detect (1=ignore) + PATTERN:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- 48-bit pattern match for pattern detect + SEL_MASK:STRING:="MASK"; -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN:STRING:="PATTERN"; -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT:STRING:="NO_PATDET"; -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED:STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED:BIT:='0'; -- Optional inversion for CARRYIN + IS_CLK_INVERTED:BIT:='0'; -- Optional inversion for CLK + IS_INMODE_INVERTED:STD_LOGIC_VECTOR(4 downto 0):="00000"; -- Optional inversion for INMODE + IS_OPMODE_INVERTED:STD_LOGIC_VECTOR(8 downto 0):="000000000"; -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED:BIT:='0'; -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED:BIT:='0'; -- Optional inversion for RSTA + IS_RSTB_INVERTED:BIT:='0'; -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED:BIT:='0'; -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED:BIT:='0'; -- Optional inversion for RSTC + IS_RSTD_INVERTED:BIT:='0'; -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED:BIT:='0'; -- Optional inversion for RSTM + IS_RSTP_INVERTED:BIT:='0'; -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG:INTEGER:=1; -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG:INTEGER:=1; -- Pipeline stages for pre-adder (0-1) + ALUMODEREG:INTEGER:=1; -- Pipeline stages for ALUMODE (0-1) + AREG:INTEGER:=1; -- Pipeline stages for A (0-2) + BCASCREG:INTEGER:=1; -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG:INTEGER:=1; -- Pipeline stages for B (0-2) + CARRYINREG:INTEGER:=1; -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG:INTEGER:=1; -- Pipeline stages for CARRYINSEL (0-1) + CREG:INTEGER:=1; -- Pipeline stages for C (0-1) + DREG:INTEGER:=1; -- Pipeline stages for D (0-1) + INMODEREG:INTEGER:=1; -- Pipeline stages for INMODE (0-1) + MREG:INTEGER:=1; -- Multiplier pipeline stages (0-1) + OPMODEREG:INTEGER:=1; -- Pipeline stages for OPMODE (0-1) + PREG:INTEGER:=1); -- Number of pipeline stages for P (0-1) + port(-- Cascade inputs: Cascade Ports + ACIN:in STD_LOGIC_VECTOR(29 downto 0):=(others=>'0'); -- 30-bit input: A cascade data + BCIN:in STD_LOGIC_VECTOR(17 downto 0):=(others=>'0'); -- 18-bit input: B cascade + CARRYCASCIN:in STD_LOGIC:='0'; -- 1-bit input: Cascade carry + MULTSIGNIN:in STD_LOGIC:='0'; -- 1-bit input: Multiplier sign cascade + PCIN:in STD_LOGIC_VECTOR(47 downto 0):=(others=>'0'); -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE:in STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- 4-bit input: ALU control + CARRYINSEL:in STD_LOGIC_VECTOR(2 downto 0):="000"; -- 3-bit input: Carry select + CLK:in STD_LOGIC:='0'; -- 1-bit input: Clock + INMODE:in STD_LOGIC_VECTOR(4 downto 0):="00000"; -- 5-bit input: INMODE control + OPMODE:in STD_LOGIC_VECTOR(8 downto 0):="000110101"; -- 9-bit input: Operation mode - default is P<=C+A*B + -- Data inputs: Data Ports + A:in SFIXED;--(Ahi downto Alo):=(others=>'0'); -- 30-bit input: A data + B:in SFIXED;--(Bhi downto Blo):=(others=>'0'); -- 18-bit input: B data + C:in SFIXED;--(Chi downto Clo):=(others=>'0'); -- 48-bit input: C data + CARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Carry-in + D:in SFIXED;--(Dhi downto Dlo):=(others=>'0'); -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage AREG + CEA2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage AREG + CEAD:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ADREG + CEALUMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ALUMODE + CEB1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage BREG + CEB2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage BREG + CEC:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CREG + CECARRYIN:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CARRYINREG + CECTRL:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for DREG + CEINMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for INMODEREG + CEM:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for MREG + CEP:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for PREG + RSTA:in STD_LOGIC:='0'; -- 1-bit input: Reset for AREG + RSTALLCARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Reset for CARRYINREG + RSTALUMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for ALUMODEREG + RSTB:in STD_LOGIC:='0'; -- 1-bit input: Reset for BREG + RSTC:in STD_LOGIC:='0'; -- 1-bit input: Reset for CREG + RSTCTRL:in STD_LOGIC:='0'; -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD:in STD_LOGIC:='0'; -- 1-bit input: Reset for DREG and ADREG + RSTINMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for INMODEREG + RSTM:in STD_LOGIC:='0'; -- 1-bit input: Reset for MREG + RSTP:in STD_LOGIC:='0'; -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT:out STD_LOGIC_VECTOR(29 downto 0); -- 30-bit output: A port cascade + BCOUT:out STD_LOGIC_VECTOR(17 downto 0); -- 18-bit output: B cascade + CARRYCASCOUT:out STD_LOGIC; -- 1-bit output: Cascade carry + MULTSIGNOUT:out STD_LOGIC; -- 1-bit output: Multiplier sign cascade + PCOUT:out STD_LOGIC_VECTOR(47 downto 0); -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW:out STD_LOGIC; -- 1-bit output: Overflow in add/acc + PATTERNBDETECT:out STD_LOGIC; -- 1-bit output: Pattern bar detect + PATTERNDETECT:out STD_LOGIC; -- 1-bit output: Pattern detect + UNDERFLOW:out STD_LOGIC; -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT:out STD_LOGIC_VECTOR(3 downto 0); -- 4-bit output: Carry + P:out SFIXED;--(Phi downto Plo); -- 48-bit output: Primary data + XOROUT:out STD_LOGIC_VECTOR(7 downto 0)); -- 8-bit output: XOR data +end entity; + +architecture WRAPPER of DSP48E2GW is + signal slvA:STD_LOGIC_VECTOR(29 downto 0); + signal slvB:STD_LOGIC_VECTOR(17 downto 0); + signal slvD:STD_LOGIC_VECTOR(26 downto 0); + signal slvC,slvP:STD_LOGIC_VECTOR(47 downto 0); +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if K=0) and (Y>=0) generate + begin + i1:if DSP48E=1 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; +-- else generate + i2:if (X<0) or (Y<0) generate + begin + i1:if DSP48E=1 generate + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; + P<=SLV_TO_SFIXED_RESIZE(slvP,P'high,P'low,A'low+B'low-P'low); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CKCM.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CKCM +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Constant Coeficient Complex Multiplier +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CKCM is -- LATENCY=3 + generic(M:INTEGER:=1; -- must be 0, 1, 2 or 3 to multiply I by (1.0,0.0), (Sqrt(0.5),-Sqrt(0.5)), (0.0,-1.0), (-Sqrt(0.5),-Sqrt(0.5)) + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + ROUNDING:BOOLEAN:=FALSE; -- set to TRUE to round the result + CONJUGATE:BOOLEAN:=FALSE); -- set to TRUE for IFFT + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CKCM; + +architecture TEST of CKCM is + attribute use_dsp48:STRING; + attribute use_dsp48 of TEST:architecture is "no"; +--2008 signal RND:SFIXED(O.RE'high downto O.RE'low-1); + signal RND:SFIXED((O'high+1)/2-1 downto O'low/2-1); + constant nCONJUGATE:BOOLEAN:=not CONJUGATE; +begin + i0:if M=0 generate + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>I, + O=>O); + end generate; +--elsif i1: M=2 generate + i1:if M=2 generate + ic:if CONJUGATE generate +--2008 signal NIIM1D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal NIIM1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IRE:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIIM1D<=RESIZE(-I.IM,I.IM); + NIIM1D<=RESIZE(-IM(I),NIIM1D); + end if; + end process; + r2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIIM1D, +--2008 O=>O.RE); + O=>ORE); + IRE<=RE(I); + i3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.IM); + I=>IRE, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + ---else generate + nc:if not CONJUGATE generate +--2008 signal NIRE1D:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal NIRE1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + IIM<=IM(I); + r3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.RE); + I=>IIM, + O=>ORE); + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIRE1D<=RESIZE(-I.RE,I.RE); + NIRE1D<=RESIZE(-RE(I),RE(I)); + end if; + end process; + i2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIRE1D, +--2008 O=>O.IM); + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + end generate; +-- else generate -- M=1 or 3 + i2:if (M=1) or (M=3) generate -- M=1 or 3 + constant K:SFIXED(0 downto -18):="0101101010000010100"; -- SQRT(0.5) + +--2008 signal X1,Y1:SFIXED(I.RE'high downto I.RE'low-14); +--2008 signal X2,Y2:SFIXED(I.RE'range); +--2008 signal KIRE,KIIM:SFIXED(I.RE'range); + + + + signal X1,Y1:SFIXED((I'high+1)/2-1 downto I'low/2-14); + signal X2,Y2:SFIXED((I'high+1)/2-1 downto I'low/2):=(others=>'0'); + signal KIRE,KIIM:SFIXED((I'high+1)/2-1 downto I'low/2); +--2008 signal I_1:CFIXED(RE(I.RE'high-1 downto I.RE'low-1),IM(I.IM'high-1 downto I.IM'low-1)); +--2008 signal I_6:CFIXED(RE(I.RE'high-6 downto I.RE'low-6),IM(I.IM'high-6 downto I.IM'low-6)); +--2008 signal I_14:CFIXED(RE(I.RE'high-14 downto I.RE'low-14),IM(I.IM'high-14 downto I.IM'low-14)); + signal I_1:CFIXED(I'high-2*1 downto I'low-2*1); + signal I_6:CFIXED(I'high-2*6 downto I'low-2*6); + signal I_14:CFIXED(I'high-2*14 downto I'low-2*14); + signal I_1RE,I_1IM:SFIXED((I_1'high+1)/2-1 downto I_1'low/2); + signal I_6RE,I_6IM:SFIXED((I_6'high+1)/2-1 downto I_6'low/2); + signal I_14RE,I_14IM:SFIXED((I_14'high+1)/2-1 downto I_14'low/2); + signal X1_2:SFIXED(X1'high-2 downto X1'low-2); + signal X2_4:SFIXED(X2'high-4 downto X2'low-4); + signal Y1_2:SFIXED(Y1'high-2 downto Y1'low-2); + signal Y2_4:SFIXED(Y2'high-4 downto Y2'low-4); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + constant MEQ3:BOOLEAN:=M=3; + begin +--2008 RND<=TO_SFIXED(2.0**(O.RE'low-1),RND) when ROUNDING else (others=>'0'); + RND<=TO_SFIXED(2.0**(O'low/2-1),RND) when ROUNDING else (others=>'0'); + process(CLK) + begin + if rising_edge(CLK) then +--2008 X2<=I.RE; +--2008 Y2<=I.IM; + X2<=RE(I); + Y2<=IM(I); + end if; + end process; + + I_1<=SHIFT_RIGHT(I,1); + I_6<=SHIFT_RIGHT(I,6); + I_14<=SHIFT_RIGHT(I,14); + X1_2<=SHIFT_RIGHT(X1,2); + X2_4<=SHIFT_RIGHT(X2,4); + Y1_2<=SHIFT_RIGHT(Y1,2); + Y2_4<=SHIFT_RIGHT(Y2,4); + I_1RE<=RE(I_1); + I_6RE<=RE(I_6); + I_14RE<=RE(I_14); + + a1:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.RE, +--2008 B=>I_6.RE, +--2008 C=>I_14.RE, + A=>I_1RE, + B=>I_6RE, + C=>I_14RE, + P=>X1); -- P=C+A+B + + a2:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>X1, + B=>X1_2, + C=>X2_4, + P=>KIRE); -- P=C+A+B + + I_1IM<=IM(I_1); + I_6IM<=IM(I_6); + I_14IM<=IM(I_14); + a3:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.IM, +--2008 B=>I_6.IM, +--2008 C=>I_14.IM, + A=>I_1IM, + B=>I_6IM, + C=>I_14IM, + P=>Y1); -- P=C+A+B + + a4:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>Y1, + B=>Y1_2, + C=>Y2_4, + P=>KIIM); -- P=C+A+B + + a5:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>MEQ3, --2008 M=3, + NEGATIVE_B=>CONJUGATE, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>MEQ3, --2008 M=3, + CY2=>CONJUGATE, +--2008 P=>O.RE); -- P=C+A+B + P=>ORE); -- P=C+A+B + + a6:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>nCONJUGATE, + NEGATIVE_B=>MEQ3, --2008 M=3, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>nCONJUGATE, + CY2=>MEQ3, --2008 M=3, +--2008 P=>O.IM); -- P=C+A+B + P=>OIM); -- P=C+A+B + O<=TO_CFIXED(ORE,OIM); + --end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: ADDSUB.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity ADDSUB is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SUB:in BOOLEAN:=FALSE; +-- P:out SIGNED); -- O=A±B + P:out SFIXED); -- O=A±B +end ADDSUB; + +architecture FAST of ADDSUB is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB:SFIXED(SH downto SM); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0"; + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + signal I_4:STD_LOGIC; + begin + I_4<='1' when SUB else '0'; + l6:LUT6_2 generic map(INIT=>(I5 and (I2 xor I3 xor I4)) or (not I5 and ((I2 xor I4) and I3))) + port map(I0=>'0',I1=>'0',I2=>SB(K),I3=>SA(K),I4=>I_4,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + +-- ll:for L in SM to SH+1 generate + ll:for L in SM to SH generate +-- S(L)<=O(L-SM+1); + S(L)<=O(L-SM); + end generate; + S(SH+1)<=S(SH); + + ia:if A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: TABLE.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: TABLE +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, SinCos Table Module +-- +-- Latency is always 2 +-- when INV_FFT=FALSE W=exp(-2.0*PI*i*JK/N) and when INV_FFT=TRUE W=exp(2.0*PI*i*JK/N) +-- to maximize W output bit size utilization W.RE and W.IM are always negative (MSB='1') and that bit could be ignored, this is why W.RE'length can be 19 bits but a single BRAM would still be used +-- when W.RE or W.IM need to be positive CS respectively SS are TRUE, same thing when they are 0.0 CZ respectively SZ are TRUE - the complex multiplier has to use CS, SS, CZ and SZ, not just W to produce the correct result +-- the SIN and COS ROM table sizes are N/4 deep and W.RE'length-1 wide (it is implictly assumed that W.RE and W.IM always have the same range) +-- if STYLE="block" a single dual port BRAM is used for both tables +-- if STYLE="distributed" then two fabric LUT based ROMs are used +-- as a general rule for N<2048 "distributed" should be used, otherwise "block" makes more sense but this is not a hard rule +-- W range is unconstrained but W.RE'high and W.IM'high really have to be 0 all the time, do not use other values +-- the maximum SNR without using extra BRAMs is achieved when W.RE'low and W.IM'low are -18 so W.RE'length and W.IM'length are 19 bits but they can be less than that - this would reduce SNR and save resources only when STYLE="distributed" +-- TABLE.VHD also works with more than 19 bits but the current complex multiplier implementation does not support that - this would essentially double the number of BRAMs and DSP48s used and seems too high a price to pay for a few extra dB of SNR +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use IEEE.MATH_REAL.all; + +use work.COMPLEX_FIXED_PKG.all; + +--!! entity TABLE is -- LATENCY=3 (2 if SEPARATE_SIGN is TRUE) +entity TABLE is -- LATENCY=4 (3 if SEPARATE_SIGN is TRUE) when SPLIT_RADIX=0 else LATENCY=0 + generic(N:INTEGER:=1024; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and J*1 or J*3 with J>0 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + SEPARATE_SIGN:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + STYLE:STRING:="block"); -- use only "block" or "distributed" + port(CLK:in STD_LOGIC; + JK:in UNSIGNED; + VI:in BOOLEAN; + W:out CFIXED; + CS,SS,CZ,SZ:out BOOLEAN; + VO:out BOOLEAN); +end TABLE; + +architecture TEST of TABLE is +--2008 constant WH:INTEGER:=W.RE'high-1+BOOLEAN'pos(SEPARATE_SIGN); +--2008 constant WL:INTEGER:=W.RE'low; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 + constant WH:INTEGER:=(W'high+1)/2-1-1+BOOLEAN'pos(SEPARATE_SIGN); + constant WL:INTEGER:=W'low/2; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 +begin + i0:if SPLIT_RADIX=0 generate + type wSFIXED_VECTOR is array(INTEGER range <>) of SFIXED(WH-1 downto WL); -- local constrained array of SFIXED type +--2008 function LUT_VALUE(N,WH,WL:INTEGER) return SFIXED_VECTOR is +--2008 variable RESULT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL); + function LUT_VALUE(N,WH,WL:INTEGER) return wSFIXED_VECTOR is + variable RESULT:wSFIXED_VECTOR(0 to N/4-1); + begin + RESULT(0):=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + for J in 1 to N/4-1 loop + RESULT(J):=TO_SFIXED(-COS(-2.0*MATH_PI*REAL(J)/REAL(N))+2.0**(WL-1),WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + if RESULT(J)=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL) then + RESULT(J):=TO_SFIXED(-1.0+2.0**WL,WH,WL)(WH-1 downto WL); + end if; + end loop; + return RESULT; + end; + + signal JKD:UNSIGNED(JK'range):=(others=>'0'); + signal KC,KS:UNSIGNED(JK'range):=(others=>'0');--!! + signal DC,C,DS,S:SFIXED(WH-1 downto WL):=(others=>'0'); +--2008 signal LUT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL):=LUT_VALUE(N,WH,WL); + signal LUT:wSFIXED_VECTOR(0 to N/4-1):=LUT_VALUE(N,WH,WL); + attribute rom_style:STRING; + attribute rom_style of LUT:signal is STYLE; + signal RC,RS:BOOLEAN:=FALSE; + signal MC,MS:STD_LOGIC:='0'; + signal CS1,SS1,CS2,SS2:BOOLEAN:=FALSE; + signal W_RE,W_IM:SFIXED((W'high+1)/2-1 downto W'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--!! +--2008 KC<=JK when JK(JK'high-1)='0' else (not JK)+1; +--2008 KS<=(not JK)+1 when JK(JK'high-1)='0' else JK; + if JK(JK'high-1)='0' then + KC<=JK; + KS<=(not JK)+1; + else + KC<=(not JK)+1; + KS<=JK; + end if; + JKD<=JK; + if (JKD and TO_UNSIGNED(2**(JK'length-2)-1,JK'length))=0 then --mask first two MSBs of JK + RC<=JKD(JK'high-1)='1'; + RS<=JKD(JK'high-1)='0'; + else + RC<=FALSE; + RS<=FALSE; + end if; + DC<=LUT(TO_INTEGER(KC and TO_UNSIGNED(2**(KC'length-2)-1,KC'length))); + DS<=LUT(TO_INTEGER(KS and TO_UNSIGNED(2**(KS'length-2)-1,KS'length))); + if RC then + C<=(others=>'0'); + MC<='0'; + else + C<=DC; + MC<='1'; + end if; + if RS then + S<=(others=>'0'); + MS<='0'; + else + S<=DS; + MS<='1'; + end if; + CS1<=JKD(JK'high)=JKD(JK'high-1); + SS1<=(JKD(JK'high)='1') xor INV_FFT; + CS2<=CS1; + SS2<=SS1; + end if; + end process; + + i0:if SEPARATE_SIGN generate +--2008 W.RE<=MC&C; +--2008 W.IM<=MS&S; + W(W'length/2-1+W'low downto W'low)<=CFIXED(MC&C); + W(W'high downto W'length/2+W'low)<=CFIXED(MS&S); + CS<=CS2; + SS<=SS2; +-- else generate + end generate; + i1:if not SEPARATE_SIGN generate + signal WRE,WIM:SFIXED(WH downto WL):=(others=>'0'); + attribute keep:STRING; + attribute keep of WRE:signal is "yes"; + attribute keep of WIM:signal is "yes"; + signal ZERO:SFIXED(WH downto WL):=TO_SFIXED(0.0,WH,WL); + begin + WRE<=MC&C; + WIM<=MS&S; + + process(CLK) + begin + if rising_edge(CLK) then + CS<=CS2; + SS<=SS2; + CZ<=WRE(WRE'high)='0'; + SZ<=WIM(WIM'high)='0'; + end if; + end process; + ar:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WRE, + SUB=>CS2, +--2008 P=>W.RE); -- P=±B + P=>W_RE); -- P=±B + ai:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WIM, + SUB=>SS2, +--2008 P=>W.IM); -- P=±B + P=>W_IM); -- P=±B + W(W'length/2-1+W'low downto W'low)<=CFIXED(W_RE); + W(W'high downto W'length/2+W'low)<=CFIXED(W_IM); +-- end; + end generate; + +--!! b2:entity work.BDELAY generic map(SIZE=>3-BOOLEAN'pos(SEPARATE_SIGN)) + b2:entity work.BDELAY generic map(SIZE=>4-BOOLEAN'pos(SEPARATE_SIGN)) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- else generate + i1:if SPLIT_RADIX>0 generate + begin + i0:if SEPARATE_SIGN generate +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + end generate; +-- else generate + ii:if not SEPARATE_SIGN generate + begin +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + CZ<=(SPLIT_RADIX=N/4) or (SPLIT_RADIX=3*N/4); + SZ<=(SPLIT_RADIX=0) or (SPLIT_RADIX=N/2); +-- end; + end generate; + VO<=VI; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3 +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Complex Multiplier Using 3 DSP48E2s +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3 is -- LATENCY=6 + generic(ROUNDING:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED; -- I.RE'length and I.IM'length<27 + W:in CFIXED; -- W must be (1 downto -16) or (1 downto -17) + CS,SS,CZ,SZ:in BOOLEAN:=FALSE; + VI:in BOOLEAN; + O:out CFIXED; + VO:out BOOLEAN); +end CM3; + +architecture TEST of CM3 is + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute loc:STRING; + +--2008 constant HMAX:INTEGER:=MAX(I.RE'high,I.IM'high)+MAX(W.RE'high,W.IM'high)+3; +--2008 constant LMIN:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(I.RE'low,I.IM'low)+work.COMPLEX_FIXED_PKG.MIN(W.RE'low,W.IM'low); + constant HMAX:INTEGER:=(I'high+1)/2-1+(W'high+1)/2-1+3; + constant LMIN:INTEGER:=I'low/2+W'low/2; + +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,1) downto MAX(W.RE'low,-16)); +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,0) downto MAX(W.RE'low,-17)); +--2008 signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'low+17,1) downto W.RE'low); -- we only have 18 bits max to work with +--2008 signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); +--2008 signal IRE1D,IRE2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); +--2008 signal IIM1D,IIM2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W'low/2+17,1) downto W'low/2); -- we only have 18 bits max to work with + signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal IRE,IRE1D,IRE2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM,IIM1D,IIM2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal CS2D,SS2D:BOOLEAN; + signal C0S1:BOOLEAN:=FALSE; + signal P1,P2,P3:SFIXED(HMAX downto LMIN); + signal P2D:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal C1,C2,C3:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal AC1,AC2:STD_LOGIC_VECTOR(29 downto 0); + signal BC1:STD_LOGIC_VECTOR(17 downto 0); + signal PC1,PC2:STD_LOGIC_VECTOR(47 downto 0); +--2008 signal A_ZERO:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal A_ZERO:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal B_ZERO:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal C_ZERO:SFIXED(HMAX downto LMIN):=TO_SFIXED(0.0,HMAX,LMIN); + signal BR,BI:BOOLEAN; + signal iO:CFIXED(O'range); +begin +--!! +--2008 WRE<=RESIZE(W.RE,WRE); + WRE<=RESIZE(RE(W),WRE); +--!! WRE<=TO_SFIXED(1.0-2.0**WRE'low,WRE) when W.RE=TO_SFIXED(1.0,W.RE) else RESIZE(W.RE,WRE); +--!! +--2008 WIM<=RESIZE(W.IM,WIM); + WIM<=RESIZE(IM(W),WIM); + process(CLK) + begin + if rising_edge(CLK) then + WRE1D<=WRE; +--2008 IRE1D<=I.RE; +--2008 IIM1D<=I.IM; + IRE1D<=RE(I); + IIM1D<=IM(I); +--2008 C0S1<=CZ and (W.IM(W.IM'high)='0'); + C0S1<=CZ and (W(W'high)='0'); +--!! + NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! if WRE1D=TO_SFIXED(-1.0,WRE1D) then +--!! for K in NWRE2D'range loop +--!! NWRE2D(K)<=not WRE1D(K); +--!! end loop; +--!! else +--!! NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! end if; +--!! + IRE2D<=IRE1D; + IIM2D<=IIM1D; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and C0S1 then + if (W'low/2=-17) and C0S1 then + C1<=RESIZE(SHIFT_LEFT(IRE1D+IIM1D,1),C1); + else + C1<=TO_SFIXED(0.0,C1); + end if; + end if; + end process; + + IRE<=RE(I); + IIM<=IM(I); + dsp1:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"00101", -- (D+A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110000101", -- PCOUT=-C-(D+A1)*B2 +--2008 A=>I.RE, + A=>IRE, + B=>WIM, + C=>C1, +--2008 D=>I.IM, + D=>IIM, + ACOUT=>AC1, + BCOUT=>BC1, + P=>P1, + PCOUT=>PC1); + +-- C2<=TO_SFIXED(2.0**(O.RE'low-1),C2) when ROUNDING else TO_SFIXED(0.0,C2); + BR<=W(W'length/2-1+W'low)='0'; + BI<=W(W'high)='0'; + cd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.RE(W.RE'high)='0', + I=>BR, + O=>CS2D); + sd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.IM(W.IM'high)='0', + I=>BI, + O=>SS2D); + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and CS2D=SS2D then + if (W'low/2=-17) and CS2D=SS2D then + if CS2D then + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(I.RE,C2); + C2<=RESIZE(SHIFT_LEFT(IRE2D,1),C2); + end if; + else + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(-I.RE,C2); + C2<=RESIZE(-SHIFT_LEFT(IRE2D,1),C2); + end if; + end if; + else + if ROUNDING then +--2008 C2<=TO_SFIXED(2.0**(O.RE'low-1),C2); + C2<=TO_SFIXED(2.0**(O'low/2-1),C2); + else + C2<=TO_SFIXED(0.0,C2); + end if; + end if; + end if; + end process; + + dsp2:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL=>"AD", -- Selects B input to multiplier (AD, B) + B_INPUT=>"CASCADE", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL=>"B", -- Selects input to preadder (A, B) + AREG=>2) -- Pipeline stages for A (0-2) + port map(CLK=>CLK, + INMODE=>"10100", -- (D+B1)*A2 + ALUMODE=>"0000", -- Z+W+X+Y + OPMODE=>"110010101", -- PCOUT=PCIN+C+(D+B1)*A2 + A=>A_ZERO, + B=>B_ZERO, + C=>C2, + D=>WRE1D, + ACIN=>AC1, + BCIN=>BC1, + PCIN=>PC1, + ACOUT=>AC2, + P=>P2, + PCOUT=>PC2); + +-- C3<=RESIZE(SHIFT_RIGHT(P1,-16-W.RE'low),P1); + C3<=P1; + dsp3:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"01101", --5x"0C", -- (D-A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110010101", -- PCOUT=PCIN-C-(D-A1)*B2 + A=>A_ZERO, + B=>NWRE2D, + C=>C3, + D=>IIM2D, + ACIN=>AC2, + PCIN=>PC2, + P=>P3); + + process(CLK) + begin + if rising_edge(CLK) then +--2008 O.RE<=RESIZE(P2,O.RE); + P2D<=P2; + end if; + end process; +--2008 O.IM<=RESIZE(P3,O.IM); +-- O<=RESIZE(TO_CFIXED(P2D,P3),O); + O<=RESIZE(TO_CFIXED(P2D,P3),iO); + + bd:entity work.BDELAY generic map(SIZE=>6) + port map(CLK=>CLK, + I=>VI, + O=>VO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. 3 +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3FFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic Complex Multiplier Stage Module - uses 3 DSP48s/complex multiplication +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3FFT is -- LATENCY=10 + generic(N:INTEGER; + RADIX:INTEGER; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and 1 or 3 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CM3FFT; + +architecture TEST of CM3FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + function STYLE(N:INTEGER) return STRING is + begin + if N>BRAM_THRESHOLD then + return "block"; + else + return "distributed"; + end if; + end; + + function TABLE_LATENCY(SPLIT_RADIX:INTEGER) return INTEGER is + begin + if SPLIT_RADIX=0 then + return 4; + else + return 0; + end if; + end; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + signal CNT:UNSIGNED(L2N-L2R-1 downto 0):=(others=>'0'); + signal I0:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal O0:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + +--!! cd:entity work.CDELAY generic map(SIZE=>3+6) + I0<=ELEMENT(I,0,RADIX); + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, +--2008 I=>I(I'low), +--2008 O=>O(O'low)); + I=>I0, + O=>O0); + O(O'length/RADIX-1+O'low downto O'low)<=CFIXED_VECTOR(O0); + + process(CLK) + begin + if rising_edge(CLK) then + if not VI or (SPLIT_RADIX/=0) then + CNT<=(others=>'0'); + else + CNT<=CNT+1; + end if; + end if; + end process; + +--2008 lk:for J in 1 to I'length-1 generate + lk:for J in 1 to RADIX-1 generate + signal JK:UNSIGNED(L2N-1 downto 0):=(others=>'0'); +--2008 signal W:CFIXED(RE(W_high downto W_low),IM(W_high downto W_low)); + signal W:CFIXED(2*(W_high+1)-1 downto 2*W_low); + signal V,CZ:BOOLEAN; +--2008 signal ID:CFIXED(RE(I(I'low).RE'high downto I(I'low).RE'low),IM(I(I'low).IM'high downto I(I'low).IM'low)); + signal ID:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal IJ:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal OJ:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if SPLIT_RADIX=0 then + if not VI or (CNT=N/RADIX-1) then + JK<=(others=>'0'); + else + JK<=JK+J; + end if; + else + JK<=TO_UNSIGNED(J*SPLIT_RADIX,JK'length); + end if; + end if; + end process; + + ut:entity work.TABLE generic map(N=>N, + INV_FFT=>INV_FFT, + DSP48E=>DSP48E, + STYLE=>STYLE(N/4)) + port map(CLK=>CLK, + JK=>JK, + VI=>VI, + CZ=>CZ, + W=>W, + VO=>V); + + IJ<=ELEMENT(I,J,RADIX); +--!! cd:entity work.CDELAY generic map(SIZE=>3) + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)) + port map(CLK=>CLK, +--2008 I=>I(I'low+J), + I=>IJ, + O=>ID); + + u1:entity work.CM3 generic map(ROUNDING=>ROUNDING, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ID, + W=>W, + CZ=>CZ, + VI=>V, +--2008 O=>O(O'low+J), + O=>OJ, + VO=>open); + O((J+1)*O'length/RADIX-1+O'low downto J*O'length/RADIX+O'low)<=CFIXED_VECTOR(OJ); + end generate; + +--!! bd:entity work.BDELAY generic map(SIZE=>3+6) + bd:entity work.BDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>VI, + O=>VO); + +--!! ud:entity work.UDELAY generic map(SIZE=>3+6) + ud:entity work.UDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>SI, + O=>SO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: PARFFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity PARFFT is + generic(N:INTEGER:=4; + F:INTEGER:=0; + INV_FFT:BOOLEAN:=FALSE; + ROUNDING:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-16; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end PARFFT; + +architecture TEST of PARFFT is + constant I_low:INTEGER:=I'low/2/N; + constant I_high:INTEGER:=I'length/2/N-1+I_low; + constant O_low:INTEGER:=O'low/2/N; + constant O_high:INTEGER:=O'length/2/N-1+O_low; + + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + constant L2N:INTEGER:=LOG2(N); +begin +--2008 assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + + f0:if F=0 generate + begin + l2:if N=2 generate -- FFT2 case + signal I0,I1:CFIXED(2*I_high+1 downto 2*I_low); + signal O0,O1:CFIXED(2*O_high+1 downto 2*O_low); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,2); + I1<=ELEMENT(I,1,2); +-- complex add/sub butterfly with scaling and overflow detection + bf:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I1, + SCALE=>SI(SI'low), + O0=>O0, + O1=>O1, + OVR=>SO(SO'high)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/2-1+O'low downto 0*O'length/2+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/2-1+O'low downto 1*O'length/2+O'low)<=CFIXED_VECTOR(O1); + + process(CLK) + begin + if rising_edge(CLK) then + iSO<=SI(SI'high downto SI'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>1) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=4 generate -- FFT4 case + l4:if N=4 generate -- FFT4 case + signal I0,I1,I2,I3:CFIXED(2*I_high+1 downto 2*I_low); + signal P0,P1,P2,P3,P3S:CFIXED(2*I_high+3 downto 2*I_low); + signal O0,O1,O2,O3,O1S,O3S:CFIXED(2*O_high+1 downto 2*O_low); + signal S:UNSIGNED(SI'range):=(others=>'0'); + signal OVR1,OVR2:UNSIGNED(1 downto 0); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,4); + I1<=ELEMENT(I,1,4); + I2<=ELEMENT(I,2,4); + I3<=ELEMENT(I,3,4); +-- complex add/sub butterflies with scaling and overflow detection + u0:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I2, + SCALE=>SI(SI'low), + O0=>P0, + O1=>P1, + OVR=>OVR1(0)); + + u1:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I1, + I1=>I3, + SCALE=>SI(SI'low), + O0=>P2, + O1=>P3, + OVR=>OVR1(1)); + + process(CLK) + begin + if rising_edge(CLK) then + S<=(OVR1(0) or OVR1(1))&SI(SI'high downto SI'low+1); + end if; + end process; + + u2:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P0, + I1=>P2, + SCALE=>S(S'low), + O0=>O0, + O1=>O2, + OVR=>OVR2(0)); + + P3S<=SWAP(P3); + u3:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P1, + I1=>P3S, + SCALE=>S(S'low), + O0=>O1S, + O1=>O3S, + OVR=>OVR2(1)); + O1<=TO_CFIXED(RE(O1S),IM(O3S)); + O3<=TO_CFIXED(RE(O3S),IM(O1S)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/4-1+O'low downto 0*O'length/4+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/4-1+O'low downto 1*O'length/4+O'low)<=CFIXED_VECTOR(O1); + O((2+1)*O'length/4-1+O'low downto 2*O'length/4+O'low)<=CFIXED_VECTOR(O2); + O((3+1)*O'length/4-1+O'low downto 3*O'length/4+O'low)<=CFIXED_VECTOR(O3); + + SO(SO'high)<=(OVR2(0) or OVR2(1)); + process(CLK) + begin + if rising_edge(CLK) then + iSO<=S(S'high downto S'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=8 generate -- FFT8 case + l8:if N=8 generate -- FFT8 case +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/8/2-(I'high+1)/8/2; + constant X:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,1); -- ModelSim workaround + signal iV:BOOLEAN_VECTOR(0 to 3); +--2008 signal S:UNSIGNED_VECTOR(0 to 3)(SI'range); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:TUV(0 to 3); + signal SS:UNSIGNED(SI'range); + signal P:CFIXED_VECTOR(I'high+8*2*X downto I'low); + signal VP:BOOLEAN; + signal SP:UNSIGNED(SI'range); + signal oV:BOOLEAN_VECTOR(0 to 1); +--2008 signal oS:UNSIGNED_VECTOR(0 to 1)(SO'range); + signal oS:TUV(0 to 1); + begin + s1:for K in 0 to 3 generate +--2008 signal II:CFIXED_VECTOR(0 to 1)(RE(I(0).RE'high downto I(0).RE'low),IM(I(0).IM'high downto I(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 1)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); + signal II:CFIXED_VECTOR(4*(I_high+1)-1 downto 4*I_low); + signal OO:CFIXED_VECTOR(4*(I_high+1+2*X)-1 downto 4*I_low); + signal OO0,OO1:CFIXED(2*(I_high+1+2*X)-1 downto 2*I_low); + signal P0,P1:CFIXED(I'length/8+2*X-1+I'low/8 downto I'low/8); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=I(K); +--2008 II(1)<=I(K+4); + II((0+1)*II'length/2-1+II'low downto 0*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K,8)); + II((1+1)*II'length/2-1+II'low downto 1*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K+4,8)); + p2:entity work.PARFFT generic map(N=>2, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>iV(K), + SO=>S(K)); + OO0<=ELEMENT(OO,0,2); + OO1<=ELEMENT(OO,1,2); + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>OO(0), +--2008 O=>P(2*K+0)); + I=>OO0, + O=>P0); + ck:entity work.CKCM generic map(DSP48E=>DSP48E, + M=>K, + ROUNDING=>ROUNDING, + CONJUGATE=>INV_FFT) + port map(CLK=>CLK, +--2008 I=>OO(1), +--2008 O=>P(2*K+1)); + I=>OO1, + O=>P1); + P((2*K+1)*P'length/8-1+P'low downto (2*K+0)*P'length/8+P'low)<=CFIXED_VECTOR(P0); + P((2*K+2)*P'length/8-1+P'low downto (2*K+1)*P'length/8+P'low)<=CFIXED_VECTOR(P1); + end generate; + SS(SI'high)<=S(0)(SI'high) or S(1)(SI'high) or S(2)(SI'high) or S(3)(SI'high) when iV(0) else '0'; + SS(SI'high-1 downto SI'low)<=S(0)(SI'high-1 downto SI'low); + ud:entity work.UDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>SS, + O=>SP); + bd:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>iV(0), + O=>VP); + s2:for K in 0 to 1 generate +--2008 signal II:CFIXED_VECTOR(0 to 3)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 3)(RE(O(0).RE'high downto O(0).RE'low),IM(O(0).IM'high downto O(0).IM'low)); + signal II:CFIXED_VECTOR((P'high+1)/2-1 downto P'low/2); + signal OO:CFIXED_VECTOR((O'high+1)/2-1 downto O'low/2); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=P(K+0); +--2008 II(1)<=P(K+2); +--2008 II(2)<=P(K+4); +--2008 II(3)<=P(K+6); + II((0+1)*II'length/4-1+II'low downto 0*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+0,8)); + II((1+1)*II'length/4-1+II'low downto 1*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+2,8)); + II((2+1)*II'length/4-1+II'low downto 2*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+4,8)); + II((3+1)*II'length/4-1+II'low downto 3*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+6,8)); + p2:entity work.PARFFT generic map(N=>4, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VP, + SI=>SP, + O=>OO, + VO=>oV(K), + SO=>oS(K)); +--2008 O(K+0)<=OO(0); +--2008 O(K+2)<=OO(1); +--2008 O(K+4)<=OO(2); +--2008 O(K+6)<=OO(3); + O((K+0+1)*O'length/8-1+O'low downto (K+0)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,0,4)); + O((K+2+1)*O'length/8-1+O'low downto (K+2)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,1,4)); + O((K+4+1)*O'length/8-1+O'low downto (K+4)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,2,4)); + O((K+6+1)*O'length/8-1+O'low downto (K+6)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,3,4)); + end generate; + VO<=oV(0); + SO(SO'high downto SO'high-1)<=oS(0)(SO'high downto SO'high-1) or oS(1)(SO'high downto SO'high-1) when oV(0) else "00"; + SO(SO'high-2 downto SO'low)<=oS(0)(SO'high-2 downto SO'low); +-- end; + end generate; +-- elsif N=2**L2N generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation + ln:if (N>8) and (N=2**L2N) generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/N/2-(I'high+1)/N/2; + constant X1:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-2); -- ModelSim workaround + constant X2:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-1); -- ModelSim workaround + function MUL_LATENCY(N:INTEGER) return INTEGER is + begin + return 6; + end; + function LATENCY(N:INTEGER) return INTEGER is + begin + return LOG2(N)*4-6; + end; +--2008 signal IU:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal U,UD:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); + signal IU:CFIXED_VECTOR((I'high+1)/2-1 downto I'low/2); + signal U,UD:CFIXED_VECTOR((I'high+1)/2-1+N/2*2*X2 downto I'low/2); + signal SU,SUD:UNSIGNED(SI'range); + signal VU,VU4D:BOOLEAN; +--2008 signal ZO:CFIXED_MATRIX(0 to N/4-1)(0 to 1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(2*2*(I_high+X1+1)-1 downto 2*2*I_low); -- unconstrained array of CFIXED_VECTOR + signal ZO:CFIXED_MATRIX(0 to N/4-1); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); +--2008 signal S1:UNSIGNED_VECTOR(0 to 1)(SI'range); + signal S1:TUV(0 to 1); + signal S1I:UNSIGNED(SI'range); +--2008 signal S2:UNSIGNED_VECTOR(0 to N/4-1)(SI'range); + signal S2:TUV(0 to N/4-1); + signal S2I:UNSIGNED(SI'range):=(others=>'0'); +--2008 signal S:UNSIGNED_VECTOR(0 to N/2-1)(SI'range); + signal S:TUV(0 to N/2-1); + begin + lk:for K in 0 to N/2-1 generate +--2008 IU(K)<=I(I'low+2*K); + IU((K+1)*IU'length/N*2-1+IU'low downto K*IU'length/N*2+IU'low)<=CFIXED_VECTOR(ELEMENT(I,2*K,N)); + end generate; + pu:entity work.PARFFT generic map(N=>N/2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IU, + VI=>VI, + SI=>SI, + O=>U, + VO=>VU, + SO=>SU); + du:for K in 0 to N/2-1 generate + signal UK,UDK:CFIXED((UD'high+1)/N*2-1 downto UD'low/N*2); + begin + UK<=ELEMENT(U,K,N/2); + cd:entity work.CDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+1-LATENCY(N/2))--3) -- when CMUL latency is 6 + port map(CLK=>CLK, +--2008 I=>U(K), +--2008 O=>UD(K)); + I=>UK, + O=>UDK); + UD((K+1)*UD'length/N*2-1+UD'low downto K*UD'length/N*2+UD'low)<=CFIXED_VECTOR(UDK); + end generate; + u4:entity work.UDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>SU, + O=>SUD); + b5:entity work.BDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>VU, + O=>VO); + ll:for L in 0 to 1 generate +--2008 signal IZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal Z,OZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + signal IZ:CFIXED_VECTOR((I'high+1)/4-1 downto I'low/4); + signal Z,OZ:CFIXED_VECTOR((I'high+1)/4-1+N/4*2*X1 downto I'low/4); + signal SZ:UNSIGNED(SI'range); + signal SM:UNSIGNED(SI'range); + signal VZ:BOOLEAN; + begin + li:for J in 0 to N/4-1 generate +--2008 IZ(J)<=I(I'low+4*J+2*L+1); + IZ(2*(J+1)*(I_high-I_low+1)-1+IZ'low downto 2*J*(I_high-I_low+1)+IZ'low)<=CFIXED_VECTOR(ELEMENT(I,4*J+2*L+1,N)); + end generate; + pe:entity work.PARFFT generic map(N=>N/4, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IZ, + VI=>VI, + SI=>SI, + O=>Z, + VO=>VZ, + SO=>SZ); + me:entity work.CM3FFT generic map(N=>N, + RADIX=>N/4, + SPLIT_RADIX=>2*L+1, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>Z, + VI=>VZ, + SI=>SZ, + O=>OZ, + VO=>open, + SO=>S1(L)); + lo:for J in 0 to N/4-1 generate +--2008 ZO(J)(L)<=OZ(J); + ZO(J)((L+1)*ZO(J)'length/2-1+ZO(J)'low downto L*ZO(J)'length/2+ZO(J)'low)<=CFIXED_VECTOR(ELEMENT(OZ,J,N/4)); + end generate; + end generate; + S1I<=S1(0) or S1(1); + l2:for J in 0 to N/4-1 generate +--2008 signal O2:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal IE,IO:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal OE,OO:CFIXED_VECTOR(0 to 1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal O2:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal IE,IO:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal OE,OO:CFIXED_VECTOR(2*2*(O_high+1)-1 downto 2*2*O_low); + begin + p2:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ZO(J), + VI=>TRUE, + SI=>S1I, + O=>O2, + VO=>open, + SO=>S2(J)); +--2008 IE(0)<=UD(J); +--2008 IE(1)<=O2(0); + IE((0+1)*IE'length/2-1+IE'low downto 0*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(UD,J,N/2)); + IE((1+1)*IE'length/2-1+IE'low downto 1*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(O2,0,2)); + pe:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IE, + VI=>TRUE, + SI=>S2I, + O=>OE, + VO=>open, + SO=>S(2*J)); +--2008 O(O'low+J)<=OE(0); +--2008 O(O'low+J+N/2)<=OE(1); +--2008 IO(0)<=UD(J+N/4); +--2008 IO(1).RE<=O2(1).IM; +--2008 IO(1).IM<=O2(1).RE; +-- O((J+1)*O'length/N-1+O'low downto J*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); +-- O((J+N/2+1)*O'length/N-1+O'low downto (J+N/2)*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + O(2*(J+1)*(O_high-O_low+1)-1+O'low downto 2*J*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); + O(2*(J+N/2+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/2)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + IO((0+1)*IO'length/2-1+IO'low downto 0*IO'length/2+IO'low)<=CFIXED_VECTOR(ELEMENT(UD,J+N/4,N/2)); + IO((1+1)*IO'length/2-1+IO'low downto 1*IO'length/2+IO'low)<=CFIXED_VECTOR(TO_CFIXED(IM(ELEMENT(O2,1,2)),RE(ELEMENT(O2,1,2)))); + po:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IO, + VI=>TRUE, + SI=>S2I, + O=>OO, + VO=>open, + SO=>S(2*J+1)); + ii:if INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(1).RE; +--2008 O(O'low+J+N/4).IM<=OO(0).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(0).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(1).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- end; + end generate; +-- else generate + id:if not INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(0).RE; +--2008 O(O'low+J+N/4).IM<=OO(1).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(1).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(0).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- end; + end generate; + end generate; + process(S2) + variable vS2:UNSIGNED(SI'range); + begin + vS2:=SUD; + for K in S2'range loop + vS2:=vS2 or S2(K); + end loop; + S2I<=vS2; + end process; + process(S) + variable vS:UNSIGNED(SI'range); + begin + vS:=(others=>'0'); + for K in S'range loop + vS:=vS or S(K); + end loop; + SO<=vS; + end process; +-- end; + end generate; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=N/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.PARFFT generic map(N=>G, + F=>0, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ?? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: INPUT_SWAP.vhd +-- / / Date Last Modified: 14 February 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: INPUT_SWAP +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Input Order Swap Module for Systolic FFT +-- The module takes N samples, I'length per clock, in natural input order +-- and outputs them in natural transposed order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity INPUT_SWAP is + generic(N:INTEGER; -- N must be a power of 2 + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + USE_CB:BOOLEAN:=TRUE); -- if FALSE use alternate architecture + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; -- I'length must be a divisor of N, so it is also a power of 2 + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end INPUT_SWAP; + +architecture TEST of INPUT_SWAP is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs in last stage + + function RS(K:INTEGER) return STRING is + begin + if K) of CFIXED_VECTOR(I'range); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + + i0:if USE_CB or (L2N<=2*L2R) generate + constant SIZE:INTEGER:=L2N/L2R; -- floor(LOG2(N)/LOG2(RADIX)) + + signal V:BOOLEAN_VECTOR(0 to SIZE-1); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE-1)(SI'range); +--2008 signal D:CFIXED_MATRIX(0 to SIZE-1)(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:UNSIGNED_VECTOR(0 to SIZE-1); + signal D:iCFIXED_MATRIX(0 to SIZE-1); + begin + D(D'low)<=I; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-2 generate + bc:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>RADIX**K, + INPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K/RADIX), -- this helps reduce + OUTPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K mod RADIX**(SIZE-2)), -- RAM count and + SHORTEN_VO_BY=>(RADIX-1)*RADIX**K mod ((RADIX-1)*RADIX**(SIZE-2))) -- latency by N/RADIX/RADIX-1 clocks + port map(CLK=>CLK, + I=>D(K), + VI=>V(K), + SI=>S(K), + O=>D(K+1), + VO=>V(K+1), + SO=>S(K+1)); + end generate; +--Last stage, it becomes a trivial assignment if F=0 + bl:block + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SI'range); + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + lj:for J in OV'range generate +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin + bc:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>RADIX**(SIZE-1)) + port map(CLK=>CLK, +--2008 I=>D(D'high)(I'low+G*J+0 to I'low+G*J+G-1), + I=>D(D'high)(I'length/H*(J+1)-1+I'low downto I'length/H*J+I'low), + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>OV(J), + SO=>OS(J)); + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(K); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+1)-1+OO'low downto O'length/SSR*K+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); + end block; +--2008 end; + end generate; +--2008 else generate + i1:if (not USE_CB) and (L2N>2*L2R) generate + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + signal WSEL:UNSIGNED(LOG2(WCNT'length)-1 downto 0):=TO_UNSIGNED(0,LOG2(RCNT'length)); + signal RSEL:UNSIGNED(LOG2(RCNT'length)-1 downto 0):=TO_UNSIGNED(L2N-2*L2R,LOG2(RCNT'length)); +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal OV:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + if RSEL'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + WA<=ROTATE_LEFT(WCNT,TO_INTEGER(WSEL)); + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + RA<=ROTATE_LEFT(RCNT,TO_INTEGER(RSEL)); + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); + IO<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>OV); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+5) + port map(CLK=>CLK, + I=>SI, + O=>S); + + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>IO, + VI=>OV, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SYSTOLIC_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SYSTOLIC_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Systolic FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity SYSTOLIC_FFT is + generic(N:INTEGER; + SSR:INTEGER; --93 + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end SYSTOLIC_FFT; + +architecture TEST of SYSTOLIC_FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB and PARFFT in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs and PARFFTsin last stage + constant SIZE:INTEGER:=(L2N-1)/L2R; -- ceil(LOG2(N)/LOG2(RADIX)), number of stages +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/2/SSR-(I'high+1)/2/SSR; + +-- constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((SIZE-1)*L2R,BIT_GROWTH); + constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); +--2008 signal D:CFIXED_MATRIX(0 to SIZE)(I'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(O'range); -- unconstrained array of CFIXED_VECTOR + signal D:CFIXED_MATRIX(0 to SIZE); + signal V:BOOLEAN_VECTOR(0 to SIZE); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE)(SI'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); --93 + signal S:UNSIGNED_VECTOR(0 to SIZE); + +-- constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(L2N,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal OO:CFIXED_VECTOR(O'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal OO:CFIXED_VECTOR(O'range); +begin +--2008 lj:for J in I'range generate +--2008 D(D'low)(J)<=RESIZE(I(J),D(D'low)(J)); + lj:for J in 0 to SSR-1 generate + D(D'low)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(I,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-1 generate + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(K*L2R,BIT_GROWTH); + constant XO:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((K+1)*L2R,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal DM,DB,DO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XO downto I(I'low).RE'low),IM(I(I'low).IM'high+XO downto I(I'low).IM'low)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal DM,DB,DO:CFIXED_VECTOR(I'high+2*SSR*XO downto I'low); + signal VM,VB:BOOLEAN; + signal SM,SB:UNSIGNED(SI'range); + begin +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(K)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(K),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, --93 + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(K), + SI=>S(K), + O=>DM, + VO=>VM, + SO=>SM); + cm:entity work.CM3FFT generic map(N=>N/(RADIX**K), + RADIX=>RADIX, --93 + INV_FFT=>FALSE, + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DM, + VI=>VM, + SI=>SM, + O=>DB, + VO=>VB, + SO=>SB); + + bc:entity work.CB generic map(SSR=>RADIX, --93 + F=>F*BOOLEAN'pos(K=SIZE-1), + PACKING_FACTOR=>N/(RADIX**(K+2))*BOOLEAN'pos(KBRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DB, + VI=>VB, + SI=>SB, + O=>DO, + VO=>V(K+1), + SO=>S(K+1)); +--2008 lo:for J in 0 to I'length-1 generate +--2008 D(K+1)(J)<=RESIZE(DO(DO'low+J),D(K+1)(J)); + lo:for J in 0 to SSR-1 generate + D(K+1)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(DO,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + end generate; +--last PARFFT stage +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(D'high)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(D'high),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, + F=>F, + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>VO, + SO=>SO); + lo:for J in 0 to H-1 generate + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(OO'low+K+G*J); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+G*J+1)-1+OO'low downto O'length/SSR*(K+G*J)+OO'low); + end generate; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DS.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DS +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Transposed Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DS is -- LATENCY=0 when N=2*SSR else LATENCY=N/SSR+1 + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DS; + +architecture TEST of DS is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + + function RS(K:INTEGER) return STRING is + begin + if K) of UNSIGNED(RCNT'range); --93 + function IDENTITY(K:INTEGER) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(0 to K-1);--93 (LOG2(K)-1 downto 0); + begin + for J in RESULT'range loop + RESULT(J):=TO_UNSIGNED(J,RESULT(J)'length); + end loop; + return RESULT; + end; + + function PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT((A'length/L2R-1-J)*L2R+K+F):=A(J*L2R+K); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(K):=A(A'length/L2R*L2R+K); + end loop; + end loop; + return RESULT; + end; + + function INVERSE_PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT(J*L2R+K):=A((A'length/L2R-1-J)*L2R+K+F); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(A'length/L2R*L2R+K):=A(K); + end loop; + end loop; + return RESULT; + end; + +--2008 signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1)(LOG2(WCNT'length)-1 downto 0):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); +--2008 signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1)(LOG2(RCNT'length)-1 downto 0):=IDENTITY(RCNT'length); + signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); + signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1):=IDENTITY(RCNT'length); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i0:if L2N-L2R<2 generate + O<=I; + VO<=VI; + SO<=SI; +--2008 else generate + end generate; + i1:if L2N-L2R>=2 generate + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + RSEL<=PERMUTE(WSEL); + end if; + RCNT<=RCNT+1; + else + RCNT<=(others=>'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in WCNT'range loop + WA(K)<=WCNT(TO_INTEGER(WSEL(K))); + end loop; + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in RCNT'range loop + RA(K)<=RCNT(TO_INTEGER(RSEL(K))); + end loop; + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + type iCFIXED_MATRIX is array(NATURAL range <>) of CFIXED_VECTOR(I'range); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); +--2008 O(K)<=Q; + O<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>VO); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX+1) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DSN.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DSN +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Natural Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DSN is + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DSN; + +architecture TEST of DSN is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + constant H:INTEGER:=RADIX/G; +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i1:if L2N<2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SI'range); + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SO'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SO'range); --93 + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + sd:entity work.DS generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + lk:for K in 0 to H-1 generate +----2008 signal II,OO:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal II,OO:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + begin + li:for J in 0 to G-1 generate +--2008 II(J)<=IO(IO'low+K+H*J); + II(I'length/SSR*(J+1)-1+II'low downto I'length/SSR*J+II'low)<=IO(I'length/SSR*(K+H*J+1)-1+I'low downto I'length/SSR*(K+H*J)+I'low); + end generate; + ci:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OO, + VO=>OV(K), + SO=>OS(K)); + lo:for J in 0 to G-1 generate +----2008 O(O'low+K*G+J)<=OO(J); + O(O'length/SSR*(K*G+J+1)-1+O'low downto O'length/SSR*(K*G+J)+O'low)<=OO(O'length/SSR*(J+1)-1+OO'low downto O'length/SSR*J+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); +--2008 end; + end generate; +--2008 elsif L2N=2*L2R generate + i2:if L2N=2*L2R generate + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>O, + VO=>VO, + SO=>SO); +--2008 else generate + end generate; + i3:if L2N>2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>N/RADIX/RADIX, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + + sd:entity work.DS generic map(N=>N/RADIX, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>IO, + VI=>V, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: VECTOR_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: VECTOR_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Top Level Test Module for SYSTOLIC_FFT +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity VECTOR_FFT is + generic(SSR:INTEGER:=8;--4; + N:INTEGER:=16384;--8192;--4096;--1024; + I_high:INTEGER:=0; + I_low:INTEGER:=-17; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; +--2008 I:in CFIXED_VECTOR(0 to RADIX-1)(RE(I_high downto I_low),IM(I_high downto I_low)); + I:in CFIXED_VECTOR(SSR*2*(I_high-I_low+1)-1 downto 0); + VI:in BOOLEAN; + SI:in UNSIGNED(LOG2(N)-1 downto 0); +--2008 O:out CFIXED_VECTOR(0 to RADIX-1)(RE(O_high downto O_low),IM(O_high downto O_low)); + O:out CFIXED_VECTOR(SSR*2*(O_high-O_low+1)-1 downto 0); + VO:out BOOLEAN; + SO:out UNSIGNED(LOG2(N)-1 downto 0)); +end VECTOR_FFT; + +architecture TEST of VECTOR_FFT is + function TO_SFIXED(S:STD_LOGIC_VECTOR;I:SFIXED) return SFIXED is + variable R:SFIXED(I'range); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + + function TO_STD_LOGIC_VECTOR(S:SFIXED) return STD_LOGIC_VECTOR is + variable R:STD_LOGIC_VECTOR(S'length-1 downto 0); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + +--2008 signal II:CFIXED_VECTOR(I'range)(RE(I_high downto I_low),IM(I_high downto I_low)); + signal II:CFIXED_VECTOR(I'range); + signal V,VOFFT,VODS:BOOLEAN; + signal S,SFFT,SODS:UNSIGNED(SI'range); +--2008 signal OFFT,ODS:CFIXED_VECTOR(O'range)(RE(O_high downto O_low),IM(O_high downto O_low)); + signal OFFT,ODS:CFIXED_VECTOR(O'range); +begin + u0:entity work.INPUT_SWAP generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>II, + VO=>V, + SO=>S); + + u1:entity work.SYSTOLIC_FFT generic map(N=>N, + SSR=>SSR, --93 + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OFFT, + VO=>VOFFT, + SO=>SFFT); + + u2:entity work.DSN generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>OFFT, + VI=>VOFFT, + SI=>SFFT, + O=>O, + VO=>VO, + SO=>SO); +-- O<=OFFT; +-- VO<=VOFFT; +-- SO<=SFFT; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.COMPLEX_FIXED_PKG.all; + +entity WRAPPER_VECTOR_FFT is + generic(SSR:INTEGER:=8; + N:INTEGER:=512; + L2N:INTEGER:=9; -- L2N must be set equal to log2(N)!!! + I_high:INTEGER:=0; + I_low:INTEGER:=-15; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-15; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + CE:in STD_LOGIC:='1'; -- not used, for SysGen only + I:in STD_LOGIC_VECTOR(2*SSR*(I_high-I_low+1)-1 downto 0); + VI:in STD_LOGIC; + SI:in STD_LOGIC_VECTOR(L2N-1 downto 0):=(L2N-1 downto 0=>'0'); -- can be left unconnected if internal scaling is not used, must be a (LOG2(N)-1 downto 0) port + O:out STD_LOGIC_VECTOR(2*SSR*(O_high-O_low+1)-1 downto 0); + VO:out STD_LOGIC; + SO:out STD_LOGIC_VECTOR(L2N-1 downto 0)); -- can be left unconnected if internal overflow is not possible, must be a (LOG2(N)-1 downto 0) port +end WRAPPER_VECTOR_FFT; + +architecture WRAPPER of WRAPPER_VECTOR_FFT is +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if KSSR, + N=>N, + I_high=>I_high, + I_low=>I_low, + W_high=>W_high, + W_low=>W_low, + O_high=>O_high, + O_low=>O_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB, + DSP48E=>DSP48E) -- 1 for DSP48E1, 2 for DSP48E2 + port map(CLK=>CLK, + I=>II, + VI=>VII, + SI=>SII, + O=>OO, + VO=>VOO, + SO=>SOO); + O<=STD_LOGIC_VECTOR(OO); + VO<='1' when VOO else '0'; + SO<=STD_LOGIC_VECTOR(SOO); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity WRAPPER_VECTOR_FFT_c5415935ecc00ff9eff39575a72e6e61 is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 6; + N : integer := 64; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(5 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(5 downto 0); + CLK : in std_logic; + CE : in std_logic + ); +end WRAPPER_VECTOR_FFT_c5415935ecc00ff9eff39575a72e6e61; +architecture structural of WRAPPER_VECTOR_FFT_c5415935ecc00ff9eff39575a72e6e61 is + signal I_net : std_logic_vector(255 downto 0); + signal VI_net : std_logic; + signal SI_net : std_logic_vector(5 downto 0); + signal O_net : std_logic_vector(431 downto 0); + signal VO_net : std_logic; + signal SO_net : std_logic_vector(5 downto 0); + signal CLK_net : std_logic; + signal CE_net : std_logic; + component WRAPPER_VECTOR_FFT is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 6; + N : integer := 64; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(5 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(5 downto 0); + CLK : in std_logic; + CE : in std_logic + ); + end component; +begin + I_net <= I; + VI_net <= VI; + SI_net <= SI; + O <= O_net; + VO <= VO_net; + SO <= SO_net; + CLK_net <= CLK; + CE_net <= CE; + WRAPPER_VECTOR_FFT_inst : WRAPPER_VECTOR_FFT + generic map( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 6, + N => 64, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map( + I => I_net, + VI => VI_net, + SI => SI_net, + O => O_net, + VO => VO_net, + SO => SO_net, + CLK => CLK_net, + CE => CE_net + ); +end structural; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlslice.vhd +-- +-- Description : VHDL description of a block that sets the output to a +-- specified range of the input bits. The output is always +-- set to an unsigned type with it's binary point at zero. +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x64_xlslice is + generic ( + new_msb : integer := 9; -- position of new msb + new_lsb : integer := 1; -- position of new lsb + x_width : integer := 16; -- Width of x input + y_width : integer := 8); -- Width of y output + port ( + x : in std_logic_vector (x_width-1 downto 0); + y : out std_logic_vector (y_width-1 downto 0)); +end ssr_8x64_xlslice; + +architecture behavior of ssr_8x64_xlslice is +begin + y <= x(new_msb downto new_lsb); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_384683215a is + port ( + in0 : in std_logic_vector((16 - 1) downto 0); + in1 : in std_logic_vector((16 - 1) downto 0); + y : out std_logic_vector((32 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_384683215a; +architecture behavior of sysgen_concat_384683215a +is + signal in0_1_23: unsigned((16 - 1) downto 0); + signal in1_1_27: unsigned((16 - 1) downto 0); + signal y_2_1_concat: unsigned((32 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_53c8e6f5a2 is + port ( + input_port : in std_logic_vector((16 - 1) downto 0); + output_port : out std_logic_vector((16 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_53c8e6f5a2; +architecture behavior of sysgen_reinterpret_53c8e6f5a2 +is + signal input_port_1_40: signed((16 - 1) downto 0); + signal output_port_5_5_force: unsigned((16 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_signed(input_port); + output_port_5_5_force <= signed_to_unsigned(input_port_1_40); + output_port <= unsigned_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_d7a483898b is + port ( + input_port : in std_logic_vector((27 - 1) downto 0); + output_port : out std_logic_vector((27 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_d7a483898b; +architecture behavior of sysgen_reinterpret_d7a483898b +is + signal input_port_1_40: unsigned((27 - 1) downto 0); + signal output_port_5_5_force: signed((27 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_unsigned(input_port); + output_port_5_5_force <= unsigned_to_signed(input_port_1_40); + output_port <= signed_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_c0fcf025b9 is + port ( + in0 : in std_logic_vector((32 - 1) downto 0); + in1 : in std_logic_vector((32 - 1) downto 0); + in2 : in std_logic_vector((32 - 1) downto 0); + in3 : in std_logic_vector((32 - 1) downto 0); + in4 : in std_logic_vector((32 - 1) downto 0); + in5 : in std_logic_vector((32 - 1) downto 0); + in6 : in std_logic_vector((32 - 1) downto 0); + in7 : in std_logic_vector((32 - 1) downto 0); + y : out std_logic_vector((256 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_c0fcf025b9; +architecture behavior of sysgen_concat_c0fcf025b9 +is + signal in0_1_23: unsigned((32 - 1) downto 0); + signal in1_1_27: unsigned((32 - 1) downto 0); + signal in2_1_31: unsigned((32 - 1) downto 0); + signal in3_1_35: unsigned((32 - 1) downto 0); + signal in4_1_39: unsigned((32 - 1) downto 0); + signal in5_1_43: unsigned((32 - 1) downto 0); + signal in6_1_47: unsigned((32 - 1) downto 0); + signal in7_1_51: unsigned((32 - 1) downto 0); + signal y_2_1_concat: unsigned((256 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + in2_1_31 <= std_logic_vector_to_unsigned(in2); + in3_1_35 <= std_logic_vector_to_unsigned(in3); + in4_1_39 <= std_logic_vector_to_unsigned(in4); + in5_1_43 <= std_logic_vector_to_unsigned(in5); + in6_1_47 <= std_logic_vector_to_unsigned(in6); + in7_1_51 <= std_logic_vector_to_unsigned(in7); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39) & unsigned_to_std_logic_vector(in5_1_43) & unsigned_to_std_logic_vector(in6_1_47) & unsigned_to_std_logic_vector(in7_1_51)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/synth_reg.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/synth_reg.vhd new file mode 100644 index 0000000..770ff70 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/synth_reg.vhd @@ -0,0 +1,95 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register without +-- an init value and a clear. SRLC32E components are used. The +-- initial value is always 0 +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRLC32s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg; + +architecture structural of synth_reg is + component srlc33e + generic (width : integer:=16; + latency : integer :=8); + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); + end component; + + function calc_num_srlc33es (latency : integer) + return integer + is + variable remaining_latency : integer; + variable result : integer; + begin + result := latency / 33; + + remaining_latency := latency - (result * 33); + -- If latency is not an even multiple of 33 then add one more + -- srlc33e to the pipeline + if (remaining_latency /= 0) then + result := result + 1; + end if; + + return result; + end; + + + constant complete_num_srlc33es : integer := latency / 33; + constant num_srlc33es : integer := calc_num_srlc33es(latency); + constant remaining_latency : integer := latency - (complete_num_srlc33es * 33); + -- Array for std_logic_vectors + type register_array is array (num_srlc33es downto 0) of + std_logic_vector(width-1 downto 0); + signal z : register_array; + +begin + + z(0) <= i; + complete_ones : if complete_num_srlc33es > 0 generate + srlc33e_array: for i in 0 to complete_num_srlc33es-1 generate + delay_comp : srlc33e + generic map (width => width, + latency => 33) + port map (clk => clk, + ce => ce, + d => z(i), + q => z(i+1)); + + end generate; + end generate; + + partial_one : if remaining_latency > 0 generate + last_srlc33e : srlc33e + generic map (width => width, + latency => remaining_latency) + port map (clk => clk, + ce => ce, + d => z(num_srlc33es-1), + q => z(num_srlc33es)); + end generate; + o <= z(num_srlc33es); +end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/synth_reg_reg.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/synth_reg_reg.vhd new file mode 100644 index 0000000..5d837de --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/synth_reg_reg.vhd @@ -0,0 +1,64 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_reg.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRL16s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg_reg; + +architecture behav of synth_reg_reg is + type reg_array_type is array (latency downto 0) of std_logic_vector(width -1 downto 0); + signal reg_bank : reg_array_type := (others => (others => '0')); + signal reg_bank_in : reg_array_type := (others => (others => '0')); + attribute syn_allow_retiming : boolean; + attribute syn_srlstyle : string; + attribute syn_allow_retiming of reg_bank : signal is true; + attribute syn_allow_retiming of reg_bank_in : signal is true; + attribute syn_srlstyle of reg_bank : signal is "registers"; + attribute syn_srlstyle of reg_bank_in : signal is "registers"; +begin -- behav + + latency_eq_0: if latency = 0 generate + o <= i; + end generate latency_eq_0; + + latency_gt_0: if latency >= 1 generate + o <= reg_bank(latency); + reg_bank(0) <= i; + + sync_loop: for sync_idx in latency downto 1 generate + sync_proc: process (clk) + begin -- process sync_proc + if clk'event and clk = '1' then -- rising clock edge + if clr = '1' then + reg_bank(sync_idx) <= (others => '0'); + elsif ce = '1' then + reg_bank(sync_idx) <= reg_bank(sync_idx-1); + end if; + end if; + end process sync_proc; + end generate sync_loop; + end generate latency_gt_0; + end behav; + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/synth_reg_w_init.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/synth_reg_w_init.vhd new file mode 100644 index 0000000..34bfa2e --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/synth_reg_w_init.vhd @@ -0,0 +1,98 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_w_init.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register with +-- an initial value. The register has clr and ce pins and +-- is implemented using flip-flops (i.e., not SRL16s). +-- +-- Mod. History : Delayed input .1 ns so that there isn't a setup +-- violation in the fdse or fdre Unisim models. +-- : Changed VHDL so that initial register is passed as a bit +-- vector generic value, instead of the const_pkg. +-- +-- Mod. Dates : 8/10/2001 +-- 3/19/2003 +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000"; + latency: integer := 1 + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end synth_reg_w_init; + +architecture structural of synth_reg_w_init is + component single_reg_w_init + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; -- end single_reg_w_init + + -- 1D array used to connect all the register together + signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); + signal dly_clr: std_logic; +begin + latency_eq_0: if (latency = 0) generate + o <= i; + end generate; -- end latency_eq_0 + + latency_gt_0: if (latency >= 1) generate + -- Delayed input 200 ps so that there isn't a setup violation in the + -- fdse or fdre Unisim models + dly_i((latency + 1) * width - 1 downto latency * width) <= i + after 200 ps; + dly_clr <= clr after 200 ps; + + fd_array: for index in latency downto 1 generate + reg_comp: single_reg_w_init + generic map ( + width => width, + init_index => init_index, + init_value => init_value + ) + port map ( + clk => clk, + i => dly_i((index + 1) * width - 1 downto index * width), + o => dly_i(index * width - 1 downto (index - 1) * width), + ce => ce, + clr => dly_clr + ); + end generate; -- end fd_array + + o <= dly_i(width - 1 downto 0); + end generate; -- end latency_gt_0 +end structural; + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/xlclockdriver_rd.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/xlclockdriver_rd.vhd new file mode 100644 index 0000000..92017d4 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssr_fft_8x64/xlclockdriver_rd.vhd @@ -0,0 +1,338 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlclockdriver.vhd +-- +-- Date : 10/1/99 +-- +-- Description : VHDL description of a clock enable generator block. +-- This code is synthesizable. +-- +-- Assumptions : period >= 1 +-- +-- Mod. History : Removed one shot & OR gate +-- If period is power of 2 a 1-bit smaller counter +-- is used and no sync clear +-- : Logic needed for use_bufg generic added +-- : Initial ce output is now 0 instead of 1 +-- Enable pulse now occurs at the end of the sample +-- period, instead of at the start +-- : Added pipeline registers +-- : added OR gate for sysclr to work properly +-- +-- Mod. Dates : 7/26/2001 +-- : 8/05/2001 +-- : 1/02/2002 +-- : 11/30/2004 +-- : 4/11/2005 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +entity xlclockdriver is + generic ( + period: integer := 2; + log_2_period: integer := 0; + pipeline_regs: integer := 5; + use_bufg: integer := 0 + ); + port ( + sysclk: in std_logic; + sysclr: in std_logic; + sysce: in std_logic; + clk: out std_logic; + clr: out std_logic; + ce: out std_logic; + ce_logic: out std_logic + ); +end xlclockdriver; + +architecture behavior of xlclockdriver is + component bufg + port ( + i: in std_logic; + o: out std_logic + ); + end component; + + component synth_reg_w_init + generic ( + width: integer; + init_index: integer; + init_value: bit_vector; + latency: integer + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; + + -- Returns the size of an unsigned integer + -- if power_of_2 is true return value is one less + function size_of_uint(inp: integer; power_of_2: boolean) + return integer + is + constant inp_vec: std_logic_vector(31 downto 0) := + integer_to_std_logic_vector(inp,32, xlUnsigned); + variable result: integer; + begin + result := 32; + for i in 0 to 31 loop + if inp_vec(i) = '1' then + result := i; + end if; + end loop; + if power_of_2 then + return result; + else + return result+1; + end if; + end; + + -- Returns boolean which says if 'inp' is a power of two + function is_power_of_2(inp: std_logic_vector) + return boolean + is + constant width: integer := inp'length; + variable vec: std_logic_vector(width - 1 downto 0); + variable single_bit_set: boolean; + variable more_than_one_bit_set: boolean; + variable result: boolean; + begin + vec := inp; + single_bit_set := false; + more_than_one_bit_set := false; + + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if width > 0 then + for i in 0 to width - 1 loop + if vec(i) = '1' then + if single_bit_set then + more_than_one_bit_set := true; + end if; + single_bit_set := true; + end if; + end loop; + end if; + if (single_bit_set and not(more_than_one_bit_set)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Returns initial value for pipeline registers + function ce_reg_init_val(index, period : integer) + return integer + is + variable result: integer; + begin + result := 0; + if ((index mod period) = 0) then + result := 1; + end if; + return result; + end; + + -- Returns the remainder(num_pipeline_regs/period) + 1 + function remaining_pipe_regs(num_pipeline_regs, period : integer) + return integer + is + variable factor, result: integer; + begin + factor := (num_pipeline_regs / period); + result := num_pipeline_regs - (period * factor) + 1; + return result; + end; + + -- Calculate the min + function sg_min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + constant max_pipeline_regs : integer := 8; + constant pipe_regs : integer := 5; + + -- Check if requested pipeline regs are greater than the max amount + constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); + constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); + + constant period_floor: integer := max(2, period); + constant power_of_2_counter: boolean := + is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); + constant cnt_width: integer := + size_of_uint(period_floor, power_of_2_counter); + constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); + + signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); + signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); + signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0); + signal internal_ce: std_logic_vector(0 downto 0); + signal internal_ce_logic: std_logic_vector(0 downto 0); + signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); +begin + -- Pass through the system clock and clear + clk <= sysclk; + clr <= sysclr; + + -- Clock Number Counter + cntr_gen: process(sysclk) + begin + if sysclk'event and sysclk = '1' then + if (sysce = '1') then + if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then + clk_num <= (others => '0'); + else + clk_num <= clk_num + 1; + end if; + end if; + end if; + end process; + + -- Clear logic for counter + clr_gen: process(clk_num, sysclr) + begin + if power_of_2_counter then + cnt_clr(0) <= sysclr; + else + -- Counter does not reset when clk_num = a power of 2 + if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 + or sysclr = '1') then + cnt_clr(0) <= '1'; + else + cnt_clr(0) <= '0'; + end if; + end if; + end process; + + clr_reg: synth_reg_w_init + generic map ( + width => 1, + init_index => 0, + init_value => b"0000", + latency => 1 + ) + port map ( + i => cnt_clr, + ce => sysce, + clr => sysclr, + clk => sysclk, + o => cnt_clr_dly + ); + + -- Clock enable generation + pipelined_ce : if period > 1 generate + ce_gen: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec(num_pipeline_regs) <= '1'; + else + ce_vec(num_pipeline_regs) <= '0'; + end if; + end process; + ce_pipeline: for index in num_pipeline_regs downto 1 generate + ce_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec(index-1 downto index-1) + ); + end generate; -- i + internal_ce <= ce_vec(0 downto 0); + end generate; + + -- Clock enable generation + pipelined_ce_logic: if period > 1 generate + ce_gen_logic: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec_logic(num_pipeline_regs) <= '1'; + else + ce_vec_logic(num_pipeline_regs) <= '0'; + end if; + end process; + ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate + ce_logic_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec_logic(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec_logic(index-1 downto index-1) + ); + end generate; -- i + internal_ce_logic <= ce_vec_logic(0 downto 0); + end generate; + + + use_bufg_true: if period > 1 and use_bufg = 1 generate + -- Clock enable with bufg + ce_bufg_inst: bufg + port map ( + i => internal_ce(0), + o => ce + ); + ce_bufg_inst_logic: bufg + port map ( + i => internal_ce_logic(0), + o => ce_logic + ); + end generate; + + use_bufg_false: if period > 1 and (use_bufg = 0) generate + -- Clock enable without bufg + ce <= internal_ce(0) and sysce; + ce_logic <= internal_ce_logic(0) and sysce; + end generate; + + generate_system_clk: if period = 1 generate + ce <= sysce; + ce_logic <= sysce; + end generate; +end architecture behavior; + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssrfft_8x64_sync.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssrfft_8x64_sync.vhd new file mode 100644 index 0000000..606006c --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/ssrfft_8x64_sync.vhd @@ -0,0 +1,294 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity ssrfft_8x64_sync is + Generic + ( + NFFT : Integer := 16; + SSR : Integer := 4; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (2*SSR*B-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end entity; + +architecture rtl of ssrfft_8x64_sync is + +-- Framing. +component framing is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4; + + -- Bits. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- Synced outputs. + tdata : out std_logic_vector (2*SSR*B-1 downto 0); + tvalid : out std_logic + ); +end component; + +-- TLAST Generator. +component tlast_gen is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4 + ); + Port + ( + -- Input reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Input enable. + en : in std_logic; + + -- TLAST input/output. + o_tlast : out std_logic + ); +end component; + +-- SSR FFT 8x64. +component ssr_8x64 is + port ( + -- Clock signal. + clk : in std_logic; + + -- Input data. + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_scale : in std_logic_vector( 6-1 downto 0 ); + + -- Output data. + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_scale : out std_logic_vector( 6-1 downto 0 ) + ); +end component; + +-- Vectors with individual I,Q samples. +type data_v is array (SSR-1 downto 0) of std_logic_vector (B-1 downto 0); +signal din_iv : data_v; +signal din_qv : data_v; +signal dout_iv : data_v; +signal dout_qv : data_v; + +-- Vector with individual I,Q samples (fft out full precision). +type data_vf is array (SSR-1 downto 0) of std_logic_vector (27-1 downto 0); +signal dout_ivf : data_vf; +signal dout_qvf : data_vf; + +-- I,Q parts of input. +signal din_i : std_logic_vector (SSR*B-1 downto 0); +signal din_q : std_logic_vector (SSR*B-1 downto 0); + +-- Framing block signals. +signal framing_tdata : std_logic_vector (2*SSR*B-1 downto 0); +signal framing_tvalid : std_logic; + +-- FFT scale. +signal o_scale : std_logic_vector (5 downto 0); + +-- FFT output valid/last. +signal o_axis_tvalid : std_logic; +signal o_axis_tlast : std_logic; + +-- FFT data output. +signal o_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); + +-- Registers. +signal scale_reg_i : std_logic_vector (5 downto 0); +signal qout_reg_i : unsigned (3 downto 0); + +begin + +-- Registers. +scale_reg_i <= SCALE_REG (5 downto 0); + +-- Full-precision output: 27 bits. Required output: 16 bits. +-- Quantization selection from 0 to 11. +qout_reg_i <= (others => '0') when ( unsigned(QOUT_REG) > to_unsigned(11,QOUT_REG'length) ) else + unsigned(QOUT_REG(3 downto 0)); + +-- Input/output data to vector. +GEN: for I in 0 to SSR-1 generate + -- Input data to vector. + din_iv(I) <= framing_tdata(I*2*B+B-1 downto I*2*B ); + din_qv(I) <= framing_tdata(I*2*B+2*B-1 downto I*2*B+B ); + + -- Quantization selection. + dout_iv(I) <= dout_ivf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + dout_qv(I) <= dout_qvf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + + -- Output data to vector. + o_axis_tdata(I*2*B+B-1 downto I*2*B ) <= dout_iv(I); + o_axis_tdata(I*2*B+2*B-1 downto I*2*B+B ) <= dout_qv(I); +end generate GEN; + +-- Framing. +framing_i : framing + Generic map + ( + -- SSR and FFT Length. + NFFT => NFFT , + SSR => SSR , + + -- Bits. + B => B + ) + Port map + ( + -- Reset and clock. + aresetn => aresetn , + aclk => aclk , + + -- AXIS Slave. + s_axis_tdata => s_axis_tdata , + s_axis_tlast => s_axis_tlast , + s_axis_tvalid => s_axis_tvalid , + + -- Synced outputs. + tdata => framing_tdata , + tvalid => framing_tvalid + ); + +-- TLAST Generator. +tlast_gen_i : tlast_gen + Generic map + ( + -- SSR and FFT Length. + NFFT => NFFT , + SSR => SSR + ) + Port map + ( + -- Input reset and clock. + rstn => aresetn , + clk => aclk , + + -- Input enable. + en => o_axis_tvalid , + + -- TLAST input/output. + o_tlast => o_axis_tlast + ); + +-- SSR FFT 8x1024. +ssr_8x64_i : ssr_8x64 + port map ( + -- Clock signal. + clk => aclk , + + -- Input data. + i_re_0 => din_iv(0) , + i_re_1 => din_iv(1) , + i_re_2 => din_iv(2) , + i_re_3 => din_iv(3) , + i_re_4 => din_iv(4) , + i_re_5 => din_iv(5) , + i_re_6 => din_iv(6) , + i_re_7 => din_iv(7) , + i_im_0 => din_qv(0) , + i_im_1 => din_qv(1) , + i_im_2 => din_qv(2) , + i_im_3 => din_qv(3) , + i_im_4 => din_qv(4) , + i_im_5 => din_qv(5) , + i_im_6 => din_qv(6) , + i_im_7 => din_qv(7) , + i_valid(0) => framing_tvalid , + i_scale => scale_reg_i , + + -- Output data. + o_re_0 => dout_ivf(0) , + o_re_1 => dout_ivf(1) , + o_re_2 => dout_ivf(2) , + o_re_3 => dout_ivf(3) , + o_re_4 => dout_ivf(4) , + o_re_5 => dout_ivf(5) , + o_re_6 => dout_ivf(6) , + o_re_7 => dout_ivf(7) , + o_im_0 => dout_qvf(0) , + o_im_1 => dout_qvf(1) , + o_im_2 => dout_qvf(2) , + o_im_3 => dout_qvf(3) , + o_im_4 => dout_qvf(4) , + o_im_5 => dout_qvf(5) , + o_im_6 => dout_qvf(6) , + o_im_7 => dout_qvf(7) , + o_valid(0) => o_axis_tvalid , + o_scale => o_scale + ); + +-- Assign outputs. +m_axis_tdata <= o_axis_tdata; +m_axis_tlast <= o_axis_tlast; +m_axis_tvalid <= o_axis_tvalid; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/tb.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/tb.vhd new file mode 100644 index 0000000..1303dec --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/tb.vhd @@ -0,0 +1,301 @@ +-- %%%%%%%%%%%%%%%%%%% Test Description %%%%%%%%%%%%%%%%%%%%% +-- +-- This test is for understanding if moving tvalid makes the +-- block to generate incorrect tlast at the output. +-- +-- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_TEXTIO.ALL; +use STD.TEXTIO.ALL; + +entity tb is +end tb; + +architecture rtl of tb is + +-- DUT. +component ssrfft_8x64_sync is + Generic + ( + NFFT : Integer := 16; + SSR : Integer := 4; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (2*SSR*B-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end component; + +constant NFFT : Integer := 64; +constant SSR : Integer := 8; +constant B : Integer := 16; + +signal aresetn : std_logic; +signal aclk : std_logic; +signal s_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0) := (others => '0'); +signal s_axis_tlast : std_logic := '0'; +signal s_axis_tvalid : std_logic := '0'; + +signal m_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); +signal m_axis_tlast : std_logic; +signal m_axis_tvalid : std_logic; + +signal SCALE_REG : std_logic_vector (31 downto 0) := (others => '0'); +signal QOUT_REG : std_logic_vector (31 downto 0) := std_logic_vector(to_unsigned(0,32)); + +-- TB control. +signal rd_start : std_logic := '0'; + +signal i_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); + +signal o_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); + +begin + +-- DUT. +DUT : ssrfft_8x64_sync + Generic map + ( + NFFT => NFFT , + SSR => SSR , + B => B + ) + Port map + ( + -- Reset and clock. + aresetn => aresetn , + aclk => aclk , + + -- AXIS Slave. + s_axis_tdata => s_axis_tdata , + s_axis_tlast => s_axis_tlast , + s_axis_tvalid => s_axis_tvalid , + + -- AXIS Master. + m_axis_tdata => m_axis_tdata , + m_axis_tlast => m_axis_tlast , + m_axis_tvalid => m_axis_tvalid , + + -- Registers. + SCALE_REG => SCALE_REG , + QOUT_REG => QOUT_REG + ); + +-- Input data. +s_axis_tdata <= i_im_7 & i_re_7 & i_im_6 & i_re_6 & i_im_5 & i_re_5 & i_im_4 & i_re_4 & i_im_3 & i_re_3 & i_im_2 & i_re_2 & i_im_1 & i_re_1 & i_im_0 & i_re_0; + +-- Output data. +o_re_0 <= m_axis_tdata (1*B-1 downto 0*B); +o_im_0 <= m_axis_tdata (2*B-1 downto 1*B); +o_re_1 <= m_axis_tdata (3*B-1 downto 2*B); +o_im_1 <= m_axis_tdata (4*B-1 downto 3*B); +o_re_2 <= m_axis_tdata (5*B-1 downto 4*B); +o_im_2 <= m_axis_tdata (6*B-1 downto 5*B); +o_re_3 <= m_axis_tdata (7*B-1 downto 6*B); +o_im_3 <= m_axis_tdata (8*B-1 downto 7*B); +o_re_4 <= m_axis_tdata (9*B-1 downto 8*B); +o_im_4 <= m_axis_tdata (10*B-1 downto 9*B); +o_re_5 <= m_axis_tdata (11*B-1 downto 10*B); +o_im_5 <= m_axis_tdata (12*B-1 downto 11*B); +o_re_6 <= m_axis_tdata (13*B-1 downto 12*B); +o_im_6 <= m_axis_tdata (14*B-1 downto 13*B); +o_re_7 <= m_axis_tdata (15*B-1 downto 14*B); +o_im_7 <= m_axis_tdata (16*B-1 downto 15*B); + +-- Main TB. +process +begin + aresetn <= '0'; + wait for 250 ns; + aresetn <= '1'; + + wait for 3 us; + + rd_start <= '1'; + --wait for 110 ns; + --rd_start <= '0'; + --wait for 220 ns; + --rd_start <= '1'; + --wait for 490 ns; + --rd_start <= '0'; + --wait for 100 ns; + --rd_start <= '1'; + + wait for 20 us; + +end process; + +-- Data process. +process + variable I : Integer := 0; + + begin + + i_re_0 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_1 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_2 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_3 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_4 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_5 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_6 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_re_7 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_0 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_1 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_2 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_3 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_4 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_5 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_6 <= std_logic_vector(to_signed(0,i_re_0'length)); + i_im_7 <= std_logic_vector(to_signed(0,i_re_0'length)); + + for K in 0 to 200 loop + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + i_re_1 <= std_logic_vector(to_signed(10000,i_re_0'length)); + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + i_re_1 <= std_logic_vector(to_signed(0,i_re_0'length)); + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tlast <= '1'; + s_axis_tvalid <= '1'; + --for J in 0 to 2 loop + -- while rd_start = '0' loop + -- wait until rising_edge(aclk); + -- s_axis_tvalid <= '0'; + -- end loop; + -- wait until rising_edge(aclk); + -- s_axis_tlast <= '0'; + -- s_axis_tvalid <= '1'; + -- i_re_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_re_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + -- i_im_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + + -- I := I + 1; + --end loop; + + --while rd_start = '0' loop + -- wait until rising_edge(aclk); + -- s_axis_tvalid <= '0'; + --end loop; + --wait until rising_edge(aclk); + --s_axis_tlast <= '1'; + --s_axis_tvalid <= '1'; + --i_re_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_re_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + --i_im_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + + --I := I + 1; + end loop; + +end process; + +-- Clock. +process +begin + aclk <= '0'; + wait for 5 ns; + aclk <= '1'; + wait for 5 ns; +end process; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/tlast_gen.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/tlast_gen.vhd new file mode 100644 index 0000000..c07cb2e --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fft/tlast_gen.vhd @@ -0,0 +1,61 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity tlast_gen is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4 + ); + Port + ( + -- Input reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Input enable. + en : in std_logic; + + -- TLAST input/output. + o_tlast : out std_logic + ); +end entity; + +architecture rtl of tlast_gen is + +-- Number of transactions. +constant NTRAN : Integer := NFFT/SSR; +constant NTRAN_LOG2 : Integer := Integer(ceil(log2(real(NTRAN)))); + +-- Counter for transactions. +signal cnt : unsigned (NTRAN_LOG2-1 downto 0); + +begin + +-- Registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + cnt <= (others => '0'); + else + if ( en = '1' ) then + if ( cnt < to_unsigned(NTRAN-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + end if; + end if; + end if; + end if; +end process; + +-- Assign outputs. +o_tlast <= '1' when cnt = to_unsigned(NTRAN-1,cnt'length) else + '0'; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/Makefile b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/Makefile new file mode 100644 index 0000000..df6451c --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/Makefile @@ -0,0 +1,21 @@ +all: ipgen copy sedxci clean_proj + +ipgen: fir.tcl + vivado -mode batch -source tcl/ipgen.tcl + +copy: + cp -r `find ./ipgen/ipgen.srcs -type d -name "fir*"` . + cp -r `find ./ipgen/ipgen.gen -name "fir_0.veo"` . + +sedxci: + sed -i -r 's#(../)+(coef/fir.*.coe)#../\2#' `find . -name "fir*.xci"` + +fir.tcl: tcl/fir.tcl.template + ./gen.pl tcl/fir.tcl.template + +clean: clean_proj + rm -rf `find . -type d -name "fir*"` + rm -rf fir*.veo fir.tcl add.tcl + +clean_proj: + rm -rf ipgen vivado* diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/add.tcl b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/add.tcl new file mode 100644 index 0000000..9523c5d --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/add.tcl @@ -0,0 +1,8 @@ +add_files ./fir/fir_0/fir_0.xci +add_files ./fir/fir_1/fir_1.xci +add_files ./fir/fir_2/fir_2.xci +add_files ./fir/fir_3/fir_3.xci +add_files ./fir/fir_4/fir_4.xci +add_files ./fir/fir_5/fir_5.xci +add_files ./fir/fir_6/fir_6.xci +add_files ./fir/fir_7/fir_7.xci diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_0.coe b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_0.coe new file mode 100644 index 0000000..90cedee --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_0.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -409,-1113,14782,1965,1397,-401,0,-481,-393,12156,4247,1154,-459,0,-509,245,9446,6773,767,-499,0,-499,767,6773,9446,245,-509,0,-459,1154,4247,12156,-393,-481,0,-401,1397,1965,14782,-1113,-409,0,-331,1501,4,17203,-1868,-288,12,-259,1480,-1584,19303,-2600,-116,10 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_1.coe b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_1.coe new file mode 100644 index 0000000..c695165 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_1.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -190,1356,-2768,20978,-3243,101,2,-129,1154,-3547,22144,-3726,353,-14,-79,903,-3937,22742,-3979,627,-41,-41,627,-3979,22742,-3937,903,-79,-14,353,-3726,22144,-3547,1154,-129,2,101,-3243,20978,-2768,1356,-190,10,-116,-2600,19303,-1584,1480,-259,12,-288,-1868,17203,4,1501,-331 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_2.coe b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_2.coe new file mode 100644 index 0000000..8a55eee --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_2.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -432,-928,14140,2508,1349,-417,0,-492,-225,11481,4859,1070,-471,0,-510,387,8770,7431,649,-504,0,-491,877,6123,10125,95,-506,0,-446,1228,3650,12825,-567,-468,0,-384,1435,1442,15411,-1301,-383,90,-313,1507,-430,17763,-2056,-249,12,-241,1458,-1918,19765,-2772,-66,9 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_3.coe b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_3.coe new file mode 100644 index 0000000..a5989f5 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_3.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -174,1312,-3001,21320,-3381,161,-1,-116,1095,-3680,22349,-3813,421,-20,-68,835,-3979,22799,-3999,697,-49,-33,558,-3941,22648,-3874,969,-91,-9,288,-3624,21904,-3390,1211,-143,5,43,-3094,20604,-2511,1396,-206,11,-164,-2423,18814,-1224,1496,-277,12,-323,-1679,16624,461,1487,-349 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_4.coe b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_4.coe new file mode 100644 index 0000000..5c3d7af --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_4.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -451,-746,13487,3070,1293,-432,0,-500,-62,10804,5485,978,-482,0,-508,522,8098,8098,522,-508,0,-482,978,5485,10804,-62,-500,0,-432,1293,3070,13487,-746,-451,0,-367,1466,940,16026,-1490,-355,12,-295,1505,-839,18300,-2241,-208,12,-224,1430,-2227,20199,-2937,-13,7 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_5.coe b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_5.coe new file mode 100644 index 0000000..f5b7af0 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_5.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -158,1263,-3208,21629,-3509,223,-5,-103,1033,-3789,22517,-3885,489,-26,-59,766,-3999,22818,-3999,766,-59,-26,489,-3885,22517,-3789,1033,-103,-5,223,-3509,21629,-3208,1263,-158,7,-13,-2937,20199,-2227,1430,-224,12,-208,-2241,18300,-839,1505,-295,12,-355,-1490,16026,940,1466,-367 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_6.coe b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_6.coe new file mode 100644 index 0000000..5e0828d --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_6.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -468,-567,12825,3650,1228,-446,0,-506,95,10125,6123,877,-491,0,-504,649,7431,8770,387,-510,0,-471,1070,4859,11481,-225,-492,0,-417,1349,2508,14140,-928,-432,0,-349,1487,461,16624,-1679,-323,12,-277,1496,-1224,18814,-2423,-164,11,-206,1396,-2511,20604,-3094,43,5 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_7.coe b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_7.coe new file mode 100644 index 0000000..e67b9d3 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/coef/fir_7.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -143,1211,-3390,21904,-3624,288,-9,-91,969,-3874,22648,-3941,558,-33,-49,697,-3999,22799,-3979,835,-68,-20,421,-3813,22349,-3680,1095,-116,-1,161,-3381,21320,-3001,1312,-174,9,-66,-2772,19765,-1918,1458,-241,12,-249,-2056,17763,-430,1507,-313,90,-383,-1301,15411,1442,1435,-384 \ No newline at end of file diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir.tcl b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir.tcl new file mode 100644 index 0000000..df91aaf --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir.tcl @@ -0,0 +1,256 @@ +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_0 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_0.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_0] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_1 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_1.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_1] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_2 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_2.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_2] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_3 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_3.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_3] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_4 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_4.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_4] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_5 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_5.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_5] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_6 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_6.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_6] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_7 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/fir_7.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_7] diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_0.veo b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_0.veo new file mode 100644 index 0000000..b9961ec --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_0.veo @@ -0,0 +1,80 @@ +// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fir_compiler:7.2 +// IP Revision: 18 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fir_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready + .s_axis_data_tlast(s_axis_data_tlast), // input wire s_axis_data_tlast + .s_axis_data_tdata(s_axis_data_tdata), // input wire [31 : 0] s_axis_data_tdata + .s_axis_config_tvalid(s_axis_config_tvalid), // input wire s_axis_config_tvalid + .s_axis_config_tready(s_axis_config_tready), // output wire s_axis_config_tready + .s_axis_config_tlast(s_axis_config_tlast), // input wire s_axis_config_tlast + .s_axis_config_tdata(s_axis_config_tdata), // input wire [7 : 0] s_axis_config_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tlast(m_axis_data_tlast), // output wire m_axis_data_tlast + .m_axis_data_tdata(m_axis_data_tdata), // output wire [31 : 0] m_axis_data_tdata + .event_s_data_tlast_missing(event_s_data_tlast_missing), // output wire event_s_data_tlast_missing + .event_s_data_tlast_unexpected(event_s_data_tlast_unexpected), // output wire event_s_data_tlast_unexpected + .event_s_config_tlast_missing(event_s_config_tlast_missing), // output wire event_s_config_tlast_missing + .event_s_config_tlast_unexpected(event_s_config_tlast_unexpected) // output wire event_s_config_tlast_unexpected +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fir_0.v when simulating +// the core, fir_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_0/fir_0.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_0/fir_0.xci new file mode 100644 index 0000000..d3704de --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_0/fir_0.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_0.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_0 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_0.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_0 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v4/top/top.tmp/axis_pfb_readout_v4_v1_0_project/axis_pfb_readout_v4_v1_0_project.gen/sources_1/ip/fir_0 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_1/fir_1.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_1/fir_1.xci new file mode 100644 index 0000000..09d6032 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_1/fir_1.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_1 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_1.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_1 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_1.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_1 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v4/top/top.tmp/axis_pfb_readout_v4_v1_0_project/axis_pfb_readout_v4_v1_0_project.gen/sources_1/ip/fir_1 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_2/fir_2.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_2/fir_2.xci new file mode 100644 index 0000000..6c6b57b --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_2/fir_2.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_2 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_2.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_2 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_2.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_2 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v4/top/top.tmp/axis_pfb_readout_v4_v1_0_project/axis_pfb_readout_v4_v1_0_project.gen/sources_1/ip/fir_2 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_3/fir_3.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_3/fir_3.xci new file mode 100644 index 0000000..578e4d7 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_3/fir_3.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_3 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_3.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_3 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_3.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_3 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v4/top/top.tmp/axis_pfb_readout_v4_v1_0_project/axis_pfb_readout_v4_v1_0_project.gen/sources_1/ip/fir_3 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_4/fir_4.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_4/fir_4.xci new file mode 100644 index 0000000..a711e88 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_4/fir_4.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_4 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_4.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_4 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 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ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v4/top/top.tmp/axis_pfb_readout_v4_v1_0_project/axis_pfb_readout_v4_v1_0_project.gen/sources_1/ip/fir_4 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_5/fir_5.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_5/fir_5.xci new file mode 100644 index 0000000..7a66fd7 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_5/fir_5.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_5 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_5.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_5 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_5.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_5 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v4/top/top.tmp/axis_pfb_readout_v4_v1_0_project/axis_pfb_readout_v4_v1_0_project.gen/sources_1/ip/fir_5 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_6/fir_6.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_6/fir_6.xci new file mode 100644 index 0000000..c5d2362 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_6/fir_6.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_6 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_6.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_6 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_6.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_6 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v4/top/top.tmp/axis_pfb_readout_v4_v1_0_project/axis_pfb_readout_v4_v1_0_project.gen/sources_1/ip/fir_6 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_7/fir_7.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_7/fir_7.xci new file mode 100644 index 0000000..f3d9096 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_7/fir_7.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_7 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_7.mif + 56 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 7 + 1 + 4 + fir_7 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 16 + 2 + 0 + 0 + 32 + 1 + 8 + 8 + 7 + 1 + 7 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_7.coe + 0 + false + 8 + Signed + Inferred + 16 + 7 + fir_7 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 8 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../../zcu216/test_pfb_v4/top/top.tmp/axis_pfb_readout_v4_v1_0_project/axis_pfb_readout_v4_v1_0_project.gen/sources_1/ip/fir_7 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/gen.pl b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/gen.pl new file mode 100644 index 0000000..deba046 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/gen.pl @@ -0,0 +1,30 @@ +#!/usr/bin/perl +# This file generates the fir.tcl file to be run from vivado. +# Copy fir coefficient files. One IP per .coe file will be created. +# Copy generated .xci files to avoid generating FIR cores every time. + +open(my $file, "$ARGV[0]") or die "Could not open file '$ARGV[0]' $!"; +my @lines = <$file>; + +open(my $out_tcl, ">", "fir.tcl") or die "Could not open file fir.tcl $!"; +open(my $out_add, ">", "add.tcl") or die "Could not open file fir.tcl $!"; + +@out = `ls coef/*.coe`; +foreach (@out) +{ + chomp($_); + $fir = $_; + $fir =~ s/coef\///g; + $fir =~ s/.coe//g; + + print $out_add ("add_files ./fir/$fir/$fir.xci\n"); + + foreach my $line (@lines) + { + my $temp = $line; + chomp($temp); + $temp =~ s//$fir/g; + print $out_tcl ("$temp\n"); + } +} + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/tcl/fir.tcl.template b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/tcl/fir.tcl.template new file mode 100644 index 0000000..264e198 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/tcl/fir.tcl.template @@ -0,0 +1,32 @@ +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfb_readout_v3/src/pfb/fir/coef/.coe} \ + CONFIG.Coefficient_Sets {8} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {8} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips ] diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/tcl/ipgen.tcl b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/tcl/ipgen.tcl new file mode 100644 index 0000000..e1a3705 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/tcl/ipgen.tcl @@ -0,0 +1,13 @@ +# Create project. +create_project ipgen ./ipgen -part xczu49dr-ffvf1760-2-e + +# Set language options. +set_property simulator_language Mixed [current_project] +set_property target_language Verilog [current_project] + +# Create IPs. +source fir.tcl + +# Generate instantiation templates. +generate_target instantiation_template [get_ips *] + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/firs.sv b/firmware/ip/axis_pfb_readout_v4/src/pfb/firs.sv new file mode 100644 index 0000000..195dd2a --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/firs.sv @@ -0,0 +1,301 @@ +module firs + ( + // Reset and clock. + aresetn , + aclk , + + // S_AXIS for input data. + s_axis_tvalid , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tlast , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of channels. +parameter N = 32; + +// Number of Lanes (Input). +parameter L = 4; + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +input s_axis_tvalid; +input [L*32-1:0] s_axis_tdata; + +output m_axis_tvalid; +output m_axis_tlast; +output [2*L*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// FIR Configuration interface. +wire config_tvalid; +wire config_tready; +wire config_tlast; +wire[7:0] config_tdata; + +// Framing. +wire fr_sync; +wire fr_out; + +// Input delay. +wire[L*32-1:0] data_d; +reg [31:0] data_r1_v[0:L-1]; +reg [31:0] data_r2_v[0:L-1]; + +// Valid input. +reg valid_r = 1'b0; + +// FIR outputs. +wire[31:0] dout_v [0:2*L-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i '0'); + + else + -- State register. + current_state <= next_state; + + -- Counter for config. + if ( cfg_cnt_en = '1' ) then + cfg_cnt <= cfg_cnt + 1; + end if; + + end if; + end if; +end process; + +-- tlast. +tlast_i <= '1' when cfg_cnt = to_unsigned(N-1,cfg_cnt'length) else + '0'; + +-- Next state logic. +process (current_state, cfg_en, tready, cfg_cnt) +begin + case current_state is + when INIT_ST => + if ( cfg_en = '1' and tready = '1' ) then + next_state <= CNT_ST; + else + next_state <= INIT_ST; + end if; + + when CNT_ST => + if ( cfg_cnt = to_unsigned(N-1,cfg_cnt'length) ) then + next_state <= END_ST; + else + next_state <= CNT_ST; + end if; + + when END_ST => + if ( cfg_en = '1' ) then + next_state <= END_ST; + else + next_state <= INIT_ST; + end if; + + end case; +end process; + +-- Output logic. +process (current_state) +begin +cfg_cnt_en <= '0'; + case current_state is + when INIT_ST => + + when CNT_ST=> + cfg_cnt_en <= '1'; + + when END_ST => + + end case; +end process; + +-- Assign outputs. +tvalid <= cfg_cnt_en; +tlast <= tlast_i; +tdata <= std_logic_vector (cfg_cnt); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_chsel.sv b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_chsel.sv new file mode 100644 index 0000000..ec89d1b --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_chsel.sv @@ -0,0 +1,108 @@ +// This block will extract 1 channel from the TDM-input. +// It uses ID_REG which is as follows: +// ID_REG [7:0] : packet. +// ID_REG [15:8] : index. +// +// Input packets are as follows: +// |-------| |-------| +// | | | | +// tlast --------------| |-------------| | +// +// |-----|-------|-------|-----|-------|-------| +// t | 0 | L | 2*L | 0 | L | 2*L | +// a | 1 | L+1 | 2*L+1 | 1 | L+1 | 2*L+1 | +// d | 2 | L+2 | 2*L+2 | 2 | L+2 | 2*L+2 | +// a | . | . | . | . | . | . | +// t | . | . | . | . | . | . | +// a | . | . | . | . | . | . | +// | L-1 | 2*L-1 | 3*L-1 | L-1 | 2*L-1 | 3*L-1 | +// |-----|-------|-------|-----|-------|-------| +// +// The internal counter counts packets relying on tlast and resets. +// Offset within a packet is given by index. +module pfb_chsel + #( + // Bits. + parameter B = 32, + + // Number of lanes. + parameter L = 8 + ) + ( + // Clock. + input wire aclk , + + // S_AXIS for input data. + input wire [L*B-1:0] s_axis_tdata , + input wire s_axis_tlast , + + // M_AXIS for output data. + output wire m_axis_tvalid , + output wire [B-1:0] m_axis_tdata , + + // Registers. + input wire [15:0] ID_REG + ); + +/********************/ +/* Internal signals */ +/********************/ +// Packet counter. +reg [7:0] cnt = 0; +wire wr_en; + +// Registers. +reg [7:0] packet_reg ; +reg [7:0] index_reg ; + +// Data registers. +reg [L*B-1:0] tdata_r ; +reg [B-1:0] data_mux_r ; + +// Muxed data. +wire [B-1:0] data_mux ; + +// tlast_pipeline (for tvalid). +reg tlast_r1 ; +reg tlast_r2 ; + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// Packet counter. +assign wr_en = (cnt == packet_reg)? 1'b1 : 1'b0; + +// Muxed data. +assign data_mux = tdata_r [index_reg*B +: B]; + +// Registers. +always @(posedge aclk) begin + // Packet counter. + if (s_axis_tlast == 1'b1) + cnt <= 0; + else + cnt <= cnt + 1; + + // Registers. + packet_reg <= ID_REG [7:0]; + index_reg <= ID_REG [15:8]; + + // Data registers. + if (wr_en == 1'b1) + tdata_r <= s_axis_tdata; + + if (tlast_r1 == 1'b1) + data_mux_r <= data_mux; + + // tlast_pipeline (for tvalid). + tlast_r1 <= s_axis_tlast; + tlast_r2 <= tlast_r1; +end + +// Assign outputs. +assign m_axis_tvalid = tlast_r2; +assign m_axis_tdata = data_mux_r; + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_ctrl.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_ctrl.vhd new file mode 100644 index 0000000..24bd0a2 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_ctrl.vhd @@ -0,0 +1,113 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use WORK.pfb_ctrl_pkg.ALL; + +entity pfb_ctrl is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + aresetn : in std_logic; + aclk : in std_logic; + + -- M_AXIS for Configuration. + m_axis_config_tvalid : out std_logic; + m_axis_config_tready : in std_logic; + m_axis_config_tlast : out std_logic; + m_axis_config_tdata : out std_logic_vector (7 downto 0); + + -- Filter config. + cfg_en : in std_logic; + + -- Framing. + tready : in std_logic; + tvalid : in std_logic; + fr_sync : in std_logic; + fr_out : out std_logic + ); +end pfb_ctrl; + +architecture rtl of pfb_ctrl is + +-- PFB configuration. +component pfb_cfg is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Filter config. + cfg_en : in std_logic; + tready : in std_logic; + tvalid : out std_logic; + tlast : out std_logic; + tdata : out std_logic_vector (f_nbit_axis(N)-1 downto 0) + ); +end component; + +-- PFB framing. +component pfb_framing is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Framing. + tready : in std_logic; + tvalid : in std_logic; + fr_sync : in std_logic; + fr_out : out std_logic + ); +end component; + +begin + +-- PFB configuration. +cfg_i : pfb_cfg + Generic map ( + -- Number of channels. + N => N + ) + Port map ( + -- Reset and clock. + rstn => aresetn , + clk => aclk , + + -- Filter config. + cfg_en => cfg_en , + tready => m_axis_config_tready , + tvalid => m_axis_config_tvalid , + tlast => m_axis_config_tlast , + tdata => m_axis_config_tdata + ); + +-- PFB framing. +framing_i : pfb_framing + Generic map ( + -- Number of channels. + N => N + ) + Port map ( + -- Reset and clock. + rstn => aresetn , + clk => aclk , + + -- Framing. + tready => tready , + tvalid => tvalid , + fr_sync => fr_sync , + fr_out => fr_out + ); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_ctrl_pkg.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_ctrl_pkg.vhd new file mode 100644 index 0000000..db99fb3 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_ctrl_pkg.vhd @@ -0,0 +1,38 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +package pfb_ctrl_pkg is + + -- Functions. + function f_nbit_axis (ARG: Integer) return Integer; + +end pfb_ctrl_pkg; + +package body pfb_ctrl_pkg is + + function f_nbit_axis (ARG: Integer) return Integer is + -- Function variables. + variable arg_log2 : Integer := Integer(ceil(log2(real(ARG)))); + variable tmp : Integer; + + begin + + if (arg_log2 <= 8 ) then + tmp := 8; + elsif ( arg_log2 <= 16 ) then + tmp := 16; + elsif ( arg_log2 <= 24 ) then + tmp := 24; + elsif ( arg_log2 <= 32 ) then + tmp := 32; + else + tmp := -1; + end if; + + return tmp; + end; + +end package body pfb_ctrl_pkg; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_framing.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_framing.vhd new file mode 100644 index 0000000..5ff7e74 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_framing.vhd @@ -0,0 +1,137 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity pfb_framing is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Framing. + tready : in std_logic; + tvalid : in std_logic; + fr_sync : in std_logic; + fr_out : out std_logic + ); +end pfb_framing; + +architecture rtl of pfb_framing is + +-- Number of bits of N. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Wait value. +constant WAIT_C : Integer := 10*N; +constant WAIT_C_LOG2 : Integer := Integer(ceil(log2(real(WAIT_C)))); + +-- FSM. +type fsm_type is ( INIT_ST , + SHIFT_ST , + WAIT_ST ); + +signal current_state, next_state : fsm_type; + +-- Free running counter for framing. +signal fr_cnt : unsigned (N_LOG2-1 downto 0); +signal fr_cnt_en : std_logic; + +-- Counter for waiting until next calibration. +signal wait_cnt : unsigned (WAIT_C_LOG2-1 downto 0); +signal wait_cnt_en : std_logic; + +-- Framing sync. +signal fr_i : std_logic; + +begin + +-- Registers. +process(clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + -- State register. + current_state <= INIT_ST; + + -- Counters. + fr_cnt <= (others => '0'); + wait_cnt <= (others => '0'); + else + -- State register. + current_state <= next_state; + + -- Counters. + if ( fr_cnt_en = '1' and tready = '1' and tvalid = '1' ) then + if ( fr_cnt < to_unsigned(N-1,fr_cnt'length) ) then + fr_cnt <= fr_cnt + 1; + else + fr_cnt <= (others => '0'); + end if; + end if; + if ( wait_cnt_en = '1' ) then + if ( wait_cnt < to_unsigned(WAIT_C-1,wait_cnt'length) ) then + wait_cnt <= wait_cnt + 1; + else + wait_cnt <= (others => '0'); + end if; + end if; + + end if; + end if; +end process; + +-- Framing sync. +fr_i <= '1' when fr_cnt = to_unsigned(N-1,fr_cnt'length) else + '0'; + +-- Next state logic. +process (current_state, fr_sync, wait_cnt) +begin + case current_state is + when INIT_ST => + if ( fr_sync = '0' ) then + next_state <= INIT_ST; + else + next_state <= SHIFT_ST; + end if; + + when SHIFT_ST => + next_state <= WAIT_ST; + + when WAIT_ST => + if ( wait_cnt = to_unsigned(WAIT_C-1,wait_cnt'length) ) then + next_state <= INIT_ST; + else + next_state <= WAIT_ST; + end if; + end case; +end process; + +-- Output logic. +process (current_state) +begin +fr_cnt_en <= '0'; +wait_cnt_en <= '0'; + case current_state is + when INIT_ST => + fr_cnt_en <= '1'; + + when SHIFT_ST => + + when WAIT_ST => + fr_cnt_en <= '1'; + wait_cnt_en <= '1'; + + end case; +end process; + +-- Assign outputs. +fr_out <= fr_i; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_reorder.sv b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_reorder.sv new file mode 100644 index 0000000..4b57dab --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/pfb_reorder.sv @@ -0,0 +1,113 @@ +// This block reorders PFB output to get it ready for the +// SSR FFT. +module pfb_reorder + ( + // Reset and clock. + aclk , + + // S_AXIS for input data. + s_axis_tvalid , + s_axis_tlast , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tlast , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Bits. +parameter B = 32; + +// Number of Lanes. +parameter L = 4; + +/*********/ +/* Ports */ +/*********/ +input aclk; + +input s_axis_tvalid; +input s_axis_tlast; +input [2*L*B-1:0] s_axis_tdata; + +output m_axis_tvalid; +output m_axis_tlast; +output [2*L*B-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Sorted input data. +wire [2*L*B-1:0] din_sort; + +// Data registers. +reg [2*L*B-1:0] data_r1 = 0; +reg [2*L*B-1:0] data_r2 = 0; +reg [2*L*B-1:0] data_r3 = 0; +reg [2*L*B-1:0] data_r4 = 0; + +// Tlast registers. +reg last_r1 = 0; +reg last_r2 = 0; +reg last_r3 = 0; + +// Low/High data. +wire [2*L*B-1:0] dlow; +wire [2*L*B-1:0] dhigh; + +// Muxed output. +reg sel = 0; +wire [2*L*B-1:0] dmux; + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i NBITS+1 , + + -- Fifo depth. + N => 4 + ) + Port map + ( + rstn => aresetn , + clk => aclk , + + -- Write I/F. + wr_en => s_axis_tvalid , + din => fifo_din , + + -- Read I/F. + rd_en => m_axis_tready , + dout => fifo_dout , + + -- Flags. + full => fifo_full , + empty => fifo_empty + ); + +-- Fifo connections. +fifo_din <= s_axis_tlast & s_axis_tdata; +s_axis_tready <= not(fifo_full); + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( aresetn = '0' ) then + -- Pipeline registers. + d_r <= (others => '0'); + d_rr <= (others => '0'); + empty_r <= '1'; + empty_rr <= '1'; + last_r <= '0'; + last_rr <= '0'; + + -- sel register. + cnt <= (others => '0'); + sel <= (others => '0'); + else + -- Pipeline registers. + d_r <= d_i; + d_rr <= d_mux; + empty_r <= fifo_empty; + empty_rr <= empty_r; + last_r <= last_i; + last_rr <= last_r; + + -- sel register: if reading and not empty, count. + if ( m_axis_tready = '1' and empty_r = '0' ) then + if ( cnt < to_unsigned(T-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + sel <= sel + 1; + end if; + end if; + + end if; + end if; +end process; + +-- Input data/tlast. +d_i <= fifo_dout(NBITS-1 downto 0); +last_i <= fifo_dout(NBITS); + +-- Slice input. +GEN_SLICE_IN: for I in 0 to L-1 generate + dv_i(I) <= signed(d_r ( 2*I*B+B-1 downto 2*I*B)); + dv_q(I) <= signed(d_r ( (2*I+1)*B+B-1 downto (2*I+1)*B)); +end generate GEN_SLICE_IN; + +-- Multiply by -1 only odd samples. +GEN_PM: for I in 0 to L/2-1 generate + -- Even samples: multiply always by 1. + dv_i_pm(2*I) <= dv_i(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_i_pm(2*I+1) <= to_signed(MAX_P,B) when dv_i(2*I+1) = to_signed(MIN_N,B) else + -dv_i(2*I+1); + + -- Even samples: multiply always by 1. + dv_q_pm(2*I) <= dv_q(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_q_pm(2*I+1) <= to_signed(MAX_P,B) when dv_q(2*I+1) = to_signed(MIN_N,B) else + -dv_q(2*I+1); +end generate GEN_PM; + +-- Combine signals back. +GEN_COMBINE_PM: for I in 0 to L-1 generate + d_pm ( 2*I*B+B-1 downto 2*I*B) <= std_logic_vector(dv_i_pm(I)); + d_pm ((2*I+1)*B+B-1 downto (2*I+1)*B) <= std_logic_vector(dv_q_pm(I)); +end generate GEN_COMBINE_PM; + +-- Data mux. +d_mux <= d_r when sel = to_unsigned(0,sel'length) else + d_pm; + + +-- Assign outputs. +m_axis_tdata <= d_rr; +m_axis_tlast <= last_rr; +m_axis_tvalid <= not(empty_rr); + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/zn_nb.vhd b/firmware/ip/axis_pfb_readout_v4/src/pfb/zn_nb.vhd new file mode 100644 index 0000000..2add8e5 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/zn_nb.vhd @@ -0,0 +1,54 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity zn_nb is + Generic + ( + -- Number of bits. + B : Integer := 16; + + -- Delay. + N : Integer := 4 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- S_AXIS for intput. + s_axis_tvalid : in std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + + -- M_AXIS for output. + m_axis_tvalid : out std_logic; + m_axis_tdata : out std_logic_vector(B-1 downto 0) + + ); +end zn_nb; + +architecture rtl of zn_nb is + +-- Shift register for data. +type reg_v is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal shift_reg_tdata : reg_v; + +begin + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( s_axis_tvalid = '1' ) then + shift_reg_tdata <= shift_reg_tdata (N-2 downto 0) & s_axis_tdata; + end if; + end if; +end process; + +-- Assign outputs. +m_axis_tdata <= shift_reg_tdata (N-1); +m_axis_tvalid <= s_axis_tvalid; + +end rtl; + diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb_readout.v b/firmware/ip/axis_pfb_readout_v4/src/pfb_readout.v new file mode 100644 index 0000000..56d4be8 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/pfb_readout.v @@ -0,0 +1,168 @@ +/* + * Top-leve block which instantiates the following: + * + * 1) PFB, 50 % Overlap, 64 Channels, 8 selectable outputs. + * 2) DDS, 8 channels, independent freq/phase, phase coherent. + */ +module pfb_readout + #( + // Number of channels. + parameter N = 32, + + // Number of Lanes (Input). + parameter L = 4 + ) + ( + // Reset and clock. + input wire aresetn , + input wire aclk , + + // S_AXIS for input data. + input wire s_axis_tvalid , + input wire [L*32-1:0] s_axis_tdata , + + // M_AXIS for output data. + output wire m_axis_tvalid , + output wire [31:0] m0_axis_tdata , + output wire [31:0] m1_axis_tdata , + output wire [31:0] m2_axis_tdata , + output wire [31:0] m3_axis_tdata , + output wire [31:0] m4_axis_tdata , + output wire [31:0] m5_axis_tdata , + output wire [31:0] m6_axis_tdata , + output wire [31:0] m7_axis_tdata , + + // Registers. + input wire [15:0] ID0_REG , + input wire [15:0] ID1_REG , + input wire [15:0] ID2_REG , + input wire [15:0] ID3_REG , + input wire [15:0] ID4_REG , + input wire [15:0] ID5_REG , + input wire [15:0] ID6_REG , + input wire [15:0] ID7_REG , + input wire [31:0] PINC0_REG , + input wire [31:0] POFF0_REG , + input wire [31:0] PINC1_REG , + input wire [31:0] POFF1_REG , + input wire [31:0] PINC2_REG , + input wire [31:0] POFF2_REG , + input wire [31:0] PINC3_REG , + input wire [31:0] POFF3_REG , + input wire [31:0] PINC4_REG , + input wire [31:0] POFF4_REG , + input wire [31:0] PINC5_REG , + input wire [31:0] POFF5_REG , + input wire [31:0] PINC6_REG , + input wire [31:0] POFF6_REG , + input wire [31:0] PINC7_REG , + input wire [31:0] POFF7_REG + ); + +/********************/ +/* Internal signals */ +/********************/ + +wire tvalid_i; +wire [31:0] tdata0_i; +wire [31:0] tdata1_i; +wire [31:0] tdata2_i; +wire [31:0] tdata3_i; +wire [31:0] tdata4_i; +wire [31:0] tdata5_i; +wire [31:0] tdata6_i; +wire [31:0] tdata7_i; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// PFB. +pfb_top + #( + // Number of channels. + .N(N), + + // Number of Lanes (Input). + .L(L) + ) + pfb_top_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input data. + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for output data. + .m_axis_tvalid (tvalid_i ), + .m0_axis_tdata (tdata0_i ), + .m1_axis_tdata (tdata1_i ), + .m2_axis_tdata (tdata2_i ), + .m3_axis_tdata (tdata3_i ), + .m4_axis_tdata (tdata4_i ), + .m5_axis_tdata (tdata5_i ), + .m6_axis_tdata (tdata6_i ), + .m7_axis_tdata (tdata7_i ), + + // Registers. + .ID0_REG (ID0_REG ), + .ID1_REG (ID1_REG ), + .ID2_REG (ID2_REG ), + .ID3_REG (ID3_REG ), + .ID4_REG (ID4_REG ), + .ID5_REG (ID5_REG ), + .ID6_REG (ID6_REG ), + .ID7_REG (ID7_REG ) + ); + +// DDS. +ddsprod_v ddsprod_v_i + ( + // Clock. + .aclk (aclk ), + + // S_AXIS for input data. + .s_axis_tvalid (tvalid_i ), + .s0_axis_tdata (tdata0_i ), + .s1_axis_tdata (tdata1_i ), + .s2_axis_tdata (tdata2_i ), + .s3_axis_tdata (tdata3_i ), + .s4_axis_tdata (tdata4_i ), + .s5_axis_tdata (tdata5_i ), + .s6_axis_tdata (tdata6_i ), + .s7_axis_tdata (tdata7_i ), + + // M_AXIS for output data. + .m_axis_tvalid (m_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + .m1_axis_tdata (m1_axis_tdata ), + .m2_axis_tdata (m2_axis_tdata ), + .m3_axis_tdata (m3_axis_tdata ), + .m4_axis_tdata (m4_axis_tdata ), + .m5_axis_tdata (m5_axis_tdata ), + .m6_axis_tdata (m6_axis_tdata ), + .m7_axis_tdata (m7_axis_tdata ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .POFF0_REG (POFF0_REG ), + .PINC1_REG (PINC1_REG ), + .POFF1_REG (POFF1_REG ), + .PINC2_REG (PINC2_REG ), + .POFF2_REG (POFF2_REG ), + .PINC3_REG (PINC3_REG ), + .POFF3_REG (POFF3_REG ), + .PINC4_REG (PINC4_REG ), + .POFF4_REG (POFF4_REG ), + .PINC5_REG (PINC5_REG ), + .POFF5_REG (POFF5_REG ), + .PINC6_REG (PINC6_REG ), + .POFF6_REG (POFF6_REG ), + .PINC7_REG (PINC7_REG ), + .POFF7_REG (POFF7_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/axis_pfb_readout_v3.xdc b/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/axis_pfb_readout_v3.xdc new file mode 100644 index 0000000..d22e7ee --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/axis_pfb_readout_v3.xdc @@ -0,0 +1,60 @@ +create_clock -period 1.000 -name aclk -waveform {0.000 0.500} [get_ports aclk] +create_clock -period 10.000 -name s_axi_aclk -waveform {0.000 5.000} [get_ports s_axi_aclk] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_araddr[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports {s_axi_araddr[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_awaddr[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports {s_axi_awaddr[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_wdata[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports {s_axi_wdata[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_wstrb[*]}] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports {s_axi_wstrb[*]}] +set _xlnx_shared_i0 [get_ports {s_axis_tdata[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 $_xlnx_shared_i0 +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 $_xlnx_shared_i0 +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports aresetn] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports aresetn] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_aresetn] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_aresetn] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_arvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_arvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_awvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_awvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_bready] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_bready] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_rready] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_rready] +set_input_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_wvalid] +set_input_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.400 [get_ports s_axi_wvalid] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports s_axis_tvalid] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports s_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {m0_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports {m0_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {m1_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports {m1_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {m2_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports {m2_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {m3_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports {m3_axis_tdata[*]}] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports {s_axi_rdata[*]}] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports {s_axi_rdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports m0_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports m0_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports m1_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports m1_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports m2_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports m2_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports m3_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.500 [get_ports m3_axis_tvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_arready] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_arready] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_awready] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_awready] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_bvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_bvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_rvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_rvalid] +set_output_delay -clock [get_clocks s_axi_aclk] -min -add_delay 0.200 [get_ports s_axi_wready] +set_output_delay -clock [get_clocks s_axi_aclk] -max -add_delay 0.500 [get_ports s_axi_wready] +set_clock_groups -asynchronous -group [get_clocks s_axi_aclk] -group [get_clocks aclk] + +set_false_path -to [all_outputs] diff --git a/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/dds_ctrl.xdc b/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/dds_ctrl.xdc new file mode 100644 index 0000000..46515ba --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/dds_ctrl.xdc @@ -0,0 +1,13 @@ +create_clock -period 1.000 -name aclk -waveform {0.000 0.500} [get_ports aclk] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports en] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports en] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {POFF_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {POFF_REG[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports dout_valid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports dout_valid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports {dout[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports {dout[*]}] + +set_false_path -to [get_ports *dout*] diff --git a/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/dds_top.xdc b/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/dds_top.xdc new file mode 100644 index 0000000..8e8a0a2 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/dds_top.xdc @@ -0,0 +1,13 @@ +create_clock -period 1.000 -name aclk -waveform {0.000 0.500} [get_ports aclk] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports din_valid] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports din_valid] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {POFF_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {POFF_REG[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports dout_valid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports dout_valid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports {dout[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports {dout[*]}] + +set_false_path -to [get_ports *dout*] diff --git a/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/ddsprod.xdc b/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/ddsprod.xdc new file mode 100644 index 0000000..5505ca0 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/synth/xdcs/ddsprod.xdc @@ -0,0 +1,15 @@ +create_clock -period 1.000 -name aclk -waveform {0.000 0.500} [get_ports aclk] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports s_axis_tvalid] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports s_axis_tvalid] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {s_axis_tdata[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {s_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports m_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports m_axis_tvalid] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.000 [get_ports {m_axis_tdata[*]}] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports {m_axis_tdata[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {PINC_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.200 [get_ports {POFF_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.400 [get_ports {POFF_REG[*]}] + +set_false_path -to [get_ports *m_axis*] diff --git a/firmware/ip/axis_pfb_readout_v4/src/tb/tb.sv b/firmware/ip/axis_pfb_readout_v4/src/tb/tb.sv new file mode 100644 index 0000000..86da2a5 --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/src/tb/tb.sv @@ -0,0 +1,426 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// Number of channels. +parameter N = 64; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; + +wire [7:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [7:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +reg s_axis_tvalid; +wire [4*32-1:0] s_axis_tdata; + +wire m0_axis_tvalid; +wire [31:0] m0_axis_tdata; +wire m1_axis_tvalid; +wire [31:0] m1_axis_tdata; +wire m2_axis_tvalid; +wire [31:0] m2_axis_tdata; +wire m3_axis_tvalid; +wire [31:0] m3_axis_tdata; +wire m4_axis_tvalid; +wire [31:0] m4_axis_tdata; +wire m5_axis_tvalid; +wire [31:0] m5_axis_tdata; +wire m6_axis_tvalid; +wire [31:0] m6_axis_tdata; +wire m7_axis_tvalid; +wire [31:0] m7_axis_tdata; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Input data. +reg [31:0] din_ii [0:7]; + +// Output data. +wire [15:0] dout0_real; +wire [15:0] dout0_imag; +wire [15:0] dout1_real; +wire [15:0] dout1_imag; +wire [15:0] dout2_real; +wire [15:0] dout2_imag; +wire [15:0] dout3_real; +wire [15:0] dout3_imag; +wire [15:0] dout4_real; +wire [15:0] dout4_imag; +wire [15:0] dout5_real; +wire [15:0] dout5_imag; +wire [15:0] dout6_real; +wire [15:0] dout6_imag; +wire [15:0] dout7_real; +wire [15:0] dout7_imag; + +// Test bench control. +reg tb_data = 0; +reg tb_data_done= 0; +reg tb_write_out= 0; + + +generate +genvar ii; +for (ii = 0; ii < 8; ii = ii + 1) begin + assign s_axis_tdata[32*ii +: 32] = din_ii[ii]; +end +endgenerate + +assign dout0_real = m0_axis_tdata [15:0]; +assign dout0_imag = m0_axis_tdata [31:16]; +assign dout1_real = m1_axis_tdata [15:0]; +assign dout1_imag = m1_axis_tdata [31:16]; +assign dout2_real = m2_axis_tdata [15:0]; +assign dout2_imag = m2_axis_tdata [31:16]; +assign dout3_real = m3_axis_tdata [15:0]; +assign dout3_imag = m3_axis_tdata [31:16]; +assign dout4_real = m4_axis_tdata [15:0]; +assign dout4_imag = m4_axis_tdata [31:16]; +assign dout5_real = m5_axis_tdata [15:0]; +assign dout5_imag = m5_axis_tdata [31:16]; +assign dout6_real = m6_axis_tdata [15:0]; +assign dout6_imag = m6_axis_tdata [31:16]; +assign dout7_real = m7_axis_tdata [15:0]; +assign dout7_imag = m7_axis_tdata [31:16]; + +// axi_mst_0. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_pfb_readout_v4 + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // s_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input samples. + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for CH0 output. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + + // M_AXIS for CH1 output. + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tdata (m1_axis_tdata ), + + // M_AXIS for CH2 output. + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tdata (m2_axis_tdata ), + + // M_AXIS for CH3 output. + .m3_axis_tvalid (m3_axis_tvalid ), + .m3_axis_tdata (m3_axis_tdata ), + + // M_AXIS for CH4 output. + .m4_axis_tvalid (m4_axis_tvalid ), + .m4_axis_tdata (m4_axis_tdata ), + + // M_AXIS for CH5 output. + .m5_axis_tvalid (m5_axis_tvalid ), + .m5_axis_tdata (m5_axis_tdata ), + + // M_AXIS for CH6 output. + .m6_axis_tvalid (m6_axis_tvalid ), + .m6_axis_tdata (m6_axis_tdata ), + + // M_AXIS for CH7 output. + .m7_axis_tvalid (m7_axis_tvalid ), + .m7_axis_tdata (m7_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("###################"); + $display("### Program DDS ###"); + $display("###################"); + $display("t = %0t", $time); + + // ID0/1/2/3/4/5/6/7. + // ID [7:0]: packet + // ID [15:8]: id + axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, (0 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(1*4, prot, (1 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(2*4, prot, (6 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(3*4, prot, (6 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, (6 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, (6 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(6*4, prot, (6 << 8) + 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(7*4, prot, (6 << 8) + 0, resp); + + // FREQ0/PHASE0. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(8*4, prot, 0, resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(9*4, prot, 0, resp); + + // FREQ1/PHASE1. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(10*4, prot, freq(1,10), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(11*4, prot, 0, resp); + + // FREQ2/PHASE2. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(12*4, prot, freq(1, 33), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(13*4, prot, 0, resp); + + // FREQ3/PHASE3. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(14*4, prot, freq(1, 3), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(15*4, prot, 0, resp); + + // FREQ4/PHASE4. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(16*4, prot, freq(1, 3), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(17*4, prot, 0, resp); + + // FREQ5/PHASE5. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(18*4, prot, freq(1, 3), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(19*4, prot, 0, resp); + + // FREQ6/PHASE6. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(20*4, prot, freq(1, 3), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(21*4, prot, 0, resp); + + // FREQ7/PHASE7. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(22*4, prot, freq(1, 3), resp); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(23*4, prot, 0, resp); + + $display("###############################"); + $display("### Start Recording Outputs ###"); + $display("###############################"); + $display("t = %0t", $time); + + tb_data <= 1; + tb_write_out <= 1; + wait (tb_data_done); + tb_write_out <= 0; + +end + +// Input data. +initial begin + int fd; + int i; + bit signed [15:0] vali, valq; + s_axis_tvalid <= 0; + + // Open file with Coefficients. + fd = $fopen("../../../../../tb/data_iq.txt","r"); + + wait(tb_data); + @(posedge aclk); + + i = 0; + while ($fscanf(fd,"%d,%d", vali, valq) == 2) begin + //$display("T = %d, i = %d, I = %d, Q = %d", $time, i, vali, valq); + din_ii[i] <= {valq,vali}; + i = i + 1; + if (i == 4) begin + i = 0; + @(posedge aclk); + s_axis_tvalid <= 1; + end + end + + @(posedge aclk); + s_axis_tvalid <= 0; + tb_data_done <= 1; + +end + +// Write output into file. +initial begin + int fd0, fd1, fd2, fd3, fd4, fd5, fd6, fd7; + int i; + shortint real_d0, imag_d0; + shortint real_d1, imag_d1; + shortint real_d2, imag_d2; + shortint real_d3, imag_d3; + shortint real_d4, imag_d4; + shortint real_d5, imag_d5; + shortint real_d6, imag_d6; + shortint real_d7, imag_d7; + + // Output file. + fd0 = $fopen("../../../../../tb/dout_0.csv","w"); + fd1 = $fopen("../../../../../tb/dout_1.csv","w"); + fd2 = $fopen("../../../../../tb/dout_2.csv","w"); + fd3 = $fopen("../../../../../tb/dout_3.csv","w"); + fd4 = $fopen("../../../../../tb/dout_4.csv","w"); + fd5 = $fopen("../../../../../tb/dout_5.csv","w"); + fd6 = $fopen("../../../../../tb/dout_6.csv","w"); + fd7 = $fopen("../../../../../tb/dout_7.csv","w"); + + // Data format. + $fdisplay(fd0, "valid, real, imag"); + $fdisplay(fd1, "valid, real, imag"); + $fdisplay(fd2, "valid, real, imag"); + $fdisplay(fd3, "valid, real, imag"); + $fdisplay(fd4, "valid, real, imag"); + $fdisplay(fd5, "valid, real, imag"); + $fdisplay(fd6, "valid, real, imag"); + $fdisplay(fd7, "valid, real, imag"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + real_d0 = m0_axis_tdata[15:0]; + imag_d0 = m0_axis_tdata[31:16]; + real_d1 = m1_axis_tdata[15:0]; + imag_d1 = m1_axis_tdata[31:16]; + real_d2 = m2_axis_tdata[15:0]; + imag_d2 = m2_axis_tdata[31:16]; + real_d3 = m3_axis_tdata[15:0]; + imag_d3 = m3_axis_tdata[31:16]; + real_d4 = m4_axis_tdata[15:0]; + imag_d4 = m4_axis_tdata[31:16]; + real_d5 = m5_axis_tdata[15:0]; + imag_d5 = m5_axis_tdata[31:16]; + real_d6 = m6_axis_tdata[15:0]; + imag_d6 = m6_axis_tdata[31:16]; + real_d7 = m7_axis_tdata[15:0]; + imag_d7 = m7_axis_tdata[31:16]; + $fdisplay(fd0,"%d,%d,%d",m0_axis_tvalid,real_d0,imag_d0); + $fdisplay(fd1,"%d,%d,%d",m1_axis_tvalid,real_d1,imag_d1); + $fdisplay(fd2,"%d,%d,%d",m2_axis_tvalid,real_d2,imag_d2); + $fdisplay(fd3,"%d,%d,%d",m3_axis_tvalid,real_d3,imag_d3); + $fdisplay(fd4,"%d,%d,%d",m4_axis_tvalid,real_d4,imag_d4); + $fdisplay(fd5,"%d,%d,%d",m5_axis_tvalid,real_d5,imag_d5); + $fdisplay(fd6,"%d,%d,%d",m6_axis_tvalid,real_d6,imag_d6); + $fdisplay(fd7,"%d,%d,%d",m7_axis_tvalid,real_d7,imag_d7); + end + + $display("Closing file, t = %0t", $time); + $fclose(fd0); + $fclose(fd1); + $fclose(fd2); + $fclose(fd3); + $fclose(fd4); + $fclose(fd5); + $fclose(fd6); + $fclose(fd7); +end + +always begin + s_axi_aclk <= 0; + #10; + s_axi_aclk <= 1; + #10; +end + +always begin + aclk <= 0; + #1; + aclk <= 1; + #1; +end + +function bit [31:0] freq (input real f, fs); + int ret; + + // I use only 16 bits for rounding. Add the remaining later... + ret = 2**16*f/fs; + + return {ret,16'h0000}; +endfunction + +function bit [31:0] phase (input real phi); + int ret; + + // I use only 16 bits for rounding. Add the remaining later... + ret = 2**16*phi/360; + + return {ret,16'h0000}; +endfunction + +endmodule + diff --git a/firmware/ip/axis_pfb_readout_v4/xgui/axis_pfb_readout_v4_v1_0.tcl b/firmware/ip/axis_pfb_readout_v4/xgui/axis_pfb_readout_v4_v1_0.tcl new file mode 100644 index 0000000..716ad7e --- /dev/null +++ b/firmware/ip/axis_pfb_readout_v4/xgui/axis_pfb_readout_v4_v1_0.tcl @@ -0,0 +1,24 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/README b/firmware/ip/axis_pfba_pr_4x256_v1/README new file mode 100644 index 0000000..6d9b83f --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/README @@ -0,0 +1 @@ +This IP is a PFB for Analysis and Perfect Reconstruction (cascaded). diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/component.xml b/firmware/ip/axis_pfba_pr_4x256_v1/component.xml new file mode 100644 index 0000000..c92f2a1 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/component.xml @@ -0,0 +1,1323 @@ + + + user.org + user + axis_pfba_pr_4x256_v1 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TLAST + + + m_axis_tlast + + + + + TVALID + + + m_axis_tvalid + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axis_pfba_pr_4x256_v1 + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 0960c124 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axis_pfba_pr_4x256_v1 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 0960c124 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 0891018f + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 255 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N + N + 256 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/fir/fir_7/fir_7.xci + xci + CELL_NAME_pfb_i/firs_i/fir7_i + + + src/fir/fir_6/fir_6.xci + xci + CELL_NAME_pfb_i/firs_i/fir6_i + + + src/fir/fir_5/fir_5.xci + xci + CELL_NAME_pfb_i/firs_i/fir5_i + + + src/fir/fir_4/fir_4.xci + xci + CELL_NAME_pfb_i/firs_i/fir4_i + + + src/fir/fir_3/fir_3.xci + xci + CELL_NAME_pfb_i/firs_i/fir3_i + + + src/fir/fir_2/fir_2.xci + xci + CELL_NAME_pfb_i/firs_i/fir2_i + + + src/fir/fir_1/fir_1.xci + xci + CELL_NAME_pfb_i/firs_i/fir1_i + + + src/fir/fir_0/fir_0.xci + xci + CELL_NAME_pfb_i/firs_i/fir0_i + + + src/fir/coef/fir_7.coe + coe + + + src/fir/coef/fir_6.coe + coe + + + src/fir/coef/fir_5.coe + coe + + + src/fir/coef/fir_4.coe + coe + + + src/fir/coef/fir_3.coe + coe + + + src/fir/coef/fir_2.coe + coe + + + src/fir/coef/fir_1.coe + coe + + + src/fir/coef/fir_0.coe + coe + + + src/pfb_switch.v + verilogSource + + + src/firs.sv + systemVerilogSource + + + src/pfb.sv + systemVerilogSource + + + src/pfb_reorder.sv + systemVerilogSource + + + src/pfb_swap.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/conv_pkg.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/fft/framing.vhd + vhdlSource + + + src/pfb_ctrl_pkg.vhd + vhdlSource + + + src/pfb_cfg.vhd + vhdlSource + + + src/pfb_ctrl.vhd + vhdlSource + + + src/pfb_framing.vhd + vhdlSource + + + src/pimod_pfb.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/single_reg_w_init.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/srl33e.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/ssr_8x256.vhd + vhdlSource + + + src/fft/ssrfft_8x256_sync.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg_reg.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg_w_init.vhd + vhdlSource + + + src/fft/tlast_gen.vhd + vhdlSource + + + src/zn_nb.vhd + vhdlSource + + + src/axis_pfba_pr_4x256_v1.sv + systemVerilogSource + CHECKSUM_b87cf49d + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/fir/fir_7/fir_7.xci + xci + CELL_NAME_pfb_i/firs_i/fir7_i + + + src/fir/fir_6/fir_6.xci + xci + CELL_NAME_pfb_i/firs_i/fir6_i + + + src/fir/fir_5/fir_5.xci + xci + CELL_NAME_pfb_i/firs_i/fir5_i + + + src/fir/fir_4/fir_4.xci + xci + CELL_NAME_pfb_i/firs_i/fir4_i + + + src/fir/fir_3/fir_3.xci + xci + CELL_NAME_pfb_i/firs_i/fir3_i + + + src/fir/fir_2/fir_2.xci + xci + CELL_NAME_pfb_i/firs_i/fir2_i + + + src/fir/fir_1/fir_1.xci + xci + CELL_NAME_pfb_i/firs_i/fir1_i + + + src/fir/fir_0/fir_0.xci + xci + CELL_NAME_pfb_i/firs_i/fir0_i + + + src/fir/coef/fir_7.coe + coe + + + src/fir/coef/fir_6.coe + coe + + + src/fir/coef/fir_5.coe + coe + + + src/fir/coef/fir_4.coe + coe + + + src/fir/coef/fir_3.coe + coe + + + src/fir/coef/fir_2.coe + coe + + + src/fir/coef/fir_1.coe + coe + + + src/fir/coef/fir_0.coe + coe + + + src/pfb_switch.v + verilogSource + + + src/firs.sv + systemVerilogSource + + + src/pfb.sv + systemVerilogSource + + + src/pfb_reorder.sv + systemVerilogSource + + + src/pfb_swap.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/conv_pkg.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/fft/framing.vhd + vhdlSource + + + src/pfb_ctrl_pkg.vhd + vhdlSource + + + src/pfb_cfg.vhd + vhdlSource + + + src/pfb_ctrl.vhd + vhdlSource + + + src/pfb_framing.vhd + vhdlSource + + + src/pimod_pfb.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/single_reg_w_init.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/srl33e.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/ssr_8x256.vhd + vhdlSource + + + src/fft/ssrfft_8x256_sync.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg_reg.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg_w_init.vhd + vhdlSource + + + src/fft/tlast_gen.vhd + vhdlSource + + + src/zn_nb.vhd + vhdlSource + + + src/axis_pfba_pr_4x256_v1.sv + systemVerilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_pfba_pr_4x256_v1_v1_0.tcl + tclSource + CHECKSUM_0891018f + XGUI_VERSION_2 + + + + AXIS PFB 4 lanes, 256 Channels, 50 % Overlap, Perfect Reconstruction, V1. + + + Component_Name + axis_pfba_pr_4x256_v1_v1_0 + + + N + N + 256 + + + + + + zynquplus + + + /UserIP + + AXIS PFBA PR 4x256 V1 + package_project + 7 + 2023-04-26T18:18:48Z + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 0000000..7cfbd51 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 8 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 0000000..a53be60 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 8 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..ac9cf04 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,200 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 0000000..0fecc6e --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4760 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + 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std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rlast + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_ruser + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_rvalid + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rready + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + M_INITIATOR_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + wr_socket + + + width + 32 + + + + + + + 1 + + + + + M_INITIATOR_rd_socket + AXIMM Read Socket + AXIMM Socket for Read + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + rd_socket + + + width + 32 + + + + + + + 1 + + + + + S_TARGET_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + + + + + 1 + + + + + S_TARGET_rd_socket + AXIMM Read Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + + + + + 1 + + + + + + + C_AXI_PROTOCOL + 2 + + + C_AXI_INTERFACE_MODE + 0 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_WDATA_WIDTH + 32 + + + C_AXI_RDATA_WIDTH + 32 + + + C_AXI_WID_WIDTH + 0 + + + C_AXI_RID_WIDTH + 0 + + + C_AXI_AWUSER_WIDTH + 0 + + + C_AXI_ARUSER_WIDTH + 0 + + + C_AXI_WUSER_WIDTH + 0 + + + C_AXI_RUSER_WIDTH + 0 + + + C_AXI_BUSER_WIDTH + 0 + + + C_AXI_SUPPORTS_NARROW + 0 + + + C_AXI_HAS_BURST + 0 + + + C_AXI_HAS_LOCK + 0 + + + C_AXI_HAS_CACHE + 0 + + + C_AXI_HAS_REGION + 0 + + + C_AXI_HAS_PROT + 1 + + + C_AXI_HAS_QOS + 0 + + + C_AXI_HAS_WSTRB + 1 + + + C_AXI_HAS_BRESP + 1 + + + C_AXI_HAS_RRESP + 1 + + + C_AXI_HAS_ARESETN + 1 + + + + + + choice_list_04fafd91 + AXI3 + AXI4 + AXI4LITE + + + choice_list_6240decd + READ_ONLY + READ_WRITE + WRITE_ONLY + + + choice_list_642e7122 + MASTER + PASS_THROUGH + SLAVE + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_0fc128e8 + 0 + 0 + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi_mst_0.vho + vhdlTemplate + + + axi_mst_0.veo + verilogTemplate + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_8 + + + + xilinx_synthesisconstraints_view_fileset + + axi_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_8 + + + + xilinx_externalfiles_view_fileset + + axi_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axi_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axi_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_8 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_8 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_8 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 8 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_slv.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_slv.vhd new file mode 100644 index 0000000..6d4348a --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_slv.vhd @@ -0,0 +1,510 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + QOUT_REG : out std_logic_vector (31 downto 0) + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Output Registers. + QOUT_REG <= slv_reg0; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/axis_pfba_pr_4x256_v1.sv b/firmware/ip/axis_pfba_pr_4x256_v1/src/axis_pfba_pr_4x256_v1.sv new file mode 100644 index 0000000..5db508f --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/axis_pfba_pr_4x256_v1.sv @@ -0,0 +1,169 @@ +// Polyphase Filter Bank, 4 lanes, 256 channels, 50 % overlap. +// This block has FIR coefficients that are good for cascading +// with the Synthesis PFB only. +// s_axi_aclk : clock for s_axi_* +// aclk : clock for s_axis_* and m_axis_* +module axis_pfba_pr_4x256_v1 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // s_* and m_* reset/clock. + aresetn , + aclk , + + // S_AXIS for data input. + s_axis_tready , + s_axis_tvalid , + s_axis_tdata , + + // M_AXIS for data output. + m_axis_tvalid , + m_axis_tlast , + m_axis_tdata + ); + +parameter N = 256; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [4*32-1:0] s_axis_tdata; + +output m_axis_tvalid; +output m_axis_tlast; +output [8*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] QOUT_REG; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .QOUT_REG (QOUT_REG ) + ); + +// PFB Block. +pfb + #( + .N (256), + .L (4 ) + ) + pfb_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input data. + .s_axis_tready (s_axis_tready ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for output data. + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tlast (m_axis_tlast ), + .m_axis_tdata (m_axis_tdata ), + + // Registers. + .QOUT_REG (QOUT_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/README b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/README new file mode 100644 index 0000000..a8858c0 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/README @@ -0,0 +1,9 @@ +This block integrates Xilinx's SSR FFT, generated with Syetem Generator. + +The top level also includes the framing block, which aligns the data with +the input TLAST to ensure data is properly aligned. + +NOTE: This implementation does not use pkt_align block, which allows to +buffer packets in the case tvalid drops in the middle of a frame. This +simplified implementation will just discard samples and re-sync again. + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/framing.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/framing.vhd new file mode 100644 index 0000000..42f6086 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/framing.vhd @@ -0,0 +1,178 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity framing is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4; + + -- Bits. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- Synced outputs. + tdata : out std_logic_vector (2*SSR*B-1 downto 0); + tvalid : out std_logic + ); +end framing; + +architecture rtl of framing is + +constant NWAIT : Integer := 256; +constant NWAIT_LOG2 : Integer := Integer(ceil(log2(real(NWAIT)))); +constant CYCLES : Integer := NFFT/SSR; +constant CYCLES_LOG2 : Integer := Integer(ceil(log2(real(CYCLES)))); + +-- FSM. +type fsm_type is ( INIT_ST , + RST_ST , + S0_ST , + S1_ST , + S2_ST ); +signal current_state, next_state : fsm_type; + +signal rst_state : std_logic; + +signal data_r : std_logic_vector (s_axis_tdata'length-1 downto 0); +signal data_rr : std_logic_vector (s_axis_tdata'length-1 downto 0); + +signal valid_i : std_logic; +signal valid_r : std_logic; +signal valid_rr : std_logic; + +signal cnt_nwait : unsigned (NWAIT_LOG2-1 downto 0); +signal cnt : unsigned (CYCLES_LOG2-1 downto 0); + +begin + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( aresetn = '0' ) then + -- State register. + current_state <= INIT_ST; + + -- Pipeline registers. + data_r <= (others => '0'); + data_rr <= (others => '0'); + valid_r <= '0'; + valid_rr <= '0'; + + -- Counters. + cnt_nwait <= (others => '0'); + cnt <= (others => '0'); + else + -- State register. + current_state <= next_state; + + -- Pipeline registers. + data_r <= s_axis_tdata; + data_rr <= data_r; + valid_r <= valid_i; + valid_rr <= valid_r; + + -- Counters. + if ( rst_state = '1' ) then + cnt_nwait <= cnt_nwait + 1; + end if; + + if ( valid_i = '1' ) then + if ( cnt < to_unsigned(CYCLES-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + end if; + end if; + end if; + end if; +end process; + +-- Next state logic. +process (current_state, cnt_nwait, s_axis_tlast, cnt) +begin + case (current_state) is + when INIT_ST => + next_state <= RST_ST; + + when RST_ST => + if ( cnt_nwait < to_unsigned(NWAIT-1,cnt_nwait'length) ) then + next_state <= RST_ST; + else + next_state <= S0_ST; + end if; + + when S0_ST => + if ( s_axis_tlast = '1' ) then + -- Check if tlast is in the right position. + if ( cnt = to_unsigned(CYCLES-1,cnt'length) ) then + next_state <= S0_ST; + else + -- tlast in the wrong position. + next_state <= S1_ST; + end if; + else + next_state <= S0_ST; + end if; + + when S1_ST => + -- Wait until a frame is completed. + if ( cnt = to_unsigned(CYCLES-1,cnt'length) ) then + next_state <= S2_ST; + else + next_state <= S1_ST; + end if; + + when S2_ST => + -- Wait for the next tlast. + if ( s_axis_tlast = '1' ) then + next_state <= S0_ST; + else + next_state <= S2_ST; + end if; + + end case; +end process; + +-- Output logic. +process (current_state) +begin +rst_state <= '0'; +valid_i <= '0'; + case (current_state) is + when INIT_ST => + + when RST_ST => + rst_state <= '1'; + + when S0_ST => + valid_i <= '1'; + + when S1_ST => + valid_i <= '1'; + + when S2_ST => + + end case; +end process; + +-- Assign outputs. +tdata <= data_rr; +tvalid <= valid_rr; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/conv_pkg.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/conv_pkg.vhd new file mode 100644 index 0000000..b8f1a8f --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/conv_pkg.vhd @@ -0,0 +1,1922 @@ +--------------------------------------------------------------------- +-- +-- Package : conv_pkg +-- +-- Filename : conv_pkg.vhd +-- +-- Date : 8/16/99 +-- +-- Description : Package that defines constant values that is used in the +-- XBS and functions that convert one type to another. +-- +-- Note : This package uses a VHDL 93 constructs therefore when +-- compiling with ModelTech use: vcom -93 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package conv_pkg is + --------------------------------------------------------------------------- + -- Constant that tells whether we're simulating + --------------------------------------------------------------------------- + constant simulating : boolean := false + -- synthesis translate_off + or true + -- synthesis translate_on + ; + + --------------------------------------------------------------------------- + -- Constants for XBS + --------------------------------------------------------------------------- + -- Arithmetic types + constant xlUnsigned : integer := 1; + constant xlSigned : integer := 2; + constant xlFloat : integer := 3; + + -- Constants for Quantization and Overflow + constant xlWrap : integer := 1; + constant xlSaturate : integer := 2; + constant xlTruncate : integer := 1; + constant xlRound : integer := 2; + constant xlRoundBanker : integer := 3; + + -- Constants for xladdsub s-function + constant xlAddMode : integer := 1; + constant xlSubMode : integer := 2; + + --------------------------------------------------------------------------- + -- Black Box Attributes + --------------------------------------------------------------------------- + attribute black_box : boolean; -- for Synplicity (obsolete) + attribute syn_black_box : boolean; -- for Synplicity Version 6.0 + attribute fpga_dont_touch: string; -- for FPGA Express + attribute box_type : string; -- for XST + + --------------------------------------------------------------------------- + -- Attributes to keep clock enable signals + --------------------------------------------------------------------------- + attribute keep : string; + attribute syn_keep : boolean; + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type and vice versa + function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; + function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; + + -- convert a std_logic_vector to a signed type and vice versa + function std_logic_vector_to_signed(inp : std_logic_vector) return signed; + function signed_to_std_logic_vector(inp : signed) return std_logic_vector; + -- convert signed to unsigned and vice versa + function unsigned_to_signed(inp : unsigned) return signed; + function signed_to_unsigned(inp : signed) return unsigned; + -- Tests used in convert_type + function pos(inp : std_logic_vector; arith : INTEGER) return boolean; + function all_same(inp: std_logic_vector) return boolean; + function all_zeros(inp: std_logic_vector) return boolean; + function is_point_five(inp: std_logic_vector) return boolean; + function all_ones(inp: std_logic_vector) return boolean; + + + + -- Convert a fixed point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + -- slice a vector + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector; + + -- slice a signed + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned; + + -- slice a unsigned + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Quantization Functions + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + + -- Overflow functions + function max_signed(width : INTEGER) return std_logic_vector; + function min_signed(width : INTEGER) return std_logic_vector; + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) return std_logic_vector; + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + --------------------------------------------------------------------------- + -- Binary point alignment functions + --------------------------------------------------------------------------- + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; + + -- Returns the number of integer bits after alignment of fixed point num. + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector; + + -- Pad LSB with zeros + function pad_LSB(inp : std_logic_vector; new_width: integer) + return std_logic_vector; + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith : integer) + return std_logic_vector; + + -- Find the max & min integer. + function max(L, R: INTEGER) return INTEGER; + function min(L, R: INTEGER) return INTEGER; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean; + + -- convert a boolean into a signed + function boolean_to_signed (inp : boolean; width: integer) + return signed; + -- convert a boolean into an unsigned + function boolean_to_unsigned (inp : boolean; width: integer) + return unsigned; + -- convert a boolean into std_logic_vector + function boolean_to_vector (inp : boolean) + return std_logic_vector; + -- convert a std_logic into std_logic_vector + function std_logic_to_vector (inp : std_logic) + return std_logic_vector; + -- convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector; + + -- Convert std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer; + function std_logic_to_integer(constant inp : std_logic := '0') + return integer; + + -- Convert a binary string array element into a std_logic_vector + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector; + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector; + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector (inp : string; width : integer) + return std_logic_vector; + + -- Make a binary string that represents zero + function makeZeroBinStr (width : integer) return STRING; + + + --------------------------------------------------------------------------- + -- Debugging functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's (i.e., 0bXX.X) + function is_binary_string_invalid (inp : string) + return boolean; + -- Check for all U's (i.e., 0bUU.U) + function is_binary_string_undefined (inp : string) + return boolean; + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean; + + + -- convert a std_logic_vector to a real type and vice versa + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real; + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real; + + + -- convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector; + -- convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector; + + -- display_precision is the number of digits to display in ModelTech's + -- waveform viewer ( used in to_string(inp : real) ) + constant display_precision : integer := 20; + -- convert a real into a string type + function real_to_string (inp : real) return string; + + -- Check of 0b and the beginning of a string + function valid_bin_string(inp : string) return boolean; + + -- Convert a std_logic_vector to a binary string + function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; + -- Convert a std_logic to a binary string + function std_logic_to_bin_string(inp : std_logic) return string; + -- convert a std_logic_vector to a binary string and add a binary point + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string; + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string; + + -- convert a std_logic_vector value to a character + type stdlogic_to_char_t is array(std_logic) of character; + constant to_char : stdlogic_to_char_t := ( + 'U' => 'U', + 'X' => 'X', + '0' => '0', + '1' => '1', + 'Z' => 'Z', + 'W' => 'W', + 'L' => 'L', + 'H' => 'H', + '-' => '-'); + + -- synthesis translate_on + +end conv_pkg; + +package body conv_pkg is + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type + function std_logic_vector_to_unsigned(inp : std_logic_vector) + return unsigned + is + begin + return unsigned (inp); + end; + + -- convert an unsigend to a std_logic_vector + function unsigned_to_std_logic_vector(inp : unsigned) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert an std_logic_vector to a signed + function std_logic_vector_to_signed(inp : std_logic_vector) + return signed + is + begin + return signed (inp); + end; + + -- convert an std_logic_vector to a sigend + function signed_to_std_logic_vector(inp : signed) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert unsigned to signed + function unsigned_to_signed (inp : unsigned) + return signed + is + begin -- unsigned_to_signed + return signed(std_logic_vector(inp)); + end; + + + -- convert signed to unsigned + function signed_to_unsigned (inp : signed) + return unsigned + is + begin -- signed_to_unsigned + return unsigned(std_logic_vector(inp)); + end; + + -- Test if a number is positive + function pos(inp : std_logic_vector; arith : INTEGER) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := inp; + if arith = xlUnsigned then + return true; + else + if vec(width-1) = '0' then + return true; + else + return false; + end if; + end if; + + -- Error + return true; + end; + + function max_signed(width : INTEGER) + return std_logic_vector + is + variable ones : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + ones := (others => '1'); + result(width-1) := '0'; + result(width-2 downto 0) := ones; + return result; + end; + + function min_signed(width : INTEGER) + return std_logic_vector + is + variable zeros : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + zeros := (others => '0'); + result(width-1) := '1'; + result(width-2 downto 0) := zeros; + return result; + end; + + -- Check if all the bits are the same + function all_same(inp: std_logic_vector) return boolean + is + variable result: boolean; + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + begin + vec := inp; + result := true; + if width > 0 then + for i in 1 to width-1 loop + if vec(i) /= vec(0) then + result := false; + end if; + end loop; + end if; + return result; + end; + + + -- Check if a number is all zeros + function all_zeros(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable zero : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + zero := (others => '0'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Check if a number is point five + function is_point_five(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (width > 1) then + if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then + result := true; + else + result := false; + end if; + else + if (vec(width-1) = '1') then + result := true; + else + result := false; + end if; + end if; + + return result; + end; + + -- Check if a number is all ones + function all_ones(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable one : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + one := (others => '1'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then + result := true; + else + result := false; + end if; + return result; + end; + + + --------------------------------------------------------------------------- + -- Type conersion functions + --------------------------------------------------------------------------- + + + -- Calculate the width of the temp. full precision representation + function full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return integer + is + variable result : integer; + begin + result := old_width + 2; + return result; + end; + + -- Calculate the width of the temp. quantized representation + -- ASSUMES POSITIVE BIN_PT + function quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return integer + is + variable right_of_dp, left_of_dp, result : integer; + begin + + right_of_dp := max(new_bin_pt, old_bin_pt); + left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); + + result := (old_width + 2) + (new_bin_pt - old_bin_pt); + return result; + end; + + + + -- Convert one Fix point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector + is + constant fp_width : integer := + full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, new_width, + new_bin_pt, new_arith); + constant fp_bin_pt : integer := old_bin_pt; + constant fp_arith : integer := old_arith; + variable full_precision_result : std_logic_vector(fp_width-1 downto 0); + + constant q_width : integer := + quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith); + constant q_bin_pt : integer := new_bin_pt; + constant q_arith : integer := old_arith; + variable quantized_result : std_logic_vector(q_width-1 downto 0); + + variable result : std_logic_vector(new_width-1 downto 0); + begin + result := (others => '0'); + + full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, + fp_arith); + + -- Apply quantization functions. This will remove LSB bits. + if (quantization = xlRound) then + + quantized_result := round_towards_inf(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + elsif (quantization = xlRoundBanker) then + quantized_result := round_towards_even(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + else + quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, q_arith); + end if; + + + -- Apply overflow function. This will remove MSB bits. + if (overflow = xlSaturate) then + result := saturation_arith(quantized_result, q_width, q_bin_pt, + q_arith, new_width, new_bin_pt, new_arith); + else + result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, + new_width, new_bin_pt, new_arith); + end if; + + + return result; + end; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, new_width, + new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (new_width - new_bin_pt) + - (old_width - old_bin_pt); + -- Number of digits to add/subract to the right of the decimal point + constant right_of_dp : integer := (new_bin_pt - old_bin_pt); + + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable j : integer; + + begin + vec := inp; + for i in new_width-1 downto 0 loop + j := i - right_of_dp; + if ( j > old_width-1) then + -- Bits to the left of the decimal point + if (new_arith = xlUnsigned) then + -- If unsigned zero pad MSB + result(i) := '0'; + else + -- If signed, sign extend MSB + result(i) := vec(old_width-1); + end if; + elsif ( j >= 0) then + -- Copy bits from input + result(i) := vec(j); + else + -- zero pad LSB + result(i) := '0'; + end if; + end loop; + + return result; + end; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant q_width : integer := quotient'length; + constant f_width : integer := fraction'length; + constant vec_MSB : integer := q_width+f_width-1; + constant result_MSB : integer := q_width+fraction_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := ( quotient & fraction ); + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant inp_width : integer := inp'length; + constant vec_MSB : integer := inp_width-1; + constant result_MSB : integer := result_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := inp; + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + -- vector slice + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector + is + begin + return inp(upper downto lower); + end; + + -- signed slice + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- unsigned slice + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); + end; + + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); + end; + + function boolean_to_signed (inp : boolean; width : integer) + return signed + is + variable result : signed(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_unsigned (inp : boolean; width : integer) + return unsigned + is + variable result : unsigned(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_vector (inp : boolean) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function std_logic_to_vector (inp : std_logic) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result(0) := inp; + return result; + end; + + --------------------------------------------------------------------------- + -- Quantization Functions + --------------------------------------------------------------------------- + + -- Truncate LSB bits + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign Extent or zero extend if necessary + if new_arith = xlUnsigned then + result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); + else + result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + result := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + result := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + return result; + end; + + + -- Round towards infinity + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + if (new_arith = xlSigned) then + -- Roundeing logic for signed numbers + -- Example: + -- Fix(5,-2) = 101.11 (bin) -2.25 (dec) + -- Converted to: Fix(4,-1) = 101.1 (bin) -2.5 (dec) + -- Note: same algorithm used for unsigned numbers can't be used. + + -- 1st check the sign bit of the input to see if it is a positive + -- number + if (vec(old_width-1) = '0') then + one_or_zero(0) := '1'; + end if; + + -- 2nd check if digits being truncated are all zeros + -- (in example it is bit zero) + if (right_of_dp >= 2) and (right_of_dp <= old_width) then + if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then + one_or_zero(0) := '1'; + end if; + end if; + + -- 3rd check if the bit right before the truncation point is '1' + -- or '0' (in example it is bit one) + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if vec(right_of_dp-1) = '0' then + one_or_zero(0) := '0'; + end if; + else + -- No rounding to be performed + one_or_zero(0) := '0'; + end if; + else + -- For an unsigned number just check if the bit right before the + -- truncation point is '1' or '0' + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + one_or_zero(0) := vec(right_of_dp-1); + end if; + end if; + + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + -- Round towards even values + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + -- For the truncated bits just check if the bits after the + -- truncation point are 0.5 + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then + one_or_zero(0) := vec(right_of_dp-1); + else + one_or_zero(0) := vec(right_of_dp); + end if; + end if; + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + --------------------------------------------------------------------------- + -- Overflow Functions + --------------------------------------------------------------------------- + + -- Apply Saturation arithmetic. The new_bin_pt and old bin_pt should be + -- equal. The function chops bits off MSB bits. + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (old_width - old_bin_pt) - + (new_width - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable overflow : boolean; + begin + vec := inp; + overflow := true; + result := (others => '0'); + + ----------------------------------------------------------------------- + -- Check for cases when overflow does not occur + ----------------------------------------------------------------------- + + -- Output width is >= input width + if (new_width >= old_width) then + overflow := false; + end if; + + -- Case #1: + -- Both the input and output are signed and the bits that will + -- be truncated plus the sign bit are all the same + -- (i.e., number has been sign extended) + if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + -- Case #2: + -- If the input is converted to a unsigned from an signed then only + -- check the bits that will be truncated are all zero + if (old_arith = xlSigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + -- Check if input is positive + if (vec(new_width-1) = '0') then + overflow := false; + end if; + end if; + end if; + end if; + + -- Case #3: + -- Input is unsigned and the bits that will be truncated are all zero + if (old_arith = xlUnsigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + overflow := false; + end if; + end if; + end if; + + -- Case #4: + -- Input is unsigned but output signed and the bits that will be + -- truncated are all zero + if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + + if overflow then + -- Overflow occured + if new_arith = xlSigned then + -- Check sign bit and set to max signed or min signed value + if vec(old_width-1) = '0' then + result := max_signed(new_width); + else + result := min_signed(new_width); + end if; + else + -- Check sign bit and set to zero if negative + if ((old_arith = xlSigned) and vec(old_width-1) = '1') then + result := (others => '0'); + else + -- Set to max unsigned positive value + result := (others => '1'); + end if; + end if; + else + -- Overflow did not occur + + -- Check for case when input type is signed and output type + -- unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + -- if negative number set vec to zero + if (vec(old_width-1) = '1') then + vec := (others => '0'); + end if; + end if; + + if new_width <= old_width then + result := vec(new_width-1 downto 0); + else + -- Sign or zero extend number depending on arith of new number + if new_arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + end if; + end if; + + return result; + end; + + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + variable result_arith : integer; + begin + -- Check for case when input type is signed and output type unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + result_arith := xlSigned; + end if; + + result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); + + return result; + end; + + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is + begin + return max(a_bin_pt, b_bin_pt); + end; + + -- Returns the number of integer bits after alignment of fixed point num + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER is + begin + return max(a_width - a_bin_pt, b_width - b_bin_pt); + end; + + function pad_LSB(inp : std_logic_vector; new_width: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + -- Added for XST + constant pad_pos : integer := new_width - orig_width - 1; + + begin + vec := inp; + pos := new_width-1; + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pad_pos >= 0 then + for i in pad_pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + -- sign extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := vec(old_width-1); + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + -- zero extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := '0'; + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + begin + result(0) := inp; + for i in new_width-1 downto 1 loop + result(i) := '0'; + end loop; + + return result; + end; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + return result; + end; + + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + begin + vec := inp; + pos := new_width-1; + + if (arith = xlUnsigned) then + -- set MSB to zero + result(pos) := '0'; + pos := pos - 1; + else + -- sign extend + result(pos) := vec(orig_width-1); + pos := pos - 1; + end if; + + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pos >= 0 then + for i in pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector + is + variable vec : std_logic_vector(old_width-1 downto 0); + variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if delta > 0 then + padded_inp := pad_LSB(vec, old_width+delta); + + -- sign or zero extend zero padded input depending on arith type + result := extend_MSB(padded_inp, new_width, new_arith); + else + -- sign or zero extend input depending on arith type + result := extend_MSB(vec, new_width, new_arith); + end if; + + return result; + end; + + function max(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + function min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean is +-- constant NULL_Str : string := ""; + begin + if (left'length /= right'length) then + return false; + else + -- Check for NULL string + -- FPGA Express does not like empty strings +-- if (left'length = NULL_Str'length) or +-- (right'length = NULL_Str'length) then +-- return true; +-- end if; + test : for i in 1 to left'length loop + if left(i) /= right(i) then + return false; + end if; + end loop test; + return true; + end if; + end; + + + --------------------------------------------------------------------------- + -- Debugging and Simulation only functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's + function is_binary_string_invalid (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'X' ) then + result := true; + end if; + end loop; + return result; + end; + + -- Check for all U's + function is_binary_string_undefined (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'U' ) then + result := true; + end if; + end loop; + return result; + end; + + + + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + result := false; + for i in 0 to width-1 loop + if (vec(i) = 'U') or (vec(i) = 'X') then + result := true; + end if; + end loop; + return result; + end; + + -- Converts a std_logic_vector to a real + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real + is + variable vec : std_logic_vector(inp'length-1 downto 0); + variable result, shift_val, undefined_real : real; + variable neg_num : boolean; + begin + vec := inp; + result := 0.0; + neg_num := false; + if vec(inp'length-1) = '1' then + neg_num := true; + end if; + + for i in 0 to inp'length-1 loop + if vec(i) = 'U' or vec(i) = 'X' then + return undefined_real; + end if; + if arith = xlSigned then + if neg_num then + -- Perform 1's count if negative number + if vec(i) = '0' then + result := result + 2.0**i; + end if; + else + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + else + -- Unsigned numbers + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + end loop; + + if arith = xlSigned then + if neg_num then + -- Add one to 1's comp number to make 2's comp number + result := result + 1.0; + result := result * (-1.0); + end if; + end if; + -- Realign based on binary point + shift_val := 2.0**(-1*bin_pt); + result := result * shift_val; + return result; + end; + + -- This function is just for consistancy + -- bin_pt and arith not used. + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real + is + variable result : real := 0.0; + begin + if inp = '1' then + result := 1.0; + end if; + + if arith = xlSigned then + assert false + report "It doesn't make sense to convert a 1 bit number to a signed real."; + end if; + return result; + end; + + -- synthesis translate_on + -- Convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + begin + + if (arith = xlSigned) then + signed_val := to_signed(inp, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(inp, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- Convert an std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer + is + constant width : integer := inp'length; + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + variable result : integer; + begin + + if (arith = xlSigned) then + signed_val := std_logic_vector_to_signed(inp); + result := to_integer(signed_val); + else + unsigned_val := std_logic_vector_to_unsigned(inp); + result := to_integer(unsigned_val); + end if; + + return result; + end; + + function std_logic_to_integer(constant inp : std_logic := '0') + return integer + is + begin + if inp = '1' then + return 1; + else + return 0; + end if; + end; + + + function makeZeroBinStr (width : integer) return STRING is + variable result : string(1 to width+3); + begin + result(1) := '0'; + result(2) := 'b'; + for i in 3 to width+2 loop + result(i) := '0'; + end loop; -- i + result(width+3) := '.'; + + return result; + end; + + + + -- synthesis translate_off + -- Convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + begin + --result := to_std_logic_vector(real'value(inp), width, bin_pt, arith); + result := (others => '0'); + return result; + end; + + -- Convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector + is + variable real_val : real; + variable int_val : integer; + variable result : std_logic_vector(width-1 downto 0) := (others => '0'); + variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); + variable signed_val : signed(width-1 downto 0) := (others => '0'); + begin + + real_val := inp; + + -- Scale double and make it an integer + int_val := integer(real_val * 2.0**(bin_pt)); + + if (arith = xlSigned) then + signed_val := to_signed(int_val, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(int_val, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- synthesis translate_on + -- Check of 0b and the beginning of a string + function valid_bin_string (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + begin + vec := inp; + if (vec(1) = '0' and vec(2) = 'b') then + return true; + else + return false; + end if; + end; + + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector(inp: string; width : integer) + return std_logic_vector is + + constant strlen : integer := inp'LENGTH; + variable result : std_logic_vector(width-1 downto 0); + variable bitval : std_logic_vector((strlen*4)-1 downto 0); + variable posn : integer; + variable ch : character; + variable vec : string(1 to strlen); + begin + vec := inp; + + -- default value is zero + result := (others => '0'); + posn := (strlen*4)-1; + + for i in 1 to strlen loop + ch := vec(i); + case ch is + when '0' => bitval(posn downto posn-3) := "0000"; + when '1' => bitval(posn downto posn-3) := "0001"; + when '2' => bitval(posn downto posn-3) := "0010"; + when '3' => bitval(posn downto posn-3) := "0011"; + when '4' => bitval(posn downto posn-3) := "0100"; + when '5' => bitval(posn downto posn-3) := "0101"; + when '6' => bitval(posn downto posn-3) := "0110"; + when '7' => bitval(posn downto posn-3) := "0111"; + when '8' => bitval(posn downto posn-3) := "1000"; + when '9' => bitval(posn downto posn-3) := "1001"; + when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; + when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; + when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; + when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; + when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; + when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; + when others => bitval(posn downto posn-3) := "XXXX"; + -- synthesis translate_off + ASSERT false + REPORT "Invalid hex value" SEVERITY ERROR; + -- synthesis translate_on + end case; + posn := posn - 4; + end loop; + + if (width <= strlen*4) then + -- bitval larger than desired width + result := bitval(width-1 downto 0); + else + -- bitval smaller than desired width + -- MSB is padded with zeros since default value for result is all 0s + result((strlen*4)-1 downto 0) := bitval; + end if; + return result; + end; + + + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector + is + variable pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(inp'length-1 downto 0); + begin + vec := inp; + pos := inp'length-1; + -- Set default value + result := (others => '0'); + + for i in 1 to vec'length loop + -- synthesis translate_off + if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then + assert false + report "Input string is larger than output std_logic_vector. Truncating output."; + return result; + end if; + -- synthesis translate_on + + if vec(i) = '0' then + result(pos) := '0'; + pos := pos - 1; + end if; + if vec(i) = '1' then + result(pos) := '1'; + pos := pos - 1; + end if; + -- synthesis translate_off + if (vec(i) = 'X' or vec(i) = 'U') then + result(pos) := 'U'; + pos := pos - 1; + end if; + -- synthesis translate_on + end loop; + return result; + end; + + + -- Convert a binary string array element into a std_logic_vector + -- Example "0b000.0000000 0b001.0000000" + -- string_pos: 123456789111111111122222222 + -- 012345678901234567 + -- + -- "0b000.0000000" = inp(0) + -- "0b001.0000000" = inp(1) + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector + is + constant str_width : integer := width + 4; -- +4 for '0b' '.' & ' ' + constant inp_len : integer := inp'length; + constant num_elements : integer := (inp_len + 1)/str_width; + constant reverse_index : integer := (num_elements-1) - index; + + -- Calc position of desired str + variable left_pos : integer; + variable right_pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(width-1 downto 0); + begin + -- Can't pad input with a space (Synplicity crashes) + vec := inp; + + -- Set default value + result := (others => '0'); + + -- Special Case for string like "0b01.0" without extra ' ' after string + if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := 1; + right_pos := width + 3; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := (reverse_index * str_width) + 1; + right_pos := left_pos + width + 2; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + return result; + end; + -- synthesis translate_off + + -- + -- convert a std_logic_vector to a string + -- + function std_logic_vector_to_bin_string(inp : std_logic_vector) + return string + is + variable vec : std_logic_vector(1 to inp'length); + variable result : string(vec'range); + begin + vec := inp; + for i in vec'range loop + result(i) := to_char(vec(i)); + end loop; + return result; + end; + + -- + -- convert a std_logic to a string + -- + function std_logic_to_bin_string(inp : std_logic) + return string + is + variable result : string(1 to 3); + begin + -- Add 0b prefix + result(1) := '0'; + result(2) := 'b'; + result(3) := to_char(inp); + return result; + end; + + -- + -- convert a std_logic_vector to a string and add a binary point + -- + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string + is + variable width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable str_pos : integer; + variable result : string(1 to width+3); + begin + vec := inp; + -- Add 0b prefeix + str_pos := 1; + result(str_pos) := '0'; + str_pos := 2; + result(str_pos) := 'b'; + str_pos := 3; + for i in width-1 downto 0 loop + -- Insert decimal point + -- if i = (width - bin_pt + 1) then + if (((width+3) - bin_pt) = str_pos) then + result(str_pos) := '.'; + str_pos := str_pos + 1; + end if; + result(str_pos) := to_char(vec(i)); + str_pos := str_pos + 1; + end loop; + -- Add binary point at end of string when bin_pt = 0 + if (bin_pt = 0) then + result(str_pos) := '.'; + end if; + + return result; + end; + + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string + is + variable result : string(1 to width); + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := real_to_std_logic_vector(inp, width, bin_pt, arith); + result := std_logic_vector_to_bin_string(vec); + + return result; + end; + + + -- Convert a real to string + -- Note: the size of the string returned is 'display_precision' chars long + function real_to_string (inp : real) return string + is + variable result : string(1 to display_precision) := (others => ' '); + begin + result(real'image(inp)'range) := real'image(inp); + return result; + end; + + -- synthesis translate_on + + +end conv_pkg; + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/single_reg_w_init.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/single_reg_w_init.vhd new file mode 100644 index 0000000..26af1d6 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/single_reg_w_init.vhd @@ -0,0 +1,109 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : single_reg_w_init.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg_w_init.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity single_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end single_reg_w_init; + +architecture structural of single_reg_w_init is + function build_init_const(width: integer; + init_index: integer; + init_value: bit_vector) + return std_logic_vector + is + variable result: std_logic_vector(width - 1 downto 0); + begin + if init_index = 0 then + result := (others => '0'); + elsif init_index = 1 then + result := (others => '0'); + result(0) := '1'; + else + result := to_stdlogicvector(init_value); + end if; + return result; + end; + + component fdre + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + r: in std_ulogic + ); + end component; -- end fdre + attribute syn_black_box of fdre: component is true; + attribute fpga_dont_touch of fdre: component is "true"; + + component fdse + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + s: in std_ulogic + ); + end component; -- end fdse + attribute syn_black_box of fdse: component is true; + attribute fpga_dont_touch of fdse: component is "true"; + + constant init_const: std_logic_vector(width - 1 downto 0) + := build_init_const(width, init_index, init_value); +begin + fd_prim_array: for index in 0 to width - 1 generate + + bit_is_0: if (init_const(index) = '0') generate + fdre_comp: fdre + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + r => clr + ); + end generate; -- end bit_is_0 + + bit_is_1: if (init_const(index) = '1') generate + fdse_comp: fdse + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + s => clr + ); + end generate; -- end bit_is_1 + end generate; -- end fd_prim_array +end architecture structural; + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/srl17e.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/srl17e.vhd new file mode 100644 index 0000000..8ec9c8d --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/srl17e.vhd @@ -0,0 +1,93 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srl17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srl17e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srl17e; + +architecture structural of srl17e is + + component SRL16E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRL16E : component is true; + attribute fpga_dont_touch of SRL16E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srl16_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srl16_used: if latency > 1 generate + u1 : srl16e port map(clk => clk, + d => d_delayed(i), + q => srl16_out(i), + ce => ce, + a0 => a(0), + a1 => a(1), + a2 => a(2), + a3 => a(3)); + end generate; + srl16_not_used: if latency <= 1 generate + srl16_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srl16_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srl16_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/srl33e.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/srl33e.vhd new file mode 100644 index 0000000..c943462 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/srl33e.vhd @@ -0,0 +1,87 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srlc17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srlc33e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srlc33e; + +architecture structural of srlc33e is + + component SRLC32E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A : in std_logic_vector(4 downto 0); + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRLC32E : component is true; + attribute fpga_dont_touch of SRLC32E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srlc32_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srlc32_used: if latency > 1 generate + u1 : srlc32e port map(clk => clk, + d => d_delayed(i), + q => srlc32_out(i), + ce => ce, + a => a); + end generate; + srlc32_not_used: if latency <= 1 generate + srlc32_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srlc32_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srlc32_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256.vhd new file mode 100644 index 0000000..8ae6b87 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256.vhd @@ -0,0 +1,2133 @@ +-- Generated from Simulink block ssr_8x256/Vector FFT/Scalar2Vector +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_scalar2vector is + port ( + i : in std_logic_vector( 432-1 downto 0 ); + o_1 : out std_logic_vector( 54-1 downto 0 ); + o_2 : out std_logic_vector( 54-1 downto 0 ); + o_3 : out std_logic_vector( 54-1 downto 0 ); + o_4 : out std_logic_vector( 54-1 downto 0 ); + o_5 : out std_logic_vector( 54-1 downto 0 ); + o_6 : out std_logic_vector( 54-1 downto 0 ); + o_7 : out std_logic_vector( 54-1 downto 0 ); + o_8 : out std_logic_vector( 54-1 downto 0 ) + ); +end ssr_8x256_scalar2vector; +architecture structural of ssr_8x256_scalar2vector is + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); +begin + o_1 <= slice0_y_net; + o_2 <= slice1_y_net; + o_3 <= slice2_y_net; + o_4 <= slice3_y_net; + o_5 <= slice4_y_net; + o_6 <= slice5_y_net; + o_7 <= slice6_y_net; + o_8 <= slice7_y_net; + test_systolicfft_vhdl_black_box_o_net <= i; + slice0 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 53, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice0_y_net + ); + slice1 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 54, + new_msb => 107, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice1_y_net + ); + slice2 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 108, + new_msb => 161, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice2_y_net + ); + slice3 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 162, + new_msb => 215, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice3_y_net + ); + slice4 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 216, + new_msb => 269, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice4_y_net + ); + slice5 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 270, + new_msb => 323, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice5_y_net + ); + slice6 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 324, + new_msb => 377, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice6_y_net + ); + slice7 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 378, + new_msb => 431, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Concat +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_concat is + port ( + hi_1 : in std_logic_vector( 16-1 downto 0 ); + lo_1 : in std_logic_vector( 16-1 downto 0 ); + hi_2 : in std_logic_vector( 16-1 downto 0 ); + hi_3 : in std_logic_vector( 16-1 downto 0 ); + hi_4 : in std_logic_vector( 16-1 downto 0 ); + hi_5 : in std_logic_vector( 16-1 downto 0 ); + hi_6 : in std_logic_vector( 16-1 downto 0 ); + hi_7 : in std_logic_vector( 16-1 downto 0 ); + hi_8 : in std_logic_vector( 16-1 downto 0 ); + lo_2 : in std_logic_vector( 16-1 downto 0 ); + lo_3 : in std_logic_vector( 16-1 downto 0 ); + lo_4 : in std_logic_vector( 16-1 downto 0 ); + lo_5 : in std_logic_vector( 16-1 downto 0 ); + lo_6 : in std_logic_vector( 16-1 downto 0 ); + lo_7 : in std_logic_vector( 16-1 downto 0 ); + lo_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 32-1 downto 0 ); + out_2 : out std_logic_vector( 32-1 downto 0 ); + out_3 : out std_logic_vector( 32-1 downto 0 ); + out_4 : out std_logic_vector( 32-1 downto 0 ); + out_5 : out std_logic_vector( 32-1 downto 0 ); + out_6 : out std_logic_vector( 32-1 downto 0 ); + out_7 : out std_logic_vector( 32-1 downto 0 ); + out_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x256_vector_concat; +architecture structural of ssr_8x256_vector_concat is + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= concat0_y_net; + out_2 <= concat1_y_net; + out_3 <= concat2_y_net; + out_4 <= concat3_y_net; + out_5 <= concat4_y_net; + out_6 <= concat5_y_net; + out_7 <= concat6_y_net; + out_8 <= concat7_y_net; + reinterpret0_output_port_net_x0 <= hi_1; + reinterpret0_output_port_net <= lo_1; + reinterpret1_output_port_net_x0 <= hi_2; + reinterpret2_output_port_net_x0 <= hi_3; + reinterpret3_output_port_net_x0 <= hi_4; + reinterpret4_output_port_net_x0 <= hi_5; + reinterpret5_output_port_net_x0 <= hi_6; + reinterpret6_output_port_net_x0 <= hi_7; + reinterpret7_output_port_net_x0 <= hi_8; + reinterpret1_output_port_net <= lo_2; + reinterpret2_output_port_net <= lo_3; + reinterpret3_output_port_net <= lo_4; + reinterpret4_output_port_net <= lo_5; + reinterpret5_output_port_net <= lo_6; + reinterpret6_output_port_net <= lo_7; + reinterpret7_output_port_net <= lo_8; + concat0 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret0_output_port_net_x0, + in1 => reinterpret0_output_port_net, + y => concat0_y_net + ); + concat1 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret1_output_port_net_x0, + in1 => reinterpret1_output_port_net, + y => concat1_y_net + ); + concat2 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret2_output_port_net_x0, + in1 => reinterpret2_output_port_net, + y => concat2_y_net + ); + concat3 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret3_output_port_net_x0, + in1 => reinterpret3_output_port_net, + y => concat3_y_net + ); + concat4 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret4_output_port_net_x0, + in1 => reinterpret4_output_port_net, + y => concat4_y_net + ); + concat5 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret5_output_port_net_x0, + in1 => reinterpret5_output_port_net, + y => concat5_y_net + ); + concat6 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret6_output_port_net_x0, + in1 => reinterpret6_output_port_net, + y => concat6_y_net + ); + concat7 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret7_output_port_net_x0, + in1 => reinterpret7_output_port_net, + y => concat7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Delay +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_delay is + port ( + d_1 : in std_logic_vector( 32-1 downto 0 ); + d_2 : in std_logic_vector( 32-1 downto 0 ); + d_3 : in std_logic_vector( 32-1 downto 0 ); + d_4 : in std_logic_vector( 32-1 downto 0 ); + d_5 : in std_logic_vector( 32-1 downto 0 ); + d_6 : in std_logic_vector( 32-1 downto 0 ); + d_7 : in std_logic_vector( 32-1 downto 0 ); + d_8 : in std_logic_vector( 32-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + q_1 : out std_logic_vector( 32-1 downto 0 ); + q_2 : out std_logic_vector( 32-1 downto 0 ); + q_3 : out std_logic_vector( 32-1 downto 0 ); + q_4 : out std_logic_vector( 32-1 downto 0 ); + q_5 : out std_logic_vector( 32-1 downto 0 ); + q_6 : out std_logic_vector( 32-1 downto 0 ); + q_7 : out std_logic_vector( 32-1 downto 0 ); + q_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x256_vector_delay; +architecture structural of ssr_8x256_vector_delay is + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal ce_net : std_logic; + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal clk_net : std_logic; + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); +begin + q_1 <= delay0_q_net; + q_2 <= delay1_q_net; + q_3 <= delay2_q_net; + q_4 <= delay3_q_net; + q_5 <= delay4_q_net; + q_6 <= delay5_q_net; + q_7 <= delay6_q_net; + q_8 <= delay7_q_net; + concat0_y_net <= d_1; + concat1_y_net <= d_2; + concat2_y_net <= d_3; + concat3_y_net <= d_4; + concat4_y_net <= d_5; + concat5_y_net <= d_6; + concat6_y_net <= d_7; + concat7_y_net <= d_8; + clk_net <= clk_1; + ce_net <= ce_1; + delay0 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat0_y_net, + clk => clk_net, + ce => ce_net, + q => delay0_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat1_y_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net + ); + delay2 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat2_y_net, + clk => clk_net, + ce => ce_net, + q => delay2_q_net + ); + delay3 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat3_y_net, + clk => clk_net, + ce => ce_net, + q => delay3_q_net + ); + delay4 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat4_y_net, + clk => clk_net, + ce => ce_net, + q => delay4_q_net + ); + delay5 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat5_y_net, + clk => clk_net, + ce => ce_net, + q => delay5_q_net + ); + delay6 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat6_y_net, + clk => clk_net, + ce => ce_net, + q => delay6_q_net + ); + delay7 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat7_y_net, + clk => clk_net, + ce => ce_net, + q => delay7_q_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Reinterpret +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_reinterpret is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x256_vector_reinterpret; +architecture structural of ssr_8x256_vector_reinterpret is + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_re_0_net <= in_1; + i_re_1_net <= in_2; + i_re_2_net <= in_3; + i_re_3_net <= in_4; + i_re_4_net <= in_5; + i_re_5_net <= in_6; + i_re_6_net <= in_7; + i_re_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Reinterpret1 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_reinterpret1 is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x256_vector_reinterpret1; +architecture structural of ssr_8x256_vector_reinterpret1 is + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_im_0_net <= in_1; + i_im_1_net <= in_2; + i_im_2_net <= in_3; + i_im_3_net <= in_4; + i_im_4_net <= in_5; + i_im_5_net <= in_6; + i_im_6_net <= in_7; + i_im_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Reinterpret2 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_reinterpret2 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_reinterpret2; +architecture structural of ssr_8x256_vector_reinterpret2 is + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Reinterpret3 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_reinterpret3 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_reinterpret3; +architecture structural of ssr_8x256_vector_reinterpret3 is + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Slice Im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_slice_im is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_slice_im; +architecture structural of ssr_8x256_vector_slice_im is + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Slice Re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_slice_re is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_slice_re; +architecture structural of ssr_8x256_vector_slice_re is + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector2Scalar +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector2scalar is + port ( + i_1 : in std_logic_vector( 32-1 downto 0 ); + i_2 : in std_logic_vector( 32-1 downto 0 ); + i_3 : in std_logic_vector( 32-1 downto 0 ); + i_4 : in std_logic_vector( 32-1 downto 0 ); + i_5 : in std_logic_vector( 32-1 downto 0 ); + i_6 : in std_logic_vector( 32-1 downto 0 ); + i_7 : in std_logic_vector( 32-1 downto 0 ); + i_8 : in std_logic_vector( 32-1 downto 0 ); + o : out std_logic_vector( 256-1 downto 0 ) + ); +end ssr_8x256_vector2scalar; +architecture structural of ssr_8x256_vector2scalar is + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); +begin + o <= concat1_y_net; + delay0_q_net <= i_1; + delay1_q_net <= i_2; + delay2_q_net <= i_3; + delay3_q_net <= i_4; + delay4_q_net <= i_5; + delay5_q_net <= i_6; + delay6_q_net <= i_7; + delay7_q_net <= i_8; + concat1 : entity xil_defaultlib.sysgen_concat_c6ccfb3c89 + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => delay7_q_net, + in1 => delay6_q_net, + in2 => delay5_q_net, + in3 => delay4_q_net, + in4 => delay3_q_net, + in5 => delay2_q_net, + in6 => delay1_q_net, + in7 => delay0_q_net, + y => concat1_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_fft is + port ( + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + vi : in std_logic_vector( 1-1 downto 0 ); + si : in std_logic_vector( 8-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_8 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_8 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + vo : out std_logic; + so : out std_logic_vector( 8-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_8 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_fft; +architecture structural of ssr_8x256_vector_fft is + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_scale_net : std_logic_vector( 8-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 8-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_vo_net : std_logic; + signal reinterpret0_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret6_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); + signal slice3_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal slice5_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret7_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret4_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice6_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal reinterpret6_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal ce_net : std_logic; + signal slice4_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice0_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal concat1_y_net_x0 : std_logic_vector( 32-1 downto 0 ); + signal slice1_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal slice2_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal clk_net : std_logic; + signal slice7_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay_q_net : std_logic_vector( 1-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay1_q_net_x0 : std_logic_vector( 8-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); +begin + o_re_1 <= reinterpret0_output_port_net_x0; + o_im_1 <= reinterpret0_output_port_net; + vo <= test_systolicfft_vhdl_black_box_vo_net; + so <= test_systolicfft_vhdl_black_box_so_net; + o_re_2 <= reinterpret1_output_port_net_x0; + o_re_3 <= reinterpret2_output_port_net_x0; + o_re_4 <= reinterpret3_output_port_net_x0; + o_re_5 <= reinterpret4_output_port_net_x0; + o_re_6 <= reinterpret5_output_port_net_x0; + o_re_7 <= reinterpret6_output_port_net_x0; + o_re_8 <= reinterpret7_output_port_net_x0; + o_im_2 <= reinterpret1_output_port_net; + o_im_3 <= reinterpret2_output_port_net; + o_im_4 <= reinterpret3_output_port_net; + o_im_5 <= reinterpret4_output_port_net; + o_im_6 <= reinterpret5_output_port_net; + o_im_7 <= reinterpret6_output_port_net; + o_im_8 <= reinterpret7_output_port_net; + i_re_0_net <= i_re_1; + i_im_0_net <= i_im_1; + i_valid_net <= vi; + i_scale_net <= si; + i_re_1_net <= i_re_2; + i_re_2_net <= i_re_3; + i_re_3_net <= i_re_4; + i_re_4_net <= i_re_5; + i_re_5_net <= i_re_6; + i_re_6_net <= i_re_7; + i_re_7_net <= i_re_8; + i_im_1_net <= i_im_2; + i_im_2_net <= i_im_3; + i_im_3_net <= i_im_4; + i_im_4_net <= i_im_5; + i_im_5_net <= i_im_6; + i_im_6_net <= i_im_7; + i_im_7_net <= i_im_8; + clk_net <= clk_1; + ce_net <= ce_1; + scalar2vector : entity xil_defaultlib.ssr_8x256_scalar2vector + port map ( + i => test_systolicfft_vhdl_black_box_o_net, + o_1 => slice0_y_net_x1, + o_2 => slice1_y_net_x1, + o_3 => slice2_y_net_x1, + o_4 => slice3_y_net_x1, + o_5 => slice4_y_net_x1, + o_6 => slice5_y_net_x1, + o_7 => slice6_y_net_x1, + o_8 => slice7_y_net_x1 + ); + vector_concat : entity xil_defaultlib.ssr_8x256_vector_concat + port map ( + hi_1 => reinterpret0_output_port_net_x1, + lo_1 => reinterpret0_output_port_net_x2, + hi_2 => reinterpret1_output_port_net_x1, + hi_3 => reinterpret2_output_port_net_x1, + hi_4 => reinterpret3_output_port_net_x1, + hi_5 => reinterpret4_output_port_net_x1, + hi_6 => reinterpret5_output_port_net_x1, + hi_7 => reinterpret6_output_port_net_x1, + hi_8 => reinterpret7_output_port_net_x1, + lo_2 => reinterpret1_output_port_net_x2, + lo_3 => reinterpret2_output_port_net_x2, + lo_4 => reinterpret3_output_port_net_x2, + lo_5 => reinterpret4_output_port_net_x2, + lo_6 => reinterpret5_output_port_net_x2, + lo_7 => reinterpret6_output_port_net_x2, + lo_8 => reinterpret7_output_port_net_x2, + out_1 => concat0_y_net, + out_2 => concat1_y_net_x0, + out_3 => concat2_y_net, + out_4 => concat3_y_net, + out_5 => concat4_y_net, + out_6 => concat5_y_net, + out_7 => concat6_y_net, + out_8 => concat7_y_net + ); + vector_delay : entity xil_defaultlib.ssr_8x256_vector_delay + port map ( + d_1 => concat0_y_net, + d_2 => concat1_y_net_x0, + d_3 => concat2_y_net, + d_4 => concat3_y_net, + d_5 => concat4_y_net, + d_6 => concat5_y_net, + d_7 => concat6_y_net, + d_8 => concat7_y_net, + clk_1 => clk_net, + ce_1 => ce_net, + q_1 => delay0_q_net, + q_2 => delay1_q_net, + q_3 => delay2_q_net, + q_4 => delay3_q_net, + q_5 => delay4_q_net, + q_6 => delay5_q_net, + q_7 => delay6_q_net, + q_8 => delay7_q_net + ); + vector_reinterpret : entity xil_defaultlib.ssr_8x256_vector_reinterpret + port map ( + in_1 => i_re_0_net, + in_2 => i_re_1_net, + in_3 => i_re_2_net, + in_4 => i_re_3_net, + in_5 => i_re_4_net, + in_6 => i_re_5_net, + in_7 => i_re_6_net, + in_8 => i_re_7_net, + out_1 => reinterpret0_output_port_net_x2, + out_2 => reinterpret1_output_port_net_x2, + out_3 => reinterpret2_output_port_net_x2, + out_4 => reinterpret3_output_port_net_x2, + out_5 => reinterpret4_output_port_net_x2, + out_6 => reinterpret5_output_port_net_x2, + out_7 => reinterpret6_output_port_net_x2, + out_8 => reinterpret7_output_port_net_x2 + ); + vector_reinterpret1 : entity xil_defaultlib.ssr_8x256_vector_reinterpret1 + port map ( + in_1 => i_im_0_net, + in_2 => i_im_1_net, + in_3 => i_im_2_net, + in_4 => i_im_3_net, + in_5 => i_im_4_net, + in_6 => i_im_5_net, + in_7 => i_im_6_net, + in_8 => i_im_7_net, + out_1 => reinterpret0_output_port_net_x1, + out_2 => reinterpret1_output_port_net_x1, + out_3 => reinterpret2_output_port_net_x1, + out_4 => reinterpret3_output_port_net_x1, + out_5 => reinterpret4_output_port_net_x1, + out_6 => reinterpret5_output_port_net_x1, + out_7 => reinterpret6_output_port_net_x1, + out_8 => reinterpret7_output_port_net_x1 + ); + vector_reinterpret2 : entity xil_defaultlib.ssr_8x256_vector_reinterpret2 + port map ( + in_1 => slice0_y_net, + in_2 => slice1_y_net, + in_3 => slice2_y_net, + in_4 => slice3_y_net, + in_5 => slice4_y_net, + in_6 => slice5_y_net, + in_7 => slice6_y_net, + in_8 => slice7_y_net, + out_1 => reinterpret0_output_port_net_x0, + out_2 => reinterpret1_output_port_net_x0, + out_3 => reinterpret2_output_port_net_x0, + out_4 => reinterpret3_output_port_net_x0, + out_5 => reinterpret4_output_port_net_x0, + out_6 => reinterpret5_output_port_net_x0, + out_7 => reinterpret6_output_port_net_x0, + out_8 => reinterpret7_output_port_net_x0 + ); + vector_reinterpret3 : entity xil_defaultlib.ssr_8x256_vector_reinterpret3 + port map ( + in_1 => slice0_y_net_x0, + in_2 => slice1_y_net_x0, + in_3 => slice2_y_net_x0, + in_4 => slice3_y_net_x0, + in_5 => slice4_y_net_x0, + in_6 => slice5_y_net_x0, + in_7 => slice6_y_net_x0, + in_8 => slice7_y_net_x0, + out_1 => reinterpret0_output_port_net, + out_2 => reinterpret1_output_port_net, + out_3 => reinterpret2_output_port_net, + out_4 => reinterpret3_output_port_net, + out_5 => reinterpret4_output_port_net, + out_6 => reinterpret5_output_port_net, + out_7 => reinterpret6_output_port_net, + out_8 => reinterpret7_output_port_net + ); + vector_slice_im : entity xil_defaultlib.ssr_8x256_vector_slice_im + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net_x0, + out_2 => slice1_y_net_x0, + out_3 => slice2_y_net_x0, + out_4 => slice3_y_net_x0, + out_5 => slice4_y_net_x0, + out_6 => slice5_y_net_x0, + out_7 => slice6_y_net_x0, + out_8 => slice7_y_net_x0 + ); + vector_slice_re : entity xil_defaultlib.ssr_8x256_vector_slice_re + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net, + out_2 => slice1_y_net, + out_3 => slice2_y_net, + out_4 => slice3_y_net, + out_5 => slice4_y_net, + out_6 => slice5_y_net, + out_7 => slice6_y_net, + out_8 => slice7_y_net + ); + vector2scalar : entity xil_defaultlib.ssr_8x256_vector2scalar + port map ( + i_1 => delay0_q_net, + i_2 => delay1_q_net, + i_3 => delay2_q_net, + i_4 => delay3_q_net, + i_5 => delay4_q_net, + i_6 => delay5_q_net, + i_7 => delay6_q_net, + i_8 => delay7_q_net, + o => concat1_y_net + ); + delay : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 1 + ) + port map ( + en => '1', + rst => '0', + d => i_valid_net, + clk => clk_net, + ce => ce_net, + q => delay_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 8 + ) + port map ( + en => '1', + rst => '0', + d => i_scale_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net_x0 + ); + test_systolicfft_vhdl_black_box : entity xil_defaultlib.WRAPPER_VECTOR_FFT_c48f0cd3f27fd6fdac4ed316c161272e + generic map ( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 8, + N => 256, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map ( + i => concat1_y_net, + vi => delay_q_net(0), + si => delay1_q_net_x0, + CLK => clk_net, + CE => ce_net, + o => test_systolicfft_vhdl_black_box_o_net, + vo => test_systolicfft_vhdl_black_box_vo_net, + so => test_systolicfft_vhdl_black_box_so_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/i_im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_i_im is + port ( + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x256_i_im; +architecture structural of ssr_8x256_i_im is + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); +begin + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; +end structural; +-- Generated from Simulink block ssr_8x256/i_re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_i_re is + port ( + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x256_i_re; +architecture structural of ssr_8x256_i_re is + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); +begin + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; +end structural; +-- Generated from Simulink block ssr_8x256_struct +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_struct is + port ( + i_scale : in std_logic_vector( 8-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_scale : out std_logic_vector( 8-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_struct; +architecture structural of ssr_8x256_struct is + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_vo_net : std_logic_vector( 1-1 downto 0 ); + signal i_scale_net : std_logic_vector( 8-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 8-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal clk_net : std_logic; + signal ce_net : std_logic; + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); +begin + i_scale_net <= i_scale; + i_valid_net <= i_valid; + o_scale <= test_systolicfft_vhdl_black_box_so_net; + o_valid <= test_systolicfft_vhdl_black_box_vo_net; + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; + o_im_0 <= reinterpret0_output_port_net; + o_im_1 <= reinterpret1_output_port_net; + o_im_2 <= reinterpret2_output_port_net; + o_im_3 <= reinterpret3_output_port_net; + o_im_4 <= reinterpret4_output_port_net_x0; + o_im_5 <= reinterpret5_output_port_net; + o_im_6 <= reinterpret6_output_port_net; + o_im_7 <= reinterpret7_output_port_net; + o_re_0 <= reinterpret0_output_port_net_x0; + o_re_1 <= reinterpret1_output_port_net_x0; + o_re_2 <= reinterpret2_output_port_net_x0; + o_re_3 <= reinterpret3_output_port_net_x0; + o_re_4 <= reinterpret4_output_port_net; + o_re_5 <= reinterpret5_output_port_net_x0; + o_re_6 <= reinterpret6_output_port_net_x0; + o_re_7 <= reinterpret7_output_port_net_x0; + clk_net <= clk_1; + ce_net <= ce_1; + vector_fft : entity xil_defaultlib.ssr_8x256_vector_fft + port map ( + i_re_1 => i_re_0_net, + i_im_1 => i_im_0_net, + vi => i_valid_net, + si => i_scale_net, + i_re_2 => i_re_1_net, + i_re_3 => i_re_2_net, + i_re_4 => i_re_3_net, + i_re_5 => i_re_4_net, + i_re_6 => i_re_5_net, + i_re_7 => i_re_6_net, + i_re_8 => i_re_7_net, + i_im_2 => i_im_1_net, + i_im_3 => i_im_2_net, + i_im_4 => i_im_3_net, + i_im_5 => i_im_4_net, + i_im_6 => i_im_5_net, + i_im_7 => i_im_6_net, + i_im_8 => i_im_7_net, + clk_1 => clk_net, + ce_1 => ce_net, + o_re_1 => reinterpret0_output_port_net_x0, + o_im_1 => reinterpret0_output_port_net, + vo => test_systolicfft_vhdl_black_box_vo_net(0), + so => test_systolicfft_vhdl_black_box_so_net, + o_re_2 => reinterpret1_output_port_net_x0, + o_re_3 => reinterpret2_output_port_net_x0, + o_re_4 => reinterpret3_output_port_net_x0, + o_re_5 => reinterpret4_output_port_net, + o_re_6 => reinterpret5_output_port_net_x0, + o_re_7 => reinterpret6_output_port_net_x0, + o_re_8 => reinterpret7_output_port_net_x0, + o_im_2 => reinterpret1_output_port_net, + o_im_3 => reinterpret2_output_port_net, + o_im_4 => reinterpret3_output_port_net, + o_im_5 => reinterpret4_output_port_net_x0, + o_im_6 => reinterpret5_output_port_net, + o_im_7 => reinterpret6_output_port_net, + o_im_8 => reinterpret7_output_port_net + ); + i_im : entity xil_defaultlib.ssr_8x256_i_im + port map ( + i_im_0 => i_im_0_net, + i_im_1 => i_im_1_net, + i_im_2 => i_im_2_net, + i_im_3 => i_im_3_net, + i_im_4 => i_im_4_net, + i_im_5 => i_im_5_net, + i_im_6 => i_im_6_net, + i_im_7 => i_im_7_net + ); + i_re : entity xil_defaultlib.ssr_8x256_i_re + port map ( + i_re_0 => i_re_0_net, + i_re_1 => i_re_1_net, + i_re_2 => i_re_2_net, + i_re_3 => i_re_3_net, + i_re_4 => i_re_4_net, + i_re_5 => i_re_5_net, + i_re_6 => i_re_6_net, + i_re_7 => i_re_7_net + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_default_clock_driver is + port ( + ssr_8x256_sysclk : in std_logic; + ssr_8x256_sysce : in std_logic; + ssr_8x256_sysclr : in std_logic; + ssr_8x256_clk1 : out std_logic; + ssr_8x256_ce1 : out std_logic + ); +end ssr_8x256_default_clock_driver; +architecture structural of ssr_8x256_default_clock_driver is +begin + clockdriver : entity xil_defaultlib.xlclockdriver + generic map ( + period => 1, + log_2_period => 1 + ) + port map ( + sysclk => ssr_8x256_sysclk, + sysce => ssr_8x256_sysce, + sysclr => ssr_8x256_sysclr, + clk => ssr_8x256_clk1, + ce => ssr_8x256_ce1 + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256 is + port ( + i_scale : in std_logic_vector( 8-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk : in std_logic; + o_scale : out std_logic_vector( 8-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256; +architecture structural of ssr_8x256 is + attribute core_generation_info : string; + attribute core_generation_info of structural : architecture is "ssr_8x256,sysgen_core_2019_2,{,compilation=HDL Netlist,block_icon_display=Default,family=zynquplusRFSOC,part=xczu28dr,speed=-2-e,package=ffvg1517,synthesis_language=vhdl,hdl_library=xil_defaultlib,synthesis_strategy=Vivado Synthesis Defaults,implementation_strategy=Vivado Implementation Defaults,testbench=0,interface_doc=0,ce_clr=0,clock_period=10,system_simulink_period=1,waveform_viewer=0,axilite_interface=0,ip_catalog_plugin=0,hwcosim_burst_mode=0,simulation_time=10,blackbox2=1,concat=9,delay=10,reinterpret=32,slice=24,}"; + signal clk_1_net : std_logic; + signal ce_1_net : std_logic; +begin + ssr_8x256_default_clock_driver : entity xil_defaultlib.ssr_8x256_default_clock_driver + port map ( + ssr_8x256_sysclk => clk, + ssr_8x256_sysce => '1', + ssr_8x256_sysclr => '0', + ssr_8x256_clk1 => clk_1_net, + ssr_8x256_ce1 => ce_1_net + ); + ssr_8x256_struct : entity xil_defaultlib.ssr_8x256_struct + port map ( + i_scale => i_scale, + i_valid => i_valid, + i_im_0 => i_im_0, + i_im_1 => i_im_1, + i_im_2 => i_im_2, + i_im_3 => i_im_3, + i_im_4 => i_im_4, + i_im_5 => i_im_5, + i_im_6 => i_im_6, + i_im_7 => i_im_7, + i_re_0 => i_re_0, + i_re_1 => i_re_1, + i_re_2 => i_re_2, + i_re_3 => i_re_3, + i_re_4 => i_re_4, + i_re_5 => i_re_5, + i_re_6 => i_re_6, + i_re_7 => i_re_7, + clk_1 => clk_1_net, + ce_1 => ce_1_net, + o_scale => o_scale, + o_valid => o_valid, + o_im_0 => o_im_0, + o_im_1 => o_im_1, + o_im_2 => o_im_2, + o_im_3 => o_im_3, + o_im_4 => o_im_4, + o_im_5 => o_im_5, + o_im_6 => o_im_6, + o_im_7 => o_im_7, + o_re_0 => o_re_0, + o_re_1 => o_re_1, + o_re_2 => o_re_2, + o_re_3 => o_re_3, + o_re_4 => o_re_4, + o_re_5 => o_re_5, + o_re_6 => o_re_6, + o_re_7 => o_re_7 + ); +end structural; diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd new file mode 100644 index 0000000..9ed7c14 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd @@ -0,0 +1,6159 @@ +------------------------------------------------------------------- +-- System Generator version 2019.2 VHDL source file. +-- +-- Copyright(C) 2019 by Xilinx, Inc. All rights reserved. This +-- text/file contains proprietary, confidential information of Xilinx, +-- Inc., is distributed under license from Xilinx, Inc., and may be used, +-- copied and/or disclosed only pursuant to the terms of a valid license +-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use +-- this text/file solely for design, simulation, implementation and +-- creation of design files limited to Xilinx devices or technologies. +-- Use with non-Xilinx devices or technologies is expressly prohibited +-- and immediately terminates your license unless covered by a separate +-- agreement. +-- +-- Xilinx is providing this design, code, or information "as is" solely +-- for use in developing programs and solutions for Xilinx devices. By +-- providing this design, code, or information as one possible +-- implementation of this feature, application or standard, Xilinx is +-- making no representation that this implementation is free from any +-- claims of infringement. You are responsible for obtaining any rights +-- you may require for your implementation. Xilinx expressly disclaims +-- any warranty whatsoever with respect to the adequacy of the +-- implementation, including but not limited to warranties of +-- merchantability or fitness for a particular purpose. +-- +-- Xilinx products are not intended for use in life support appliances, +-- devices, or systems. Use in such applications is expressly prohibited. +-- +-- Any modifications that are made to the source code are done at the user's +-- sole risk and will be unsupported. +-- +-- This copyright and support notice must be retained as part of this +-- text at all times. (c) Copyright 1995-2019 Xilinx, Inc. All rights +-- reserved. +------------------------------------------------------------------- + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x256_xldelay is + generic(width : integer := -1; + latency : integer := -1; + reg_retiming : integer := 0; + reset : integer := 0); + port(d : in std_logic_vector (width-1 downto 0); + ce : in std_logic; + clk : in std_logic; + en : in std_logic; + rst : in std_logic; + q : out std_logic_vector (width-1 downto 0)); + +end ssr_8x256_xldelay; + +architecture behavior of ssr_8x256_xldelay is + component synth_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; -- end component synth_reg + + component synth_reg_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; + + signal internal_ce : std_logic; + +begin + internal_ce <= ce and en; + + srl_delay: if ((reg_retiming = 0) and (reset = 0)) or (latency < 1) generate + synth_reg_srl_inst : synth_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => '0', + clk => clk, + o => q); + end generate srl_delay; + + reg_delay: if ((reg_retiming = 1) or (reset = 1)) and (latency >= 1) generate + synth_reg_reg_inst : synth_reg_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => rst, + clk => clk, + o => q); + end generate reg_delay; +end architecture behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: COMPLEX_FIXED_PKG.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Package Name: COMPLEX_FIXED_PKG +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Unconstrained Size Vectors and Matrices of Complex Arbitrary Precision Fixed Point Numbers +-- +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +package COMPLEX_FIXED_PKG is + type BOOLEAN_VECTOR is array(NATURAL range <>) of BOOLEAN; + type INTEGER_VECTOR is array(NATURAL range <>) of INTEGER; + type REAL_VECTOR is array(NATURAL range <>) of REAL; +--2008 type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED; + type COMPLEX_VECTOR is array(INTEGER range <>) of COMPLEX; + + type SFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point signed number, like SIGNED but lower bound can be negative +--2008 type SFIXED_VECTOR is array(INTEGER range <>) of SFIXED; -- unconstrained array of SFIXED +--2008 type CFIXED is record RE,IM:SFIXED; end record; -- arbitrary precision fixed point complex signed number +--2008 type CFIXED_VECTOR is array(INTEGER range <>) of CFIXED; -- unconstrained array of CFIXED +--2008 type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR; -- unconstrained array of CFIXED_VECTOR + type SFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of SFIXED, vector size must be given by a separate generic + type CFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point complex signed number, CFIXED'low is always even and CFIXED'high is always odd + type CFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of CFIXED, vector size must be given by a separate generic + +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED; -- returns the CFIXED range for X(K) +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).RE +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).IM + + function MIN(A,B:INTEGER) return INTEGER; + function MIN(A,B,C:INTEGER) return INTEGER; + function MIN(A,B,C,D:INTEGER) return INTEGER; + function MED(A,B,C:INTEGER) return INTEGER; + function MAX(A,B:INTEGER) return INTEGER; + function MAX(A,B,C:INTEGER) return INTEGER; + function MAX(A,B,C,D:INTEGER) return INTEGER; + function "+"(X,Y:SFIXED) return SFIXED; -- full precision add with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X,Y:SFIXED) return SFIXED; -- full precision subtract with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X:SFIXED) return SFIXED; -- full precision negate with SFIXED(X'high+1 downto X'low) result + function "*"(X,Y:SFIXED) return SFIXED; -- full precision multiply with SFIXED(X'high+Y'high+1 downto X'low+Y'low) result + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED; -- multiply by 0 or 1 with SFIXED(X'high downto X'low) result + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED; -- resizes X and returns SFIXED(H downto L) + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED; -- resizes X to match HL and returns SFIXED(HL'high downto HL'low) + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high+N downto X'low+N) result + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED; -- returns SFIXED(H downto L) result + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED; -- returns SFIXED(HL'high downto HL'low) result + function TO_REAL(S:SFIXED) return REAL; -- returns REAL result +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED; -- returns element K out of an N-size array X + + function RE(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vRE(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure RE(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function IM(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vIM(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure IM(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function "+"(X,Y:CFIXED) return CFIXED; -- full precision add with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "-"(X,Y:CFIXED) return CFIXED; -- full precision subtract with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "*"(X,Y:CFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high+2 downto X'low+Y'low) result + function "*"(X:CFIXED;Y:SFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high downto X'low+Y'low) result + function "*"(X:SFIXED;Y:CFIXED) return CFIXED; + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED; -- resizes X and returns CFIXED(H downto L) + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED; -- resizes X to match HL and returns CFIXED(HL'high downto HL'low) + function PLUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function "-"(X:CFIXED) return CFIXED; -- full precision negate with CFIXED(X'high+2 downto X'low) result + function MINUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function SWAP(X:CFIXED) return CFIXED; -- returns CFIXED(X'high downto X'low) result + function CONJ(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high+N downto X'low+N) result + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED; -- returns CFIXED(H downto L) result + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED; -- returns CFIXED(HL'high downto HL'low) result + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED; -- returns CFIXED(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_CFIXED(R,I:SFIXED) return CFIXED; -- returns CFIXED(2*MAX(R'high,I'high)+1 downto 2*MIN(R'low,I'low)) result + function TO_COMPLEX(C:CFIXED) return COMPLEX; -- returns COMPLEX result + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR; -- returns CFIXED_VECTOR(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR; -- returns COMPLEX_VECTOR result + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR; -- returns R*C + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED; -- returns element K out of an N-size array X + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a variable, set element K out of an N-size array X to C + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a signal, set element K out of an N-size array X to C + + function LOG2(N:INTEGER) return INTEGER; -- returns ceil(log2(N)) +end COMPLEX_FIXED_PKG; + +package body COMPLEX_FIXED_PKG is +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED is -- returns the CFIXED range for X(K) +-- variable O:CFIXED(X'length/N*(K+1)-1+X'low/N downto X'length/N*K+X'low/N); +-- begin +-- return O; +-- end; + +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).RE +-- begin +-- return RE(ELEMENT(X,K,N)); +-- end; + +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).IM +-- begin +-- return IM(ELEMENT(X,K,N)); +-- end; + + function MIN(A,B:INTEGER) return INTEGER is + begin + if AB then + return A; + else + return B; + end if; + end; + + function MAX(A,B,C:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),C); + end; + + function MAX(A,B,C,D:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),MAX(C,D)); + end; + + function "+"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX+SY; -- SIGNED addition + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX-SY; -- SIGNED subtraction + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SR:SIGNED(X'high-X'low+1 downto 0); + variable R:SFIXED(X'high+1 downto X'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + SR:=-RESIZE(SX,SR'length); -- SIGNED negation + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X,Y:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SY:SIGNED(Y'high-Y'low downto 0); + variable SR:SIGNED(SX'high+SY'high+1 downto 0); + variable R:SFIXED(X'high+Y'high+1 downto X'low+Y'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + for K in SY'range loop + SY(K):=Y(Y'low+K); + end loop; + SR:=SX*SY; -- SIGNED multiplication + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED is + begin + if Y='1' then + return X; + else + return TO_SFIXED(0.0,X); + end if; + end; + + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED is + variable R:SFIXED(H downto L); + begin + for K in R'range loop + if KX'high then + R(K):=X(X'high); -- sign extend X MSBs + else + R(K):=X(K); + end if; + end loop; + return R; + end; + + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED is + begin + return RESIZE(X,HL'high,HL'low); + end; + + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high-N downto X'low-N); + begin + for K in R'range loop + R(K):=X(K+N); + end loop; + return R; + end; + + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high+N downto X'low+N); + begin + for K in R'range loop + R(K):=X(K-N); + end loop; + return R; + end; + + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED is + variable RR:REAL; + variable V:SFIXED(H downto L); + begin + assert (R<2.0**H) and (R>=-2.0**H) report "TO_SFIXED vector truncation!" severity warning; + if R<0.0 then + V(V'high):='1'; + RR:=R+2.0**V'high; + else + V(V'high):='0'; + RR:=R; + end if; + for K in V'high-1 downto V'low loop + if RR>=2.0**K then + V(K):='1'; + RR:=RR-2.0**K; + else + V(K):='0'; + end if; + end loop; + return V; + end; + + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED is + begin + return TO_SFIXED(R,HL'high,HL'low); + end; + + function TO_REAL(S:SFIXED) return REAL is + variable R:REAL; + begin + R:=0.0; + for K in S'range loop + if K=S'high then + if S(K)='1' then + R:=R-2.0**K; + end if; + else + if S(K)='1' then + R:=R+2.0**K; + end if; + end if; + end loop; + return R; + end; + +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED is -- X'low and X'length are always multiples of N +-- variable R:SFIXED(X'length/N-1+X'low/N downto X'low/N); +-- begin +-- R:=SFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); +-- return R; -- element K out of N of X +-- end; + + function RE(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(R'length-1+X'low downto X'low)); + return R; --lower half of X + end; + +-- procedure vRE(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low):=CFIXED(S); -- set lower half of X +-- end; + +-- procedure RE(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low)<=CFIXED(S); -- set lower half of X +-- end; + + function IM(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(X'high downto R'length+X'low)); + return R; --upper half of X + end; + +-- procedure vIM(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low):=CFIXED(S); -- set upper half of X +-- end; + +-- procedure IM(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low)<=CFIXED(S); -- set upper half of X +-- end; + + function "+"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+RE(Y),IM(X)+IM(Y)); + end; + + function "-"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-RE(Y),IM(X)-IM(Y)); + end; + + function "*"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*RE(Y)-IM(X)*IM(Y),RE(X)*IM(Y)+IM(X)*RE(Y)); + end; + + function "*"(X:CFIXED;Y:SFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*Y,IM(X)*Y); + end; + + function "*"(X:SFIXED;Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(X*RE(Y),X*IM(Y)); + end; + + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(RESIZE(RE(X),H,L),RESIZE(IM(X),H,L)); + end; + + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED is + begin + return RESIZE(X,HL'high/2,HL'low/2); + end; + + function PLUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-IM(X),RE(X)); + end; + + function "-"(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-RE(X),-IM(X)); + end; + + function MINUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),-RE(X)); + end; + + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-IM(Y)+RE(RND),IM(X)+RE(Y)+IM(RND)); + end; + + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+IM(Y)+RE(RND),IM(X)-RE(Y)+IM(RND)); + end; + + function SWAP(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),RE(X)); + end; + + function CONJ(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X),-IM(X)); + end; + + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_RIGHT(RE(X),N),SHIFT_RIGHT(IM(X),N)); + end; + + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_LEFT(RE(X),N),SHIFT_LEFT(IM(X),N)); + end; + + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(TO_SFIXED(R,H,L),TO_SFIXED(I,H,L)); + end; + + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(R,I,HL'high/2,HL'low/2); + end; + + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(C.RE,C.IM,HL); + end; + + function TO_CFIXED(R,I:SFIXED) return CFIXED is + constant H:INTEGER:=MAX(R'high,I'high); + constant L:INTEGER:=MIN(R'low,I'low); + variable C:CFIXED(2*H+1 downto 2*L); + begin + C:=CFIXED(RESIZE(I,H,L))&CFIXED(RESIZE(R,H,L)); + return C; -- I&R + end; + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED is -- X'low and X'length are always multiples of N + variable R:CFIXED(X'length/N-1+X'low/N downto X'low/N); + begin + R:=CFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); + return R; -- element K out of N of X + end; + + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low):=CFIXED_VECTOR(C); -- element K out of N of X + end; + + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low)<=CFIXED_VECTOR(C); -- element K out of N of X + end; + + function TO_COMPLEX(C:CFIXED) return COMPLEX is + variable R:COMPLEX; + begin + R.RE:=TO_REAL(RE(C)); + R.IM:=TO_REAL(IM(C)); + return R; + end; + + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR is + variable R:CFIXED_VECTOR(C'length*(HL'high+1)-1 downto C'length*HL'low); + begin + for K in C'range loop + R((K-C'low+1)*HL'length-1+R'low downto (K-C'low)*HL'length+R'low):=CFIXED_VECTOR(TO_CFIXED(C(K),HL)); + end loop; + return R; + end; + + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR is + variable R:COMPLEX_VECTOR(0 to N-1); + begin + for K in 0 to N-1 loop + R(K):=TO_COMPLEX(ELEMENT(C,K,N)); + end loop; + return R; + end; + + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR is + variable X:COMPLEX_VECTOR(C'range); + begin + for K in C'range loop + X(K):=R*C(K); + end loop; + return X; + end; + + function LOG2(N:INTEGER) return INTEGER is + variable TEMP:INTEGER; + variable RESULT:INTEGER; + begin + TEMP:=N; + RESULT:=0; + while TEMP>1 loop + RESULT:=RESULT+1; + TEMP:=(TEMP+1)/2; + end loop; + return RESULT; + end; +end COMPLEX_FIXED_PKG; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic BOOLEAN Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); +end BDELAY; + +architecture TEST of BDELAY is + attribute rloc:STRING; + + component BDELAY + generic(SIZE:INTEGER:=1); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); + end component; + +begin + l0:if SIZE=0 generate + begin + O<=I; + end generate l0; + -- end; + + l1:if SIZE=1 generate + signal iO:BOOLEAN:=FALSE; + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; + end generate l1; + -- end; + + l17: if SIZE>=2 and SIZE<18 generate + signal A:UNSIGNED(3 downto 0); + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + D<='1' when I else '0'; + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>D, + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l17; + -- end; + + l33: if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + D<='1' when I else '0'; + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>D, + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l33; + -- end; + + l257: if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.BDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + -- end; + end generate l257; + + ln: if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + type TUV is array(0 to SIZE-3) of UNSIGNED(0 downto 0); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(0 downto 0):=(others=>(others=>'0')); + signal MEM:TUV:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(0 downto 0):=(others=>'0'); + signal D,Q:UNSIGNED(0 downto 0); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + D<="1" when I else "0"; + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=D; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO="1"; + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: UDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: UDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic UNSIGNED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity UDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in UNSIGNED; + O:out UNSIGNED); +end UDELAY; + +architecture TEST of UDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin + assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=I; +-- end; + end generate; +-- elsif l1: SIZE=1 generate + l1:if SIZE=1 generate + signal iO:UNSIGNED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; +-- end; + end generate; +-- elsif l17: SIZE>=2 and SIZE<18 generate + l17:if SIZE>=2 and SIZE<18 generate + lk:for K in 0 to O'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l33: SIZE>=18 and SIZE<34 generate + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l257: SIZE>=34 and SIZE=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.UDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); +-- end; + end generate; +-- elsif ln: SIZE>=BRAM_THRESHOLD generate + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of UNSIGNED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO; + end if; + end process; +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic SFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity SDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in SFIXED; + O:out SFIXED); +end SDELAY; + +architecture TEST of SDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin +-- assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=RESIZE(I,O'high,O'low); + end generate l0; + --end; + + l1:if SIZE=1 generate + signal iO:SFIXED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=RESIZE(I,iO); + end if; + end process; + O<=iO; + end generate l1; + --end; + + l17:if SIZE>=2 and SIZE<18 generate +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); + begin + lk:for K in 0 to I'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l17; + --end; + + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- iO<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l33; + --end; + + l257:if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.SDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + --end; + end generate l257; + + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:SFIXED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of SFIXED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:SFIXED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=RESIZE(iO,O'high,O'low); + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic CFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CDELAY; + +architecture TEST of CDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; + signal IRE,IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); +begin + IRE<=RE(I); + IIM<=IM(I); + dr:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.RE); + I=>IRE, + O=>ORE); + di:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.IM); + I=>IIM, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CB.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CB +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Matrix Transposer (Corner Bender) Module Stage +-- It does an RxR matrix transposition where R=I'length +-- and each matrix element is a group of PACKING_FACTOR consecutive samples +-- LATENCY=(I'length-1)*PACKING_FACTOR+1 when I'length>1 or 0 when I'length=1 +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CB is + generic(SSR:INTEGER:=4; --93 + F:INTEGER:=0; + PACKING_FACTOR:INTEGER:=1; + INPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + OUTPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + SHORTEN_VO_BY:INTEGER:=0; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CB; + +architecture TEST of CB is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(LOG2(SSR)-1 downto 0); --93 local constrained UNSIGNED_VECTOR type + type iCFIXED_VECTOR is array(NATURAL range <>) of CFIXED((I'high+1)/SSR-1 downto I'low/SSR); --93 local constrained CFIXED_VECTOR type + + signal CNTP:UNSIGNED(LOG2(PACKING_FACTOR) downto 0):=(others=>'0'); + signal CNT:UNSIGNED(LOG2(SSR)-1 downto 0):=(others=>'0'); +--2008 signal A:UNSIGNED_VECTOR(0 to I'length):=(others=>(others=>'0')); +--2008 signal EN:BOOLEAN_VECTOR(0 to I'length):=(others=>FALSE); +--2008 signal DI:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal DO:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(0 to I'length-1=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).IM'range=>'0'))); + signal A:UNSIGNED_VECTOR(0 to SSR):=(others=>(others=>'0')); + signal EN:BOOLEAN_VECTOR(0 to SSR):=(others=>FALSE); + signal II,DI,OO:iCFIXED_VECTOR(0 to SSR-1); + signal DO:iCFIXED_VECTOR(0 to SSR-1):=(others=>(others=>'0')); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity error; + + f0:if F=0 generate + begin +--2008 i0:if I'length=1 generate + i0:if SSR=1 generate + O<=I; + VO<=VI; + SO<=SI; + end generate; +--2008 else generate +--2008 i1:if I'length>1 generate + i1:if SSR>1 generate + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if CNTP=PACKING_FACTOR-1 then + CNTP<=(others=>'0'); + CNT<=CNT+1; + else + CNTP<=CNTP+1; + end if; + else + CNTP<=(others=>'0'); + CNT<=(others=>'0'); + end if; + end if; + end process; + + A(0)<=CNT; + EN(0)<=CNTP=PACKING_FACTOR-1; +--2008 lk:for K in 0 to I'length-1 generate + lk:for K in 0 to SSR-1 generate + begin + II(K)<=CFIXED(I(I'length/SSR*(K+1)-1+I'low downto I'length/SSR*K+I'low)); --93 + i1:entity work.CDELAY generic map(SIZE=>K*(PACKING_FACTOR+INPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II(K), --93 I(I'low+K), + O=>DI(K)); + process(CLK) + begin + if rising_edge(CLK) then + DO(K)<=DI(TO_INTEGER(A(K))); + if EN(K) then + A(K+1)<=A(K); + end if; + end if; + end process; + bd:entity work.BDELAY generic map(SIZE=>PACKING_FACTOR) + port map(CLK=>CLK, + I=>EN(K), + O=>EN(K+1)); + o1:entity work.CDELAY generic map(SIZE=>(SSR-1-K)*(PACKING_FACTOR+OUTPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DO(K), + O=>OO(K)); --93 O(O'low+K)); + O(O'length/SSR*(K+1)-1+O'low downto O'length/SSR*K+O'low)<=CFIXED_VECTOR(OO(K)); --93 + end generate; + + bd:entity work.BDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY) + port map(CLK=>CLK, + I=>VI, + O=>VO); + + ud:entity work.UDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +-- end; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=SSR/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.CB generic map(SSR=>G, + F=>0, + PACKING_FACTOR=>PACKING_FACTOR, + INPUT_PACKING_FACTOR_ADJUST=>INPUT_PACKING_FACTOR_ADJUST, + OUTPUT_PACKING_FACTOR_ADJUST=>OUTPUT_PACKING_FACTOR_ADJUST, + SHORTEN_VO_BY=>SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Real Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BFS is + generic(PIPELINE:BOOLEAN:=TRUE; + SUB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SCALE:in STD_LOGIC; +-- P:out SIGNED); -- O=A±B + P:out SFIXED; -- O=A±B + OVR:out STD_LOGIC); +end BFS; + +architecture FAST of BFS is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH+1 downto SM-1); +-- signal S:SIGNED(SH+1 downto SL); + signal SA,SB:SFIXED(SH+1 downto SM-1); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM+1 downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1)/8*8+8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1)/8*8+7 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH+1 generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (((I0 and not I4) or (I2 and I4)) xor ((I1 and not I4) or (I3 and I4)))) or (not I5 and ((I1 and not I4) or (I3 and I4)))) + port map(I0=>SB(K-1),I1=>SA(K-1),I2=>SB(K),I3=>SA(K),I4=>SCALE,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM+1)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM+1); + end generate; + S(SH+1)<=O(O'high); + + ia:if A'low'0'); + signal iOVR:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + iOVR<=S(S'high) xor S(S'high-1); + end if; + end process; + P<=iP; + OVR<=iOVR; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CBFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CBFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Complex Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CBFS is -- O0=I0+I1, O1=I0-I1 + generic(ROUNDING:BOOLEAN:=TRUE; + PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC; + I0,I1:in CFIXED; + SCALE:in STD_LOGIC; + O0,O1:out CFIXED; + OVR:out STD_LOGIC); +end CBFS; + +architecture TEST of CBFS is + signal I0RE,I0IM,I1RE,I1IM:SFIXED(I0'high/2 downto I0'low/2); + signal O0RE,O0IM,O1RE,O1IM:SFIXED(O0'high/2 downto O0'low/2); + signal OVR4:STD_LOGIC_VECTOR(3 downto 0); +begin + I0RE<=RE(I0); + I0IM<=IM(I0); + I1RE<=RE(I1); + I1IM<=IM(I1); + + u0:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0RE=I0RE+I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O0RE, + OVR=>OVR4(0)); + + u1:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0IM=I0IM+I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O0IM, + OVR=>OVR4(1)); + + u2:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1RE=I0RE-I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O1RE, + OVR=>OVR4(2)); + + u3:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1IM=I0IM-I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O1IM, + OVR=>OVR4(3)); + + O0<=TO_CFIXED(O0RE,O0IM); + O1<=TO_CFIXED(O1RE,O1IM); + OVR<=OVR4(0) or OVR4(1) or OVR4(2) or OVR4(3); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CSA3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CSA3 +-- Purpose: Generic 3-input Add/Sub Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Carry Save 3-input Adder/Subtracter +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CSA3 is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + NEGATIVE_A:BOOLEAN:=FALSE; + NEGATIVE_B:BOOLEAN:=FALSE; + EXTRA_MSBs:INTEGER:=2); + port(CLK:in STD_LOGIC:='0'; +-- A,B,C:in SIGNED; -- if SIGNED, A, B, C and P must be LSB aligned + A,B,C:in SFIXED; -- if SFIXED, A, B, C and P can be any size + CY1,CY2:in BOOLEAN:=FALSE; -- the number of CYs TRUE must equal the number of negative A and B terms +-- P:out SIGNED); -- O=C±A±B + P:out SFIXED); -- O=C±A±B +end CSA3; + +architecture FAST of CSA3 is + constant SH:INTEGER:=MAX(A'high,B'high,C'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MED(A'low,B'low,C'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low,C'low); +-- signal SA,SB,SC,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB,SC:SFIXED(SH downto SM); + signal S:SFIXED(SH downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + SC<=RESIZE(C,SC); + O5(0)<='1' when CY1 else '0'; + CY(0)<='1' when CY2 else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_B))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_A))); + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (I1 xor I2 xor I3 xor I4)) or (not I5 and ((I2 and I3) or (I3 and I1) or (I1 and I2)))) + port map(I0=>'0',I1=>SC(K),I2=>SB(K),I3=>SA(K),I4=>O5(K-SM),I5=>'1',O5=>O5(K+1-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM); + end generate; + + ia:if (A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +--***************************************************************************** +-- © Copyright 2008 - 2018 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +--***************************************************************************** +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : v1.2 +-- \ \ Application : DSP48E2 generic wrapper +-- / / Filename : DSP48E2GW.vhd +-- /___/ /\ Date Last Modified : Oct 11 2017 +-- \ \ / \ Date Created : Nov 14 2014 +-- \___\/\___\ +-- +--Device : UltraScale and UltraScale+ +--Design Name : DSP48E2GW +--Purpose : DSP48E2 Generic Wrapper makes DSP48E2 primitive instantiation easier +--Reference : +--Revision History : v1.0 - original version +--Revision History : v1.1 - smart SFIXED resizing +--Revision History : v1.2 - fix for output resizing +--***************************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +--use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity DSP48E2GW is + generic(X,Y:INTEGER:=-1; + DSP48E:INTEGER:=2; -- use 1 for DSP48E1 and 2 for DSP48E2 + -- Feature Control Attributes: Data Path Selection + AMULTSEL:STRING:="A"; -- Selects A input to multiplier (A, AD) + A_INPUT:STRING:="DIRECT"; -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL:STRING:="B"; -- Selects B input to multiplier (AD, B) + B_INPUT:STRING:="DIRECT"; -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL:STRING:="A"; -- Selects input to preadder (A, B) + RND:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- Rounding Constant + USE_MULT:STRING:="MULTIPLY"; -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD:STRING:="ONE48"; -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR:STRING:="FALSE"; -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD:STRING:="XOR24_48_96"; -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET:STRING:="NO_RESET"; -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY:STRING:="RESET"; -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK:STD_LOGIC_VECTOR(47 downto 0):=X"3fffffffffff"; -- 48-bit mask value for pattern detect (1=ignore) + PATTERN:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- 48-bit pattern match for pattern detect + SEL_MASK:STRING:="MASK"; -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN:STRING:="PATTERN"; -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT:STRING:="NO_PATDET"; -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED:STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED:BIT:='0'; -- Optional inversion for CARRYIN + IS_CLK_INVERTED:BIT:='0'; -- Optional inversion for CLK + IS_INMODE_INVERTED:STD_LOGIC_VECTOR(4 downto 0):="00000"; -- Optional inversion for INMODE + IS_OPMODE_INVERTED:STD_LOGIC_VECTOR(8 downto 0):="000000000"; -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED:BIT:='0'; -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED:BIT:='0'; -- Optional inversion for RSTA + IS_RSTB_INVERTED:BIT:='0'; -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED:BIT:='0'; -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED:BIT:='0'; -- Optional inversion for RSTC + IS_RSTD_INVERTED:BIT:='0'; -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED:BIT:='0'; -- Optional inversion for RSTM + IS_RSTP_INVERTED:BIT:='0'; -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG:INTEGER:=1; -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG:INTEGER:=1; -- Pipeline stages for pre-adder (0-1) + ALUMODEREG:INTEGER:=1; -- Pipeline stages for ALUMODE (0-1) + AREG:INTEGER:=1; -- Pipeline stages for A (0-2) + BCASCREG:INTEGER:=1; -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG:INTEGER:=1; -- Pipeline stages for B (0-2) + CARRYINREG:INTEGER:=1; -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG:INTEGER:=1; -- Pipeline stages for CARRYINSEL (0-1) + CREG:INTEGER:=1; -- Pipeline stages for C (0-1) + DREG:INTEGER:=1; -- Pipeline stages for D (0-1) + INMODEREG:INTEGER:=1; -- Pipeline stages for INMODE (0-1) + MREG:INTEGER:=1; -- Multiplier pipeline stages (0-1) + OPMODEREG:INTEGER:=1; -- Pipeline stages for OPMODE (0-1) + PREG:INTEGER:=1); -- Number of pipeline stages for P (0-1) + port(-- Cascade inputs: Cascade Ports + ACIN:in STD_LOGIC_VECTOR(29 downto 0):=(others=>'0'); -- 30-bit input: A cascade data + BCIN:in STD_LOGIC_VECTOR(17 downto 0):=(others=>'0'); -- 18-bit input: B cascade + CARRYCASCIN:in STD_LOGIC:='0'; -- 1-bit input: Cascade carry + MULTSIGNIN:in STD_LOGIC:='0'; -- 1-bit input: Multiplier sign cascade + PCIN:in STD_LOGIC_VECTOR(47 downto 0):=(others=>'0'); -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE:in STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- 4-bit input: ALU control + CARRYINSEL:in STD_LOGIC_VECTOR(2 downto 0):="000"; -- 3-bit input: Carry select + CLK:in STD_LOGIC:='0'; -- 1-bit input: Clock + INMODE:in STD_LOGIC_VECTOR(4 downto 0):="00000"; -- 5-bit input: INMODE control + OPMODE:in STD_LOGIC_VECTOR(8 downto 0):="000110101"; -- 9-bit input: Operation mode - default is P<=C+A*B + -- Data inputs: Data Ports + A:in SFIXED;--(Ahi downto Alo):=(others=>'0'); -- 30-bit input: A data + B:in SFIXED;--(Bhi downto Blo):=(others=>'0'); -- 18-bit input: B data + C:in SFIXED;--(Chi downto Clo):=(others=>'0'); -- 48-bit input: C data + CARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Carry-in + D:in SFIXED;--(Dhi downto Dlo):=(others=>'0'); -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage AREG + CEA2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage AREG + CEAD:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ADREG + CEALUMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ALUMODE + CEB1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage BREG + CEB2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage BREG + CEC:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CREG + CECARRYIN:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CARRYINREG + CECTRL:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for DREG + CEINMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for INMODEREG + CEM:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for MREG + CEP:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for PREG + RSTA:in STD_LOGIC:='0'; -- 1-bit input: Reset for AREG + RSTALLCARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Reset for CARRYINREG + RSTALUMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for ALUMODEREG + RSTB:in STD_LOGIC:='0'; -- 1-bit input: Reset for BREG + RSTC:in STD_LOGIC:='0'; -- 1-bit input: Reset for CREG + RSTCTRL:in STD_LOGIC:='0'; -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD:in STD_LOGIC:='0'; -- 1-bit input: Reset for DREG and ADREG + RSTINMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for INMODEREG + RSTM:in STD_LOGIC:='0'; -- 1-bit input: Reset for MREG + RSTP:in STD_LOGIC:='0'; -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT:out STD_LOGIC_VECTOR(29 downto 0); -- 30-bit output: A port cascade + BCOUT:out STD_LOGIC_VECTOR(17 downto 0); -- 18-bit output: B cascade + CARRYCASCOUT:out STD_LOGIC; -- 1-bit output: Cascade carry + MULTSIGNOUT:out STD_LOGIC; -- 1-bit output: Multiplier sign cascade + PCOUT:out STD_LOGIC_VECTOR(47 downto 0); -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW:out STD_LOGIC; -- 1-bit output: Overflow in add/acc + PATTERNBDETECT:out STD_LOGIC; -- 1-bit output: Pattern bar detect + PATTERNDETECT:out STD_LOGIC; -- 1-bit output: Pattern detect + UNDERFLOW:out STD_LOGIC; -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT:out STD_LOGIC_VECTOR(3 downto 0); -- 4-bit output: Carry + P:out SFIXED;--(Phi downto Plo); -- 48-bit output: Primary data + XOROUT:out STD_LOGIC_VECTOR(7 downto 0)); -- 8-bit output: XOR data +end entity; + +architecture WRAPPER of DSP48E2GW is + signal slvA:STD_LOGIC_VECTOR(29 downto 0); + signal slvB:STD_LOGIC_VECTOR(17 downto 0); + signal slvD:STD_LOGIC_VECTOR(26 downto 0); + signal slvC,slvP:STD_LOGIC_VECTOR(47 downto 0); +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if K=0) and (Y>=0) generate + begin + i1:if DSP48E=1 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; +-- else generate + i2:if (X<0) or (Y<0) generate + begin + i1:if DSP48E=1 generate + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; + P<=SLV_TO_SFIXED_RESIZE(slvP,P'high,P'low,A'low+B'low-P'low); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CKCM.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CKCM +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Constant Coeficient Complex Multiplier +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CKCM is -- LATENCY=3 + generic(M:INTEGER:=1; -- must be 0, 1, 2 or 3 to multiply I by (1.0,0.0), (Sqrt(0.5),-Sqrt(0.5)), (0.0,-1.0), (-Sqrt(0.5),-Sqrt(0.5)) + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + ROUNDING:BOOLEAN:=FALSE; -- set to TRUE to round the result + CONJUGATE:BOOLEAN:=FALSE); -- set to TRUE for IFFT + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CKCM; + +architecture TEST of CKCM is + attribute use_dsp48:STRING; + attribute use_dsp48 of TEST:architecture is "no"; +--2008 signal RND:SFIXED(O.RE'high downto O.RE'low-1); + signal RND:SFIXED((O'high+1)/2-1 downto O'low/2-1); + constant nCONJUGATE:BOOLEAN:=not CONJUGATE; +begin + i0:if M=0 generate + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>I, + O=>O); + end generate; +--elsif i1: M=2 generate + i1:if M=2 generate + ic:if CONJUGATE generate +--2008 signal NIIM1D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal NIIM1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IRE:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIIM1D<=RESIZE(-I.IM,I.IM); + NIIM1D<=RESIZE(-IM(I),NIIM1D); + end if; + end process; + r2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIIM1D, +--2008 O=>O.RE); + O=>ORE); + IRE<=RE(I); + i3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.IM); + I=>IRE, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + ---else generate + nc:if not CONJUGATE generate +--2008 signal NIRE1D:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal NIRE1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + IIM<=IM(I); + r3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.RE); + I=>IIM, + O=>ORE); + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIRE1D<=RESIZE(-I.RE,I.RE); + NIRE1D<=RESIZE(-RE(I),RE(I)); + end if; + end process; + i2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIRE1D, +--2008 O=>O.IM); + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + end generate; +-- else generate -- M=1 or 3 + i2:if (M=1) or (M=3) generate -- M=1 or 3 + constant K:SFIXED(0 downto -18):="0101101010000010100"; -- SQRT(0.5) + +--2008 signal X1,Y1:SFIXED(I.RE'high downto I.RE'low-14); +--2008 signal X2,Y2:SFIXED(I.RE'range); +--2008 signal KIRE,KIIM:SFIXED(I.RE'range); + + + + signal X1,Y1:SFIXED((I'high+1)/2-1 downto I'low/2-14); + signal X2,Y2:SFIXED((I'high+1)/2-1 downto I'low/2):=(others=>'0'); + signal KIRE,KIIM:SFIXED((I'high+1)/2-1 downto I'low/2); +--2008 signal I_1:CFIXED(RE(I.RE'high-1 downto I.RE'low-1),IM(I.IM'high-1 downto I.IM'low-1)); +--2008 signal I_6:CFIXED(RE(I.RE'high-6 downto I.RE'low-6),IM(I.IM'high-6 downto I.IM'low-6)); +--2008 signal I_14:CFIXED(RE(I.RE'high-14 downto I.RE'low-14),IM(I.IM'high-14 downto I.IM'low-14)); + signal I_1:CFIXED(I'high-2*1 downto I'low-2*1); + signal I_6:CFIXED(I'high-2*6 downto I'low-2*6); + signal I_14:CFIXED(I'high-2*14 downto I'low-2*14); + signal I_1RE,I_1IM:SFIXED((I_1'high+1)/2-1 downto I_1'low/2); + signal I_6RE,I_6IM:SFIXED((I_6'high+1)/2-1 downto I_6'low/2); + signal I_14RE,I_14IM:SFIXED((I_14'high+1)/2-1 downto I_14'low/2); + signal X1_2:SFIXED(X1'high-2 downto X1'low-2); + signal X2_4:SFIXED(X2'high-4 downto X2'low-4); + signal Y1_2:SFIXED(Y1'high-2 downto Y1'low-2); + signal Y2_4:SFIXED(Y2'high-4 downto Y2'low-4); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + constant MEQ3:BOOLEAN:=M=3; + begin +--2008 RND<=TO_SFIXED(2.0**(O.RE'low-1),RND) when ROUNDING else (others=>'0'); + RND<=TO_SFIXED(2.0**(O'low/2-1),RND) when ROUNDING else (others=>'0'); + process(CLK) + begin + if rising_edge(CLK) then +--2008 X2<=I.RE; +--2008 Y2<=I.IM; + X2<=RE(I); + Y2<=IM(I); + end if; + end process; + + I_1<=SHIFT_RIGHT(I,1); + I_6<=SHIFT_RIGHT(I,6); + I_14<=SHIFT_RIGHT(I,14); + X1_2<=SHIFT_RIGHT(X1,2); + X2_4<=SHIFT_RIGHT(X2,4); + Y1_2<=SHIFT_RIGHT(Y1,2); + Y2_4<=SHIFT_RIGHT(Y2,4); + I_1RE<=RE(I_1); + I_6RE<=RE(I_6); + I_14RE<=RE(I_14); + + a1:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.RE, +--2008 B=>I_6.RE, +--2008 C=>I_14.RE, + A=>I_1RE, + B=>I_6RE, + C=>I_14RE, + P=>X1); -- P=C+A+B + + a2:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>X1, + B=>X1_2, + C=>X2_4, + P=>KIRE); -- P=C+A+B + + I_1IM<=IM(I_1); + I_6IM<=IM(I_6); + I_14IM<=IM(I_14); + a3:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.IM, +--2008 B=>I_6.IM, +--2008 C=>I_14.IM, + A=>I_1IM, + B=>I_6IM, + C=>I_14IM, + P=>Y1); -- P=C+A+B + + a4:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>Y1, + B=>Y1_2, + C=>Y2_4, + P=>KIIM); -- P=C+A+B + + a5:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>MEQ3, --2008 M=3, + NEGATIVE_B=>CONJUGATE, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>MEQ3, --2008 M=3, + CY2=>CONJUGATE, +--2008 P=>O.RE); -- P=C+A+B + P=>ORE); -- P=C+A+B + + a6:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>nCONJUGATE, + NEGATIVE_B=>MEQ3, --2008 M=3, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>nCONJUGATE, + CY2=>MEQ3, --2008 M=3, +--2008 P=>O.IM); -- P=C+A+B + P=>OIM); -- P=C+A+B + O<=TO_CFIXED(ORE,OIM); + --end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: ADDSUB.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity ADDSUB is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SUB:in BOOLEAN:=FALSE; +-- P:out SIGNED); -- O=A±B + P:out SFIXED); -- O=A±B +end ADDSUB; + +architecture FAST of ADDSUB is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB:SFIXED(SH downto SM); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0"; + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + signal I_4:STD_LOGIC; + begin + I_4<='1' when SUB else '0'; + l6:LUT6_2 generic map(INIT=>(I5 and (I2 xor I3 xor I4)) or (not I5 and ((I2 xor I4) and I3))) + port map(I0=>'0',I1=>'0',I2=>SB(K),I3=>SA(K),I4=>I_4,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + +-- ll:for L in SM to SH+1 generate + ll:for L in SM to SH generate +-- S(L)<=O(L-SM+1); + S(L)<=O(L-SM); + end generate; + S(SH+1)<=S(SH); + + ia:if A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: TABLE.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: TABLE +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, SinCos Table Module +-- +-- Latency is always 2 +-- when INV_FFT=FALSE W=exp(-2.0*PI*i*JK/N) and when INV_FFT=TRUE W=exp(2.0*PI*i*JK/N) +-- to maximize W output bit size utilization W.RE and W.IM are always negative (MSB='1') and that bit could be ignored, this is why W.RE'length can be 19 bits but a single BRAM would still be used +-- when W.RE or W.IM need to be positive CS respectively SS are TRUE, same thing when they are 0.0 CZ respectively SZ are TRUE - the complex multiplier has to use CS, SS, CZ and SZ, not just W to produce the correct result +-- the SIN and COS ROM table sizes are N/4 deep and W.RE'length-1 wide (it is implictly assumed that W.RE and W.IM always have the same range) +-- if STYLE="block" a single dual port BRAM is used for both tables +-- if STYLE="distributed" then two fabric LUT based ROMs are used +-- as a general rule for N<2048 "distributed" should be used, otherwise "block" makes more sense but this is not a hard rule +-- W range is unconstrained but W.RE'high and W.IM'high really have to be 0 all the time, do not use other values +-- the maximum SNR without using extra BRAMs is achieved when W.RE'low and W.IM'low are -18 so W.RE'length and W.IM'length are 19 bits but they can be less than that - this would reduce SNR and save resources only when STYLE="distributed" +-- TABLE.VHD also works with more than 19 bits but the current complex multiplier implementation does not support that - this would essentially double the number of BRAMs and DSP48s used and seems too high a price to pay for a few extra dB of SNR +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use IEEE.MATH_REAL.all; + +use work.COMPLEX_FIXED_PKG.all; + +--!! entity TABLE is -- LATENCY=3 (2 if SEPARATE_SIGN is TRUE) +entity TABLE is -- LATENCY=4 (3 if SEPARATE_SIGN is TRUE) when SPLIT_RADIX=0 else LATENCY=0 + generic(N:INTEGER:=1024; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and J*1 or J*3 with J>0 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + SEPARATE_SIGN:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + STYLE:STRING:="block"); -- use only "block" or "distributed" + port(CLK:in STD_LOGIC; + JK:in UNSIGNED; + VI:in BOOLEAN; + W:out CFIXED; + CS,SS,CZ,SZ:out BOOLEAN; + VO:out BOOLEAN); +end TABLE; + +architecture TEST of TABLE is +--2008 constant WH:INTEGER:=W.RE'high-1+BOOLEAN'pos(SEPARATE_SIGN); +--2008 constant WL:INTEGER:=W.RE'low; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 + constant WH:INTEGER:=(W'high+1)/2-1-1+BOOLEAN'pos(SEPARATE_SIGN); + constant WL:INTEGER:=W'low/2; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 +begin + i0:if SPLIT_RADIX=0 generate + type wSFIXED_VECTOR is array(INTEGER range <>) of SFIXED(WH-1 downto WL); -- local constrained array of SFIXED type +--2008 function LUT_VALUE(N,WH,WL:INTEGER) return SFIXED_VECTOR is +--2008 variable RESULT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL); + function LUT_VALUE(N,WH,WL:INTEGER) return wSFIXED_VECTOR is + variable RESULT:wSFIXED_VECTOR(0 to N/4-1); + begin + RESULT(0):=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + for J in 1 to N/4-1 loop + RESULT(J):=TO_SFIXED(-COS(-2.0*MATH_PI*REAL(J)/REAL(N))+2.0**(WL-1),WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + if RESULT(J)=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL) then + RESULT(J):=TO_SFIXED(-1.0+2.0**WL,WH,WL)(WH-1 downto WL); + end if; + end loop; + return RESULT; + end; + + signal JKD:UNSIGNED(JK'range):=(others=>'0'); + signal KC,KS:UNSIGNED(JK'range):=(others=>'0');--!! + signal DC,C,DS,S:SFIXED(WH-1 downto WL):=(others=>'0'); +--2008 signal LUT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL):=LUT_VALUE(N,WH,WL); + signal LUT:wSFIXED_VECTOR(0 to N/4-1):=LUT_VALUE(N,WH,WL); + attribute rom_style:STRING; + attribute rom_style of LUT:signal is STYLE; + signal RC,RS:BOOLEAN:=FALSE; + signal MC,MS:STD_LOGIC:='0'; + signal CS1,SS1,CS2,SS2:BOOLEAN:=FALSE; + signal W_RE,W_IM:SFIXED((W'high+1)/2-1 downto W'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--!! +--2008 KC<=JK when JK(JK'high-1)='0' else (not JK)+1; +--2008 KS<=(not JK)+1 when JK(JK'high-1)='0' else JK; + if JK(JK'high-1)='0' then + KC<=JK; + KS<=(not JK)+1; + else + KC<=(not JK)+1; + KS<=JK; + end if; + JKD<=JK; + if (JKD and TO_UNSIGNED(2**(JK'length-2)-1,JK'length))=0 then --mask first two MSBs of JK + RC<=JKD(JK'high-1)='1'; + RS<=JKD(JK'high-1)='0'; + else + RC<=FALSE; + RS<=FALSE; + end if; + DC<=LUT(TO_INTEGER(KC and TO_UNSIGNED(2**(KC'length-2)-1,KC'length))); + DS<=LUT(TO_INTEGER(KS and TO_UNSIGNED(2**(KS'length-2)-1,KS'length))); + if RC then + C<=(others=>'0'); + MC<='0'; + else + C<=DC; + MC<='1'; + end if; + if RS then + S<=(others=>'0'); + MS<='0'; + else + S<=DS; + MS<='1'; + end if; + CS1<=JKD(JK'high)=JKD(JK'high-1); + SS1<=(JKD(JK'high)='1') xor INV_FFT; + CS2<=CS1; + SS2<=SS1; + end if; + end process; + + i0:if SEPARATE_SIGN generate +--2008 W.RE<=MC&C; +--2008 W.IM<=MS&S; + W(W'length/2-1+W'low downto W'low)<=CFIXED(MC&C); + W(W'high downto W'length/2+W'low)<=CFIXED(MS&S); + CS<=CS2; + SS<=SS2; +-- else generate + end generate; + i1:if not SEPARATE_SIGN generate + signal WRE,WIM:SFIXED(WH downto WL):=(others=>'0'); + attribute keep:STRING; + attribute keep of WRE:signal is "yes"; + attribute keep of WIM:signal is "yes"; + signal ZERO:SFIXED(WH downto WL):=TO_SFIXED(0.0,WH,WL); + begin + WRE<=MC&C; + WIM<=MS&S; + + process(CLK) + begin + if rising_edge(CLK) then + CS<=CS2; + SS<=SS2; + CZ<=WRE(WRE'high)='0'; + SZ<=WIM(WIM'high)='0'; + end if; + end process; + ar:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WRE, + SUB=>CS2, +--2008 P=>W.RE); -- P=±B + P=>W_RE); -- P=±B + ai:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WIM, + SUB=>SS2, +--2008 P=>W.IM); -- P=±B + P=>W_IM); -- P=±B + W(W'length/2-1+W'low downto W'low)<=CFIXED(W_RE); + W(W'high downto W'length/2+W'low)<=CFIXED(W_IM); +-- end; + end generate; + +--!! b2:entity work.BDELAY generic map(SIZE=>3-BOOLEAN'pos(SEPARATE_SIGN)) + b2:entity work.BDELAY generic map(SIZE=>4-BOOLEAN'pos(SEPARATE_SIGN)) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- else generate + i1:if SPLIT_RADIX>0 generate + begin + i0:if SEPARATE_SIGN generate +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + end generate; +-- else generate + ii:if not SEPARATE_SIGN generate + begin +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + CZ<=(SPLIT_RADIX=N/4) or (SPLIT_RADIX=3*N/4); + SZ<=(SPLIT_RADIX=0) or (SPLIT_RADIX=N/2); +-- end; + end generate; + VO<=VI; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3 +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Complex Multiplier Using 3 DSP48E2s +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3 is -- LATENCY=6 + generic(ROUNDING:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED; -- I.RE'length and I.IM'length<27 + W:in CFIXED; -- W must be (1 downto -16) or (1 downto -17) + CS,SS,CZ,SZ:in BOOLEAN:=FALSE; + VI:in BOOLEAN; + O:out CFIXED; + VO:out BOOLEAN); +end CM3; + +architecture TEST of CM3 is + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute loc:STRING; + +--2008 constant HMAX:INTEGER:=MAX(I.RE'high,I.IM'high)+MAX(W.RE'high,W.IM'high)+3; +--2008 constant LMIN:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(I.RE'low,I.IM'low)+work.COMPLEX_FIXED_PKG.MIN(W.RE'low,W.IM'low); + constant HMAX:INTEGER:=(I'high+1)/2-1+(W'high+1)/2-1+3; + constant LMIN:INTEGER:=I'low/2+W'low/2; + +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,1) downto MAX(W.RE'low,-16)); +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,0) downto MAX(W.RE'low,-17)); +--2008 signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'low+17,1) downto W.RE'low); -- we only have 18 bits max to work with +--2008 signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); +--2008 signal IRE1D,IRE2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); +--2008 signal IIM1D,IIM2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W'low/2+17,1) downto W'low/2); -- we only have 18 bits max to work with + signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal IRE,IRE1D,IRE2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM,IIM1D,IIM2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal CS2D,SS2D:BOOLEAN; + signal C0S1:BOOLEAN:=FALSE; + signal P1,P2,P3:SFIXED(HMAX downto LMIN); + signal P2D:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal C1,C2,C3:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal AC1,AC2:STD_LOGIC_VECTOR(29 downto 0); + signal BC1:STD_LOGIC_VECTOR(17 downto 0); + signal PC1,PC2:STD_LOGIC_VECTOR(47 downto 0); +--2008 signal A_ZERO:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal A_ZERO:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal B_ZERO:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal C_ZERO:SFIXED(HMAX downto LMIN):=TO_SFIXED(0.0,HMAX,LMIN); + signal BR,BI:BOOLEAN; + signal iO:CFIXED(O'range); +begin +--!! +--2008 WRE<=RESIZE(W.RE,WRE); + WRE<=RESIZE(RE(W),WRE); +--!! WRE<=TO_SFIXED(1.0-2.0**WRE'low,WRE) when W.RE=TO_SFIXED(1.0,W.RE) else RESIZE(W.RE,WRE); +--!! +--2008 WIM<=RESIZE(W.IM,WIM); + WIM<=RESIZE(IM(W),WIM); + process(CLK) + begin + if rising_edge(CLK) then + WRE1D<=WRE; +--2008 IRE1D<=I.RE; +--2008 IIM1D<=I.IM; + IRE1D<=RE(I); + IIM1D<=IM(I); +--2008 C0S1<=CZ and (W.IM(W.IM'high)='0'); + C0S1<=CZ and (W(W'high)='0'); +--!! + NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! if WRE1D=TO_SFIXED(-1.0,WRE1D) then +--!! for K in NWRE2D'range loop +--!! NWRE2D(K)<=not WRE1D(K); +--!! end loop; +--!! else +--!! NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! end if; +--!! + IRE2D<=IRE1D; + IIM2D<=IIM1D; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and C0S1 then + if (W'low/2=-17) and C0S1 then + C1<=RESIZE(SHIFT_LEFT(IRE1D+IIM1D,1),C1); + else + C1<=TO_SFIXED(0.0,C1); + end if; + end if; + end process; + + IRE<=RE(I); + IIM<=IM(I); + dsp1:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"00101", -- (D+A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110000101", -- PCOUT=-C-(D+A1)*B2 +--2008 A=>I.RE, + A=>IRE, + B=>WIM, + C=>C1, +--2008 D=>I.IM, + D=>IIM, + ACOUT=>AC1, + BCOUT=>BC1, + P=>P1, + PCOUT=>PC1); + +-- C2<=TO_SFIXED(2.0**(O.RE'low-1),C2) when ROUNDING else TO_SFIXED(0.0,C2); + BR<=W(W'length/2-1+W'low)='0'; + BI<=W(W'high)='0'; + cd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.RE(W.RE'high)='0', + I=>BR, + O=>CS2D); + sd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.IM(W.IM'high)='0', + I=>BI, + O=>SS2D); + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and CS2D=SS2D then + if (W'low/2=-17) and CS2D=SS2D then + if CS2D then + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(I.RE,C2); + C2<=RESIZE(SHIFT_LEFT(IRE2D,1),C2); + end if; + else + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(-I.RE,C2); + C2<=RESIZE(-SHIFT_LEFT(IRE2D,1),C2); + end if; + end if; + else + if ROUNDING then +--2008 C2<=TO_SFIXED(2.0**(O.RE'low-1),C2); + C2<=TO_SFIXED(2.0**(O'low/2-1),C2); + else + C2<=TO_SFIXED(0.0,C2); + end if; + end if; + end if; + end process; + + dsp2:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL=>"AD", -- Selects B input to multiplier (AD, B) + B_INPUT=>"CASCADE", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL=>"B", -- Selects input to preadder (A, B) + AREG=>2) -- Pipeline stages for A (0-2) + port map(CLK=>CLK, + INMODE=>"10100", -- (D+B1)*A2 + ALUMODE=>"0000", -- Z+W+X+Y + OPMODE=>"110010101", -- PCOUT=PCIN+C+(D+B1)*A2 + A=>A_ZERO, + B=>B_ZERO, + C=>C2, + D=>WRE1D, + ACIN=>AC1, + BCIN=>BC1, + PCIN=>PC1, + ACOUT=>AC2, + P=>P2, + PCOUT=>PC2); + +-- C3<=RESIZE(SHIFT_RIGHT(P1,-16-W.RE'low),P1); + C3<=P1; + dsp3:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"01101", --5x"0C", -- (D-A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110010101", -- PCOUT=PCIN-C-(D-A1)*B2 + A=>A_ZERO, + B=>NWRE2D, + C=>C3, + D=>IIM2D, + ACIN=>AC2, + PCIN=>PC2, + P=>P3); + + process(CLK) + begin + if rising_edge(CLK) then +--2008 O.RE<=RESIZE(P2,O.RE); + P2D<=P2; + end if; + end process; +--2008 O.IM<=RESIZE(P3,O.IM); +-- O<=RESIZE(TO_CFIXED(P2D,P3),O); + O<=RESIZE(TO_CFIXED(P2D,P3),iO); + + bd:entity work.BDELAY generic map(SIZE=>6) + port map(CLK=>CLK, + I=>VI, + O=>VO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. 3 +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3FFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic Complex Multiplier Stage Module - uses 3 DSP48s/complex multiplication +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3FFT is -- LATENCY=10 + generic(N:INTEGER; + RADIX:INTEGER; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and 1 or 3 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CM3FFT; + +architecture TEST of CM3FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + function STYLE(N:INTEGER) return STRING is + begin + if N>BRAM_THRESHOLD then + return "block"; + else + return "distributed"; + end if; + end; + + function TABLE_LATENCY(SPLIT_RADIX:INTEGER) return INTEGER is + begin + if SPLIT_RADIX=0 then + return 4; + else + return 0; + end if; + end; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + signal CNT:UNSIGNED(L2N-L2R-1 downto 0):=(others=>'0'); + signal I0:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal O0:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + +--!! cd:entity work.CDELAY generic map(SIZE=>3+6) + I0<=ELEMENT(I,0,RADIX); + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, +--2008 I=>I(I'low), +--2008 O=>O(O'low)); + I=>I0, + O=>O0); + O(O'length/RADIX-1+O'low downto O'low)<=CFIXED_VECTOR(O0); + + process(CLK) + begin + if rising_edge(CLK) then + if not VI or (SPLIT_RADIX/=0) then + CNT<=(others=>'0'); + else + CNT<=CNT+1; + end if; + end if; + end process; + +--2008 lk:for J in 1 to I'length-1 generate + lk:for J in 1 to RADIX-1 generate + signal JK:UNSIGNED(L2N-1 downto 0):=(others=>'0'); +--2008 signal W:CFIXED(RE(W_high downto W_low),IM(W_high downto W_low)); + signal W:CFIXED(2*(W_high+1)-1 downto 2*W_low); + signal V,CZ:BOOLEAN; +--2008 signal ID:CFIXED(RE(I(I'low).RE'high downto I(I'low).RE'low),IM(I(I'low).IM'high downto I(I'low).IM'low)); + signal ID:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal IJ:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal OJ:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if SPLIT_RADIX=0 then + if not VI or (CNT=N/RADIX-1) then + JK<=(others=>'0'); + else + JK<=JK+J; + end if; + else + JK<=TO_UNSIGNED(J*SPLIT_RADIX,JK'length); + end if; + end if; + end process; + + ut:entity work.TABLE generic map(N=>N, + INV_FFT=>INV_FFT, + DSP48E=>DSP48E, + STYLE=>STYLE(N/4)) + port map(CLK=>CLK, + JK=>JK, + VI=>VI, + CZ=>CZ, + W=>W, + VO=>V); + + IJ<=ELEMENT(I,J,RADIX); +--!! cd:entity work.CDELAY generic map(SIZE=>3) + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)) + port map(CLK=>CLK, +--2008 I=>I(I'low+J), + I=>IJ, + O=>ID); + + u1:entity work.CM3 generic map(ROUNDING=>ROUNDING, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ID, + W=>W, + CZ=>CZ, + VI=>V, +--2008 O=>O(O'low+J), + O=>OJ, + VO=>open); + O((J+1)*O'length/RADIX-1+O'low downto J*O'length/RADIX+O'low)<=CFIXED_VECTOR(OJ); + end generate; + +--!! bd:entity work.BDELAY generic map(SIZE=>3+6) + bd:entity work.BDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>VI, + O=>VO); + +--!! ud:entity work.UDELAY generic map(SIZE=>3+6) + ud:entity work.UDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>SI, + O=>SO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: PARFFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity PARFFT is + generic(N:INTEGER:=4; + F:INTEGER:=0; + INV_FFT:BOOLEAN:=FALSE; + ROUNDING:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-16; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end PARFFT; + +architecture TEST of PARFFT is + constant I_low:INTEGER:=I'low/2/N; + constant I_high:INTEGER:=I'length/2/N-1+I_low; + constant O_low:INTEGER:=O'low/2/N; + constant O_high:INTEGER:=O'length/2/N-1+O_low; + + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + constant L2N:INTEGER:=LOG2(N); +begin +--2008 assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + + f0:if F=0 generate + begin + l2:if N=2 generate -- FFT2 case + signal I0,I1:CFIXED(2*I_high+1 downto 2*I_low); + signal O0,O1:CFIXED(2*O_high+1 downto 2*O_low); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,2); + I1<=ELEMENT(I,1,2); +-- complex add/sub butterfly with scaling and overflow detection + bf:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I1, + SCALE=>SI(SI'low), + O0=>O0, + O1=>O1, + OVR=>SO(SO'high)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/2-1+O'low downto 0*O'length/2+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/2-1+O'low downto 1*O'length/2+O'low)<=CFIXED_VECTOR(O1); + + process(CLK) + begin + if rising_edge(CLK) then + iSO<=SI(SI'high downto SI'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>1) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=4 generate -- FFT4 case + l4:if N=4 generate -- FFT4 case + signal I0,I1,I2,I3:CFIXED(2*I_high+1 downto 2*I_low); + signal P0,P1,P2,P3,P3S:CFIXED(2*I_high+3 downto 2*I_low); + signal O0,O1,O2,O3,O1S,O3S:CFIXED(2*O_high+1 downto 2*O_low); + signal S:UNSIGNED(SI'range):=(others=>'0'); + signal OVR1,OVR2:UNSIGNED(1 downto 0); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,4); + I1<=ELEMENT(I,1,4); + I2<=ELEMENT(I,2,4); + I3<=ELEMENT(I,3,4); +-- complex add/sub butterflies with scaling and overflow detection + u0:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I2, + SCALE=>SI(SI'low), + O0=>P0, + O1=>P1, + OVR=>OVR1(0)); + + u1:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I1, + I1=>I3, + SCALE=>SI(SI'low), + O0=>P2, + O1=>P3, + OVR=>OVR1(1)); + + process(CLK) + begin + if rising_edge(CLK) then + S<=(OVR1(0) or OVR1(1))&SI(SI'high downto SI'low+1); + end if; + end process; + + u2:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P0, + I1=>P2, + SCALE=>S(S'low), + O0=>O0, + O1=>O2, + OVR=>OVR2(0)); + + P3S<=SWAP(P3); + u3:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P1, + I1=>P3S, + SCALE=>S(S'low), + O0=>O1S, + O1=>O3S, + OVR=>OVR2(1)); + O1<=TO_CFIXED(RE(O1S),IM(O3S)); + O3<=TO_CFIXED(RE(O3S),IM(O1S)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/4-1+O'low downto 0*O'length/4+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/4-1+O'low downto 1*O'length/4+O'low)<=CFIXED_VECTOR(O1); + O((2+1)*O'length/4-1+O'low downto 2*O'length/4+O'low)<=CFIXED_VECTOR(O2); + O((3+1)*O'length/4-1+O'low downto 3*O'length/4+O'low)<=CFIXED_VECTOR(O3); + + SO(SO'high)<=(OVR2(0) or OVR2(1)); + process(CLK) + begin + if rising_edge(CLK) then + iSO<=S(S'high downto S'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=8 generate -- FFT8 case + l8:if N=8 generate -- FFT8 case +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/8/2-(I'high+1)/8/2; + constant X:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,1); -- ModelSim workaround + signal iV:BOOLEAN_VECTOR(0 to 3); +--2008 signal S:UNSIGNED_VECTOR(0 to 3)(SI'range); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:TUV(0 to 3); + signal SS:UNSIGNED(SI'range); + signal P:CFIXED_VECTOR(I'high+8*2*X downto I'low); + signal VP:BOOLEAN; + signal SP:UNSIGNED(SI'range); + signal oV:BOOLEAN_VECTOR(0 to 1); +--2008 signal oS:UNSIGNED_VECTOR(0 to 1)(SO'range); + signal oS:TUV(0 to 1); + begin + s1:for K in 0 to 3 generate +--2008 signal II:CFIXED_VECTOR(0 to 1)(RE(I(0).RE'high downto I(0).RE'low),IM(I(0).IM'high downto I(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 1)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); + signal II:CFIXED_VECTOR(4*(I_high+1)-1 downto 4*I_low); + signal OO:CFIXED_VECTOR(4*(I_high+1+2*X)-1 downto 4*I_low); + signal OO0,OO1:CFIXED(2*(I_high+1+2*X)-1 downto 2*I_low); + signal P0,P1:CFIXED(I'length/8+2*X-1+I'low/8 downto I'low/8); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=I(K); +--2008 II(1)<=I(K+4); + II((0+1)*II'length/2-1+II'low downto 0*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K,8)); + II((1+1)*II'length/2-1+II'low downto 1*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K+4,8)); + p2:entity work.PARFFT generic map(N=>2, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>iV(K), + SO=>S(K)); + OO0<=ELEMENT(OO,0,2); + OO1<=ELEMENT(OO,1,2); + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>OO(0), +--2008 O=>P(2*K+0)); + I=>OO0, + O=>P0); + ck:entity work.CKCM generic map(DSP48E=>DSP48E, + M=>K, + ROUNDING=>ROUNDING, + CONJUGATE=>INV_FFT) + port map(CLK=>CLK, +--2008 I=>OO(1), +--2008 O=>P(2*K+1)); + I=>OO1, + O=>P1); + P((2*K+1)*P'length/8-1+P'low downto (2*K+0)*P'length/8+P'low)<=CFIXED_VECTOR(P0); + P((2*K+2)*P'length/8-1+P'low downto (2*K+1)*P'length/8+P'low)<=CFIXED_VECTOR(P1); + end generate; + SS(SI'high)<=S(0)(SI'high) or S(1)(SI'high) or S(2)(SI'high) or S(3)(SI'high) when iV(0) else '0'; + SS(SI'high-1 downto SI'low)<=S(0)(SI'high-1 downto SI'low); + ud:entity work.UDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>SS, + O=>SP); + bd:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>iV(0), + O=>VP); + s2:for K in 0 to 1 generate +--2008 signal II:CFIXED_VECTOR(0 to 3)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 3)(RE(O(0).RE'high downto O(0).RE'low),IM(O(0).IM'high downto O(0).IM'low)); + signal II:CFIXED_VECTOR((P'high+1)/2-1 downto P'low/2); + signal OO:CFIXED_VECTOR((O'high+1)/2-1 downto O'low/2); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=P(K+0); +--2008 II(1)<=P(K+2); +--2008 II(2)<=P(K+4); +--2008 II(3)<=P(K+6); + II((0+1)*II'length/4-1+II'low downto 0*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+0,8)); + II((1+1)*II'length/4-1+II'low downto 1*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+2,8)); + II((2+1)*II'length/4-1+II'low downto 2*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+4,8)); + II((3+1)*II'length/4-1+II'low downto 3*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+6,8)); + p2:entity work.PARFFT generic map(N=>4, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VP, + SI=>SP, + O=>OO, + VO=>oV(K), + SO=>oS(K)); +--2008 O(K+0)<=OO(0); +--2008 O(K+2)<=OO(1); +--2008 O(K+4)<=OO(2); +--2008 O(K+6)<=OO(3); + O((K+0+1)*O'length/8-1+O'low downto (K+0)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,0,4)); + O((K+2+1)*O'length/8-1+O'low downto (K+2)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,1,4)); + O((K+4+1)*O'length/8-1+O'low downto (K+4)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,2,4)); + O((K+6+1)*O'length/8-1+O'low downto (K+6)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,3,4)); + end generate; + VO<=oV(0); + SO(SO'high downto SO'high-1)<=oS(0)(SO'high downto SO'high-1) or oS(1)(SO'high downto SO'high-1) when oV(0) else "00"; + SO(SO'high-2 downto SO'low)<=oS(0)(SO'high-2 downto SO'low); +-- end; + end generate; +-- elsif N=2**L2N generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation + ln:if (N>8) and (N=2**L2N) generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/N/2-(I'high+1)/N/2; + constant X1:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-2); -- ModelSim workaround + constant X2:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-1); -- ModelSim workaround + function MUL_LATENCY(N:INTEGER) return INTEGER is + begin + return 6; + end; + function LATENCY(N:INTEGER) return INTEGER is + begin + return LOG2(N)*4-6; + end; +--2008 signal IU:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal U,UD:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); + signal IU:CFIXED_VECTOR((I'high+1)/2-1 downto I'low/2); + signal U,UD:CFIXED_VECTOR((I'high+1)/2-1+N/2*2*X2 downto I'low/2); + signal SU,SUD:UNSIGNED(SI'range); + signal VU,VU4D:BOOLEAN; +--2008 signal ZO:CFIXED_MATRIX(0 to N/4-1)(0 to 1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(2*2*(I_high+X1+1)-1 downto 2*2*I_low); -- unconstrained array of CFIXED_VECTOR + signal ZO:CFIXED_MATRIX(0 to N/4-1); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); +--2008 signal S1:UNSIGNED_VECTOR(0 to 1)(SI'range); + signal S1:TUV(0 to 1); + signal S1I:UNSIGNED(SI'range); +--2008 signal S2:UNSIGNED_VECTOR(0 to N/4-1)(SI'range); + signal S2:TUV(0 to N/4-1); + signal S2I:UNSIGNED(SI'range):=(others=>'0'); +--2008 signal S:UNSIGNED_VECTOR(0 to N/2-1)(SI'range); + signal S:TUV(0 to N/2-1); + begin + lk:for K in 0 to N/2-1 generate +--2008 IU(K)<=I(I'low+2*K); + IU((K+1)*IU'length/N*2-1+IU'low downto K*IU'length/N*2+IU'low)<=CFIXED_VECTOR(ELEMENT(I,2*K,N)); + end generate; + pu:entity work.PARFFT generic map(N=>N/2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IU, + VI=>VI, + SI=>SI, + O=>U, + VO=>VU, + SO=>SU); + du:for K in 0 to N/2-1 generate + signal UK,UDK:CFIXED((UD'high+1)/N*2-1 downto UD'low/N*2); + begin + UK<=ELEMENT(U,K,N/2); + cd:entity work.CDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+1-LATENCY(N/2))--3) -- when CMUL latency is 6 + port map(CLK=>CLK, +--2008 I=>U(K), +--2008 O=>UD(K)); + I=>UK, + O=>UDK); + UD((K+1)*UD'length/N*2-1+UD'low downto K*UD'length/N*2+UD'low)<=CFIXED_VECTOR(UDK); + end generate; + u4:entity work.UDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>SU, + O=>SUD); + b5:entity work.BDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>VU, + O=>VO); + ll:for L in 0 to 1 generate +--2008 signal IZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal Z,OZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + signal IZ:CFIXED_VECTOR((I'high+1)/4-1 downto I'low/4); + signal Z,OZ:CFIXED_VECTOR((I'high+1)/4-1+N/4*2*X1 downto I'low/4); + signal SZ:UNSIGNED(SI'range); + signal SM:UNSIGNED(SI'range); + signal VZ:BOOLEAN; + begin + li:for J in 0 to N/4-1 generate +--2008 IZ(J)<=I(I'low+4*J+2*L+1); + IZ(2*(J+1)*(I_high-I_low+1)-1+IZ'low downto 2*J*(I_high-I_low+1)+IZ'low)<=CFIXED_VECTOR(ELEMENT(I,4*J+2*L+1,N)); + end generate; + pe:entity work.PARFFT generic map(N=>N/4, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IZ, + VI=>VI, + SI=>SI, + O=>Z, + VO=>VZ, + SO=>SZ); + me:entity work.CM3FFT generic map(N=>N, + RADIX=>N/4, + SPLIT_RADIX=>2*L+1, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>Z, + VI=>VZ, + SI=>SZ, + O=>OZ, + VO=>open, + SO=>S1(L)); + lo:for J in 0 to N/4-1 generate +--2008 ZO(J)(L)<=OZ(J); + ZO(J)((L+1)*ZO(J)'length/2-1+ZO(J)'low downto L*ZO(J)'length/2+ZO(J)'low)<=CFIXED_VECTOR(ELEMENT(OZ,J,N/4)); + end generate; + end generate; + S1I<=S1(0) or S1(1); + l2:for J in 0 to N/4-1 generate +--2008 signal O2:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal IE,IO:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal OE,OO:CFIXED_VECTOR(0 to 1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal O2:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal IE,IO:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal OE,OO:CFIXED_VECTOR(2*2*(O_high+1)-1 downto 2*2*O_low); + begin + p2:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ZO(J), + VI=>TRUE, + SI=>S1I, + O=>O2, + VO=>open, + SO=>S2(J)); +--2008 IE(0)<=UD(J); +--2008 IE(1)<=O2(0); + IE((0+1)*IE'length/2-1+IE'low downto 0*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(UD,J,N/2)); + IE((1+1)*IE'length/2-1+IE'low downto 1*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(O2,0,2)); + pe:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IE, + VI=>TRUE, + SI=>S2I, + O=>OE, + VO=>open, + SO=>S(2*J)); +--2008 O(O'low+J)<=OE(0); +--2008 O(O'low+J+N/2)<=OE(1); +--2008 IO(0)<=UD(J+N/4); +--2008 IO(1).RE<=O2(1).IM; +--2008 IO(1).IM<=O2(1).RE; +-- O((J+1)*O'length/N-1+O'low downto J*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); +-- O((J+N/2+1)*O'length/N-1+O'low downto (J+N/2)*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + O(2*(J+1)*(O_high-O_low+1)-1+O'low downto 2*J*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); + O(2*(J+N/2+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/2)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + IO((0+1)*IO'length/2-1+IO'low downto 0*IO'length/2+IO'low)<=CFIXED_VECTOR(ELEMENT(UD,J+N/4,N/2)); + IO((1+1)*IO'length/2-1+IO'low downto 1*IO'length/2+IO'low)<=CFIXED_VECTOR(TO_CFIXED(IM(ELEMENT(O2,1,2)),RE(ELEMENT(O2,1,2)))); + po:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IO, + VI=>TRUE, + SI=>S2I, + O=>OO, + VO=>open, + SO=>S(2*J+1)); + ii:if INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(1).RE; +--2008 O(O'low+J+N/4).IM<=OO(0).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(0).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(1).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- end; + end generate; +-- else generate + id:if not INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(0).RE; +--2008 O(O'low+J+N/4).IM<=OO(1).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(1).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(0).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- end; + end generate; + end generate; + process(S2) + variable vS2:UNSIGNED(SI'range); + begin + vS2:=SUD; + for K in S2'range loop + vS2:=vS2 or S2(K); + end loop; + S2I<=vS2; + end process; + process(S) + variable vS:UNSIGNED(SI'range); + begin + vS:=(others=>'0'); + for K in S'range loop + vS:=vS or S(K); + end loop; + SO<=vS; + end process; +-- end; + end generate; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=N/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.PARFFT generic map(N=>G, + F=>0, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ?? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: INPUT_SWAP.vhd +-- / / Date Last Modified: 14 February 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: INPUT_SWAP +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Input Order Swap Module for Systolic FFT +-- The module takes N samples, I'length per clock, in natural input order +-- and outputs them in natural transposed order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity INPUT_SWAP is + generic(N:INTEGER; -- N must be a power of 2 + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + USE_CB:BOOLEAN:=TRUE); -- if FALSE use alternate architecture + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; -- I'length must be a divisor of N, so it is also a power of 2 + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end INPUT_SWAP; + +architecture TEST of INPUT_SWAP is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs in last stage + + function RS(K:INTEGER) return STRING is + begin + if K) of CFIXED_VECTOR(I'range); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + + i0:if USE_CB or (L2N<=2*L2R) generate + constant SIZE:INTEGER:=L2N/L2R; -- floor(LOG2(N)/LOG2(RADIX)) + + signal V:BOOLEAN_VECTOR(0 to SIZE-1); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE-1)(SI'range); +--2008 signal D:CFIXED_MATRIX(0 to SIZE-1)(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:UNSIGNED_VECTOR(0 to SIZE-1); + signal D:iCFIXED_MATRIX(0 to SIZE-1); + begin + D(D'low)<=I; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-2 generate + bc:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>RADIX**K, + INPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K/RADIX), -- this helps reduce + OUTPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K mod RADIX**(SIZE-2)), -- RAM count and + SHORTEN_VO_BY=>(RADIX-1)*RADIX**K mod ((RADIX-1)*RADIX**(SIZE-2))) -- latency by N/RADIX/RADIX-1 clocks + port map(CLK=>CLK, + I=>D(K), + VI=>V(K), + SI=>S(K), + O=>D(K+1), + VO=>V(K+1), + SO=>S(K+1)); + end generate; +--Last stage, it becomes a trivial assignment if F=0 + bl:block + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SI'range); + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + lj:for J in OV'range generate +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin + bc:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>RADIX**(SIZE-1)) + port map(CLK=>CLK, +--2008 I=>D(D'high)(I'low+G*J+0 to I'low+G*J+G-1), + I=>D(D'high)(I'length/H*(J+1)-1+I'low downto I'length/H*J+I'low), + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>OV(J), + SO=>OS(J)); + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(K); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+1)-1+OO'low downto O'length/SSR*K+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); + end block; +--2008 end; + end generate; +--2008 else generate + i1:if (not USE_CB) and (L2N>2*L2R) generate + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + signal WSEL:UNSIGNED(LOG2(WCNT'length)-1 downto 0):=TO_UNSIGNED(0,LOG2(RCNT'length)); + signal RSEL:UNSIGNED(LOG2(RCNT'length)-1 downto 0):=TO_UNSIGNED(L2N-2*L2R,LOG2(RCNT'length)); +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal OV:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + if RSEL'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + WA<=ROTATE_LEFT(WCNT,TO_INTEGER(WSEL)); + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + RA<=ROTATE_LEFT(RCNT,TO_INTEGER(RSEL)); + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); + IO<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>OV); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+5) + port map(CLK=>CLK, + I=>SI, + O=>S); + + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>IO, + VI=>OV, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SYSTOLIC_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SYSTOLIC_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Systolic FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity SYSTOLIC_FFT is + generic(N:INTEGER; + SSR:INTEGER; --93 + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end SYSTOLIC_FFT; + +architecture TEST of SYSTOLIC_FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB and PARFFT in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs and PARFFTsin last stage + constant SIZE:INTEGER:=(L2N-1)/L2R; -- ceil(LOG2(N)/LOG2(RADIX)), number of stages +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/2/SSR-(I'high+1)/2/SSR; + +-- constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((SIZE-1)*L2R,BIT_GROWTH); + constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); +--2008 signal D:CFIXED_MATRIX(0 to SIZE)(I'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(O'range); -- unconstrained array of CFIXED_VECTOR + signal D:CFIXED_MATRIX(0 to SIZE); + signal V:BOOLEAN_VECTOR(0 to SIZE); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE)(SI'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); --93 + signal S:UNSIGNED_VECTOR(0 to SIZE); + +-- constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(L2N,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal OO:CFIXED_VECTOR(O'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal OO:CFIXED_VECTOR(O'range); +begin +--2008 lj:for J in I'range generate +--2008 D(D'low)(J)<=RESIZE(I(J),D(D'low)(J)); + lj:for J in 0 to SSR-1 generate + D(D'low)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(I,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-1 generate + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(K*L2R,BIT_GROWTH); + constant XO:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((K+1)*L2R,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal DM,DB,DO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XO downto I(I'low).RE'low),IM(I(I'low).IM'high+XO downto I(I'low).IM'low)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal DM,DB,DO:CFIXED_VECTOR(I'high+2*SSR*XO downto I'low); + signal VM,VB:BOOLEAN; + signal SM,SB:UNSIGNED(SI'range); + begin +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(K)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(K),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, --93 + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(K), + SI=>S(K), + O=>DM, + VO=>VM, + SO=>SM); + cm:entity work.CM3FFT generic map(N=>N/(RADIX**K), + RADIX=>RADIX, --93 + INV_FFT=>FALSE, + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DM, + VI=>VM, + SI=>SM, + O=>DB, + VO=>VB, + SO=>SB); + + bc:entity work.CB generic map(SSR=>RADIX, --93 + F=>F*BOOLEAN'pos(K=SIZE-1), + PACKING_FACTOR=>N/(RADIX**(K+2))*BOOLEAN'pos(KBRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DB, + VI=>VB, + SI=>SB, + O=>DO, + VO=>V(K+1), + SO=>S(K+1)); +--2008 lo:for J in 0 to I'length-1 generate +--2008 D(K+1)(J)<=RESIZE(DO(DO'low+J),D(K+1)(J)); + lo:for J in 0 to SSR-1 generate + D(K+1)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(DO,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + end generate; +--last PARFFT stage +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(D'high)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(D'high),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, + F=>F, + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>VO, + SO=>SO); + lo:for J in 0 to H-1 generate + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(OO'low+K+G*J); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+G*J+1)-1+OO'low downto O'length/SSR*(K+G*J)+OO'low); + end generate; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DS.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DS +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Transposed Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DS is -- LATENCY=0 when N=2*SSR else LATENCY=N/SSR+1 + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DS; + +architecture TEST of DS is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + + function RS(K:INTEGER) return STRING is + begin + if K) of UNSIGNED(RCNT'range); --93 + function IDENTITY(K:INTEGER) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(0 to K-1);--93 (LOG2(K)-1 downto 0); + begin + for J in RESULT'range loop + RESULT(J):=TO_UNSIGNED(J,RESULT(J)'length); + end loop; + return RESULT; + end; + + function PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT((A'length/L2R-1-J)*L2R+K+F):=A(J*L2R+K); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(K):=A(A'length/L2R*L2R+K); + end loop; + end loop; + return RESULT; + end; + + function INVERSE_PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT(J*L2R+K):=A((A'length/L2R-1-J)*L2R+K+F); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(A'length/L2R*L2R+K):=A(K); + end loop; + end loop; + return RESULT; + end; + +--2008 signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1)(LOG2(WCNT'length)-1 downto 0):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); +--2008 signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1)(LOG2(RCNT'length)-1 downto 0):=IDENTITY(RCNT'length); + signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); + signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1):=IDENTITY(RCNT'length); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i0:if L2N-L2R<2 generate + O<=I; + VO<=VI; + SO<=SI; +--2008 else generate + end generate; + i1:if L2N-L2R>=2 generate + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + RSEL<=PERMUTE(WSEL); + end if; + RCNT<=RCNT+1; + else + RCNT<=(others=>'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in WCNT'range loop + WA(K)<=WCNT(TO_INTEGER(WSEL(K))); + end loop; + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in RCNT'range loop + RA(K)<=RCNT(TO_INTEGER(RSEL(K))); + end loop; + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + type iCFIXED_MATRIX is array(NATURAL range <>) of CFIXED_VECTOR(I'range); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); +--2008 O(K)<=Q; + O<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>VO); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX+1) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DSN.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DSN +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Natural Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DSN is + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DSN; + +architecture TEST of DSN is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + constant H:INTEGER:=RADIX/G; +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i1:if L2N<2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SI'range); + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SO'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SO'range); --93 + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + sd:entity work.DS generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + lk:for K in 0 to H-1 generate +----2008 signal II,OO:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal II,OO:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + begin + li:for J in 0 to G-1 generate +--2008 II(J)<=IO(IO'low+K+H*J); + II(I'length/SSR*(J+1)-1+II'low downto I'length/SSR*J+II'low)<=IO(I'length/SSR*(K+H*J+1)-1+I'low downto I'length/SSR*(K+H*J)+I'low); + end generate; + ci:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OO, + VO=>OV(K), + SO=>OS(K)); + lo:for J in 0 to G-1 generate +----2008 O(O'low+K*G+J)<=OO(J); + O(O'length/SSR*(K*G+J+1)-1+O'low downto O'length/SSR*(K*G+J)+O'low)<=OO(O'length/SSR*(J+1)-1+OO'low downto O'length/SSR*J+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); +--2008 end; + end generate; +--2008 elsif L2N=2*L2R generate + i2:if L2N=2*L2R generate + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>O, + VO=>VO, + SO=>SO); +--2008 else generate + end generate; + i3:if L2N>2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>N/RADIX/RADIX, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + + sd:entity work.DS generic map(N=>N/RADIX, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>IO, + VI=>V, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: VECTOR_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: VECTOR_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Top Level Test Module for SYSTOLIC_FFT +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity VECTOR_FFT is + generic(SSR:INTEGER:=8;--4; + N:INTEGER:=16384;--8192;--4096;--1024; + I_high:INTEGER:=0; + I_low:INTEGER:=-17; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; +--2008 I:in CFIXED_VECTOR(0 to RADIX-1)(RE(I_high downto I_low),IM(I_high downto I_low)); + I:in CFIXED_VECTOR(SSR*2*(I_high-I_low+1)-1 downto 0); + VI:in BOOLEAN; + SI:in UNSIGNED(LOG2(N)-1 downto 0); +--2008 O:out CFIXED_VECTOR(0 to RADIX-1)(RE(O_high downto O_low),IM(O_high downto O_low)); + O:out CFIXED_VECTOR(SSR*2*(O_high-O_low+1)-1 downto 0); + VO:out BOOLEAN; + SO:out UNSIGNED(LOG2(N)-1 downto 0)); +end VECTOR_FFT; + +architecture TEST of VECTOR_FFT is + function TO_SFIXED(S:STD_LOGIC_VECTOR;I:SFIXED) return SFIXED is + variable R:SFIXED(I'range); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + + function TO_STD_LOGIC_VECTOR(S:SFIXED) return STD_LOGIC_VECTOR is + variable R:STD_LOGIC_VECTOR(S'length-1 downto 0); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + +--2008 signal II:CFIXED_VECTOR(I'range)(RE(I_high downto I_low),IM(I_high downto I_low)); + signal II:CFIXED_VECTOR(I'range); + signal V,VOFFT,VODS:BOOLEAN; + signal S,SFFT,SODS:UNSIGNED(SI'range); +--2008 signal OFFT,ODS:CFIXED_VECTOR(O'range)(RE(O_high downto O_low),IM(O_high downto O_low)); + signal OFFT,ODS:CFIXED_VECTOR(O'range); +begin + u0:entity work.INPUT_SWAP generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>II, + VO=>V, + SO=>S); + + u1:entity work.SYSTOLIC_FFT generic map(N=>N, + SSR=>SSR, --93 + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OFFT, + VO=>VOFFT, + SO=>SFFT); + + u2:entity work.DSN generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>OFFT, + VI=>VOFFT, + SI=>SFFT, + O=>O, + VO=>VO, + SO=>SO); +-- O<=OFFT; +-- VO<=VOFFT; +-- SO<=SFFT; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.COMPLEX_FIXED_PKG.all; + +entity WRAPPER_VECTOR_FFT is + generic(SSR:INTEGER:=8; + N:INTEGER:=512; + L2N:INTEGER:=9; -- L2N must be set equal to log2(N)!!! + I_high:INTEGER:=0; + I_low:INTEGER:=-15; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-15; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + CE:in STD_LOGIC:='1'; -- not used, for SysGen only + I:in STD_LOGIC_VECTOR(2*SSR*(I_high-I_low+1)-1 downto 0); + VI:in STD_LOGIC; + SI:in STD_LOGIC_VECTOR(L2N-1 downto 0):=(L2N-1 downto 0=>'0'); -- can be left unconnected if internal scaling is not used, must be a (LOG2(N)-1 downto 0) port + O:out STD_LOGIC_VECTOR(2*SSR*(O_high-O_low+1)-1 downto 0); + VO:out STD_LOGIC; + SO:out STD_LOGIC_VECTOR(L2N-1 downto 0)); -- can be left unconnected if internal overflow is not possible, must be a (LOG2(N)-1 downto 0) port +end WRAPPER_VECTOR_FFT; + +architecture WRAPPER of WRAPPER_VECTOR_FFT is +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if KSSR, + N=>N, + I_high=>I_high, + I_low=>I_low, + W_high=>W_high, + W_low=>W_low, + O_high=>O_high, + O_low=>O_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB, + DSP48E=>DSP48E) -- 1 for DSP48E1, 2 for DSP48E2 + port map(CLK=>CLK, + I=>II, + VI=>VII, + SI=>SII, + O=>OO, + VO=>VOO, + SO=>SOO); + O<=STD_LOGIC_VECTOR(OO); + VO<='1' when VOO else '0'; + SO<=STD_LOGIC_VECTOR(SOO); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity WRAPPER_VECTOR_FFT_c48f0cd3f27fd6fdac4ed316c161272e is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 8; + N : integer := 256; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(7 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(7 downto 0); + CLK : in std_logic; + CE : in std_logic + ); +end WRAPPER_VECTOR_FFT_c48f0cd3f27fd6fdac4ed316c161272e; +architecture structural of WRAPPER_VECTOR_FFT_c48f0cd3f27fd6fdac4ed316c161272e is + signal I_net : std_logic_vector(255 downto 0); + signal VI_net : std_logic; + signal SI_net : std_logic_vector(7 downto 0); + signal O_net : std_logic_vector(431 downto 0); + signal VO_net : std_logic; + signal SO_net : std_logic_vector(7 downto 0); + signal CLK_net : std_logic; + signal CE_net : std_logic; + component WRAPPER_VECTOR_FFT is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 8; + N : integer := 256; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(7 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(7 downto 0); + CLK : in std_logic; + CE : in std_logic + ); + end component; +begin + I_net <= I; + VI_net <= VI; + SI_net <= SI; + O <= O_net; + VO <= VO_net; + SO <= SO_net; + CLK_net <= CLK; + CE_net <= CE; + WRAPPER_VECTOR_FFT_inst : WRAPPER_VECTOR_FFT + generic map( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 8, + N => 256, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map( + I => I_net, + VI => VI_net, + SI => SI_net, + O => O_net, + VO => VO_net, + SO => SO_net, + CLK => CLK_net, + CE => CE_net + ); +end structural; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlslice.vhd +-- +-- Description : VHDL description of a block that sets the output to a +-- specified range of the input bits. The output is always +-- set to an unsigned type with it's binary point at zero. +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x256_xlslice is + generic ( + new_msb : integer := 9; -- position of new msb + new_lsb : integer := 1; -- position of new lsb + x_width : integer := 16; -- Width of x input + y_width : integer := 8); -- Width of y output + port ( + x : in std_logic_vector (x_width-1 downto 0); + y : out std_logic_vector (y_width-1 downto 0)); +end ssr_8x256_xlslice; + +architecture behavior of ssr_8x256_xlslice is +begin + y <= x(new_msb downto new_lsb); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_6128f842cc is + port ( + in0 : in std_logic_vector((16 - 1) downto 0); + in1 : in std_logic_vector((16 - 1) downto 0); + y : out std_logic_vector((32 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_6128f842cc; +architecture behavior of sysgen_concat_6128f842cc +is + signal in0_1_23: unsigned((16 - 1) downto 0); + signal in1_1_27: unsigned((16 - 1) downto 0); + signal y_2_1_concat: unsigned((32 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_3bad6996c0 is + port ( + input_port : in std_logic_vector((16 - 1) downto 0); + output_port : out std_logic_vector((16 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_3bad6996c0; +architecture behavior of sysgen_reinterpret_3bad6996c0 +is + signal input_port_1_40: signed((16 - 1) downto 0); + signal output_port_5_5_force: unsigned((16 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_signed(input_port); + output_port_5_5_force <= signed_to_unsigned(input_port_1_40); + output_port <= unsigned_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_9cd5a6908e is + port ( + input_port : in std_logic_vector((27 - 1) downto 0); + output_port : out std_logic_vector((27 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_9cd5a6908e; +architecture behavior of sysgen_reinterpret_9cd5a6908e +is + signal input_port_1_40: unsigned((27 - 1) downto 0); + signal output_port_5_5_force: signed((27 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_unsigned(input_port); + output_port_5_5_force <= unsigned_to_signed(input_port_1_40); + output_port <= signed_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_c6ccfb3c89 is + port ( + in0 : in std_logic_vector((32 - 1) downto 0); + in1 : in std_logic_vector((32 - 1) downto 0); + in2 : in std_logic_vector((32 - 1) downto 0); + in3 : in std_logic_vector((32 - 1) downto 0); + in4 : in std_logic_vector((32 - 1) downto 0); + in5 : in std_logic_vector((32 - 1) downto 0); + in6 : in std_logic_vector((32 - 1) downto 0); + in7 : in std_logic_vector((32 - 1) downto 0); + y : out std_logic_vector((256 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_c6ccfb3c89; +architecture behavior of sysgen_concat_c6ccfb3c89 +is + signal in0_1_23: unsigned((32 - 1) downto 0); + signal in1_1_27: unsigned((32 - 1) downto 0); + signal in2_1_31: unsigned((32 - 1) downto 0); + signal in3_1_35: unsigned((32 - 1) downto 0); + signal in4_1_39: unsigned((32 - 1) downto 0); + signal in5_1_43: unsigned((32 - 1) downto 0); + signal in6_1_47: unsigned((32 - 1) downto 0); + signal in7_1_51: unsigned((32 - 1) downto 0); + signal y_2_1_concat: unsigned((256 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + in2_1_31 <= std_logic_vector_to_unsigned(in2); + in3_1_35 <= std_logic_vector_to_unsigned(in3); + in4_1_39 <= std_logic_vector_to_unsigned(in4); + in5_1_43 <= std_logic_vector_to_unsigned(in5); + in6_1_47 <= std_logic_vector_to_unsigned(in6); + in7_1_51 <= std_logic_vector_to_unsigned(in7); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39) & unsigned_to_std_logic_vector(in5_1_43) & unsigned_to_std_logic_vector(in6_1_47) & unsigned_to_std_logic_vector(in7_1_51)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg.vhd new file mode 100644 index 0000000..770ff70 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg.vhd @@ -0,0 +1,95 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register without +-- an init value and a clear. SRLC32E components are used. The +-- initial value is always 0 +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRLC32s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg; + +architecture structural of synth_reg is + component srlc33e + generic (width : integer:=16; + latency : integer :=8); + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); + end component; + + function calc_num_srlc33es (latency : integer) + return integer + is + variable remaining_latency : integer; + variable result : integer; + begin + result := latency / 33; + + remaining_latency := latency - (result * 33); + -- If latency is not an even multiple of 33 then add one more + -- srlc33e to the pipeline + if (remaining_latency /= 0) then + result := result + 1; + end if; + + return result; + end; + + + constant complete_num_srlc33es : integer := latency / 33; + constant num_srlc33es : integer := calc_num_srlc33es(latency); + constant remaining_latency : integer := latency - (complete_num_srlc33es * 33); + -- Array for std_logic_vectors + type register_array is array (num_srlc33es downto 0) of + std_logic_vector(width-1 downto 0); + signal z : register_array; + +begin + + z(0) <= i; + complete_ones : if complete_num_srlc33es > 0 generate + srlc33e_array: for i in 0 to complete_num_srlc33es-1 generate + delay_comp : srlc33e + generic map (width => width, + latency => 33) + port map (clk => clk, + ce => ce, + d => z(i), + q => z(i+1)); + + end generate; + end generate; + + partial_one : if remaining_latency > 0 generate + last_srlc33e : srlc33e + generic map (width => width, + latency => remaining_latency) + port map (clk => clk, + ce => ce, + d => z(num_srlc33es-1), + q => z(num_srlc33es)); + end generate; + o <= z(num_srlc33es); +end structural; + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_reg.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_reg.vhd new file mode 100644 index 0000000..5d837de --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_reg.vhd @@ -0,0 +1,64 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_reg.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRL16s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg_reg; + +architecture behav of synth_reg_reg is + type reg_array_type is array (latency downto 0) of std_logic_vector(width -1 downto 0); + signal reg_bank : reg_array_type := (others => (others => '0')); + signal reg_bank_in : reg_array_type := (others => (others => '0')); + attribute syn_allow_retiming : boolean; + attribute syn_srlstyle : string; + attribute syn_allow_retiming of reg_bank : signal is true; + attribute syn_allow_retiming of reg_bank_in : signal is true; + attribute syn_srlstyle of reg_bank : signal is "registers"; + attribute syn_srlstyle of reg_bank_in : signal is "registers"; +begin -- behav + + latency_eq_0: if latency = 0 generate + o <= i; + end generate latency_eq_0; + + latency_gt_0: if latency >= 1 generate + o <= reg_bank(latency); + reg_bank(0) <= i; + + sync_loop: for sync_idx in latency downto 1 generate + sync_proc: process (clk) + begin -- process sync_proc + if clk'event and clk = '1' then -- rising clock edge + if clr = '1' then + reg_bank(sync_idx) <= (others => '0'); + elsif ce = '1' then + reg_bank(sync_idx) <= reg_bank(sync_idx-1); + end if; + end if; + end process sync_proc; + end generate sync_loop; + end generate latency_gt_0; + end behav; + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_w_init.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_w_init.vhd new file mode 100644 index 0000000..34bfa2e --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_w_init.vhd @@ -0,0 +1,98 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_w_init.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register with +-- an initial value. The register has clr and ce pins and +-- is implemented using flip-flops (i.e., not SRL16s). +-- +-- Mod. History : Delayed input .1 ns so that there isn't a setup +-- violation in the fdse or fdre Unisim models. +-- : Changed VHDL so that initial register is passed as a bit +-- vector generic value, instead of the const_pkg. +-- +-- Mod. Dates : 8/10/2001 +-- 3/19/2003 +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000"; + latency: integer := 1 + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end synth_reg_w_init; + +architecture structural of synth_reg_w_init is + component single_reg_w_init + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; -- end single_reg_w_init + + -- 1D array used to connect all the register together + signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); + signal dly_clr: std_logic; +begin + latency_eq_0: if (latency = 0) generate + o <= i; + end generate; -- end latency_eq_0 + + latency_gt_0: if (latency >= 1) generate + -- Delayed input 200 ps so that there isn't a setup violation in the + -- fdse or fdre Unisim models + dly_i((latency + 1) * width - 1 downto latency * width) <= i + after 200 ps; + dly_clr <= clr after 200 ps; + + fd_array: for index in latency downto 1 generate + reg_comp: single_reg_w_init + generic map ( + width => width, + init_index => init_index, + init_value => init_value + ) + port map ( + clk => clk, + i => dly_i((index + 1) * width - 1 downto index * width), + o => dly_i(index * width - 1 downto (index - 1) * width), + ce => ce, + clr => dly_clr + ); + end generate; -- end fd_array + + o <= dly_i(width - 1 downto 0); + end generate; -- end latency_gt_0 +end structural; + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd new file mode 100644 index 0000000..92017d4 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd @@ -0,0 +1,338 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlclockdriver.vhd +-- +-- Date : 10/1/99 +-- +-- Description : VHDL description of a clock enable generator block. +-- This code is synthesizable. +-- +-- Assumptions : period >= 1 +-- +-- Mod. History : Removed one shot & OR gate +-- If period is power of 2 a 1-bit smaller counter +-- is used and no sync clear +-- : Logic needed for use_bufg generic added +-- : Initial ce output is now 0 instead of 1 +-- Enable pulse now occurs at the end of the sample +-- period, instead of at the start +-- : Added pipeline registers +-- : added OR gate for sysclr to work properly +-- +-- Mod. Dates : 7/26/2001 +-- : 8/05/2001 +-- : 1/02/2002 +-- : 11/30/2004 +-- : 4/11/2005 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +entity xlclockdriver is + generic ( + period: integer := 2; + log_2_period: integer := 0; + pipeline_regs: integer := 5; + use_bufg: integer := 0 + ); + port ( + sysclk: in std_logic; + sysclr: in std_logic; + sysce: in std_logic; + clk: out std_logic; + clr: out std_logic; + ce: out std_logic; + ce_logic: out std_logic + ); +end xlclockdriver; + +architecture behavior of xlclockdriver is + component bufg + port ( + i: in std_logic; + o: out std_logic + ); + end component; + + component synth_reg_w_init + generic ( + width: integer; + init_index: integer; + init_value: bit_vector; + latency: integer + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; + + -- Returns the size of an unsigned integer + -- if power_of_2 is true return value is one less + function size_of_uint(inp: integer; power_of_2: boolean) + return integer + is + constant inp_vec: std_logic_vector(31 downto 0) := + integer_to_std_logic_vector(inp,32, xlUnsigned); + variable result: integer; + begin + result := 32; + for i in 0 to 31 loop + if inp_vec(i) = '1' then + result := i; + end if; + end loop; + if power_of_2 then + return result; + else + return result+1; + end if; + end; + + -- Returns boolean which says if 'inp' is a power of two + function is_power_of_2(inp: std_logic_vector) + return boolean + is + constant width: integer := inp'length; + variable vec: std_logic_vector(width - 1 downto 0); + variable single_bit_set: boolean; + variable more_than_one_bit_set: boolean; + variable result: boolean; + begin + vec := inp; + single_bit_set := false; + more_than_one_bit_set := false; + + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if width > 0 then + for i in 0 to width - 1 loop + if vec(i) = '1' then + if single_bit_set then + more_than_one_bit_set := true; + end if; + single_bit_set := true; + end if; + end loop; + end if; + if (single_bit_set and not(more_than_one_bit_set)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Returns initial value for pipeline registers + function ce_reg_init_val(index, period : integer) + return integer + is + variable result: integer; + begin + result := 0; + if ((index mod period) = 0) then + result := 1; + end if; + return result; + end; + + -- Returns the remainder(num_pipeline_regs/period) + 1 + function remaining_pipe_regs(num_pipeline_regs, period : integer) + return integer + is + variable factor, result: integer; + begin + factor := (num_pipeline_regs / period); + result := num_pipeline_regs - (period * factor) + 1; + return result; + end; + + -- Calculate the min + function sg_min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + constant max_pipeline_regs : integer := 8; + constant pipe_regs : integer := 5; + + -- Check if requested pipeline regs are greater than the max amount + constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); + constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); + + constant period_floor: integer := max(2, period); + constant power_of_2_counter: boolean := + is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); + constant cnt_width: integer := + size_of_uint(period_floor, power_of_2_counter); + constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); + + signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); + signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); + signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0); + signal internal_ce: std_logic_vector(0 downto 0); + signal internal_ce_logic: std_logic_vector(0 downto 0); + signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); +begin + -- Pass through the system clock and clear + clk <= sysclk; + clr <= sysclr; + + -- Clock Number Counter + cntr_gen: process(sysclk) + begin + if sysclk'event and sysclk = '1' then + if (sysce = '1') then + if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then + clk_num <= (others => '0'); + else + clk_num <= clk_num + 1; + end if; + end if; + end if; + end process; + + -- Clear logic for counter + clr_gen: process(clk_num, sysclr) + begin + if power_of_2_counter then + cnt_clr(0) <= sysclr; + else + -- Counter does not reset when clk_num = a power of 2 + if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 + or sysclr = '1') then + cnt_clr(0) <= '1'; + else + cnt_clr(0) <= '0'; + end if; + end if; + end process; + + clr_reg: synth_reg_w_init + generic map ( + width => 1, + init_index => 0, + init_value => b"0000", + latency => 1 + ) + port map ( + i => cnt_clr, + ce => sysce, + clr => sysclr, + clk => sysclk, + o => cnt_clr_dly + ); + + -- Clock enable generation + pipelined_ce : if period > 1 generate + ce_gen: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec(num_pipeline_regs) <= '1'; + else + ce_vec(num_pipeline_regs) <= '0'; + end if; + end process; + ce_pipeline: for index in num_pipeline_regs downto 1 generate + ce_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec(index-1 downto index-1) + ); + end generate; -- i + internal_ce <= ce_vec(0 downto 0); + end generate; + + -- Clock enable generation + pipelined_ce_logic: if period > 1 generate + ce_gen_logic: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec_logic(num_pipeline_regs) <= '1'; + else + ce_vec_logic(num_pipeline_regs) <= '0'; + end if; + end process; + ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate + ce_logic_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec_logic(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec_logic(index-1 downto index-1) + ); + end generate; -- i + internal_ce_logic <= ce_vec_logic(0 downto 0); + end generate; + + + use_bufg_true: if period > 1 and use_bufg = 1 generate + -- Clock enable with bufg + ce_bufg_inst: bufg + port map ( + i => internal_ce(0), + o => ce + ); + ce_bufg_inst_logic: bufg + port map ( + i => internal_ce_logic(0), + o => ce_logic + ); + end generate; + + use_bufg_false: if period > 1 and (use_bufg = 0) generate + -- Clock enable without bufg + ce <= internal_ce(0) and sysce; + ce_logic <= internal_ce_logic(0) and sysce; + end generate; + + generate_system_clk: if period = 1 generate + ce <= sysce; + ce_logic <= sysce; + end generate; +end architecture behavior; + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssrfft_8x256_sync.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssrfft_8x256_sync.vhd new file mode 100644 index 0000000..30f2d1e --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/ssrfft_8x256_sync.vhd @@ -0,0 +1,294 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity ssrfft_8x256_sync is + Generic + ( + NFFT : Integer := 16; + SSR : Integer := 4; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (2*SSR*B-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end entity; + +architecture rtl of ssrfft_8x256_sync is + +-- Framing. +component framing is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4; + + -- Bits. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- Synced outputs. + tdata : out std_logic_vector (2*SSR*B-1 downto 0); + tvalid : out std_logic + ); +end component; + +-- TLAST Generator. +component tlast_gen is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4 + ); + Port + ( + -- Input reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Input enable. + en : in std_logic; + + -- TLAST input/output. + o_tlast : out std_logic + ); +end component; + +-- SSR FFT 8x256. +component ssr_8x256 is + port ( + -- Clock signal. + clk : in std_logic; + + -- Input data. + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_scale : in std_logic_vector( 8-1 downto 0 ); + + -- Output data. + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_scale : out std_logic_vector( 8-1 downto 0 ) + ); +end component; + +-- Vectors with individual I,Q samples. +type data_v is array (SSR-1 downto 0) of std_logic_vector (B-1 downto 0); +signal din_iv : data_v; +signal din_qv : data_v; +signal dout_iv : data_v; +signal dout_qv : data_v; + +-- Vector with individual I,Q samples (fft out full precision). +type data_vf is array (SSR-1 downto 0) of std_logic_vector (27-1 downto 0); +signal dout_ivf : data_vf; +signal dout_qvf : data_vf; + +-- I,Q parts of input. +signal din_i : std_logic_vector (SSR*B-1 downto 0); +signal din_q : std_logic_vector (SSR*B-1 downto 0); + +-- Framing block signals. +signal framing_tdata : std_logic_vector (2*SSR*B-1 downto 0); +signal framing_tvalid : std_logic; + +-- FFT scale. +signal o_scale : std_logic_vector (7 downto 0); + +-- FFT output valid/last. +signal o_axis_tvalid : std_logic; +signal o_axis_tlast : std_logic; + +-- FFT data output. +signal o_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); + +-- Registers. +signal scale_reg_i : std_logic_vector (7 downto 0); +signal qout_reg_i : unsigned (3 downto 0); + +begin + +-- Registers. +scale_reg_i <= SCALE_REG (7 downto 0); + +-- Full-precision output: 27 bits. Required output: 16 bits. +-- Quantization selection from 0 to 11. +qout_reg_i <= (others => '0') when ( unsigned(QOUT_REG) > to_unsigned(11,QOUT_REG'length) ) else + unsigned(QOUT_REG(3 downto 0)); + +-- Input/output data to vector. +GEN: for I in 0 to SSR-1 generate + -- Input data to vector. + din_iv(I) <= framing_tdata(I*2*B+B-1 downto I*2*B ); + din_qv(I) <= framing_tdata(I*2*B+2*B-1 downto I*2*B+B ); + + -- Quantization selection. + dout_iv(I) <= dout_ivf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + dout_qv(I) <= dout_qvf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + + -- Output data to vector. + o_axis_tdata(I*2*B+B-1 downto I*2*B ) <= dout_iv(I); + o_axis_tdata(I*2*B+2*B-1 downto I*2*B+B ) <= dout_qv(I); +end generate GEN; + +-- Framing. +framing_i : framing + Generic map + ( + -- SSR and FFT Length. + NFFT => NFFT , + SSR => SSR , + + -- Bits. + B => B + ) + Port map + ( + -- Reset and clock. + aresetn => aresetn , + aclk => aclk , + + -- AXIS Slave. + s_axis_tdata => s_axis_tdata , + s_axis_tlast => s_axis_tlast , + s_axis_tvalid => s_axis_tvalid , + + -- Synced outputs. + tdata => framing_tdata , + tvalid => framing_tvalid + ); + +-- TLAST Generator. +tlast_gen_i : tlast_gen + Generic map + ( + -- SSR and FFT Length. + NFFT => NFFT , + SSR => SSR + ) + Port map + ( + -- Input reset and clock. + rstn => aresetn , + clk => aclk , + + -- Input enable. + en => o_axis_tvalid , + + -- TLAST input/output. + o_tlast => o_axis_tlast + ); + +-- SSR FFT 8x256. +ssr_8x256_i : ssr_8x256 + port map ( + -- Clock signal. + clk => aclk , + + -- Input data. + i_re_0 => din_iv(0) , + i_re_1 => din_iv(1) , + i_re_2 => din_iv(2) , + i_re_3 => din_iv(3) , + i_re_4 => din_iv(4) , + i_re_5 => din_iv(5) , + i_re_6 => din_iv(6) , + i_re_7 => din_iv(7) , + i_im_0 => din_qv(0) , + i_im_1 => din_qv(1) , + i_im_2 => din_qv(2) , + i_im_3 => din_qv(3) , + i_im_4 => din_qv(4) , + i_im_5 => din_qv(5) , + i_im_6 => din_qv(6) , + i_im_7 => din_qv(7) , + i_valid(0) => framing_tvalid , + i_scale => scale_reg_i , + + -- Output data. + o_re_0 => dout_ivf(0) , + o_re_1 => dout_ivf(1) , + o_re_2 => dout_ivf(2) , + o_re_3 => dout_ivf(3) , + o_re_4 => dout_ivf(4) , + o_re_5 => dout_ivf(5) , + o_re_6 => dout_ivf(6) , + o_re_7 => dout_ivf(7) , + o_im_0 => dout_qvf(0) , + o_im_1 => dout_qvf(1) , + o_im_2 => dout_qvf(2) , + o_im_3 => dout_qvf(3) , + o_im_4 => dout_qvf(4) , + o_im_5 => dout_qvf(5) , + o_im_6 => dout_qvf(6) , + o_im_7 => dout_qvf(7) , + o_valid(0) => o_axis_tvalid , + o_scale => o_scale + ); + +-- Assign outputs. +m_axis_tdata <= o_axis_tdata; +m_axis_tlast <= o_axis_tlast; +m_axis_tvalid <= o_axis_tvalid; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/tb.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/tb.vhd new file mode 100644 index 0000000..ef0ef03 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/tb.vhd @@ -0,0 +1,251 @@ +-- %%%%%%%%%%%%%%%%%%% Test Description %%%%%%%%%%%%%%%%%%%%% +-- +-- This test is for understanding if moving tvalid makes the +-- block to generate incorrect tlast at the output. +-- +-- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_TEXTIO.ALL; +use STD.TEXTIO.ALL; + +entity tb is +end tb; + +architecture rtl of tb is + +-- DUT. +component ssrfft_8x32_sync is + Generic + ( + NFFT : Integer := 16; + SSR : Integer := 4; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (2*SSR*B-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end component; + +constant NFFT : Integer := 32; +constant SSR : Integer := 8; +constant B : Integer := 16; + +signal aresetn : std_logic; +signal aclk : std_logic; +signal s_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0) := (others => '0'); +signal s_axis_tlast : std_logic := '0'; +signal s_axis_tvalid : std_logic := '0'; + +signal m_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); +signal m_axis_tlast : std_logic; +signal m_axis_tvalid : std_logic; + +signal SCALE_REG : std_logic_vector (31 downto 0) := (others => '0'); +signal QOUT_REG : std_logic_vector (31 downto 0) := std_logic_vector(to_unsigned(0,32)); + +-- TB control. +signal rd_start : std_logic := '0'; + +signal i_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); + +signal o_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); + +begin + +-- DUT. +DUT : ssrfft_8x32_sync + Generic map + ( + NFFT => NFFT , + SSR => SSR , + B => B + ) + Port map + ( + -- Reset and clock. + aresetn => aresetn , + aclk => aclk , + + -- AXIS Slave. + s_axis_tdata => s_axis_tdata , + s_axis_tlast => s_axis_tlast , + s_axis_tvalid => s_axis_tvalid , + + -- AXIS Master. + m_axis_tdata => m_axis_tdata , + m_axis_tlast => m_axis_tlast , + m_axis_tvalid => m_axis_tvalid , + + -- Registers. + SCALE_REG => SCALE_REG , + QOUT_REG => QOUT_REG + ); + +-- Input data. +s_axis_tdata <= i_im_7 & i_im_6 & i_im_5 & i_im_4 & i_im_3 & i_im_2 & i_im_1 & i_im_0 & i_re_7 & i_re_6 & i_re_5 & i_re_4 & i_re_3 & i_re_2 & i_re_1 & i_re_0; + +-- Output data. +o_re_0 <= m_axis_tdata (1*B-1 downto 0*B); +o_re_1 <= m_axis_tdata (2*B-1 downto 1*B); +o_re_2 <= m_axis_tdata (3*B-1 downto 2*B); +o_re_3 <= m_axis_tdata (4*B-1 downto 3*B); +o_re_4 <= m_axis_tdata (5*B-1 downto 4*B); +o_re_5 <= m_axis_tdata (6*B-1 downto 5*B); +o_re_6 <= m_axis_tdata (7*B-1 downto 6*B); +o_re_7 <= m_axis_tdata (8*B-1 downto 7*B); +o_im_0 <= m_axis_tdata (9*B-1 downto 8*B); +o_im_1 <= m_axis_tdata (10*B-1 downto 9*B); +o_im_2 <= m_axis_tdata (11*B-1 downto 10*B); +o_im_3 <= m_axis_tdata (12*B-1 downto 11*B); +o_im_4 <= m_axis_tdata (13*B-1 downto 12*B); +o_im_5 <= m_axis_tdata (14*B-1 downto 13*B); +o_im_6 <= m_axis_tdata (15*B-1 downto 14*B); +o_im_7 <= m_axis_tdata (16*B-1 downto 15*B); + +-- Main TB. +process +begin + aresetn <= '0'; + wait for 250 ns; + aresetn <= '1'; + + wait for 3 us; + + rd_start <= '1'; + wait for 110 ns; + rd_start <= '0'; + wait for 220 ns; + rd_start <= '1'; + wait for 490 ns; + rd_start <= '0'; + wait for 100 ns; + rd_start <= '1'; + + wait for 20 us; + +end process; + +-- Data process. +process + variable I : Integer := 0; + + begin + + for K in 0 to 200 loop + for J in 0 to 2 loop + while rd_start = '0' loop + wait until rising_edge(aclk); + s_axis_tvalid <= '0'; + end loop; + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + i_re_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + + I := I + 1; + end loop; + + while rd_start = '0' loop + wait until rising_edge(aclk); + s_axis_tvalid <= '0'; + end loop; + wait until rising_edge(aclk); + s_axis_tlast <= '1'; + s_axis_tvalid <= '1'; + i_re_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + + I := I + 1; + end loop; + +end process; + +-- Clock. +process +begin + aclk <= '0'; + wait for 5 ns; + aclk <= '1'; + wait for 5 ns; +end process; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/tlast_gen.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/tlast_gen.vhd new file mode 100644 index 0000000..c07cb2e --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fft/tlast_gen.vhd @@ -0,0 +1,61 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity tlast_gen is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4 + ); + Port + ( + -- Input reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Input enable. + en : in std_logic; + + -- TLAST input/output. + o_tlast : out std_logic + ); +end entity; + +architecture rtl of tlast_gen is + +-- Number of transactions. +constant NTRAN : Integer := NFFT/SSR; +constant NTRAN_LOG2 : Integer := Integer(ceil(log2(real(NTRAN)))); + +-- Counter for transactions. +signal cnt : unsigned (NTRAN_LOG2-1 downto 0); + +begin + +-- Registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + cnt <= (others => '0'); + else + if ( en = '1' ) then + if ( cnt < to_unsigned(NTRAN-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + end if; + end if; + end if; + end if; +end process; + +-- Assign outputs. +o_tlast <= '1' when cnt = to_unsigned(NTRAN-1,cnt'length) else + '0'; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/bin2gray.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/bin2gray.vhd new file mode 100644 index 0000000..4ecc09b --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/bin2gray.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end bin2gray; + +architecture rtl of bin2gray is + +signal gray : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +gray(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + gray(I) <= din(I+1) xor din(I); +end generate; + +-- Assign output. +dout <= gray; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/bram_dp.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/bram_dp.vhd new file mode 100644 index 0000000..d57aad1 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/bram_dp.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture rtl of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/bram_simple_dp.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/bram_simple_dp.vhd new file mode 100644 index 0000000..1494332 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/bram_simple_dp.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_simple_dp; + +architecture rtl of bram_simple_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo.vhd new file mode 100644 index 0000000..957362b --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture rtl of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Dual port, single clock BRAM. +component bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- FIFO memory. +mem_i : bram_simple_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo_axi.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo_dc.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/gray2bin.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/rd2axi.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/Makefile b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/Makefile new file mode 100644 index 0000000..df6451c --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/Makefile @@ -0,0 +1,21 @@ +all: ipgen copy sedxci clean_proj + +ipgen: fir.tcl + vivado -mode batch -source tcl/ipgen.tcl + +copy: + cp -r `find ./ipgen/ipgen.srcs -type d -name "fir*"` . + cp -r `find ./ipgen/ipgen.gen -name "fir_0.veo"` . + +sedxci: + sed -i -r 's#(../)+(coef/fir.*.coe)#../\2#' `find . -name "fir*.xci"` + +fir.tcl: tcl/fir.tcl.template + ./gen.pl tcl/fir.tcl.template + +clean: clean_proj + rm -rf `find . -type d -name "fir*"` + rm -rf fir*.veo fir.tcl add.tcl + +clean_proj: + rm -rf ipgen vivado* diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/add.tcl b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/add.tcl new file mode 100644 index 0000000..9523c5d --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/add.tcl @@ -0,0 +1,8 @@ +add_files ./fir/fir_0/fir_0.xci +add_files ./fir/fir_1/fir_1.xci +add_files ./fir/fir_2/fir_2.xci +add_files ./fir/fir_3/fir_3.xci +add_files ./fir/fir_4/fir_4.xci +add_files ./fir/fir_5/fir_5.xci +add_files ./fir/fir_6/fir_6.xci +add_files ./fir/fir_7/fir_7.xci diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_0.coe b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_0.coe new file mode 100644 index 0000000..e8a9cad --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_0.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -2,12,-50,16384,51,-12,2,0,-8,57,-245,16372,260,-61,9,0,-14,100,-430,16346,478,-112,17,0,-20,141,-606,16305,705,-165,26,-1,-25,179,-772,16249,941,-220,35,-1,-30,215,-929,16178,1186,-278,44,-1,-34,248,-1076,16092,1439,-337,54,-2,-38,279,-1214,15992,1701,-399,65,-2,-41,308,-1343,15878,1971,-462,76,-3,-44,334,-1462,15750,2248,-526,87,-3,-46,358,-1571,15607,2534,-592,99,-4,-48,379,-1672,15452,2826,-660,112,-5,-50,399,-1763,15283,3126,-728,125,-6,-51,416,-1846,15101,3432,-798,138,-6,-52,431,-1920,14906,3745,-868,152,-7,-53,443,-1985,14699,4063,-939,166,-8,-53,454,-2042,14480,4387,-1011,180,-10,-53,463,-2090,14250,4715,-1082,195,-11,-53,469,-2131,14009,5049,-1154,210,-12,-53,474,-2164,13757,5386,-1226,225,-13,-52,477,-2189,13495,5727,-1297,240,-15,-51,479,-2207,13224,6072,-1368,255,-16,-50,479,-2218,12943,6419,-1438,270,-18,-49,477,-2222,12654,6768,-1506,286,-19,-48,474,-2220,12356,7119,-1573,301,-21,-47,469,-2212,12051,7471,-1639,316,-23,-45,463,-2198,11739,7824,-1702,331,-24,-43,456,-2178,11420,8177,-1763,346,-26,-42,448,-2152,11096,8529,-1822,360,-28,-40,439,-2122,10766,8880,-1878,374,-30,-38,429,-2087,10431,9229,-1931,387,-32,-36,418,-2047,10092,9576,-1980,400,-34 \ No newline at end of file diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_1.coe b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_1.coe new file mode 100644 index 0000000..7aecf75 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_1.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -34,406,-2004,9749,9921,-2026,412,-35,-33,393,-1956,9403,10262,-2068,423,-37,-31,380,-1905,9055,10599,-2105,434,-39,-29,367,-1850,8704,10931,-2138,444,-41,-27,353,-1793,8353,11259,-2166,452,-43,-25,338,-1733,8000,11580,-2188,460,-44,-23,324,-1671,7647,11896,-2205,466,-46,-22,309,-1606,7295,12205,-2217,472,-47,-20,293,-1540,6944,12506,-2222,475,-49,-18,278,-1472,6593,12799,-2221,478,-50,-17,263,-1403,6245,13085,-2213,479,-51,-15,247,-1333,5899,13361,-2199,478,-52,-14,232,-1262,5556,13628,-2177,476,-53,-13,217,-1190,5217,13884,-2148,472,-53,-11,202,-1118,4881,14131,-2111,466,-53,-10,187,-1047,4550,14367,-2067,458,-53,-9,173,-975,4224,14591,-2014,449,-53,-8,159,-904,3903,14804,-1953,437,-53,-7,145,-833,3588,15005,-1884,423,-52,-6,131,-763,3278,15193,-1806,407,-51,-5,118,-694,2975,15369,-1719,389,-49,-4,105,-626,2679,15531,-1623,369,-47,-4,93,-559,2390,15680,-1518,346,-45,-3,81,-494,2109,15815,-1403,321,-42,-3,70,-430,1835,15937,-1280,294,-39,-2,59,-368,1569,16044,-1147,264,-36,-2,49,-307,1311,16137,-1004,232,-32,-1,39,-249,1062,16215,-852,197,-28,-1,30,-193,822,16279,-690,160,-23,-1,21,-138,590,16327,-519,121,-17,0,13,-86,367,16361,-339,79,-11,0,5,-36,154,16380,-149,35,-5 \ No newline at end of file diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_2.coe b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_2.coe new file mode 100644 index 0000000..96cdeb0 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_2.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -3,23,-100,16382,102,-24,4,0,-10,68,-292,16367,313,-73,11,0,-16,110,-475,16337,534,-125,19,0,-21,151,-649,16292,763,-179,28,-1,-26,188,-813,16232,1001,-235,37,-1,-31,223,-967,16158,1248,-293,47,-1,-35,256,-1112,16069,1504,-352,57,-2,-39,287,-1247,15965,1768,-414,67,-2,-42,315,-1373,15847,2039,-478,79,-3,-44,340,-1490,15715,2319,-542,90,-4,-47,363,-1597,15570,2606,-609,102,-4,-49,384,-1695,15411,2901,-677,115,-5,-50,403,-1785,15238,3202,-745,128,-6,-52,420,-1865,15053,3510,-815,141,-7,-52,434,-1937,14855,3824,-886,155,-8,-53,446,-2000,14646,4143,-957,169,-9,-53,456,-2054,14424,4468,-1029,184,-10,-53,464,-2101,14191,4798,-1100,198,-11,-53,471,-2140,13947,5133,-1172,213,-12,-53,475,-2171,13693,5471,-1244,228,-14,-52,478,-2194,13428,5813,-1315,244,-15,-51,479,-2211,13154,6158,-1385,259,-17,-50,478,-2220,12872,6506,-1455,274,-18,-49,476,-2223,12580,6856,-1523,290,-20,-48,473,-2219,12281,7207,-1590,305,-21,-46,468,-2209,11974,7559,-1655,320,-23,-45,462,-2193,11660,7912,-1718,335,-25,-43,454,-2172,11340,8265,-1778,349,-27,-41,446,-2145,11014,8617,-1836,363,-28,-40,436,-2114,10682,8967,-1892,377,-30,-38,426,-2077,10346,9316,-1943,390,-32,-36,415,-2037,10006,9663,-1992,403,-34 \ No newline at end of file diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_3.coe b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_3.coe new file mode 100644 index 0000000..6a67668 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_3.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = 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\ No newline at end of file diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_4.coe b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_4.coe new file mode 100644 index 0000000..369ba04 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_4.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -5,35,-149,16380,154,-36,5,0,-11,79,-339,16361,367,-86,13,0,-17,121,-519,16327,590,-138,21,-1,-23,160,-690,16279,822,-193,30,-1,-28,197,-852,16215,1062,-249,39,-1,-32,232,-1004,16137,1311,-307,49,-2,-36,264,-1147,16044,1569,-368,59,-2,-39,294,-1280,15937,1835,-430,70,-3,-42,321,-1403,15815,2109,-494,81,-3,-45,346,-1518,15680,2390,-559,93,-4,-47,369,-1623,15531,2679,-626,105,-4,-49,389,-1719,15369,2975,-694,118,-5,-51,407,-1806,15193,3278,-763,131,-6,-52,423,-1884,15005,3588,-833,145,-7,-53,437,-1953,14804,3903,-904,159,-8,-53,449,-2014,14591,4224,-975,173,-9,-53,458,-2067,14367,4550,-1047,187,-10,-53,466,-2111,14131,4881,-1118,202,-11,-53,472,-2148,13884,5217,-1190,217,-13,-53,476,-2177,13628,5556,-1262,232,-14,-52,478,-2199,13361,5899,-1333,247,-15,-51,479,-2213,13085,6245,-1403,263,-17,-50,478,-2221,12799,6593,-1472,278,-18,-49,475,-2222,12506,6944,-1540,293,-20,-47,472,-2217,12205,7295,-1606,309,-22,-46,466,-2205,11896,7647,-1671,324,-23,-44,460,-2188,11580,8000,-1733,338,-25,-43,452,-2166,11259,8353,-1793,353,-27,-41,444,-2138,10931,8704,-1850,367,-29,-39,434,-2105,10599,9055,-1905,380,-31,-37,423,-2068,10262,9403,-1956,393,-33,-35,412,-2026,9921,9749,-2004,406,-34 \ No newline at end of file diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_5.coe b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_5.coe new file mode 100644 index 0000000..2fc62d0 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_5.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = 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\ No newline at end of file diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_6.coe b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_6.coe new file mode 100644 index 0000000..ac9e2a2 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_6.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = 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\ No newline at end of file diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_7.coe b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_7.coe new file mode 100644 index 0000000..e732530 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_7.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -33,397,-1968,9490,10177,-2058,420,-37,-31,384,-1918,9142,10515,-2096,431,-39,-29,370,-1864,8792,10849,-2130,441,-40,-28,356,-1808,8441,11177,-2159,450,-42,-26,342,-1748,8088,11501,-2183,458,-44,-24,327,-1686,7736,11818,-2202,465,-45,-22,312,-1622,7383,12128,-2215,470,-47,-21,297,-1557,7031,12431,-2221,475,-48,-19,282,-1489,6681,12727,-2222,477,-50,-17,267,-1420,6332,13014,-2216,479,-51,-16,251,-1350,5985,13293,-2203,479,-52,-14,236,-1279,5642,13562,-2183,477,-52,-13,221,-1208,5302,13821,-2156,473,-53,-12,206,-1136,4965,14070,-2121,468,-53,-10,191,-1065,4633,14309,-2079,461,-53,-9,176,-993,4305,14536,-2028,451,-53,-8,162,-921,3983,14752,-1969,440,-53,-7,148,-850,3666,14956,-1902,427,-52,-6,135,-780,3355,15147,-1826,412,-51,-5,121,-711,3050,15326,-1741,394,-50,-5,109,-643,2753,15492,-1647,374,-48,-4,96,-575,2462,15644,-1545,352,-46,-3,84,-510,2178,15783,-1433,328,-43,-3,73,-446,1902,15908,-1311,301,-40,-2,62,-383,1635,16019,-1181,272,-37,-2,52,-322,1375,16115,-1041,240,-33,-1,42,-263,1124,16197,-891,206,-29,-1,32,-206,881,16264,-732,170,-24,-1,23,-152,647,16316,-563,131,-19,0,15,-99,422,16354,-385,90,-13,0,7,-48,206,16376,-197,46,-7,0,0,0,0,16384,0,0,0 \ No newline at end of file diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir.tcl b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir.tcl new file mode 100644 index 0000000..7d82aaf --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir.tcl @@ -0,0 +1,256 @@ +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_0 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_0.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_0] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_1 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_1.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_1] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_2 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_2.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_2] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_3 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_3.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_3] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_4 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_4.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_4] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_5 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_5.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_5] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_6 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_6.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_6] +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_7 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfba_pr_4x256_v1/src/fir/coef/fir_7.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_7] diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_0.veo b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_0.veo new file mode 100644 index 0000000..b2d1d6f --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_0.veo @@ -0,0 +1,80 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fir_compiler:7.2 +// IP Revision: 18 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fir_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready + .s_axis_data_tlast(s_axis_data_tlast), // input wire s_axis_data_tlast + .s_axis_data_tdata(s_axis_data_tdata), // input wire [31 : 0] s_axis_data_tdata + .s_axis_config_tvalid(s_axis_config_tvalid), // input wire s_axis_config_tvalid + .s_axis_config_tready(s_axis_config_tready), // output wire s_axis_config_tready + .s_axis_config_tlast(s_axis_config_tlast), // input wire s_axis_config_tlast + .s_axis_config_tdata(s_axis_config_tdata), // input wire [7 : 0] s_axis_config_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tlast(m_axis_data_tlast), // output wire m_axis_data_tlast + .m_axis_data_tdata(m_axis_data_tdata), // output wire [31 : 0] m_axis_data_tdata + .event_s_data_tlast_missing(event_s_data_tlast_missing), // output wire event_s_data_tlast_missing + .event_s_data_tlast_unexpected(event_s_data_tlast_unexpected), // output wire event_s_data_tlast_unexpected + .event_s_config_tlast_missing(event_s_config_tlast_missing), // output wire event_s_config_tlast_missing + .event_s_config_tlast_unexpected(event_s_config_tlast_unexpected) // output wire event_s_config_tlast_unexpected +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fir_0.v when simulating +// the core, fir_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_0/fir_0.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_0/fir_0.xci new file mode 100644 index 0000000..db459c2 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_0/fir_0.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_0.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_0 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_0.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_0 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfba_pr_4x256_v1_v1_0_project/axis_pfba_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_0 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_1/fir_1.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_1/fir_1.xci new file mode 100644 index 0000000..c9d7b7d --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_1/fir_1.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_1 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_1.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_1 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_1.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_1 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfba_pr_4x256_v1_v1_0_project/axis_pfba_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_1 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_2/fir_2.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_2/fir_2.xci new file mode 100644 index 0000000..eccedac --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_2/fir_2.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_2 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_2.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_2 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_2.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_2 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfba_pr_4x256_v1_v1_0_project/axis_pfba_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_2 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_3/fir_3.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_3/fir_3.xci new file mode 100644 index 0000000..c14a39b --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_3/fir_3.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_3 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_3.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_3 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_3.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_3 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfba_pr_4x256_v1_v1_0_project/axis_pfba_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_3 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_4/fir_4.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_4/fir_4.xci new file mode 100644 index 0000000..b084bdf --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_4/fir_4.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_4 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_4.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_4 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_4.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_4 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfba_pr_4x256_v1_v1_0_project/axis_pfba_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_4 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_5/fir_5.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_5/fir_5.xci new file mode 100644 index 0000000..d8f3747 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_5/fir_5.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_5 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_5.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_5 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_5.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_5 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfba_pr_4x256_v1_v1_0_project/axis_pfba_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_5 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_6/fir_6.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_6/fir_6.xci new file mode 100644 index 0000000..b2c12a7 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_6/fir_6.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_6 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_6.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_6 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_6.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_6 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfba_pr_4x256_v1_v1_0_project/axis_pfba_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_6 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_7/fir_7.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_7/fir_7.xci new file mode 100644 index 0000000..37996fc --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/fir_7/fir_7.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_7 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31 + 31,31 + fixed + fir_7.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_7 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_7.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_7 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfba_pr_4x256_v1_v1_0_project/axis_pfba_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_7 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/gen.pl b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/gen.pl new file mode 100644 index 0000000..deba046 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/gen.pl @@ -0,0 +1,30 @@ +#!/usr/bin/perl +# This file generates the fir.tcl file to be run from vivado. +# Copy fir coefficient files. One IP per .coe file will be created. +# Copy generated .xci files to avoid generating FIR cores every time. + +open(my $file, "$ARGV[0]") or die "Could not open file '$ARGV[0]' $!"; +my @lines = <$file>; + +open(my $out_tcl, ">", "fir.tcl") or die "Could not open file fir.tcl $!"; +open(my $out_add, ">", "add.tcl") or die "Could not open file fir.tcl $!"; + +@out = `ls coef/*.coe`; +foreach (@out) +{ + chomp($_); + $fir = $_; + $fir =~ s/coef\///g; + $fir =~ s/.coe//g; + + print $out_add ("add_files ./fir/$fir/$fir.xci\n"); + + foreach my $line (@lines) + { + my $temp = $line; + chomp($temp); + $temp =~ s//$fir/g; + print $out_tcl ("$temp\n"); + } +} + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/tcl/fir.tcl.template b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/tcl/fir.tcl.template new file mode 100644 index 0000000..c35fdf9 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/tcl/fir.tcl.template @@ -0,0 +1,32 @@ +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfba_pr_4x256_v1/src/fir/coef/.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips ] diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/tcl/ipgen.tcl b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/tcl/ipgen.tcl new file mode 100644 index 0000000..e1a3705 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/fir/tcl/ipgen.tcl @@ -0,0 +1,13 @@ +# Create project. +create_project ipgen ./ipgen -part xczu49dr-ffvf1760-2-e + +# Set language options. +set_property simulator_language Mixed [current_project] +set_property target_language Verilog [current_project] + +# Create IPs. +source fir.tcl + +# Generate instantiation templates. +generate_target instantiation_template [get_ips *] + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/firs.sv b/firmware/ip/axis_pfba_pr_4x256_v1/src/firs.sv new file mode 100644 index 0000000..c7f296c --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/firs.sv @@ -0,0 +1,312 @@ +module firs + ( + // Reset and clock. + aresetn , + aclk , + + // S_AXIS for input data. + s_axis_tready , + s_axis_tvalid , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tlast , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of channels. +parameter N = 32; + +// Number of Lanes (Input). +parameter L = 4; + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [L*32-1:0] s_axis_tdata; + +output m_axis_tvalid; +output m_axis_tlast; +output [2*L*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// FIR Configuration interface. +wire config_tvalid; +wire config_tready; +wire config_tlast; +wire[7:0] config_tdata; + +// Framing. +wire fr_sync; +wire fr_out; + +// Input delay. +wire[L*32-1:0] data_d; +reg [31:0] data_r1_v[0:L-1]; +reg [31:0] data_r2_v[0:L-1]; + +// Valid input. +reg valid_r; + +// FIR outputs. +wire[31:0] dout_v [0:2*L-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i '0'); + + else + -- State register. + current_state <= next_state; + + -- Counter for config. + if ( cfg_cnt_en = '1' ) then + cfg_cnt <= cfg_cnt + 1; + end if; + + end if; + end if; +end process; + +-- tlast. +tlast_i <= '1' when cfg_cnt = to_unsigned(N-1,cfg_cnt'length) else + '0'; + +-- Next state logic. +process (current_state, cfg_en, tready, cfg_cnt) +begin + case current_state is + when INIT_ST => + if ( cfg_en = '1' and tready = '1' ) then + next_state <= CNT_ST; + else + next_state <= INIT_ST; + end if; + + when CNT_ST => + if ( cfg_cnt = to_unsigned(N-1,cfg_cnt'length) ) then + next_state <= END_ST; + else + next_state <= CNT_ST; + end if; + + when END_ST => + if ( cfg_en = '1' ) then + next_state <= END_ST; + else + next_state <= INIT_ST; + end if; + + end case; +end process; + +-- Output logic. +process (current_state) +begin +cfg_cnt_en <= '0'; + case current_state is + when INIT_ST => + + when CNT_ST=> + cfg_cnt_en <= '1'; + + when END_ST => + + end case; +end process; + +-- Assign outputs. +tvalid <= cfg_cnt_en; +tlast <= tlast_i; +tdata <= std_logic_vector (cfg_cnt); + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_ctrl.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_ctrl.vhd new file mode 100644 index 0000000..24bd0a2 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_ctrl.vhd @@ -0,0 +1,113 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use WORK.pfb_ctrl_pkg.ALL; + +entity pfb_ctrl is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + aresetn : in std_logic; + aclk : in std_logic; + + -- M_AXIS for Configuration. + m_axis_config_tvalid : out std_logic; + m_axis_config_tready : in std_logic; + m_axis_config_tlast : out std_logic; + m_axis_config_tdata : out std_logic_vector (7 downto 0); + + -- Filter config. + cfg_en : in std_logic; + + -- Framing. + tready : in std_logic; + tvalid : in std_logic; + fr_sync : in std_logic; + fr_out : out std_logic + ); +end pfb_ctrl; + +architecture rtl of pfb_ctrl is + +-- PFB configuration. +component pfb_cfg is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Filter config. + cfg_en : in std_logic; + tready : in std_logic; + tvalid : out std_logic; + tlast : out std_logic; + tdata : out std_logic_vector (f_nbit_axis(N)-1 downto 0) + ); +end component; + +-- PFB framing. +component pfb_framing is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Framing. + tready : in std_logic; + tvalid : in std_logic; + fr_sync : in std_logic; + fr_out : out std_logic + ); +end component; + +begin + +-- PFB configuration. +cfg_i : pfb_cfg + Generic map ( + -- Number of channels. + N => N + ) + Port map ( + -- Reset and clock. + rstn => aresetn , + clk => aclk , + + -- Filter config. + cfg_en => cfg_en , + tready => m_axis_config_tready , + tvalid => m_axis_config_tvalid , + tlast => m_axis_config_tlast , + tdata => m_axis_config_tdata + ); + +-- PFB framing. +framing_i : pfb_framing + Generic map ( + -- Number of channels. + N => N + ) + Port map ( + -- Reset and clock. + rstn => aresetn , + clk => aclk , + + -- Framing. + tready => tready , + tvalid => tvalid , + fr_sync => fr_sync , + fr_out => fr_out + ); + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_ctrl_pkg.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_ctrl_pkg.vhd new file mode 100644 index 0000000..db99fb3 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_ctrl_pkg.vhd @@ -0,0 +1,38 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +package pfb_ctrl_pkg is + + -- Functions. + function f_nbit_axis (ARG: Integer) return Integer; + +end pfb_ctrl_pkg; + +package body pfb_ctrl_pkg is + + function f_nbit_axis (ARG: Integer) return Integer is + -- Function variables. + variable arg_log2 : Integer := Integer(ceil(log2(real(ARG)))); + variable tmp : Integer; + + begin + + if (arg_log2 <= 8 ) then + tmp := 8; + elsif ( arg_log2 <= 16 ) then + tmp := 16; + elsif ( arg_log2 <= 24 ) then + tmp := 24; + elsif ( arg_log2 <= 32 ) then + tmp := 32; + else + tmp := -1; + end if; + + return tmp; + end; + +end package body pfb_ctrl_pkg; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_framing.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_framing.vhd new file mode 100644 index 0000000..5ff7e74 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_framing.vhd @@ -0,0 +1,137 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity pfb_framing is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Framing. + tready : in std_logic; + tvalid : in std_logic; + fr_sync : in std_logic; + fr_out : out std_logic + ); +end pfb_framing; + +architecture rtl of pfb_framing is + +-- Number of bits of N. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Wait value. +constant WAIT_C : Integer := 10*N; +constant WAIT_C_LOG2 : Integer := Integer(ceil(log2(real(WAIT_C)))); + +-- FSM. +type fsm_type is ( INIT_ST , + SHIFT_ST , + WAIT_ST ); + +signal current_state, next_state : fsm_type; + +-- Free running counter for framing. +signal fr_cnt : unsigned (N_LOG2-1 downto 0); +signal fr_cnt_en : std_logic; + +-- Counter for waiting until next calibration. +signal wait_cnt : unsigned (WAIT_C_LOG2-1 downto 0); +signal wait_cnt_en : std_logic; + +-- Framing sync. +signal fr_i : std_logic; + +begin + +-- Registers. +process(clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + -- State register. + current_state <= INIT_ST; + + -- Counters. + fr_cnt <= (others => '0'); + wait_cnt <= (others => '0'); + else + -- State register. + current_state <= next_state; + + -- Counters. + if ( fr_cnt_en = '1' and tready = '1' and tvalid = '1' ) then + if ( fr_cnt < to_unsigned(N-1,fr_cnt'length) ) then + fr_cnt <= fr_cnt + 1; + else + fr_cnt <= (others => '0'); + end if; + end if; + if ( wait_cnt_en = '1' ) then + if ( wait_cnt < to_unsigned(WAIT_C-1,wait_cnt'length) ) then + wait_cnt <= wait_cnt + 1; + else + wait_cnt <= (others => '0'); + end if; + end if; + + end if; + end if; +end process; + +-- Framing sync. +fr_i <= '1' when fr_cnt = to_unsigned(N-1,fr_cnt'length) else + '0'; + +-- Next state logic. +process (current_state, fr_sync, wait_cnt) +begin + case current_state is + when INIT_ST => + if ( fr_sync = '0' ) then + next_state <= INIT_ST; + else + next_state <= SHIFT_ST; + end if; + + when SHIFT_ST => + next_state <= WAIT_ST; + + when WAIT_ST => + if ( wait_cnt = to_unsigned(WAIT_C-1,wait_cnt'length) ) then + next_state <= INIT_ST; + else + next_state <= WAIT_ST; + end if; + end case; +end process; + +-- Output logic. +process (current_state) +begin +fr_cnt_en <= '0'; +wait_cnt_en <= '0'; + case current_state is + when INIT_ST => + fr_cnt_en <= '1'; + + when SHIFT_ST => + + when WAIT_ST => + fr_cnt_en <= '1'; + wait_cnt_en <= '1'; + + end case; +end process; + +-- Assign outputs. +fr_out <= fr_i; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_reorder.sv b/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_reorder.sv new file mode 100644 index 0000000..2541b11 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/pfb_reorder.sv @@ -0,0 +1,132 @@ +// This block reorders PFB output to get it ready for the +// SSR FFT. +module pfb_reorder + ( + // Reset and clock. + aresetn , + aclk , + + // S_AXIS for input data. + s_axis_tvalid , + s_axis_tlast , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tlast , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Bits. +parameter B = 32; + +// Number of Lanes. +parameter L = 4; + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +input s_axis_tvalid; +input s_axis_tlast; +input [2*L*B-1:0] s_axis_tdata; + +output m_axis_tvalid; +output m_axis_tlast; +output [2*L*B-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Sorted input data. +wire [2*L*B-1:0] din_sort; + +// Data registers. +reg [2*L*B-1:0] data_r1; +reg [2*L*B-1:0] data_r2; +reg [2*L*B-1:0] data_r3; +reg [2*L*B-1:0] data_r4; + +// Tlast registers. +reg last_r1; +reg last_r2; +reg last_r3; + +// Low/High data. +wire [2*L*B-1:0] dlow; +wire [2*L*B-1:0] dhigh; + +// Muxed output. +reg sel = 0; +wire [2*L*B-1:0] dmux; + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i NBITS+1 , + + -- Fifo depth. + N => 4 + ) + Port map + ( + rstn => aresetn , + clk => aclk , + + -- Write I/F. + wr_en => s_axis_tvalid , + din => fifo_din , + + -- Read I/F. + rd_en => m_axis_tready , + dout => fifo_dout , + + -- Flags. + full => fifo_full , + empty => fifo_empty + ); + +-- Fifo connections. +fifo_din <= s_axis_tlast & s_axis_tdata; +s_axis_tready <= not(fifo_full); + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( aresetn = '0' ) then + -- Pipeline registers. + d_r <= (others => '0'); + d_rr <= (others => '0'); + empty_r <= '1'; + empty_rr <= '1'; + last_r <= '0'; + last_rr <= '0'; + + -- sel register. + cnt <= (others => '0'); + sel <= (others => '0'); + else + -- Pipeline registers. + d_r <= d_i; + d_rr <= d_mux; + empty_r <= fifo_empty; + empty_rr <= empty_r; + last_r <= last_i; + last_rr <= last_r; + + -- sel register: if reading and not empty, count. + if ( m_axis_tready = '1' and empty_r = '0' ) then + if ( cnt < to_unsigned(T-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + sel <= sel + 1; + end if; + end if; + + end if; + end if; +end process; + +-- Input data/tlast. +d_i <= fifo_dout(NBITS-1 downto 0); +last_i <= fifo_dout(NBITS); + +-- Slice input. +GEN_SLICE_IN: for I in 0 to L-1 generate + dv_i(I) <= signed(d_r ( 2*I*B+B-1 downto 2*I*B)); + dv_q(I) <= signed(d_r ( (2*I+1)*B+B-1 downto (2*I+1)*B)); +end generate GEN_SLICE_IN; + +-- Multiply by -1 only odd samples. +GEN_PM: for I in 0 to L/2-1 generate + -- Even samples: multiply always by 1. + dv_i_pm(2*I) <= dv_i(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_i_pm(2*I+1) <= to_signed(MAX_P,B) when dv_i(2*I+1) = to_signed(MIN_N,B) else + -dv_i(2*I+1); + + -- Even samples: multiply always by 1. + dv_q_pm(2*I) <= dv_q(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_q_pm(2*I+1) <= to_signed(MAX_P,B) when dv_q(2*I+1) = to_signed(MIN_N,B) else + -dv_q(2*I+1); +end generate GEN_PM; + +-- Combine signals back. +GEN_COMBINE_PM: for I in 0 to L-1 generate + d_pm ( 2*I*B+B-1 downto 2*I*B) <= std_logic_vector(dv_i_pm(I)); + d_pm ((2*I+1)*B+B-1 downto (2*I+1)*B) <= std_logic_vector(dv_q_pm(I)); +end generate GEN_COMBINE_PM; + +-- Data mux. +d_mux <= d_r when sel = to_unsigned(0,sel'length) else + d_pm; + + +-- Assign outputs. +m_axis_tdata <= d_rr; +m_axis_tlast <= last_rr; +m_axis_tvalid <= not(empty_rr); + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/tb/tb.sv b/firmware/ip/axis_pfba_pr_4x256_v1/src/tb/tb.sv new file mode 100644 index 0000000..d762ef5 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/tb/tb.sv @@ -0,0 +1,254 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +parameter L = 4; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +wire s_axis_tready; +reg s_axis_tvalid; +reg [4*32-1:0] s_axis_tdata; + +wire m_axis_tvalid; +wire m_axis_tlast; +reg [8*32-1:0] m_axis_tdata; + + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Input data. +reg [31:0] din_ii [0:7]; + +// Output data. +wire[31:0] dout_ii [0:2*L-1]; +wire[15:0] dout_real_ii [0:2*L-1]; +wire[15:0] dout_imag_ii [0:2*L-1]; + +// Test bench control. +reg tb_data = 0; +reg tb_data_done= 0; +reg tb_write_out= 0; + +generate +genvar ii; +for (ii = 0; ii < L; ii = ii + 1) begin + assign s_axis_tdata[32*ii +: 32] = din_ii[ii]; + assign dout_ii[ii] = m_axis_tdata[32*ii +: 32]; + assign dout_ii[ii+L] = m_axis_tdata[32*(ii+L) +: 32]; + assign dout_real_ii[ii] = m_axis_tdata[32*ii +: 16]; + assign dout_real_ii[ii+L] = m_axis_tdata[32*(ii+L) +: 16]; + assign dout_imag_ii[ii] = m_axis_tdata[32*ii+16 +: 16]; + assign dout_imag_ii[ii+L] = m_axis_tdata[32*(ii+L)+16 +: 16]; +end +endgenerate + +// axi_mst_0. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_pfba_pr_4x256_v1 + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk , + .s_axi_aresetn , + .s_axi_araddr , + .s_axi_arprot , + .s_axi_arready , + .s_axi_arvalid , + .s_axi_awaddr , + .s_axi_awprot , + .s_axi_awready , + .s_axi_awvalid , + .s_axi_bready , + .s_axi_bresp , + .s_axi_bvalid , + .s_axi_rdata , + .s_axi_rready , + .s_axi_rresp , + .s_axi_rvalid , + .s_axi_wdata , + .s_axi_wready , + .s_axi_wstrb , + .s_axi_wvalid , + + // s_* and m_* reset/clock. + .aresetn , + .aclk , + + // S_AXIS for data input. + .s_axis_tvalid , + .s_axis_tready , + .s_axis_tdata , + + // M_AXIS for data output. + .m_axis_tvalid , + .m_axis_tlast , + .m_axis_tdata + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + // QOUT_REG + data_wr = 8; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); + #10; + + // Wait until FIR framing is done. + #48000; + + // Start data. + tb_data <= 1; + #3500; + tb_write_out <= 1; + wait (tb_data_done); + tb_write_out <= 0; +end + +// Input data. +initial begin + int fd; + int i; + bit signed [15:0] vali, valq; + s_axis_tvalid <= 1; + + // Open file with Coefficients. + fd = $fopen("../../../../../tb/data_iq.txt","r"); + + wait(tb_data); + @(posedge aclk); + + i = 0; + while ($fscanf(fd,"%d,%d", vali, valq) == 2) begin + //$display("T = %d, i = %d, I = %d, Q = %d", $time, i, vali, valq); + din_ii[i] <= {valq,vali}; + i = i + 1; + if (i == L) begin + i = 0; + @(posedge aclk); + //s_axis_tvalid <= 1; + end + end + + @(posedge aclk); + //s_axis_tvalid <= 0; + tb_data_done <= 1; + +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d, imag_d; + + // Output file. + fd = $fopen("../../../../../tb/dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, last, real, imag"); + + wait (tb_write_out); + wait (m_axis_tlast); + wait (!m_axis_tlast); + + while (tb_write_out) begin + @(posedge aclk); + for (int i=0; i<2*L; i = i+1) begin + real_d = m_axis_tdata[32*i +: 16]; + imag_d = m_axis_tdata[32*i+16 +: 16]; + $fdisplay(fd,"%d,%d,%d,%d",m_axis_tvalid,m_axis_tlast,real_d,imag_d); + end + end + + $display("Closing file, t = %0t", $time); + $fclose(fd); +end + +always begin + s_axi_aclk <= 0; + #10; + s_axi_aclk <= 1; + #10; +end + +always begin + aclk <= 0; + #5; + aclk <= 1; + #5; +end + +endmodule + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/zn_nb.vhd b/firmware/ip/axis_pfba_pr_4x256_v1/src/zn_nb.vhd new file mode 100644 index 0000000..7846385 --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/zn_nb.vhd @@ -0,0 +1,59 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity zn_nb is + Generic + ( + -- Number of bits. + B : Integer := 16; + + -- Delay. + N : Integer := 4 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- S_AXIS for intput. + s_axis_tvalid : in std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + + -- M_AXIS for output. + m_axis_tvalid : out std_logic; + m_axis_tdata : out std_logic_vector(B-1 downto 0) + + ); +end zn_nb; + +architecture rtl of zn_nb is + +-- Shift register for data. +type reg_v is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal shift_reg_tdata : reg_v; + +begin + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( aresetn = '0' ) then + -- Shift registers. + shift_reg_tdata <= (others => (others => '0')); + else + if ( s_axis_tvalid = '1' ) then + shift_reg_tdata <= shift_reg_tdata (N-2 downto 0) & s_axis_tdata; + end if; + end if; + end if; +end process; + +-- Assign outputs. +m_axis_tdata <= shift_reg_tdata (N-1); +m_axis_tvalid <= s_axis_tvalid; + +end rtl; + diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/xgui/axis_pfba_pr_4x256_v1_v1_0.tcl b/firmware/ip/axis_pfba_pr_4x256_v1/xgui/axis_pfba_pr_4x256_v1_v1_0.tcl new file mode 100644 index 0000000..716ad7e --- /dev/null +++ b/firmware/ip/axis_pfba_pr_4x256_v1/xgui/axis_pfba_pr_4x256_v1_v1_0.tcl @@ -0,0 +1,24 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/README b/firmware/ip/axis_pfbs_pr_4x256_v1/README new file mode 100644 index 0000000..eb01445 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/README @@ -0,0 +1 @@ +This IP is a PFB for Synthesis and Perfect Reconstruction (cascaded). diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/component.xml b/firmware/ip/axis_pfbs_pr_4x256_v1/component.xml new file mode 100644 index 0000000..e623d03 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/component.xml @@ -0,0 +1,1334 @@ + + + user.org + user + axis_pfbs_pr_4x256_v1 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axis_pfbs_pr_4x256_v1 + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + e141cd30 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axis_pfbs_pr_4x256_v1 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + e141cd30 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 0891018f + + + + + + + s_axi_aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 255 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axis_tlast + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axis_tvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 127 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N + N + 256 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/fir/fir_7/fir_7.xci + xci + CELL_NAME_pfb_i/firs_i/fir7_i + + + src/fir/fir_6/fir_6.xci + xci + CELL_NAME_pfb_i/firs_i/fir6_i + + + src/fir/fir_5/fir_5.xci + xci + CELL_NAME_pfb_i/firs_i/fir5_i + + + src/fir/fir_4/fir_4.xci + xci + CELL_NAME_pfb_i/firs_i/fir4_i + + + src/fir/fir_3/fir_3.xci + xci + CELL_NAME_pfb_i/firs_i/fir3_i + + + src/fir/fir_2/fir_2.xci + xci + CELL_NAME_pfb_i/firs_i/fir2_i + + + src/fir/fir_1/fir_1.xci + xci + CELL_NAME_pfb_i/firs_i/fir1_i + + + src/fir/fir_0/fir_0.xci + xci + CELL_NAME_pfb_i/firs_i/fir0_i + + + src/fir/coef/fir_7.coe + coe + + + src/fir/coef/fir_6.coe + coe + + + src/fir/coef/fir_5.coe + coe + + + src/fir/coef/fir_4.coe + coe + + + src/fir/coef/fir_3.coe + coe + + + src/fir/coef/fir_2.coe + coe + + + src/fir/coef/fir_1.coe + coe + + + src/fir/coef/fir_0.coe + coe + + + src/pfb_switch.v + verilogSource + + + src/firs.sv + systemVerilogSource + + + src/pfb.sv + systemVerilogSource + + + src/pfb_conjugate.sv + systemVerilogSource + + + src/pfb_reorder.sv + systemVerilogSource + + + src/pfb_swap.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/conv_pkg.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/fft/framing.vhd + vhdlSource + + + src/pfb_ctrl_pkg.vhd + vhdlSource + + + src/pfb_cfg.vhd + vhdlSource + + + src/pfb_ctrl.vhd + vhdlSource + + + src/pfb_framing.vhd + vhdlSource + + + src/pimod_pfb.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/single_reg_w_init.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/srl33e.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/ssr_8x256.vhd + vhdlSource + + + src/fft/ssrfft_8x256_sync.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg_reg.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg_w_init.vhd + vhdlSource + + + src/fft/tlast_gen.vhd + vhdlSource + + + src/zn_nb.vhd + vhdlSource + + + src/axis_pfbs_pr_4x256_v1.sv + systemVerilogSource + CHECKSUM_50266a58 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/fir/fir_7/fir_7.xci + xci + CELL_NAME_pfb_i/firs_i/fir7_i + + + src/fir/fir_6/fir_6.xci + xci + CELL_NAME_pfb_i/firs_i/fir6_i + + + src/fir/fir_5/fir_5.xci + xci + CELL_NAME_pfb_i/firs_i/fir5_i + + + src/fir/fir_4/fir_4.xci + xci + CELL_NAME_pfb_i/firs_i/fir4_i + + + src/fir/fir_3/fir_3.xci + xci + CELL_NAME_pfb_i/firs_i/fir3_i + + + src/fir/fir_2/fir_2.xci + xci + CELL_NAME_pfb_i/firs_i/fir2_i + + + src/fir/fir_1/fir_1.xci + xci + CELL_NAME_pfb_i/firs_i/fir1_i + + + src/fir/fir_0/fir_0.xci + xci + CELL_NAME_pfb_i/firs_i/fir0_i + + + src/fir/coef/fir_7.coe + coe + + + src/fir/coef/fir_6.coe + coe + + + src/fir/coef/fir_5.coe + coe + + + src/fir/coef/fir_4.coe + coe + + + src/fir/coef/fir_3.coe + coe + + + src/fir/coef/fir_2.coe + coe + + + src/fir/coef/fir_1.coe + coe + + + src/fir/coef/fir_0.coe + coe + + + src/pfb_switch.v + verilogSource + + + src/firs.sv + systemVerilogSource + + + src/pfb.sv + systemVerilogSource + + + src/pfb_conjugate.sv + systemVerilogSource + + + src/pfb_reorder.sv + systemVerilogSource + + + src/pfb_swap.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/conv_pkg.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/fft/framing.vhd + vhdlSource + + + src/pfb_ctrl_pkg.vhd + vhdlSource + + + src/pfb_cfg.vhd + vhdlSource + + + src/pfb_ctrl.vhd + vhdlSource + + + src/pfb_framing.vhd + vhdlSource + + + src/pimod_pfb.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/single_reg_w_init.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/srl33e.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/ssr_8x256.vhd + vhdlSource + + + src/fft/ssrfft_8x256_sync.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg_reg.vhd + vhdlSource + + + src/fft/ssr_fft_8x256/synth_reg_w_init.vhd + vhdlSource + + + src/fft/tlast_gen.vhd + vhdlSource + + + src/zn_nb.vhd + vhdlSource + + + src/axis_pfbs_pr_4x256_v1.sv + systemVerilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_pfbs_pr_4x256_v1_v1_0.tcl + tclSource + CHECKSUM_0891018f + XGUI_VERSION_2 + + + + AXIS PFB 4 lanes, 256 Channels, 50 % Overlap, Perfect Reconstruction, V1. + + + Component_Name + axis_pfbs_pr_4x256_v1_v1_0 + + + N + N + 256 + + + + + + zynquplus + + + /UserIP + + AXIS PFBS PR 4x256 V1 + package_project + 4 + 2023-04-26T18:26:06Z + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 0000000..7cfbd51 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 8 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 0000000..a53be60 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 8 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..ac9cf04 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,200 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 0000000..8a5353a --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4760 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + ARSIZE + + + m_axi_arsize + + + + + ARUSER + + + m_axi_aruser + + + + + ARVALID + + + m_axi_arvalid + + + + + AWADDR + + + m_axi_awaddr + + + + + AWBURST + + + m_axi_awburst + + + + + AWCACHE + + + m_axi_awcache + + + + + AWID + + + m_axi_awid + + + + + AWLEN + + + m_axi_awlen + + + + + AWLOCK + + + m_axi_awlock + + + + + AWPROT + + + m_axi_awprot + + + + + AWQOS + + + m_axi_awqos + + + + + AWREADY + + + m_axi_awready + + + + + AWREGION + + + m_axi_awregion + + + + + AWSIZE + + + m_axi_awsize + + + + + AWUSER + + + m_axi_awuser + + + + + AWVALID + + + m_axi_awvalid + + + + + BID + + + m_axi_bid + + + + + BREADY + + + m_axi_bready + + + + + BRESP + + + m_axi_bresp + + + + + BUSER + + + m_axi_buser + + + + + BVALID + + + m_axi_bvalid + + + + + RDATA + + + m_axi_rdata + + + + + RID + + + m_axi_rid + + + + + RLAST + + + m_axi_rlast + + + + + RREADY + + + m_axi_rready + + + + + RRESP + + + m_axi_rresp + + + + + RUSER + + + m_axi_ruser + + + + + RVALID + + + m_axi_rvalid + + + + + WDATA + + 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0 + + + simulation.tlm + + + + + HAS_WSTRB + 1 + + + simulation.tlm + + + + + HAS_BRESP + 1 + + + simulation.tlm + + + + + HAS_RRESP + 1 + + + simulation.tlm + + + + + SUPPORTS_NARROW_BURST + 0 + + + simulation.tlm + + + + + NUM_READ_OUTSTANDING + 1 + + + simulation.tlm + + + + + NUM_WRITE_OUTSTANDING + 1 + + + simulation.tlm + + + + + MAX_BURST_LENGTH + 1 + + + simulation.tlm + + + + + PHASE + 0.000 + + + simulation.tlm + + + + + CLK_DOMAIN + + + + simulation.tlm + + + + + NUM_READ_THREADS + 1 + + + simulation.tlm + + + + + NUM_WRITE_THREADS + 1 + + + simulation.tlm + + + + + RUSER_BITS_PER_BYTE + 0 + + + simulation.tlm + + + + + WUSER_BITS_PER_BYTE + 0 + + + simulation.tlm + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + true + + + + + + S_AXI + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARBURST + + + s_axi_arburst + + + + + ARCACHE + + + s_axi_arcache + + + + + ARID + + + s_axi_arid + + + + + ARLEN + + + s_axi_arlen + + + + + ARLOCK + + + s_axi_arlock + + + + + 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std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rlast + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_ruser + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_rvalid + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rready + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + M_INITIATOR_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + wr_socket + + + width + 32 + + + + + + + 1 + + + + + M_INITIATOR_rd_socket + AXIMM Read Socket + AXIMM Socket for Read + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + rd_socket + + + width + 32 + + + + + + + 1 + + + + + S_TARGET_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + + + + + 1 + + + + + S_TARGET_rd_socket + AXIMM Read Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + + + + + 1 + + + + + + + C_AXI_PROTOCOL + 2 + + + C_AXI_INTERFACE_MODE + 0 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_WDATA_WIDTH + 32 + + + C_AXI_RDATA_WIDTH + 32 + + + C_AXI_WID_WIDTH + 0 + + + C_AXI_RID_WIDTH + 0 + + + C_AXI_AWUSER_WIDTH + 0 + + + C_AXI_ARUSER_WIDTH + 0 + + + C_AXI_WUSER_WIDTH + 0 + + + C_AXI_RUSER_WIDTH + 0 + + + C_AXI_BUSER_WIDTH + 0 + + + C_AXI_SUPPORTS_NARROW + 0 + + + C_AXI_HAS_BURST + 0 + + + C_AXI_HAS_LOCK + 0 + + + C_AXI_HAS_CACHE + 0 + + + C_AXI_HAS_REGION + 0 + + + C_AXI_HAS_PROT + 1 + + + C_AXI_HAS_QOS + 0 + + + C_AXI_HAS_WSTRB + 1 + + + C_AXI_HAS_BRESP + 1 + + + C_AXI_HAS_RRESP + 1 + + + C_AXI_HAS_ARESETN + 1 + + + + + + choice_list_04fafd91 + AXI3 + AXI4 + AXI4LITE + + + choice_list_6240decd + READ_ONLY + READ_WRITE + WRITE_ONLY + + + choice_list_642e7122 + MASTER + PASS_THROUGH + SLAVE + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_0fc128e8 + 0 + 0 + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi_mst_0.vho + vhdlTemplate + + + axi_mst_0.veo + verilogTemplate + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_8 + + + + xilinx_synthesisconstraints_view_fileset + + axi_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_8 + + + + xilinx_externalfiles_view_fileset + + axi_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axi_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axi_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_8 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_8 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_8 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 8 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_slv.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_slv.vhd new file mode 100644 index 0000000..6d4348a --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_slv.vhd @@ -0,0 +1,510 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + QOUT_REG : out std_logic_vector (31 downto 0) + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Output Registers. + QOUT_REG <= slv_reg0; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/axis_pfbs_pr_4x256_v1.sv b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axis_pfbs_pr_4x256_v1.sv new file mode 100644 index 0000000..1e76952 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axis_pfbs_pr_4x256_v1.sv @@ -0,0 +1,127 @@ +// Synthesis Polyphase Filter Bank, 4 lanes, 256 channels, 50 % overlap. +// This IP is good for cascading with the Analysis PFB only. +// s_axi_aclk : clock for s_axi_* +// aclk : clock for s_axis_* and m_axis_* +module axis_pfbs_pr_4x256_v1 + ( + // AXI Slave I/F for configuration. + input wire s_axi_aclk , + input wire s_axi_aresetn , + + input wire [5:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + + input wire [31:0] s_axi_wdata , + input wire [3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + + output wire [1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + + input wire [5:0] s_axi_araddr , + input wire [2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + + output wire [31:0] s_axi_rdata , + output wire [1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , + + // s_* and m_* reset/clock. + input wire aresetn , + input wire aclk , + + // S_AXIS for data input. + input wire [8*32-1:0] s_axis_tdata , + input wire s_axis_tlast , + input wire s_axis_tvalid , + output wire s_axis_tready , + + // M_AXIS for data output. + output wire [4*32-1:0] m_axis_tdata , + output wire m_axis_tvalid + ); + +parameter N = 256; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] QOUT_REG; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .QOUT_REG (QOUT_REG ) + ); + +// PFB Block. +pfb + #( + .N (256), + .L (4 ) + ) + pfb_i + ( + // Reset and clock. + .aresetn , + .aclk , + + // S_AXIS for input data. + .s_axis_tdata , + .s_axis_tlast , + .s_axis_tvalid , + .s_axis_tready , + + // M_AXIS for output data. + .m_axis_tdata , + .m_axis_tvalid , + + // Registers. + .QOUT_REG + ); + +endmodule + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/README b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/README new file mode 100644 index 0000000..a8858c0 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/README @@ -0,0 +1,9 @@ +This block integrates Xilinx's SSR FFT, generated with Syetem Generator. + +The top level also includes the framing block, which aligns the data with +the input TLAST to ensure data is properly aligned. + +NOTE: This implementation does not use pkt_align block, which allows to +buffer packets in the case tvalid drops in the middle of a frame. This +simplified implementation will just discard samples and re-sync again. + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/framing.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/framing.vhd new file mode 100644 index 0000000..42f6086 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/framing.vhd @@ -0,0 +1,178 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity framing is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4; + + -- Bits. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- Synced outputs. + tdata : out std_logic_vector (2*SSR*B-1 downto 0); + tvalid : out std_logic + ); +end framing; + +architecture rtl of framing is + +constant NWAIT : Integer := 256; +constant NWAIT_LOG2 : Integer := Integer(ceil(log2(real(NWAIT)))); +constant CYCLES : Integer := NFFT/SSR; +constant CYCLES_LOG2 : Integer := Integer(ceil(log2(real(CYCLES)))); + +-- FSM. +type fsm_type is ( INIT_ST , + RST_ST , + S0_ST , + S1_ST , + S2_ST ); +signal current_state, next_state : fsm_type; + +signal rst_state : std_logic; + +signal data_r : std_logic_vector (s_axis_tdata'length-1 downto 0); +signal data_rr : std_logic_vector (s_axis_tdata'length-1 downto 0); + +signal valid_i : std_logic; +signal valid_r : std_logic; +signal valid_rr : std_logic; + +signal cnt_nwait : unsigned (NWAIT_LOG2-1 downto 0); +signal cnt : unsigned (CYCLES_LOG2-1 downto 0); + +begin + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( aresetn = '0' ) then + -- State register. + current_state <= INIT_ST; + + -- Pipeline registers. + data_r <= (others => '0'); + data_rr <= (others => '0'); + valid_r <= '0'; + valid_rr <= '0'; + + -- Counters. + cnt_nwait <= (others => '0'); + cnt <= (others => '0'); + else + -- State register. + current_state <= next_state; + + -- Pipeline registers. + data_r <= s_axis_tdata; + data_rr <= data_r; + valid_r <= valid_i; + valid_rr <= valid_r; + + -- Counters. + if ( rst_state = '1' ) then + cnt_nwait <= cnt_nwait + 1; + end if; + + if ( valid_i = '1' ) then + if ( cnt < to_unsigned(CYCLES-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + end if; + end if; + end if; + end if; +end process; + +-- Next state logic. +process (current_state, cnt_nwait, s_axis_tlast, cnt) +begin + case (current_state) is + when INIT_ST => + next_state <= RST_ST; + + when RST_ST => + if ( cnt_nwait < to_unsigned(NWAIT-1,cnt_nwait'length) ) then + next_state <= RST_ST; + else + next_state <= S0_ST; + end if; + + when S0_ST => + if ( s_axis_tlast = '1' ) then + -- Check if tlast is in the right position. + if ( cnt = to_unsigned(CYCLES-1,cnt'length) ) then + next_state <= S0_ST; + else + -- tlast in the wrong position. + next_state <= S1_ST; + end if; + else + next_state <= S0_ST; + end if; + + when S1_ST => + -- Wait until a frame is completed. + if ( cnt = to_unsigned(CYCLES-1,cnt'length) ) then + next_state <= S2_ST; + else + next_state <= S1_ST; + end if; + + when S2_ST => + -- Wait for the next tlast. + if ( s_axis_tlast = '1' ) then + next_state <= S0_ST; + else + next_state <= S2_ST; + end if; + + end case; +end process; + +-- Output logic. +process (current_state) +begin +rst_state <= '0'; +valid_i <= '0'; + case (current_state) is + when INIT_ST => + + when RST_ST => + rst_state <= '1'; + + when S0_ST => + valid_i <= '1'; + + when S1_ST => + valid_i <= '1'; + + when S2_ST => + + end case; +end process; + +-- Assign outputs. +tdata <= data_rr; +tvalid <= valid_rr; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/conv_pkg.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/conv_pkg.vhd new file mode 100644 index 0000000..b8f1a8f --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/conv_pkg.vhd @@ -0,0 +1,1922 @@ +--------------------------------------------------------------------- +-- +-- Package : conv_pkg +-- +-- Filename : conv_pkg.vhd +-- +-- Date : 8/16/99 +-- +-- Description : Package that defines constant values that is used in the +-- XBS and functions that convert one type to another. +-- +-- Note : This package uses a VHDL 93 constructs therefore when +-- compiling with ModelTech use: vcom -93 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package conv_pkg is + --------------------------------------------------------------------------- + -- Constant that tells whether we're simulating + --------------------------------------------------------------------------- + constant simulating : boolean := false + -- synthesis translate_off + or true + -- synthesis translate_on + ; + + --------------------------------------------------------------------------- + -- Constants for XBS + --------------------------------------------------------------------------- + -- Arithmetic types + constant xlUnsigned : integer := 1; + constant xlSigned : integer := 2; + constant xlFloat : integer := 3; + + -- Constants for Quantization and Overflow + constant xlWrap : integer := 1; + constant xlSaturate : integer := 2; + constant xlTruncate : integer := 1; + constant xlRound : integer := 2; + constant xlRoundBanker : integer := 3; + + -- Constants for xladdsub s-function + constant xlAddMode : integer := 1; + constant xlSubMode : integer := 2; + + --------------------------------------------------------------------------- + -- Black Box Attributes + --------------------------------------------------------------------------- + attribute black_box : boolean; -- for Synplicity (obsolete) + attribute syn_black_box : boolean; -- for Synplicity Version 6.0 + attribute fpga_dont_touch: string; -- for FPGA Express + attribute box_type : string; -- for XST + + --------------------------------------------------------------------------- + -- Attributes to keep clock enable signals + --------------------------------------------------------------------------- + attribute keep : string; + attribute syn_keep : boolean; + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type and vice versa + function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; + function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; + + -- convert a std_logic_vector to a signed type and vice versa + function std_logic_vector_to_signed(inp : std_logic_vector) return signed; + function signed_to_std_logic_vector(inp : signed) return std_logic_vector; + -- convert signed to unsigned and vice versa + function unsigned_to_signed(inp : unsigned) return signed; + function signed_to_unsigned(inp : signed) return unsigned; + -- Tests used in convert_type + function pos(inp : std_logic_vector; arith : INTEGER) return boolean; + function all_same(inp: std_logic_vector) return boolean; + function all_zeros(inp: std_logic_vector) return boolean; + function is_point_five(inp: std_logic_vector) return boolean; + function all_ones(inp: std_logic_vector) return boolean; + + + + -- Convert a fixed point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector; + + -- slice a vector + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector; + + -- slice a signed + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned; + + -- slice a unsigned + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return signed; + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return unsigned; + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, + new_width, new_bin_pt : INTEGER) + return std_logic_vector; + -- Quantization Functions + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, + new_arith : INTEGER) return std_logic_vector; + + -- Overflow functions + function max_signed(width : INTEGER) return std_logic_vector; + function min_signed(width : INTEGER) return std_logic_vector; + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) return std_logic_vector; + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector; + + --------------------------------------------------------------------------- + -- Binary point alignment functions + --------------------------------------------------------------------------- + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; + + -- Returns the number of integer bits after alignment of fixed point num. + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector; + + -- Pad LSB with zeros + function pad_LSB(inp : std_logic_vector; new_width: integer) + return std_logic_vector; + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith : integer) + return std_logic_vector; + + -- Find the max & min integer. + function max(L, R: INTEGER) return INTEGER; + function min(L, R: INTEGER) return INTEGER; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean; + + -- convert a boolean into a signed + function boolean_to_signed (inp : boolean; width: integer) + return signed; + -- convert a boolean into an unsigned + function boolean_to_unsigned (inp : boolean; width: integer) + return unsigned; + -- convert a boolean into std_logic_vector + function boolean_to_vector (inp : boolean) + return std_logic_vector; + -- convert a std_logic into std_logic_vector + function std_logic_to_vector (inp : std_logic) + return std_logic_vector; + -- convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector; + + -- Convert std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer; + function std_logic_to_integer(constant inp : std_logic := '0') + return integer; + + -- Convert a binary string array element into a std_logic_vector + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector; + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector; + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector (inp : string; width : integer) + return std_logic_vector; + + -- Make a binary string that represents zero + function makeZeroBinStr (width : integer) return STRING; + + + --------------------------------------------------------------------------- + -- Debugging functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's (i.e., 0bXX.X) + function is_binary_string_invalid (inp : string) + return boolean; + -- Check for all U's (i.e., 0bUU.U) + function is_binary_string_undefined (inp : string) + return boolean; + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean; + + + -- convert a std_logic_vector to a real type and vice versa + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real; + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real; + + + -- convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector; + -- convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector; + + -- display_precision is the number of digits to display in ModelTech's + -- waveform viewer ( used in to_string(inp : real) ) + constant display_precision : integer := 20; + -- convert a real into a string type + function real_to_string (inp : real) return string; + + -- Check of 0b and the beginning of a string + function valid_bin_string(inp : string) return boolean; + + -- Convert a std_logic_vector to a binary string + function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; + -- Convert a std_logic to a binary string + function std_logic_to_bin_string(inp : std_logic) return string; + -- convert a std_logic_vector to a binary string and add a binary point + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string; + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string; + + -- convert a std_logic_vector value to a character + type stdlogic_to_char_t is array(std_logic) of character; + constant to_char : stdlogic_to_char_t := ( + 'U' => 'U', + 'X' => 'X', + '0' => '0', + '1' => '1', + 'Z' => 'Z', + 'W' => 'W', + 'L' => 'L', + 'H' => 'H', + '-' => '-'); + + -- synthesis translate_on + +end conv_pkg; + +package body conv_pkg is + + --------------------------------------------------------------------------- + -- Arithmetic conversion functions + --------------------------------------------------------------------------- + -- convert a std_logic_vector to a unsigned type + function std_logic_vector_to_unsigned(inp : std_logic_vector) + return unsigned + is + begin + return unsigned (inp); + end; + + -- convert an unsigend to a std_logic_vector + function unsigned_to_std_logic_vector(inp : unsigned) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert an std_logic_vector to a signed + function std_logic_vector_to_signed(inp : std_logic_vector) + return signed + is + begin + return signed (inp); + end; + + -- convert an std_logic_vector to a sigend + function signed_to_std_logic_vector(inp : signed) + return std_logic_vector + is + begin + return std_logic_vector(inp); + end; + + -- convert unsigned to signed + function unsigned_to_signed (inp : unsigned) + return signed + is + begin -- unsigned_to_signed + return signed(std_logic_vector(inp)); + end; + + + -- convert signed to unsigned + function signed_to_unsigned (inp : signed) + return unsigned + is + begin -- signed_to_unsigned + return unsigned(std_logic_vector(inp)); + end; + + -- Test if a number is positive + function pos(inp : std_logic_vector; arith : INTEGER) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := inp; + if arith = xlUnsigned then + return true; + else + if vec(width-1) = '0' then + return true; + else + return false; + end if; + end if; + + -- Error + return true; + end; + + function max_signed(width : INTEGER) + return std_logic_vector + is + variable ones : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + ones := (others => '1'); + result(width-1) := '0'; + result(width-2 downto 0) := ones; + return result; + end; + + function min_signed(width : INTEGER) + return std_logic_vector + is + variable zeros : std_logic_vector(width-2 downto 0); + variable result : std_logic_vector(width-1 downto 0); + begin + zeros := (others => '0'); + result(width-1) := '1'; + result(width-2 downto 0) := zeros; + return result; + end; + + -- Check if all the bits are the same + function all_same(inp: std_logic_vector) return boolean + is + variable result: boolean; + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + begin + vec := inp; + result := true; + if width > 0 then + for i in 1 to width-1 loop + if vec(i) /= vec(0) then + result := false; + end if; + end loop; + end if; + return result; + end; + + + -- Check if a number is all zeros + function all_zeros(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable zero : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + zero := (others => '0'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Check if a number is point five + function is_point_five(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (width > 1) then + if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then + result := true; + else + result := false; + end if; + else + if (vec(width-1) = '1') then + result := true; + else + result := false; + end if; + end if; + + return result; + end; + + -- Check if a number is all ones + function all_ones(inp: std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable one : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + one := (others => '1'); + vec := inp; + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then + result := true; + else + result := false; + end if; + return result; + end; + + + --------------------------------------------------------------------------- + -- Type conersion functions + --------------------------------------------------------------------------- + + + -- Calculate the width of the temp. full precision representation + function full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return integer + is + variable result : integer; + begin + result := old_width + 2; + return result; + end; + + -- Calculate the width of the temp. quantized representation + -- ASSUMES POSITIVE BIN_PT + function quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return integer + is + variable right_of_dp, left_of_dp, result : integer; + begin + + right_of_dp := max(new_bin_pt, old_bin_pt); + left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); + + result := (old_width + 2) + (new_bin_pt - old_bin_pt); + return result; + end; + + + + -- Convert one Fix point type to another fixed point type with a + -- different bin_pt, width, and arithmetic type + function convert_type (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith, + quantization, overflow : INTEGER) + return std_logic_vector + is + constant fp_width : integer := + full_precision_num_width(quantization, overflow, old_width, + old_bin_pt, old_arith, new_width, + new_bin_pt, new_arith); + constant fp_bin_pt : integer := old_bin_pt; + constant fp_arith : integer := old_arith; + variable full_precision_result : std_logic_vector(fp_width-1 downto 0); + + constant q_width : integer := + quantized_num_width(quantization, overflow, old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith); + constant q_bin_pt : integer := new_bin_pt; + constant q_arith : integer := old_arith; + variable quantized_result : std_logic_vector(q_width-1 downto 0); + + variable result : std_logic_vector(new_width-1 downto 0); + begin + result := (others => '0'); + + full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, + fp_arith); + + -- Apply quantization functions. This will remove LSB bits. + if (quantization = xlRound) then + + quantized_result := round_towards_inf(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + elsif (quantization = xlRoundBanker) then + quantized_result := round_towards_even(full_precision_result, + fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, + q_arith); + else + quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, + fp_arith, q_width, q_bin_pt, q_arith); + end if; + + + -- Apply overflow function. This will remove MSB bits. + if (overflow = xlSaturate) then + result := saturation_arith(quantized_result, q_width, q_bin_pt, + q_arith, new_width, new_bin_pt, new_arith); + else + result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, + new_width, new_bin_pt, new_arith); + end if; + + + return result; + end; + + -- Cast type by zero pading or Sign extending MSB and + -- zero pading or truncating LSB + function cast (inp : std_logic_vector; old_bin_pt, new_width, + new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (new_width - new_bin_pt) + - (old_width - old_bin_pt); + -- Number of digits to add/subract to the right of the decimal point + constant right_of_dp : integer := (new_bin_pt - old_bin_pt); + + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable j : integer; + + begin + vec := inp; + for i in new_width-1 downto 0 loop + j := i - right_of_dp; + if ( j > old_width-1) then + -- Bits to the left of the decimal point + if (new_arith = xlUnsigned) then + -- If unsigned zero pad MSB + result(i) := '0'; + else + -- If signed, sign extend MSB + result(i) := vec(old_width-1); + end if; + elsif ( j >= 0) then + -- Copy bits from input + result(i) := vec(j); + else + -- zero pad LSB + result(i) := '0'; + end if; + end loop; + + return result; + end; + + function shift_division_result(quotient, fraction: std_logic_vector; + fraction_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant q_width : integer := quotient'length; + constant f_width : integer := fraction'length; + constant vec_MSB : integer := q_width+f_width-1; + constant result_MSB : integer := q_width+fraction_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := ( quotient & fraction ); + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + function shift_op (inp: std_logic_vector; + result_width, shift_value, shift_dir: INTEGER) + return std_logic_vector + is + constant inp_width : integer := inp'length; + constant vec_MSB : integer := inp_width-1; + constant result_MSB : integer := result_width-1; + constant result_LSB : integer := vec_MSB-result_MSB; + variable vec : std_logic_vector(vec_MSB downto 0); + variable result : std_logic_vector(result_MSB downto 0); + begin + vec := inp; + if shift_dir = 1 then + for i in vec_MSB downto 0 loop + if (i < shift_value) then + vec(i) := '0'; + else + vec(i) := vec(i-shift_value); + end if; + end loop; + --vec := vec sll shift_value; + else + for i in 0 to vec_MSB loop + if (i > vec_MSB-shift_value) then + vec(i) := vec(vec_MSB); + else + vec(i) := vec(i+shift_value); + end if; + end loop; + --vec := vec srl shift_value; + end if; + result := vec(vec_MSB downto result_LSB); + return result; + end; + + + -- vector slice + function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) + return std_logic_vector + is + begin + return inp(upper downto lower); + end; + + -- signed slice + function s2u_slice (inp : signed; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- unsigned slice + function u2u_slice (inp : unsigned; upper, lower : INTEGER) + return unsigned + is + begin + return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); + end; + + -- Cast signed to signed + function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast signed to unsigned + function s2u_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); + end; + + -- Cast unsigned to signed + function u2s_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return signed + is + begin + return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to unsigned + function u2u_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return unsigned + is + begin + return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); + end; + + -- Cast unsigned to std_logic_vector + function u2v_cast (inp : unsigned; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); + end; + + -- Cast signed to std_logic_vector + function s2v_cast (inp : signed; old_bin_pt, new_width, + new_bin_pt : INTEGER) + return std_logic_vector + is + begin + return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); + end; + + function boolean_to_signed (inp : boolean; width : integer) + return signed + is + variable result : signed(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_unsigned (inp : boolean; width : integer) + return unsigned + is + variable result : unsigned(width - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function boolean_to_vector (inp : boolean) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result := (others => '0'); + if inp then + result(0) := '1'; + else + result(0) := '0'; + end if; + return result; + end; + + function std_logic_to_vector (inp : std_logic) + return std_logic_vector + is + variable result : std_logic_vector(1 - 1 downto 0); + begin + result(0) := inp; + return result; + end; + + --------------------------------------------------------------------------- + -- Quantization Functions + --------------------------------------------------------------------------- + + -- Truncate LSB bits + function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, + new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign Extent or zero extend if necessary + if new_arith = xlUnsigned then + result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); + else + result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + result := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + result := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + return result; + end; + + + -- Round towards infinity + function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + if (new_arith = xlSigned) then + -- Roundeing logic for signed numbers + -- Example: + -- Fix(5,-2) = 101.11 (bin) -2.25 (dec) + -- Converted to: Fix(4,-1) = 101.1 (bin) -2.5 (dec) + -- Note: same algorithm used for unsigned numbers can't be used. + + -- 1st check the sign bit of the input to see if it is a positive + -- number + if (vec(old_width-1) = '0') then + one_or_zero(0) := '1'; + end if; + + -- 2nd check if digits being truncated are all zeros + -- (in example it is bit zero) + if (right_of_dp >= 2) and (right_of_dp <= old_width) then + if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then + one_or_zero(0) := '1'; + end if; + end if; + + -- 3rd check if the bit right before the truncation point is '1' + -- or '0' (in example it is bit one) + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if vec(right_of_dp-1) = '0' then + one_or_zero(0) := '0'; + end if; + else + -- No rounding to be performed + one_or_zero(0) := '0'; + end if; + else + -- For an unsigned number just check if the bit right before the + -- truncation point is '1' or '0' + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + one_or_zero(0) := vec(right_of_dp-1); + end if; + end if; + + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + -- Round towards even values + function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of binary digits to add/subract to the right of the decimal + -- point + constant right_of_dp : integer := (old_bin_pt - new_bin_pt); + + constant expected_new_width : integer := old_width - right_of_dp + 1; + variable vec : std_logic_vector(old_width-1 downto 0); + variable one_or_zero : std_logic_vector(new_width-1 downto 0); + variable truncated_val : std_logic_vector(new_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if right_of_dp >= 0 then + -- Sign extend or zero extend to size of output + if new_arith = xlUnsigned then + truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), + new_width); + else + truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), + new_width); + end if; + + else + -- Pad LSB with zeros and sign extend by one bit + if new_arith = xlUnsigned then + truncated_val := zero_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + else + truncated_val := sign_ext(pad_LSB(vec, old_width + + abs(right_of_dp)), new_width); + end if; + end if; + + -- Figure out if '1' should be added to the truncated number + one_or_zero := (others => '0'); + + -- For the truncated bits just check if the bits after the + -- truncation point are 0.5 + if (right_of_dp >= 1) and (right_of_dp <= old_width) then + if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then + one_or_zero(0) := vec(right_of_dp-1); + else + one_or_zero(0) := vec(right_of_dp); + end if; + end if; + + if new_arith = xlSigned then + result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + + std_logic_vector_to_signed(one_or_zero)); + else + result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + + std_logic_vector_to_unsigned(one_or_zero)); + end if; + + return result; + end; + + --------------------------------------------------------------------------- + -- Overflow Functions + --------------------------------------------------------------------------- + + -- Apply Saturation arithmetic. The new_bin_pt and old bin_pt should be + -- equal. The function chops bits off MSB bits. + function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith + : INTEGER) + return std_logic_vector + is + -- Number of digits to add/subract to the left of the decimal point + constant left_of_dp : integer := (old_width - old_bin_pt) - + (new_width - new_bin_pt); + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable overflow : boolean; + begin + vec := inp; + overflow := true; + result := (others => '0'); + + ----------------------------------------------------------------------- + -- Check for cases when overflow does not occur + ----------------------------------------------------------------------- + + -- Output width is >= input width + if (new_width >= old_width) then + overflow := false; + end if; + + -- Case #1: + -- Both the input and output are signed and the bits that will + -- be truncated plus the sign bit are all the same + -- (i.e., number has been sign extended) + if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + -- Case #2: + -- If the input is converted to a unsigned from an signed then only + -- check the bits that will be truncated are all zero + if (old_arith = xlSigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + -- Check if input is positive + if (vec(new_width-1) = '0') then + overflow := false; + end if; + end if; + end if; + end if; + + -- Case #3: + -- Input is unsigned and the bits that will be truncated are all zero + if (old_arith = xlUnsigned and new_arith = xlUnsigned) then + if (old_width > new_width) then + if all_zeros(vec(old_width-1 downto new_width)) then + overflow := false; + end if; + else + if (old_width = new_width) then + overflow := false; + end if; + end if; + end if; + + -- Case #4: + -- Input is unsigned but output signed and the bits that will be + -- truncated are all zero + if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then + if all_same(vec(old_width-1 downto new_width-1)) then + overflow := false; + end if; + end if; + + + if overflow then + -- Overflow occured + if new_arith = xlSigned then + -- Check sign bit and set to max signed or min signed value + if vec(old_width-1) = '0' then + result := max_signed(new_width); + else + result := min_signed(new_width); + end if; + else + -- Check sign bit and set to zero if negative + if ((old_arith = xlSigned) and vec(old_width-1) = '1') then + result := (others => '0'); + else + -- Set to max unsigned positive value + result := (others => '1'); + end if; + end if; + else + -- Overflow did not occur + + -- Check for case when input type is signed and output type + -- unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + -- if negative number set vec to zero + if (vec(old_width-1) = '1') then + vec := (others => '0'); + end if; + end if; + + if new_width <= old_width then + result := vec(new_width-1 downto 0); + else + -- Sign or zero extend number depending on arith of new number + if new_arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + end if; + end if; + + return result; + end; + + function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, + old_arith, new_width, new_bin_pt, new_arith : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + variable result_arith : integer; + begin + -- Check for case when input type is signed and output type unsigned + if (old_arith = xlSigned) and (new_arith = xlUnsigned) then + result_arith := xlSigned; + end if; + + result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); + + return result; + end; + + + -- Returns the number of fractional bits after alignment of fixed point num + function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is + begin + return max(a_bin_pt, b_bin_pt); + end; + + -- Returns the number of integer bits after alignment of fixed point num + function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) + return INTEGER is + begin + return max(a_width - a_bin_pt, b_width - b_bin_pt); + end; + + function pad_LSB(inp : std_logic_vector; new_width: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + -- Added for XST + constant pad_pos : integer := new_width - orig_width - 1; + + begin + vec := inp; + pos := new_width-1; + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pad_pos >= 0 then + for i in pad_pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + + -- sign extend the MSB + function sign_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + -- sign extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := vec(old_width-1); + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + + + -- zero extend the MSB + function zero_ext(inp : std_logic_vector; new_width : INTEGER) + return std_logic_vector + is + constant old_width : integer := inp'length; + variable vec : std_logic_vector(old_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + -- zero extend + if new_width >= old_width then + result(old_width-1 downto 0) := vec; + if new_width-1 >= old_width then + for i in new_width-1 downto old_width loop + result(i) := '0'; + end loop; + end if; + else + result(new_width-1 downto 0) := vec(new_width-1 downto 0); + end if; + + return result; + end; + + -- zero extend the MSB + function zero_ext(inp : std_logic; new_width : INTEGER) + return std_logic_vector + is + variable result : std_logic_vector(new_width-1 downto 0); + begin + result(0) := inp; + for i in new_width-1 downto 1 loop + result(i) := '0'; + end loop; + + return result; + end; + + -- zero or sign extend the MSB + function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) + return std_logic_vector + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if arith = xlUnsigned then + result := zero_ext(vec, new_width); + else + result := sign_ext(vec, new_width); + end if; + + return result; + end; + + -- Pad LSB with zeros and add a zero or sign extend the MSB + function pad_LSB(inp : std_logic_vector; new_width, arith: integer) + return STD_LOGIC_VECTOR + is + constant orig_width : integer := inp'length; + variable vec : std_logic_vector(orig_width-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + variable pos : integer; + begin + vec := inp; + pos := new_width-1; + + if (arith = xlUnsigned) then + -- set MSB to zero + result(pos) := '0'; + pos := pos - 1; + else + -- sign extend + result(pos) := vec(orig_width-1); + pos := pos - 1; + end if; + + if (new_width >= orig_width) then + for i in orig_width-1 downto 0 loop + result(pos) := vec(i); + pos := pos - 1; + end loop; + if pos >= 0 then + for i in pos downto 0 loop + result(i) := '0'; + end loop; + end if; + end if; + + return result; + end; + + -- Align input by padding LSB with zeros and sign or zero extening + function align_input(inp : std_logic_vector; old_width, delta, new_arith, + new_width: INTEGER) + return std_logic_vector + is + variable vec : std_logic_vector(old_width-1 downto 0); + variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); + variable result : std_logic_vector(new_width-1 downto 0); + begin + vec := inp; + + if delta > 0 then + padded_inp := pad_LSB(vec, old_width+delta); + + -- sign or zero extend zero padded input depending on arith type + result := extend_MSB(padded_inp, new_width, new_arith); + else + -- sign or zero extend input depending on arith type + result := extend_MSB(vec, new_width, new_arith); + end if; + + return result; + end; + + function max(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + function min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + -- Test is two strings are equal + function "="(left,right: STRING) return boolean is +-- constant NULL_Str : string := ""; + begin + if (left'length /= right'length) then + return false; + else + -- Check for NULL string + -- FPGA Express does not like empty strings +-- if (left'length = NULL_Str'length) or +-- (right'length = NULL_Str'length) then +-- return true; +-- end if; + test : for i in 1 to left'length loop + if left(i) /= right(i) then + return false; + end if; + end loop test; + return true; + end if; + end; + + + --------------------------------------------------------------------------- + -- Debugging and Simulation only functions + --------------------------------------------------------------------------- + -- synthesis translate_off + + -- Check for all X's + function is_binary_string_invalid (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'X' ) then + result := true; + end if; + end loop; + return result; + end; + + -- Check for all U's + function is_binary_string_undefined (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + variable result : boolean; + begin + vec := inp; + result := false; + + for i in 1 to vec'length loop + if ( vec(i) = 'U' ) then + result := true; + end if; + end loop; + return result; + end; + + + + + -- Check for Undefined values + function is_XorU(inp : std_logic_vector) + return boolean + is + constant width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable result : boolean; + begin + vec := inp; + result := false; + for i in 0 to width-1 loop + if (vec(i) = 'U') or (vec(i) = 'X') then + result := true; + end if; + end loop; + return result; + end; + + -- Converts a std_logic_vector to a real + function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) + return real + is + variable vec : std_logic_vector(inp'length-1 downto 0); + variable result, shift_val, undefined_real : real; + variable neg_num : boolean; + begin + vec := inp; + result := 0.0; + neg_num := false; + if vec(inp'length-1) = '1' then + neg_num := true; + end if; + + for i in 0 to inp'length-1 loop + if vec(i) = 'U' or vec(i) = 'X' then + return undefined_real; + end if; + if arith = xlSigned then + if neg_num then + -- Perform 1's count if negative number + if vec(i) = '0' then + result := result + 2.0**i; + end if; + else + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + else + -- Unsigned numbers + if vec(i) = '1' then + result := result + 2.0**i; + end if; + end if; + end loop; + + if arith = xlSigned then + if neg_num then + -- Add one to 1's comp number to make 2's comp number + result := result + 1.0; + result := result * (-1.0); + end if; + end if; + -- Realign based on binary point + shift_val := 2.0**(-1*bin_pt); + result := result * shift_val; + return result; + end; + + -- This function is just for consistancy + -- bin_pt and arith not used. + function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) + return real + is + variable result : real := 0.0; + begin + if inp = '1' then + result := 1.0; + end if; + + if arith = xlSigned then + assert false + report "It doesn't make sense to convert a 1 bit number to a signed real."; + end if; + return result; + end; + + -- synthesis translate_on + -- Convert an integer into a std_logic_vector + function integer_to_std_logic_vector (inp : integer; width, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + begin + + if (arith = xlSigned) then + signed_val := to_signed(inp, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(inp, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- Convert an std_logic or std_logic_vector to an integer + function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) + return integer + is + constant width : integer := inp'length; + variable unsigned_val : unsigned(width-1 downto 0); + variable signed_val : signed(width-1 downto 0); + variable result : integer; + begin + + if (arith = xlSigned) then + signed_val := std_logic_vector_to_signed(inp); + result := to_integer(signed_val); + else + unsigned_val := std_logic_vector_to_unsigned(inp); + result := to_integer(unsigned_val); + end if; + + return result; + end; + + function std_logic_to_integer(constant inp : std_logic := '0') + return integer + is + begin + if inp = '1' then + return 1; + else + return 0; + end if; + end; + + + function makeZeroBinStr (width : integer) return STRING is + variable result : string(1 to width+3); + begin + result(1) := '0'; + result(2) := 'b'; + for i in 3 to width+2 loop + result(i) := '0'; + end loop; -- i + result(width+3) := '.'; + + return result; + end; + + + + -- synthesis translate_off + -- Convert a real string into a std_logic_vector + function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) + return std_logic_vector + is + variable result : std_logic_vector(width-1 downto 0); + begin + --result := to_std_logic_vector(real'value(inp), width, bin_pt, arith); + result := (others => '0'); + return result; + end; + + -- Convert a real into a std_logic_vector + function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) + return std_logic_vector + is + variable real_val : real; + variable int_val : integer; + variable result : std_logic_vector(width-1 downto 0) := (others => '0'); + variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); + variable signed_val : signed(width-1 downto 0) := (others => '0'); + begin + + real_val := inp; + + -- Scale double and make it an integer + int_val := integer(real_val * 2.0**(bin_pt)); + + if (arith = xlSigned) then + signed_val := to_signed(int_val, width); + result := signed_to_std_logic_vector(signed_val); + else + unsigned_val := to_unsigned(int_val, width); + result := unsigned_to_std_logic_vector(unsigned_val); + end if; + + return result; + end; + + + -- synthesis translate_on + -- Check of 0b and the beginning of a string + function valid_bin_string (inp : string) + return boolean + is + variable vec : string(1 to inp'length); + begin + vec := inp; + if (vec(1) = '0' and vec(2) = 'b') then + return true; + else + return false; + end if; + end; + + -- convert a hex string to a std_logic_vector + function hex_string_to_std_logic_vector(inp: string; width : integer) + return std_logic_vector is + + constant strlen : integer := inp'LENGTH; + variable result : std_logic_vector(width-1 downto 0); + variable bitval : std_logic_vector((strlen*4)-1 downto 0); + variable posn : integer; + variable ch : character; + variable vec : string(1 to strlen); + begin + vec := inp; + + -- default value is zero + result := (others => '0'); + posn := (strlen*4)-1; + + for i in 1 to strlen loop + ch := vec(i); + case ch is + when '0' => bitval(posn downto posn-3) := "0000"; + when '1' => bitval(posn downto posn-3) := "0001"; + when '2' => bitval(posn downto posn-3) := "0010"; + when '3' => bitval(posn downto posn-3) := "0011"; + when '4' => bitval(posn downto posn-3) := "0100"; + when '5' => bitval(posn downto posn-3) := "0101"; + when '6' => bitval(posn downto posn-3) := "0110"; + when '7' => bitval(posn downto posn-3) := "0111"; + when '8' => bitval(posn downto posn-3) := "1000"; + when '9' => bitval(posn downto posn-3) := "1001"; + when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; + when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; + when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; + when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; + when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; + when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; + when others => bitval(posn downto posn-3) := "XXXX"; + -- synthesis translate_off + ASSERT false + REPORT "Invalid hex value" SEVERITY ERROR; + -- synthesis translate_on + end case; + posn := posn - 4; + end loop; + + if (width <= strlen*4) then + -- bitval larger than desired width + result := bitval(width-1 downto 0); + else + -- bitval smaller than desired width + -- MSB is padded with zeros since default value for result is all 0s + result((strlen*4)-1 downto 0) := bitval; + end if; + return result; + end; + + + -- convert a binary string into a std_logic_vector (e.g., 0b10.1 = 101) + function bin_string_to_std_logic_vector (inp : string) + return std_logic_vector + is + variable pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(inp'length-1 downto 0); + begin + vec := inp; + pos := inp'length-1; + -- Set default value + result := (others => '0'); + + for i in 1 to vec'length loop + -- synthesis translate_off + if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then + assert false + report "Input string is larger than output std_logic_vector. Truncating output."; + return result; + end if; + -- synthesis translate_on + + if vec(i) = '0' then + result(pos) := '0'; + pos := pos - 1; + end if; + if vec(i) = '1' then + result(pos) := '1'; + pos := pos - 1; + end if; + -- synthesis translate_off + if (vec(i) = 'X' or vec(i) = 'U') then + result(pos) := 'U'; + pos := pos - 1; + end if; + -- synthesis translate_on + end loop; + return result; + end; + + + -- Convert a binary string array element into a std_logic_vector + -- Example "0b000.0000000 0b001.0000000" + -- string_pos: 123456789111111111122222222 + -- 012345678901234567 + -- + -- "0b000.0000000" = inp(0) + -- "0b001.0000000" = inp(1) + function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) + return std_logic_vector + is + constant str_width : integer := width + 4; -- +4 for '0b' '.' & ' ' + constant inp_len : integer := inp'length; + constant num_elements : integer := (inp_len + 1)/str_width; + constant reverse_index : integer := (num_elements-1) - index; + + -- Calc position of desired str + variable left_pos : integer; + variable right_pos : integer; + variable vec : string(1 to inp'length); + variable result : std_logic_vector(width-1 downto 0); + begin + -- Can't pad input with a space (Synplicity crashes) + vec := inp; + + -- Set default value + result := (others => '0'); + + -- Special Case for string like "0b01.0" without extra ' ' after string + if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := 1; + right_pos := width + 3; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then + left_pos := (reverse_index * str_width) + 1; + right_pos := left_pos + width + 2; + result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); + end if; + + return result; + end; + -- synthesis translate_off + + -- + -- convert a std_logic_vector to a string + -- + function std_logic_vector_to_bin_string(inp : std_logic_vector) + return string + is + variable vec : std_logic_vector(1 to inp'length); + variable result : string(vec'range); + begin + vec := inp; + for i in vec'range loop + result(i) := to_char(vec(i)); + end loop; + return result; + end; + + -- + -- convert a std_logic to a string + -- + function std_logic_to_bin_string(inp : std_logic) + return string + is + variable result : string(1 to 3); + begin + -- Add 0b prefix + result(1) := '0'; + result(2) := 'b'; + result(3) := to_char(inp); + return result; + end; + + -- + -- convert a std_logic_vector to a string and add a binary point + -- + function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) + return string + is + variable width : integer := inp'length; + variable vec : std_logic_vector(width-1 downto 0); + variable str_pos : integer; + variable result : string(1 to width+3); + begin + vec := inp; + -- Add 0b prefeix + str_pos := 1; + result(str_pos) := '0'; + str_pos := 2; + result(str_pos) := 'b'; + str_pos := 3; + for i in width-1 downto 0 loop + -- Insert decimal point + -- if i = (width - bin_pt + 1) then + if (((width+3) - bin_pt) = str_pos) then + result(str_pos) := '.'; + str_pos := str_pos + 1; + end if; + result(str_pos) := to_char(vec(i)); + str_pos := str_pos + 1; + end loop; + -- Add binary point at end of string when bin_pt = 0 + if (bin_pt = 0) then + result(str_pos) := '.'; + end if; + + return result; + end; + + -- Convert a real to a binary string + function real_to_bin_string(inp : real; width, bin_pt, arith : integer) + return string + is + variable result : string(1 to width); + variable vec : std_logic_vector(width-1 downto 0); + + begin + vec := real_to_std_logic_vector(inp, width, bin_pt, arith); + result := std_logic_vector_to_bin_string(vec); + + return result; + end; + + + -- Convert a real to string + -- Note: the size of the string returned is 'display_precision' chars long + function real_to_string (inp : real) return string + is + variable result : string(1 to display_precision) := (others => ' '); + begin + result(real'image(inp)'range) := real'image(inp); + return result; + end; + + -- synthesis translate_on + + +end conv_pkg; + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/single_reg_w_init.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/single_reg_w_init.vhd new file mode 100644 index 0000000..26af1d6 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/single_reg_w_init.vhd @@ -0,0 +1,109 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : single_reg_w_init.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg_w_init.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity single_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end single_reg_w_init; + +architecture structural of single_reg_w_init is + function build_init_const(width: integer; + init_index: integer; + init_value: bit_vector) + return std_logic_vector + is + variable result: std_logic_vector(width - 1 downto 0); + begin + if init_index = 0 then + result := (others => '0'); + elsif init_index = 1 then + result := (others => '0'); + result(0) := '1'; + else + result := to_stdlogicvector(init_value); + end if; + return result; + end; + + component fdre + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + r: in std_ulogic + ); + end component; -- end fdre + attribute syn_black_box of fdre: component is true; + attribute fpga_dont_touch of fdre: component is "true"; + + component fdse + port ( + q: out std_ulogic; + d: in std_ulogic; + c: in std_ulogic; + ce: in std_ulogic; + s: in std_ulogic + ); + end component; -- end fdse + attribute syn_black_box of fdse: component is true; + attribute fpga_dont_touch of fdse: component is "true"; + + constant init_const: std_logic_vector(width - 1 downto 0) + := build_init_const(width, init_index, init_value); +begin + fd_prim_array: for index in 0 to width - 1 generate + + bit_is_0: if (init_const(index) = '0') generate + fdre_comp: fdre + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + r => clr + ); + end generate; -- end bit_is_0 + + bit_is_1: if (init_const(index) = '1') generate + fdse_comp: fdse + port map ( + c => clk, + d => i(index), + q => o(index), + ce => ce, + s => clr + ); + end generate; -- end bit_is_1 + end generate; -- end fd_prim_array +end architecture structural; + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/srl17e.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/srl17e.vhd new file mode 100644 index 0000000..8ec9c8d --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/srl17e.vhd @@ -0,0 +1,93 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srl17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srl17e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srl17e; + +architecture structural of srl17e is + + component SRL16E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A0 : in STD_ULOGIC; + A1 : in STD_ULOGIC; + A2 : in STD_ULOGIC; + A3 : in STD_ULOGIC; + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRL16E : component is true; + attribute fpga_dont_touch of SRL16E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srl16_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srl16_used: if latency > 1 generate + u1 : srl16e port map(clk => clk, + d => d_delayed(i), + q => srl16_out(i), + ce => ce, + a0 => a(0), + a1 => a(1), + a2 => a(2), + a3 => a(3)); + end generate; + srl16_not_used: if latency <= 1 generate + srl16_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srl16_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srl16_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/srl33e.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/srl33e.vhd new file mode 100644 index 0000000..c943462 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/srl33e.vhd @@ -0,0 +1,87 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : srlc17e.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity srlc33e is + generic (width : integer:=16; + latency : integer :=8); -- Max 17 + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end srlc33e; + +architecture structural of srlc33e is + + component SRLC32E + port (D : in STD_ULOGIC; + CE : in STD_ULOGIC; + CLK : in STD_ULOGIC; + A : in std_logic_vector(4 downto 0); + Q : out STD_ULOGIC); + end component; + attribute syn_black_box of SRLC32E : component is true; + attribute fpga_dont_touch of SRLC32E : component is "true"; + + component FDE + port( + Q : out STD_ULOGIC; + D : in STD_ULOGIC; + C : in STD_ULOGIC; + CE : in STD_ULOGIC); + end component; + attribute syn_black_box of FDE : component is true; + attribute fpga_dont_touch of FDE : component is "true"; + + + constant a : std_logic_vector(4 downto 0) := + integer_to_std_logic_vector(latency-2,5,xlSigned); + signal d_delayed : std_logic_vector(width-1 downto 0); + signal srlc32_out : std_logic_vector(width-1 downto 0); + +begin + d_delayed <= d after 200 ps; + + reg_array : for i in 0 to width-1 generate + srlc32_used: if latency > 1 generate + u1 : srlc32e port map(clk => clk, + d => d_delayed(i), + q => srlc32_out(i), + ce => ce, + a => a); + end generate; + srlc32_not_used: if latency <= 1 generate + srlc32_out(i) <= d_delayed(i); + end generate; + + fde_used: if latency /= 0 generate + u2 : fde port map(c => clk, + d => srlc32_out(i), + q => q(i), + ce => ce); + end generate; + fde_not_used: if latency = 0 generate + q(i) <= srlc32_out(i); + end generate; + + end generate; + end structural; + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256.vhd new file mode 100644 index 0000000..8ae6b87 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256.vhd @@ -0,0 +1,2133 @@ +-- Generated from Simulink block ssr_8x256/Vector FFT/Scalar2Vector +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_scalar2vector is + port ( + i : in std_logic_vector( 432-1 downto 0 ); + o_1 : out std_logic_vector( 54-1 downto 0 ); + o_2 : out std_logic_vector( 54-1 downto 0 ); + o_3 : out std_logic_vector( 54-1 downto 0 ); + o_4 : out std_logic_vector( 54-1 downto 0 ); + o_5 : out std_logic_vector( 54-1 downto 0 ); + o_6 : out std_logic_vector( 54-1 downto 0 ); + o_7 : out std_logic_vector( 54-1 downto 0 ); + o_8 : out std_logic_vector( 54-1 downto 0 ) + ); +end ssr_8x256_scalar2vector; +architecture structural of ssr_8x256_scalar2vector is + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); +begin + o_1 <= slice0_y_net; + o_2 <= slice1_y_net; + o_3 <= slice2_y_net; + o_4 <= slice3_y_net; + o_5 <= slice4_y_net; + o_6 <= slice5_y_net; + o_7 <= slice6_y_net; + o_8 <= slice7_y_net; + test_systolicfft_vhdl_black_box_o_net <= i; + slice0 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 53, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice0_y_net + ); + slice1 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 54, + new_msb => 107, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice1_y_net + ); + slice2 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 108, + new_msb => 161, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice2_y_net + ); + slice3 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 162, + new_msb => 215, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice3_y_net + ); + slice4 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 216, + new_msb => 269, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice4_y_net + ); + slice5 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 270, + new_msb => 323, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice5_y_net + ); + slice6 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 324, + new_msb => 377, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice6_y_net + ); + slice7 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 378, + new_msb => 431, + x_width => 432, + y_width => 54 + ) + port map ( + x => test_systolicfft_vhdl_black_box_o_net, + y => slice7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Concat +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_concat is + port ( + hi_1 : in std_logic_vector( 16-1 downto 0 ); + lo_1 : in std_logic_vector( 16-1 downto 0 ); + hi_2 : in std_logic_vector( 16-1 downto 0 ); + hi_3 : in std_logic_vector( 16-1 downto 0 ); + hi_4 : in std_logic_vector( 16-1 downto 0 ); + hi_5 : in std_logic_vector( 16-1 downto 0 ); + hi_6 : in std_logic_vector( 16-1 downto 0 ); + hi_7 : in std_logic_vector( 16-1 downto 0 ); + hi_8 : in std_logic_vector( 16-1 downto 0 ); + lo_2 : in std_logic_vector( 16-1 downto 0 ); + lo_3 : in std_logic_vector( 16-1 downto 0 ); + lo_4 : in std_logic_vector( 16-1 downto 0 ); + lo_5 : in std_logic_vector( 16-1 downto 0 ); + lo_6 : in std_logic_vector( 16-1 downto 0 ); + lo_7 : in std_logic_vector( 16-1 downto 0 ); + lo_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 32-1 downto 0 ); + out_2 : out std_logic_vector( 32-1 downto 0 ); + out_3 : out std_logic_vector( 32-1 downto 0 ); + out_4 : out std_logic_vector( 32-1 downto 0 ); + out_5 : out std_logic_vector( 32-1 downto 0 ); + out_6 : out std_logic_vector( 32-1 downto 0 ); + out_7 : out std_logic_vector( 32-1 downto 0 ); + out_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x256_vector_concat; +architecture structural of ssr_8x256_vector_concat is + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= concat0_y_net; + out_2 <= concat1_y_net; + out_3 <= concat2_y_net; + out_4 <= concat3_y_net; + out_5 <= concat4_y_net; + out_6 <= concat5_y_net; + out_7 <= concat6_y_net; + out_8 <= concat7_y_net; + reinterpret0_output_port_net_x0 <= hi_1; + reinterpret0_output_port_net <= lo_1; + reinterpret1_output_port_net_x0 <= hi_2; + reinterpret2_output_port_net_x0 <= hi_3; + reinterpret3_output_port_net_x0 <= hi_4; + reinterpret4_output_port_net_x0 <= hi_5; + reinterpret5_output_port_net_x0 <= hi_6; + reinterpret6_output_port_net_x0 <= hi_7; + reinterpret7_output_port_net_x0 <= hi_8; + reinterpret1_output_port_net <= lo_2; + reinterpret2_output_port_net <= lo_3; + reinterpret3_output_port_net <= lo_4; + reinterpret4_output_port_net <= lo_5; + reinterpret5_output_port_net <= lo_6; + reinterpret6_output_port_net <= lo_7; + reinterpret7_output_port_net <= lo_8; + concat0 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret0_output_port_net_x0, + in1 => reinterpret0_output_port_net, + y => concat0_y_net + ); + concat1 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret1_output_port_net_x0, + in1 => reinterpret1_output_port_net, + y => concat1_y_net + ); + concat2 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret2_output_port_net_x0, + in1 => reinterpret2_output_port_net, + y => concat2_y_net + ); + concat3 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret3_output_port_net_x0, + in1 => reinterpret3_output_port_net, + y => concat3_y_net + ); + concat4 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret4_output_port_net_x0, + in1 => reinterpret4_output_port_net, + y => concat4_y_net + ); + concat5 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret5_output_port_net_x0, + in1 => reinterpret5_output_port_net, + y => concat5_y_net + ); + concat6 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret6_output_port_net_x0, + in1 => reinterpret6_output_port_net, + y => concat6_y_net + ); + concat7 : entity xil_defaultlib.sysgen_concat_6128f842cc + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => reinterpret7_output_port_net_x0, + in1 => reinterpret7_output_port_net, + y => concat7_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Delay +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_delay is + port ( + d_1 : in std_logic_vector( 32-1 downto 0 ); + d_2 : in std_logic_vector( 32-1 downto 0 ); + d_3 : in std_logic_vector( 32-1 downto 0 ); + d_4 : in std_logic_vector( 32-1 downto 0 ); + d_5 : in std_logic_vector( 32-1 downto 0 ); + d_6 : in std_logic_vector( 32-1 downto 0 ); + d_7 : in std_logic_vector( 32-1 downto 0 ); + d_8 : in std_logic_vector( 32-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + q_1 : out std_logic_vector( 32-1 downto 0 ); + q_2 : out std_logic_vector( 32-1 downto 0 ); + q_3 : out std_logic_vector( 32-1 downto 0 ); + q_4 : out std_logic_vector( 32-1 downto 0 ); + q_5 : out std_logic_vector( 32-1 downto 0 ); + q_6 : out std_logic_vector( 32-1 downto 0 ); + q_7 : out std_logic_vector( 32-1 downto 0 ); + q_8 : out std_logic_vector( 32-1 downto 0 ) + ); +end ssr_8x256_vector_delay; +architecture structural of ssr_8x256_vector_delay is + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 32-1 downto 0 ); + signal ce_net : std_logic; + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal clk_net : std_logic; + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); +begin + q_1 <= delay0_q_net; + q_2 <= delay1_q_net; + q_3 <= delay2_q_net; + q_4 <= delay3_q_net; + q_5 <= delay4_q_net; + q_6 <= delay5_q_net; + q_7 <= delay6_q_net; + q_8 <= delay7_q_net; + concat0_y_net <= d_1; + concat1_y_net <= d_2; + concat2_y_net <= d_3; + concat3_y_net <= d_4; + concat4_y_net <= d_5; + concat5_y_net <= d_6; + concat6_y_net <= d_7; + concat7_y_net <= d_8; + clk_net <= clk_1; + ce_net <= ce_1; + delay0 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat0_y_net, + clk => clk_net, + ce => ce_net, + q => delay0_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat1_y_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net + ); + delay2 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat2_y_net, + clk => clk_net, + ce => ce_net, + q => delay2_q_net + ); + delay3 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat3_y_net, + clk => clk_net, + ce => ce_net, + q => delay3_q_net + ); + delay4 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat4_y_net, + clk => clk_net, + ce => ce_net, + q => delay4_q_net + ); + delay5 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat5_y_net, + clk => clk_net, + ce => ce_net, + q => delay5_q_net + ); + delay6 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat6_y_net, + clk => clk_net, + ce => ce_net, + q => delay6_q_net + ); + delay7 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 32 + ) + port map ( + en => '1', + rst => '0', + d => concat7_y_net, + clk => clk_net, + ce => ce_net, + q => delay7_q_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Reinterpret +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_reinterpret is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x256_vector_reinterpret; +architecture structural of ssr_8x256_vector_reinterpret is + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_re_0_net <= in_1; + i_re_1_net <= in_2; + i_re_2_net <= in_3; + i_re_3_net <= in_4; + i_re_4_net <= in_5; + i_re_5_net <= in_6; + i_re_6_net <= in_7; + i_re_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_re_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Reinterpret1 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_reinterpret1 is + port ( + in_1 : in std_logic_vector( 16-1 downto 0 ); + in_2 : in std_logic_vector( 16-1 downto 0 ); + in_3 : in std_logic_vector( 16-1 downto 0 ); + in_4 : in std_logic_vector( 16-1 downto 0 ); + in_5 : in std_logic_vector( 16-1 downto 0 ); + in_6 : in std_logic_vector( 16-1 downto 0 ); + in_7 : in std_logic_vector( 16-1 downto 0 ); + in_8 : in std_logic_vector( 16-1 downto 0 ); + out_1 : out std_logic_vector( 16-1 downto 0 ); + out_2 : out std_logic_vector( 16-1 downto 0 ); + out_3 : out std_logic_vector( 16-1 downto 0 ); + out_4 : out std_logic_vector( 16-1 downto 0 ); + out_5 : out std_logic_vector( 16-1 downto 0 ); + out_6 : out std_logic_vector( 16-1 downto 0 ); + out_7 : out std_logic_vector( 16-1 downto 0 ); + out_8 : out std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x256_vector_reinterpret1; +architecture structural of ssr_8x256_vector_reinterpret1 is + signal reinterpret3_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 16-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + i_im_0_net <= in_1; + i_im_1_net <= in_2; + i_im_2_net <= in_3; + i_im_3_net <= in_4; + i_im_4_net <= in_5; + i_im_5_net <= in_6; + i_im_6_net <= in_7; + i_im_7_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_0_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_1_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_2_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_3_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_4_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_5_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_6_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_3bad6996c0 + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => i_im_7_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Reinterpret2 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_reinterpret2 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_reinterpret2; +architecture structural of ssr_8x256_vector_reinterpret2 is + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Reinterpret3 +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_reinterpret3 is + port ( + in_1 : in std_logic_vector( 27-1 downto 0 ); + in_2 : in std_logic_vector( 27-1 downto 0 ); + in_3 : in std_logic_vector( 27-1 downto 0 ); + in_4 : in std_logic_vector( 27-1 downto 0 ); + in_5 : in std_logic_vector( 27-1 downto 0 ); + in_6 : in std_logic_vector( 27-1 downto 0 ); + in_7 : in std_logic_vector( 27-1 downto 0 ); + in_8 : in std_logic_vector( 27-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_reinterpret3; +architecture structural of ssr_8x256_vector_reinterpret3 is + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); +begin + out_1 <= reinterpret0_output_port_net; + out_2 <= reinterpret1_output_port_net; + out_3 <= reinterpret2_output_port_net; + out_4 <= reinterpret3_output_port_net; + out_5 <= reinterpret4_output_port_net; + out_6 <= reinterpret5_output_port_net; + out_7 <= reinterpret6_output_port_net; + out_8 <= reinterpret7_output_port_net; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + reinterpret0 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice0_y_net, + output_port => reinterpret0_output_port_net + ); + reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice1_y_net, + output_port => reinterpret1_output_port_net + ); + reinterpret2 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice2_y_net, + output_port => reinterpret2_output_port_net + ); + reinterpret3 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice3_y_net, + output_port => reinterpret3_output_port_net + ); + reinterpret4 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice4_y_net, + output_port => reinterpret4_output_port_net + ); + reinterpret5 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice5_y_net, + output_port => reinterpret5_output_port_net + ); + reinterpret6 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice6_y_net, + output_port => reinterpret6_output_port_net + ); + reinterpret7 : entity xil_defaultlib.sysgen_reinterpret_9cd5a6908e + port map ( + clk => '0', + ce => '0', + clr => '0', + input_port => slice7_y_net, + output_port => reinterpret7_output_port_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Slice Im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_slice_im is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_slice_im; +architecture structural of ssr_8x256_vector_slice_im is + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 27, + new_msb => 53, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector Slice Re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_slice_re is + port ( + in_1 : in std_logic_vector( 54-1 downto 0 ); + in_2 : in std_logic_vector( 54-1 downto 0 ); + in_3 : in std_logic_vector( 54-1 downto 0 ); + in_4 : in std_logic_vector( 54-1 downto 0 ); + in_5 : in std_logic_vector( 54-1 downto 0 ); + in_6 : in std_logic_vector( 54-1 downto 0 ); + in_7 : in std_logic_vector( 54-1 downto 0 ); + in_8 : in std_logic_vector( 54-1 downto 0 ); + out_1 : out std_logic_vector( 27-1 downto 0 ); + out_2 : out std_logic_vector( 27-1 downto 0 ); + out_3 : out std_logic_vector( 27-1 downto 0 ); + out_4 : out std_logic_vector( 27-1 downto 0 ); + out_5 : out std_logic_vector( 27-1 downto 0 ); + out_6 : out std_logic_vector( 27-1 downto 0 ); + out_7 : out std_logic_vector( 27-1 downto 0 ); + out_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_slice_re; +architecture structural of ssr_8x256_vector_slice_re is + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 54-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 54-1 downto 0 ); +begin + out_1 <= slice0_y_net_x0; + out_2 <= slice1_y_net_x0; + out_3 <= slice2_y_net_x0; + out_4 <= slice3_y_net_x0; + out_5 <= slice4_y_net_x0; + out_6 <= slice5_y_net_x0; + out_7 <= slice6_y_net_x0; + out_8 <= slice7_y_net_x0; + slice0_y_net <= in_1; + slice1_y_net <= in_2; + slice2_y_net <= in_3; + slice3_y_net <= in_4; + slice4_y_net <= in_5; + slice5_y_net <= in_6; + slice6_y_net <= in_7; + slice7_y_net <= in_8; + slice0 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice0_y_net, + y => slice0_y_net_x0 + ); + slice1 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice1_y_net, + y => slice1_y_net_x0 + ); + slice2 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice2_y_net, + y => slice2_y_net_x0 + ); + slice3 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice3_y_net, + y => slice3_y_net_x0 + ); + slice4 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice4_y_net, + y => slice4_y_net_x0 + ); + slice5 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice5_y_net, + y => slice5_y_net_x0 + ); + slice6 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice6_y_net, + y => slice6_y_net_x0 + ); + slice7 : entity xil_defaultlib.ssr_8x256_xlslice + generic map ( + new_lsb => 0, + new_msb => 26, + x_width => 54, + y_width => 27 + ) + port map ( + x => slice7_y_net, + y => slice7_y_net_x0 + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT/Vector2Scalar +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector2scalar is + port ( + i_1 : in std_logic_vector( 32-1 downto 0 ); + i_2 : in std_logic_vector( 32-1 downto 0 ); + i_3 : in std_logic_vector( 32-1 downto 0 ); + i_4 : in std_logic_vector( 32-1 downto 0 ); + i_5 : in std_logic_vector( 32-1 downto 0 ); + i_6 : in std_logic_vector( 32-1 downto 0 ); + i_7 : in std_logic_vector( 32-1 downto 0 ); + i_8 : in std_logic_vector( 32-1 downto 0 ); + o : out std_logic_vector( 256-1 downto 0 ) + ); +end ssr_8x256_vector2scalar; +architecture structural of ssr_8x256_vector2scalar is + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); +begin + o <= concat1_y_net; + delay0_q_net <= i_1; + delay1_q_net <= i_2; + delay2_q_net <= i_3; + delay3_q_net <= i_4; + delay4_q_net <= i_5; + delay5_q_net <= i_6; + delay6_q_net <= i_7; + delay7_q_net <= i_8; + concat1 : entity xil_defaultlib.sysgen_concat_c6ccfb3c89 + port map ( + clk => '0', + ce => '0', + clr => '0', + in0 => delay7_q_net, + in1 => delay6_q_net, + in2 => delay5_q_net, + in3 => delay4_q_net, + in4 => delay3_q_net, + in5 => delay2_q_net, + in6 => delay1_q_net, + in7 => delay0_q_net, + y => concat1_y_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/Vector FFT +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_vector_fft is + port ( + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + vi : in std_logic_vector( 1-1 downto 0 ); + si : in std_logic_vector( 8-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_8 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_8 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + vo : out std_logic; + so : out std_logic_vector( 8-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_8 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_8 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_vector_fft; +architecture structural of ssr_8x256_vector_fft is + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_scale_net : std_logic_vector( 8-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 8-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_vo_net : std_logic; + signal reinterpret0_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret4_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal concat6_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret6_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_o_net : std_logic_vector( 432-1 downto 0 ); + signal slice3_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal slice5_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal concat7_y_net : std_logic_vector( 32-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal concat3_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret7_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal concat0_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret4_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal concat2_y_net : std_logic_vector( 32-1 downto 0 ); + signal reinterpret5_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal slice6_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal reinterpret6_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret7_output_port_net_x2 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret3_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net_x1 : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal ce_net : std_logic; + signal slice4_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal slice0_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal concat1_y_net_x0 : std_logic_vector( 32-1 downto 0 ); + signal slice1_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal concat4_y_net : std_logic_vector( 32-1 downto 0 ); + signal concat5_y_net : std_logic_vector( 32-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal slice2_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal clk_net : std_logic; + signal slice7_y_net_x1 : std_logic_vector( 54-1 downto 0 ); + signal delay1_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice2_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice7_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice2_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice0_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay_q_net : std_logic_vector( 1-1 downto 0 ); + signal delay2_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice0_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice4_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay0_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice1_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice5_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay5_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice6_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay1_q_net_x0 : std_logic_vector( 8-1 downto 0 ); + signal delay4_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice1_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal delay3_q_net : std_logic_vector( 32-1 downto 0 ); + signal delay6_q_net : std_logic_vector( 32-1 downto 0 ); + signal slice7_y_net : std_logic_vector( 27-1 downto 0 ); + signal delay7_q_net : std_logic_vector( 32-1 downto 0 ); + signal concat1_y_net : std_logic_vector( 256-1 downto 0 ); + signal slice4_y_net : std_logic_vector( 27-1 downto 0 ); + signal slice3_y_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal slice6_y_net_x0 : std_logic_vector( 27-1 downto 0 ); +begin + o_re_1 <= reinterpret0_output_port_net_x0; + o_im_1 <= reinterpret0_output_port_net; + vo <= test_systolicfft_vhdl_black_box_vo_net; + so <= test_systolicfft_vhdl_black_box_so_net; + o_re_2 <= reinterpret1_output_port_net_x0; + o_re_3 <= reinterpret2_output_port_net_x0; + o_re_4 <= reinterpret3_output_port_net_x0; + o_re_5 <= reinterpret4_output_port_net_x0; + o_re_6 <= reinterpret5_output_port_net_x0; + o_re_7 <= reinterpret6_output_port_net_x0; + o_re_8 <= reinterpret7_output_port_net_x0; + o_im_2 <= reinterpret1_output_port_net; + o_im_3 <= reinterpret2_output_port_net; + o_im_4 <= reinterpret3_output_port_net; + o_im_5 <= reinterpret4_output_port_net; + o_im_6 <= reinterpret5_output_port_net; + o_im_7 <= reinterpret6_output_port_net; + o_im_8 <= reinterpret7_output_port_net; + i_re_0_net <= i_re_1; + i_im_0_net <= i_im_1; + i_valid_net <= vi; + i_scale_net <= si; + i_re_1_net <= i_re_2; + i_re_2_net <= i_re_3; + i_re_3_net <= i_re_4; + i_re_4_net <= i_re_5; + i_re_5_net <= i_re_6; + i_re_6_net <= i_re_7; + i_re_7_net <= i_re_8; + i_im_1_net <= i_im_2; + i_im_2_net <= i_im_3; + i_im_3_net <= i_im_4; + i_im_4_net <= i_im_5; + i_im_5_net <= i_im_6; + i_im_6_net <= i_im_7; + i_im_7_net <= i_im_8; + clk_net <= clk_1; + ce_net <= ce_1; + scalar2vector : entity xil_defaultlib.ssr_8x256_scalar2vector + port map ( + i => test_systolicfft_vhdl_black_box_o_net, + o_1 => slice0_y_net_x1, + o_2 => slice1_y_net_x1, + o_3 => slice2_y_net_x1, + o_4 => slice3_y_net_x1, + o_5 => slice4_y_net_x1, + o_6 => slice5_y_net_x1, + o_7 => slice6_y_net_x1, + o_8 => slice7_y_net_x1 + ); + vector_concat : entity xil_defaultlib.ssr_8x256_vector_concat + port map ( + hi_1 => reinterpret0_output_port_net_x1, + lo_1 => reinterpret0_output_port_net_x2, + hi_2 => reinterpret1_output_port_net_x1, + hi_3 => reinterpret2_output_port_net_x1, + hi_4 => reinterpret3_output_port_net_x1, + hi_5 => reinterpret4_output_port_net_x1, + hi_6 => reinterpret5_output_port_net_x1, + hi_7 => reinterpret6_output_port_net_x1, + hi_8 => reinterpret7_output_port_net_x1, + lo_2 => reinterpret1_output_port_net_x2, + lo_3 => reinterpret2_output_port_net_x2, + lo_4 => reinterpret3_output_port_net_x2, + lo_5 => reinterpret4_output_port_net_x2, + lo_6 => reinterpret5_output_port_net_x2, + lo_7 => reinterpret6_output_port_net_x2, + lo_8 => reinterpret7_output_port_net_x2, + out_1 => concat0_y_net, + out_2 => concat1_y_net_x0, + out_3 => concat2_y_net, + out_4 => concat3_y_net, + out_5 => concat4_y_net, + out_6 => concat5_y_net, + out_7 => concat6_y_net, + out_8 => concat7_y_net + ); + vector_delay : entity xil_defaultlib.ssr_8x256_vector_delay + port map ( + d_1 => concat0_y_net, + d_2 => concat1_y_net_x0, + d_3 => concat2_y_net, + d_4 => concat3_y_net, + d_5 => concat4_y_net, + d_6 => concat5_y_net, + d_7 => concat6_y_net, + d_8 => concat7_y_net, + clk_1 => clk_net, + ce_1 => ce_net, + q_1 => delay0_q_net, + q_2 => delay1_q_net, + q_3 => delay2_q_net, + q_4 => delay3_q_net, + q_5 => delay4_q_net, + q_6 => delay5_q_net, + q_7 => delay6_q_net, + q_8 => delay7_q_net + ); + vector_reinterpret : entity xil_defaultlib.ssr_8x256_vector_reinterpret + port map ( + in_1 => i_re_0_net, + in_2 => i_re_1_net, + in_3 => i_re_2_net, + in_4 => i_re_3_net, + in_5 => i_re_4_net, + in_6 => i_re_5_net, + in_7 => i_re_6_net, + in_8 => i_re_7_net, + out_1 => reinterpret0_output_port_net_x2, + out_2 => reinterpret1_output_port_net_x2, + out_3 => reinterpret2_output_port_net_x2, + out_4 => reinterpret3_output_port_net_x2, + out_5 => reinterpret4_output_port_net_x2, + out_6 => reinterpret5_output_port_net_x2, + out_7 => reinterpret6_output_port_net_x2, + out_8 => reinterpret7_output_port_net_x2 + ); + vector_reinterpret1 : entity xil_defaultlib.ssr_8x256_vector_reinterpret1 + port map ( + in_1 => i_im_0_net, + in_2 => i_im_1_net, + in_3 => i_im_2_net, + in_4 => i_im_3_net, + in_5 => i_im_4_net, + in_6 => i_im_5_net, + in_7 => i_im_6_net, + in_8 => i_im_7_net, + out_1 => reinterpret0_output_port_net_x1, + out_2 => reinterpret1_output_port_net_x1, + out_3 => reinterpret2_output_port_net_x1, + out_4 => reinterpret3_output_port_net_x1, + out_5 => reinterpret4_output_port_net_x1, + out_6 => reinterpret5_output_port_net_x1, + out_7 => reinterpret6_output_port_net_x1, + out_8 => reinterpret7_output_port_net_x1 + ); + vector_reinterpret2 : entity xil_defaultlib.ssr_8x256_vector_reinterpret2 + port map ( + in_1 => slice0_y_net, + in_2 => slice1_y_net, + in_3 => slice2_y_net, + in_4 => slice3_y_net, + in_5 => slice4_y_net, + in_6 => slice5_y_net, + in_7 => slice6_y_net, + in_8 => slice7_y_net, + out_1 => reinterpret0_output_port_net_x0, + out_2 => reinterpret1_output_port_net_x0, + out_3 => reinterpret2_output_port_net_x0, + out_4 => reinterpret3_output_port_net_x0, + out_5 => reinterpret4_output_port_net_x0, + out_6 => reinterpret5_output_port_net_x0, + out_7 => reinterpret6_output_port_net_x0, + out_8 => reinterpret7_output_port_net_x0 + ); + vector_reinterpret3 : entity xil_defaultlib.ssr_8x256_vector_reinterpret3 + port map ( + in_1 => slice0_y_net_x0, + in_2 => slice1_y_net_x0, + in_3 => slice2_y_net_x0, + in_4 => slice3_y_net_x0, + in_5 => slice4_y_net_x0, + in_6 => slice5_y_net_x0, + in_7 => slice6_y_net_x0, + in_8 => slice7_y_net_x0, + out_1 => reinterpret0_output_port_net, + out_2 => reinterpret1_output_port_net, + out_3 => reinterpret2_output_port_net, + out_4 => reinterpret3_output_port_net, + out_5 => reinterpret4_output_port_net, + out_6 => reinterpret5_output_port_net, + out_7 => reinterpret6_output_port_net, + out_8 => reinterpret7_output_port_net + ); + vector_slice_im : entity xil_defaultlib.ssr_8x256_vector_slice_im + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net_x0, + out_2 => slice1_y_net_x0, + out_3 => slice2_y_net_x0, + out_4 => slice3_y_net_x0, + out_5 => slice4_y_net_x0, + out_6 => slice5_y_net_x0, + out_7 => slice6_y_net_x0, + out_8 => slice7_y_net_x0 + ); + vector_slice_re : entity xil_defaultlib.ssr_8x256_vector_slice_re + port map ( + in_1 => slice0_y_net_x1, + in_2 => slice1_y_net_x1, + in_3 => slice2_y_net_x1, + in_4 => slice3_y_net_x1, + in_5 => slice4_y_net_x1, + in_6 => slice5_y_net_x1, + in_7 => slice6_y_net_x1, + in_8 => slice7_y_net_x1, + out_1 => slice0_y_net, + out_2 => slice1_y_net, + out_3 => slice2_y_net, + out_4 => slice3_y_net, + out_5 => slice4_y_net, + out_6 => slice5_y_net, + out_7 => slice6_y_net, + out_8 => slice7_y_net + ); + vector2scalar : entity xil_defaultlib.ssr_8x256_vector2scalar + port map ( + i_1 => delay0_q_net, + i_2 => delay1_q_net, + i_3 => delay2_q_net, + i_4 => delay3_q_net, + i_5 => delay4_q_net, + i_6 => delay5_q_net, + i_7 => delay6_q_net, + i_8 => delay7_q_net, + o => concat1_y_net + ); + delay : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 1 + ) + port map ( + en => '1', + rst => '0', + d => i_valid_net, + clk => clk_net, + ce => ce_net, + q => delay_q_net + ); + delay1 : entity xil_defaultlib.ssr_8x256_xldelay + generic map ( + latency => 4, + reg_retiming => 0, + reset => 0, + width => 8 + ) + port map ( + en => '1', + rst => '0', + d => i_scale_net, + clk => clk_net, + ce => ce_net, + q => delay1_q_net_x0 + ); + test_systolicfft_vhdl_black_box : entity xil_defaultlib.WRAPPER_VECTOR_FFT_c48f0cd3f27fd6fdac4ed316c161272e + generic map ( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 8, + N => 256, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map ( + i => concat1_y_net, + vi => delay_q_net(0), + si => delay1_q_net_x0, + CLK => clk_net, + CE => ce_net, + o => test_systolicfft_vhdl_black_box_o_net, + vo => test_systolicfft_vhdl_black_box_vo_net, + so => test_systolicfft_vhdl_black_box_so_net + ); +end structural; +-- Generated from Simulink block ssr_8x256/i_im +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_i_im is + port ( + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x256_i_im; +architecture structural of ssr_8x256_i_im is + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); +begin + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; +end structural; +-- Generated from Simulink block ssr_8x256/i_re +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_i_re is + port ( + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ) + ); +end ssr_8x256_i_re; +architecture structural of ssr_8x256_i_re is + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); +begin + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; +end structural; +-- Generated from Simulink block ssr_8x256_struct +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_struct is + port ( + i_scale : in std_logic_vector( 8-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk_1 : in std_logic; + ce_1 : in std_logic; + o_scale : out std_logic_vector( 8-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256_struct; +architecture structural of ssr_8x256_struct is + signal i_im_6_net : std_logic_vector( 16-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_vo_net : std_logic_vector( 1-1 downto 0 ); + signal i_scale_net : std_logic_vector( 8-1 downto 0 ); + signal i_im_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_2_net : std_logic_vector( 16-1 downto 0 ); + signal test_systolicfft_vhdl_black_box_so_net : std_logic_vector( 8-1 downto 0 ); + signal i_re_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_4_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_2_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_5_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_6_net : std_logic_vector( 16-1 downto 0 ); + signal i_valid_net : std_logic_vector( 1-1 downto 0 ); + signal i_im_7_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_7_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret0_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_re_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret2_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_im_3_net : std_logic_vector( 16-1 downto 0 ); + signal i_re_1_net : std_logic_vector( 16-1 downto 0 ); + signal i_im_0_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret1_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal i_im_1_net : std_logic_vector( 16-1 downto 0 ); + signal reinterpret5_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret7_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal clk_net : std_logic; + signal ce_net : std_logic; + signal reinterpret6_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret1_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret4_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret0_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret5_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); + signal reinterpret3_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret6_output_port_net : std_logic_vector( 27-1 downto 0 ); + signal reinterpret2_output_port_net_x0 : std_logic_vector( 27-1 downto 0 ); +begin + i_scale_net <= i_scale; + i_valid_net <= i_valid; + o_scale <= test_systolicfft_vhdl_black_box_so_net; + o_valid <= test_systolicfft_vhdl_black_box_vo_net; + i_im_0_net <= i_im_0; + i_im_1_net <= i_im_1; + i_im_2_net <= i_im_2; + i_im_3_net <= i_im_3; + i_im_4_net <= i_im_4; + i_im_5_net <= i_im_5; + i_im_6_net <= i_im_6; + i_im_7_net <= i_im_7; + i_re_0_net <= i_re_0; + i_re_1_net <= i_re_1; + i_re_2_net <= i_re_2; + i_re_3_net <= i_re_3; + i_re_4_net <= i_re_4; + i_re_5_net <= i_re_5; + i_re_6_net <= i_re_6; + i_re_7_net <= i_re_7; + o_im_0 <= reinterpret0_output_port_net; + o_im_1 <= reinterpret1_output_port_net; + o_im_2 <= reinterpret2_output_port_net; + o_im_3 <= reinterpret3_output_port_net; + o_im_4 <= reinterpret4_output_port_net_x0; + o_im_5 <= reinterpret5_output_port_net; + o_im_6 <= reinterpret6_output_port_net; + o_im_7 <= reinterpret7_output_port_net; + o_re_0 <= reinterpret0_output_port_net_x0; + o_re_1 <= reinterpret1_output_port_net_x0; + o_re_2 <= reinterpret2_output_port_net_x0; + o_re_3 <= reinterpret3_output_port_net_x0; + o_re_4 <= reinterpret4_output_port_net; + o_re_5 <= reinterpret5_output_port_net_x0; + o_re_6 <= reinterpret6_output_port_net_x0; + o_re_7 <= reinterpret7_output_port_net_x0; + clk_net <= clk_1; + ce_net <= ce_1; + vector_fft : entity xil_defaultlib.ssr_8x256_vector_fft + port map ( + i_re_1 => i_re_0_net, + i_im_1 => i_im_0_net, + vi => i_valid_net, + si => i_scale_net, + i_re_2 => i_re_1_net, + i_re_3 => i_re_2_net, + i_re_4 => i_re_3_net, + i_re_5 => i_re_4_net, + i_re_6 => i_re_5_net, + i_re_7 => i_re_6_net, + i_re_8 => i_re_7_net, + i_im_2 => i_im_1_net, + i_im_3 => i_im_2_net, + i_im_4 => i_im_3_net, + i_im_5 => i_im_4_net, + i_im_6 => i_im_5_net, + i_im_7 => i_im_6_net, + i_im_8 => i_im_7_net, + clk_1 => clk_net, + ce_1 => ce_net, + o_re_1 => reinterpret0_output_port_net_x0, + o_im_1 => reinterpret0_output_port_net, + vo => test_systolicfft_vhdl_black_box_vo_net(0), + so => test_systolicfft_vhdl_black_box_so_net, + o_re_2 => reinterpret1_output_port_net_x0, + o_re_3 => reinterpret2_output_port_net_x0, + o_re_4 => reinterpret3_output_port_net_x0, + o_re_5 => reinterpret4_output_port_net, + o_re_6 => reinterpret5_output_port_net_x0, + o_re_7 => reinterpret6_output_port_net_x0, + o_re_8 => reinterpret7_output_port_net_x0, + o_im_2 => reinterpret1_output_port_net, + o_im_3 => reinterpret2_output_port_net, + o_im_4 => reinterpret3_output_port_net, + o_im_5 => reinterpret4_output_port_net_x0, + o_im_6 => reinterpret5_output_port_net, + o_im_7 => reinterpret6_output_port_net, + o_im_8 => reinterpret7_output_port_net + ); + i_im : entity xil_defaultlib.ssr_8x256_i_im + port map ( + i_im_0 => i_im_0_net, + i_im_1 => i_im_1_net, + i_im_2 => i_im_2_net, + i_im_3 => i_im_3_net, + i_im_4 => i_im_4_net, + i_im_5 => i_im_5_net, + i_im_6 => i_im_6_net, + i_im_7 => i_im_7_net + ); + i_re : entity xil_defaultlib.ssr_8x256_i_re + port map ( + i_re_0 => i_re_0_net, + i_re_1 => i_re_1_net, + i_re_2 => i_re_2_net, + i_re_3 => i_re_3_net, + i_re_4 => i_re_4_net, + i_re_5 => i_re_5_net, + i_re_6 => i_re_6_net, + i_re_7 => i_re_7_net + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256_default_clock_driver is + port ( + ssr_8x256_sysclk : in std_logic; + ssr_8x256_sysce : in std_logic; + ssr_8x256_sysclr : in std_logic; + ssr_8x256_clk1 : out std_logic; + ssr_8x256_ce1 : out std_logic + ); +end ssr_8x256_default_clock_driver; +architecture structural of ssr_8x256_default_clock_driver is +begin + clockdriver : entity xil_defaultlib.xlclockdriver + generic map ( + period => 1, + log_2_period => 1 + ) + port map ( + sysclk => ssr_8x256_sysclk, + sysce => ssr_8x256_sysce, + sysclr => ssr_8x256_sysclr, + clk => ssr_8x256_clk1, + ce => ssr_8x256_ce1 + ); +end structural; +-- Generated from Simulink block +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; +entity ssr_8x256 is + port ( + i_scale : in std_logic_vector( 8-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + clk : in std_logic; + o_scale : out std_logic_vector( 8-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ) + ); +end ssr_8x256; +architecture structural of ssr_8x256 is + attribute core_generation_info : string; + attribute core_generation_info of structural : architecture is "ssr_8x256,sysgen_core_2019_2,{,compilation=HDL Netlist,block_icon_display=Default,family=zynquplusRFSOC,part=xczu28dr,speed=-2-e,package=ffvg1517,synthesis_language=vhdl,hdl_library=xil_defaultlib,synthesis_strategy=Vivado Synthesis Defaults,implementation_strategy=Vivado Implementation Defaults,testbench=0,interface_doc=0,ce_clr=0,clock_period=10,system_simulink_period=1,waveform_viewer=0,axilite_interface=0,ip_catalog_plugin=0,hwcosim_burst_mode=0,simulation_time=10,blackbox2=1,concat=9,delay=10,reinterpret=32,slice=24,}"; + signal clk_1_net : std_logic; + signal ce_1_net : std_logic; +begin + ssr_8x256_default_clock_driver : entity xil_defaultlib.ssr_8x256_default_clock_driver + port map ( + ssr_8x256_sysclk => clk, + ssr_8x256_sysce => '1', + ssr_8x256_sysclr => '0', + ssr_8x256_clk1 => clk_1_net, + ssr_8x256_ce1 => ce_1_net + ); + ssr_8x256_struct : entity xil_defaultlib.ssr_8x256_struct + port map ( + i_scale => i_scale, + i_valid => i_valid, + i_im_0 => i_im_0, + i_im_1 => i_im_1, + i_im_2 => i_im_2, + i_im_3 => i_im_3, + i_im_4 => i_im_4, + i_im_5 => i_im_5, + i_im_6 => i_im_6, + i_im_7 => i_im_7, + i_re_0 => i_re_0, + i_re_1 => i_re_1, + i_re_2 => i_re_2, + i_re_3 => i_re_3, + i_re_4 => i_re_4, + i_re_5 => i_re_5, + i_re_6 => i_re_6, + i_re_7 => i_re_7, + clk_1 => clk_1_net, + ce_1 => ce_1_net, + o_scale => o_scale, + o_valid => o_valid, + o_im_0 => o_im_0, + o_im_1 => o_im_1, + o_im_2 => o_im_2, + o_im_3 => o_im_3, + o_im_4 => o_im_4, + o_im_5 => o_im_5, + o_im_6 => o_im_6, + o_im_7 => o_im_7, + o_re_0 => o_re_0, + o_re_1 => o_re_1, + o_re_2 => o_re_2, + o_re_3 => o_re_3, + o_re_4 => o_re_4, + o_re_5 => o_re_5, + o_re_6 => o_re_6, + o_re_7 => o_re_7 + ); +end structural; diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd new file mode 100644 index 0000000..9ed7c14 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/ssr_8x256_entity_declarations.vhd @@ -0,0 +1,6159 @@ +------------------------------------------------------------------- +-- System Generator version 2019.2 VHDL source file. +-- +-- Copyright(C) 2019 by Xilinx, Inc. All rights reserved. This +-- text/file contains proprietary, confidential information of Xilinx, +-- Inc., is distributed under license from Xilinx, Inc., and may be used, +-- copied and/or disclosed only pursuant to the terms of a valid license +-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use +-- this text/file solely for design, simulation, implementation and +-- creation of design files limited to Xilinx devices or technologies. +-- Use with non-Xilinx devices or technologies is expressly prohibited +-- and immediately terminates your license unless covered by a separate +-- agreement. +-- +-- Xilinx is providing this design, code, or information "as is" solely +-- for use in developing programs and solutions for Xilinx devices. By +-- providing this design, code, or information as one possible +-- implementation of this feature, application or standard, Xilinx is +-- making no representation that this implementation is free from any +-- claims of infringement. You are responsible for obtaining any rights +-- you may require for your implementation. Xilinx expressly disclaims +-- any warranty whatsoever with respect to the adequacy of the +-- implementation, including but not limited to warranties of +-- merchantability or fitness for a particular purpose. +-- +-- Xilinx products are not intended for use in life support appliances, +-- devices, or systems. Use in such applications is expressly prohibited. +-- +-- Any modifications that are made to the source code are done at the user's +-- sole risk and will be unsupported. +-- +-- This copyright and support notice must be retained as part of this +-- text at all times. (c) Copyright 1995-2019 Xilinx, Inc. All rights +-- reserved. +------------------------------------------------------------------- + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x256_xldelay is + generic(width : integer := -1; + latency : integer := -1; + reg_retiming : integer := 0; + reset : integer := 0); + port(d : in std_logic_vector (width-1 downto 0); + ce : in std_logic; + clk : in std_logic; + en : in std_logic; + rst : in std_logic; + q : out std_logic_vector (width-1 downto 0)); + +end ssr_8x256_xldelay; + +architecture behavior of ssr_8x256_xldelay is + component synth_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; -- end component synth_reg + + component synth_reg_reg + generic (width : integer; + latency : integer); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); + end component; + + signal internal_ce : std_logic; + +begin + internal_ce <= ce and en; + + srl_delay: if ((reg_retiming = 0) and (reset = 0)) or (latency < 1) generate + synth_reg_srl_inst : synth_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => '0', + clk => clk, + o => q); + end generate srl_delay; + + reg_delay: if ((reg_retiming = 1) or (reset = 1)) and (latency >= 1) generate + synth_reg_reg_inst : synth_reg_reg + generic map ( + width => width, + latency => latency) + port map ( + i => d, + ce => internal_ce, + clr => rst, + clk => clk, + o => q); + end generate reg_delay; +end architecture behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: COMPLEX_FIXED_PKG.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Package Name: COMPLEX_FIXED_PKG +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Unconstrained Size Vectors and Matrices of Complex Arbitrary Precision Fixed Point Numbers +-- +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +package COMPLEX_FIXED_PKG is + type BOOLEAN_VECTOR is array(NATURAL range <>) of BOOLEAN; + type INTEGER_VECTOR is array(NATURAL range <>) of INTEGER; + type REAL_VECTOR is array(NATURAL range <>) of REAL; +--2008 type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED; + type COMPLEX_VECTOR is array(INTEGER range <>) of COMPLEX; + + type SFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point signed number, like SIGNED but lower bound can be negative +--2008 type SFIXED_VECTOR is array(INTEGER range <>) of SFIXED; -- unconstrained array of SFIXED +--2008 type CFIXED is record RE,IM:SFIXED; end record; -- arbitrary precision fixed point complex signed number +--2008 type CFIXED_VECTOR is array(INTEGER range <>) of CFIXED; -- unconstrained array of CFIXED +--2008 type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR; -- unconstrained array of CFIXED_VECTOR + type SFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of SFIXED, vector size must be given by a separate generic + type CFIXED is array(INTEGER range <>) of STD_LOGIC; -- arbitrary precision fixed point complex signed number, CFIXED'low is always even and CFIXED'high is always odd + type CFIXED_VECTOR is array(INTEGER range <>) of STD_LOGIC; -- unconstrained array of CFIXED, vector size must be given by a separate generic + +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED; -- returns the CFIXED range for X(K) +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).RE +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED; -- returns the CFIXED range for X(K).IM + + function MIN(A,B:INTEGER) return INTEGER; + function MIN(A,B,C:INTEGER) return INTEGER; + function MIN(A,B,C,D:INTEGER) return INTEGER; + function MED(A,B,C:INTEGER) return INTEGER; + function MAX(A,B:INTEGER) return INTEGER; + function MAX(A,B,C:INTEGER) return INTEGER; + function MAX(A,B,C,D:INTEGER) return INTEGER; + function "+"(X,Y:SFIXED) return SFIXED; -- full precision add with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X,Y:SFIXED) return SFIXED; -- full precision subtract with SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)) result + function "-"(X:SFIXED) return SFIXED; -- full precision negate with SFIXED(X'high+1 downto X'low) result + function "*"(X,Y:SFIXED) return SFIXED; -- full precision multiply with SFIXED(X'high+Y'high+1 downto X'low+Y'low) result + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED; -- multiply by 0 or 1 with SFIXED(X'high downto X'low) result + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED; -- resizes X and returns SFIXED(H downto L) + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED; -- resizes X to match HL and returns SFIXED(HL'high downto HL'low) + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED; -- returns SFIXED(X'high+N downto X'low+N) result + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED; -- returns SFIXED(H downto L) result + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED; -- returns SFIXED(HL'high downto HL'low) result + function TO_REAL(S:SFIXED) return REAL; -- returns REAL result +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED; -- returns element K out of an N-size array X + + function RE(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vRE(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure RE(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function IM(X:CFIXED) return SFIXED; -- returns SFIXED(X'high/2 downto X'low/2) result +-- procedure vIM(X:out CFIXED;S:SFIXED); -- use when X is a variable, X'low is always even and X'high is always odd +-- procedure IM(signal X:out CFIXED;S:SFIXED); -- use when X is a signal, X'low is always even and X'high is always odd + function "+"(X,Y:CFIXED) return CFIXED; -- full precision add with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "-"(X,Y:CFIXED) return CFIXED; -- full precision subtract with CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function "*"(X,Y:CFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high+2 downto X'low+Y'low) result + function "*"(X:CFIXED;Y:SFIXED) return CFIXED; -- full precision multiply with CFIXED(X'high+Y'high downto X'low+Y'low) result + function "*"(X:SFIXED;Y:CFIXED) return CFIXED; + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED; -- resizes X and returns CFIXED(H downto L) + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED; -- resizes X to match HL and returns CFIXED(HL'high downto HL'low) + function PLUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function "-"(X:CFIXED) return CFIXED; -- full precision negate with CFIXED(X'high+2 downto X'low) result + function MINUS_i_TIMES(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED; -- returns CFIXED(MAX(X'high,Y'high)+2 downto MIN(X'low,Y'low)) result + function SWAP(X:CFIXED) return CFIXED; -- returns CFIXED(X'high downto X'low) result + function CONJ(X:CFIXED) return CFIXED; -- returns CFIXED(X'high+2 downto X'low) result + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high-N downto X'low-N) result + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED; -- returns CFIXED(X'high+N downto X'low+N) result + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED; -- returns CFIXED(H downto L) result + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED; -- returns CFIXED(HL'high downto HL'low) result + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED; -- returns CFIXED(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_CFIXED(R,I:SFIXED) return CFIXED; -- returns CFIXED(2*MAX(R'high,I'high)+1 downto 2*MIN(R'low,I'low)) result + function TO_COMPLEX(C:CFIXED) return COMPLEX; -- returns COMPLEX result + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR; -- returns CFIXED_VECTOR(RE(HL.RE'high downto HL.RE'low),IM(RE(HL.IM'high downto HL.IM'low)) result + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR; -- returns COMPLEX_VECTOR result + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR; -- returns R*C + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED; -- returns element K out of an N-size array X + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a variable, set element K out of an N-size array X to C + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED); -- use when X is a signal, set element K out of an N-size array X to C + + function LOG2(N:INTEGER) return INTEGER; -- returns ceil(log2(N)) +end COMPLEX_FIXED_PKG; + +package body COMPLEX_FIXED_PKG is +-- function ELEMENT(X:CFIXED;K,N:INTEGER) return CFIXED is -- returns the CFIXED range for X(K) +-- variable O:CFIXED(X'length/N*(K+1)-1+X'low/N downto X'length/N*K+X'low/N); +-- begin +-- return O; +-- end; + +-- function RE(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).RE +-- begin +-- return RE(ELEMENT(X,K,N)); +-- end; + +-- function IM(X:CFIXED;K,N:INTEGER) return SFIXED is -- returns the CFIXED range for X(K).IM +-- begin +-- return IM(ELEMENT(X,K,N)); +-- end; + + function MIN(A,B:INTEGER) return INTEGER is + begin + if AB then + return A; + else + return B; + end if; + end; + + function MAX(A,B,C:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),C); + end; + + function MAX(A,B,C,D:INTEGER) return INTEGER is + begin + return MAX(MAX(A,B),MAX(C,D)); + end; + + function "+"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX+SY; -- SIGNED addition + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X,Y:SFIXED) return SFIXED is + variable SX,SY,SR:SIGNED(MAX(X'high,Y'high)+1-MIN(X'low,Y'low) downto 0); + variable R:SFIXED(MAX(X'high,Y'high)+1 downto MIN(X'low,Y'low)); + begin + for K in SX'range loop + if KX'high-R'low then + SX(K):=X(X'high); -- sign extend X MSBs + else + SX(K):=X(R'low+K); + end if; + end loop; + for K in SY'range loop + if KY'high-R'low then + SY(K):=Y(Y'high); -- sign extend Y MSBs + else + SY(K):=Y(R'low+K); + end if; + end loop; + SR:=SX-SY; -- SIGNED subtraction + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "-"(X:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SR:SIGNED(X'high-X'low+1 downto 0); + variable R:SFIXED(X'high+1 downto X'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + SR:=-RESIZE(SX,SR'length); -- SIGNED negation + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X,Y:SFIXED) return SFIXED is + variable SX:SIGNED(X'high-X'low downto 0); + variable SY:SIGNED(Y'high-Y'low downto 0); + variable SR:SIGNED(SX'high+SY'high+1 downto 0); + variable R:SFIXED(X'high+Y'high+1 downto X'low+Y'low); + begin + for K in SX'range loop + SX(K):=X(X'low+K); + end loop; + for K in SY'range loop + SY(K):=Y(Y'low+K); + end loop; + SR:=SX*SY; -- SIGNED multiplication + for K in SR'range loop + R(R'low+K):=SR(K); + end loop; + return R; + end; + + function "*"(X:SFIXED;Y:STD_LOGIC) return SFIXED is + begin + if Y='1' then + return X; + else + return TO_SFIXED(0.0,X); + end if; + end; + + function RESIZE(X:SFIXED;H,L:INTEGER) return SFIXED is + variable R:SFIXED(H downto L); + begin + for K in R'range loop + if KX'high then + R(K):=X(X'high); -- sign extend X MSBs + else + R(K):=X(K); + end if; + end loop; + return R; + end; + + function RESIZE(X:SFIXED;HL:SFIXED) return SFIXED is + begin + return RESIZE(X,HL'high,HL'low); + end; + + function SHIFT_RIGHT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high-N downto X'low-N); + begin + for K in R'range loop + R(K):=X(K+N); + end loop; + return R; + end; + + function SHIFT_LEFT(X:SFIXED;N:INTEGER) return SFIXED is + variable R:SFIXED(X'high+N downto X'low+N); + begin + for K in R'range loop + R(K):=X(K-N); + end loop; + return R; + end; + + function TO_SFIXED(R:REAL;H,L:INTEGER) return SFIXED is + variable RR:REAL; + variable V:SFIXED(H downto L); + begin + assert (R<2.0**H) and (R>=-2.0**H) report "TO_SFIXED vector truncation!" severity warning; + if R<0.0 then + V(V'high):='1'; + RR:=R+2.0**V'high; + else + V(V'high):='0'; + RR:=R; + end if; + for K in V'high-1 downto V'low loop + if RR>=2.0**K then + V(K):='1'; + RR:=RR-2.0**K; + else + V(K):='0'; + end if; + end loop; + return V; + end; + + function TO_SFIXED(R:REAL;HL:SFIXED) return SFIXED is + begin + return TO_SFIXED(R,HL'high,HL'low); + end; + + function TO_REAL(S:SFIXED) return REAL is + variable R:REAL; + begin + R:=0.0; + for K in S'range loop + if K=S'high then + if S(K)='1' then + R:=R-2.0**K; + end if; + else + if S(K)='1' then + R:=R+2.0**K; + end if; + end if; + end loop; + return R; + end; + +-- function ELEMENT(X:SFIXED_VECTOR;K,N:INTEGER) return SFIXED is -- X'low and X'length are always multiples of N +-- variable R:SFIXED(X'length/N-1+X'low/N downto X'low/N); +-- begin +-- R:=SFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); +-- return R; -- element K out of N of X +-- end; + + function RE(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(R'length-1+X'low downto X'low)); + return R; --lower half of X + end; + +-- procedure vRE(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low):=CFIXED(S); -- set lower half of X +-- end; + +-- procedure RE(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(S'length-1+X'low downto X'low)<=CFIXED(S); -- set lower half of X +-- end; + + function IM(X:CFIXED) return SFIXED is -- X'low is always even and X'high is always odd + variable R:SFIXED((X'high+1)/2-1 downto X'low/2); + begin + R:=SFIXED(X(X'high downto R'length+X'low)); + return R; --upper half of X + end; + +-- procedure vIM(X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low):=CFIXED(S); -- set upper half of X +-- end; + +-- procedure IM(signal X:out CFIXED;S:SFIXED) is -- X'low is always even and X'high is always odd +-- begin +-- X(X'high downto S'length+X'low)<=CFIXED(S); -- set upper half of X +-- end; + + function "+"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+RE(Y),IM(X)+IM(Y)); + end; + + function "-"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-RE(Y),IM(X)-IM(Y)); + end; + + function "*"(X,Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*RE(Y)-IM(X)*IM(Y),RE(X)*IM(Y)+IM(X)*RE(Y)); + end; + + function "*"(X:CFIXED;Y:SFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)*Y,IM(X)*Y); + end; + + function "*"(X:SFIXED;Y:CFIXED) return CFIXED is + begin + return TO_CFIXED(X*RE(Y),X*IM(Y)); + end; + + function RESIZE(X:CFIXED;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(RESIZE(RE(X),H,L),RESIZE(IM(X),H,L)); + end; + + function RESIZE(X:CFIXED;HL:CFIXED) return CFIXED is + begin + return RESIZE(X,HL'high/2,HL'low/2); + end; + + function PLUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-IM(X),RE(X)); + end; + + function "-"(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(-RE(X),-IM(X)); + end; + + function MINUS_i_TIMES(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),-RE(X)); + end; + + function X_PLUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)-IM(Y)+RE(RND),IM(X)+RE(Y)+IM(RND)); + end; + + function X_MINUS_i_TIMES_Y(X,Y:CFIXED;RND:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X)+IM(Y)+RE(RND),IM(X)-RE(Y)+IM(RND)); + end; + + function SWAP(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(IM(X),RE(X)); + end; + + function CONJ(X:CFIXED) return CFIXED is + begin + return TO_CFIXED(RE(X),-IM(X)); + end; + + function SHIFT_RIGHT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_RIGHT(RE(X),N),SHIFT_RIGHT(IM(X),N)); + end; + + function SHIFT_LEFT(X:CFIXED;N:INTEGER) return CFIXED is + begin + return TO_CFIXED(SHIFT_LEFT(RE(X),N),SHIFT_LEFT(IM(X),N)); + end; + + function TO_CFIXED(R,I:REAL;H,L:INTEGER) return CFIXED is + begin + return TO_CFIXED(TO_SFIXED(R,H,L),TO_SFIXED(I,H,L)); + end; + + function TO_CFIXED(R,I:REAL;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(R,I,HL'high/2,HL'low/2); + end; + + function TO_CFIXED(C:COMPLEX;HL:CFIXED) return CFIXED is + begin + return TO_CFIXED(C.RE,C.IM,HL); + end; + + function TO_CFIXED(R,I:SFIXED) return CFIXED is + constant H:INTEGER:=MAX(R'high,I'high); + constant L:INTEGER:=MIN(R'low,I'low); + variable C:CFIXED(2*H+1 downto 2*L); + begin + C:=CFIXED(RESIZE(I,H,L))&CFIXED(RESIZE(R,H,L)); + return C; -- I&R + end; + + function ELEMENT(X:CFIXED_VECTOR;K,N:INTEGER) return CFIXED is -- X'low and X'length are always multiples of N + variable R:CFIXED(X'length/N-1+X'low/N downto X'low/N); + begin + R:=CFIXED(X((K+1)*R'length-1+X'low downto K*R'length+X'low)); + return R; -- element K out of N of X + end; + + procedure vELEMENT(X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low):=CFIXED_VECTOR(C); -- element K out of N of X + end; + + procedure ELEMENT(signal X:out CFIXED_VECTOR;K,N:INTEGER;C:CFIXED) is -- X'low and X'length are always multiples of N + begin + X((K+1)*C'length-1+X'low downto K*C'length+X'low)<=CFIXED_VECTOR(C); -- element K out of N of X + end; + + function TO_COMPLEX(C:CFIXED) return COMPLEX is + variable R:COMPLEX; + begin + R.RE:=TO_REAL(RE(C)); + R.IM:=TO_REAL(IM(C)); + return R; + end; + + function TO_CFIXED_VECTOR(C:COMPLEX_VECTOR;HL:CFIXED) return CFIXED_VECTOR is + variable R:CFIXED_VECTOR(C'length*(HL'high+1)-1 downto C'length*HL'low); + begin + for K in C'range loop + R((K-C'low+1)*HL'length-1+R'low downto (K-C'low)*HL'length+R'low):=CFIXED_VECTOR(TO_CFIXED(C(K),HL)); + end loop; + return R; + end; + + function TO_COMPLEX_VECTOR(C:CFIXED_VECTOR;N:INTEGER) return COMPLEX_VECTOR is + variable R:COMPLEX_VECTOR(0 to N-1); + begin + for K in 0 to N-1 loop + R(K):=TO_COMPLEX(ELEMENT(C,K,N)); + end loop; + return R; + end; + + function "*"(R:REAL;C:COMPLEX_VECTOR) return COMPLEX_VECTOR is + variable X:COMPLEX_VECTOR(C'range); + begin + for K in C'range loop + X(K):=R*C(K); + end loop; + return X; + end; + + function LOG2(N:INTEGER) return INTEGER is + variable TEMP:INTEGER; + variable RESULT:INTEGER; + begin + TEMP:=N; + RESULT:=0; + while TEMP>1 loop + RESULT:=RESULT+1; + TEMP:=(TEMP+1)/2; + end loop; + return RESULT; + end; +end COMPLEX_FIXED_PKG; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic BOOLEAN Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); +end BDELAY; + +architecture TEST of BDELAY is + attribute rloc:STRING; + + component BDELAY + generic(SIZE:INTEGER:=1); + port(CLK:in STD_LOGIC; + I:in BOOLEAN; + O:out BOOLEAN); + end component; + +begin + l0:if SIZE=0 generate + begin + O<=I; + end generate l0; + -- end; + + l1:if SIZE=1 generate + signal iO:BOOLEAN:=FALSE; + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; + end generate l1; + -- end; + + l17: if SIZE>=2 and SIZE<18 generate + signal A:UNSIGNED(3 downto 0); + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + D<='1' when I else '0'; + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>D, + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l17; + -- end; + + l33: if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + signal D,Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + D<='1' when I else '0'; + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>D, + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O<=RQ='1'; + end generate l33; + -- end; + + l257: if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.BDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + -- end; + end generate l257; + + ln: if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + type TUV is array(0 to SIZE-3) of UNSIGNED(0 downto 0); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(0 downto 0):=(others=>(others=>'0')); + signal MEM:TUV:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(0 downto 0):=(others=>'0'); + signal D,Q:UNSIGNED(0 downto 0); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + D<="1" when I else "0"; + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=D; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO="1"; + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: UDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: UDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic UNSIGNED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity UDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in UNSIGNED; + O:out UNSIGNED); +end UDELAY; + +architecture TEST of UDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin + assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=I; +-- end; + end generate; +-- elsif l1: SIZE=1 generate + l1:if SIZE=1 generate + signal iO:UNSIGNED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=I; + end if; + end process; + O<=iO; +-- end; + end generate; +-- elsif l17: SIZE>=2 and SIZE<18 generate + l17:if SIZE>=2 and SIZE<18 generate + lk:for K in 0 to O'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l33: SIZE>=18 and SIZE<34 generate + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:UFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- O<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + O(O'low+K)<=RQ; + end generate; +-- end; + end generate; +-- elsif l257: SIZE>=34 and SIZE=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.UDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); +-- end; + end generate; +-- elsif ln: SIZE>=BRAM_THRESHOLD generate + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:UNSIGNED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:UNSIGNED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of UNSIGNED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:UNSIGNED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=iO; + end if; + end process; +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic SFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity SDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in SFIXED; + O:out SFIXED); +end SDELAY; + +architecture TEST of SDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; +begin +-- assert I'length=O'length report "Ports I and O must have the same length" severity error; + + l0:if SIZE=0 generate + begin + O<=RESIZE(I,O'high,O'low); + end generate l0; + --end; + + l1:if SIZE=1 generate + signal iO:SFIXED(O'range):=(others=>'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iO<=RESIZE(I,iO); + end if; + end process; + O<=iO; + end generate l1; + --end; + + l17:if SIZE>=2 and SIZE<18 generate +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); + begin + lk:for K in 0 to I'length-1 generate + signal A:UNSIGNED(3 downto 0); + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + A<=TO_UNSIGNED(SIZE-2,A'length); + sr:SRL16E port map(CLK=>CLK, + CE=>'1', + A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + D=>I(I'low+K), + Q=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l17; + --end; + + l33:if SIZE>=18 and SIZE<34 generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); + signal A:UNSIGNED(LOG2(SIZE-1)-1 downto 0):=(others=>'0'); +-- signal iO:SFIXED(I'range):=(others=>'0'); + signal iO:SFIXED(I'range); +-- attribute ram_style:STRING; +-- attribute ram_style of MEM:signal is "distributed"; + begin + process(CLK) + begin + if rising_edge(CLK) then + if A=SIZE-2 then + A<=(others=>'0'); + else + A<=A+1; + end if; +-- MEM(TO_INTEGER(A))<=I; +-- iO<=MEM(TO_INTEGER(A)); + end if; + end process; +-- O<=RESIZE(iO,O); + lk:for K in 0 to I'length-1 generate + signal Q:STD_LOGIC; + signal RQ:STD_LOGIC:='0'; + --attribute rloc of sr:label is "X0Y"&INTEGER'image(K/8); + begin + rs:RAM32X1S port map(A0=>A(0), + A1=>A(1), + A2=>A(2), + A3=>A(3), + A4=>A(4), + D=>I(I'low+K), + WCLK=>CLK, + WE=>'1', + O=>Q); + process(CLK) + begin + if rising_edge(CLK) then + RQ<=Q; + end if; + end process; + iO(iO'low+K)<=RQ; + end generate; + O<=RESIZE(iO,O'high,O'low); + end generate l33; + --end; + + l257:if SIZE>=34 and SIZE33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + O=>iO); + hd:entity work.SDELAY generic map(SIZE=>SIZE-33, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>iO, + O=>O); + --end; + end generate l257; + + ln:if SIZE>=BRAM_THRESHOLD generate +-- signal MEM:SFIXED_VECTOR(0 to SIZE-2)(I'range):=(others=>(others=>'0')); +--2008 signal MEM:SFIXED_VECTOR(0 to SIZE-3)(I'range):=(others=>(others=>'0')); + type TMEM is array(0 to SIZE-3) of SFIXED(I'range); + signal MEM:TMEM:=(others=>(others=>'0')); + signal RA,WA:UNSIGNED(LOG2(SIZE-2)-1 downto 0):=(others=>'0'); + signal iO1E,iO:SFIXED(I'range):=(others=>'0'); + attribute ram_style:STRING; + attribute ram_style of MEM:signal is "block"; + begin + process(CLK) + begin + if rising_edge(CLK) then +-- if RA=SIZE-2 then + if RA=SIZE-3 then + RA<=(others=>'0'); + else + RA<=RA+1; + end if; + WA<=RA; + MEM(TO_INTEGER(WA))<=I; +-- iO<=MEM(TO_INTEGER(RA)); + iO1E<=MEM(TO_INTEGER(RA)); + iO<=iO1E; + O<=RESIZE(iO,O'high,O'low); + end if; + end process; + -- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CDELAY.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CDELAY +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic CFIXED Delay Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CDELAY is + generic(SIZE:INTEGER:=1; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CDELAY; + +architecture TEST of CDELAY is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute rloc:STRING; + signal IRE,IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); +begin + IRE<=RE(I); + IIM<=IM(I); + dr:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.RE); + I=>IRE, + O=>ORE); + di:entity work.SDELAY generic map(SIZE=>SIZE, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.IM); + I=>IIM, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CB.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CB +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Matrix Transposer (Corner Bender) Module Stage +-- It does an RxR matrix transposition where R=I'length +-- and each matrix element is a group of PACKING_FACTOR consecutive samples +-- LATENCY=(I'length-1)*PACKING_FACTOR+1 when I'length>1 or 0 when I'length=1 +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CB is + generic(SSR:INTEGER:=4; --93 + F:INTEGER:=0; + PACKING_FACTOR:INTEGER:=1; + INPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + OUTPUT_PACKING_FACTOR_ADJUST:INTEGER:=0; + SHORTEN_VO_BY:INTEGER:=0; + BRAM_THRESHOLD:INTEGER:=258); + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CB; + +architecture TEST of CB is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(LOG2(SSR)-1 downto 0); --93 local constrained UNSIGNED_VECTOR type + type iCFIXED_VECTOR is array(NATURAL range <>) of CFIXED((I'high+1)/SSR-1 downto I'low/SSR); --93 local constrained CFIXED_VECTOR type + + signal CNTP:UNSIGNED(LOG2(PACKING_FACTOR) downto 0):=(others=>'0'); + signal CNT:UNSIGNED(LOG2(SSR)-1 downto 0):=(others=>'0'); +--2008 signal A:UNSIGNED_VECTOR(0 to I'length):=(others=>(others=>'0')); +--2008 signal EN:BOOLEAN_VECTOR(0 to I'length):=(others=>FALSE); +--2008 signal DI:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal DO:CFIXED_VECTOR(0 to I'length-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(0 to I'length-1=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).IM'range=>'0'))); + signal A:UNSIGNED_VECTOR(0 to SSR):=(others=>(others=>'0')); + signal EN:BOOLEAN_VECTOR(0 to SSR):=(others=>FALSE); + signal II,DI,OO:iCFIXED_VECTOR(0 to SSR-1); + signal DO:iCFIXED_VECTOR(0 to SSR-1):=(others=>(others=>'0')); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity error; + + f0:if F=0 generate + begin +--2008 i0:if I'length=1 generate + i0:if SSR=1 generate + O<=I; + VO<=VI; + SO<=SI; + end generate; +--2008 else generate +--2008 i1:if I'length>1 generate + i1:if SSR>1 generate + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if CNTP=PACKING_FACTOR-1 then + CNTP<=(others=>'0'); + CNT<=CNT+1; + else + CNTP<=CNTP+1; + end if; + else + CNTP<=(others=>'0'); + CNT<=(others=>'0'); + end if; + end if; + end process; + + A(0)<=CNT; + EN(0)<=CNTP=PACKING_FACTOR-1; +--2008 lk:for K in 0 to I'length-1 generate + lk:for K in 0 to SSR-1 generate + begin + II(K)<=CFIXED(I(I'length/SSR*(K+1)-1+I'low downto I'length/SSR*K+I'low)); --93 + i1:entity work.CDELAY generic map(SIZE=>K*(PACKING_FACTOR+INPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II(K), --93 I(I'low+K), + O=>DI(K)); + process(CLK) + begin + if rising_edge(CLK) then + DO(K)<=DI(TO_INTEGER(A(K))); + if EN(K) then + A(K+1)<=A(K); + end if; + end if; + end process; + bd:entity work.BDELAY generic map(SIZE=>PACKING_FACTOR) + port map(CLK=>CLK, + I=>EN(K), + O=>EN(K+1)); + o1:entity work.CDELAY generic map(SIZE=>(SSR-1-K)*(PACKING_FACTOR+OUTPUT_PACKING_FACTOR_ADJUST), + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DO(K), + O=>OO(K)); --93 O(O'low+K)); + O(O'length/SSR*(K+1)-1+O'low downto O'length/SSR*K+O'low)<=CFIXED_VECTOR(OO(K)); --93 + end generate; + + bd:entity work.BDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY) + port map(CLK=>CLK, + I=>VI, + O=>VO); + + ud:entity work.UDELAY generic map(SIZE=>(SSR-1)*PACKING_FACTOR+1-SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +-- end; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=SSR/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.CB generic map(SSR=>G, + F=>0, + PACKING_FACTOR=>PACKING_FACTOR, + INPUT_PACKING_FACTOR_ADJUST=>INPUT_PACKING_FACTOR_ADJUST, + OUTPUT_PACKING_FACTOR_ADJUST=>OUTPUT_PACKING_FACTOR_ADJUST, + SHORTEN_VO_BY=>SHORTEN_VO_BY, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: BFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: BFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Real Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity BFS is + generic(PIPELINE:BOOLEAN:=TRUE; + SUB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SCALE:in STD_LOGIC; +-- P:out SIGNED); -- O=A±B + P:out SFIXED; -- O=A±B + OVR:out STD_LOGIC); +end BFS; + +architecture FAST of BFS is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH+1 downto SM-1); +-- signal S:SIGNED(SH+1 downto SL); + signal SA,SB:SFIXED(SH+1 downto SM-1); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM+1 downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1)/8*8+8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1)/8*8+7 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH+1 generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(SUB))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (((I0 and not I4) or (I2 and I4)) xor ((I1 and not I4) or (I3 and I4)))) or (not I5 and ((I1 and not I4) or (I3 and I4)))) + port map(I0=>SB(K-1),I1=>SA(K-1),I2=>SB(K),I3=>SA(K),I4=>SCALE,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM+1)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM+1); + end generate; + S(SH+1)<=O(O'high); + + ia:if A'low'0'); + signal iOVR:STD_LOGIC:='0'; + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + iOVR<=S(S'high) xor S(S'high-1); + end if; + end process; + P<=iP; + OVR<=iOVR; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CBFS.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CBFS +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Complex Arbitrary Fixed Point Size, Add/Subtract FFT Module with scaling and overflow detection +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CBFS is -- O0=I0+I1, O1=I0-I1 + generic(ROUNDING:BOOLEAN:=TRUE; + PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC; + I0,I1:in CFIXED; + SCALE:in STD_LOGIC; + O0,O1:out CFIXED; + OVR:out STD_LOGIC); +end CBFS; + +architecture TEST of CBFS is + signal I0RE,I0IM,I1RE,I1IM:SFIXED(I0'high/2 downto I0'low/2); + signal O0RE,O0IM,O1RE,O1IM:SFIXED(O0'high/2 downto O0'low/2); + signal OVR4:STD_LOGIC_VECTOR(3 downto 0); +begin + I0RE<=RE(I0); + I0IM<=IM(I0); + I1RE<=RE(I1); + I1IM<=IM(I1); + + u0:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0RE=I0RE+I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O0RE, + OVR=>OVR4(0)); + + u1:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>FALSE) -- O0IM=I0IM+I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O0IM, + OVR=>OVR4(1)); + + u2:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1RE=I0RE-I1RE + port map(CLK=>CLK, + A=>I0RE, + B=>I1RE, + SCALE=>SCALE, + P=>O1RE, + OVR=>OVR4(2)); + + u3:entity work.BFS generic map(DSP48E=>DSP48E, + SUB=>TRUE) -- O1IM=I0IM-I1IM + port map(CLK=>CLK, + A=>I0IM, + B=>I1IM, + SCALE=>SCALE, + P=>O1IM, + OVR=>OVR4(3)); + + O0<=TO_CFIXED(O0RE,O0IM); + O1<=TO_CFIXED(O1RE,O1IM); + OVR<=OVR4(0) or OVR4(1) or OVR4(2) or OVR4(3); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CSA3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CSA3 +-- Purpose: Generic 3-input Add/Sub Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Carry Save 3-input Adder/Subtracter +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity CSA3 is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + NEGATIVE_A:BOOLEAN:=FALSE; + NEGATIVE_B:BOOLEAN:=FALSE; + EXTRA_MSBs:INTEGER:=2); + port(CLK:in STD_LOGIC:='0'; +-- A,B,C:in SIGNED; -- if SIGNED, A, B, C and P must be LSB aligned + A,B,C:in SFIXED; -- if SFIXED, A, B, C and P can be any size + CY1,CY2:in BOOLEAN:=FALSE; -- the number of CYs TRUE must equal the number of negative A and B terms +-- P:out SIGNED); -- O=C±A±B + P:out SFIXED); -- O=C±A±B +end CSA3; + +architecture FAST of CSA3 is + constant SH:INTEGER:=MAX(A'high,B'high,C'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MED(A'low,B'low,C'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low,C'low); +-- signal SA,SB,SC,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB,SC:SFIXED(SH downto SM); + signal S:SFIXED(SH downto SL); + + signal O5:SIGNED(SH-SM+1 downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + SC<=RESIZE(C,SC); + O5(0)<='1' when CY1 else '0'; + CY(0)<='1' when CY2 else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_B))); + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00" xor (63 downto 0=>BIT'val(BOOLEAN'pos(NEGATIVE_A))); + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + begin + l6:LUT6_2 generic map(INIT=>(I5 and (I1 xor I2 xor I3 xor I4)) or (not I5 and ((I2 and I3) or (I3 and I1) or (I1 and I2)))) + port map(I0=>'0',I1=>SC(K),I2=>SB(K),I3=>SA(K),I4=>O5(K-SM),I5=>'1',O5=>O5(K+1-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + + ll:for L in SM to SH generate + S(L)<=O(L-SM); + end generate; + + ia:if (A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +--***************************************************************************** +-- © Copyright 2008 - 2018 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +--***************************************************************************** +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : v1.2 +-- \ \ Application : DSP48E2 generic wrapper +-- / / Filename : DSP48E2GW.vhd +-- /___/ /\ Date Last Modified : Oct 11 2017 +-- \ \ / \ Date Created : Nov 14 2014 +-- \___\/\___\ +-- +--Device : UltraScale and UltraScale+ +--Design Name : DSP48E2GW +--Purpose : DSP48E2 Generic Wrapper makes DSP48E2 primitive instantiation easier +--Reference : +--Revision History : v1.0 - original version +--Revision History : v1.1 - smart SFIXED resizing +--Revision History : v1.2 - fix for output resizing +--***************************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +--use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity DSP48E2GW is + generic(X,Y:INTEGER:=-1; + DSP48E:INTEGER:=2; -- use 1 for DSP48E1 and 2 for DSP48E2 + -- Feature Control Attributes: Data Path Selection + AMULTSEL:STRING:="A"; -- Selects A input to multiplier (A, AD) + A_INPUT:STRING:="DIRECT"; -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL:STRING:="B"; -- Selects B input to multiplier (AD, B) + B_INPUT:STRING:="DIRECT"; -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL:STRING:="A"; -- Selects input to preadder (A, B) + RND:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- Rounding Constant + USE_MULT:STRING:="MULTIPLY"; -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD:STRING:="ONE48"; -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR:STRING:="FALSE"; -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD:STRING:="XOR24_48_96"; -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET:STRING:="NO_RESET"; -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY:STRING:="RESET"; -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK:STD_LOGIC_VECTOR(47 downto 0):=X"3fffffffffff"; -- 48-bit mask value for pattern detect (1=ignore) + PATTERN:STD_LOGIC_VECTOR(47 downto 0):=X"000000000000"; -- 48-bit pattern match for pattern detect + SEL_MASK:STRING:="MASK"; -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN:STRING:="PATTERN"; -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT:STRING:="NO_PATDET"; -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED:STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED:BIT:='0'; -- Optional inversion for CARRYIN + IS_CLK_INVERTED:BIT:='0'; -- Optional inversion for CLK + IS_INMODE_INVERTED:STD_LOGIC_VECTOR(4 downto 0):="00000"; -- Optional inversion for INMODE + IS_OPMODE_INVERTED:STD_LOGIC_VECTOR(8 downto 0):="000000000"; -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED:BIT:='0'; -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED:BIT:='0'; -- Optional inversion for RSTA + IS_RSTB_INVERTED:BIT:='0'; -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED:BIT:='0'; -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED:BIT:='0'; -- Optional inversion for RSTC + IS_RSTD_INVERTED:BIT:='0'; -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED:BIT:='0'; -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED:BIT:='0'; -- Optional inversion for RSTM + IS_RSTP_INVERTED:BIT:='0'; -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG:INTEGER:=1; -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG:INTEGER:=1; -- Pipeline stages for pre-adder (0-1) + ALUMODEREG:INTEGER:=1; -- Pipeline stages for ALUMODE (0-1) + AREG:INTEGER:=1; -- Pipeline stages for A (0-2) + BCASCREG:INTEGER:=1; -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG:INTEGER:=1; -- Pipeline stages for B (0-2) + CARRYINREG:INTEGER:=1; -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG:INTEGER:=1; -- Pipeline stages for CARRYINSEL (0-1) + CREG:INTEGER:=1; -- Pipeline stages for C (0-1) + DREG:INTEGER:=1; -- Pipeline stages for D (0-1) + INMODEREG:INTEGER:=1; -- Pipeline stages for INMODE (0-1) + MREG:INTEGER:=1; -- Multiplier pipeline stages (0-1) + OPMODEREG:INTEGER:=1; -- Pipeline stages for OPMODE (0-1) + PREG:INTEGER:=1); -- Number of pipeline stages for P (0-1) + port(-- Cascade inputs: Cascade Ports + ACIN:in STD_LOGIC_VECTOR(29 downto 0):=(others=>'0'); -- 30-bit input: A cascade data + BCIN:in STD_LOGIC_VECTOR(17 downto 0):=(others=>'0'); -- 18-bit input: B cascade + CARRYCASCIN:in STD_LOGIC:='0'; -- 1-bit input: Cascade carry + MULTSIGNIN:in STD_LOGIC:='0'; -- 1-bit input: Multiplier sign cascade + PCIN:in STD_LOGIC_VECTOR(47 downto 0):=(others=>'0'); -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE:in STD_LOGIC_VECTOR(3 downto 0):=X"0"; -- 4-bit input: ALU control + CARRYINSEL:in STD_LOGIC_VECTOR(2 downto 0):="000"; -- 3-bit input: Carry select + CLK:in STD_LOGIC:='0'; -- 1-bit input: Clock + INMODE:in STD_LOGIC_VECTOR(4 downto 0):="00000"; -- 5-bit input: INMODE control + OPMODE:in STD_LOGIC_VECTOR(8 downto 0):="000110101"; -- 9-bit input: Operation mode - default is P<=C+A*B + -- Data inputs: Data Ports + A:in SFIXED;--(Ahi downto Alo):=(others=>'0'); -- 30-bit input: A data + B:in SFIXED;--(Bhi downto Blo):=(others=>'0'); -- 18-bit input: B data + C:in SFIXED;--(Chi downto Clo):=(others=>'0'); -- 48-bit input: C data + CARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Carry-in + D:in SFIXED;--(Dhi downto Dlo):=(others=>'0'); -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage AREG + CEA2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage AREG + CEAD:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ADREG + CEALUMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for ALUMODE + CEB1:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 1st stage BREG + CEB2:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for 2nd stage BREG + CEC:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CREG + CECARRYIN:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for CARRYINREG + CECTRL:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for DREG + CEINMODE:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for INMODEREG + CEM:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for MREG + CEP:in STD_LOGIC:='1'; -- 1-bit input: Clock enable for PREG + RSTA:in STD_LOGIC:='0'; -- 1-bit input: Reset for AREG + RSTALLCARRYIN:in STD_LOGIC:='0'; -- 1-bit input: Reset for CARRYINREG + RSTALUMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for ALUMODEREG + RSTB:in STD_LOGIC:='0'; -- 1-bit input: Reset for BREG + RSTC:in STD_LOGIC:='0'; -- 1-bit input: Reset for CREG + RSTCTRL:in STD_LOGIC:='0'; -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD:in STD_LOGIC:='0'; -- 1-bit input: Reset for DREG and ADREG + RSTINMODE:in STD_LOGIC:='0'; -- 1-bit input: Reset for INMODEREG + RSTM:in STD_LOGIC:='0'; -- 1-bit input: Reset for MREG + RSTP:in STD_LOGIC:='0'; -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT:out STD_LOGIC_VECTOR(29 downto 0); -- 30-bit output: A port cascade + BCOUT:out STD_LOGIC_VECTOR(17 downto 0); -- 18-bit output: B cascade + CARRYCASCOUT:out STD_LOGIC; -- 1-bit output: Cascade carry + MULTSIGNOUT:out STD_LOGIC; -- 1-bit output: Multiplier sign cascade + PCOUT:out STD_LOGIC_VECTOR(47 downto 0); -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW:out STD_LOGIC; -- 1-bit output: Overflow in add/acc + PATTERNBDETECT:out STD_LOGIC; -- 1-bit output: Pattern bar detect + PATTERNDETECT:out STD_LOGIC; -- 1-bit output: Pattern detect + UNDERFLOW:out STD_LOGIC; -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT:out STD_LOGIC_VECTOR(3 downto 0); -- 4-bit output: Carry + P:out SFIXED;--(Phi downto Plo); -- 48-bit output: Primary data + XOROUT:out STD_LOGIC_VECTOR(7 downto 0)); -- 8-bit output: XOR data +end entity; + +architecture WRAPPER of DSP48E2GW is + signal slvA:STD_LOGIC_VECTOR(29 downto 0); + signal slvB:STD_LOGIC_VECTOR(17 downto 0); + signal slvD:STD_LOGIC_VECTOR(26 downto 0); + signal slvC,slvP:STD_LOGIC_VECTOR(47 downto 0); +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if K=0) and (Y>=0) generate + begin + i1:if DSP48E=1 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + attribute loc:STRING; + attribute loc of ds:label is "DSP48E2_X"&INTEGER'image(X)&"Y"&INTEGER'image(Y); + begin + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; +-- else generate + i2:if (X<0) or (Y<0) generate + begin + i1:if DSP48E=1 generate + ds:DSP48E1 generic map(-- Feature Control Attributes: Data Path Selection + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH +-- MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) +-- PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE(6 downto 0), -- 7-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD(24 downto 0), -- 25-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP); -- 48-bit output: Primary data + end generate; + i2:if DSP48E=2 generate + ds:DSP48E2 generic map(-- Feature Control Attributes: Data Path Selection + AMULTSEL => AMULTSEL, -- Selects A input to multiplier (A, AD) + A_INPUT => A_INPUT, -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => BMULTSEL, -- Selects B input to multiplier (AD, B) + B_INPUT => B_INPUT, -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => PREADDINSEL, -- Selects input to preadder (A, B) + RND => RND, -- Rounding Constant + USE_MULT => USE_MULT, -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => USE_SIMD, -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => USE_WIDEXOR, -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => XORSIMD, -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => AUTORESET_PATDET, -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => AUTORESET_PRIORITY, -- Priority of AUTORESET vs.CEP (CEP, RESET). + MASK => MASK, -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => PATTERN, -- 48-bit pattern match for pattern detect + SEL_MASK => SEL_MASK, -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => SEL_PATTERN, -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => USE_PATTERN_DETECT, -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => IS_ALUMODE_INVERTED, -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => IS_CARRYIN_INVERTED, -- Optional inversion for CARRYIN + IS_CLK_INVERTED => IS_CLK_INVERTED, -- Optional inversion for CLK + IS_INMODE_INVERTED => IS_INMODE_INVERTED, -- Optional inversion for INMODE + IS_OPMODE_INVERTED => IS_OPMODE_INVERTED, -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => IS_RSTALLCARRYIN_INVERTED, -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => IS_RSTALUMODE_INVERTED, -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => IS_RSTA_INVERTED, -- Optional inversion for RSTA + IS_RSTB_INVERTED => IS_RSTB_INVERTED, -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => IS_RSTCTRL_INVERTED, -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => IS_RSTC_INVERTED, -- Optional inversion for RSTC + IS_RSTD_INVERTED => IS_RSTD_INVERTED, -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => IS_RSTINMODE_INVERTED, -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => IS_RSTM_INVERTED, -- Optional inversion for RSTM + IS_RSTP_INVERTED => IS_RSTP_INVERTED, -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => ACASCREG, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => ADREG, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => ALUMODEREG, -- Pipeline stages for ALUMODE (0-1) + AREG => AREG, -- Pipeline stages for A (0-2) + BCASCREG => BCASCREG, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => BREG, -- Pipeline stages for B (0-2) + CARRYINREG => CARRYINREG, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => CARRYINSELREG, -- Pipeline stages for CARRYINSEL (0-1) + CREG => CREG, -- Pipeline stages for C (0-1) + DREG => DREG, -- Pipeline stages for D (0-1) + INMODEREG => INMODEREG, -- Pipeline stages for INMODE (0-1) + MREG => MREG, -- Multiplier pipeline stages (0-1) + OPMODEREG => OPMODEREG, -- Pipeline stages for OPMODE (0-1) + PREG => PREG) -- Number of pipeline stages for P (0-1) + port map(-- Cascade inputs: Cascade Ports + ACIN => ACIN, -- 30-bit input: A cascade data + BCIN => BCIN, -- 18-bit input: B cascade + CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry + MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade + PCIN => PCIN, -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => ALUMODE, -- 4-bit input: ALU control + CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select + CLK => CLK, -- 1-bit input: Clock + INMODE => INMODE, -- 5-bit input: INMODE control + OPMODE => OPMODE, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => slvA, -- 30-bit input: A data + B => slvB, -- 18-bit input: B data + C => slvC, -- 48-bit input: C data + CARRYIN => CARRYIN, -- 1-bit input: Carry-in + D => slvD, -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => CEAD, -- 1-bit input: Clock enable for ADREG + CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE + CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => CEC, -- 1-bit input: Clock enable for CREG + CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => CED, -- 1-bit input: Clock enable for DREG + CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG + CEM => CEM, -- 1-bit input: Clock enable for MREG + CEP => CEP, -- 1-bit input: Clock enable for PREG + RSTA => RSTA, -- 1-bit input: Reset for AREG + RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG + RSTB => RSTB, -- 1-bit input: Reset for BREG + RSTC => RSTC, -- 1-bit input: Reset for CREG + RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG + RSTM => RSTM, -- 1-bit input: Reset for MREG + RSTP => RSTP, -- 1-bit input: Reset for PREG + -- Cascade outputs: Cascade Ports + ACOUT => ACOUT, -- 30-bit output: A port cascade + BCOUT => BCOUT, -- 18-bit output: B cascade + CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry + MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade + PCOUT => PCOUT, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect + PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect + UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc + -- Data outputs: Data Ports + CARRYOUT => CARRYOUT, -- 4-bit output: Carry + P => slvP, -- 48-bit output: Primary data + XOROUT => XOROUT); -- 8-bit output: XOR data + end generate; +-- end; + end generate; + P<=SLV_TO_SFIXED_RESIZE(slvP,P'high,P'low,A'low+B'low-P'low); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CKCM.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CKCM +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Constant Coeficient Complex Multiplier +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CKCM is -- LATENCY=3 + generic(M:INTEGER:=1; -- must be 0, 1, 2 or 3 to multiply I by (1.0,0.0), (Sqrt(0.5),-Sqrt(0.5)), (0.0,-1.0), (-Sqrt(0.5),-Sqrt(0.5)) + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + ROUNDING:BOOLEAN:=FALSE; -- set to TRUE to round the result + CONJUGATE:BOOLEAN:=FALSE); -- set to TRUE for IFFT + port(CLK:in STD_LOGIC; + I:in CFIXED; + O:out CFIXED); +end CKCM; + +architecture TEST of CKCM is + attribute use_dsp48:STRING; + attribute use_dsp48 of TEST:architecture is "no"; +--2008 signal RND:SFIXED(O.RE'high downto O.RE'low-1); + signal RND:SFIXED((O'high+1)/2-1 downto O'low/2-1); + constant nCONJUGATE:BOOLEAN:=not CONJUGATE; +begin + i0:if M=0 generate + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>I, + O=>O); + end generate; +--elsif i1: M=2 generate + i1:if M=2 generate + ic:if CONJUGATE generate +--2008 signal NIIM1D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal NIIM1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IRE:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIIM1D<=RESIZE(-I.IM,I.IM); + NIIM1D<=RESIZE(-IM(I),NIIM1D); + end if; + end process; + r2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIIM1D, +--2008 O=>O.RE); + O=>ORE); + IRE<=RE(I); + i3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.RE, +--2008 O=>O.IM); + I=>IRE, + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + ---else generate + nc:if not CONJUGATE generate +--2008 signal NIRE1D:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal NIRE1D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM:SFIXED((I'high+1)/2-1 downto I'low/2); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + begin + IIM<=IM(I); + r3:entity work.SDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>I.IM, +--2008 O=>O.RE); + I=>IIM, + O=>ORE); + process(CLK) + begin + if rising_edge(CLK) then +--2008 NIRE1D<=RESIZE(-I.RE,I.RE); + NIRE1D<=RESIZE(-RE(I),RE(I)); + end if; + end process; + i2:entity work.SDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>NIRE1D, +--2008 O=>O.IM); + O=>OIM); + O<=TO_CFIXED(ORE,OIM); +-- end; + end generate; + end generate; +-- else generate -- M=1 or 3 + i2:if (M=1) or (M=3) generate -- M=1 or 3 + constant K:SFIXED(0 downto -18):="0101101010000010100"; -- SQRT(0.5) + +--2008 signal X1,Y1:SFIXED(I.RE'high downto I.RE'low-14); +--2008 signal X2,Y2:SFIXED(I.RE'range); +--2008 signal KIRE,KIIM:SFIXED(I.RE'range); + + + + signal X1,Y1:SFIXED((I'high+1)/2-1 downto I'low/2-14); + signal X2,Y2:SFIXED((I'high+1)/2-1 downto I'low/2):=(others=>'0'); + signal KIRE,KIIM:SFIXED((I'high+1)/2-1 downto I'low/2); +--2008 signal I_1:CFIXED(RE(I.RE'high-1 downto I.RE'low-1),IM(I.IM'high-1 downto I.IM'low-1)); +--2008 signal I_6:CFIXED(RE(I.RE'high-6 downto I.RE'low-6),IM(I.IM'high-6 downto I.IM'low-6)); +--2008 signal I_14:CFIXED(RE(I.RE'high-14 downto I.RE'low-14),IM(I.IM'high-14 downto I.IM'low-14)); + signal I_1:CFIXED(I'high-2*1 downto I'low-2*1); + signal I_6:CFIXED(I'high-2*6 downto I'low-2*6); + signal I_14:CFIXED(I'high-2*14 downto I'low-2*14); + signal I_1RE,I_1IM:SFIXED((I_1'high+1)/2-1 downto I_1'low/2); + signal I_6RE,I_6IM:SFIXED((I_6'high+1)/2-1 downto I_6'low/2); + signal I_14RE,I_14IM:SFIXED((I_14'high+1)/2-1 downto I_14'low/2); + signal X1_2:SFIXED(X1'high-2 downto X1'low-2); + signal X2_4:SFIXED(X2'high-4 downto X2'low-4); + signal Y1_2:SFIXED(Y1'high-2 downto Y1'low-2); + signal Y2_4:SFIXED(Y2'high-4 downto Y2'low-4); + signal ORE,OIM:SFIXED((O'high+1)/2-1 downto O'low/2); + constant MEQ3:BOOLEAN:=M=3; + begin +--2008 RND<=TO_SFIXED(2.0**(O.RE'low-1),RND) when ROUNDING else (others=>'0'); + RND<=TO_SFIXED(2.0**(O'low/2-1),RND) when ROUNDING else (others=>'0'); + process(CLK) + begin + if rising_edge(CLK) then +--2008 X2<=I.RE; +--2008 Y2<=I.IM; + X2<=RE(I); + Y2<=IM(I); + end if; + end process; + + I_1<=SHIFT_RIGHT(I,1); + I_6<=SHIFT_RIGHT(I,6); + I_14<=SHIFT_RIGHT(I,14); + X1_2<=SHIFT_RIGHT(X1,2); + X2_4<=SHIFT_RIGHT(X2,4); + Y1_2<=SHIFT_RIGHT(Y1,2); + Y2_4<=SHIFT_RIGHT(Y2,4); + I_1RE<=RE(I_1); + I_6RE<=RE(I_6); + I_14RE<=RE(I_14); + + a1:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.RE, +--2008 B=>I_6.RE, +--2008 C=>I_14.RE, + A=>I_1RE, + B=>I_6RE, + C=>I_14RE, + P=>X1); -- P=C+A+B + + a2:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>X1, + B=>X1_2, + C=>X2_4, + P=>KIRE); -- P=C+A+B + + I_1IM<=IM(I_1); + I_6IM<=IM(I_6); + I_14IM<=IM(I_14); + a3:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, +--2008 A=>I_1.IM, +--2008 B=>I_6.IM, +--2008 C=>I_14.IM, + A=>I_1IM, + B=>I_6IM, + C=>I_14IM, + P=>Y1); -- P=C+A+B + + a4:entity work.CSA3 generic map(DSP48E=>DSP48E, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>Y1, + B=>Y1_2, + C=>Y2_4, + P=>KIIM); -- P=C+A+B + + a5:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>MEQ3, --2008 M=3, + NEGATIVE_B=>CONJUGATE, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>MEQ3, --2008 M=3, + CY2=>CONJUGATE, +--2008 P=>O.RE); -- P=C+A+B + P=>ORE); -- P=C+A+B + + a6:entity work.CSA3 generic map(DSP48E=>DSP48E, + NEGATIVE_A=>nCONJUGATE, + NEGATIVE_B=>MEQ3, --2008 M=3, + EXTRA_MSBs=>0) + port map(CLK=>CLK, + A=>KIRE, + B=>KIIM, + C=>RND, + CY1=>nCONJUGATE, + CY2=>MEQ3, --2008 M=3, +--2008 P=>O.IM); -- P=C+A+B + P=>OIM); -- P=C+A+B + O<=TO_CFIXED(ORE,OIM); + --end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: ADDSUB.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Add/Subtract Module +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity ADDSUB is + generic(PIPELINE:BOOLEAN:=TRUE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + EXTRA_MSBs:INTEGER:=1); + port(CLK:in STD_LOGIC:='0'; +-- A,B:in SIGNED; -- if SIGNED, A, B and P must be LSB aligned + A,B:in SFIXED; -- if SFIXED, A, B and P can be any size + SUB:in BOOLEAN:=FALSE; +-- P:out SIGNED); -- O=A±B + P:out SFIXED); -- O=A±B +end ADDSUB; + +architecture FAST of ADDSUB is + constant SH:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'high,B'high)+EXTRA_MSBs; + constant SM:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(A'low,B'low); + constant SL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(A'low,B'low); +-- signal SA,SB,M:SIGNED(SH downto SM); +-- signal S:SIGNED(SH downto SL); + signal SA,SB:SFIXED(SH downto SM); + signal S:SFIXED(SH+1 downto SL); + + signal O5:SIGNED(SH-SM downto 0); + signal O6:SIGNED(SH-SM downto 0); + signal CY:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8 downto 0); + signal SI,DI,O:STD_LOGIC_VECTOR((SH-SM+1+7)/8*8-1 downto 0); +begin + SA<=RESIZE(A,SA); + SB<=RESIZE(B,SB); + CY(0)<='1' when SUB else '0'; + lk:for K in SM to SH generate + constant I0:BIT_VECTOR(63 downto 0):=X"AAAAAAAAAAAAAAAA"; + constant I1:BIT_VECTOR(63 downto 0):=X"CCCCCCCCCCCCCCCC"; + constant I2:BIT_VECTOR(63 downto 0):=X"F0F0F0F0F0F0F0F0"; + constant I3:BIT_VECTOR(63 downto 0):=X"FF00FF00FF00FF00"; + constant I4:BIT_VECTOR(63 downto 0):=X"FFFF0000FFFF0000"; + constant I5:BIT_VECTOR(63 downto 0):=X"FFFFFFFF00000000"; + signal I_4:STD_LOGIC; + begin + I_4<='1' when SUB else '0'; + l6:LUT6_2 generic map(INIT=>(I5 and (I2 xor I3 xor I4)) or (not I5 and ((I2 xor I4) and I3))) + port map(I0=>'0',I1=>'0',I2=>SB(K),I3=>SA(K),I4=>I_4,I5=>'1',O5=>O5(K-SM),O6=>O6(K-SM)); + end generate; + + SI<=STD_LOGIC_VECTOR(RESIZE(O6,SI'length)); + DI<=STD_LOGIC_VECTOR(RESIZE(O5,DI'length)); + lj:for J in 0 to (SH-SM)/8 generate + begin + i1:if DSP48E=1 generate -- 7-series + cl:CARRY4 port map(CI=>CY(8*J), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+3 downto 8*J), -- 4-bit carry-MUX data in + S=>SI(8*J+3 downto 8*J), -- 4-bit carry-MUX select input + CO=>CY(8*J+4 downto 8*J+1), -- 4-bit carry out + O=>O(8*J+3 downto 8*J)); -- 4-bit carry chain XOR data out + ch:CARRY4 port map(CI=>CY(8*J+4), -- 1-bit carry cascade input + CYINIT=>'0', -- 1-bit carry initialization + DI=>DI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX data in + S=>SI(8*J+7 downto 8*J+4), -- 4-bit carry-MUX select input + CO=>CY(8*J+8 downto 8*J+5), -- 4-bit carry out + O=>O(8*J+7 downto 8*J+4)); -- 4-bit carry chain XOR data out + end generate; + i2:if DSP48E=2 generate -- US/US+ + c8:CARRY8 generic map(CARRY_TYPE=>"SINGLE_CY8") -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8) + port map(CI=>CY(8*J), -- 1-bit input: Lower Carry-In + CI_TOP=>'0', -- 1-bit input: Upper Carry-In + DI=>DI(8*J+7 downto 8*J), -- 8-bit input: Carry-MUX data in + S=>SI(8*J+7 downto 8*J), -- 8-bit input: Carry-mux select + CO=>CY(8*J+8 downto 8*J+1), -- 8-bit output: Carry-out + O=>O(8*J+7 downto 8*J)); -- 8-bit output: Carry chain XOR data out + end generate; + end generate; + +-- ll:for L in SM to SH+1 generate + ll:for L in SM to SH generate +-- S(L)<=O(L-SM+1); + S(L)<=O(L-SM); + end generate; + S(SH+1)<=S(SH); + + ia:if A'low'0'); + begin + process(CLK) + begin + if rising_edge(CLK) then + iP<=RESIZE(S,P'high,P'low); + end if; + end process; + P<=iP; + end generate; +end FAST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: TABLE.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: TABLE +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, SinCos Table Module +-- +-- Latency is always 2 +-- when INV_FFT=FALSE W=exp(-2.0*PI*i*JK/N) and when INV_FFT=TRUE W=exp(2.0*PI*i*JK/N) +-- to maximize W output bit size utilization W.RE and W.IM are always negative (MSB='1') and that bit could be ignored, this is why W.RE'length can be 19 bits but a single BRAM would still be used +-- when W.RE or W.IM need to be positive CS respectively SS are TRUE, same thing when they are 0.0 CZ respectively SZ are TRUE - the complex multiplier has to use CS, SS, CZ and SZ, not just W to produce the correct result +-- the SIN and COS ROM table sizes are N/4 deep and W.RE'length-1 wide (it is implictly assumed that W.RE and W.IM always have the same range) +-- if STYLE="block" a single dual port BRAM is used for both tables +-- if STYLE="distributed" then two fabric LUT based ROMs are used +-- as a general rule for N<2048 "distributed" should be used, otherwise "block" makes more sense but this is not a hard rule +-- W range is unconstrained but W.RE'high and W.IM'high really have to be 0 all the time, do not use other values +-- the maximum SNR without using extra BRAMs is achieved when W.RE'low and W.IM'low are -18 so W.RE'length and W.IM'length are 19 bits but they can be less than that - this would reduce SNR and save resources only when STYLE="distributed" +-- TABLE.VHD also works with more than 19 bits but the current complex multiplier implementation does not support that - this would essentially double the number of BRAMs and DSP48s used and seems too high a price to pay for a few extra dB of SNR +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use IEEE.MATH_REAL.all; + +use work.COMPLEX_FIXED_PKG.all; + +--!! entity TABLE is -- LATENCY=3 (2 if SEPARATE_SIGN is TRUE) +entity TABLE is -- LATENCY=4 (3 if SEPARATE_SIGN is TRUE) when SPLIT_RADIX=0 else LATENCY=0 + generic(N:INTEGER:=1024; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and J*1 or J*3 with J>0 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + SEPARATE_SIGN:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2; -- use 1 for 7-series and 2 for US/US+ + STYLE:STRING:="block"); -- use only "block" or "distributed" + port(CLK:in STD_LOGIC; + JK:in UNSIGNED; + VI:in BOOLEAN; + W:out CFIXED; + CS,SS,CZ,SZ:out BOOLEAN; + VO:out BOOLEAN); +end TABLE; + +architecture TEST of TABLE is +--2008 constant WH:INTEGER:=W.RE'high-1+BOOLEAN'pos(SEPARATE_SIGN); +--2008 constant WL:INTEGER:=W.RE'low; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 + constant WH:INTEGER:=(W'high+1)/2-1-1+BOOLEAN'pos(SEPARATE_SIGN); + constant WL:INTEGER:=W'low/2; -- SNR=110.06dB with WL=-17 and 116.27dB with WL=-18 +begin + i0:if SPLIT_RADIX=0 generate + type wSFIXED_VECTOR is array(INTEGER range <>) of SFIXED(WH-1 downto WL); -- local constrained array of SFIXED type +--2008 function LUT_VALUE(N,WH,WL:INTEGER) return SFIXED_VECTOR is +--2008 variable RESULT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL); + function LUT_VALUE(N,WH,WL:INTEGER) return wSFIXED_VECTOR is + variable RESULT:wSFIXED_VECTOR(0 to N/4-1); + begin + RESULT(0):=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + for J in 1 to N/4-1 loop + RESULT(J):=TO_SFIXED(-COS(-2.0*MATH_PI*REAL(J)/REAL(N))+2.0**(WL-1),WH,WL)(WH-1 downto WL); -- round and drop MSB, it is always 1 + if RESULT(J)=TO_SFIXED(-1.0,WH,WL)(WH-1 downto WL) then + RESULT(J):=TO_SFIXED(-1.0+2.0**WL,WH,WL)(WH-1 downto WL); + end if; + end loop; + return RESULT; + end; + + signal JKD:UNSIGNED(JK'range):=(others=>'0'); + signal KC,KS:UNSIGNED(JK'range):=(others=>'0');--!! + signal DC,C,DS,S:SFIXED(WH-1 downto WL):=(others=>'0'); +--2008 signal LUT:SFIXED_VECTOR(0 to N/4-1)(WH-1 downto WL):=LUT_VALUE(N,WH,WL); + signal LUT:wSFIXED_VECTOR(0 to N/4-1):=LUT_VALUE(N,WH,WL); + attribute rom_style:STRING; + attribute rom_style of LUT:signal is STYLE; + signal RC,RS:BOOLEAN:=FALSE; + signal MC,MS:STD_LOGIC:='0'; + signal CS1,SS1,CS2,SS2:BOOLEAN:=FALSE; + signal W_RE,W_IM:SFIXED((W'high+1)/2-1 downto W'low/2); + begin + process(CLK) + begin + if rising_edge(CLK) then +--!! +--2008 KC<=JK when JK(JK'high-1)='0' else (not JK)+1; +--2008 KS<=(not JK)+1 when JK(JK'high-1)='0' else JK; + if JK(JK'high-1)='0' then + KC<=JK; + KS<=(not JK)+1; + else + KC<=(not JK)+1; + KS<=JK; + end if; + JKD<=JK; + if (JKD and TO_UNSIGNED(2**(JK'length-2)-1,JK'length))=0 then --mask first two MSBs of JK + RC<=JKD(JK'high-1)='1'; + RS<=JKD(JK'high-1)='0'; + else + RC<=FALSE; + RS<=FALSE; + end if; + DC<=LUT(TO_INTEGER(KC and TO_UNSIGNED(2**(KC'length-2)-1,KC'length))); + DS<=LUT(TO_INTEGER(KS and TO_UNSIGNED(2**(KS'length-2)-1,KS'length))); + if RC then + C<=(others=>'0'); + MC<='0'; + else + C<=DC; + MC<='1'; + end if; + if RS then + S<=(others=>'0'); + MS<='0'; + else + S<=DS; + MS<='1'; + end if; + CS1<=JKD(JK'high)=JKD(JK'high-1); + SS1<=(JKD(JK'high)='1') xor INV_FFT; + CS2<=CS1; + SS2<=SS1; + end if; + end process; + + i0:if SEPARATE_SIGN generate +--2008 W.RE<=MC&C; +--2008 W.IM<=MS&S; + W(W'length/2-1+W'low downto W'low)<=CFIXED(MC&C); + W(W'high downto W'length/2+W'low)<=CFIXED(MS&S); + CS<=CS2; + SS<=SS2; +-- else generate + end generate; + i1:if not SEPARATE_SIGN generate + signal WRE,WIM:SFIXED(WH downto WL):=(others=>'0'); + attribute keep:STRING; + attribute keep of WRE:signal is "yes"; + attribute keep of WIM:signal is "yes"; + signal ZERO:SFIXED(WH downto WL):=TO_SFIXED(0.0,WH,WL); + begin + WRE<=MC&C; + WIM<=MS&S; + + process(CLK) + begin + if rising_edge(CLK) then + CS<=CS2; + SS<=SS2; + CZ<=WRE(WRE'high)='0'; + SZ<=WIM(WIM'high)='0'; + end if; + end process; + ar:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WRE, + SUB=>CS2, +--2008 P=>W.RE); -- P=±B + P=>W_RE); -- P=±B + ai:entity work.ADDSUB generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + A=>ZERO, + B=>WIM, + SUB=>SS2, +--2008 P=>W.IM); -- P=±B + P=>W_IM); -- P=±B + W(W'length/2-1+W'low downto W'low)<=CFIXED(W_RE); + W(W'high downto W'length/2+W'low)<=CFIXED(W_IM); +-- end; + end generate; + +--!! b2:entity work.BDELAY generic map(SIZE=>3-BOOLEAN'pos(SEPARATE_SIGN)) + b2:entity work.BDELAY generic map(SIZE=>4-BOOLEAN'pos(SEPARATE_SIGN)) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- else generate + i1:if SPLIT_RADIX>0 generate + begin + i0:if SEPARATE_SIGN generate +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + end generate; +-- else generate + ii:if not SEPARATE_SIGN generate + begin +--2008 W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W); + W<=TO_CFIXED(COS(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),SIN(-2.0*MATH_PI*REAL(SPLIT_RADIX)/REAL(N))+2.0**(WL-1),W'high/2,W'low/2); + CS<=FALSE; + SS<=FALSE; + CZ<=(SPLIT_RADIX=N/4) or (SPLIT_RADIX=3*N/4); + SZ<=(SPLIT_RADIX=0) or (SPLIT_RADIX=N/2); +-- end; + end generate; + VO<=VI; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3 +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Complex Multiplier Using 3 DSP48E2s +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3 is -- LATENCY=6 + generic(ROUNDING:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED; -- I.RE'length and I.IM'length<27 + W:in CFIXED; -- W must be (1 downto -16) or (1 downto -17) + CS,SS,CZ,SZ:in BOOLEAN:=FALSE; + VI:in BOOLEAN; + O:out CFIXED; + VO:out BOOLEAN); +end CM3; + +architecture TEST of CM3 is + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute loc:STRING; + +--2008 constant HMAX:INTEGER:=MAX(I.RE'high,I.IM'high)+MAX(W.RE'high,W.IM'high)+3; +--2008 constant LMIN:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(I.RE'low,I.IM'low)+work.COMPLEX_FIXED_PKG.MIN(W.RE'low,W.IM'low); + constant HMAX:INTEGER:=(I'high+1)/2-1+(W'high+1)/2-1+3; + constant LMIN:INTEGER:=I'low/2+W'low/2; + +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,1) downto MAX(W.RE'low,-16)); +-- signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'high,0) downto MAX(W.RE'low,-17)); +--2008 signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W.RE'low+17,1) downto W.RE'low); -- we only have 18 bits max to work with +--2008 signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); +--2008 signal IRE1D,IRE2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); +--2008 signal IIM1D,IIM2D:SFIXED(I.IM'range):=TO_SFIXED(0.0,I.IM'high,I.IM'low); + signal WRE,WIM:SFIXED(work.COMPLEX_FIXED_PKG.MIN(W'low/2+17,1) downto W'low/2); -- we only have 18 bits max to work with + signal WRE1D,nWRE2D:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal IRE,IRE1D,IRE2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal IIM,IIM1D,IIM2D:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal CS2D,SS2D:BOOLEAN; + signal C0S1:BOOLEAN:=FALSE; + signal P1,P2,P3:SFIXED(HMAX downto LMIN); + signal P2D:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal C1,C2,C3:SFIXED(HMAX downto LMIN):=(others=>'0'); + signal AC1,AC2:STD_LOGIC_VECTOR(29 downto 0); + signal BC1:STD_LOGIC_VECTOR(17 downto 0); + signal PC1,PC2:STD_LOGIC_VECTOR(47 downto 0); +--2008 signal A_ZERO:SFIXED(I.RE'range):=TO_SFIXED(0.0,I.RE'high,I.RE'low); + signal A_ZERO:SFIXED((I'high+1)/2-1 downto I'low/2):=TO_SFIXED(0.0,(I'high+1)/2-1,I'low/2); + signal B_ZERO:SFIXED(WRE'range):=TO_SFIXED(0.0,WRE'high,WRE'low); + signal C_ZERO:SFIXED(HMAX downto LMIN):=TO_SFIXED(0.0,HMAX,LMIN); + signal BR,BI:BOOLEAN; + signal iO:CFIXED(O'range); +begin +--!! +--2008 WRE<=RESIZE(W.RE,WRE); + WRE<=RESIZE(RE(W),WRE); +--!! WRE<=TO_SFIXED(1.0-2.0**WRE'low,WRE) when W.RE=TO_SFIXED(1.0,W.RE) else RESIZE(W.RE,WRE); +--!! +--2008 WIM<=RESIZE(W.IM,WIM); + WIM<=RESIZE(IM(W),WIM); + process(CLK) + begin + if rising_edge(CLK) then + WRE1D<=WRE; +--2008 IRE1D<=I.RE; +--2008 IIM1D<=I.IM; + IRE1D<=RE(I); + IIM1D<=IM(I); +--2008 C0S1<=CZ and (W.IM(W.IM'high)='0'); + C0S1<=CZ and (W(W'high)='0'); +--!! + NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! if WRE1D=TO_SFIXED(-1.0,WRE1D) then +--!! for K in NWRE2D'range loop +--!! NWRE2D(K)<=not WRE1D(K); +--!! end loop; +--!! else +--!! NWRE2D<=RESIZE(-WRE1D,NWRE2D); +--!! end if; +--!! + IRE2D<=IRE1D; + IIM2D<=IIM1D; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and C0S1 then + if (W'low/2=-17) and C0S1 then + C1<=RESIZE(SHIFT_LEFT(IRE1D+IIM1D,1),C1); + else + C1<=TO_SFIXED(0.0,C1); + end if; + end if; + end process; + + IRE<=RE(I); + IIM<=IM(I); + dsp1:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"00101", -- (D+A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110000101", -- PCOUT=-C-(D+A1)*B2 +--2008 A=>I.RE, + A=>IRE, + B=>WIM, + C=>C1, +--2008 D=>I.IM, + D=>IIM, + ACOUT=>AC1, + BCOUT=>BC1, + P=>P1, + PCOUT=>PC1); + +-- C2<=TO_SFIXED(2.0**(O.RE'low-1),C2) when ROUNDING else TO_SFIXED(0.0,C2); + BR<=W(W'length/2-1+W'low)='0'; + BI<=W(W'high)='0'; + cd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.RE(W.RE'high)='0', + I=>BR, + O=>CS2D); + sd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, +--2008 I=>W.IM(W.IM'high)='0', + I=>BI, + O=>SS2D); + process(CLK) + begin + if rising_edge(CLK) then +--2008 if (W.RE'low=-17) and CS2D=SS2D then + if (W'low/2=-17) and CS2D=SS2D then + if CS2D then + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)+SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(I.RE,C2); + C2<=RESIZE(SHIFT_LEFT(IRE2D,1),C2); + end if; + else + if ROUNDING then +--2008 C2<=RESIZE(TO_SFIXED(2.0**(O.RE'low-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + C2<=RESIZE(TO_SFIXED(2.0**(O'low/2-1),C2)-SHIFT_LEFT(IRE2D,1),C2); + else +--2008 C2<=RESIZE(-I.RE,C2); + C2<=RESIZE(-SHIFT_LEFT(IRE2D,1),C2); + end if; + end if; + else + if ROUNDING then +--2008 C2<=TO_SFIXED(2.0**(O.RE'low-1),C2); + C2<=TO_SFIXED(2.0**(O'low/2-1),C2); + else + C2<=TO_SFIXED(0.0,C2); + end if; + end if; + end if; + end process; + + dsp2:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL=>"AD", -- Selects B input to multiplier (AD, B) + B_INPUT=>"CASCADE", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL=>"B", -- Selects input to preadder (A, B) + AREG=>2) -- Pipeline stages for A (0-2) + port map(CLK=>CLK, + INMODE=>"10100", -- (D+B1)*A2 + ALUMODE=>"0000", -- Z+W+X+Y + OPMODE=>"110010101", -- PCOUT=PCIN+C+(D+B1)*A2 + A=>A_ZERO, + B=>B_ZERO, + C=>C2, + D=>WRE1D, + ACIN=>AC1, + BCIN=>BC1, + PCIN=>PC1, + ACOUT=>AC2, + P=>P2, + PCOUT=>PC2); + +-- C3<=RESIZE(SHIFT_RIGHT(P1,-16-W.RE'low),P1); + C3<=P1; + dsp3:entity work.DSP48E2GW generic map(DSP48E=>DSP48E, -- 1 for DSP48E1, 2 for DSP48E2 + AMULTSEL=>"AD", -- Selects A input to multiplier (A, AD) + A_INPUT=>"CASCADE", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BREG=>2) -- Pipeline stages for B (0-2) + port map(CLK=>CLK, + INMODE=>"01101", --5x"0C", -- (D-A1)*B2 + ALUMODE=>"0011", -- Z-W-X-Y + OPMODE=>"110010101", -- PCOUT=PCIN-C-(D-A1)*B2 + A=>A_ZERO, + B=>NWRE2D, + C=>C3, + D=>IIM2D, + ACIN=>AC2, + PCIN=>PC2, + P=>P3); + + process(CLK) + begin + if rising_edge(CLK) then +--2008 O.RE<=RESIZE(P2,O.RE); + P2D<=P2; + end if; + end process; +--2008 O.IM<=RESIZE(P3,O.IM); +-- O<=RESIZE(TO_CFIXED(P2D,P3),O); + O<=RESIZE(TO_CFIXED(P2D,P3),iO); + + bd:entity work.BDELAY generic map(SIZE=>6) + port map(CLK=>CLK, + I=>VI, + O=>VO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. 3 +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: CM3FFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: CM3FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic Complex Multiplier Stage Module - uses 3 DSP48s/complex multiplication +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity CM3FFT is -- LATENCY=10 + generic(N:INTEGER; + RADIX:INTEGER; + SPLIT_RADIX:INTEGER:=0; -- 0 for use in systolic FFT and 1 or 3 for use in parallel Split Radix FFT + INV_FFT:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end CM3FFT; + +architecture TEST of CM3FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + function STYLE(N:INTEGER) return STRING is + begin + if N>BRAM_THRESHOLD then + return "block"; + else + return "distributed"; + end if; + end; + + function TABLE_LATENCY(SPLIT_RADIX:INTEGER) return INTEGER is + begin + if SPLIT_RADIX=0 then + return 4; + else + return 0; + end if; + end; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + signal CNT:UNSIGNED(L2N-L2R-1 downto 0):=(others=>'0'); + signal I0:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal O0:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + +--!! cd:entity work.CDELAY generic map(SIZE=>3+6) + I0<=ELEMENT(I,0,RADIX); + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, +--2008 I=>I(I'low), +--2008 O=>O(O'low)); + I=>I0, + O=>O0); + O(O'length/RADIX-1+O'low downto O'low)<=CFIXED_VECTOR(O0); + + process(CLK) + begin + if rising_edge(CLK) then + if not VI or (SPLIT_RADIX/=0) then + CNT<=(others=>'0'); + else + CNT<=CNT+1; + end if; + end if; + end process; + +--2008 lk:for J in 1 to I'length-1 generate + lk:for J in 1 to RADIX-1 generate + signal JK:UNSIGNED(L2N-1 downto 0):=(others=>'0'); +--2008 signal W:CFIXED(RE(W_high downto W_low),IM(W_high downto W_low)); + signal W:CFIXED(2*(W_high+1)-1 downto 2*W_low); + signal V,CZ:BOOLEAN; +--2008 signal ID:CFIXED(RE(I(I'low).RE'high downto I(I'low).RE'low),IM(I(I'low).IM'high downto I(I'low).IM'low)); + signal ID:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal IJ:CFIXED((I'high+1)/RADIX-1 downto I'low/RADIX); + signal OJ:CFIXED((O'high+1)/RADIX-1 downto O'low/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if SPLIT_RADIX=0 then + if not VI or (CNT=N/RADIX-1) then + JK<=(others=>'0'); + else + JK<=JK+J; + end if; + else + JK<=TO_UNSIGNED(J*SPLIT_RADIX,JK'length); + end if; + end if; + end process; + + ut:entity work.TABLE generic map(N=>N, + INV_FFT=>INV_FFT, + DSP48E=>DSP48E, + STYLE=>STYLE(N/4)) + port map(CLK=>CLK, + JK=>JK, + VI=>VI, + CZ=>CZ, + W=>W, + VO=>V); + + IJ<=ELEMENT(I,J,RADIX); +--!! cd:entity work.CDELAY generic map(SIZE=>3) + cd:entity work.CDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)) + port map(CLK=>CLK, +--2008 I=>I(I'low+J), + I=>IJ, + O=>ID); + + u1:entity work.CM3 generic map(ROUNDING=>ROUNDING, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ID, + W=>W, + CZ=>CZ, + VI=>V, +--2008 O=>O(O'low+J), + O=>OJ, + VO=>open); + O((J+1)*O'length/RADIX-1+O'low downto J*O'length/RADIX+O'low)<=CFIXED_VECTOR(OJ); + end generate; + +--!! bd:entity work.BDELAY generic map(SIZE=>3+6) + bd:entity work.BDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>VI, + O=>VO); + +--!! ud:entity work.UDELAY generic map(SIZE=>3+6) + ud:entity work.UDELAY generic map(SIZE=>TABLE_LATENCY(SPLIT_RADIX)+6) + port map(CLK=>CLK, + I=>SI, + O=>SO); +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: PARFFT.vhd +-- / / Date Last Modified: 16 Apr 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: PARFFT +-- Purpose: Generic Parallel FFT Module (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-April-16 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Parallel FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use ieee.math_real.all; +use ieee.math_complex.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity PARFFT is + generic(N:INTEGER:=4; + F:INTEGER:=0; + INV_FFT:BOOLEAN:=FALSE; + ROUNDING:BOOLEAN:=FALSE; + W_high:INTEGER:=1; + W_low:INTEGER:=-16; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end PARFFT; + +architecture TEST of PARFFT is + constant I_low:INTEGER:=I'low/2/N; + constant I_high:INTEGER:=I'length/2/N-1+I_low; + constant O_low:INTEGER:=O'low/2/N; + constant O_high:INTEGER:=O'length/2/N-1+O_low; + + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + + constant L2N:INTEGER:=LOG2(N); +begin +--2008 assert I'length=O'length report "Ports I and O must have the same length!" severity warning; + assert SI'length=SO'length report "Ports SI and SO must have the same length!" severity warning; + + f0:if F=0 generate + begin + l2:if N=2 generate -- FFT2 case + signal I0,I1:CFIXED(2*I_high+1 downto 2*I_low); + signal O0,O1:CFIXED(2*O_high+1 downto 2*O_low); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,2); + I1<=ELEMENT(I,1,2); +-- complex add/sub butterfly with scaling and overflow detection + bf:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I1, + SCALE=>SI(SI'low), + O0=>O0, + O1=>O1, + OVR=>SO(SO'high)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/2-1+O'low downto 0*O'length/2+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/2-1+O'low downto 1*O'length/2+O'low)<=CFIXED_VECTOR(O1); + + process(CLK) + begin + if rising_edge(CLK) then + iSO<=SI(SI'high downto SI'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>1) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=4 generate -- FFT4 case + l4:if N=4 generate -- FFT4 case + signal I0,I1,I2,I3:CFIXED(2*I_high+1 downto 2*I_low); + signal P0,P1,P2,P3,P3S:CFIXED(2*I_high+3 downto 2*I_low); + signal O0,O1,O2,O3,O1S,O3S:CFIXED(2*O_high+1 downto 2*O_low); + signal S:UNSIGNED(SI'range):=(others=>'0'); + signal OVR1,OVR2:UNSIGNED(1 downto 0); + signal iSO:UNSIGNED(SO'high-1 downto SO'low):=(others=>'0'); + begin +-- unpack CFIXED_VECTOR I + I0<=ELEMENT(I,0,4); + I1<=ELEMENT(I,1,4); + I2<=ELEMENT(I,2,4); + I3<=ELEMENT(I,3,4); +-- complex add/sub butterflies with scaling and overflow detection + u0:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I0, + I1=>I2, + SCALE=>SI(SI'low), + O0=>P0, + O1=>P1, + OVR=>OVR1(0)); + + u1:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>I1, + I1=>I3, + SCALE=>SI(SI'low), + O0=>P2, + O1=>P3, + OVR=>OVR1(1)); + + process(CLK) + begin + if rising_edge(CLK) then + S<=(OVR1(0) or OVR1(1))&SI(SI'high downto SI'low+1); + end if; + end process; + + u2:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P0, + I1=>P2, + SCALE=>S(S'low), + O0=>O0, + O1=>O2, + OVR=>OVR2(0)); + + P3S<=SWAP(P3); + u3:entity work.CBFS generic map(DSP48E=>DSP48E) + port map(CLK=>CLK, + I0=>P1, + I1=>P3S, + SCALE=>S(S'low), + O0=>O1S, + O1=>O3S, + OVR=>OVR2(1)); + O1<=TO_CFIXED(RE(O1S),IM(O3S)); + O3<=TO_CFIXED(RE(O3S),IM(O1S)); +-- pack CFIXED_VECTOR O + O((0+1)*O'length/4-1+O'low downto 0*O'length/4+O'low)<=CFIXED_VECTOR(O0); + O((1+1)*O'length/4-1+O'low downto 1*O'length/4+O'low)<=CFIXED_VECTOR(O1); + O((2+1)*O'length/4-1+O'low downto 2*O'length/4+O'low)<=CFIXED_VECTOR(O2); + O((3+1)*O'length/4-1+O'low downto 3*O'length/4+O'low)<=CFIXED_VECTOR(O3); + + SO(SO'high)<=(OVR2(0) or OVR2(1)); + process(CLK) + begin + if rising_edge(CLK) then + iSO<=S(S'high downto S'low+1); + end if; + end process; + SO(SO'high-1 downto SO'low)<=iSO; + + bd:entity work.BDELAY generic map(SIZE=>2) + port map(CLK=>CLK, + I=>VI, + O=>VO); +-- end; + end generate; +-- elsif N=8 generate -- FFT8 case + l8:if N=8 generate -- FFT8 case +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/8/2-(I'high+1)/8/2; + constant X:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,1); -- ModelSim workaround + signal iV:BOOLEAN_VECTOR(0 to 3); +--2008 signal S:UNSIGNED_VECTOR(0 to 3)(SI'range); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:TUV(0 to 3); + signal SS:UNSIGNED(SI'range); + signal P:CFIXED_VECTOR(I'high+8*2*X downto I'low); + signal VP:BOOLEAN; + signal SP:UNSIGNED(SI'range); + signal oV:BOOLEAN_VECTOR(0 to 1); +--2008 signal oS:UNSIGNED_VECTOR(0 to 1)(SO'range); + signal oS:TUV(0 to 1); + begin + s1:for K in 0 to 3 generate +--2008 signal II:CFIXED_VECTOR(0 to 1)(RE(I(0).RE'high downto I(0).RE'low),IM(I(0).IM'high downto I(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 1)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); + signal II:CFIXED_VECTOR(4*(I_high+1)-1 downto 4*I_low); + signal OO:CFIXED_VECTOR(4*(I_high+1+2*X)-1 downto 4*I_low); + signal OO0,OO1:CFIXED(2*(I_high+1+2*X)-1 downto 2*I_low); + signal P0,P1:CFIXED(I'length/8+2*X-1+I'low/8 downto I'low/8); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=I(K); +--2008 II(1)<=I(K+4); + II((0+1)*II'length/2-1+II'low downto 0*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K,8)); + II((1+1)*II'length/2-1+II'low downto 1*II'length/2+II'low)<=CFIXED_VECTOR(ELEMENT(I,K+4,8)); + p2:entity work.PARFFT generic map(N=>2, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>iV(K), + SO=>S(K)); + OO0<=ELEMENT(OO,0,2); + OO1<=ELEMENT(OO,1,2); + cd:entity work.CDELAY generic map(SIZE=>3) + port map(CLK=>CLK, +--2008 I=>OO(0), +--2008 O=>P(2*K+0)); + I=>OO0, + O=>P0); + ck:entity work.CKCM generic map(DSP48E=>DSP48E, + M=>K, + ROUNDING=>ROUNDING, + CONJUGATE=>INV_FFT) + port map(CLK=>CLK, +--2008 I=>OO(1), +--2008 O=>P(2*K+1)); + I=>OO1, + O=>P1); + P((2*K+1)*P'length/8-1+P'low downto (2*K+0)*P'length/8+P'low)<=CFIXED_VECTOR(P0); + P((2*K+2)*P'length/8-1+P'low downto (2*K+1)*P'length/8+P'low)<=CFIXED_VECTOR(P1); + end generate; + SS(SI'high)<=S(0)(SI'high) or S(1)(SI'high) or S(2)(SI'high) or S(3)(SI'high) when iV(0) else '0'; + SS(SI'high-1 downto SI'low)<=S(0)(SI'high-1 downto SI'low); + ud:entity work.UDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>SS, + O=>SP); + bd:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>iV(0), + O=>VP); + s2:for K in 0 to 1 generate +--2008 signal II:CFIXED_VECTOR(0 to 3)(RE(P(0).RE'high downto P(0).RE'low),IM(P(0).IM'high downto P(0).IM'low)); +--2008 signal OO:CFIXED_VECTOR(0 to 3)(RE(O(0).RE'high downto O(0).RE'low),IM(O(0).IM'high downto O(0).IM'low)); + signal II:CFIXED_VECTOR((P'high+1)/2-1 downto P'low/2); + signal OO:CFIXED_VECTOR((O'high+1)/2-1 downto O'low/2); + signal SS:UNSIGNED(SI'range); + begin +--2008 II(0)<=P(K+0); +--2008 II(1)<=P(K+2); +--2008 II(2)<=P(K+4); +--2008 II(3)<=P(K+6); + II((0+1)*II'length/4-1+II'low downto 0*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+0,8)); + II((1+1)*II'length/4-1+II'low downto 1*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+2,8)); + II((2+1)*II'length/4-1+II'low downto 2*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+4,8)); + II((3+1)*II'length/4-1+II'low downto 3*II'length/4+II'low)<=CFIXED_VECTOR(ELEMENT(P,K+6,8)); + p2:entity work.PARFFT generic map(N=>4, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VP, + SI=>SP, + O=>OO, + VO=>oV(K), + SO=>oS(K)); +--2008 O(K+0)<=OO(0); +--2008 O(K+2)<=OO(1); +--2008 O(K+4)<=OO(2); +--2008 O(K+6)<=OO(3); + O((K+0+1)*O'length/8-1+O'low downto (K+0)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,0,4)); + O((K+2+1)*O'length/8-1+O'low downto (K+2)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,1,4)); + O((K+4+1)*O'length/8-1+O'low downto (K+4)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,2,4)); + O((K+6+1)*O'length/8-1+O'low downto (K+6)*O'length/8+O'low)<=CFIXED_VECTOR(ELEMENT(OO,3,4)); + end generate; + VO<=oV(0); + SO(SO'high downto SO'high-1)<=oS(0)(SO'high downto SO'high-1) or oS(1)(SO'high downto SO'high-1) when oV(0) else "00"; + SO(SO'high-2 downto SO'low)<=oS(0)(SO'high-2 downto SO'low); +-- end; + end generate; +-- elsif N=2**L2N generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation + ln:if (N>8) and (N=2**L2N) generate -- FFT2**n case using Split Radix decomposition, uses recursive PARFFT instantiation +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/N/2-(I'high+1)/N/2; + constant X1:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-2); -- ModelSim workaround + constant X2:INTEGER:=work.COMPLEX_FIXED_PKG.MAX(0,work.COMPLEX_FIXED_PKG.MIN(BIT_GROWTH,L2N)-1); -- ModelSim workaround + function MUL_LATENCY(N:INTEGER) return INTEGER is + begin + return 6; + end; + function LATENCY(N:INTEGER) return INTEGER is + begin + return LOG2(N)*4-6; + end; +--2008 signal IU:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal U,UD:CFIXED_VECTOR(0 to N/2-1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); + signal IU:CFIXED_VECTOR((I'high+1)/2-1 downto I'low/2); + signal U,UD:CFIXED_VECTOR((I'high+1)/2-1+N/2*2*X2 downto I'low/2); + signal SU,SUD:UNSIGNED(SI'range); + signal VU,VU4D:BOOLEAN; +--2008 signal ZO:CFIXED_MATRIX(0 to N/4-1)(0 to 1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(2*2*(I_high+X1+1)-1 downto 2*2*I_low); -- unconstrained array of CFIXED_VECTOR + signal ZO:CFIXED_MATRIX(0 to N/4-1); + type TUV is array(NATURAL range <>) of UNSIGNED(SI'range); +--2008 signal S1:UNSIGNED_VECTOR(0 to 1)(SI'range); + signal S1:TUV(0 to 1); + signal S1I:UNSIGNED(SI'range); +--2008 signal S2:UNSIGNED_VECTOR(0 to N/4-1)(SI'range); + signal S2:TUV(0 to N/4-1); + signal S2I:UNSIGNED(SI'range):=(others=>'0'); +--2008 signal S:UNSIGNED_VECTOR(0 to N/2-1)(SI'range); + signal S:TUV(0 to N/2-1); + begin + lk:for K in 0 to N/2-1 generate +--2008 IU(K)<=I(I'low+2*K); + IU((K+1)*IU'length/N*2-1+IU'low downto K*IU'length/N*2+IU'low)<=CFIXED_VECTOR(ELEMENT(I,2*K,N)); + end generate; + pu:entity work.PARFFT generic map(N=>N/2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IU, + VI=>VI, + SI=>SI, + O=>U, + VO=>VU, + SO=>SU); + du:for K in 0 to N/2-1 generate + signal UK,UDK:CFIXED((UD'high+1)/N*2-1 downto UD'low/N*2); + begin + UK<=ELEMENT(U,K,N/2); + cd:entity work.CDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+1-LATENCY(N/2))--3) -- when CMUL latency is 6 + port map(CLK=>CLK, +--2008 I=>U(K), +--2008 O=>UD(K)); + I=>UK, + O=>UDK); + UD((K+1)*UD'length/N*2-1+UD'low downto K*UD'length/N*2+UD'low)<=CFIXED_VECTOR(UDK); + end generate; + u4:entity work.UDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>SU, + O=>SUD); + b5:entity work.BDELAY generic map(SIZE=>LATENCY(N/4)+MUL_LATENCY(N)+2-LATENCY(N/2))--4) -- when CMUL latency is 6 + port map(CLK=>CLK, + I=>VU, + O=>VO); + ll:for L in 0 to 1 generate +--2008 signal IZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal Z,OZ:CFIXED_VECTOR(0 to N/4-1)(RE(I(I'low).RE'high+X1 downto I(I'low).RE'low),IM(I(I'low).IM'high+X1 downto I(I'low).IM'low)); + signal IZ:CFIXED_VECTOR((I'high+1)/4-1 downto I'low/4); + signal Z,OZ:CFIXED_VECTOR((I'high+1)/4-1+N/4*2*X1 downto I'low/4); + signal SZ:UNSIGNED(SI'range); + signal SM:UNSIGNED(SI'range); + signal VZ:BOOLEAN; + begin + li:for J in 0 to N/4-1 generate +--2008 IZ(J)<=I(I'low+4*J+2*L+1); + IZ(2*(J+1)*(I_high-I_low+1)-1+IZ'low downto 2*J*(I_high-I_low+1)+IZ'low)<=CFIXED_VECTOR(ELEMENT(I,4*J+2*L+1,N)); + end generate; + pe:entity work.PARFFT generic map(N=>N/4, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IZ, + VI=>VI, + SI=>SI, + O=>Z, + VO=>VZ, + SO=>SZ); + me:entity work.CM3FFT generic map(N=>N, + RADIX=>N/4, + SPLIT_RADIX=>2*L+1, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>Z, + VI=>VZ, + SI=>SZ, + O=>OZ, + VO=>open, + SO=>S1(L)); + lo:for J in 0 to N/4-1 generate +--2008 ZO(J)(L)<=OZ(J); + ZO(J)((L+1)*ZO(J)'length/2-1+ZO(J)'low downto L*ZO(J)'length/2+ZO(J)'low)<=CFIXED_VECTOR(ELEMENT(OZ,J,N/4)); + end generate; + end generate; + S1I<=S1(0) or S1(1); + l2:for J in 0 to N/4-1 generate +--2008 signal O2:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal IE,IO:CFIXED_VECTOR(0 to 1)(RE(I(I'low).RE'high+X2 downto I(I'low).RE'low),IM(I(I'low).IM'high+X2 downto I(I'low).IM'low)); +--2008 signal OE,OO:CFIXED_VECTOR(0 to 1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal O2:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal IE,IO:CFIXED_VECTOR(2*2*(I_high+X2+1)-1 downto 2*2*I_low); + signal OE,OO:CFIXED_VECTOR(2*2*(O_high+1)-1 downto 2*2*O_low); + begin + p2:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>ZO(J), + VI=>TRUE, + SI=>S1I, + O=>O2, + VO=>open, + SO=>S2(J)); +--2008 IE(0)<=UD(J); +--2008 IE(1)<=O2(0); + IE((0+1)*IE'length/2-1+IE'low downto 0*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(UD,J,N/2)); + IE((1+1)*IE'length/2-1+IE'low downto 1*IE'length/2+IE'low)<=CFIXED_VECTOR(ELEMENT(O2,0,2)); + pe:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IE, + VI=>TRUE, + SI=>S2I, + O=>OE, + VO=>open, + SO=>S(2*J)); +--2008 O(O'low+J)<=OE(0); +--2008 O(O'low+J+N/2)<=OE(1); +--2008 IO(0)<=UD(J+N/4); +--2008 IO(1).RE<=O2(1).IM; +--2008 IO(1).IM<=O2(1).RE; +-- O((J+1)*O'length/N-1+O'low downto J*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); +-- O((J+N/2+1)*O'length/N-1+O'low downto (J+N/2)*O'length/N+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + O(2*(J+1)*(O_high-O_low+1)-1+O'low downto 2*J*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,0,2)); + O(2*(J+N/2+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/2)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(ELEMENT(OE,1,2)); + IO((0+1)*IO'length/2-1+IO'low downto 0*IO'length/2+IO'low)<=CFIXED_VECTOR(ELEMENT(UD,J+N/4,N/2)); + IO((1+1)*IO'length/2-1+IO'low downto 1*IO'length/2+IO'low)<=CFIXED_VECTOR(TO_CFIXED(IM(ELEMENT(O2,1,2)),RE(ELEMENT(O2,1,2)))); + po:entity work.PARFFT generic map(N=>2, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + INV_FFT=>INV_FFT, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>IO, + VI=>TRUE, + SI=>S2I, + O=>OO, + VO=>open, + SO=>S(2*J+1)); + ii:if INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(1).RE; +--2008 O(O'low+J+N/4).IM<=OO(0).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(0).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(1).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- end; + end generate; +-- else generate + id:if not INV_FFT generate + begin +--2008 O(O'low+J+N/4).RE<=OO(0).RE; +--2008 O(O'low+J+N/4).IM<=OO(1).IM; +--2008 O(O'low+J+3*N/4).RE<=OO(1).RE; +--2008 O(O'low+J+3*N/4).IM<=OO(0).IM; +-- O((J+N/4+1)*O'length/N-1+O'low downto (J+N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); +-- O((J+3*N/4+1)*O'length/N-1+O'low downto (J+3*N/4)*O'length/N+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); + O(2*(J+N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,0,2)),IM(ELEMENT(OO,1,2)))); + O(2*(J+3*N/4+1)*(O_high-O_low+1)-1+O'low downto 2*(J+3*N/4)*(O_high-O_low+1)+O'low)<=CFIXED_VECTOR(TO_CFIXED(RE(ELEMENT(OO,1,2)),IM(ELEMENT(OO,0,2)))); +-- end; + end generate; + end generate; + process(S2) + variable vS2:UNSIGNED(SI'range); + begin + vS2:=SUD; + for K in S2'range loop + vS2:=vS2 or S2(K); + end loop; + S2I<=vS2; + end process; + process(S) + variable vS:UNSIGNED(SI'range); + begin + vS:=(others=>'0'); + for K in S'range loop + vS:=vS or S(K); + end loop; + SO<=vS; + end process; +-- end; + end generate; +-- else generate + end generate; + i1:if F>0 generate + constant G:INTEGER:=2**F; -- size of each PARFFT + constant H:INTEGER:=N/G; -- number of PARFFTs +--2008 signal S:UNSIGNED_VECTOR(0 to H)(SO'range); + type TUV is array(0 to H) of UNSIGNED(SO'range); + signal S:TUV; + signal V:BOOLEAN_VECTOR(0 to H-1); + begin + S(S'low)<=(others=>'0'); + lk:for K in 0 to H-1 generate + signal SK:UNSIGNED(SO'range); +--workaround for QuestaSim bug +--2008 signal II:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal II:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin +--2008 II<=I(I'low+G*K+0 to I'low+G*K+G-1); + II<=I(I'length/H*(K+1)-1+I'low downto I'length/H*K+I'low); + bc:entity work.PARFFT generic map(N=>G, + F=>0, + INV_FFT=>INV_FFT, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>VI, + SI=>SI, + O=>OO, + VO=>V(K), + SO=>SK); +--workaround for QuestaSim bug +-- O(O'low+G*K+0 to O'low+G*K+G-1)<=OO; +--2008 lo:for J in 0 to G-1 generate +--2008 O(O'low+G*K+J)<=OO(J); +--2008 end generate; + O(O'length/H*(K+1)-1+O'low downto O'length/H*K+O'low)<=OO; + S(K+1)<=S(K) or SK; + end generate; + SO<=S(S'high); + VO<=V(V'high); +-- end; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ?? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: INPUT_SWAP.vhd +-- / / Date Last Modified: 14 February 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: INPUT_SWAP +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Input Order Swap Module for Systolic FFT +-- The module takes N samples, I'length per clock, in natural input order +-- and outputs them in natural transposed order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity INPUT_SWAP is + generic(N:INTEGER; -- N must be a power of 2 + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256; -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + USE_CB:BOOLEAN:=TRUE); -- if FALSE use alternate architecture + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; -- I'length must be a divisor of N, so it is also a power of 2 + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end INPUT_SWAP; + +architecture TEST of INPUT_SWAP is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs in last stage + + function RS(K:INTEGER) return STRING is + begin + if K) of CFIXED_VECTOR(I'range); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**LOG2(I'length) report "Port I length must be a power of 2!" severity error; + assert SSR=2**LOG2(SSR) report "SSR must be a power of 2!" severity error; + + i0:if USE_CB or (L2N<=2*L2R) generate + constant SIZE:INTEGER:=L2N/L2R; -- floor(LOG2(N)/LOG2(RADIX)) + + signal V:BOOLEAN_VECTOR(0 to SIZE-1); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE-1)(SI'range); +--2008 signal D:CFIXED_MATRIX(0 to SIZE-1)(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); + signal S:UNSIGNED_VECTOR(0 to SIZE-1); + signal D:iCFIXED_MATRIX(0 to SIZE-1); + begin + D(D'low)<=I; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-2 generate + bc:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>RADIX**K, + INPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K/RADIX), -- this helps reduce + OUTPUT_PACKING_FACTOR_ADJUST=>-(RADIX**K mod RADIX**(SIZE-2)), -- RAM count and + SHORTEN_VO_BY=>(RADIX-1)*RADIX**K mod ((RADIX-1)*RADIX**(SIZE-2))) -- latency by N/RADIX/RADIX-1 clocks + port map(CLK=>CLK, + I=>D(K), + VI=>V(K), + SI=>S(K), + O=>D(K+1), + VO=>V(K+1), + SO=>S(K+1)); + end generate; +--Last stage, it becomes a trivial assignment if F=0 + bl:block + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SI'range); + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + lj:for J in OV'range generate +--2008 signal OO:CFIXED_VECTOR(0 to G-1)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal OO:CFIXED_VECTOR((O'high+1)/H-1 downto O'low/H); + begin + bc:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>RADIX**(SIZE-1)) + port map(CLK=>CLK, +--2008 I=>D(D'high)(I'low+G*J+0 to I'low+G*J+G-1), + I=>D(D'high)(I'length/H*(J+1)-1+I'low downto I'length/H*J+I'low), + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>OV(J), + SO=>OS(J)); + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(K); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+1)-1+OO'low downto O'length/SSR*K+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); + end block; +--2008 end; + end generate; +--2008 else generate + i1:if (not USE_CB) and (L2N>2*L2R) generate + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + signal WSEL:UNSIGNED(LOG2(WCNT'length)-1 downto 0):=TO_UNSIGNED(0,LOG2(RCNT'length)); + signal RSEL:UNSIGNED(LOG2(RCNT'length)-1 downto 0):=TO_UNSIGNED(L2N-2*L2R,LOG2(RCNT'length)); +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal OV:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + if RSEL'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + WA<=ROTATE_LEFT(WCNT,TO_INTEGER(WSEL)); + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + RA<=ROTATE_LEFT(RCNT,TO_INTEGER(RSEL)); + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); + IO<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>OV); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX-RADIX-N/RADIX/RADIX+5) + port map(CLK=>CLK, + I=>SI, + O=>S); + + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>IO, + VI=>OV, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: SYSTOLIC_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: SYSTOLIC_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Generic, Arbitrary Size, Systolic FFT Module +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity SYSTOLIC_FFT is + generic(N:INTEGER; + SSR:INTEGER; --93 + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=256; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end SYSTOLIC_FFT; + +architecture TEST of SYSTOLIC_FFT is + attribute syn_hier:STRING; + attribute syn_hier of all:architecture is "hard"; + attribute keep_hierarchy:STRING; + attribute keep_hierarchy of all:architecture is "yes"; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; -- if F is not zero there will be a partial last stage + constant G:INTEGER:=2**F; -- size of each CB and PARFFT in last stage + constant H:INTEGER:=RADIX/G; -- number of CBs and PARFFTsin last stage + constant SIZE:INTEGER:=(L2N-1)/L2R; -- ceil(LOG2(N)/LOG2(RADIX)), number of stages +--2008 constant BIT_GROWTH:INTEGER:=MAX(O(O'low).RE'high,O(O'low).IM'high)-MAX(I(I'low).RE'high,I(I'low).IM'high); + constant BIT_GROWTH:INTEGER:=(O'high+1)/2/SSR-(I'high+1)/2/SSR; + +-- constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((SIZE-1)*L2R,BIT_GROWTH); + constant XL:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); +--2008 signal D:CFIXED_MATRIX(0 to SIZE)(I'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR(O'range); -- unconstrained array of CFIXED_VECTOR + signal D:CFIXED_MATRIX(0 to SIZE); + signal V:BOOLEAN_VECTOR(0 to SIZE); +--2008 signal S:UNSIGNED_VECTOR(0 to SIZE)(SI'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SI'range); --93 + signal S:UNSIGNED_VECTOR(0 to SIZE); + +-- constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(SIZE*L2R,BIT_GROWTH); + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(L2N,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal OO:CFIXED_VECTOR(O'range)(RE(O(O'low).RE'range),IM(O(O'low).IM'range)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal OO:CFIXED_VECTOR(O'range); +begin +--2008 lj:for J in I'range generate +--2008 D(D'low)(J)<=RESIZE(I(J),D(D'low)(J)); + lj:for J in 0 to SSR-1 generate + D(D'low)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(I,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + V(V'low)<=VI; + S(S'low)<=SI; + lk:for K in 0 to SIZE-1 generate + constant XI:INTEGER:=work.COMPLEX_FIXED_PKG.MIN(K*L2R,BIT_GROWTH); + constant XO:INTEGER:=work.COMPLEX_FIXED_PKG.MIN((K+1)*L2R,BIT_GROWTH); +--2008 signal DI:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XI downto I(I'low).RE'low),IM(I(I'low).IM'high+XI downto I(I'low).IM'low)); +--2008 signal DM,DB,DO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'high+XO downto I(I'low).RE'low),IM(I(I'low).IM'high+XO downto I(I'low).IM'low)); + signal DI:CFIXED_VECTOR(I'high+2*SSR*XI downto I'low); + signal DM,DB,DO:CFIXED_VECTOR(I'high+2*SSR*XO downto I'low); + signal VM,VB:BOOLEAN; + signal SM,SB:UNSIGNED(SI'range); + begin +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(K)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(K),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, --93 + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(K), + SI=>S(K), + O=>DM, + VO=>VM, + SO=>SM); + cm:entity work.CM3FFT generic map(N=>N/(RADIX**K), + RADIX=>RADIX, --93 + INV_FFT=>FALSE, + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DM, + VI=>VM, + SI=>SM, + O=>DB, + VO=>VB, + SO=>SB); + + bc:entity work.CB generic map(SSR=>RADIX, --93 + F=>F*BOOLEAN'pos(K=SIZE-1), + PACKING_FACTOR=>N/(RADIX**(K+2))*BOOLEAN'pos(KBRAM_THRESHOLD) + port map(CLK=>CLK, + I=>DB, + VI=>VB, + SI=>SB, + O=>DO, + VO=>V(K+1), + SO=>S(K+1)); +--2008 lo:for J in 0 to I'length-1 generate +--2008 D(K+1)(J)<=RESIZE(DO(DO'low+J),D(K+1)(J)); + lo:for J in 0 to SSR-1 generate + D(K+1)(O'length/SSR*(J+1)-1+O'low downto O'length/SSR*J+O'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(DO,J,SSR),(O'high+1)/2/SSR-1,O'low/2/SSR)); + end generate; + end generate; +--last PARFFT stage +--2008 li:for J in 0 to I'length-1 generate +--2008 DI(DI'low+J)<=RESIZE(D(D'high)(J),DI(DI'low+J)); + li:for J in 0 to SSR-1 generate + DI(DI'length/SSR*(J+1)-1+DI'low downto DI'length/SSR*J+DI'low)<=CFIXED_VECTOR(RESIZE(ELEMENT(D(D'high),J,SSR),(DI'high+1)/2/SSR-1,DI'low/2/SSR)); + end generate; + pf:entity work.PARFFT generic map(N=>RADIX, + F=>F, + INV_FFT=>FALSE, + ROUNDING=>ROUNDING, + W_high=>W_high, + W_low=>W_low, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>DI, + VI=>V(V'high), + SI=>S(S'high), + O=>OO, + VO=>VO, + SO=>SO); + lo:for J in 0 to H-1 generate + lk:for K in 0 to G-1 generate +--2008 O(O'low+J+H*K)<=OO(OO'low+K+G*J); + O(O'length/SSR*(J+H*K+1)-1+O'low downto O'length/SSR*(J+H*K)+O'low)<=OO(O'length/SSR*(K+G*J+1)-1+OO'low downto O'length/SSR*(K+G*J)+OO'low); + end generate; + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DS.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DS +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Transposed Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DS is -- LATENCY=0 when N=2*SSR else LATENCY=N/SSR+1 + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DS; + +architecture TEST of DS is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute ram_style:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + + signal VI1D:BOOLEAN:=FALSE; + signal V:BOOLEAN; +--2008 signal I1D:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(I'range=>(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0'))); + signal I1D:CFIXED_VECTOR(I'range):=(others=>'0'); + signal WCNT,RCNT:UNSIGNED(LOG2(N/RADIX)-1 downto 0):=(others=>'0'); + signal WA:UNSIGNED(WCNT'range):=(others=>'0'); + signal RA:UNSIGNED(RCNT'range):=(others=>'0'); + + function RS(K:INTEGER) return STRING is + begin + if K) of UNSIGNED(RCNT'range); --93 + function IDENTITY(K:INTEGER) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(0 to K-1);--93 (LOG2(K)-1 downto 0); + begin + for J in RESULT'range loop + RESULT(J):=TO_UNSIGNED(J,RESULT(J)'length); + end loop; + return RESULT; + end; + + function PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT((A'length/L2R-1-J)*L2R+K+F):=A(J*L2R+K); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(K):=A(A'length/L2R*L2R+K); + end loop; + end loop; + return RESULT; + end; + + function INVERSE_PERMUTE(A:UNSIGNED_VECTOR) return UNSIGNED_VECTOR is + variable RESULT:UNSIGNED_VECTOR(A'range);--93 (A(A'low)'range); + begin + for J in RESULT'range loop + for J in 0 to A'length/L2R-1 loop + for K in 0 to L2R-1 loop + RESULT(J*L2R+K):=A((A'length/L2R-1-J)*L2R+K+F); + end loop; + end loop; + for K in 0 to F-1 loop + RESULT(A'length/L2R*L2R+K):=A(K); + end loop; + end loop; + return RESULT; + end; + +--2008 signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1)(LOG2(WCNT'length)-1 downto 0):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); +--2008 signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1)(LOG2(RCNT'length)-1 downto 0):=IDENTITY(RCNT'length); + signal WSEL:UNSIGNED_VECTOR(0 to WCNT'length-1):=INVERSE_PERMUTE(IDENTITY(WCNT'length)); + signal RSEL:UNSIGNED_VECTOR(0 to RCNT'length-1):=IDENTITY(RCNT'length); +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i0:if L2N-L2R<2 generate + O<=I; + VO<=VI; + SO<=SI; +--2008 else generate + end generate; + i1:if L2N-L2R>=2 generate + bd:entity work.BDELAY generic map(SIZE=>N/RADIX-2) + port map(CLK=>CLK, + I=>VI, + O=>V); + + process(CLK) + begin + if rising_edge(CLK) then + if VI then + if WCNT=N/RADIX-1 then + WSEL<=RSEL; + end if; + WCNT<=WCNT+1; + else + WCNT<=(others=>'0'); + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if V then + if RCNT=N/RADIX-1 then + RSEL<=PERMUTE(WSEL); + end if; + RCNT<=RCNT+1; + else + RCNT<=(others=>'0'); + end if; + VI1D<=VI; + I1D<=I; + end if; + end process; +-- Write Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in WCNT'range loop + WA(K)<=WCNT(TO_INTEGER(WSEL(K))); + end loop; + end if; + end process; +-- Read Address Digit Swapping + process(CLK) + begin + if rising_edge(CLK) then + for K in RCNT'range loop + RA(K)<=RCNT(TO_INTEGER(RSEL(K))); + end loop; + end if; + end process; + +--2008 lk:for K in 0 to I'length-1 generate + lk:if TRUE generate +--? Vivado synthesis does not infer RAM from this code, just LUTs and FFs +-- signal MEM:CFIXED_VECTOR(0 to 2**(CNT'length+1)-1)(RE(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).RE)),IM(high_f(I(low_f(I)).RE) downto low_f(I(low_f(I)).IM))):=(0 to 2**(CNT'length+1)-1=>(RE=>(I(low_f(I)).RE'range=>'0'),IM=>(I(low_f(I)).IM'range=>'0'))); +--2008 signal MEMR:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 signal MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).IM'range):=(0 to 2**WCNT'length-1=>(I(I'low).IM'range=>'0')); +--2008 signal Q:CFIXED(RE(I(I'low).RE'range),IM(I(I'low).IM'range)):=(RE=>(I(I'low).RE'range=>'0'),IM=>(I(I'low).RE'range=>'0')); + type iCFIXED_MATRIX is array(NATURAL range <>) of CFIXED_VECTOR(I'range); + signal MEM:iCFIXED_MATRIX(0 to 2**WCNT'length-1):=(0 to 2**WCNT'length-1=>(others=>'0')); + signal Q:CFIXED_VECTOR(I'range):=(others=>'0'); +--WBR shared variable MEMR,MEMI:SFIXED_VECTOR(0 to 2**WCNT'length-1)(I(I'low).RE'range):=(0 to 2**WCNT'length-1=>(I(I'low).RE'range=>'0')); +--2008 attribute ram_style of MEMR:signal is RS(N/RADIX); +--2008 attribute ram_style of MEMI:signal is RS(N/RADIX); + attribute ram_style of MEM:signal is RS(N/RADIX); + begin + process(CLK) + begin + if rising_edge(CLK) then + if VI1D then + MEM(TO_INTEGER(WA))<=I1D; +--2008 MEMR(TO_INTEGER(WA))<=I1D(K).RE; +--2008 MEMI(TO_INTEGER(WA))<=I1D(K).IM; +-- MEMR(TO_INTEGER(WA)):=I1D(K).RE; +-- MEMI(TO_INTEGER(WA)):=I1D(K).IM; +--WBR Q.RE<=I1D(K).RE; +--WBR Q.IM<=I1D(K).IM; +--WBR else +--WBR Q.RE<=MEMR(TO_INTEGER(WA)); +--WBR Q.IM<=MEMI(TO_INTEGER(WA)); + end if; + Q<=MEM(TO_INTEGER(RA)); +--2008 Q.RE<=MEMR(TO_INTEGER(RA)); +--2008 Q.IM<=MEMI(TO_INTEGER(RA)); +--2008 O(K)<=Q; + O<=Q; + end if; + end process; + end generate; + + bo:entity work.BDELAY generic map(SIZE=>3) + port map(CLK=>CLK, + I=>V, + O=>VO); + + sd:entity work.UDELAY generic map(SIZE=>N/RADIX+1) + port map(CLK=>CLK, + I=>SI, + O=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- © Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: DSN.vhd +-- / / Date Last Modified: 14 Feb 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: DSN +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Feb-14 Initial final release +-------------------------------------------------------------------------------- +-- +-- Module Description: Output Order Swap Module for Systolic FFT (Digit Swap) +-- Produces Natural Output Order +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity DSN is + generic(N:INTEGER; + SSR:INTEGER; -- SSR must be a power of 2 + BRAM_THRESHOLD:INTEGER:=256); -- adjust this threshold to trade utilization between Distributed RAMs and BRAMs + port(CLK:in STD_LOGIC; + I:in CFIXED_VECTOR; + VI:in BOOLEAN; + SI:in UNSIGNED; + O:out CFIXED_VECTOR; + VO:out BOOLEAN; + SO:out UNSIGNED); +end DSN; + +architecture TEST of DSN is + attribute syn_keep:STRING; + attribute syn_keep of all:architecture is "hard"; + attribute rloc:STRING; + +--2008 constant RADIX:INTEGER:=I'length; -- this is the Systolic FFT RADIX or SSR + constant RADIX:INTEGER:=SSR; -- this is the Systolic FFT RADIX or SSR + constant L2N:INTEGER:=LOG2(N); + constant L2R:INTEGER:=LOG2(RADIX); + constant F:INTEGER:=L2N mod L2R; + constant G:INTEGER:=2**F; + constant H:INTEGER:=RADIX/G; +begin + assert I'length=O'length report "Ports I and O must have the same length!" severity error; +--2008 assert I'length=2**L2R report "Port I length must be a power of 2!" severity error; + assert SSR=2**L2R report "Port I length must be a power of 2!" severity error; + + i1:if L2N<2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SI'range); + signal OV:BOOLEAN_VECTOR(0 to H-1); +--2008 signal OS:UNSIGNED_VECTOR(0 to H-1)(SO'range); + type UNSIGNED_VECTOR is array(NATURAL range <>) of UNSIGNED(SO'range); --93 + signal OS:UNSIGNED_VECTOR(0 to H-1); + begin + sd:entity work.DS generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + lk:for K in 0 to H-1 generate +----2008 signal II,OO:CFIXED_VECTOR(0 to G-1)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal II,OO:CFIXED_VECTOR((I'high+1)/H-1 downto I'low/H); + begin + li:for J in 0 to G-1 generate +--2008 II(J)<=IO(IO'low+K+H*J); + II(I'length/SSR*(J+1)-1+II'low downto I'length/SSR*J+II'low)<=IO(I'length/SSR*(K+H*J+1)-1+I'low downto I'length/SSR*(K+H*J)+I'low); + end generate; + ci:entity work.CB generic map(SSR=>G, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OO, + VO=>OV(K), + SO=>OS(K)); + lo:for J in 0 to G-1 generate +----2008 O(O'low+K*G+J)<=OO(J); + O(O'length/SSR*(K*G+J+1)-1+O'low downto O'length/SSR*(K*G+J)+O'low)<=OO(O'length/SSR*(J+1)-1+OO'low downto O'length/SSR*J+OO'low); + end generate; + end generate; + VO<=OV(OV'low); + SO<=OS(OS'low); +--2008 end; + end generate; +--2008 elsif L2N=2*L2R generate + i2:if L2N=2*L2R generate + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>1) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>O, + VO=>VO, + SO=>SO); +--2008 else generate + end generate; + i3:if L2N>2*L2R generate +--2008 signal IO:CFIXED_VECTOR(I'range)(RE(I(I'low).RE'range),IM(I(I'low).IM'range)); + signal IO:CFIXED_VECTOR(I'range); + signal V:BOOLEAN; + signal S:UNSIGNED(SO'range); + begin + ci:entity work.CB generic map(SSR=>SSR, --93 + PACKING_FACTOR=>N/RADIX/RADIX, + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>IO, + VO=>V, + SO=>S); + + sd:entity work.DS generic map(N=>N/RADIX, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>IO, + VI=>V, + SI=>S, + O=>O, + VO=>VO, + SO=>SO); + end generate; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +----------------------------------------------------------------------------------------------- +-- ? Copyright 2018 Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail catalinb@xilinx.com - this design is not supported by Xilinx +-- Worldwide Technical Support (WTS), for support please contact the author +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx Inc. +-- \ \ \/ Version: 0.14 +-- \ \ Filename: VECTOR_FFT.vhd +-- / / Date Last Modified: 9 Mar 2018 +-- /___/ /\ Date Created: +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: Any UltraScale Xilinx FPGA +-- Author: Catalin Baetoniu +-- Entity Name: VECTOR_FFT +-- Purpose: Arbitrary Size Systolic FFT - any size N, any SSR (powers of 2 only) +-- +-- Revision History: +-- Revision 0.14 2018-Mar-09 Version with workarounds for Vivado Simulator limited VHDL-2008 support +-------------------------------------------------------------------------------- +-- +-- Module Description: Top Level Test Module for SYSTOLIC_FFT +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +use work.COMPLEX_FIXED_PKG.all; + +entity VECTOR_FFT is + generic(SSR:INTEGER:=8;--4; + N:INTEGER:=16384;--8192;--4096;--1024; + I_high:INTEGER:=0; + I_low:INTEGER:=-17; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-17; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; +--2008 I:in CFIXED_VECTOR(0 to RADIX-1)(RE(I_high downto I_low),IM(I_high downto I_low)); + I:in CFIXED_VECTOR(SSR*2*(I_high-I_low+1)-1 downto 0); + VI:in BOOLEAN; + SI:in UNSIGNED(LOG2(N)-1 downto 0); +--2008 O:out CFIXED_VECTOR(0 to RADIX-1)(RE(O_high downto O_low),IM(O_high downto O_low)); + O:out CFIXED_VECTOR(SSR*2*(O_high-O_low+1)-1 downto 0); + VO:out BOOLEAN; + SO:out UNSIGNED(LOG2(N)-1 downto 0)); +end VECTOR_FFT; + +architecture TEST of VECTOR_FFT is + function TO_SFIXED(S:STD_LOGIC_VECTOR;I:SFIXED) return SFIXED is + variable R:SFIXED(I'range); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + + function TO_STD_LOGIC_VECTOR(S:SFIXED) return STD_LOGIC_VECTOR is + variable R:STD_LOGIC_VECTOR(S'length-1 downto 0); + begin + for K in 0 to R'length-1 loop + R(R'low+K):=S(S'low+K); + end loop; + return R; + end; + +--2008 signal II:CFIXED_VECTOR(I'range)(RE(I_high downto I_low),IM(I_high downto I_low)); + signal II:CFIXED_VECTOR(I'range); + signal V,VOFFT,VODS:BOOLEAN; + signal S,SFFT,SODS:UNSIGNED(SI'range); +--2008 signal OFFT,ODS:CFIXED_VECTOR(O'range)(RE(O_high downto O_low),IM(O_high downto O_low)); + signal OFFT,ODS:CFIXED_VECTOR(O'range); +begin + u0:entity work.INPUT_SWAP generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB) + port map(CLK=>CLK, + I=>I, + VI=>VI, + SI=>SI, + O=>II, + VO=>V, + SO=>S); + + u1:entity work.SYSTOLIC_FFT generic map(N=>N, + SSR=>SSR, --93 + W_high=>W_high, + W_low=>W_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + DSP48E=>DSP48E) + port map(CLK=>CLK, + I=>II, + VI=>V, + SI=>S, + O=>OFFT, + VO=>VOFFT, + SO=>SFFT); + + u2:entity work.DSN generic map(N=>N, + SSR=>SSR, --93 + BRAM_THRESHOLD=>BRAM_THRESHOLD) + port map(CLK=>CLK, + I=>OFFT, + VI=>VOFFT, + SI=>SFFT, + O=>O, + VO=>VO, + SO=>SO); +-- O<=OFFT; +-- VO<=VOFFT; +-- SO<=SFFT; +end TEST; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.COMPLEX_FIXED_PKG.all; + +entity WRAPPER_VECTOR_FFT is + generic(SSR:INTEGER:=8; + N:INTEGER:=512; + L2N:INTEGER:=9; -- L2N must be set equal to log2(N)!!! + I_high:INTEGER:=0; + I_low:INTEGER:=-15; + W_high:INTEGER:=1; + W_low:INTEGER:=-17; + O_high:INTEGER:=0; + O_low:INTEGER:=-15; + ROUNDING:BOOLEAN:=TRUE; + BRAM_THRESHOLD:INTEGER:=512; + USE_CB:BOOLEAN:=FALSE; + DSP48E:INTEGER:=2); -- use 1 for DSP48E1 and 2 for DSP48E2 + port(CLK:in STD_LOGIC; + CE:in STD_LOGIC:='1'; -- not used, for SysGen only + I:in STD_LOGIC_VECTOR(2*SSR*(I_high-I_low+1)-1 downto 0); + VI:in STD_LOGIC; + SI:in STD_LOGIC_VECTOR(L2N-1 downto 0):=(L2N-1 downto 0=>'0'); -- can be left unconnected if internal scaling is not used, must be a (LOG2(N)-1 downto 0) port + O:out STD_LOGIC_VECTOR(2*SSR*(O_high-O_low+1)-1 downto 0); + VO:out STD_LOGIC; + SO:out STD_LOGIC_VECTOR(L2N-1 downto 0)); -- can be left unconnected if internal overflow is not possible, must be a (LOG2(N)-1 downto 0) port +end WRAPPER_VECTOR_FFT; + +architecture WRAPPER of WRAPPER_VECTOR_FFT is +-- resize SFIXED and convert to STD_LOGIC_VECTOR + function SFIXED_TO_SLV_RESIZE(I:SFIXED;hi,lo:INTEGER) return STD_LOGIC_VECTOR is + variable O:STD_LOGIC_VECTOR(hi-lo downto 0); + begin + for K in O'range loop + if KSSR, + N=>N, + I_high=>I_high, + I_low=>I_low, + W_high=>W_high, + W_low=>W_low, + O_high=>O_high, + O_low=>O_low, + ROUNDING=>ROUNDING, + BRAM_THRESHOLD=>BRAM_THRESHOLD, + USE_CB=>USE_CB, + DSP48E=>DSP48E) -- 1 for DSP48E1, 2 for DSP48E2 + port map(CLK=>CLK, + I=>II, + VI=>VII, + SI=>SII, + O=>OO, + VO=>VOO, + SO=>SOO); + O<=STD_LOGIC_VECTOR(OO); + VO<='1' when VOO else '0'; + SO<=STD_LOGIC_VECTOR(SOO); +end WRAPPER; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity WRAPPER_VECTOR_FFT_c48f0cd3f27fd6fdac4ed316c161272e is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 8; + N : integer := 256; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(7 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(7 downto 0); + CLK : in std_logic; + CE : in std_logic + ); +end WRAPPER_VECTOR_FFT_c48f0cd3f27fd6fdac4ed316c161272e; +architecture structural of WRAPPER_VECTOR_FFT_c48f0cd3f27fd6fdac4ed316c161272e is + signal I_net : std_logic_vector(255 downto 0); + signal VI_net : std_logic; + signal SI_net : std_logic_vector(7 downto 0); + signal O_net : std_logic_vector(431 downto 0); + signal VO_net : std_logic; + signal SO_net : std_logic_vector(7 downto 0); + signal CLK_net : std_logic; + signal CE_net : std_logic; + component WRAPPER_VECTOR_FFT is + generic ( + BRAM_THRESHOLD : integer := 258; + DSP48E : integer := 2; + I_high : integer := -2; + I_low : integer := -17; + L2N : integer := 8; + N : integer := 256; + O_high : integer := 9; + O_low : integer := -17; + SSR : integer := 8; + W_high : integer := 1; + W_low : integer := -17 + ); + port( + I : in std_logic_vector(255 downto 0); + VI : in std_logic; + SI : in std_logic_vector(7 downto 0); + O : out std_logic_vector(431 downto 0); + VO : out std_logic; + SO : out std_logic_vector(7 downto 0); + CLK : in std_logic; + CE : in std_logic + ); + end component; +begin + I_net <= I; + VI_net <= VI; + SI_net <= SI; + O <= O_net; + VO <= VO_net; + SO <= SO_net; + CLK_net <= CLK; + CE_net <= CE; + WRAPPER_VECTOR_FFT_inst : WRAPPER_VECTOR_FFT + generic map( + BRAM_THRESHOLD => 258, + DSP48E => 2, + I_high => -2, + I_low => -17, + L2N => 8, + N => 256, + O_high => 9, + O_low => -17, + SSR => 8, + W_high => 1, + W_low => -17 + ) + port map( + I => I_net, + VI => VI_net, + SI => SI_net, + O => O_net, + VO => VO_net, + SO => SO_net, + CLK => CLK_net, + CE => CE_net + ); +end structural; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlslice.vhd +-- +-- Description : VHDL description of a block that sets the output to a +-- specified range of the input bits. The output is always +-- set to an unsigned type with it's binary point at zero. +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + + +entity ssr_8x256_xlslice is + generic ( + new_msb : integer := 9; -- position of new msb + new_lsb : integer := 1; -- position of new lsb + x_width : integer := 16; -- Width of x input + y_width : integer := 8); -- Width of y output + port ( + x : in std_logic_vector (x_width-1 downto 0); + y : out std_logic_vector (y_width-1 downto 0)); +end ssr_8x256_xlslice; + +architecture behavior of ssr_8x256_xlslice is +begin + y <= x(new_msb downto new_lsb); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_6128f842cc is + port ( + in0 : in std_logic_vector((16 - 1) downto 0); + in1 : in std_logic_vector((16 - 1) downto 0); + y : out std_logic_vector((32 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_6128f842cc; +architecture behavior of sysgen_concat_6128f842cc +is + signal in0_1_23: unsigned((16 - 1) downto 0); + signal in1_1_27: unsigned((16 - 1) downto 0); + signal y_2_1_concat: unsigned((32 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_3bad6996c0 is + port ( + input_port : in std_logic_vector((16 - 1) downto 0); + output_port : out std_logic_vector((16 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_3bad6996c0; +architecture behavior of sysgen_reinterpret_3bad6996c0 +is + signal input_port_1_40: signed((16 - 1) downto 0); + signal output_port_5_5_force: unsigned((16 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_signed(input_port); + output_port_5_5_force <= signed_to_unsigned(input_port_1_40); + output_port <= unsigned_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_reinterpret_9cd5a6908e is + port ( + input_port : in std_logic_vector((27 - 1) downto 0); + output_port : out std_logic_vector((27 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_reinterpret_9cd5a6908e; +architecture behavior of sysgen_reinterpret_9cd5a6908e +is + signal input_port_1_40: unsigned((27 - 1) downto 0); + signal output_port_5_5_force: signed((27 - 1) downto 0); +begin + input_port_1_40 <= std_logic_vector_to_unsigned(input_port); + output_port_5_5_force <= unsigned_to_signed(input_port_1_40); + output_port <= signed_to_std_logic_vector(output_port_5_5_force); +end behavior; + +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity sysgen_concat_c6ccfb3c89 is + port ( + in0 : in std_logic_vector((32 - 1) downto 0); + in1 : in std_logic_vector((32 - 1) downto 0); + in2 : in std_logic_vector((32 - 1) downto 0); + in3 : in std_logic_vector((32 - 1) downto 0); + in4 : in std_logic_vector((32 - 1) downto 0); + in5 : in std_logic_vector((32 - 1) downto 0); + in6 : in std_logic_vector((32 - 1) downto 0); + in7 : in std_logic_vector((32 - 1) downto 0); + y : out std_logic_vector((256 - 1) downto 0); + clk : in std_logic; + ce : in std_logic; + clr : in std_logic); +end sysgen_concat_c6ccfb3c89; +architecture behavior of sysgen_concat_c6ccfb3c89 +is + signal in0_1_23: unsigned((32 - 1) downto 0); + signal in1_1_27: unsigned((32 - 1) downto 0); + signal in2_1_31: unsigned((32 - 1) downto 0); + signal in3_1_35: unsigned((32 - 1) downto 0); + signal in4_1_39: unsigned((32 - 1) downto 0); + signal in5_1_43: unsigned((32 - 1) downto 0); + signal in6_1_47: unsigned((32 - 1) downto 0); + signal in7_1_51: unsigned((32 - 1) downto 0); + signal y_2_1_concat: unsigned((256 - 1) downto 0); +begin + in0_1_23 <= std_logic_vector_to_unsigned(in0); + in1_1_27 <= std_logic_vector_to_unsigned(in1); + in2_1_31 <= std_logic_vector_to_unsigned(in2); + in3_1_35 <= std_logic_vector_to_unsigned(in3); + in4_1_39 <= std_logic_vector_to_unsigned(in4); + in5_1_43 <= std_logic_vector_to_unsigned(in5); + in6_1_47 <= std_logic_vector_to_unsigned(in6); + in7_1_51 <= std_logic_vector_to_unsigned(in7); + y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39) & unsigned_to_std_logic_vector(in5_1_43) & unsigned_to_std_logic_vector(in6_1_47) & unsigned_to_std_logic_vector(in7_1_51)); + y <= unsigned_to_std_logic_vector(y_2_1_concat); +end behavior; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg.vhd new file mode 100644 index 0000000..770ff70 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg.vhd @@ -0,0 +1,95 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register without +-- an init value and a clear. SRLC32E components are used. The +-- initial value is always 0 +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRLC32s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg; + +architecture structural of synth_reg is + component srlc33e + generic (width : integer:=16; + latency : integer :=8); + port (clk : in std_logic; + ce : in std_logic; + d : in std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); + end component; + + function calc_num_srlc33es (latency : integer) + return integer + is + variable remaining_latency : integer; + variable result : integer; + begin + result := latency / 33; + + remaining_latency := latency - (result * 33); + -- If latency is not an even multiple of 33 then add one more + -- srlc33e to the pipeline + if (remaining_latency /= 0) then + result := result + 1; + end if; + + return result; + end; + + + constant complete_num_srlc33es : integer := latency / 33; + constant num_srlc33es : integer := calc_num_srlc33es(latency); + constant remaining_latency : integer := latency - (complete_num_srlc33es * 33); + -- Array for std_logic_vectors + type register_array is array (num_srlc33es downto 0) of + std_logic_vector(width-1 downto 0); + signal z : register_array; + +begin + + z(0) <= i; + complete_ones : if complete_num_srlc33es > 0 generate + srlc33e_array: for i in 0 to complete_num_srlc33es-1 generate + delay_comp : srlc33e + generic map (width => width, + latency => 33) + port map (clk => clk, + ce => ce, + d => z(i), + q => z(i+1)); + + end generate; + end generate; + + partial_one : if remaining_latency > 0 generate + last_srlc33e : srlc33e + generic map (width => width, + latency => remaining_latency) + port map (clk => clk, + ce => ce, + d => z(num_srlc33es-1), + q => z(num_srlc33es)); + end generate; + o <= z(num_srlc33es); +end structural; + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_reg.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_reg.vhd new file mode 100644 index 0000000..5d837de --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_reg.vhd @@ -0,0 +1,64 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +-- $Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/hdl_pkg/synth_reg.vhd,v 1.2 2005/01/11 00:33:32 stroomer Exp $ +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_reg.vhd +-- +-- Created : 6/28/2013 +-- +-- Description : splitted from synth_reg.vhd +-- +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_reg is + generic (width : integer := 8; + latency : integer := 1); + port (i : in std_logic_vector(width-1 downto 0); + ce : in std_logic; + clr : in std_logic; -- Not used since implemented w/ SRL16s + clk : in std_logic; + o : out std_logic_vector(width-1 downto 0)); +end synth_reg_reg; + +architecture behav of synth_reg_reg is + type reg_array_type is array (latency downto 0) of std_logic_vector(width -1 downto 0); + signal reg_bank : reg_array_type := (others => (others => '0')); + signal reg_bank_in : reg_array_type := (others => (others => '0')); + attribute syn_allow_retiming : boolean; + attribute syn_srlstyle : string; + attribute syn_allow_retiming of reg_bank : signal is true; + attribute syn_allow_retiming of reg_bank_in : signal is true; + attribute syn_srlstyle of reg_bank : signal is "registers"; + attribute syn_srlstyle of reg_bank_in : signal is "registers"; +begin -- behav + + latency_eq_0: if latency = 0 generate + o <= i; + end generate latency_eq_0; + + latency_gt_0: if latency >= 1 generate + o <= reg_bank(latency); + reg_bank(0) <= i; + + sync_loop: for sync_idx in latency downto 1 generate + sync_proc: process (clk) + begin -- process sync_proc + if clk'event and clk = '1' then -- rising clock edge + if clr = '1' then + reg_bank(sync_idx) <= (others => '0'); + elsif ce = '1' then + reg_bank(sync_idx) <= reg_bank(sync_idx-1); + end if; + end if; + end process sync_proc; + end generate sync_loop; + end generate latency_gt_0; + end behav; + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_w_init.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_w_init.vhd new file mode 100644 index 0000000..34bfa2e --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/synth_reg_w_init.vhd @@ -0,0 +1,98 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +---------------------------------------------------------------------------- +-- +-- Filename : synth_reg_w_init.vhd +-- +-- Created : 6/10/2000 +-- +-- Description : Synthesizable VHDL description of parallel register with +-- an initial value. The register has clr and ce pins and +-- is implemented using flip-flops (i.e., not SRL16s). +-- +-- Mod. History : Delayed input .1 ns so that there isn't a setup +-- violation in the fdse or fdre Unisim models. +-- : Changed VHDL so that initial register is passed as a bit +-- vector generic value, instead of the const_pkg. +-- +-- Mod. Dates : 8/10/2001 +-- 3/19/2003 +---------------------------------------------------------------------------- + +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +library IEEE; +use IEEE.std_logic_1164.all; + +entity synth_reg_w_init is + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000"; + latency: integer := 1 + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); +end synth_reg_w_init; + +architecture structural of synth_reg_w_init is + component single_reg_w_init + generic ( + width: integer := 8; + init_index: integer := 0; + init_value: bit_vector := b"0000" + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; -- end single_reg_w_init + + -- 1D array used to connect all the register together + signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); + signal dly_clr: std_logic; +begin + latency_eq_0: if (latency = 0) generate + o <= i; + end generate; -- end latency_eq_0 + + latency_gt_0: if (latency >= 1) generate + -- Delayed input 200 ps so that there isn't a setup violation in the + -- fdse or fdre Unisim models + dly_i((latency + 1) * width - 1 downto latency * width) <= i + after 200 ps; + dly_clr <= clr after 200 ps; + + fd_array: for index in latency downto 1 generate + reg_comp: single_reg_w_init + generic map ( + width => width, + init_index => init_index, + init_value => init_value + ) + port map ( + clk => clk, + i => dly_i((index + 1) * width - 1 downto index * width), + o => dly_i(index * width - 1 downto (index - 1) * width), + ce => ce, + clr => dly_clr + ); + end generate; -- end fd_array + + o <= dly_i(width - 1 downto 0); + end generate; -- end latency_gt_0 +end structural; + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd new file mode 100644 index 0000000..92017d4 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssr_fft_8x256/xlclockdriver_rd.vhd @@ -0,0 +1,338 @@ +library xil_defaultlib; +use xil_defaultlib.conv_pkg.all; + +--------------------------------------------------------------------- +-- +-- Filename : xlclockdriver.vhd +-- +-- Date : 10/1/99 +-- +-- Description : VHDL description of a clock enable generator block. +-- This code is synthesizable. +-- +-- Assumptions : period >= 1 +-- +-- Mod. History : Removed one shot & OR gate +-- If period is power of 2 a 1-bit smaller counter +-- is used and no sync clear +-- : Logic needed for use_bufg generic added +-- : Initial ce output is now 0 instead of 1 +-- Enable pulse now occurs at the end of the sample +-- period, instead of at the start +-- : Added pipeline registers +-- : added OR gate for sysclr to work properly +-- +-- Mod. Dates : 7/26/2001 +-- : 8/05/2001 +-- : 1/02/2002 +-- : 11/30/2004 +-- : 4/11/2005 +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +-- synthesis translate_off +library unisim; +use unisim.vcomponents.all; +-- synthesis translate_on + +entity xlclockdriver is + generic ( + period: integer := 2; + log_2_period: integer := 0; + pipeline_regs: integer := 5; + use_bufg: integer := 0 + ); + port ( + sysclk: in std_logic; + sysclr: in std_logic; + sysce: in std_logic; + clk: out std_logic; + clr: out std_logic; + ce: out std_logic; + ce_logic: out std_logic + ); +end xlclockdriver; + +architecture behavior of xlclockdriver is + component bufg + port ( + i: in std_logic; + o: out std_logic + ); + end component; + + component synth_reg_w_init + generic ( + width: integer; + init_index: integer; + init_value: bit_vector; + latency: integer + ); + port ( + i: in std_logic_vector(width - 1 downto 0); + ce: in std_logic; + clr: in std_logic; + clk: in std_logic; + o: out std_logic_vector(width - 1 downto 0) + ); + end component; + + -- Returns the size of an unsigned integer + -- if power_of_2 is true return value is one less + function size_of_uint(inp: integer; power_of_2: boolean) + return integer + is + constant inp_vec: std_logic_vector(31 downto 0) := + integer_to_std_logic_vector(inp,32, xlUnsigned); + variable result: integer; + begin + result := 32; + for i in 0 to 31 loop + if inp_vec(i) = '1' then + result := i; + end if; + end loop; + if power_of_2 then + return result; + else + return result+1; + end if; + end; + + -- Returns boolean which says if 'inp' is a power of two + function is_power_of_2(inp: std_logic_vector) + return boolean + is + constant width: integer := inp'length; + variable vec: std_logic_vector(width - 1 downto 0); + variable single_bit_set: boolean; + variable more_than_one_bit_set: boolean; + variable result: boolean; + begin + vec := inp; + single_bit_set := false; + more_than_one_bit_set := false; + + -- synthesis translate_off + if (is_XorU(vec)) then + return false; + end if; + -- synthesis translate_on + if width > 0 then + for i in 0 to width - 1 loop + if vec(i) = '1' then + if single_bit_set then + more_than_one_bit_set := true; + end if; + single_bit_set := true; + end if; + end loop; + end if; + if (single_bit_set and not(more_than_one_bit_set)) then + result := true; + else + result := false; + end if; + return result; + end; + + -- Returns initial value for pipeline registers + function ce_reg_init_val(index, period : integer) + return integer + is + variable result: integer; + begin + result := 0; + if ((index mod period) = 0) then + result := 1; + end if; + return result; + end; + + -- Returns the remainder(num_pipeline_regs/period) + 1 + function remaining_pipe_regs(num_pipeline_regs, period : integer) + return integer + is + variable factor, result: integer; + begin + factor := (num_pipeline_regs / period); + result := num_pipeline_regs - (period * factor) + 1; + return result; + end; + + -- Calculate the min + function sg_min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + constant max_pipeline_regs : integer := 8; + constant pipe_regs : integer := 5; + + -- Check if requested pipeline regs are greater than the max amount + constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); + constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); + + constant period_floor: integer := max(2, period); + constant power_of_2_counter: boolean := + is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); + constant cnt_width: integer := + size_of_uint(period_floor, power_of_2_counter); + constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); + constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := + integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); + + signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); + signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); + signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0); + signal internal_ce: std_logic_vector(0 downto 0); + signal internal_ce_logic: std_logic_vector(0 downto 0); + signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); +begin + -- Pass through the system clock and clear + clk <= sysclk; + clr <= sysclr; + + -- Clock Number Counter + cntr_gen: process(sysclk) + begin + if sysclk'event and sysclk = '1' then + if (sysce = '1') then + if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then + clk_num <= (others => '0'); + else + clk_num <= clk_num + 1; + end if; + end if; + end if; + end process; + + -- Clear logic for counter + clr_gen: process(clk_num, sysclr) + begin + if power_of_2_counter then + cnt_clr(0) <= sysclr; + else + -- Counter does not reset when clk_num = a power of 2 + if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 + or sysclr = '1') then + cnt_clr(0) <= '1'; + else + cnt_clr(0) <= '0'; + end if; + end if; + end process; + + clr_reg: synth_reg_w_init + generic map ( + width => 1, + init_index => 0, + init_value => b"0000", + latency => 1 + ) + port map ( + i => cnt_clr, + ce => sysce, + clr => sysclr, + clk => sysclk, + o => cnt_clr_dly + ); + + -- Clock enable generation + pipelined_ce : if period > 1 generate + ce_gen: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec(num_pipeline_regs) <= '1'; + else + ce_vec(num_pipeline_regs) <= '0'; + end if; + end process; + ce_pipeline: for index in num_pipeline_regs downto 1 generate + ce_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec(index-1 downto index-1) + ); + end generate; -- i + internal_ce <= ce_vec(0 downto 0); + end generate; + + -- Clock enable generation + pipelined_ce_logic: if period > 1 generate + ce_gen_logic: process(clk_num) + begin + if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then + ce_vec_logic(num_pipeline_regs) <= '1'; + else + ce_vec_logic(num_pipeline_regs) <= '0'; + end if; + end process; + ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate + ce_logic_reg : synth_reg_w_init + generic map ( + width => 1, + init_index => ce_reg_init_val(index, period), + init_value => b"0000", -- not used + latency => 1 + ) + port map ( + i => ce_vec_logic(index downto index), + ce => sysce, + clr => sysclr, + clk => sysclk, + o => ce_vec_logic(index-1 downto index-1) + ); + end generate; -- i + internal_ce_logic <= ce_vec_logic(0 downto 0); + end generate; + + + use_bufg_true: if period > 1 and use_bufg = 1 generate + -- Clock enable with bufg + ce_bufg_inst: bufg + port map ( + i => internal_ce(0), + o => ce + ); + ce_bufg_inst_logic: bufg + port map ( + i => internal_ce_logic(0), + o => ce_logic + ); + end generate; + + use_bufg_false: if period > 1 and (use_bufg = 0) generate + -- Clock enable without bufg + ce <= internal_ce(0) and sysce; + ce_logic <= internal_ce_logic(0) and sysce; + end generate; + + generate_system_clk: if period = 1 generate + ce <= sysce; + ce_logic <= sysce; + end generate; +end architecture behavior; + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssrfft_8x256_sync.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssrfft_8x256_sync.vhd new file mode 100644 index 0000000..30f2d1e --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/ssrfft_8x256_sync.vhd @@ -0,0 +1,294 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity ssrfft_8x256_sync is + Generic + ( + NFFT : Integer := 16; + SSR : Integer := 4; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (2*SSR*B-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end entity; + +architecture rtl of ssrfft_8x256_sync is + +-- Framing. +component framing is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4; + + -- Bits. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- Synced outputs. + tdata : out std_logic_vector (2*SSR*B-1 downto 0); + tvalid : out std_logic + ); +end component; + +-- TLAST Generator. +component tlast_gen is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4 + ); + Port + ( + -- Input reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Input enable. + en : in std_logic; + + -- TLAST input/output. + o_tlast : out std_logic + ); +end component; + +-- SSR FFT 8x256. +component ssr_8x256 is + port ( + -- Clock signal. + clk : in std_logic; + + -- Input data. + i_re_0 : in std_logic_vector( 16-1 downto 0 ); + i_re_1 : in std_logic_vector( 16-1 downto 0 ); + i_re_2 : in std_logic_vector( 16-1 downto 0 ); + i_re_3 : in std_logic_vector( 16-1 downto 0 ); + i_re_4 : in std_logic_vector( 16-1 downto 0 ); + i_re_5 : in std_logic_vector( 16-1 downto 0 ); + i_re_6 : in std_logic_vector( 16-1 downto 0 ); + i_re_7 : in std_logic_vector( 16-1 downto 0 ); + i_im_0 : in std_logic_vector( 16-1 downto 0 ); + i_im_1 : in std_logic_vector( 16-1 downto 0 ); + i_im_2 : in std_logic_vector( 16-1 downto 0 ); + i_im_3 : in std_logic_vector( 16-1 downto 0 ); + i_im_4 : in std_logic_vector( 16-1 downto 0 ); + i_im_5 : in std_logic_vector( 16-1 downto 0 ); + i_im_6 : in std_logic_vector( 16-1 downto 0 ); + i_im_7 : in std_logic_vector( 16-1 downto 0 ); + i_valid : in std_logic_vector( 1-1 downto 0 ); + i_scale : in std_logic_vector( 8-1 downto 0 ); + + -- Output data. + o_re_0 : out std_logic_vector( 27-1 downto 0 ); + o_re_1 : out std_logic_vector( 27-1 downto 0 ); + o_re_2 : out std_logic_vector( 27-1 downto 0 ); + o_re_3 : out std_logic_vector( 27-1 downto 0 ); + o_re_4 : out std_logic_vector( 27-1 downto 0 ); + o_re_5 : out std_logic_vector( 27-1 downto 0 ); + o_re_6 : out std_logic_vector( 27-1 downto 0 ); + o_re_7 : out std_logic_vector( 27-1 downto 0 ); + o_im_0 : out std_logic_vector( 27-1 downto 0 ); + o_im_1 : out std_logic_vector( 27-1 downto 0 ); + o_im_2 : out std_logic_vector( 27-1 downto 0 ); + o_im_3 : out std_logic_vector( 27-1 downto 0 ); + o_im_4 : out std_logic_vector( 27-1 downto 0 ); + o_im_5 : out std_logic_vector( 27-1 downto 0 ); + o_im_6 : out std_logic_vector( 27-1 downto 0 ); + o_im_7 : out std_logic_vector( 27-1 downto 0 ); + o_valid : out std_logic_vector( 1-1 downto 0 ); + o_scale : out std_logic_vector( 8-1 downto 0 ) + ); +end component; + +-- Vectors with individual I,Q samples. +type data_v is array (SSR-1 downto 0) of std_logic_vector (B-1 downto 0); +signal din_iv : data_v; +signal din_qv : data_v; +signal dout_iv : data_v; +signal dout_qv : data_v; + +-- Vector with individual I,Q samples (fft out full precision). +type data_vf is array (SSR-1 downto 0) of std_logic_vector (27-1 downto 0); +signal dout_ivf : data_vf; +signal dout_qvf : data_vf; + +-- I,Q parts of input. +signal din_i : std_logic_vector (SSR*B-1 downto 0); +signal din_q : std_logic_vector (SSR*B-1 downto 0); + +-- Framing block signals. +signal framing_tdata : std_logic_vector (2*SSR*B-1 downto 0); +signal framing_tvalid : std_logic; + +-- FFT scale. +signal o_scale : std_logic_vector (7 downto 0); + +-- FFT output valid/last. +signal o_axis_tvalid : std_logic; +signal o_axis_tlast : std_logic; + +-- FFT data output. +signal o_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); + +-- Registers. +signal scale_reg_i : std_logic_vector (7 downto 0); +signal qout_reg_i : unsigned (3 downto 0); + +begin + +-- Registers. +scale_reg_i <= SCALE_REG (7 downto 0); + +-- Full-precision output: 27 bits. Required output: 16 bits. +-- Quantization selection from 0 to 11. +qout_reg_i <= (others => '0') when ( unsigned(QOUT_REG) > to_unsigned(11,QOUT_REG'length) ) else + unsigned(QOUT_REG(3 downto 0)); + +-- Input/output data to vector. +GEN: for I in 0 to SSR-1 generate + -- Input data to vector. + din_iv(I) <= framing_tdata(I*2*B+B-1 downto I*2*B ); + din_qv(I) <= framing_tdata(I*2*B+2*B-1 downto I*2*B+B ); + + -- Quantization selection. + dout_iv(I) <= dout_ivf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + dout_qv(I) <= dout_qvf(I)(to_integer(qout_reg_i)+B-1 downto to_integer(qout_reg_i)); + + -- Output data to vector. + o_axis_tdata(I*2*B+B-1 downto I*2*B ) <= dout_iv(I); + o_axis_tdata(I*2*B+2*B-1 downto I*2*B+B ) <= dout_qv(I); +end generate GEN; + +-- Framing. +framing_i : framing + Generic map + ( + -- SSR and FFT Length. + NFFT => NFFT , + SSR => SSR , + + -- Bits. + B => B + ) + Port map + ( + -- Reset and clock. + aresetn => aresetn , + aclk => aclk , + + -- AXIS Slave. + s_axis_tdata => s_axis_tdata , + s_axis_tlast => s_axis_tlast , + s_axis_tvalid => s_axis_tvalid , + + -- Synced outputs. + tdata => framing_tdata , + tvalid => framing_tvalid + ); + +-- TLAST Generator. +tlast_gen_i : tlast_gen + Generic map + ( + -- SSR and FFT Length. + NFFT => NFFT , + SSR => SSR + ) + Port map + ( + -- Input reset and clock. + rstn => aresetn , + clk => aclk , + + -- Input enable. + en => o_axis_tvalid , + + -- TLAST input/output. + o_tlast => o_axis_tlast + ); + +-- SSR FFT 8x256. +ssr_8x256_i : ssr_8x256 + port map ( + -- Clock signal. + clk => aclk , + + -- Input data. + i_re_0 => din_iv(0) , + i_re_1 => din_iv(1) , + i_re_2 => din_iv(2) , + i_re_3 => din_iv(3) , + i_re_4 => din_iv(4) , + i_re_5 => din_iv(5) , + i_re_6 => din_iv(6) , + i_re_7 => din_iv(7) , + i_im_0 => din_qv(0) , + i_im_1 => din_qv(1) , + i_im_2 => din_qv(2) , + i_im_3 => din_qv(3) , + i_im_4 => din_qv(4) , + i_im_5 => din_qv(5) , + i_im_6 => din_qv(6) , + i_im_7 => din_qv(7) , + i_valid(0) => framing_tvalid , + i_scale => scale_reg_i , + + -- Output data. + o_re_0 => dout_ivf(0) , + o_re_1 => dout_ivf(1) , + o_re_2 => dout_ivf(2) , + o_re_3 => dout_ivf(3) , + o_re_4 => dout_ivf(4) , + o_re_5 => dout_ivf(5) , + o_re_6 => dout_ivf(6) , + o_re_7 => dout_ivf(7) , + o_im_0 => dout_qvf(0) , + o_im_1 => dout_qvf(1) , + o_im_2 => dout_qvf(2) , + o_im_3 => dout_qvf(3) , + o_im_4 => dout_qvf(4) , + o_im_5 => dout_qvf(5) , + o_im_6 => dout_qvf(6) , + o_im_7 => dout_qvf(7) , + o_valid(0) => o_axis_tvalid , + o_scale => o_scale + ); + +-- Assign outputs. +m_axis_tdata <= o_axis_tdata; +m_axis_tlast <= o_axis_tlast; +m_axis_tvalid <= o_axis_tvalid; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/tb.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/tb.vhd new file mode 100644 index 0000000..ef0ef03 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/tb.vhd @@ -0,0 +1,251 @@ +-- %%%%%%%%%%%%%%%%%%% Test Description %%%%%%%%%%%%%%%%%%%%% +-- +-- This test is for understanding if moving tvalid makes the +-- block to generate incorrect tlast at the output. +-- +-- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_TEXTIO.ALL; +use STD.TEXTIO.ALL; + +entity tb is +end tb; + +architecture rtl of tb is + +-- DUT. +component ssrfft_8x32_sync is + Generic + ( + NFFT : Integer := 16; + SSR : Integer := 4; + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + aresetn : in std_logic; + aclk : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (2*SSR*B-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXIS Master. + m_axis_tdata : out std_logic_vector (2*SSR*B-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + + -- Registers. + SCALE_REG : in std_logic_vector (31 downto 0); + QOUT_REG : in std_logic_vector (31 downto 0) + ); +end component; + +constant NFFT : Integer := 32; +constant SSR : Integer := 8; +constant B : Integer := 16; + +signal aresetn : std_logic; +signal aclk : std_logic; +signal s_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0) := (others => '0'); +signal s_axis_tlast : std_logic := '0'; +signal s_axis_tvalid : std_logic := '0'; + +signal m_axis_tdata : std_logic_vector (2*SSR*B-1 downto 0); +signal m_axis_tlast : std_logic; +signal m_axis_tvalid : std_logic; + +signal SCALE_REG : std_logic_vector (31 downto 0) := (others => '0'); +signal QOUT_REG : std_logic_vector (31 downto 0) := std_logic_vector(to_unsigned(0,32)); + +-- TB control. +signal rd_start : std_logic := '0'; + +signal i_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal i_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); + +signal o_re_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_re_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_0 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_1 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_2 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_3 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_4 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_5 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_6 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); +signal o_im_7 : std_logic_vector( 16-1 downto 0 ) := (others => '0'); + +begin + +-- DUT. +DUT : ssrfft_8x32_sync + Generic map + ( + NFFT => NFFT , + SSR => SSR , + B => B + ) + Port map + ( + -- Reset and clock. + aresetn => aresetn , + aclk => aclk , + + -- AXIS Slave. + s_axis_tdata => s_axis_tdata , + s_axis_tlast => s_axis_tlast , + s_axis_tvalid => s_axis_tvalid , + + -- AXIS Master. + m_axis_tdata => m_axis_tdata , + m_axis_tlast => m_axis_tlast , + m_axis_tvalid => m_axis_tvalid , + + -- Registers. + SCALE_REG => SCALE_REG , + QOUT_REG => QOUT_REG + ); + +-- Input data. +s_axis_tdata <= i_im_7 & i_im_6 & i_im_5 & i_im_4 & i_im_3 & i_im_2 & i_im_1 & i_im_0 & i_re_7 & i_re_6 & i_re_5 & i_re_4 & i_re_3 & i_re_2 & i_re_1 & i_re_0; + +-- Output data. +o_re_0 <= m_axis_tdata (1*B-1 downto 0*B); +o_re_1 <= m_axis_tdata (2*B-1 downto 1*B); +o_re_2 <= m_axis_tdata (3*B-1 downto 2*B); +o_re_3 <= m_axis_tdata (4*B-1 downto 3*B); +o_re_4 <= m_axis_tdata (5*B-1 downto 4*B); +o_re_5 <= m_axis_tdata (6*B-1 downto 5*B); +o_re_6 <= m_axis_tdata (7*B-1 downto 6*B); +o_re_7 <= m_axis_tdata (8*B-1 downto 7*B); +o_im_0 <= m_axis_tdata (9*B-1 downto 8*B); +o_im_1 <= m_axis_tdata (10*B-1 downto 9*B); +o_im_2 <= m_axis_tdata (11*B-1 downto 10*B); +o_im_3 <= m_axis_tdata (12*B-1 downto 11*B); +o_im_4 <= m_axis_tdata (13*B-1 downto 12*B); +o_im_5 <= m_axis_tdata (14*B-1 downto 13*B); +o_im_6 <= m_axis_tdata (15*B-1 downto 14*B); +o_im_7 <= m_axis_tdata (16*B-1 downto 15*B); + +-- Main TB. +process +begin + aresetn <= '0'; + wait for 250 ns; + aresetn <= '1'; + + wait for 3 us; + + rd_start <= '1'; + wait for 110 ns; + rd_start <= '0'; + wait for 220 ns; + rd_start <= '1'; + wait for 490 ns; + rd_start <= '0'; + wait for 100 ns; + rd_start <= '1'; + + wait for 20 us; + +end process; + +-- Data process. +process + variable I : Integer := 0; + + begin + + for K in 0 to 200 loop + for J in 0 to 2 loop + while rd_start = '0' loop + wait until rising_edge(aclk); + s_axis_tvalid <= '0'; + end loop; + wait until rising_edge(aclk); + s_axis_tlast <= '0'; + s_axis_tvalid <= '1'; + i_re_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + + I := I + 1; + end loop; + + while rd_start = '0' loop + wait until rising_edge(aclk); + s_axis_tvalid <= '0'; + end loop; + wait until rising_edge(aclk); + s_axis_tlast <= '1'; + s_axis_tvalid <= '1'; + i_re_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_re_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_0 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_1 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_2 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_3 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_4 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_5 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_6 <= std_logic_vector(to_signed(I,i_re_0'length)); + i_im_7 <= std_logic_vector(to_signed(I,i_re_0'length)); + + I := I + 1; + end loop; + +end process; + +-- Clock. +process +begin + aclk <= '0'; + wait for 5 ns; + aclk <= '1'; + wait for 5 ns; +end process; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/tlast_gen.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/tlast_gen.vhd new file mode 100644 index 0000000..c07cb2e --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fft/tlast_gen.vhd @@ -0,0 +1,61 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity tlast_gen is + Generic + ( + -- SSR and FFT Length. + NFFT : Integer := 16; + SSR : Integer := 4 + ); + Port + ( + -- Input reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Input enable. + en : in std_logic; + + -- TLAST input/output. + o_tlast : out std_logic + ); +end entity; + +architecture rtl of tlast_gen is + +-- Number of transactions. +constant NTRAN : Integer := NFFT/SSR; +constant NTRAN_LOG2 : Integer := Integer(ceil(log2(real(NTRAN)))); + +-- Counter for transactions. +signal cnt : unsigned (NTRAN_LOG2-1 downto 0); + +begin + +-- Registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + cnt <= (others => '0'); + else + if ( en = '1' ) then + if ( cnt < to_unsigned(NTRAN-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + end if; + end if; + end if; + end if; +end process; + +-- Assign outputs. +o_tlast <= '1' when cnt = to_unsigned(NTRAN-1,cnt'length) else + '0'; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/bin2gray.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/bin2gray.vhd new file mode 100644 index 0000000..4ecc09b --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/bin2gray.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end bin2gray; + +architecture rtl of bin2gray is + +signal gray : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +gray(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + gray(I) <= din(I+1) xor din(I); +end generate; + +-- Assign output. +dout <= gray; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/bram_dp.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/bram_dp.vhd new file mode 100644 index 0000000..d57aad1 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/bram_dp.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture rtl of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/bram_simple_dp.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/bram_simple_dp.vhd new file mode 100644 index 0000000..1494332 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/bram_simple_dp.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_simple_dp; + +architecture rtl of bram_simple_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo.vhd new file mode 100644 index 0000000..957362b --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture rtl of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Dual port, single clock BRAM. +component bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- FIFO memory. +mem_i : bram_simple_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo_axi.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo_dc.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/gray2bin.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/rd2axi.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/Makefile b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/Makefile new file mode 100644 index 0000000..df6451c --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/Makefile @@ -0,0 +1,21 @@ +all: ipgen copy sedxci clean_proj + +ipgen: fir.tcl + vivado -mode batch -source tcl/ipgen.tcl + +copy: + cp -r `find ./ipgen/ipgen.srcs -type d -name "fir*"` . + cp -r `find ./ipgen/ipgen.gen -name "fir_0.veo"` . + +sedxci: + sed -i -r 's#(../)+(coef/fir.*.coe)#../\2#' `find . -name "fir*.xci"` + +fir.tcl: tcl/fir.tcl.template + ./gen.pl tcl/fir.tcl.template + +clean: clean_proj + rm -rf `find . -type d -name "fir*"` + rm -rf fir*.veo fir.tcl add.tcl + +clean_proj: + rm -rf ipgen vivado* diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/add.tcl b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/add.tcl new file mode 100644 index 0000000..9523c5d --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/add.tcl @@ -0,0 +1,8 @@ +add_files ./fir/fir_0/fir_0.xci +add_files ./fir/fir_1/fir_1.xci +add_files ./fir/fir_2/fir_2.xci +add_files ./fir/fir_3/fir_3.xci +add_files ./fir/fir_4/fir_4.xci +add_files ./fir/fir_5/fir_5.xci +add_files ./fir/fir_6/fir_6.xci +add_files ./fir/fir_7/fir_7.xci diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_0.coe b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_0.coe new file mode 100644 index 0000000..63207d0 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_0.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = 0,-293,-611,-893,31761,-893,-611,-293,-28,-331,-750,-1340,31712,-455,-471,-254,-30,-367,-886,-1793,31565,-31,-332,-215,-31,-401,-1019,-2247,31322,378,-195,-175,-32,-433,-1147,-2699,30983,768,-60,-135,-32,-463,-1269,-3145,30551,1136,70,-95,-32,-489,-1383,-3580,30028,1481,196,-56,-31,-511,-1488,-4000,29417,1798,316,-18,-29,-530,-1582,-4401,28722,2088,428,19,-27,-544,-1665,-4778,27945,2349,533,54,-24,-554,-1735,-5126,27093,2578,630,87,-20,-559,-1792,-5442,26168,2776,717,119,-15,-560,-1833,-5721,25178,2941,795,148,-10,-554,-1859,-5958,24126,3074,863,174,-3,-544,-1868,-6151,23020,3175,922,199,4,-528,-1861,-6294,21864,3243,969,221,13,-506,-1835,-6385,20666,3279,1007,240,22,-479,-1791,-6420,19431,3284,1034,256,32,-446,-1729,-6396,18166,3260,1050,270,43,-407,-1649,-6310,16878,3206,1057,281,55,-364,-1551,-6160,15574,3125,1054,290,67,-315,-1434,-5944,14261,3019,1041,296,81,-261,-1301,-5659,12944,2889,1020,300,95,-203,-1150,-5306,11631,2738,990,301,109,-140,-984,-4882,10328,2566,952,300,124,-74,-802,-4388,9042,2378,907,297,139,-4,-607,-3824,7778,2174,856,292,155,68,-400,-3190,6543,1957,798,285,170,143,-181,-2486,5342,1730,736,276,186,219,46,-1716,4180,1495,669,267,201,296,281,-880,3062,1254,599,255,215,373,521,19,1993,1010,525,242 \ No newline at end of file diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_1.coe b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_1.coe new file mode 100644 index 0000000..e24661a --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_1.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = 230,450,765,978,978,765,450,230,242,525,1010,1993,19,521,373,215,255,599,1254,3062,-880,281,296,201,267,669,1495,4180,-1716,46,219,186,276,736,1730,5342,-2486,-181,143,170,285,798,1957,6543,-3190,-400,68,155,292,856,2174,7778,-3824,-607,-4,139,297,907,2378,9042,-4388,-802,-74,124,300,952,2566,10328,-4882,-984,-140,109,301,990,2738,11631,-5306,-1150,-203,95,300,1020,2889,12944,-5659,-1301,-261,81,296,1041,3019,14261,-5944,-1434,-315,67,290,1054,3125,15574,-6160,-1551,-364,55,281,1057,3206,16878,-6310,-1649,-407,43,270,1050,3260,18166,-6396,-1729,-446,32,256,1034,3284,19431,-6420,-1791,-479,22,240,1007,3279,20666,-6385,-1835,-506,13,221,969,3243,21864,-6294,-1861,-528,4,199,922,3175,23020,-6151,-1868,-544,-3,174,863,3074,24126,-5958,-1859,-554,-10,148,795,2941,25178,-5721,-1833,-560,-15,119,717,2776,26168,-5442,-1792,-559,-20,87,630,2578,27093,-5126,-1735,-554,-24,54,533,2349,27945,-4778,-1665,-544,-27,19,428,2088,28722,-4401,-1582,-530,-29,-18,316,1798,29417,-4000,-1488,-511,-31,-56,196,1481,30028,-3580,-1383,-489,-32,-95,70,1136,30551,-3145,-1269,-463,-32,-135,-60,768,30983,-2699,-1147,-433,-32,-175,-195,378,31322,-2247,-1019,-401,-31,-215,-332,-31,31565,-1793,-886,-367,-30,-254,-471,-455,31712,-1340,-750,-331,-28 \ No newline at end of file diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_2.coe b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_2.coe new file mode 100644 index 0000000..ab437e3 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_2.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -688,-303,-646,-1004,31758,-783,-576,-284,-28,-340,-784,-1453,31684,-348,-437,-244,-30,-376,-920,-1906,31514,73,-298,-205,-31,-410,-1052,-2360,31246,478,-161,-165,-32,-441,-1178,-2811,30884,862,-27,-125,-32,-469,-1298,-3255,30429,1225,102,-85,-32,-495,-1410,-3687,29884,1563,226,-46,-31,-516,-1512,-4102,29251,1874,344,-9,-29,-534,-1604,-4497,28535,2156,455,28,-26,-547,-1684,-4867,27739,2409,558,62,-23,-556,-1751,-5208,26868,2631,652,95,-19,-560,-1804,-5515,25927,2820,738,126,-14,-559,-1841,-5784,24920,2978,813,155,-8,-552,-1863,-6011,23855,3103,879,181,-1,-540,-1868,-6191,22735,3195,934,205,6,-523,-1856,-6322,21568,3255,980,226,15,-500,-1826,-6399,20360,3283,1014,244,24,-471,-1777,-6420,19117,3281,1039,260,35,-437,-1711,-6380,17846,3249,1053,273,46,-397,-1626,-6279,16554,3188,1057,284,58,-352,-1523,-6112,15247,3101,1052,292,71,-302,-1402,-5879,13931,2989,1037,297,84,-247,-1264,-5578,12615,2853,1013,300,98,-187,-1110,-5207,11304,2697,981,301,113,-124,-940,-4765,10005,2521,942,299,128,-56,-755,-4254,8724,2328,895,296,143,14,-556,-3672,7466,2121,842,290,159,87,-346,-3020,6239,1901,783,283,174,162,-125,-2300,5047,1672,720,274,189,238,104,-1513,3896,1435,652,264,204,315,341,-661,2790,1193,581,252,219,393,582,253,1734,949,507,239 \ No newline at end of file diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_3.coe b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_3.coe new file mode 100644 index 0000000..58e8704 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_3.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = 233,469,826,1226,732,704,431,226,245,544,1071,2256,-212,461,354,212,258,616,1315,3337,-1095,222,277,197,269,686,1554,4466,-1915,-12,200,182,279,752,1788,5638,-2669,-237,124,166,287,813,2012,6849,-3355,-453,50,151,293,869,2226,8092,-3971,-657,-22,136,298,919,2426,9362,-4518,-849,-91,120,301,963,2611,10653,-4995,-1027,-156,106,301,998,2778,11959,-5401,-1189,-218,91,299,1026,2924,13273,-5737,-1336,-275,77,295,1045,3048,14590,-6004,-1465,-327,64,288,1056,3148,15901,-6204,-1577,-375,52,279,1056,3222,17202,-6338,-1671,-418,40,267,1047,3268,18485,-6408,-1747,-455,29,253,1028,3286,19742,-6417,-1804,-486,19,235,998,3273,20969,-6368,-1843,-512,10,215,958,3229,22157,-6263,-1864,-532,2,193,908,3153,23301,-6107,-1868,-547,-5,168,847,3044,24395,-5903,-1854,-556,-11,141,777,2903,25431,-5655,-1824,-560,-17,111,696,2729,26406,-5366,-1779,-559,-21,79,606,2524,27313,-5042,-1719,-552,-25,45,508,2286,28147,-4686,-1645,-541,-28,10,401,2019,28903,-4303,-1559,-526,-30,-27,286,1722,29578,-3897,-1462,-506,-31,-66,165,1397,30167,-3473,-1355,-482,-32,-105,38,1047,30668,-3034,-1239,-456,-32,-145,-94,673,31077,-2587,-1116,-426,-31,-185,-229,278,31392,-2133,-986,-393,-31,-225,-367,-135,31611,-1679,-852,-358,-29,-264,-506,-564,31733,-1228,-715,-322,-27 \ No newline at end of file diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_4.coe b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_4.coe new file mode 100644 index 0000000..915b71e --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_4.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -27,-312,-681,-1116,31749,-673,-541,-274,-29,-349,-818,-1566,31651,-241,-402,-235,-30,-384,-953,-2020,31456,176,-263,-195,-31,-418,-1084,-2474,31165,576,-127,-155,-32,-448,-1209,-2923,30779,955,6,-115,-32,-476,-1327,-3364,30301,1312,134,-75,-31,-500,-1436,-3792,29734,1643,257,-37,-30,-521,-1536,-4203,29080,1947,373,1,-28,-538,-1625,-4592,28343,2222,482,37,-26,-550,-1702,-4956,27528,2467,582,71,-22,-557,-1765,-5288,26639,2681,675,103,-18,-560,-1814,-5586,25681,2863,757,133,-13,-558,-1848,-5845,24659,3012,831,161,-7,-550,-1866,-6060,23580,3129,894,187,0,-537,-1867,-6229,22448,3213,947,210,8,-518,-1850,-6346,21270,3265,989,231,17,-493,-1815,-6410,20052,3285,1021,248,27,-463,-1763,-6416,18802,3276,1043,264,37,-427,-1691,-6361,17525,3236,1055,276,49,-386,-1602,-6243,16228,3169,1057,286,61,-340,-1495,-6060,14918,3075,1049,293,74,-288,-1370,-5810,13602,2957,1032,298,88,-232,-1227,-5491,12287,2816,1006,301,102,-172,-1069,-5103,10978,2654,972,301,117,-107,-895,-4644,9683,2474,931,299,132,-39,-706,-4115,8407,2278,882,295,147,32,-505,-3515,7157,2067,828,289,163,105,-292,-2847,5938,1845,768,281,178,181,-69,-2110,4755,1613,703,272,193,258,163,-1306,3615,1375,634,261,208,335,401,-438,2521,1132,562,250,223,412,643,491,1479,888,488,236 \ No newline at end of file diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_5.coe b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_5.coe new file mode 100644 index 0000000..dca0ad4 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_5.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = 236,488,888,1479,491,643,412,223,250,562,1132,2521,-438,401,335,208,261,634,1375,3615,-1306,163,258,193,272,703,1613,4755,-2110,-69,181,178,281,768,1845,5938,-2847,-292,105,163,289,828,2067,7157,-3515,-505,32,147,295,882,2278,8407,-4115,-706,-39,132,299,931,2474,9683,-4644,-895,-107,117,301,972,2654,10978,-5103,-1069,-172,102,301,1006,2816,12287,-5491,-1227,-232,88,298,1032,2957,13602,-5810,-1370,-288,74,293,1049,3075,14918,-6060,-1495,-340,61,286,1057,3169,16228,-6243,-1602,-386,49,276,1055,3236,17525,-6361,-1691,-427,37,264,1043,3276,18802,-6416,-1763,-463,27,248,1021,3285,20052,-6410,-1815,-493,17,231,989,3265,21270,-6346,-1850,-518,8,210,947,3213,22448,-6229,-1867,-537,0,187,894,3129,23580,-6060,-1866,-550,-7,161,831,3012,24659,-5845,-1848,-558,-13,133,757,2863,25681,-5586,-1814,-560,-18,103,675,2681,26639,-5288,-1765,-557,-22,71,582,2467,27528,-4956,-1702,-550,-26,37,482,2222,28343,-4592,-1625,-538,-28,1,373,1947,29080,-4203,-1536,-521,-30,-37,257,1643,29734,-3792,-1436,-500,-31,-75,134,1312,30301,-3364,-1327,-476,-32,-115,6,955,30779,-2923,-1209,-448,-32,-155,-127,576,31165,-2474,-1084,-418,-31,-195,-263,176,31456,-2020,-953,-384,-30,-235,-402,-241,31651,-1566,-818,-349,-29,-274,-541,-673,31749,-1116,-681,-312,-27 \ No newline at end of file diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_6.coe b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_6.coe new file mode 100644 index 0000000..5a7d377 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_6.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -27,-322,-715,-1228,31733,-564,-506,-264,-29,-358,-852,-1679,31611,-135,-367,-225,-31,-393,-986,-2133,31392,278,-229,-185,-31,-426,-1116,-2587,31077,673,-94,-145,-32,-456,-1239,-3034,30668,1047,38,-105,-32,-482,-1355,-3473,30167,1397,165,-66,-31,-506,-1462,-3897,29578,1722,286,-27,-30,-526,-1559,-4303,28903,2019,401,10,-28,-541,-1645,-4686,28147,2286,508,45,-25,-552,-1719,-5042,27313,2524,606,79,-21,-559,-1779,-5366,26406,2729,696,111,-17,-560,-1824,-5655,25431,2903,777,141,-11,-556,-1854,-5903,24395,3044,847,168,-5,-547,-1868,-6107,23301,3153,908,193,2,-532,-1864,-6263,22157,3229,958,215,10,-512,-1843,-6368,20969,3273,998,235,19,-486,-1804,-6417,19742,3286,1028,253,29,-455,-1747,-6408,18485,3268,1047,267,40,-418,-1671,-6338,17202,3222,1056,279,52,-375,-1577,-6204,15901,3148,1056,288,64,-327,-1465,-6004,14590,3048,1045,295,77,-275,-1336,-5737,13273,2924,1026,299,91,-218,-1189,-5401,11959,2778,998,301,106,-156,-1027,-4995,10653,2611,963,301,120,-91,-849,-4518,9362,2426,919,298,136,-22,-657,-3971,8092,2226,869,293,151,50,-453,-3355,6849,2012,813,287,166,124,-237,-2669,5638,1788,752,279,182,200,-12,-1915,4466,1554,686,269,197,277,222,-1095,3337,1315,616,258,212,354,461,-212,2256,1071,544,245,226,431,704,732,1226,826,469,233 \ No newline at end of file diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_7.coe b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_7.coe new file mode 100644 index 0000000..af87417 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_7.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = 239,507,949,1734,253,582,393,219,252,581,1193,2790,-661,341,315,204,264,652,1435,3896,-1513,104,238,189,274,720,1672,5047,-2300,-125,162,174,283,783,1901,6239,-3020,-346,87,159,290,842,2121,7466,-3672,-556,14,143,296,895,2328,8724,-4254,-755,-56,128,299,942,2521,10005,-4765,-940,-124,113,301,981,2697,11304,-5207,-1110,-187,98,300,1013,2853,12615,-5578,-1264,-247,84,297,1037,2989,13931,-5879,-1402,-302,71,292,1052,3101,15247,-6112,-1523,-352,58,284,1057,3188,16554,-6279,-1626,-397,46,273,1053,3249,17846,-6380,-1711,-437,35,260,1039,3281,19117,-6420,-1777,-471,24,244,1014,3283,20360,-6399,-1826,-500,15,226,980,3255,21568,-6322,-1856,-523,6,205,934,3195,22735,-6191,-1868,-540,-1,181,879,3103,23855,-6011,-1863,-552,-8,155,813,2978,24920,-5784,-1841,-559,-14,126,738,2820,25927,-5515,-1804,-560,-19,95,652,2631,26868,-5208,-1751,-556,-23,62,558,2409,27739,-4867,-1684,-547,-26,28,455,2156,28535,-4497,-1604,-534,-29,-9,344,1874,29251,-4102,-1512,-516,-31,-46,226,1563,29884,-3687,-1410,-495,-32,-85,102,1225,30429,-3255,-1298,-469,-32,-125,-27,862,30884,-2811,-1178,-441,-32,-165,-161,478,31246,-2360,-1052,-410,-31,-205,-298,73,31514,-1906,-920,-376,-30,-244,-437,-348,31684,-1453,-784,-340,-28,-284,-576,-783,31758,-1004,-646,-303,-688 \ No newline at end of file diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir.tcl b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir.tcl new file mode 100644 index 0000000..83d67e0 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir.tcl @@ -0,0 +1,264 @@ +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_0 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_0.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_0] + +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_1 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_1.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_1] + +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_2 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_2.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_2] + +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_3 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_3.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_3] + +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_4 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_4.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_4] + +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_5 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_5.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_5] + +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_6 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_6.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_6] + +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_7 +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/fir_7.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips fir_7] + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_0.veo b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_0.veo new file mode 100644 index 0000000..b2d1d6f --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_0.veo @@ -0,0 +1,80 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fir_compiler:7.2 +// IP Revision: 18 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fir_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready + .s_axis_data_tlast(s_axis_data_tlast), // input wire s_axis_data_tlast + .s_axis_data_tdata(s_axis_data_tdata), // input wire [31 : 0] s_axis_data_tdata + .s_axis_config_tvalid(s_axis_config_tvalid), // input wire s_axis_config_tvalid + .s_axis_config_tready(s_axis_config_tready), // output wire s_axis_config_tready + .s_axis_config_tlast(s_axis_config_tlast), // input wire s_axis_config_tlast + .s_axis_config_tdata(s_axis_config_tdata), // input wire [7 : 0] s_axis_config_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tlast(m_axis_data_tlast), // output wire m_axis_data_tlast + .m_axis_data_tdata(m_axis_data_tdata), // output wire [31 : 0] m_axis_data_tdata + .event_s_data_tlast_missing(event_s_data_tlast_missing), // output wire event_s_data_tlast_missing + .event_s_data_tlast_unexpected(event_s_data_tlast_unexpected), // output wire event_s_data_tlast_unexpected + .event_s_config_tlast_missing(event_s_config_tlast_missing), // output wire event_s_config_tlast_missing + .event_s_config_tlast_unexpected(event_s_config_tlast_unexpected) // output wire event_s_config_tlast_unexpected +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fir_0.v when simulating +// the core, fir_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_0/fir_0.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_0/fir_0.xci new file mode 100644 index 0000000..a73c782 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_0/fir_0.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 32,32 + 32,32 + fixed + fir_0.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_0 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_0.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_0 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfbs_pr_4x256_v1_v1_0_project/axis_pfbs_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_0 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_1/fir_1.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_1/fir_1.xci new file mode 100644 index 0000000..81ced9d --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_1/fir_1.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_1 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 32,32 + 32,32 + fixed + fir_1.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_1 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_1.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_1 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfbs_pr_4x256_v1_v1_0_project/axis_pfbs_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_1 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_2/fir_2.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_2/fir_2.xci new file mode 100644 index 0000000..f1fbb7a --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_2/fir_2.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_2 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 32,32 + 32,32 + fixed + fir_2.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_2 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_2.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_2 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfbs_pr_4x256_v1_v1_0_project/axis_pfbs_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_2 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_3/fir_3.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_3/fir_3.xci new file mode 100644 index 0000000..652cf8e --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_3/fir_3.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_3 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 32,32 + 32,32 + fixed + fir_3.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_3 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_3.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_3 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfbs_pr_4x256_v1_v1_0_project/axis_pfbs_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_3 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_4/fir_4.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_4/fir_4.xci new file mode 100644 index 0000000..42ef532 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_4/fir_4.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_4 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 32,32 + 32,32 + fixed + fir_4.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_4 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_4.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_4 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfbs_pr_4x256_v1_v1_0_project/axis_pfbs_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_4 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_5/fir_5.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_5/fir_5.xci new file mode 100644 index 0000000..15e1f9a --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_5/fir_5.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_5 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 32,32 + 32,32 + fixed + fir_5.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_5 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_5.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_5 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfbs_pr_4x256_v1_v1_0_project/axis_pfbs_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_5 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_6/fir_6.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_6/fir_6.xci new file mode 100644 index 0000000..00552f8 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_6/fir_6.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_6 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 32,32 + 32,32 + fixed + fir_6.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_6 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_6.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_6 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfbs_pr_4x256_v1_v1_0_project/axis_pfbs_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_6 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_7/fir_7.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_7/fir_7.xci new file mode 100644 index 0000000..c5b4328 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/fir_7/fir_7.xci @@ -0,0 +1,530 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_7 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 1 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 1 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 32,32 + 32,32 + fixed + fir_7.mif + 256 + 2 + 0 + 0,0 + 0,0 + 16,16 + 0 + 16 + 8 + 1 + 4 + fir_7 + 1 + 0 + 8 + 0 + 1 + 16,16 + 0 + 0 + 0 + 0,0 + 0,1 + 16,16 + 16,16 + 16 + 1 + ./ + none + 5 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 17 + 2 + 0 + 0 + 32 + 1 + 32 + 32 + 8 + 1 + 8 + 0 + 0 + none + 0 + 16,16 + 1 + 16 + 1 + 0,1 + 1 + 2 + 0 + 1 + 0 + 32 + 1 + zynquplus + 2 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../coef/fir_7.coe + 0 + false + 32 + Signed + Inferred + 16 + 8 + fir_7 + false + false + false + false + Vector_Framing + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolated + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 32 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + By_Channel + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 2 + zynquplusRFSOC + realdigital.org:rfsoc4x2:part0:1.0 + + xczu48dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../../rfsoc4x2/mkids_kidsim_v1/top/top.tmp/axis_pfbs_pr_4x256_v1_v1_0_project/axis_pfbs_pr_4x256_v1_v1_0_project.gen/sources_1/ip/fir_7 + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/gen.pl b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/gen.pl new file mode 100644 index 0000000..deba046 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/gen.pl @@ -0,0 +1,30 @@ +#!/usr/bin/perl +# This file generates the fir.tcl file to be run from vivado. +# Copy fir coefficient files. One IP per .coe file will be created. +# Copy generated .xci files to avoid generating FIR cores every time. + +open(my $file, "$ARGV[0]") or die "Could not open file '$ARGV[0]' $!"; +my @lines = <$file>; + +open(my $out_tcl, ">", "fir.tcl") or die "Could not open file fir.tcl $!"; +open(my $out_add, ">", "add.tcl") or die "Could not open file fir.tcl $!"; + +@out = `ls coef/*.coe`; +foreach (@out) +{ + chomp($_); + $fir = $_; + $fir =~ s/coef\///g; + $fir =~ s/.coe//g; + + print $out_add ("add_files ./fir/$fir/$fir.xci\n"); + + foreach my $line (@lines) + { + my $temp = $line; + chomp($temp); + $temp =~ s//$fir/g; + print $out_tcl ("$temp\n"); + } +} + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/tcl/fir.tcl.template b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/tcl/fir.tcl.template new file mode 100644 index 0000000..510b2d3 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/tcl/fir.tcl.template @@ -0,0 +1,33 @@ +create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name +set_property -dict [list \ + CONFIG.CoefficientSource {COE_File} \ + CONFIG.Coefficient_File {/home/lstefana/rfsoc-vivado-2022-1/ip/axis_pfbs_pr_4x256_v1/src/fir/coef/.coe} \ + CONFIG.Coefficient_Sets {32} \ + CONFIG.Filter_Type {Interpolated} \ + CONFIG.Number_Channels {32} \ + CONFIG.Number_Paths {2} \ + CONFIG.RateSpecification {Input_Sample_Period} \ + CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ + CONFIG.Output_Width {16} \ + CONFIG.DATA_Has_TLAST {Vector_Framing} \ + CONFIG.S_CONFIG_Method {By_Channel} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Zero_Pack_Factor {2} \ + CONFIG.Select_Pattern {All} \ + CONFIG.SamplePeriod {1} \ + CONFIG.Sample_Frequency {0.001} \ + CONFIG.Clock_Frequency {300.0} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.Coefficient_Width {16} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Data_Width {16} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.ColumnConfig {7} \ + CONFIG.S_DATA_Has_TUSER {Not_Required} \ + CONFIG.M_DATA_Has_TUSER {Not_Required} \ + CONFIG.Filter_Selection {1}] \ +[get_ips ] + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/tcl/ipgen.tcl b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/tcl/ipgen.tcl new file mode 100644 index 0000000..e1a3705 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/fir/tcl/ipgen.tcl @@ -0,0 +1,13 @@ +# Create project. +create_project ipgen ./ipgen -part xczu49dr-ffvf1760-2-e + +# Set language options. +set_property simulator_language Mixed [current_project] +set_property target_language Verilog [current_project] + +# Create IPs. +source fir.tcl + +# Generate instantiation templates. +generate_target instantiation_template [get_ips *] + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/firs.sv b/firmware/ip/axis_pfbs_pr_4x256_v1/src/firs.sv new file mode 100644 index 0000000..fb45002 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/firs.sv @@ -0,0 +1,300 @@ +module firs + #( + // Number of channels. + parameter N = 32 , + + // Number of Lanes (Input). + parameter L = 4 + ) + ( + // Reset and clock. + input wire aresetn , + input wire aclk , + + // S_AXIS for input data. + input wire [2*L*32-1:0] s_axis_tdata , + input wire s_axis_tlast , + input wire s_axis_tvalid , + + // M_AXIS for output data. + output wire [L*32-1:0] m_axis_tdata , + output wire m_axis_tvalid + ); + +/********************/ +/* Internal signals */ +/********************/ +// FIR Configuration interface. +wire config_tvalid; +wire config_tready; +wire config_tlast; +wire [7:0] config_tdata; + +// Framing. +wire tvalid_fr; +wire fr_sync; + +// Input data. +wire [31:0] data_v [2*L]; + +// FIR outputs. +wire signed [31:0] dout_v [2*L]; + +// Delayed FIR outputs. +wire signed [31:0] dout_v_d [L]; + +// Addition of FIR outputs. +wire signed [15:0] sum_real_v [L]; +wire signed [15:0] sum_imag_v [L]; +wire [31:0] sum_v [L]; +wire [L*32-1:0] sum; +reg [L*32-1:0] sum_r1; + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i '0'); + + else + -- State register. + current_state <= next_state; + + -- Counter for config. + if ( cfg_cnt_en = '1' ) then + cfg_cnt <= cfg_cnt + 1; + end if; + + end if; + end if; +end process; + +-- tlast. +tlast_i <= '1' when cfg_cnt = to_unsigned(N-1,cfg_cnt'length) else + '0'; + +-- Next state logic. +process (current_state, cfg_en, tready, cfg_cnt) +begin + case current_state is + when INIT_ST => + if ( cfg_en = '1' and tready = '1' ) then + next_state <= CNT_ST; + else + next_state <= INIT_ST; + end if; + + when CNT_ST => + if ( cfg_cnt = to_unsigned(N-1,cfg_cnt'length) ) then + next_state <= END_ST; + else + next_state <= CNT_ST; + end if; + + when END_ST => + if ( cfg_en = '1' ) then + next_state <= END_ST; + else + next_state <= INIT_ST; + end if; + + end case; +end process; + +-- Output logic. +process (current_state) +begin +cfg_cnt_en <= '0'; + case current_state is + when INIT_ST => + + when CNT_ST=> + cfg_cnt_en <= '1'; + + when END_ST => + + end case; +end process; + +-- Assign outputs. +tvalid <= cfg_cnt_en; +tlast <= tlast_i; +tdata <= std_logic_vector (cfg_cnt); + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_conjugate.sv b/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_conjugate.sv new file mode 100644 index 0000000..87944f3 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_conjugate.sv @@ -0,0 +1,108 @@ +// This block computes the complex conjugate of the data. +module pfb_conjugate + #( + // Number of bits of real/imaginary part. + parameter B = 16 , + + // Number of lanes. + parameter L = 4 + ) + ( + // Reset and clock. + input wire aresetn , + input wire aclk , + + // S_AXIS for input data. + input wire [2*B*L-1:0] s_axis_tdata , + input wire s_axis_tlast , + input wire s_axis_tvalid , + + // M_AXIS for output data. + output wire [2*B*L-1:0] m_axis_tdata , + output wire m_axis_tlast , + output wire m_axis_tvalid + ); + +/********************/ +/* Internal signals */ +/********************/ +// Input data registers. +reg [2*B*L-1:0] din_r1; + +// I/Q parts. +wire signed [B-1:0] din_i_v[L]; +wire signed [B-1:0] din_q_v[L]; + +// Complex conjugate. +wire signed [B-1:0] din_i_conj_v[L]; +wire signed [B-1:0] din_q_conj_v[L]; + +// Output data. +wire [2*B*L-1:0] dout; + +// Output data registers. +reg [2*B*L-1:0] dout_r1; + +// tlast/tvalid registers. +reg tlast_r1; +reg tlast_r2; +reg tvalid_r1; +reg tvalid_r2; + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i N + ) + Port map ( + -- Reset and clock. + rstn => aresetn , + clk => aclk , + + -- Filter config. + cfg_en => cfg_en , + tready => m_axis_config_tready , + tvalid => m_axis_config_tvalid , + tlast => m_axis_config_tlast , + tdata => m_axis_config_tdata + ); + +-- PFB framing. +framing_i : pfb_framing + Generic map ( + -- Number of channels. + N => N + ) + Port map ( + -- Reset and clock. + rstn => aresetn , + clk => aclk , + + -- Framing. + tvalid => tvalid , + fr_sync => fr_sync + ); + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_ctrl_pkg.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_ctrl_pkg.vhd new file mode 100644 index 0000000..db99fb3 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_ctrl_pkg.vhd @@ -0,0 +1,38 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +package pfb_ctrl_pkg is + + -- Functions. + function f_nbit_axis (ARG: Integer) return Integer; + +end pfb_ctrl_pkg; + +package body pfb_ctrl_pkg is + + function f_nbit_axis (ARG: Integer) return Integer is + -- Function variables. + variable arg_log2 : Integer := Integer(ceil(log2(real(ARG)))); + variable tmp : Integer; + + begin + + if (arg_log2 <= 8 ) then + tmp := 8; + elsif ( arg_log2 <= 16 ) then + tmp := 16; + elsif ( arg_log2 <= 24 ) then + tmp := 24; + elsif ( arg_log2 <= 32 ) then + tmp := 32; + else + tmp := -1; + end if; + + return tmp; + end; + +end package body pfb_ctrl_pkg; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_framing.vhd b/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_framing.vhd new file mode 100644 index 0000000..9aa0bae --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_framing.vhd @@ -0,0 +1,114 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity pfb_framing is + Generic ( + -- Number of channels. + N : Integer := 8 + ); + Port ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Framing. + tvalid : out std_logic; + fr_sync : in std_logic + ); +end pfb_framing; + +architecture rtl of pfb_framing is + +-- Wait value. +constant WAIT_C : Integer := 2*N; +constant WAIT_C_LOG2 : Integer := Integer(ceil(log2(real(WAIT_C)))); + +-- FSM. +type fsm_type is ( INIT_ST , + SHIFT_ST , + WAIT_ST ); + +signal current_state, next_state : fsm_type; + +-- Counter for waiting until next calibration. +signal wait_cnt : unsigned (WAIT_C_LOG2-1 downto 0); +signal wait_cnt_en : std_logic; + +signal tvalid_i : std_logic; + +begin + +-- Registers. +process(clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + -- State register. + current_state <= INIT_ST; + + -- Counters. + wait_cnt <= (others => '0'); + else + -- State register. + current_state <= next_state; + + -- Counters. + if ( wait_cnt_en = '1' ) then + if ( wait_cnt < to_unsigned(WAIT_C-1,wait_cnt'length) ) then + wait_cnt <= wait_cnt + 1; + else + wait_cnt <= (others => '0'); + end if; + end if; + + end if; + end if; +end process; + +-- Next state logic. +process (current_state, fr_sync, wait_cnt) +begin + case current_state is + when INIT_ST => + if ( fr_sync = '0' ) then + next_state <= INIT_ST; + else + next_state <= SHIFT_ST; + end if; + + when SHIFT_ST => + next_state <= WAIT_ST; + + when WAIT_ST => + if ( wait_cnt = to_unsigned(WAIT_C-1,wait_cnt'length) ) then + next_state <= INIT_ST; + else + next_state <= WAIT_ST; + end if; + end case; +end process; + +-- Output logic. +process (current_state) +begin +wait_cnt_en <= '0'; +tvalid_i <= '1'; + case current_state is + when INIT_ST => + + when SHIFT_ST => + tvalid_i <= '0'; + + when WAIT_ST => + wait_cnt_en <= '1'; + + end case; +end process; + +-- Assign outputs. +tvalid <= tvalid_i; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_reorder.sv b/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_reorder.sv new file mode 100644 index 0000000..1297219 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/pfb_reorder.sv @@ -0,0 +1,133 @@ +// This block reorders PFB output to get it ready for the +// SSR FFT. +module pfb_reorder + ( + // Reset and clock. + aresetn , + aclk , + + // S_AXIS for input data. + s_axis_tvalid , + s_axis_tlast , + s_axis_tdata , + + // M_AXIS for output data. + m_axis_tvalid , + m_axis_tlast , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Bits. +parameter B = 32; + +// Number of Lanes. +parameter L = 4; + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +input s_axis_tvalid; +input s_axis_tlast; +input [2*L*B-1:0] s_axis_tdata; + +output m_axis_tvalid; +output m_axis_tlast; +output [2*L*B-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Data registers. +reg [2*L*B-1:0] data_r1; +reg [2*L*B-1:0] data_r2; +reg [2*L*B-1:0] data_r3; +reg [2*L*B-1:0] data_r4; + +// Tlast registers. +reg last_r1; +reg last_r2; +reg last_r3; + +// Low/High data. +wire [2*L*B-1:0] dlow; +wire [2*L*B-1:0] dhigh; + +// Muxed output. +reg sel = 0; +wire [2*L*B-1:0] dmux; + +// Sorted output data. +wire [2*L*B-1:0] dmux_sort; + + +/**********************/ +/* Begin Architecture */ +/**********************/ +genvar i; +generate + for (i=0; i NBITS+1 , + + -- Fifo depth. + N => 4 + ) + Port map + ( + rstn => aresetn , + clk => aclk , + + -- Write I/F. + wr_en => s_axis_tvalid , + din => fifo_din , + + -- Read I/F. + rd_en => m_axis_tready , + dout => fifo_dout , + + -- Flags. + full => fifo_full , + empty => fifo_empty + ); + +-- Fifo connections. +fifo_din <= s_axis_tlast & s_axis_tdata; +s_axis_tready <= not(fifo_full); + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( aresetn = '0' ) then + -- Pipeline registers. + d_r <= (others => '0'); + d_rr <= (others => '0'); + empty_r <= '1'; + empty_rr <= '1'; + last_r <= '0'; + last_rr <= '0'; + + -- sel register. + cnt <= (others => '0'); + sel <= (others => '0'); + else + -- Pipeline registers. + d_r <= d_i; + d_rr <= d_mux; + empty_r <= fifo_empty; + empty_rr <= empty_r; + last_r <= last_i; + last_rr <= last_r; + + -- sel register: if reading and not empty, count. + if ( m_axis_tready = '1' and empty_r = '0' ) then + if ( cnt < to_unsigned(T-1,cnt'length) ) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + sel <= sel + 1; + end if; + end if; + + end if; + end if; +end process; + +-- Input data/tlast. +d_i <= fifo_dout(NBITS-1 downto 0); +last_i <= fifo_dout(NBITS); + +-- Slice input. +GEN_SLICE_IN: for I in 0 to L-1 generate + dv_i(I) <= signed(d_r ( 2*I*B+B-1 downto 2*I*B)); + dv_q(I) <= signed(d_r ( (2*I+1)*B+B-1 downto (2*I+1)*B)); +end generate GEN_SLICE_IN; + +-- Multiply by -1 only odd samples. +GEN_PM: for I in 0 to L/2-1 generate + -- Even samples: multiply always by 1. + dv_i_pm(2*I) <= dv_i(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_i_pm(2*I+1) <= to_signed(MAX_P,B) when dv_i(2*I+1) = to_signed(MIN_N,B) else + -dv_i(2*I+1); + + -- Even samples: multiply always by 1. + dv_q_pm(2*I) <= dv_q(2*I); + + -- Odd samples: multiply by -1. Check maximum negative number. + dv_q_pm(2*I+1) <= to_signed(MAX_P,B) when dv_q(2*I+1) = to_signed(MIN_N,B) else + -dv_q(2*I+1); +end generate GEN_PM; + +-- Combine signals back. +GEN_COMBINE_PM: for I in 0 to L-1 generate + d_pm ( 2*I*B+B-1 downto 2*I*B) <= std_logic_vector(dv_i_pm(I)); + d_pm ((2*I+1)*B+B-1 downto (2*I+1)*B) <= std_logic_vector(dv_q_pm(I)); +end generate GEN_COMBINE_PM; + +-- Data mux. +d_mux <= d_r when sel = to_unsigned(0,sel'length) else + d_pm; + + +-- Assign outputs. +m_axis_tdata <= d_rr; +m_axis_tlast <= last_rr; +m_axis_tvalid <= not(empty_rr); + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/tb/tb.sv b/firmware/ip/axis_pfbs_pr_4x256_v1/src/tb/tb.sv new file mode 100644 index 0000000..81b2da3 --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/tb/tb.sv @@ -0,0 +1,331 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +`timescale 1ns/1ps + +parameter N = 256; +parameter L = 4; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +wire [8*32-1:0] s_axis_tdata; +reg s_axis_tlast; +reg s_axis_tvalid; +wire s_axis_tready; + +wire [4*32-1:0] m_axis_tdata; +wire m_axis_tvalid; + + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Input data. +wire[31:0] din_ii [2*L]; +reg signed [15:0] din_real_ii [2*L]; +reg signed [15:0] din_imag_ii [2*L]; + +// Output data. +wire[31:0] dout_ii [L]; +wire[15:0] dout_real_ii[L]; +wire[15:0] dout_imag_ii[L]; + +// Debug. +reg faclk; +reg [31:0] debug_v; +reg [15:0] debug_v_real; +reg [15:0] debug_v_imag; + +// Test bench control. +reg tb_data = 0; +reg tb_data_done= 0; +reg tb_write_out= 0; + +generate +genvar ii; +for (ii = 0; ii < L; ii = ii + 1) begin + // Input data. + assign din_ii [ii] = {din_imag_ii[ii] , din_real_ii[ii]}; + assign din_ii [ii+L] = {din_imag_ii[ii+L], din_real_ii[ii+L]}; + + assign s_axis_tdata [32*ii +: 32] = din_ii[ii]; + assign s_axis_tdata [32*(ii+L) +: 32] = din_ii[ii+L]; + + assign dout_ii [ii] = m_axis_tdata[32*ii +: 32]; + assign dout_real_ii [ii] = dout_ii[ii][15:0]; + assign dout_imag_ii [ii] = dout_ii[ii][31:16]; +end +endgenerate + +// axi_mst_0. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_pfbsynth_4x256_v1 + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk , + .s_axi_aresetn , + .s_axi_araddr , + .s_axi_arprot , + .s_axi_arready , + .s_axi_arvalid , + .s_axi_awaddr , + .s_axi_awprot , + .s_axi_awready , + .s_axi_awvalid , + .s_axi_bready , + .s_axi_bresp , + .s_axi_bvalid , + .s_axi_rdata , + .s_axi_rready , + .s_axi_rresp , + .s_axi_rvalid , + .s_axi_wdata , + .s_axi_wready , + .s_axi_wstrb , + .s_axi_wvalid , + + // s_* and m_* reset/clock. + .aresetn , + .aclk , + + // S_AXIS for data input. + .s_axis_tdata , + .s_axis_tlast , + .s_axis_tvalid , + .s_axis_tready , + + // M_AXIS for data output. + .m_axis_tdata , + .m_axis_tvalid + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + // QOUT_REG + data_wr = 4; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); + #10; + + // Start data. + tb_data <= 1; + #10000; + tb_write_out <= 1; + wait (tb_data_done); + tb_write_out <= 0; +end + +// Input data. +initial begin + real pi; + real w; + real a; + int n; + + s_axis_tlast <= 0; + s_axis_tvalid <= 0; + + wait(tb_data); + @(posedge aclk); + + n = 0; + pi = 3.1415; + w = 0.07; + a = 0.9; + for (int k=0; k<500; k=k+1) begin + for (int i=0; i (others => '0')); + else + if ( s_axis_tvalid = '1' ) then + shift_reg_tdata <= shift_reg_tdata (N-2 downto 0) & s_axis_tdata; + end if; + end if; + end if; +end process; + +-- Assign outputs. +m_axis_tdata <= shift_reg_tdata (N-1); +m_axis_tvalid <= s_axis_tvalid; + +end rtl; + diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/xgui/axis_pfbs_pr_4x256_v1_v1_0.tcl b/firmware/ip/axis_pfbs_pr_4x256_v1/xgui/axis_pfbs_pr_4x256_v1_v1_0.tcl new file mode 100644 index 0000000..716ad7e --- /dev/null +++ b/firmware/ip/axis_pfbs_pr_4x256_v1/xgui/axis_pfbs_pr_4x256_v1_v1_0.tcl @@ -0,0 +1,24 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + diff --git a/firmware/ip/axis_readout_v1/component.xml b/firmware/ip/axis_readout_v1/component.xml new file mode 100644 index 0000000..1fe2856 --- /dev/null +++ b/firmware/ip/axis_readout_v1/component.xml @@ -0,0 +1,1299 @@ + + + user.org + user + axis_readout_v1 + 1.0 + + + m0_axis + + + + + + + TDATA + + + m0_axis_tdata + + + + + TVALID + + + m0_axis_tvalid + + + + + TREADY + + + m0_axis_tready + + + + + + m1_axis + + + + + + + TDATA + + + m1_axis_tdata + + + + + TVALID + + + m1_axis_tvalid + + + + + TREADY + + + m1_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m0_axis:m1_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_readout_v1 + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + f74e8136 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_readout_v1 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + f74e8136 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f92e9879 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector 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/home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + /home/lstefana/qsystem_2/ip/axis_readout_v1 + + + + 2019.1 + + + + + + + + diff --git a/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 0000000..5f33135 --- /dev/null +++ b/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 5 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 0000000..5c4d9a9 --- /dev/null +++ b/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 5 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..34f0b12 --- /dev/null +++ b/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,187 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + virtex7 + + + xc7vx485t + ffg1157 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 0000000..79a6b4d --- /dev/null +++ b/firmware/ip/axis_readout_v1/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4751 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + ARSIZE + + + m_axi_arsize + + + + + ARUSER + + + m_axi_aruser + + + + + ARVALID + + + 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xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_5 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_5 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_5 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 5 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.1 + + + + + + + + + + diff --git a/firmware/ip/axis_readout_v1/src/axi_slv.vhd b/firmware/ip/axis_readout_v1/src/axi_slv.vhd new file mode 100644 index 0000000..e23890d --- /dev/null +++ b/firmware/ip/axis_readout_v1/src/axi_slv.vhd @@ -0,0 +1,516 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + OUTSEL_REG : out std_logic_vector (1 downto 0); + DDS_FREQ_REG : out std_logic_vector (15 downto 0) + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + -- 0 : OUTSEL_REG : 2-bit. Output selection of down-conversion Full Speed. + -- 1 : DDS_FREQ_REG : 16-bit. DDS frequency for down-conversion. + + -- Output Registers. + OUTSEL_REG <= slv_reg0(1 downto 0); + DDS_FREQ_REG <= slv_reg1(15 downto 0); + +end rtl; + diff --git a/firmware/ip/axis_readout_v1/src/axis_readout_v1.v b/firmware/ip/axis_readout_v1/src/axis_readout_v1.v new file mode 100644 index 0000000..93d7673 --- /dev/null +++ b/firmware/ip/axis_readout_v1/src/axis_readout_v1.v @@ -0,0 +1,187 @@ +// Readout V1. +// s_axi_aclk : clock for s_axi_* +// aclk : clock for s0_axis_*, s1_axis_*, and m0_axis_* and m1_axis_* +// +module axis_readout_v1 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // Reset and clock (s_axis, m0_axis, m1_axis). + aresetn , + aclk , + + // S_AXIS: for input data (8x samples per clock). + s_axis_tdata , + s_axis_tvalid , + s_axis_tready , + + // M0_AXIS: for output data (before filter and decimation, 8x samples + // per clock). + m0_axis_tready , + m0_axis_tvalid , + m0_axis_tdata , + + // M1_AXIS: for output data. + m1_axis_tready , + m1_axis_tvalid , + m1_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +localparam [15:0] N_DDS = 8; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [N_DDS*16-1:0] s_axis_tdata; + +input m0_axis_tready; +output m0_axis_tvalid; +output [N_DDS*32-1:0] m0_axis_tdata; + +input m1_axis_tready; +output m1_axis_tvalid; +output [32-1:0] m1_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [1:0] OUTSEL_REG; +wire [15:0] DDS_FREQ_REG; + + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .OUTSEL_REG (OUTSEL_REG ), + .DDS_FREQ_REG (DDS_FREQ_REG ) + ); + +// Readout Top. +readout_top readout_top_i + ( + // Reset and clock (s0_axis, s1_axis, m0_axis, m1_axis). + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS: for input data (8x samples per clock). + .s_axis_tdata (s_axis_tdata ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tready (s_axis_tready ), + + // M0_AXIS: for output data (before filter and decimation, 8x samples + // per clock). + .m0_axis_tready (m0_axis_tready ), + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + + // M1_AXIS: for output data. + .m1_axis_tready (m1_axis_tready ), + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tdata (m1_axis_tdata ), + + // Registers. + .OUTSEL_REG (OUTSEL_REG ), + .DDS_FREQ_REG (DDS_FREQ_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_readout_v1/src/ctrl.sv b/firmware/ip/axis_readout_v1/src/ctrl.sv new file mode 100644 index 0000000..f46382b --- /dev/null +++ b/firmware/ip/axis_readout_v1/src/ctrl.sv @@ -0,0 +1,85 @@ +//Format of waveform interface: +module ctrl ( + // Reset and clock. + rstn , + clk , + + // dds control. + dds_ctrl_o , + + // Registers. + DDS_FREQ_REG + ); + +// Number of parallel dds blocks. +parameter [15:0] N_DDS = 16; + +// Ports. +input rstn; +input clk; +output [N_DDS*40-1:0] dds_ctrl_o; +input [15:0] DDS_FREQ_REG; + +// DDS_FREQ_REG register. +reg [15:0] DDS_FREQ_REG_r; + +// Pinc/phase. +wire [15:0] pinc_int; +reg [15:0] pinc_r1; +wire [15:0] pinc_N; +reg [15:0] pinc_N_r1; + +// Phase vectors. +wire [15:0] phase_v0 [0:N_DDS-1]; +reg [15:0] phase_v0_r1 [0:N_DDS-1]; + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // DDS_FREQ_REG register. + DDS_FREQ_REG_r <= 0; + + // Pinc. + pinc_r1 <= 0; + pinc_N_r1 <= 0; + end + else begin + // DDS_FREQ_REG regisrer. + DDS_FREQ_REG_r <= DDS_FREQ_REG; + + // Pinc. + pinc_r1 <= pinc_int; + pinc_N_r1 <= pinc_N; + end +end + +// Frequency. +assign pinc_int = DDS_FREQ_REG_r; + +// Frequency calculation. +assign pinc_N = pinc_r1*N_DDS; + +// Phase vectors. +generate +genvar i; + for (i=0; i < N_DDS; i = i + 1) begin : GEN_phase + // Registers. + always @(posedge clk) begin + if (~rstn) begin + phase_v0_r1[i] <= 0; + end + else begin + phase_v0_r1[i] <= phase_v0[i]; + end + end + + // v0. + assign phase_v0[i] = pinc_r1*i; + + // dds_ctrl_o output. + assign dds_ctrl_o[i*40 +: 40] = {8'h00,phase_v0_r1[i],pinc_N_r1}; + end +endgenerate + +endmodule + diff --git a/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.veo b/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.veo new file mode 100644 index 0000000..11a9d73 --- /dev/null +++ b/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.veo @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:dds_compiler:6.0 +// IP Revision: 18 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +dds_compiler_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [39 : 0] s_axis_phase_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file dds_compiler_0.v when simulating +// the core, dds_compiler_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.vho b/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.vho new file mode 100644 index 0000000..fca08e6 --- /dev/null +++ b/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.vho @@ -0,0 +1,83 @@ +-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:dds_compiler:6.0 +-- IP Revision: 18 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT dds_compiler_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(39 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : dds_compiler_0 + PORT MAP ( + aclk => aclk, + s_axis_phase_tvalid => s_axis_phase_tvalid, + s_axis_phase_tdata => s_axis_phase_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file dds_compiler_0.vhd when simulating +-- the core, dds_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 0000000..4ecd4c9 --- /dev/null +++ b/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,307 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_compiler_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 5 + 0 + 0 + 0 + 16 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 10 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 40 + 1 + 1 + zynquplus + Full_Range + 1 + dds_compiler_0 + Not_Required + 256 + Maximal + 3906.25 + Coregen + false + false + false + false + 10 + Auto + Not_Required + Not_Required + Auto + Standard + 9 + false + true + Phase_Dithering + Twos_Complement + Speed + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 16 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu111:part0:1.1 + + xczu28dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + . + + . + 2019.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.xml b/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.xml new file mode 100644 index 0000000..8d0fe6f --- /dev/null +++ b/firmware/ip/axis_readout_v1/src/dds_compiler_0/dds_compiler_0.xml @@ -0,0 +1,3168 @@ + + + xilinx.com + customized_ip + dds_compiler_0 + 1.0 + + + event_pinc_invalid_intf + + + + + + + INTERRUPT + + + event_pinc_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_poff_invalid_intf + + + + + + + INTERRUPT + + + event_poff_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_phase_in_invalid_intf + + + + + + + INTERRUPT + + + event_phase_in_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_phase_tlast_missing_intf + + + + + + + INTERRUPT + + + event_s_phase_tlast_missing + + + + + + SENSITIVITY + EDGE_RISING + + + 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doc/dds_compiler_v6_0_changelog.txt + text + + + + The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. + + + Component_Name + Component Name + dds_compiler_0 + + + PartsPresent + Configuration Options + Phase_Generator_and_SIN_COS_LUT + + + DDS_Clock_Rate + System Clock + 256 + + + Channels + Number of Channels + 1 + + + Mode_of_Operation + Mode Of Operation + Standard + + + Modulus + Modulus + 9 + + + Parameter_Entry + Parameter Selection + System_Parameters + + + Spurious_Free_Dynamic_Range + Spurious Free Dynamic Range + 96 + + + Frequency_Resolution + Frequency Resolution + 3906.25 + + + Noise_Shaping + Noise Shaping + Phase_Dithering + + + Phase_Width + Phase Width + 16 + + + Output_Width + Output Width + 16 + + + Phase_Increment + Phase Increment + Streaming + + + Resync + Resync + true + + + Phase_offset + Phase Offset + Streaming + + + Output_Selection + Output Selection + Sine_and_Cosine + + + Negative_Sine + Negative Sine + true + + + Negative_Cosine + Negative Cosine + false + + + Amplitude_Mode + Amplitude Mode + Full_Range + + + Memory_Type + Memory Type + Auto + + + Optimization_Goal + Optimization Goal + Speed + + + DSP48_Use + DSP48 Use + Maximal + + + Has_Phase_Out + Has Phase Out + false + + + DATA_Has_TLAST + DATA Has TLAST + Not_Required + + + Has_TREADY + Output TREADY + false + + + S_PHASE_Has_TUSER + Input + Not_Required + + + S_PHASE_TUSER_Width + User Field Width + 1 + + + M_DATA_Has_TUSER + DATA Output + Not_Required + + + M_PHASE_Has_TUSER + PHASE Output + Not_Required + + + S_CONFIG_Sync_Mode + Synchronization Mode + On_Vector + + + OUTPUT_FORM + Output Form + Twos_Complement + + + Latency_Configuration + Auto + + + Latency + 10 + + + Has_ARESETn + ARESETn (active low) + false + + + Has_ACLKEN + ACLKEN + false + + + Output_Frequency1 + 0 + + + PINC1 + 0 + + + Phase_Offset_Angles1 + 0 + + + POFF1 + 0 + + + Output_Frequency2 + 0 + + + PINC2 + 0 + + + Phase_Offset_Angles2 + 0 + + + POFF2 + 0 + + + Output_Frequency3 + 0 + + + PINC3 + 0 + + + Phase_Offset_Angles3 + 0 + + + POFF3 + 0 + + + Output_Frequency4 + 0 + + + PINC4 + 0 + + + Phase_Offset_Angles4 + 0 + + + POFF4 + 0 + + + Output_Frequency5 + 0 + + + PINC5 + 0 + + + Phase_Offset_Angles5 + 0 + + + POFF5 + 0 + + + Output_Frequency6 + 0 + + + PINC6 + 0 + + + Phase_Offset_Angles6 + 0 + + + POFF6 + 0 + + + Output_Frequency7 + 0 + + + PINC7 + 0 + + + Phase_Offset_Angles7 + 0 + + + POFF7 + 0 + + + Output_Frequency8 + 0 + + + PINC8 + 0 + + + Phase_Offset_Angles8 + 0 + + + POFF8 + 0 + + + Output_Frequency9 + 0 + + + PINC9 + 0 + + + Phase_Offset_Angles9 + 0 + + + POFF9 + 0 + + + Output_Frequency10 + 0 + + + PINC10 + 0 + + + Phase_Offset_Angles10 + 0 + + + POFF10 + 0 + + + Output_Frequency11 + 0 + + + PINC11 + 0 + + + Phase_Offset_Angles11 + 0 + + + POFF11 + 0 + + + Output_Frequency12 + 0 + + + PINC12 + 0 + + + Phase_Offset_Angles12 + 0 + + + POFF12 + 0 + + + Output_Frequency13 + 0 + + + PINC13 + 0 + + + Phase_Offset_Angles13 + 0 + + + POFF13 + 0 + + + Output_Frequency14 + 0 + + + PINC14 + 0 + + + Phase_Offset_Angles14 + 0 + + + POFF14 + 0 + + + Output_Frequency15 + 0 + + + PINC15 + 0 + + + Phase_Offset_Angles15 + 0 + + + POFF15 + 0 + + + Output_Frequency16 + 0 + + + PINC16 + 0 + + + Phase_Offset_Angles16 + 0 + + + POFF16 + 0 + + + POR_mode + POR Mode + false + + + GUI_Behaviour + Coregen + + + explicit_period + false + + + period + 1 + + + + + DDS Compiler + 18 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.1 + + + + + + + + diff --git a/firmware/ip/axis_readout_v1/src/down_conversion.v b/firmware/ip/axis_readout_v1/src/down_conversion.v new file mode 100644 index 0000000..592e92e --- /dev/null +++ b/firmware/ip/axis_readout_v1/src/down_conversion.v @@ -0,0 +1,219 @@ +module down_conversion ( + // Reset and clock. + rstn , + clk , + + // S_AXIS for input. + s_axis_tready_o , + s_axis_tvalid_i , + s_axis_tdata_i , + + // M_AXIS for output. + m_axis_tready_i , + m_axis_tvalid_o , + m_axis_tdata_o , + + // Registers. + OUTSEL_REG , + DDS_FREQ_REG + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [15:0] N_DDS = 16; + +// 0.5 for rounding. +localparam [31:0] RND_0P5 = 2**15; + +/*********/ +/* Ports */ +/*********/ +input rstn; +input clk; + +output s_axis_tready_o; +input s_axis_tvalid_i; +input [N_DDS*16-1:0] s_axis_tdata_i; + +input m_axis_tready_i; +output m_axis_tvalid_o; +output [N_DDS*32-1:0] m_axis_tdata_o; + +input [1:0] OUTSEL_REG; +input [15:0] DDS_FREQ_REG; + +/********************/ +/* Internal signals */ +/********************/ +// DDS input control. +reg dds_tvalid_r; +wire [N_DDS*40-1:0] dds_ctrl_int; +reg [N_DDS*40-1:0] dds_ctrl_int_r; + +// DDS output. +wire [31:0] dds_dout [0:N_DDS-1]; +reg [31:0] dds_dout_r1 [0:N_DDS-1]; +reg [31:0] dds_dout_r2 [0:N_DDS-1]; +reg [31:0] dds_dout_r3 [0:N_DDS-1]; +reg [31:0] dds_dout_r4 [0:N_DDS-1]; + +// Input data. +reg [15:0] din_r1 [0:N_DDS-1]; +reg signed [15:0] din_r2 [0:N_DDS-1]; +reg [15:0] din_r3 [0:N_DDS-1]; +reg [15:0] din_r4 [0:N_DDS-1]; + +// Product. +wire signed [15:0] pa_real [0:N_DDS-1]; +wire signed [15:0] pa_imag [0:N_DDS-1]; +wire signed [31:0] py_full_real [0:N_DDS-1]; +wire signed [31:0] py_full_imag [0:N_DDS-1]; +reg signed [31:0] py_full_real_r [0:N_DDS-1]; +reg signed [31:0] py_full_imag_r [0:N_DDS-1]; +wire signed [31:0] py_round_real [0:N_DDS-1]; +wire signed [31:0] py_round_imag [0:N_DDS-1]; +wire [15:0] py_real [0:N_DDS-1]; +wire [15:0] py_imag [0:N_DDS-1]; +wire [31:0] py [0:N_DDS-1]; +reg [31:0] py_r [0:N_DDS-1]; + +// Muxed output. +wire [31:0] dout_mux [0:N_DDS-1]; +reg [31:0] dout_mux_r [0:N_DDS-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Control block. +ctrl + #( + .N_DDS (N_DDS ) + ) + ctrl_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // dds control. + .dds_ctrl_o (dds_ctrl_int ), + + // Registers. + .DDS_FREQ_REG (DDS_FREQ_REG ) + ); + +generate +genvar i; + for (i=0; i aclk, + s_axis_data_tvalid => s_axis_data_tvalid, + s_axis_data_tready => s_axis_data_tready, + s_axis_data_tdata => s_axis_data_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file fir_compiler_0.vhd when simulating +-- the core, fir_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_readout_v1/src/fir_compiler_0/fir_compiler_0.xci b/firmware/ip/axis_readout_v1/src/fir_compiler_0/fir_compiler_0.xci new file mode 100644 index 0000000..af88717 --- /dev/null +++ b/firmware/ip/axis_readout_v1/src/fir_compiler_0/fir_compiler_0.xci @@ -0,0 +1,296 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_compiler_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 32 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 35,35 + 35,35,35,35,35,35,35,35,35,35,35,35,35,35,35,35 + fixed + fir_compiler_0.mif + 120 + 2 + 0 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 + 0 + 16 + 120 + 1 + 4 + fir_compiler_0 + 0 + 0 + 1 + 2 + 0 + 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 + 0 + 0 + -0,2,4,6,8,10,12,14;-1,3,5,7,9,11,13,15;0,-2,4,6,8,10,12,14;1,-3,5,7,9,11,13,15;0,2,-4,6,8,10,12,14;1,3,-5,7,9,11,13,15;0,2,4,-6,8,10,12,14;1,3,5,-7,9,11,13,15;0,2,4,6,-8,10,12,14;1,3,5,7,-9,11,13,15;0,2,4,6,8,-10,12,14;1,3,5,7,9,-11,13,15;0,2,4,6,8,10,-12,14;1,3,5,7,9,11,-13,15;0,2,4,6,8,10,12,-14;1,3,5,7,9,11,13,-15 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 + 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 + 16 + 1 + ./ + none + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 2 + 126 + 2 + 0 + 0 + 32 + 1 + 1 + 1 + 120 + 1 + 120 + 0 + 0 + none + 0,2,4,6,8,10,12,-14;1,3,5,7,9,11,13,-15 + 16,16 + 1 + 16 + 1 + 14,15,14,15,14,15,14,15,14,15,14,15,14,15,14,15 + 1 + 2 + 0 + 0 + 0 + 256 + 1 + zynquplus + 1 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + ../fir.coe + 0 + false + 1 + Signed + Inferred + 16 + 120 + fir_compiler_0 + Not_Required + 1 + Automatic + 0 + Signed + 16 + 8 + false + Systolic_Multiply_Accumulate + 1 + Decimation + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + 1 + 1 + 2 + Area + None + None + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + Automatic + Integer_Coefficients + Output_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + false + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 1 + zynquplusRFSOC + xilinx.com:zcu111:part0:1.2 + + xczu28dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 12 + TRUE + . + + . + 2019.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_readout_v1/src/fir_compiler_0/fir_compiler_0.xml b/firmware/ip/axis_readout_v1/src/fir_compiler_0/fir_compiler_0.xml new file mode 100644 index 0000000..b37bb5f --- /dev/null +++ b/firmware/ip/axis_readout_v1/src/fir_compiler_0/fir_compiler_0.xml @@ -0,0 +1,2403 @@ + + + xilinx.com + customized_ip + fir_compiler_0 + 1.0 + + + event_s_data_tlast_missing_intf + + + + + + + INTERRUPT + + + event_s_data_tlast_missing + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_data_tlast_unexpected_intf + + + + + + + INTERRUPT + + + event_s_data_tlast_unexpected + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_data_chanid_incorrect_intf + + + + + + + INTERRUPT + + + event_s_data_chanid_incorrect + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_config_tlast_missing_intf + + + + + + + INTERRUPT + + + event_s_config_tlast_missing + + + + + + SENSITIVITY + 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fir_compiler_0 + + + C_COEF_FILE + fir_compiler_0.mif + + + C_COEF_FILE_LINES + 120 + + + C_FILTER_TYPE + 0 + + + C_INTERP_RATE + 1 + + + C_DECIM_RATE + 1 + + + C_ZERO_PACKING_FACTOR + 1 + + + C_SYMMETRY + 0 + + + C_NUM_FILTS + 1 + + + C_NUM_TAPS + 120 + + + C_NUM_CHANNELS + 1 + + + C_CHANNEL_PATTERN + fixed + + + C_ROUND_MODE + 2 + + + C_COEF_RELOAD + 0 + + + C_NUM_RELOAD_SLOTS + 1 + + + C_COL_MODE + 1 + + + C_COL_PIPE_LEN + 4 + + + C_COL_CONFIG + 120 + + + C_OPTIMIZATION + 0 + + + C_DATA_PATH_WIDTHS + 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 + + + C_DATA_IP_PATH_WIDTHS + 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 + + + C_DATA_PX_PATH_WIDTHS + 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 + + + C_DATA_WIDTH + 16 + + + C_COEF_PATH_WIDTHS + 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 + + + C_COEF_WIDTH + 16 + + + C_DATA_PATH_SRC + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + + + C_COEF_PATH_SRC + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + + + C_PX_PATH_SRC + 14,15,14,15,14,15,14,15,14,15,14,15,14,15,14,15 + + + C_DATA_PATH_SIGN + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + + + C_COEF_PATH_SIGN + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + + + C_ACCUM_PATH_WIDTHS + 35,35,35,35,35,35,35,35,35,35,35,35,35,35,35,35 + + + C_OUTPUT_WIDTH + 16 + + + C_OUTPUT_PATH_WIDTHS + 16,16 + + + C_ACCUM_OP_PATH_WIDTHS + 35,35 + + + C_EXT_MULT_CNFG + none + + + C_DATA_PATH_PSAMP_SRC + -0,2,4,6,8,10,12,14;-1,3,5,7,9,11,13,15;0,-2,4,6,8,10,12,14;1,-3,5,7,9,11,13,15;0,2,-4,6,8,10,12,14;1,3,-5,7,9,11,13,15;0,2,4,-6,8,10,12,14;1,3,5,-7,9,11,13,15;0,2,4,6,-8,10,12,14;1,3,5,7,-9,11,13,15;0,2,4,6,8,-10,12,14;1,3,5,7,9,-11,13,15;0,2,4,6,8,10,-12,14;1,3,5,7,9,11,-13,15;0,2,4,6,8,10,12,-14;1,3,5,7,9,11,13,-15 + + + C_OP_PATH_PSAMP_SRC + 0,2,4,6,8,10,12,-14;1,3,5,7,9,11,13,-15 + + + C_NUM_MADDS + 120 + + + C_OPT_MADDS + none + + + C_OVERSAMPLING_RATE + 1 + + + C_INPUT_RATE + 1 + + + C_OUTPUT_RATE + 1 + + + C_DATA_MEMTYPE + 0 + + + C_COEF_MEMTYPE + 2 + + + C_IPBUFF_MEMTYPE + 2 + + + C_OPBUFF_MEMTYPE + 0 + + + C_DATAPATH_MEMTYPE + 2 + + + C_MEM_ARRANGEMENT + 2 + + + C_DATA_MEM_PACKING + 0 + + + C_COEF_MEM_PACKING + 0 + + + C_FILTS_PACKED + 0 + + + C_LATENCY + 126 + + + C_HAS_ARESETn + 0 + + + C_HAS_ACLKEN + 0 + + + C_DATA_HAS_TLAST + 0 + + + C_S_DATA_HAS_FIFO + 0 + + + C_S_DATA_HAS_TUSER + 0 + + + C_S_DATA_TDATA_WIDTH + 256 + + + C_S_DATA_TUSER_WIDTH + 1 + + + C_M_DATA_HAS_TREADY + 0 + + + C_M_DATA_HAS_TUSER + 0 + + + C_M_DATA_TDATA_WIDTH + 32 + + + C_M_DATA_TUSER_WIDTH + 1 + + + C_HAS_CONFIG_CHANNEL + 0 + + + C_CONFIG_SYNC_MODE + 0 + + + C_CONFIG_PACKET_SIZE + 0 + + + C_CONFIG_TDATA_WIDTH + 1 + + + C_RELOAD_TDATA_WIDTH + 1 + + + + + + choice_list_0dc4ca8f + Automatic + Custom + + + choice_list_24b724fb + Basic + Advanced + + + choice_list_3f660234 + All + + + choice_list_5e9d103c + Signed + + + choice_list_8506c89f + Signed + Unsigned + + + choice_list_a63914d2 + Area + Speed + Custom + + + choice_list_dd381b21 + Automatic + Block + Distributed + + + choice_pairs_18e22ec6 + Full_Precision + Truncate_LSBs + Non_Symmetric_Rounding_Down + Non_Symmetric_Rounding_Up + Symmetric_Rounding_to_Zero + Symmetric_Rounding_to_Infinity + Convergent_Rounding_to_Even + Convergent_Rounding_to_Odd + + + choice_pairs_2074757d + None + All + Data_Path_Fanout + Pre-Adder_Pipeline + Coefficient_Fanout + Control_Path_Fanout + Control_Column_Fanout + Control_Broadcast_Fanout + Control_LUT_Pipeline + No_BRAM_Read_First_Mode + Optimal_Column_Lengths + Data_Path_Broadcast + Disable_Half_Band_Centre_Tap + No_SRL_Attributes + Other + + + choice_pairs_2b265cc8 + Frequency_Specification + Input_Sample_Period + Output_Sample_Period + + + choice_pairs_3ab545a3 + Not_Required + Chan_ID_Field + + + choice_pairs_433eb1cb + Inferred + Non_Symmetric + + + choice_pairs_480f8ce0 + Not_Required + Packet_Framing + + + choice_pairs_74144f21 + COE_File + Vector + + + choice_pairs_789dfe7d + Single_Rate + Interpolation + Decimation + Hilbert + Interpolated + + + choice_pairs_8e2d2e35 + Not_Required + User_Field + + + choice_pairs_ab4ea833 + Systolic_Multiply_Accumulate + + + choice_pairs_b6c64168 + Single + By_Channel + + + choice_pairs_eb2746f0 + Integer + Fixed_Fractional + + + choice_pairs_f611af79 + On_Vector + On_Packet + + + choice_pairs_fd92e388 + Integer_Coefficients + Quantize_Only + Maximize_Dynamic_Range + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + fir_compiler_0.vho + vhdlTemplate + + + fir_compiler_0.veo + verilogTemplate + + + + The Xilinx FIR Compiler LogiCORE is a module for generation of high speed, compact filter implementations that can be configured to implement many different filtering functions. The core is fully synchronous, using a single clock, and is highly parameterizable, allowing designers to control the filter type, data and coefficient widths, the number of filter taps, the number of channels, etc. Multi-rate operation is supported. The core is delivered through the Xilinx Vivado IP Catalog and integrates seamlessly with the Xilinx design flow. + + + Component_Name + fir_compiler_0 + + + GUI_Behaviour + Coregen + + + CoefficientSource + COE_File + + + CoefficientVector + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + + + Coefficient_File + ../fir.coe + + + Coefficient_Sets + 1 + + + Coefficient_Reload + false + + + Filter_Type + Decimation + + + Rate_Change_Type + Integer + + + Interpolation_Rate + 1 + + + Decimation_Rate + 8 + + + Zero_Pack_Factor + 1 + + + Channel_Sequence + Basic + + + Number_Channels + 1 + + + Select_Pattern + All + + + Pattern_List + P4-0,P4-1,P4-2,P4-3,P4-4 + + + Number_Paths + 2 + + + RateSpecification + Output_Sample_Period + + + HardwareOversamplingRate + 1 + + + SamplePeriod + 1 + + + Sample_Frequency + 0.001 + + + Clock_Frequency + 300.0 + + + Coefficient_Sign + Signed + + + Quantization + Integer_Coefficients + + + Coefficient_Width + 16 + + + BestPrecision + false + + + Coefficient_Fractional_Bits + 0 + + + Coefficient_Structure + Inferred + + + Data_Sign + Signed + + + Data_Width + 16 + + + Data_Fractional_Bits + 0 + + + Output_Rounding_Mode + Symmetric_Rounding_to_Zero + + + Output_Width + 16 + + + Filter_Architecture + Systolic_Multiply_Accumulate + + + Optimization_Goal + Area + + + Optimization_Selection + None + + + Optimization_List + None + + + Data_Buffer_Type + Automatic + + + Coefficient_Buffer_Type + Automatic + + + Input_Buffer_Type + Automatic + + + Output_Buffer_Type + Automatic + + + Preference_For_Other_Storage + Automatic + + + Multi_Column_Support + Automatic + + + Inter_Column_Pipe_Length + 4 + + + ColumnConfig + 120 + + + DATA_Has_TLAST + Not_Required + + + M_DATA_Has_TREADY + false + + + S_DATA_Has_FIFO + false + + + S_DATA_Has_TUSER + Not_Required + + + M_DATA_Has_TUSER + Not_Required + + + DATA_TUSER_Width + 1 + + + S_CONFIG_Sync_Mode + On_Vector + + + S_CONFIG_Method + Single + + + Num_Reload_Slots + 1 + + + Has_ACLKEN + false + + + Has_ARESETn + false + + + Reset_Data_Vector + true + + + Blank_Output + false + + + Gen_MIF_from_Spec + false + + + Gen_MIF_from_COE + false + + + Reload_File + no_coe_file_loaded + + + Gen_MIF_Files + false + + + DisplayReloadOrder + false + + + Passband_Min + 0.0 + + + Passband_Max + 0.5 + + + Stopband_Min + 0.5 + + + Stopband_Max + 1.0 + + + Filter_Selection + 1 + + + + + FIR Compiler + 12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.1 + + + + + + + + diff --git a/firmware/ip/axis_readout_v1/src/readout_top.v b/firmware/ip/axis_readout_v1/src/readout_top.v new file mode 100644 index 0000000..df886fd --- /dev/null +++ b/firmware/ip/axis_readout_v1/src/readout_top.v @@ -0,0 +1,92 @@ +module readout_top + ( + // Reset and clock (s1_axis, m0_axis, m1_axis). + aresetn , + aclk , + + // S1_AXIS: for input data (8x samples per clock). + s_axis_tdata , + s_axis_tvalid , + s_axis_tready , + + // M0_AXIS: for output data (before filter and decimation, 8x samples + // per clock). + m0_axis_tready , + m0_axis_tvalid , + m0_axis_tdata , + + // M1_AXIS: for output data. + m1_axis_tready , + m1_axis_tvalid , + m1_axis_tdata , + + // Registers. + OUTSEL_REG , + DDS_FREQ_REG + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +localparam [15:0] N_DDS = 8; + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [N_DDS*16-1:0] s_axis_tdata; + +input m0_axis_tready; +output m0_axis_tvalid; +output [N_DDS*32-1:0] m0_axis_tdata; + +input m1_axis_tready; +output m1_axis_tvalid; +output [32-1:0] m1_axis_tdata; + +input [1:0] OUTSEL_REG; +input [15:0] DDS_FREQ_REG; + +/********************/ +/* Internal signals */ +/********************/ + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// Down-conversion + Filter + Decimation. +down_conversion_fir + down_conversion_fir_i + ( + // Reset and clock. + .rstn (aresetn ), + .clk (aclk ), + + // S_AXIS for input. + .s_axis_tready_o (s_axis_tready ), + .s_axis_tvalid_i (s_axis_tvalid ), + .s_axis_tdata_i (s_axis_tdata ), + + // M0_AXIS for output data (before filter and decimation). + .m0_axis_tready_i (m0_axis_tready ), + .m0_axis_tvalid_o (m0_axis_tvalid ), + .m0_axis_tdata_o (m0_axis_tdata ), + + // M1_AXIS for output data. + .m1_axis_tready_i (m1_axis_tready ), + .m1_axis_tvalid_o (m1_axis_tvalid ), + .m1_axis_tdata_o (m1_axis_tdata ), + + // Registers. + .OUTSEL_REG (OUTSEL_REG ), + .DDS_FREQ_REG (DDS_FREQ_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_readout_v1/src/tb/data_iq.txt b/firmware/ip/axis_readout_v1/src/tb/data_iq.txt new file mode 100644 index 0000000..301691a --- /dev/null +++ b/firmware/ip/axis_readout_v1/src/tb/data_iq.txt @@ -0,0 +1,10000 @@ +16392,0 +3219,0 +-15142,0 +-9091,0 +11604,0 +13648,0 +-6276,0 +-16068,0 +11,0 +16054,0 +6273,0 +-13649,0 +-11616,0 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+13650,0 +11564,0 +-9085,0 +-15115,0 +3211,0 +16358,0 +3188,0 +-15134,0 +-9115,0 +11605,0 +13633,0 +-6248,0 +-16062,0 +11,0 +16064,0 +6253,0 +-13608,0 +-11604,0 +9089,0 +15130,0 +-3169,0 diff --git a/firmware/ip/axis_readout_v1/src/tb/tb.sv b/firmware/ip/axis_readout_v1/src/tb/tb.sv new file mode 100644 index 0000000..2774dae --- /dev/null +++ b/firmware/ip/axis_readout_v1/src/tb/tb.sv @@ -0,0 +1,358 @@ +// VIP: axi_mst_0 +// DUT: axis_readout_v1 +// IF: s_axi -> axi_mst_0 + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// Define Behavioral or Post-Synthesis simulation. +//`define SYNTH_SIMU + +localparam N_DDS = 8; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +// s_axis interfase. +wire s_axis_tready; +reg s_axis_tvalid; +reg [N_DDS*16-1:0] s_axis_tdata; + +// m0_axis interfase. +reg m0_axis_tready; +wire m0_axis_tvalid; +reg [N_DDS*32-1:0] m0_axis_tdata; + +// m1_axis interfase. +reg m1_axis_tready; +wire m1_axis_tvalid; +reg [32-1:0] m1_axis_tdata; + +// Assignment of data out for debugging. +wire [31:0] dout_ii [0:N_DDS-1]; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Test bench control. +reg tb_data_in = 0; +reg tb_data_in_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m0_axis_tdata[32*ii +: 32]; +end +endgenerate + +// axi_mst_0. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_readout_v1 + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // s_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS: for input data (8x samples per clock). + .s_axis_tdata (s_axis_tdata ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tready (s_axis_tready ), + + // M0_AXIS: for output data (before filter and decimation, 8x samples + // per clock). + .m0_axis_tready (m0_axis_tready ), + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + + // M1_AXIS: for output data. + .m1_axis_tready (m1_axis_tready ), + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tdata (m1_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + m0_axis_tready <= 1; + m1_axis_tready <= 1; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("###############################"); + $display("### Start Recording Outputs ###"); + $display("###############################"); + $display("t = %0t", $time); + + tb_write_out <= 1; + + + $display("#############################"); + $display("### Select M0_AXIS output ###"); + $display("#############################"); + $display("t = %0t", $time); + + data_wr = 2; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(0, prot, data_wr, resp); + #10; + + #1000; + + $display("###################"); + $display("### Program DDS ###"); + $display("###################"); + $display("t = %0t", $time); + + data_wr = freq_calc(100, N_DDS, 625); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4, prot, data_wr, resp); + #10; + + #1000; + + #1000; + + $display("#######################"); + $display("### Send Input Data ###"); + $display("#######################"); + $display("t = %0t", $time); + tb_data_in <= 1; + + wait (tb_data_in_done); + + #1000; + + $display("##############################"); + $display("### Stop Recording Outputs ###"); + $display("##############################"); + $display("t = %0t", $time); + tb_write_out <= 0; + + #20000; + +end + +// Input data. +initial begin + int fd, i; + bit signed [15:0] vali, valq; + + tb_data_in_done <= 0; + s_axis_tvalid <= 1; + s_axis_tdata <= 0; + + wait (tb_data_in); + + #1000; + + // Open file with input data. + // Format: I, Q. + `ifdef SYNTH_SIMU + fd = $fopen("../../../../../../tb/data_iq.txt","r"); + `else + fd = $fopen("../../../../../tb/data_iq.txt","r"); + `endif + + //i = N_DDS; + i = 0; + while ($fscanf(fd,"%d,%d", vali, valq) == 2) begin + $display("Time %t: Line %d, I = %d, Q = %d", $time, i, vali, valq); + //s_axis_tdata_i[(i-1)*16 +: 16] <= vali; + s_axis_tdata[i*16 +: 16] <= vali; + //i = i - 1; + i = i + 1; + //if ( i == 0) begin + if ( i == N_DDS) begin + //i = N_DDS; + i = 0; + @(posedge aclk); + end + end + + #1000; + + @(posedge aclk); + tb_data_in_done <= 1; + +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d, imag_d; + + // Output file. + `ifdef SYNTH_SIMU + fd = $fopen("../../../../../../tb/dout_fs.csv","w"); + `else + fd = $fopen("../../../../../tb/dout_fs.csv","w"); + `endif + + // Data format. + $fdisplay(fd, "valid, idx, real, imag"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i + + user.org + user + axis_readout_v2 + 1.0 + + + m0_axis + + + + + + + TDATA + + + m0_axis_tdata + + + + + TVALID + + + m0_axis_tvalid + + + + + TREADY + + + m0_axis_tready + + + + + + + true + + + + + + m1_axis + + + + + + + TDATA + + + m1_axis_tdata + + + + + TVALID + + + m1_axis_tvalid + + + + + TREADY + + + m1_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m0_axis:m1_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_readout_v2 + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 6e284896 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_readout_v2 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 6e284896 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f835ce2d + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m0_axis_tvalid + + out + + + std_logic + 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src/fir.coe + coe + + + src/down_conversion.v + verilogSource + + + src/down_conversion_fir.v + verilogSource + + + src/readout_top.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_readout_v2.v + verilogSource + CHECKSUM_f1fe65cd + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/fir_compiler_0/fir_compiler_0.xci + xci + CELL_NAME_readout_top_i/down_conversion_fir_i/fir_i/fir_compiler_0 + + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/fir.coe + coe + + + src/down_conversion.v + verilogSource + + + src/down_conversion_fir.v + verilogSource + + + src/readout_top.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_readout_v2.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_readout_v2_v1_0.tcl + tclSource + CHECKSUM_f835ce2d + XGUI_VERSION_2 + + + + AXIS Readout V2 block with digital down-conversion (32-bit, phase coherent), filtering and 8x decimation. + + + Component_Name + axis_readout_v2_v1_0 + + + FULLSPEED_OUTPUT + Fullspeed Output + true + + + + + + zynquplus + + + /UserIP + + AXIS Readout V2 + package_project + 8 + 2023-02-13T23:05:36Z + + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + /home/lstefana/qsystem_2/ip/axis_readout_v2 + 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/home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/lstefana/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + /home/meeg/Soft/qick/firmware/ip/axis_readout_v2 + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 0000000..7cfbd51 --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 8 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 0000000..a53be60 --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 8 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..ac9cf04 --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,200 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 0000000..4b49cfe --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4760 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + ARSIZE + + + m_axi_arsize + + + + + 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axi_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_8 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_8 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_8 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_8 + + + + xilinx_externalfiles_view_fileset + + axi_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axi_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axi_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 8 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + + diff --git a/firmware/ip/axis_readout_v2/src/axi_slv.vhd b/firmware/ip/axis_readout_v2/src/axi_slv.vhd new file mode 100644 index 0000000..d8aa159 --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/axi_slv.vhd @@ -0,0 +1,528 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + FREQ_REG : out std_logic_vector (31 downto 0); + PHASE_REG : out std_logic_vector (31 downto 0); + NSAMP_REG : out std_logic_vector (15 downto 0); + OUTSEL_REG : out std_logic_vector (1 downto 0); + MODE_REG : out std_logic; + WE_REG : out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + -- 0 : FREQ_REG : 32-bit. + -- 1 : PHASE_REG : 32-bit. + -- 2 : NSAMP_REG : 16-bit. + -- 3 : OUTSEL_REG : 2-bit. + -- 4 : MODE_REG : 1-bit. + -- 5 : WE_REG : 1-bit. + + -- Output Registers. + FREQ_REG <= slv_reg0; + PHASE_REG <= slv_reg1; + NSAMP_REG <= slv_reg2(15 downto 0); + OUTSEL_REG <= slv_reg3(1 downto 0); + MODE_REG <= slv_reg4(0); + WE_REG <= slv_reg5(0); + +end rtl; + diff --git a/firmware/ip/axis_readout_v2/src/axis_readout_v2.v b/firmware/ip/axis_readout_v2/src/axis_readout_v2.v new file mode 100644 index 0000000..692caf0 --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/axis_readout_v2.v @@ -0,0 +1,195 @@ +module axis_readout_v2 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // Reset and clock (s_axis, m0_axis, m1_axis). + aresetn , + aclk , + + // S_AXIS: for input data (8x samples per clock). + s_axis_tdata , + s_axis_tvalid , + s_axis_tready , + + // M0_AXIS: for output data (before filter and decimation, 8x samples + // per clock). + m0_axis_tready , + m0_axis_tvalid , + m0_axis_tdata , + + // M1_AXIS: for output data. + m1_axis_tready , + m1_axis_tvalid , + m1_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +localparam [15:0] N_DDS = 8; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [N_DDS*16-1:0] s_axis_tdata; + +input m0_axis_tready; +output m0_axis_tvalid; +output [N_DDS*32-1:0] m0_axis_tdata; + +input m1_axis_tready; +output m1_axis_tvalid; +output [32-1:0] m1_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] FREQ_REG; +wire [31:0] PHASE_REG; +wire [15:0] NSAMP_REG; +wire [1:0] OUTSEL_REG; +wire MODE_REG; +wire WE_REG; + + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .FREQ_REG (FREQ_REG ), + .PHASE_REG (PHASE_REG ), + .NSAMP_REG (NSAMP_REG ), + .OUTSEL_REG (OUTSEL_REG ), + .MODE_REG (MODE_REG ), + .WE_REG (WE_REG ) + ); + +// Readout Top. +readout_top readout_top_i + ( + // Reset and clock (s0_axis, s1_axis, m0_axis, m1_axis). + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS: for input data (8x samples per clock). + .s_axis_tdata (s_axis_tdata ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tready (s_axis_tready ), + + // M0_AXIS: for output data (before filter and decimation, 8x samples + // per clock). + .m0_axis_tready (m0_axis_tready ), + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + + // M1_AXIS: for output data. + .m1_axis_tready (m1_axis_tready ), + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tdata (m1_axis_tdata ), + + // Registers. + .FREQ_REG (FREQ_REG ), + .PHASE_REG (PHASE_REG ), + .NSAMP_REG (NSAMP_REG ), + .OUTSEL_REG (OUTSEL_REG ), + .MODE_REG (MODE_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_readout_v2/src/ctrl.sv b/firmware/ip/axis_readout_v2/src/ctrl.sv new file mode 100644 index 0000000..a6932cf --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/ctrl.sv @@ -0,0 +1,318 @@ +//Format of waveform interface: +// |------|----------|----------|----------|---------| +// | 82 | 81 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | +// |------|----------|----------|----------|---------| +// | mode | outsel | nsamp | phase | freq | +// |------|----------|----------|----------|---------| +// freq : 32 bits +// phase : 32 bits +// nsamp : 16 bits +// outsel : 2 bits +// mode : 1 bit +// +// Fifo : 83 bits. +module ctrl ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // dds control. + dds_ctrl_o , + + // Output source selection. + outsel_o ); + +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 16; + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [82:0] fifo_dout_i; +output [N_DDS*72-1:0] dds_ctrl_o; +output [1:0] outsel_o; + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// Fifo dout register. +reg [82:0] fifo_dout_r; + +// Non-stop counter for time calculation (adds N_DDS samples each clock tick). +reg [31:0] cnt_n; +reg [31:0] cnt_n_reg; + +// Pinc/phase. +wire [31:0] pinc_int; +reg [31:0] pinc_r1; +reg [31:0] pinc_r2; +wire [31:0] pinc_N; +reg [31:0] pinc_N_r1; +reg [31:0] pinc_N_r2; +reg [31:0] pinc_N_r3; +reg [31:0] pinc_N_r4; +reg [31:0] pinc_N_r5; +wire [31:0] pinc_Nm; +reg [31:0] pinc_Nm_r1; +reg [31:0] pinc_Nm_r2; +reg [31:0] pinc_Nm_r3; + +wire [31:0] phase_int; +reg [31:0] phase_r1; +reg [31:0] phase_r2; +reg [31:0] phase_r3; +reg [31:0] phase_r4; +reg [31:0] phase_r5; +wire [31:0] phase_0; +reg [31:0] phase_0_r1; + +// Phase vectors. +wire [31:0] phase_v0 [0:N_DDS-1]; +reg [31:0] phase_v0_r1 [0:N_DDS-1]; +reg [31:0] phase_v0_r2 [0:N_DDS-1]; +reg [31:0] phase_v0_r3 [0:N_DDS-1]; +reg [31:0] phase_v0_r4 [0:N_DDS-1]; +wire [31:0] phase_v1 [0:N_DDS-1]; +reg [31:0] phase_v1_r1 [0:N_DDS-1]; + +// Number of samples. +wire [15:0] nsamp_int; + +// Output selection. +wire [1:0] outsel_int; +reg [1:0] outsel_r1; +reg [1:0] outsel_r2; +reg [1:0] outsel_r3; +reg [1:0] outsel_r4; +reg [1:0] outsel_r5; +reg [1:0] outsel_r6; +reg [1:0] outsel_r7; + +// Mode. +wire mode_int; + +// Load enable flag. +wire load_int; +reg load_r1; +reg load_r2; +reg load_r3; +reg load_r4; +reg load_r5; +reg load_r6; +reg load_r7; +reg load_r8; + +// Fifo Read Enable. +reg rd_en_int; + +// Counter. +reg [15:0] cnt; + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Non-stop counter for time calculation. + cnt_n <= 0; + cnt_n_reg <= 0; + + // Pinc/phase/sync. + pinc_r1 <= 0; + pinc_r2 <= 0; + pinc_N_r1 <= 0; + pinc_N_r2 <= 0; + pinc_N_r3 <= 0; + pinc_N_r4 <= 0; + pinc_N_r5 <= 0; + pinc_Nm_r1 <= 0; + pinc_Nm_r2 <= 0; + pinc_Nm_r3 <= 0; + + phase_r1 <= 0; + phase_r2 <= 0; + phase_r3 <= 0; + phase_r4 <= 0; + phase_r5 <= 0; + phase_0_r1 <= 0; + + // Output selection. + outsel_r1 <= 0; + outsel_r2 <= 0; + outsel_r3 <= 0; + outsel_r4 <= 0; + outsel_r5 <= 0; + outsel_r6 <= 0; + outsel_r7 <= 0; + + // Load enable flag. + load_r1 <= 0; + load_r2 <= 0; + load_r3 <= 0; + load_r4 <= 0; + load_r5 <= 0; + load_r6 <= 0; + load_r7 <= 0; + load_r8 <= 0; + + // Counter. + cnt <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (mode_int || ~fifo_empty_i) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r1) + fifo_dout_r <= fifo_dout_i; + + // Non-stop counter for time calculation. + cnt_n <= cnt_n + N_DDS; + if (load_r2) + cnt_n_reg <= cnt_n; + + // Pinc/phase/sync. + pinc_r1 <= pinc_int; + pinc_r2 <= pinc_r1; + pinc_N_r1 <= pinc_N; + pinc_N_r2 <= pinc_N_r1; + pinc_N_r3 <= pinc_N_r2; + pinc_N_r4 <= pinc_N_r3; + pinc_N_r5 <= pinc_N_r4; + pinc_Nm_r1 <= pinc_Nm; + pinc_Nm_r2 <= pinc_Nm_r1; + pinc_Nm_r3 <= pinc_Nm_r2; + + phase_r1 <= phase_int; + phase_r2 <= phase_r1; + phase_r3 <= phase_r2; + phase_r4 <= phase_r3; + phase_r5 <= phase_r4; + phase_0_r1 <= phase_0; + + // Output selection. + outsel_r1 <= outsel_int; + outsel_r2 <= outsel_r1; + outsel_r3 <= outsel_r2; + outsel_r4 <= outsel_r3; + outsel_r5 <= outsel_r4; + outsel_r6 <= outsel_r5; + outsel_r7 <= outsel_r6; + + // Load enable flag. + load_r1 <= load_int; + load_r2 <= load_r1; + load_r3 <= load_r2; + load_r4 <= load_r3; + load_r5 <= load_r4; + load_r6 <= load_r5; + load_r7 <= load_r6; + load_r8 <= load_r7; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign pinc_int = fifo_dout_r[31:0]; +assign phase_int = fifo_dout_r[63:32]; +assign nsamp_int = fifo_dout_r[79:64]; +assign outsel_int = fifo_dout_r[81:80]; +assign mode_int = fifo_dout_r[82]; + +// Frequency calculation. +assign pinc_N = pinc_r2*N_DDS; + +// Phase calculation. +assign pinc_Nm = pinc_r2*cnt_n_reg; +assign phase_0 = pinc_Nm_r3 + phase_r5; + +// Phase vectors. +generate +genvar i; + for (i=0; i < N_DDS; i = i + 1) begin : GEN_phase + // Registers. + always @(posedge clk) begin + if (~rstn) begin + // v0. + phase_v0_r1[i] <= 0; + phase_v0_r2[i] <= 0; + phase_v0_r3[i] <= 0; + phase_v0_r4[i] <= 0; + + // v1. + phase_v1_r1[i] <= 0; + end + else begin + // v0. + phase_v0_r1[i] <= phase_v0[i]; + phase_v0_r2[i] <= phase_v0_r1[i]; + phase_v0_r3[i] <= phase_v0_r2[i]; + phase_v0_r4[i] <= phase_v0_r3[i]; + + // v1. + phase_v1_r1[i] <= phase_v1[i]; + end + end + + // v0. + assign phase_v0[i] = pinc_r2*i; + + // v1. + assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; + + // dds_ctrl_o output. + assign dds_ctrl_o[i*72 +: 72] = {7'h00,load_r8,phase_v1_r1[i],pinc_N_r5}; + end +endgenerate + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign outsel_o = outsel_r7; + +endmodule + diff --git a/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.veo b/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.veo new file mode 100644 index 0000000..7bf3bc5 --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.veo @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:dds_compiler:6.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +dds_compiler_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [71 : 0] s_axis_phase_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file dds_compiler_0.v when simulating +// the core, dds_compiler_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.vho b/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.vho new file mode 100644 index 0000000..8bdeb4a --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.vho @@ -0,0 +1,83 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:dds_compiler:6.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT dds_compiler_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : dds_compiler_0 + PORT MAP ( + aclk => aclk, + s_axis_phase_tvalid => s_axis_phase_tvalid, + s_axis_phase_tdata => s_axis_phase_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file dds_compiler_0.vhd when simulating +-- the core, dds_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 0000000..4b781ec --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,318 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_compiler_0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 9 + 0 + 0 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 8 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 72 + 1 + 1 + zynquplus + Full_Range + 1 + dds_compiler_0 + Not_Required + 256 + Maximal + 0.06 + Coregen + false + false + false + false + 8 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + false + Auto + Twos_Complement + Speed + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 20 + TRUE + ../../../../top/top.tmp/axis_readout_v2_v1_0_project/axis_readout_v2_v1_0_project.gen/sources_1/ip/dds_compiler_0 + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.xml b/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.xml new file mode 100644 index 0000000..57bba34 --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/dds_compiler_0/dds_compiler_0.xml @@ -0,0 +1,2846 @@ + + + xilinx.com + customized_ip + dds_compiler_0 + 1.0 + + + event_pinc_invalid_intf + + + + + + + INTERRUPT + + + event_pinc_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_poff_invalid_intf + + + + + + + INTERRUPT + + + event_poff_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_phase_in_invalid_intf + + + + + + + INTERRUPT + + + event_phase_in_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_phase_tlast_missing_intf + + + + + + + INTERRUPT + + + event_s_phase_tlast_missing + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_phase_tlast_unexpected_intf + + + + + + + INTERRUPT + + + event_s_phase_tlast_unexpected + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_phase_chanid_incorrect_intf + + + + + + + INTERRUPT + + + event_s_phase_chanid_incorrect + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_config_tlast_missing_intf + + + + + + + INTERRUPT + + + event_s_config_tlast_missing + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_config_tlast_unexpected_intf + + + + + + + INTERRUPT + + + event_s_config_tlast_unexpected + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + S_AXIS_PHASE + S_AXIS_PHASE + + + + + + + TDATA + + + s_axis_phase_tdata + + + + + TLAST + + + s_axis_phase_tlast + + + + + TREADY + + + s_axis_phase_tready + + + + + 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xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + GENtimestamp + Fri Feb 18 20:02:41 UTC 2022 + + + outputProductCRC + 9:2d00cc37 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + dds_compiler_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Fri Feb 18 20:02:41 UTC 2022 + + + outputProductCRC + 9:2d00cc37 + + + + + + + aclk + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + aclken + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + 0x1 + + + + + + false + + + + + + aresetn + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + 0x1 + + + + + + false + + + + + + s_axis_phase_tvalid + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + s_axis_phase_tready + + out + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + s_axis_phase_tdata + + in + + 71 + 0 + + + + std_logic_vector + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axis_phase_tlast + + in + + + std_logic + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + s_axis_phase_tuser + + in + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axis_config_tvalid + + in + + + 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Auto + None + Phase_Dithering + Taylor_Series_Corrected + + + choice_pairs_944fe41d + Phase_Generator_and_SIN_COS_LUT + Phase_Generator_only + SIN_COS_LUT_only + + + choice_pairs_a54f933f + Sine + Cosine + Sine_and_Cosine + + + choice_pairs_d463c5cb + User_Field + Not_Required + + + choice_pairs_dac1efef + Not_Required + + + choice_pairs_f611af79 + On_Vector + On_Packet + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + dds_compiler_0.vho + vhdlTemplate + + + dds_compiler_0.veo + verilogTemplate + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + hdl/xbip_pipe_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_pipe_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + hdl/xbip_bram18k_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_bram18k_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + hdl/mult_gen_v12_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + mult_gen_v12_0_16 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_wrapper_v3_0_4 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_addsub_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_multadd_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/dds_compiler_v6_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + dds_compiler_v6_0_20 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/dds_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. + + + Component_Name + Component Name + dds_compiler_0 + + + PartsPresent + Configuration Options + Phase_Generator_and_SIN_COS_LUT + + + DDS_Clock_Rate + System Clock + 256 + + + Channels + Number of Channels + 1 + + + Mode_of_Operation + Mode Of Operation + Standard + + + Modulus + Modulus + 9 + + + Parameter_Entry + Parameter Selection + System_Parameters + + + Spurious_Free_Dynamic_Range + Spurious Free Dynamic Range + 96 + + + Frequency_Resolution + Frequency Resolution + 0.06 + + + Noise_Shaping + Noise Shaping + Auto + + + Phase_Width + Phase Width + 32 + + + Output_Width + Output Width + 16 + + + Phase_Increment + Phase Increment + Streaming + + + Resync + Resync + true + + + Phase_offset + Phase Offset + Streaming + + + Output_Selection + Output Selection + Sine_and_Cosine + + + Negative_Sine + Negative Sine + false + + + Negative_Cosine + Negative Cosine + false + + + Amplitude_Mode + Amplitude Mode + Full_Range + + + Memory_Type + Memory Type + Auto + + + Optimization_Goal + Optimization Goal + Speed + + + DSP48_Use + DSP48 Use + Maximal + + + Has_Phase_Out + Has Phase Out + false + + + DATA_Has_TLAST + DATA Has TLAST + Not_Required + + + Has_TREADY + Output TREADY + false + + + S_PHASE_Has_TUSER + Input + Not_Required + + + S_PHASE_TUSER_Width + User Field Width + 1 + + + M_DATA_Has_TUSER + DATA Output + Not_Required + + + M_PHASE_Has_TUSER + PHASE Output + Not_Required + + + S_CONFIG_Sync_Mode + Synchronization Mode + On_Vector + + + OUTPUT_FORM + Output Form + Twos_Complement + + + Latency_Configuration + Configurable + + + Latency + 8 + + + Has_ARESETn + ARESETn (active low) + false + + + Has_ACLKEN + ACLKEN + false + + + Output_Frequency1 + 0 + + + PINC1 + 0 + + + Phase_Offset_Angles1 + 0 + + + POFF1 + 0 + + + Output_Frequency2 + 0 + + + PINC2 + 0 + + + Phase_Offset_Angles2 + 0 + + + POFF2 + 0 + + + Output_Frequency3 + 0 + + + PINC3 + 0 + + + Phase_Offset_Angles3 + 0 + + + POFF3 + 0 + + + Output_Frequency4 + 0 + + + PINC4 + 0 + + + Phase_Offset_Angles4 + 0 + + + POFF4 + 0 + + + Output_Frequency5 + 0 + + + PINC5 + 0 + + + Phase_Offset_Angles5 + 0 + + + POFF5 + 0 + + + Output_Frequency6 + 0 + + + PINC6 + 0 + + + Phase_Offset_Angles6 + 0 + + + POFF6 + 0 + + + Output_Frequency7 + 0 + + + PINC7 + 0 + + + Phase_Offset_Angles7 + 0 + + + POFF7 + 0 + + + Output_Frequency8 + 0 + + + PINC8 + 0 + + + Phase_Offset_Angles8 + 0 + + + POFF8 + 0 + + + Output_Frequency9 + 0 + + + PINC9 + 0 + + + Phase_Offset_Angles9 + 0 + + + POFF9 + 0 + + + Output_Frequency10 + 0 + + + PINC10 + 0 + + + Phase_Offset_Angles10 + 0 + + + POFF10 + 0 + + + Output_Frequency11 + 0 + + + PINC11 + 0 + + + Phase_Offset_Angles11 + 0 + + + POFF11 + 0 + + + Output_Frequency12 + 0 + + + PINC12 + 0 + + + Phase_Offset_Angles12 + 0 + + + POFF12 + 0 + + + Output_Frequency13 + 0 + + + PINC13 + 0 + + + Phase_Offset_Angles13 + 0 + + + POFF13 + 0 + + + Output_Frequency14 + 0 + + + PINC14 + 0 + + + Phase_Offset_Angles14 + 0 + + + POFF14 + 0 + + + Output_Frequency15 + 0 + + + PINC15 + 0 + + + Phase_Offset_Angles15 + 0 + + + POFF15 + 0 + + + Output_Frequency16 + 0 + + + PINC16 + 0 + + + Phase_Offset_Angles16 + 0 + + + POFF16 + 0 + + + POR_mode + POR Mode + false + + + GUI_Behaviour + Coregen + + + explicit_period + false + + + period + 1 + + + + + DDS Compiler + 20 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_readout_v2/src/down_conversion.v b/firmware/ip/axis_readout_v2/src/down_conversion.v new file mode 100644 index 0000000..ae8bd04 --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/down_conversion.v @@ -0,0 +1,229 @@ +module down_conversion ( + // Reset and clock. + rstn , + clk , + + // S_AXIS for input. + s_axis_tready_o , + s_axis_tvalid_i , + s_axis_tdata_i , + + // M_AXIS for output. + m_axis_tready_i , + m_axis_tvalid_o , + m_axis_tdata_o , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [15:0] N_DDS = 16; + +// 0.5 for rounding. +localparam [31:0] RND_0P5 = 2**15; + +/*********/ +/* Ports */ +/*********/ +input rstn; +input clk; + +output s_axis_tready_o; +input s_axis_tvalid_i; +input [N_DDS*16-1:0] s_axis_tdata_i; + +input m_axis_tready_i; +output m_axis_tvalid_o; +output [N_DDS*32-1:0] m_axis_tdata_o; + +output fifo_rd_en_o; +input fifo_empty_i; +input [82:0] fifo_dout_i; + +/********************/ +/* Internal signals */ +/********************/ +// DDS input control. +reg dds_tvalid_r; +wire [N_DDS*72-1:0] dds_ctrl_int; +reg [N_DDS*72-1:0] dds_ctrl_int_r; + +// Output selection. +wire [1:0] outsel_int; + +// DDS output. +wire [31:0] dds_dout [0:N_DDS-1]; +reg [31:0] dds_dout_r1 [0:N_DDS-1]; +reg [31:0] dds_dout_r2 [0:N_DDS-1]; +reg [31:0] dds_dout_r3 [0:N_DDS-1]; +reg [31:0] dds_dout_r4 [0:N_DDS-1]; + +// Input data. +reg [15:0] din_r1 [0:N_DDS-1]; +reg signed [15:0] din_r2 [0:N_DDS-1]; +reg [15:0] din_r3 [0:N_DDS-1]; +reg [15:0] din_r4 [0:N_DDS-1]; + +// Product. +wire signed [15:0] pa_real [0:N_DDS-1]; +wire signed [15:0] pa_imag [0:N_DDS-1]; +wire signed [31:0] py_full_real [0:N_DDS-1]; +wire signed [31:0] py_full_imag [0:N_DDS-1]; +reg signed [31:0] py_full_real_r [0:N_DDS-1]; +reg signed [31:0] py_full_imag_r [0:N_DDS-1]; +wire signed [31:0] py_round_real [0:N_DDS-1]; +wire signed [31:0] py_round_imag [0:N_DDS-1]; +wire [15:0] py_real [0:N_DDS-1]; +wire [15:0] py_imag [0:N_DDS-1]; +wire [31:0] py [0:N_DDS-1]; +reg [31:0] py_r [0:N_DDS-1]; + +// Muxed output. +wire [31:0] dout_mux [0:N_DDS-1]; +reg [31:0] dout_mux_r [0:N_DDS-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Control block. +ctrl + #( + .N_DDS (N_DDS ) + ) + ctrl_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Fifo interface. + .fifo_rd_en_o (fifo_rd_en_o ), + .fifo_empty_i (fifo_empty_i ), + .fifo_dout_i (fifo_dout_i ), + + // dds control. + .dds_ctrl_o (dds_ctrl_int ), + + // Output source selection. + .outsel_o (outsel_int ) + ); + +generate +genvar i; + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_readout_v2/src/fifo/fifo_axi.vhd b/firmware/ip/axis_readout_v2/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_readout_v2/src/fifo/fifo_dc.vhd b/firmware/ip/axis_readout_v2/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_readout_v2/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_readout_v2/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_readout_v2/src/fifo/gray2bin.vhd b/firmware/ip/axis_readout_v2/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_readout_v2/src/fifo/rd2axi.vhd b/firmware/ip/axis_readout_v2/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_readout_v2/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_readout_v2/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_readout_v2/src/fir.coe b/firmware/ip/axis_readout_v2/src/fir.coe new file mode 100644 index 0000000..458482d --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/fir.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -56,-4,13,47,97,166,252,353,463,573,674,754,801,804,753,643,473,249,-20,-314,-611,-885,-1107,-1248,-1285,-1201,-989,-651,-206,318,878,1425,1903,2254,2428,2383,2094,1556,786,-172,-1251,-2364,-3408,-4271,-4839,-5010,-4696,-3838,-2410,-422,2076,4993,8205,11560,14889,18012,20758,22971,24523,25322,25322,24523,22971,20758,18012,14889,11560,8205,4993,2076,-422,-2410,-3838,-4696,-5010,-4839,-4271,-3408,-2364,-1251,-172,786,1556,2094,2383,2428,2254,1903,1425,878,318,-206,-651,-989,-1201,-1285,-1248,-1107,-885,-611,-314,-20,249,473,643,753,804,801,754,674,573,463,353,252,166,97,47,13,-4,-56 \ No newline at end of file diff --git a/firmware/ip/axis_readout_v2/src/fir_compiler_0.v b/firmware/ip/axis_readout_v2/src/fir_compiler_0.v new file mode 100644 index 0000000..aab1311 --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/fir_compiler_0.v @@ -0,0 +1,15 @@ +module fir_compiler_0 + ( + input aclk , + input s_axis_data_tvalid , + output s_axis_data_tready , + input [255:0] s_axis_data_tdata , + output m_axis_data_tvalid , + output [31:0] m_axis_data_tdata +); + +assign s_axis_data_tready = 1'b1; +assign m_axis_data_tvalid = s_axis_data_tvalid; +assign m_axis_data_tdata = s_axis_data_tdata[31:0]; + +endmodule diff --git a/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.veo b/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.veo new file mode 100644 index 0000000..e66a3e8 --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fir_compiler:7.2 +// IP Revision: 15 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fir_compiler_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready + .s_axis_data_tdata(s_axis_data_tdata), // input wire [255 : 0] s_axis_data_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fir_compiler_0.v when simulating +// the core, fir_compiler_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.vho b/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.vho new file mode 100644 index 0000000..a877167 --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fir_compiler:7.2 +-- IP Revision: 15 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT fir_compiler_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_data_tvalid : IN STD_LOGIC; + s_axis_data_tready : OUT STD_LOGIC; + s_axis_data_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : fir_compiler_0 + PORT MAP ( + aclk => aclk, + s_axis_data_tvalid => s_axis_data_tvalid, + s_axis_data_tready => s_axis_data_tready, + s_axis_data_tdata => s_axis_data_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file fir_compiler_0.vhd when simulating +-- the core, fir_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.xci b/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.xci new file mode 100644 index 0000000..77b68ac --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.xci @@ -0,0 +1,321 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_compiler_0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 32 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 35,35 + 35,35,35,35,35,35,35,35,35,35,35,35,35,35,35,35 + fixed + fir_compiler_0.mif + 60 + 2 + 0 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 + 0 + 16 + 60 + 1 + 4 + fir_compiler_0 + 0 + 0 + 1 + 2 + 0 + 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 + 0 + 0 + -0,2,4,6,8,10,12,14;-1,3,5,7,9,11,13,15;0,-2,4,6,8,10,12,14;1,-3,5,7,9,11,13,15;0,2,-4,6,8,10,12,14;1,3,-5,7,9,11,13,15;0,2,4,-6,8,10,12,14;1,3,5,-7,9,11,13,15;0,2,4,6,-8,10,12,14;1,3,5,7,-9,11,13,15;0,2,4,6,8,-10,12,14;1,3,5,7,9,-11,13,15;0,2,4,6,8,10,-12,14;1,3,5,7,9,11,-13,15;0,2,4,6,8,10,12,-14;1,3,5,7,9,11,13,-15 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 + 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16 + 16 + 1 + ./ + none + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 2 + 67 + 1 + 0 + 0 + 32 + 1 + 1 + 1 + 60 + 1 + 120 + 0 + 0 + none + 0,2,4,6,8,10,12,-14;1,3,5,7,9,11,13,-15 + 16,16 + 1 + 16 + 1 + 14,15,14,15,14,15,14,15,14,15,14,15,14,15,14,15 + 1 + 2 + 1 + 0 + 0 + 256 + 1 + zynquplus + 1 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../fir.coe + 0 + false + 1 + Signed + Inferred + 16 + 60 + fir_compiler_0 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 8 + false + false + Systolic_Multiply_Accumulate + 1 + Decimation + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Output_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + false + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../top/top.tmp/axis_readout_v2_v1_0_project/axis_readout_v2_v1_0_project.gen/sources_1/ip/fir_compiler_0 + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.xml b/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.xml new file mode 100644 index 0000000..8dedd26 --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/fir_compiler_0/fir_compiler_0.xml @@ -0,0 +1,2564 @@ + + + xilinx.com + customized_ip + fir_compiler_0 + 1.0 + + + event_s_data_tlast_missing_intf + + + + + + + INTERRUPT + + + event_s_data_tlast_missing + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_data_tlast_unexpected_intf + + + + + + + INTERRUPT + + + event_s_data_tlast_unexpected + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_data_chanid_incorrect_intf + + + + + + + INTERRUPT + + + event_s_data_chanid_incorrect + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_config_tlast_missing_intf + + + + + + + INTERRUPT + + + event_s_config_tlast_missing + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_config_tlast_unexpected_intf + + + + + + + INTERRUPT + + + event_s_config_tlast_unexpected + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_reload_tlast_missing_intf + + + + + + + INTERRUPT + + + event_s_reload_tlast_missing + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_reload_tlast_unexpected_intf + + + + + + + INTERRUPT + + + event_s_reload_tlast_unexpected + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + S_AXIS_RELOAD + S_AXIS_RELOAD + + + + + + + TDATA + + + s_axis_reload_tdata + + + + + TLAST + + + s_axis_reload_tlast + + + + + TREADY + + + s_axis_reload_tready + + + + + TVALID + + + s_axis_reload_tvalid + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + 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C_OUTPUT_PATH_WIDTHS + 16,16 + + + C_ACCUM_OP_PATH_WIDTHS + 35,35 + + + C_EXT_MULT_CNFG + none + + + C_DATA_PATH_PSAMP_SRC + -0,2,4,6,8,10,12,14;-1,3,5,7,9,11,13,15;0,-2,4,6,8,10,12,14;1,-3,5,7,9,11,13,15;0,2,-4,6,8,10,12,14;1,3,-5,7,9,11,13,15;0,2,4,-6,8,10,12,14;1,3,5,-7,9,11,13,15;0,2,4,6,-8,10,12,14;1,3,5,7,-9,11,13,15;0,2,4,6,8,-10,12,14;1,3,5,7,9,-11,13,15;0,2,4,6,8,10,-12,14;1,3,5,7,9,11,-13,15;0,2,4,6,8,10,12,-14;1,3,5,7,9,11,13,-15 + + + C_OP_PATH_PSAMP_SRC + 0,2,4,6,8,10,12,-14;1,3,5,7,9,11,13,-15 + + + C_NUM_MADDS + 60 + + + C_OPT_MADDS + none + + + C_OVERSAMPLING_RATE + 1 + + + C_INPUT_RATE + 1 + + + C_OUTPUT_RATE + 1 + + + C_DATA_MEMTYPE + 0 + + + C_COEF_MEMTYPE + 2 + + + C_IPBUFF_MEMTYPE + 2 + + + C_OPBUFF_MEMTYPE + 0 + + + C_DATAPATH_MEMTYPE + 2 + + + C_MEM_ARRANGEMENT + 1 + + + C_DATA_MEM_PACKING + 0 + + + C_COEF_MEM_PACKING + 0 + + + C_FILTS_PACKED + 0 + + + C_LATENCY + 67 + + + C_HAS_ARESETn + 0 + + + C_HAS_ACLKEN + 0 + + + C_DATA_HAS_TLAST + 0 + + + C_S_DATA_HAS_FIFO + 0 + + + C_S_DATA_HAS_TUSER + 0 + + + C_S_DATA_TDATA_WIDTH + 256 + + + C_S_DATA_TUSER_WIDTH + 1 + + + C_M_DATA_HAS_TREADY + 0 + + + C_M_DATA_HAS_TUSER + 0 + + + C_M_DATA_TDATA_WIDTH + 32 + + + C_M_DATA_TUSER_WIDTH + 1 + + + C_HAS_CONFIG_CHANNEL + 0 + + + C_CONFIG_SYNC_MODE + 0 + + + C_CONFIG_PACKET_SIZE + 0 + + + C_CONFIG_TDATA_WIDTH + 1 + + + C_RELOAD_TDATA_WIDTH + 1 + + + + + + choice_list_0dc4ca8f + Automatic + Custom + + + choice_list_24b724fb + Basic + Advanced + + + choice_list_3f660234 + All + + + choice_list_5e9d103c + Signed + + + choice_list_8506c89f + Signed + Unsigned + + + choice_list_a63914d2 + Area + Speed + Custom + + + choice_list_dd381b21 + Automatic + Block + Distributed + + + choice_pairs_18e22ec6 + Full_Precision + Truncate_LSBs + Non_Symmetric_Rounding_Down + Non_Symmetric_Rounding_Up + Symmetric_Rounding_to_Zero + Symmetric_Rounding_to_Infinity + Convergent_Rounding_to_Even + Convergent_Rounding_to_Odd + + + choice_pairs_2074757d + None + All + Data_Path_Fanout + Pre-Adder_Pipeline + Coefficient_Fanout + Control_Path_Fanout + Control_Column_Fanout + Control_Broadcast_Fanout + Control_LUT_Pipeline + No_BRAM_Read_First_Mode + Optimal_Column_Lengths + Data_Path_Broadcast + Disable_Half_Band_Centre_Tap + No_SRL_Attributes + Other + + + choice_pairs_2b265cc8 + Frequency_Specification + Input_Sample_Period + Output_Sample_Period + + + choice_pairs_3ab545a3 + Not_Required + Chan_ID_Field + + + choice_pairs_480f8ce0 + Not_Required + Packet_Framing + + + choice_pairs_541959c1 + Inferred + Non_Symmetric + Symmetric + + + choice_pairs_74144f21 + COE_File + Vector + + + choice_pairs_789dfe7d + Single_Rate + Interpolation + Decimation + Hilbert + Interpolated + + + choice_pairs_8e2d2e35 + Not_Required + User_Field + + + choice_pairs_ab4ea833 + Systolic_Multiply_Accumulate + + + choice_pairs_b6c64168 + Single + By_Channel + + + choice_pairs_eb2746f0 + Integer + Fixed_Fractional + + + choice_pairs_f611af79 + On_Vector + On_Packet + + + choice_pairs_fd92e388 + Integer_Coefficients + Quantize_Only + Maximize_Dynamic_Range + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + fir_compiler_0.vho + vhdlTemplate + + + fir_compiler_0.veo + verilogTemplate + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + constraints/fir_compiler_v7_2.xdc + xdc + fir_compiler_v7_2_15 + + + fir_compiler_0.mif + mif + + + hdl/fir_compiler_v7_2_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + fir_compiler_v7_2_15 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/fir_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + The Xilinx FIR Compiler LogiCORE is a module for generation of high speed, compact filter implementations that can be configured to implement many different filtering functions. The core is fully synchronous, using a single clock, and is highly parameterizable, allowing designers to control the filter type, data and coefficient widths, the number of filter taps, the number of channels, etc. Multi-rate operation is supported. The core is delivered through the Xilinx Vivado IP Catalog and integrates seamlessly with the Xilinx design flow. + + + Component_Name + fir_compiler_0 + + + GUI_Behaviour + Coregen + + + CoefficientSource + COE_File + + + CoefficientVector + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + + + Coefficient_File + ../fir.coe + + + Coefficient_Sets + 1 + + + Coefficient_Reload + false + + + Filter_Type + Decimation + + + Rate_Change_Type + Integer + + + Interpolation_Rate + 1 + + + Decimation_Rate + 8 + + + Zero_Pack_Factor + 1 + + + Channel_Sequence + Basic + + + Number_Channels + 1 + + + Select_Pattern + All + + + Pattern_List + P4-0,P4-1,P4-2,P4-3,P4-4 + + + Number_Paths + 2 + + + RateSpecification + Output_Sample_Period + + + HardwareOversamplingRate + 1 + + + SamplePeriod + 1 + + + Sample_Frequency + 0.001 + + + Clock_Frequency + 300.0 + + + Coefficient_Sign + Signed + + + Quantization + Integer_Coefficients + + + Coefficient_Width + 16 + + + BestPrecision + false + + + Coefficient_Fractional_Bits + 0 + + + Coefficient_Structure + Inferred + + + Data_Sign + Signed + + + Data_Width + 16 + + + Data_Fractional_Bits + 0 + + + Output_Rounding_Mode + Symmetric_Rounding_to_Zero + + + Output_Width + 16 + + + Filter_Architecture + Systolic_Multiply_Accumulate + + + Optimization_Goal + Area + + + Optimization_Selection + None + + + Data_Path_Fanout + false + + + Pre_Adder_Pipeline + false + + + Coefficient_Fanout + false + + + Control_Path_Fanout + false + + + Control_Column_Fanout + false + + + Control_Broadcast_Fanout + false + + + Control_LUT_Pipeline + false + + + No_BRAM_Read_First_Mode + false + + + Optimal_Column_Lengths + false + + + Data_Path_Broadcast + false + + + Disable_Half_Band_Centre_Tap + false + + + No_SRL_Attributes + false + + + Other + false + + + Optimization_List + None + + + Data_Buffer_Type + Automatic + + + Coefficient_Buffer_Type + Automatic + + + Input_Buffer_Type + Automatic + + + Output_Buffer_Type + Automatic + + + Preference_For_Other_Storage + Automatic + + + Multi_Column_Support + Automatic + + + Inter_Column_Pipe_Length + 4 + + + ColumnConfig + 60 + + + DATA_Has_TLAST + Not_Required + + + M_DATA_Has_TREADY + false + + + S_DATA_Has_FIFO + false + + + S_DATA_Has_TUSER + Not_Required + + + M_DATA_Has_TUSER + Not_Required + + + DATA_TUSER_Width + 1 + + + S_CONFIG_Sync_Mode + On_Vector + + + S_CONFIG_Method + Single + + + Num_Reload_Slots + 1 + + + Has_ACLKEN + false + + + Has_ARESETn + false + + + Reset_Data_Vector + true + + + Blank_Output + false + + + Gen_MIF_from_Spec + false + + + Gen_MIF_from_COE + false + + + Reload_File + no_coe_file_loaded + + + Gen_MIF_Files + false + + + DisplayReloadOrder + false + + + Passband_Min + 0.0 + + + Passband_Max + 0.5 + + + Stopband_Min + 0.5 + + + Stopband_Max + 1.0 + + + Filter_Selection + 1 + + + + + FIR Compiler + 15 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_readout_v2/src/readout_top.v b/firmware/ip/axis_readout_v2/src/readout_top.v new file mode 100644 index 0000000..a9fc32e --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/readout_top.v @@ -0,0 +1,158 @@ +module readout_top + ( + // Reset and clock. + aresetn , + aclk , + + // S1_AXIS: for input data (8x samples per clock). + s_axis_tdata , + s_axis_tvalid , + s_axis_tready , + + // M0_AXIS: for output data (before filter and decimation, 8x samples + // per clock). + m0_axis_tready , + m0_axis_tvalid , + m0_axis_tdata , + + // M1_AXIS: for output data. + m1_axis_tready , + m1_axis_tvalid , + m1_axis_tdata , + + // Registers. + FREQ_REG , + PHASE_REG , + NSAMP_REG , + OUTSEL_REG , + MODE_REG , + WE_REG + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +localparam [15:0] N_DDS = 8; + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [N_DDS*16-1:0] s_axis_tdata; + +input m0_axis_tready; +output m0_axis_tvalid; +output [N_DDS*32-1:0] m0_axis_tdata; + +input m1_axis_tready; +output m1_axis_tvalid; +output [32-1:0] m1_axis_tdata; + +input [31:0] FREQ_REG; +input [31:0] PHASE_REG; +input [15:0] NSAMP_REG; +input [1:0] OUTSEL_REG; +input MODE_REG; +input WE_REG; + +/********************/ +/* Internal signals */ +/********************/ +wire we; +reg we_r; + +wire fifo_wr_en; +wire [82:0] fifo_din; +wire fifo_rd_en; +wire [82:0] fifo_dout; +wire fifo_full; +wire fifo_empty; + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// WE_REG sync. +synchronizer_n + WE_REG_resync_i + ( + .rstn (aresetn ), + .clk (aclk ), + .data_in (WE_REG ), + .data_out (we ) + ); + +// Down-conversion + Filter + Decimation. +down_conversion_fir + down_conversion_fir_i + ( + // Reset and clock. + .rstn (aresetn ), + .clk (aclk ), + + // S_AXIS for input. + .s_axis_tready_o (s_axis_tready ), + .s_axis_tvalid_i (s_axis_tvalid ), + .s_axis_tdata_i (s_axis_tdata ), + + // M0_AXIS for output data (before filter and decimation). + .m0_axis_tready_i (m0_axis_tready ), + .m0_axis_tvalid_o (m0_axis_tvalid ), + .m0_axis_tdata_o (m0_axis_tdata ), + + // M1_AXIS for output data. + .m1_axis_tready_i (m1_axis_tready ), + .m1_axis_tvalid_o (m1_axis_tvalid ), + .m1_axis_tdata_o (m1_axis_tdata ), + + // Fifo interface. + .fifo_rd_en_o (fifo_rd_en ), + .fifo_empty_i (fifo_empty ), + .fifo_dout_i (fifo_dout ) + ); + +// Fifo for queuing waveforms. +fifo + #( + // Data width. + .B (83), + + // Fifo depth. + .N (8) + ) + fifo_i + ( + .rstn (aresetn ), + .clk (aclk ), + + // Write I/F. + .wr_en (fifo_wr_en ), + .din (fifo_din ), + + // Read I/F. + .rd_en (fifo_rd_en ), + .dout (fifo_dout ), + + // Flags. + .full (fifo_full ), + .empty (fifo_empty ) + ); + +// Fifo connections. +assign fifo_wr_en = we & ~we_r; +assign fifo_din = {MODE_REG,OUTSEL_REG,NSAMP_REG,PHASE_REG,FREQ_REG}; + +always @(posedge aclk) begin + if (~aresetn) + we_r <= 0; + else + we_r <= we; +end + +endmodule + diff --git a/firmware/ip/axis_readout_v2/src/synchronizer_n.vhd b/firmware/ip/axis_readout_v2/src/synchronizer_n.vhd new file mode 100644 index 0000000..925425d --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/synchronizer_n.vhd @@ -0,0 +1,42 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library common_lib; +use common_lib.all; + +entity synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end synchronizer_n; + +architecture rtl of synchronizer_n is + +-- Internal register. +signal data_int_reg : std_logic_vector (N-1 downto 0); + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_readout_v2/src/tb/data_iq.txt b/firmware/ip/axis_readout_v2/src/tb/data_iq.txt new file mode 100644 index 0000000..301691a --- /dev/null +++ b/firmware/ip/axis_readout_v2/src/tb/data_iq.txt @@ -0,0 +1,10000 @@ +16392,0 +3219,0 +-15142,0 +-9091,0 +11604,0 +13648,0 +-6276,0 +-16068,0 +11,0 +16054,0 +6273,0 +-13649,0 +-11616,0 +9106,0 +15132,0 +-3192,0 +-16399,0 +-3234,0 +15152,0 +9107,0 +-11593,0 +-13656,0 +6261,0 +16068,0 +-33,0 +-16070,0 +-6267,0 +13617,0 +11569,0 +-9125,0 +-15134,0 +3218,0 +16370,0 +3175,0 +-15157,0 +-9123,0 +11589,0 +13654,0 +-6280,0 +-16043,0 +-18,0 +16062,0 +6261,0 +-13626,0 +-11596,0 +9094,0 +15131,0 +-3187,0 +-16385,0 +-3199,0 +15154,0 +9090,0 +-11588,0 +-13611,0 +6289,0 +16084,0 +14,0 +-16091,0 +-6292,0 +13607,0 +11584,0 +-9127,0 +-15153,0 +3189,0 +16375,0 +3200,0 +-15147,0 +-9130,0 +11565,0 +13630,0 +-6269,0 +-16083,0 +-9,0 +16060,0 +6282,0 +-13591,0 +-11583,0 +9095,0 +15149,0 +-3194,0 +-16377,0 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s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +// s_axis interfase. +wire s_axis_tready; +reg s_axis_tvalid; +reg [N_DDS*16-1:0] s_axis_tdata; + +// m0_axis interfase. +reg m0_axis_tready; +wire m0_axis_tvalid; +reg [N_DDS*32-1:0] m0_axis_tdata; + +// m1_axis interfase. +reg m1_axis_tready; +wire m1_axis_tvalid; +reg [32-1:0] m1_axis_tdata; + +// Assignment of data out for debugging. +wire [31:0] dout_ii [0:N_DDS-1]; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Test bench control. +reg tb_data_in = 0; +reg tb_data_in_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m0_axis_tdata[32*ii +: 32]; +end +endgenerate + +// axi_mst_0. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_readout_v2 + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // s_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS: for input data (8x samples per clock). + .s_axis_tdata (s_axis_tdata ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tready (s_axis_tready ), + + // M0_AXIS: for output data (before filter and decimation, 8x samples + // per clock). + .m0_axis_tready (m0_axis_tready ), + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + + // M1_AXIS: for output data. + .m1_axis_tready (m1_axis_tready ), + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tdata (m1_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + m0_axis_tready <= 1; + m1_axis_tready <= 1; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("###############################"); + $display("### Start Recording Outputs ###"); + $display("###############################"); + $display("t = %0t", $time); + + tb_write_out <= 1; + + + $display("###################"); + $display("### Program DDS ###"); + $display("###################"); + $display("t = %0t", $time); + + // FREQ. + data_wr = freq_calc(100, N_DDS, 5); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); + #10; + + // PHASE. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(1*4, prot, data_wr, resp); + #10; + + // NSAMP. + data_wr = 10; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(2*4, prot, data_wr, resp); + #10; + + // OUTSEL : 0 (product), 1 (dds), 2 (input). + data_wr = 2; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(3*4, prot, data_wr, resp); + #10; + + // MODE : 1 (periodic). + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); + #10; + + // WE. + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); + #10; + + #100; + + // WE. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); + #10; + + #10000; + + //// FREQ. + //data_wr = freq_calc(100, N_DDS, 17); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); + //#10; + + //// WE. + //data_wr = 1; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); + //#10; + + //#100; + + //// WE. + //data_wr = 0; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); + //#10; + + //#8484; + + //// FREQ. + //data_wr = freq_calc(100, N_DDS, 5); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(0*4, prot, data_wr, resp); + //#10; + + //// WE. + //data_wr = 1; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(5*4, prot, data_wr, resp); + //#10; + + #100; + + #888; + + $display("#######################"); + $display("### Send Input Data ###"); + $display("#######################"); + $display("t = %0t", $time); + tb_data_in <= 1; + + wait (tb_data_in_done); + + #1000; + + $display("##############################"); + $display("### Stop Recording Outputs ###"); + $display("##############################"); + $display("t = %0t", $time); + tb_write_out <= 0; + + #20000; + +end + +// Input data. +initial begin + int fd, i; + bit signed [15:0] vali, valq; + + tb_data_in_done <= 0; + s_axis_tvalid <= 1; + s_axis_tdata <= 0; + + wait (tb_data_in); + + #1000; + + // Open file with input data. + // Format: I, Q. + `ifdef SYNTH_SIMU + fd = $fopen("../../../../../../tb/data_iq.txt","r"); + `else + fd = $fopen("../../../../../tb/data_iq.txt","r"); + `endif + + //i = N_DDS; + i = 0; + while ($fscanf(fd,"%d,%d", vali, valq) == 2) begin + $display("Time %t: Line %d, I = %d, Q = %d", $time, i, vali, valq); + //s_axis_tdata_i[(i-1)*16 +: 16] <= vali; + s_axis_tdata[i*16 +: 16] <= vali; + //i = i - 1; + i = i + 1; + //if ( i == 0) begin + if ( i == N_DDS) begin + //i = N_DDS; + i = 0; + @(posedge aclk); + end + end + + #1000; + + @(posedge aclk); + tb_data_in_done <= 1; + +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d, imag_d; + + // Output file. + `ifdef SYNTH_SIMU + fd = $fopen("../../../../../../tb/dout_fs.csv","w"); + `else + fd = $fopen("../../../../../tb/dout_fs.csv","w"); + `endif + + // Data format. + $fdisplay(fd, "valid, idx, real, imag"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i + + user.org + user + axis_readout_v3 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s0_axis + + + + + + + TDATA + + + s0_axis_tdata + + + + + TVALID + + + s0_axis_tvalid + + + + + TREADY + + + s0_axis_tready + + + + + + s1_axis + + + + + + + TDATA + + + s1_axis_tdata + + + + + TVALID + + + s1_axis_tvalid + + + + + TREADY + + + s1_axis_tready + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s0_axis:s1_axis + + + ASSOCIATED_RESET + aresetn + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_readout_v3 + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 6ef85b24 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_readout_v3 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 6ef85b24 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f92e9879 + + + + + + + aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_tready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_tvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_tdata + + in + + 87 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s1_axis_tready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_axis_tvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_axis_tdata + + in + + 63 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/fir_0/fir.coe + coe + + + src/fir_0/fir_0/fir_0.xci + xci + CELL_NAME_down_conversion_fir_i/fir_0_i/fir_0 + + + src/dds_0/dds_0/dds_0.xci + xci + CELL_NAME_down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/dds_0 + + + src/latency_reg.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/down_conversion.sv + systemVerilogSource + + + src/down_conversion_fir.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/axis_readout_v3.v + verilogSource + CHECKSUM_ff9d9536 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/fir_0/fir.coe + coe + + + src/fir_0/fir_0/fir_0.xci + xci + CELL_NAME_down_conversion_fir_i/fir_0_i/fir_0 + + + src/dds_0/dds_0/dds_0.xci + xci + CELL_NAME_down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/dds_0 + + + src/latency_reg.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/down_conversion.sv + systemVerilogSource + + + src/down_conversion_fir.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/axis_readout_v3.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_readout_v3_v1_0.tcl + tclSource + CHECKSUM_f92e9879 + XGUI_VERSION_2 + + + + AXIS Readout V3 block with DDC (32-bit, phase coherent), filtering and 4x decimation, tProc controlled. + + + Component_Name + axis_readout_v3_v1_0 + + + + + + zynquplus + + + /UserIP + + AXIS Readout V3 + package_project + 4 + 2022-09-30T20:19:36Z + + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + /home/lstefana/v20.2/ip/axis_readout_v3 + + + + 2020.2 + + + + + + + diff --git a/firmware/ip/axis_readout_v3/src/axis_readout_v3.v b/firmware/ip/axis_readout_v3/src/axis_readout_v3.v new file mode 100644 index 0000000..0f8f84a --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/axis_readout_v3.v @@ -0,0 +1,98 @@ +module axis_readout_v3 + ( + // Reset and clock. + input wire aresetn , + input wire aclk , + + // s0_axis for pushing waveforms. + output wire s0_axis_tready , + input wire s0_axis_tvalid , + input wire [87:0] s0_axis_tdata , + + // s1_axis for input data (4 real samples per clock). + output wire s1_axis_tready , + input wire s1_axis_tvalid , + input wire [4*16-1:0] s1_axis_tdata , + + // m_axis for output data (1 complex sample per clock). + input wire m_axis_tready , + output wire m_axis_tvalid , + output wire [31:0] m_axis_tdata + ); + +/********************/ +/* Internal Signals */ +/********************/ + +// Fifo. +wire fifo_wr_en ; +wire [87:0] fifo_din ; +wire fifo_rd_en ; +wire [87:0] fifo_dout ; +wire fifo_full ; +wire fifo_empty ; + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// Fifo for queuing waveforms. +fifo + #( + // Data width. + .B (88), + + // Fifo depth. + .N (8) + ) + fifo_i + ( + .rstn (aresetn ), + .clk (aclk ), + + // Write I/F. + .wr_en (fifo_wr_en ), + .din (fifo_din ), + + // Read I/F. + .rd_en (fifo_rd_en ), + .dout (fifo_dout ), + + // Flags. + .full (fifo_full ), + .empty (fifo_empty ) + ); + +// Fifo connections. +assign fifo_wr_en = s0_axis_tvalid; +assign fifo_din = s0_axis_tdata; + +// Down-conversion + Decimation FIR. +down_conversion_fir + down_conversion_fir_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // Fifo interface. + .fifo_rd_en (fifo_rd_en ), + .fifo_empty (fifo_empty ), + .fifo_dout (fifo_dout ), + + // s_axis for input data (N samples per clock). + .s_axis_tready (s1_axis_tready ), + .s_axis_tvalid (s1_axis_tvalid ), + .s_axis_tdata (s1_axis_tdata ), + + // m_axis for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// Assign outputs. +assign s0_axis_tready = ~fifo_full; + +endmodule + diff --git a/firmware/ip/axis_readout_v3/src/ctrl.sv b/firmware/ip/axis_readout_v3/src/ctrl.sv new file mode 100644 index 0000000..7bc0714 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/ctrl.sv @@ -0,0 +1,377 @@ +//Format of waveform interface: +// |----------|-------|------|----------|----------|----------|---------| +// | 87 .. 84 | 83 | 82 | 81 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | +// |----------|-------|------|----------|----------|----------|---------| +// | xxxx | phrst | mode | outsel | nsamp | phase | freq | +// |----------|-------|------|----------|----------|----------|---------| +// freq : 32 bits +// phase : 32 bits +// nsamp : 16 bits +// outsel : 2 bits +// mode : 1 bit +// phrst : 1 bit +module ctrl + #( + parameter N = 4 + ) + ( + // Reset and clock. + input wire aresetn , + input wire aclk , + + // Fifo interface. + output wire fifo_rd_en , + input wire fifo_empty , + input wire [87:0] fifo_dout , + + // dds control. + output wire [N*72-1:0] dds_ctrl , + + // Output source selection. + output wire [1:0] outsel , + + // Output enable. + output wire en + ); + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// Fifo dout register. +reg [87:0] fifo_dout_r; + +// Non-stop counter for time calculation (adds N samples each clock tick). +reg [31:0] cnt_n; +reg [31:0] cnt_n_reg; + +// Pinc/phase. +wire [31:0] pinc_int; +reg [31:0] pinc_r1; +reg [31:0] pinc_r2; +wire [31:0] pinc_N; +reg [31:0] pinc_N_r1; +reg [31:0] pinc_N_r2; +reg [31:0] pinc_N_r3; +reg [31:0] pinc_N_r4; +reg [31:0] pinc_N_r5; +wire [31:0] pinc_Nm; +reg [31:0] pinc_Nm_r1; +reg [31:0] pinc_Nm_r2; +reg [31:0] pinc_Nm_r3; + +wire [31:0] phase_int; +reg [31:0] phase_r1; +reg [31:0] phase_r2; +reg [31:0] phase_r3; +reg [31:0] phase_r4; +reg [31:0] phase_r5; +wire [31:0] phase_0; +reg [31:0] phase_0_r1; + +// Phase vectors. +wire [31:0] phase_v0 [N]; +reg [31:0] phase_v0_r1 [N]; +reg [31:0] phase_v0_r2 [N]; +reg [31:0] phase_v0_r3 [N]; +reg [31:0] phase_v0_r4 [N]; +wire [31:0] phase_v1 [N]; +reg [31:0] phase_v1_r1 [N]; + +// sync. +reg sync_reg; +reg sync_reg_r1; +reg sync_reg_r2; +reg sync_reg_r3; +reg sync_reg_r4; +reg sync_reg_r5; +reg sync_reg_r6; +reg sync_reg_r7; + +// Number of samples. +wire [15:0] nsamp_int; + +// Output selection. +wire [1:0] outsel_int; +reg [1:0] outsel_r1; +reg [1:0] outsel_r2; +reg [1:0] outsel_r3; +reg [1:0] outsel_r4; +reg [1:0] outsel_r5; +reg [1:0] outsel_r6; +reg [1:0] outsel_r7; + +// Mode. +wire mode_int; + +// Phase reset. +wire phrst_int; + +// Load enable flag. +wire load_int; +reg load_r; + +// Fifo Read Enable. +reg rd_en_int; +reg rd_en_r1; +reg rd_en_r2; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +reg en_reg_r1; +reg en_reg_r2; +reg en_reg_r3; +reg en_reg_r4; +reg en_reg_r5; +reg en_reg_r6; +reg en_reg_r7; +reg en_reg_r8; + +// Registers. +always @(posedge aclk) begin + if (~aresetn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Non-stop counter for time calculation. + cnt_n <= 0; + cnt_n_reg <= 0; + + // Pinc/phase/sync. + pinc_r1 <= 0; + pinc_r2 <= 0; + pinc_N_r1 <= 0; + pinc_N_r2 <= 0; + pinc_N_r3 <= 0; + pinc_N_r4 <= 0; + pinc_N_r5 <= 0; + pinc_Nm_r1 <= 0; + pinc_Nm_r2 <= 0; + pinc_Nm_r3 <= 0; + + phase_r1 <= 0; + phase_r2 <= 0; + phase_r3 <= 0; + phase_r4 <= 0; + phase_r5 <= 0; + phase_0_r1 <= 0; + + sync_reg <= 0; + sync_reg_r1 <= 0; + sync_reg_r2 <= 0; + sync_reg_r3 <= 0; + sync_reg_r4 <= 0; + sync_reg_r5 <= 0; + sync_reg_r6 <= 0; + sync_reg_r7 <= 0; + + // Output selection. + outsel_r1 <= 0; + outsel_r2 <= 0; + outsel_r3 <= 0; + outsel_r4 <= 0; + outsel_r5 <= 0; + outsel_r6 <= 0; + outsel_r7 <= 0; + + // Load enable flag. + load_r <= 0; + + // Fifo Read Enable. + rd_en_r1 <= 0; + rd_en_r2 <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + en_reg_r1 <= 0; + en_reg_r2 <= 0; + en_reg_r3 <= 0; + en_reg_r4 <= 0; + en_reg_r5 <= 0; + en_reg_r6 <= 0; + en_reg_r7 <= 0; + en_reg_r8 <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (mode_int || ~fifo_empty) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout; + + // Non-stop counter for time calculation. + if (sync_reg == 1'b1 && phrst_int == 1'b1) + cnt_n <= 0; + else + cnt_n <= cnt_n + N; + + if (sync_reg_r1 == 1'b1) + cnt_n_reg <= cnt_n; + + // Pinc/phase/sync. + pinc_r1 <= pinc_int; + pinc_r2 <= pinc_r1; + pinc_N_r1 <= pinc_N; + pinc_N_r2 <= pinc_N_r1; + pinc_N_r3 <= pinc_N_r2; + pinc_N_r4 <= pinc_N_r3; + pinc_N_r5 <= pinc_N_r4; + pinc_Nm_r1 <= pinc_Nm; + pinc_Nm_r2 <= pinc_Nm_r1; + pinc_Nm_r3 <= pinc_Nm_r2; + + phase_r1 <= phase_int; + phase_r2 <= phase_r1; + phase_r3 <= phase_r2; + phase_r4 <= phase_r3; + phase_r5 <= phase_r4; + phase_0_r1 <= phase_0; + + sync_reg <= load_r; + sync_reg_r1 <= sync_reg; + sync_reg_r2 <= sync_reg_r1; + sync_reg_r3 <= sync_reg_r2; + sync_reg_r4 <= sync_reg_r3; + sync_reg_r5 <= sync_reg_r4; + sync_reg_r6 <= sync_reg_r5; + sync_reg_r7 <= sync_reg_r6; + + // Output selection. + outsel_r1 <= outsel_int; + outsel_r2 <= outsel_r1; + outsel_r3 <= outsel_r2; + outsel_r4 <= outsel_r3; + outsel_r5 <= outsel_r4; + outsel_r6 <= outsel_r5; + outsel_r7 <= outsel_r6; + + // Load enable flag. + load_r <= load_int; + + // Fifo Read Enable. + rd_en_r1 <= rd_en_int; + rd_en_r2 <= rd_en_r1; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (~mode_int && rd_en_int) + if (~fifo_empty) + en_reg <= 1; + else + en_reg <= 0; + + en_reg_r1 <= en_reg; + en_reg_r2 <= en_reg_r1; + en_reg_r3 <= en_reg_r2; + en_reg_r4 <= en_reg_r3; + en_reg_r5 <= en_reg_r4; + en_reg_r6 <= en_reg_r5; + en_reg_r7 <= en_reg_r6; + en_reg_r8 <= en_reg_r7; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign pinc_int = fifo_dout_r[31:0]; +assign phase_int = fifo_dout_r[63:32]; +assign nsamp_int = fifo_dout_r[79:64]; +assign outsel_int = fifo_dout_r[81:80]; +assign mode_int = fifo_dout_r[82]; +assign phrst_int = fifo_dout_r[83]; + +// Frequency calculation. +assign pinc_N = pinc_r2*N; + +// Phase calculation. +assign pinc_Nm = pinc_r2*cnt_n_reg; +assign phase_0 = pinc_Nm_r3 + phase_r5; + +// Phase vectors. +generate +genvar i; + for (i=0; i < N; i = i + 1) begin : GEN_phase + // Registers. + always @(posedge aclk) begin + if (~aresetn) begin + // v0. + phase_v0_r1[i] <= 0; + phase_v0_r2[i] <= 0; + phase_v0_r3[i] <= 0; + phase_v0_r4[i] <= 0; + + // v1. + phase_v1_r1[i] <= 0; + end + else begin + // v0. + phase_v0_r1[i] <= phase_v0[i]; + phase_v0_r2[i] <= phase_v0_r1[i]; + phase_v0_r3[i] <= phase_v0_r2[i]; + phase_v0_r4[i] <= phase_v0_r3[i]; + + // v1. + phase_v1_r1[i] <= phase_v1[i]; + end + end + + // v0. + assign phase_v0[i] = pinc_r2*i; + + // v1. + assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; + + // dds_ctrl_o output. + assign dds_ctrl[i*72 +: 72] = {7'h00,sync_reg_r7,phase_v1_r1[i],pinc_N_r5}; + end +endgenerate + +// load_int. +assign load_int = rd_en_int & ~fifo_empty; + +// Assign outputs. +assign fifo_rd_en = rd_en_int; +assign outsel = outsel_r7; +assign en = en_reg_r8; + +endmodule + diff --git a/firmware/ip/axis_readout_v3/src/dds_0/dds_0/dds_0.xci b/firmware/ip/axis_readout_v3/src/dds_0/dds_0/dds_0.xci new file mode 100644 index 0000000..a994dc7 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/dds_0/dds_0/dds_0.xci @@ -0,0 +1,312 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 9 + 0 + 0 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 10 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 72 + 1 + 0 + zynquplus + Full_Range + 1 + dds_0 + Not_Required + 256 + Minimal + 0.06 + Coregen + false + false + false + false + 10 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + false + Auto + Twos_Complement + Auto + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 20 + TRUE + ../../../../../test_phase/top/top.tmp/axis_readout_v3_v1_0_project/axis_readout_v3_v1_0_project.gen/sources_1/ip/dds_0 + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_readout_v3/src/down_conversion.sv b/firmware/ip/axis_readout_v3/src/down_conversion.sv new file mode 100644 index 0000000..cfd80fb --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/down_conversion.sv @@ -0,0 +1,290 @@ +/* + * This block performs product between input data and dds. + * input tvalid is not taken into account. + * output tready is not taken into account. + */ +module down_conversion + #( + parameter N = 4 + ) + ( + // Reset and clock. + input wire aresetn , + input wire aclk , + + // Fifo interface. + output wire fifo_rd_en , + input wire fifo_empty , + input wire [87:0] fifo_dout , + + // s_axis for input data (N samples per clock). + output wire s_axis_tready , + input wire s_axis_tvalid , + input wire [N*16-1:0] s_axis_tdata , + + // m_axis for output data. + input wire m_axis_tready , + output wire m_axis_tvalid , + output wire [N*32-1:0] m_axis_tdata + ); + +/********************/ +/* Internal signals */ +/********************/ +// Input data. +reg [15:0] din_real_r1 [N] ; +wire [15:0] din_real_la [N] ; +wire [15:0] din_la_mux [N] ; + +// DDS input control. +reg dds_tvalid_r ; +wire [N*72-1:0] dds_ctrl_int ; +reg [N*72-1:0] dds_ctrl_int_r ; + +// DDS output. +wire [31:0] dds_dout [N] ; +reg [31:0] dds_dout_r1 [N] ; +wire [31:0] dds_dout_la [N] ; +wire [31:0] dds_la_mux [N] ; + +// Product. +wire signed [15:0] prod_a_real [N] ; +wire signed [15:0] prod_b_real [N] ; +wire signed [15:0] prod_b_imag [N] ; +wire signed [31:0] prod_y_real [N] ; +wire signed [31:0] prod_y_imag [N] ; +wire signed [15:0] prod_y_real_round [N] ; +wire signed [15:0] prod_y_imag_round [N] ; +wire [31:0] prod_y [N] ; +reg [31:0] prod_y_r1 [N] ; +reg [31:0] prod_y_r2 [N] ; + +// Muxed output. +wire [31:0] dout_mux [N] ; +reg [31:0] dout_mux_r1 [N] ; + +// Output source selection. +wire [1:0] outsel_int ; +wire [1:0] outsel_la ; + +// Output enable. +wire en_int ; +wire en_la ; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Control block. +ctrl + #( + .N(N) + ) + ctrl_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // Fifo interface. + .fifo_rd_en (fifo_rd_en ), + .fifo_empty (fifo_empty ), + .fifo_dout (fifo_dout ), + + // dds control. + .dds_ctrl (dds_ctrl_int ), + + // Output source selection. + .outsel (outsel_int ), + + // Output enable. + .en (en_int ) + ); + +generate +genvar i; + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_readout_v3/src/fifo/fifo_axi.vhd b/firmware/ip/axis_readout_v3/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_readout_v3/src/fifo/fifo_dc.vhd b/firmware/ip/axis_readout_v3/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_readout_v3/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_readout_v3/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_readout_v3/src/fifo/gray2bin.vhd b/firmware/ip/axis_readout_v3/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_readout_v3/src/fifo/rd2axi.vhd b/firmware/ip/axis_readout_v3/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_readout_v3/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_readout_v3/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_readout_v3/src/fir_0/fir.coe b/firmware/ip/axis_readout_v3/src/fir_0/fir.coe new file mode 100644 index 0000000..26bffb3 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fir_0/fir.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = -19,178,379,653,910,1053,997,719,273,-208,-558,-646,-438,-19,424,684,623,247,-287,-726,-844,-547,58,700,1059,922,301,-547,-1218,-1351,-811,213,1262,1803,1492,367,-1114,-2244,-2387,-1307,651,2636,3623,2887,414,-2944,-5678,-6144,-3225,3142,11784,20585,27137,29559,27137,20585,11784,3142,-3225,-6144,-5678,-2944,414,2887,3623,2636,651,-1307,-2387,-2244,-1114,367,1492,1803,1262,213,-811,-1351,-1218,-547,301,922,1059,700,58,-547,-844,-726,-287,247,623,684,424,-19,-438,-646,-558,-208,273,719,997,1053,910,653,379,178,-19 \ No newline at end of file diff --git a/firmware/ip/axis_readout_v3/src/fir_0/fir_0.v b/firmware/ip/axis_readout_v3/src/fir_0/fir_0.v new file mode 100644 index 0000000..9c50b5e --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fir_0/fir_0.v @@ -0,0 +1,13 @@ +module fir_0 + ( + input wire aclk , + input wire s_axis_data_tvalid , + output wire s_axis_data_tready , + input wire [127:0] s_axis_data_tdata , + output wire m_axis_data_tvalid , + output wire [31:0] m_axis_data_tdata + ); + +assign s_axis_data_tready = 1'b1; +assign m_axis_data_tvalid = 1'b1; +assign m_axis_data_tdata = s_axis_data_tdata[0 +: 16]; diff --git a/firmware/ip/axis_readout_v3/src/fir_0/fir_0.veo b/firmware/ip/axis_readout_v3/src/fir_0/fir_0.veo new file mode 100644 index 0000000..00695f6 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fir_0/fir_0.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fir_compiler:7.2 +// IP Revision: 15 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fir_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready + .s_axis_data_tdata(s_axis_data_tdata), // input wire [127 : 0] s_axis_data_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fir_0.v when simulating +// the core, fir_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_readout_v3/src/fir_0/fir_0/fir_0.xci b/firmware/ip/axis_readout_v3/src/fir_0/fir_0/fir_0.xci new file mode 100644 index 0000000..fc04e11 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/fir_0/fir_0/fir_0.xci @@ -0,0 +1,320 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 6 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 16 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 35,35 + 35,35,35,35,35,35,35,35 + fixed + fir_0.mif + 54 + 2 + 0 + 0,0,0,0,0,0,0,0 + 0,0,0,0,0,0,0,0 + 16,16,16,16,16,16,16,16 + 0 + 16 + 54 + 1 + 4 + fir_0 + 0 + 0 + 1 + 2 + 0 + 16,16,16,16,16,16,16,16 + 0 + 0 + -0,2,4,6;-1,3,5,7;0,-2,4,6;1,-3,5,7;0,2,-4,6;1,3,-5,7;0,2,4,-6;1,3,5,-7 + 0,0,0,0,0,0,0,0 + 0,1,2,3,4,5,6,7 + 16,16,16,16,16,16,16,16 + 16,16,16,16,16,16,16,16 + 16 + 1 + ./ + none + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 2 + 61 + 1 + 0 + 0 + 48 + 1 + 1 + 1 + 54 + 1 + 107 + 0 + 0 + none + 0,2,4,-6;1,3,5,-7 + 18,18 + 1 + 18 + 1 + 6,7,6,7,6,7,6,7 + 1 + 2 + 1 + 1 + 0 + 128 + 1 + zynquplus + 1 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + ../fir.coe + 0 + false + 1 + Signed + Inferred + 16 + 54 + fir_0 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 4 + false + false + Systolic_Multiply_Accumulate + 1 + Decimation + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 1 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Zero + 18 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Integer_Coefficients + Output_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../../test_phase/top/top.tmp/axis_readout_v3_v1_0_project/axis_readout_v3_v1_0_project.gen/sources_1/ip/fir_0 + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_readout_v3/src/latency_reg.v b/firmware/ip/axis_readout_v3/src/latency_reg.v new file mode 100644 index 0000000..687a9f3 --- /dev/null +++ b/firmware/ip/axis_readout_v3/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i + + user.org + user + axis_register_slice_nb + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + axis_register_slice_nb + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 71ea944a + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + axis_register_slice_nb + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 71ea944a + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 2c3a0701 + + + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + + + B + B + 16 + + + N + N + 4 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/axis_register_slice_nb.vhd + vhdlSource + CHECKSUM_71ea944a + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/axis_register_slice_nb.vhd + vhdlSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_register_slice_nb_v1_0.tcl + tclSource + CHECKSUM_2c3a0701 + XGUI_VERSION_2 + + + + AXIS Register Slice Non-Blocking. + + + B + B + 16 + + + N + N + 4 + + + Component_Name + axis_register_slice_nb_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + kintexu + + + /UserIP + + AXIS Register Slice Non-Blocking + package_project + 2 + 2022-04-11T15:56:34Z + + /home/lstefana/v20.2/ip/axis_register_slice_nb + /home/lstefana/v20.2/ip/axis_register_slice_nb + /home/lstefana/v20.2/ip/axis_register_slice_nb + /home/lstefana/v20.2/ip/axis_register_slice_nb + /home/lstefana/v20.2/ip/axis_register_slice_nb + /home/lstefana/v20.2/ip/axis_register_slice_nb + /home/lstefana/v20.2/ip/axis_register_slice_nb + /home/lstefana/v20.2/ip/axis_register_slice_nb + /home/lstefana/v20.2/ip/axis_register_slice_nb + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_register_slice_nb/src/axis_register_slice_nb.vhd b/firmware/ip/axis_register_slice_nb/src/axis_register_slice_nb.vhd new file mode 100644 index 0000000..14fdb50 --- /dev/null +++ b/firmware/ip/axis_register_slice_nb/src/axis_register_slice_nb.vhd @@ -0,0 +1,61 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; + +entity axis_register_slice_nb is + Generic + ( + -- Number of bits. + B : Integer := 16; + + -- Delay. + N : Integer := 4 + ); + Port + ( + -- Reset and clock. + aclk : in std_logic; + aresetn : in std_logic; + + -- AXIS Slave I/F. + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + s_axis_tready : out std_logic; + + -- AXIS Master I/F. + m_axis_tdata : out std_logic_vector(B-1 downto 0); + m_axis_tvalid : out std_logic; + m_axis_tready : in std_logic + ); +end axis_register_slice_nb; + +architecture rtl of axis_register_slice_nb is + +-- Shift register for data. +type reg_v is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal shift_reg_tdata : reg_v; + +begin + +-- Registers. +process (aclk) +begin + if ( rising_edge(aclk) ) then + if ( aresetn = '0' ) then + -- Shift registers. + shift_reg_tdata <= (others => (others => '0')); + else + shift_reg_tdata <= shift_reg_tdata (N-2 downto 0) & s_axis_tdata; + end if; + end if; +end process; + +-- Assign outputs. +s_axis_tready <= '1'; + +m_axis_tdata <= shift_reg_tdata (N-1); +m_axis_tvalid <= '1'; + +end rtl; + diff --git a/firmware/ip/axis_register_slice_nb/src/tb.vhd b/firmware/ip/axis_register_slice_nb/src/tb.vhd new file mode 100644 index 0000000..cd3763f --- /dev/null +++ b/firmware/ip/axis_register_slice_nb/src/tb.vhd @@ -0,0 +1,142 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity tb is +end tb; + +architecture rtl of tb is + +constant B : Integer := 8; +constant N : Integer := 3; + +-- DUT. +component axis_register_slice_nb is + Generic + ( + -- Number of bits. + B : Integer := 16; + + -- Delay. + N : Integer := 4 + ); + Port + ( + -- Reset and clock. + aclk : in std_logic; + aresetn : in std_logic; + + -- AXIS Slave I/F. + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + s_axis_tready : out std_logic; + + -- AXIS Master I/F. + m_axis_tdata : out std_logic_vector(B-1 downto 0); + m_axis_tvalid : out std_logic; + m_axis_tready : in std_logic + ); +end component; + +-- Reset and clock. +signal aclk : std_logic; +signal aresetn : std_logic; + +-- AXIS Slave I/F. +signal s_axis_tdata : std_logic_vector(B-1 downto 0); +signal s_axis_tvalid : std_logic; +signal s_axis_tready : std_logic; + +-- AXIS Master I/F. +signal m_axis_tdata : std_logic_vector(B-1 downto 0); +signal m_axis_tvalid : std_logic; +signal m_axis_tready : std_logic; + +begin + +-- DUT. +DUT: axis_register_slice_nb + Generic map + ( + -- Number of bits. + B => B , + + -- Delay. + N => N + ) + Port map + ( + -- Reset and clock. + aclk => aclk , + aresetn => aresetn , + + -- AXIS Slave I/F. + s_axis_tdata => s_axis_tdata , + s_axis_tvalid => s_axis_tvalid , + s_axis_tready => s_axis_tready , + + -- AXIS Master I/F. + m_axis_tdata => m_axis_tdata , + m_axis_tvalid => m_axis_tvalid , + m_axis_tready => m_axis_tready + ); + +-- Main TB. +process +begin + aresetn <= '0'; + wait for 300 ns; + aresetn <= '1'; + + wait until rising_edge(aclk); + s_axis_tdata <= std_logic_vector(to_unsigned(23,s_axis_tdata'length)); + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tdata <= std_logic_vector(to_unsigned(54,s_axis_tdata'length)); + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tdata <= std_logic_vector(to_unsigned(3,s_axis_tdata'length)); + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tdata <= std_logic_vector(to_unsigned(99,s_axis_tdata'length)); + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tdata <= std_logic_vector(to_unsigned(23,s_axis_tdata'length)); + s_axis_tvalid <= '0'; + + wait until rising_edge(aclk); + wait until rising_edge(aclk); + wait until rising_edge(aclk); + + wait until rising_edge(aclk); + s_axis_tdata <= std_logic_vector(to_unsigned(38,s_axis_tdata'length)); + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tdata <= std_logic_vector(to_unsigned(3,s_axis_tdata'length)); + s_axis_tvalid <= '1'; + + wait until rising_edge(aclk); + s_axis_tdata <= std_logic_vector(to_unsigned(99,s_axis_tdata'length)); + s_axis_tvalid <= '1'; +end process; + +-- Clock. +process +begin + aclk <= '0'; + wait for 5 ns; + aclk <= '1'; + wait for 5 ns; +end process; + + +end rtl; + diff --git a/firmware/ip/axis_register_slice_nb/xgui/axis_register_slice_nb_v1_0.tcl b/firmware/ip/axis_register_slice_nb/xgui/axis_register_slice_nb_v1_0.tcl new file mode 100644 index 0000000..1717489 --- /dev/null +++ b/firmware/ip/axis_register_slice_nb/xgui/axis_register_slice_nb_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "B" -parent ${Page_0} + ipgui::add_param $IPINST -name "N" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to update B when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to validate B + return true +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + + +proc update_MODELPARAM_VALUE.B { MODELPARAM_VALUE.B PARAM_VALUE.B } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.B}] ${MODELPARAM_VALUE.B} +} + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + diff --git a/firmware/ip/axis_reorder_iq_v1/component.xml b/firmware/ip/axis_reorder_iq_v1/component.xml new file mode 100644 index 0000000..cded718 --- /dev/null +++ b/firmware/ip/axis_reorder_iq_v1/component.xml @@ -0,0 +1,409 @@ + + + user.org + user + axis_reorder_iq_v1 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axis_reorder_iq_v1 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + c6b7ae6a + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axis_reorder_iq_v1 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + c6b7ae6a + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 38cf361c + + + + + + + aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 127 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axis_tvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 127 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + + + B + B + 16 + + + L + L + 4 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/axis_reorder_iq_v1.sv + systemVerilogSource + CHECKSUM_c6b7ae6a + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/axis_reorder_iq_v1.sv + systemVerilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_reorder_iq_v1_v1_0.tcl + tclSource + CHECKSUM_38cf361c + XGUI_VERSION_2 + + + + AXIS Reorder IQ, output interleaved, V1. + + + B + B + 16 + + + L + L + 4 + + + Component_Name + axis_reorder_iq_v1_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + kintexu + + + /UserIP + + AXIS Reorder IQ V1 + package_project + 3 + 2023-02-27T15:39:16Z + + /home/lstefana/v20.2/zcu111/mkids_4x4096_v1/ip/axis_reorder_iq_v1 + /home/lstefana/v20.2/zcu111/mkids_4x4096_v1/ip/axis_reorder_iq_v1 + /home/lstefana/v20.2/zcu111/mkids_4x4096_v1/ip/axis_reorder_iq_v1 + /home/lstefana/v20.2/zcu111/mkids_4x4096_v1/ip/axis_reorder_iq_v1 + /home/lstefana/v20.2/zcu111/mkids_4x4096_v1/ip/axis_reorder_iq_v1 + /home/lstefana/v20.2/zcu111/mkids_4x4096_v1/ip/axis_reorder_iq_v1 + /home/lstefana/v20.2/zcu111/mkids_4x4096_v1/ip/axis_reorder_iq_v1 + /home/lstefana/v20.2/zcu111/mkids_4x4096_v1/ip/axis_reorder_iq_v1 + /home/lstefana/v20.2/zcu111/mkids_4x4096_v1/ip/axis_reorder_iq_v1 + + + + 2022.1 + + + + + + + + diff --git a/firmware/ip/axis_reorder_iq_v1/src/axis_reorder_iq_v1.sv b/firmware/ip/axis_reorder_iq_v1/src/axis_reorder_iq_v1.sv new file mode 100644 index 0000000..5b9ec35 --- /dev/null +++ b/firmware/ip/axis_reorder_iq_v1/src/axis_reorder_iq_v1.sv @@ -0,0 +1,70 @@ +// This block reorders the data to format it for PFB. +// Input is formatted as follows: +// +// Q[L-1] ... Q[2] Q[1] Q[0] I[L-1] .. I[2] I[1] I[0] +// +// where Q[k],I[k] are B bits. Output is reordered to +// interleave the values as follows: +// +// Q[L-1] I[L-1] .. Q[2] I[2] Q[1] I[1] Q[0] I[0] +// +module axis_reorder_iq_v1 + #( + // Number of bits. + parameter B = 16 , + + // Number of lanes. + parameter L = 4 + ) + ( + // s_* and m_* reset/clock. + input wire aresetn , + input wire aclk , + + // S_AXIS for data input. + input wire [2*B*L-1:0] s_axis_tdata , + input wire s_axis_tvalid , + output wire s_axis_tready , + + // M_AXIS for data output. + output wire [2*B*L-1:0] m_axis_tdata , + output wire m_axis_tvalid , + input wire m_axis_tready + ); + +/********************/ +/* Internal signals */ +/********************/ +// I/Q sections. +wire [B*L-1:0] data_i; +wire [B*L-1:0] data_q; + +// I/Q vectors. +wire [B-1:0] data_iv [L]; +wire [B-1:0] data_qv [L]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// I/Q sectiions. +assign data_i = s_axis_tdata[0 +: B*L]; +assign data_q = s_axis_tdata[B*L +: B*L]; + +genvar i; +generate + for (i=0; i + + user.org + user + axis_resampler_2x1_v1 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axis_resampler_2x1_v1 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 2f191ebf + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axis_resampler_2x1_v1 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 2f191ebf + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 2c3a0701 + + + + + + + aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 127 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 63 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + B + B + 16 + + + N + N + 8 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/axis_resampler_2x1_v1.sv + systemVerilogSource + CHECKSUM_2f191ebf + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/axis_resampler_2x1_v1.sv + systemVerilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_resampler_2x1_v1_v1_0.tcl + tclSource + CHECKSUM_2c3a0701 + XGUI_VERSION_2 + + + + AXIS Resampler 2x1 V1 + + + B + B + 16 + + + N + N + 8 + + + Component_Name + axis_resampler_2x1_v1_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + kintexu + + + /UserIP + + AXIS Resampler 2x1 V1 + package_project + 3 + 2022-09-30T20:20:16Z + + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + /home/lstefana/v20.2/ip/axis_resampler_2x1_v1 + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_resampler_2x1_v1/src/axis_resampler_2x1_v1.sv b/firmware/ip/axis_resampler_2x1_v1/src/axis_resampler_2x1_v1.sv new file mode 100644 index 0000000..82a6aa4 --- /dev/null +++ b/firmware/ip/axis_resampler_2x1_v1/src/axis_resampler_2x1_v1.sv @@ -0,0 +1,103 @@ +// This block resamples input data to reduce the number of lanes by 2. +// It is extremely important to be sure input data is valid only +// every other clock. Faster input data rate will make the block fail. +module axis_resampler_2x1_v1 + #( + // Number of bits. + parameter B = 16 , + + // Number of lanes (input). + parameter N = 8 + ) + ( + // Reset and clock. + input wire aclk , + input wire aresetn , + + // s_axis_* for input data. + output wire s_axis_tready , + input wire s_axis_tvalid , + input wire [N*B-1:0] s_axis_tdata , + + // m_axis_* for output data. + input wire m_axis_tready , + output wire m_axis_tvalid , + output wire [N/2*B-1:0] m_axis_tdata + ); + +/*************/ +/* Internals */ +/*************/ + +// Data registers. +reg [N*B-1:0] din_r1 ; +reg [N*B-1:0] din_r2 ; + +// Low/high part. +wire [N/2*B-1:0] din_low ; +wire [N/2*B-1:0] din_high ; + +// Muxed output. +wire [N/2*B-1:0] d_mux ; +reg [N/2*B-1:0] d_mux_r1 ; + +// Valid. +reg valid_r1 ; +reg valid_r2 ; +reg valid_r3 ; +reg valid_r4 ; +wire valid_i ; + +/****************/ +/* Architecture */ +/****************/ + +// Low/high part. +assign din_low = din_r2 [0 +: N/2*B]; +assign din_high = din_r2 [N/2*B +: N/2*B]; + +// Muxed output. +assign d_mux = (valid_r2)? din_low : din_high; + +// Valid. +assign valid_i = valid_r3 || valid_r4; + +// Registers. +always @(posedge aclk) begin + if (~aresetn) begin + // Data registers. + din_r1 <= 0; + din_r2 <= 0; + + d_mux_r1 <= 0; + + // Valid. + valid_r1 <= 0; + valid_r2 <= 0; + valid_r3 <= 0; + valid_r4 <= 0; + end + else begin + // Data registers. + din_r1 <= s_axis_tdata; + if (valid_r1) + din_r2 <= din_r1; + + // Muxed output. + d_mux_r1 <= d_mux; + + // Valid. + valid_r1 <= s_axis_tvalid; + valid_r2 <= valid_r1; + valid_r3 <= valid_r2; + valid_r4 <= valid_r3; + end +end + +// Assign outputs. +assign s_axis_tready = 1'b1 ; +assign m_axis_tvalid = valid_i ; +assign m_axis_tdata = d_mux_r1 ; + +endmodule + diff --git a/firmware/ip/axis_resampler_2x1_v1/src/tb.sv b/firmware/ip/axis_resampler_2x1_v1/src/tb.sv new file mode 100644 index 0000000..bcbbdf2 --- /dev/null +++ b/firmware/ip/axis_resampler_2x1_v1/src/tb.sv @@ -0,0 +1,84 @@ +module tb(); + +// Number of bits. +parameter B = 8; + +// Number of lanes (input). +parameter N = 4; + +// Reset and clock. +reg aresetn ; +reg aclk ; + +// s_axis_* for input data. +wire s_axis_tready ; +reg s_axis_tvalid ; +reg [N*B-1:0] s_axis_tdata ; + +// m_axis_* for output data. +reg m_axis_tready ; +wire m_axis_tvalid ; +wire [N/2*B-1:0] m_axis_tdata ; + +/**************/ +/* Test Bench */ +/**************/ + +// DUT. +axis_resampler_2x1_v1 + #( + // Number of bits. + .B(B), + + // Number of lanes (input). + .N(N) + ) + DUT + ( + // Reset and clock. + .aclk , + .aresetn , + + // s_axis_* for input data. + .s_axis_tready , + .s_axis_tvalid , + .s_axis_tdata , + + // m_axis_* for output data. + .m_axis_tready , + .m_axis_tvalid , + .m_axis_tdata + ); + +initial begin + // Reset sequence. + aresetn <= 0; + s_axis_tvalid <= 0; + m_axis_tready <= 1; + #500; + aresetn <= 1; + + #1000; + + for (int i=0; i<200; i=i+1) begin + @(posedge aclk); + s_axis_tvalid <= 0; + @(posedge aclk); + @(posedge aclk); + @(posedge aclk); + s_axis_tvalid <= 1; + for (int j=0; j + + user.org + user + axis_set_reg + 1.0 + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TSTRB + + + s_axis_tstrb + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axis_aresetn + + + + + + + RST + + + s_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axis_aclk + + + + + + + CLK + + + s_axis_aclk + + + + + + ASSOCIATED_BUSIF + s_axis + + + ASSOCIATED_RESET + s_axis_aresetn + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + axis_set_reg + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 03ba7f93 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + axis_set_reg + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 03ba7f93 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 35ebc586 + + + + + + + s_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axis_tstrb + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axis_tlast + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + DATA_WIDTH + Data Width + 16 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/axis_set_reg.vhd + vhdlSource + CHECKSUM_03ba7f93 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/axis_set_reg.vhd + vhdlSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_set_reg_v1_0.tcl + tclSource + CHECKSUM_35ebc586 + XGUI_VERSION_2 + + + + AXIS Set Register Block. + + + DATA_WIDTH + Data Width + 16 + + + Component_Name + axis_set_reg_v1_0 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + kintexuplus + kintexu + + + /UserIP + + AXIS Set Register + package_project + 3 + 2020-12-15T18:32:58Z + + /home/lstefana/v19.1/ip/axis_set_reg + /home/lstefana/v19.1/ip/axis_set_reg + /home/lstefana/v19.1/ip/axis_set_reg + /home/lstefana/v19.1/ip/axis_set_reg + /home/lstefana/v19.1/ip/axis_set_reg + /home/lstefana/v19.1/ip/axis_set_reg + /home/lstefana/v19.1/ip/axis_set_reg + /home/lstefana/v19.1/ip/axis_set_reg + /home/lstefana/v19.1/ip/axis_set_reg + /home/lstefana/v19.1/ip/axis_set_reg + /home/lstefana/v19.1/ip/axis_set_reg + /home/lstefana/v19.1/ip/axis_set_reg + /home/lstefana/v19.1/ip/axis_set_reg + + + + 2019.1 + + + + + + + + diff --git a/firmware/ip/axis_set_reg/src/axis_set_reg.vhd b/firmware/ip/axis_set_reg/src/axis_set_reg.vhd new file mode 100644 index 0000000..cc2e0ea --- /dev/null +++ b/firmware/ip/axis_set_reg/src/axis_set_reg.vhd @@ -0,0 +1,55 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity axis_set_reg is + generic + ( + -- Data width. + DATA_WIDTH : Integer := 16 + ); + port + ( + -- AXIS Slave I/F. + s_axis_aclk : in std_logic; + s_axis_aresetn : in std_logic; + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + s_axis_tstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- Output data. + dout : out std_logic_vector (DATA_WIDTH-1 downto 0) + ); +end axis_set_reg; + +architecture rtl of axis_set_reg is + +-- Data register. +signal dout_r : std_logic_vector (DATA_WIDTH-1 downto 0); + +begin + +-- Registers. +process (s_axis_aclk) +begin + if ( rising_edge(s_axis_aclk) ) then + if ( s_axis_aresetn = '0' ) then + -- Data register. + dout_r <= (others => '0'); + else + -- Data register. + if ( s_axis_tvalid = '1' ) then + dout_r <= s_axis_tdata; + end if; + end if; + end if; +end process; + +-- Assign outputs. +s_axis_tready <= '1'; +dout <= dout_r; + +end rtl; + diff --git a/firmware/ip/axis_set_reg/xgui/axis_set_reg_v1_0.tcl b/firmware/ip/axis_set_reg/xgui/axis_set_reg_v1_0.tcl new file mode 100644 index 0000000..55a2622 --- /dev/null +++ b/firmware/ip/axis_set_reg/xgui/axis_set_reg_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + diff --git a/firmware/ip/axis_sg_int4_v1/component.xml b/firmware/ip/axis_sg_int4_v1/component.xml new file mode 100644 index 0000000..3837c5a --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/component.xml @@ -0,0 +1,1305 @@ + + + user.org + user + axis_sg_int4_v1 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s0_axis + + + + + + + TDATA + + + s0_axis_tdata + + + + + TVALID + + + s0_axis_tvalid + + + + + TREADY + + + s0_axis_tready + + + + + + s1_axis + + + + + + + TDATA + + + s1_axis_tdata + + + + + TVALID + + + s1_axis_tvalid + + + + + TREADY + + + s1_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s0_axis_aclk + + + + + + + CLK + + + s0_axis_aclk + + + + + + ASSOCIATED_BUSIF + s0_axis + + + ASSOCIATED_RESET + s0_axis_aresetn + + + + + s0_axis_aresetn + + + + + + + RST + + + s0_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s1_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_sg_int4_v1 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 95568600 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_sg_int4_v1 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 95568600 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 9465d594 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s0_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_tdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s0_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_axis_tdata + + in + + 87 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s1_axis_tvalid + + in + + + std_logic + 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+ + src/signal_gen.v + verilogSource + + + src/signal_gen_top.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_int4_v1.v + verilogSource + CHECKSUM_c287fed2 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/fir_0/fir_0.coe + coe + + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/fir_0/fir_0.xci + xci + CELL_NAME_signal_gen_top_i/signal_gen_i/fir_i/fir_0 + + + src/latency_reg.v + verilogSource + + + src/signal_gen.v + verilogSource + + + src/signal_gen_top.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_int4_v1.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_sg_int4_v1_v1_0.tcl + tclSource + CHECKSUM_9465d594 + XGUI_VERSION_2 + + + + AXIS Signal Generator with x4 Interpolated Envelope + + + N + N + 12 + + + Component_Name + axis_sg_int4_v1_v1_0 + + + + + + zynquplus + + + /UserIP + + AXIS SG x4 Interpolation + package_project + 6 + 2022-04-07T20:07:10Z + + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + /home/lstefana/v20.2/ip/axis_sg_int4_v1 + + + + 2020.2 + + + + + + + + + diff --git a/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 0000000..7cfbd51 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 8 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 0000000..a53be60 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 8 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..ac9cf04 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,200 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 0000000..7be1f50 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4760 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + ARSIZE + + + m_axi_arsize + + + + + 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USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_8 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_8 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_8 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 8 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + + diff --git a/firmware/ip/axis_sg_int4_v1/src/axi_slv.vhd b/firmware/ip/axis_sg_int4_v1/src/axi_slv.vhd new file mode 100644 index 0000000..c60ea98 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/axi_slv.vhd @@ -0,0 +1,516 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + START_ADDR_REG : out std_logic_vector (31 downto 0); + WE_REG : out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + -- 0 : START_ADDR_REG : 32-bit. Start address to write into memory. + -- 1 : WE_REG : 1-bit. Enable write into memory. + + -- Output Registers. + START_ADDR_REG <= slv_reg0; + WE_REG <= slv_reg1(0); + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/axis_sg_int4_v1.v b/firmware/ip/axis_sg_int4_v1/src/axis_sg_int4_v1.v new file mode 100644 index 0000000..f913b85 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/axis_sg_int4_v1.v @@ -0,0 +1,197 @@ +// Signal Generator V4. +// s_axi_aclk : clock for s_axi_* +// s0_axis_aclk : clock for s0_axis_* +// aclk : clock for s1_axis_* and m_axis_* +// +module axis_sg_int4_v1 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // AXIS Slave to load memory samples. + s0_axis_aclk , + s0_axis_aresetn , + s0_axis_tdata , + s0_axis_tvalid , + s0_axis_tready , + + // s1_* and m_* reset/clock. + aclk , + aresetn , + + // AXIS Slave to queue waveforms. + s1_axis_tdata , + s1_axis_tvalid , + s1_axis_tready , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +parameter N = 12; + +// Number of parallel dds blocks. +localparam [31:0] N_DDS = 4; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input s0_axis_aclk; +input s0_axis_aresetn; +input [31:0] s0_axis_tdata; +input s0_axis_tvalid; +output s0_axis_tready; + +input aresetn; +input aclk; + +input [87:0] s1_axis_tdata; +input s1_axis_tvalid; +output s1_axis_tready; + +input m_axis_tready; +output m_axis_tvalid; +output [4*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] START_ADDR_REG; +wire WE_REG; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG ), + .WE_REG (WE_REG ) + ); + +signal_gen_top + #( + .N (N ), + .N_DDS (N_DDS ) + ) + signal_gen_top_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // AXIS Slave to load memory samples. + .s0_axis_aresetn (s0_axis_aresetn ), + .s0_axis_aclk (s0_axis_aclk ), + .s0_axis_tdata_i (s0_axis_tdata ), + .s0_axis_tvalid_i (s0_axis_tvalid ), + .s0_axis_tready_o (s0_axis_tready ), + + // AXIS Slave to queue waveforms. + .s1_axis_tdata_i (s1_axis_tdata ), + .s1_axis_tvalid_i (s1_axis_tvalid ), + .s1_axis_tready_o (s1_axis_tready ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_sg_int4_v1/src/bram.v b/firmware/ip/axis_sg_int4_v1/src/bram.v new file mode 100644 index 0000000..018317e --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/bram.v @@ -0,0 +1,33 @@ +module bram (clk,ena,wea,addra,dia,doa); + +// Memory address size. +parameter N = 16; +// Data width. +parameter B = 16; + +input clk; +input ena; +input wea; +input [N-1:0] addra; +input [B-1:0] dia; +output [B-1:0] doa; + +// Ram type. +reg [B-1:0] RAM [0:2**N-1]; +reg [B-1:0] doa; + +always @(posedge clk) +begin + if (ena) + begin + if (wea) begin + RAM[addra] <= dia; + end + else begin + doa <= RAM[addra]; + end + end +end + +endmodule + diff --git a/firmware/ip/axis_sg_int4_v1/src/ctrl.sv b/firmware/ip/axis_sg_int4_v1/src/ctrl.sv new file mode 100644 index 0000000..0cfd01a --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/ctrl.sv @@ -0,0 +1,499 @@ +//Format of waveform interface: +// |-------|---------|------|----------|----------|----------|----------|----------|---------| +// | 84 | 83 | 82 | 81 .. 80 | 79 .. 64 | 63 .. 48 | 47 .. 32 | 31 .. 16 | 15 .. 0 | +// |-------|---------|------|----------|----------|----------|----------|----------|---------| +// | phrst | stdysel | mode | outsel | nsamp | gain | addr | phase | freq | +// |-------|---------|------|----------|----------|----------|----------|----------|---------| +// freq : 16 bits +// phase : 16 bits +// addr : 16 bits +// gain : 16 bits +// nsamp : 16 bits +// outsel : 2 bits +// mode : 1 bit +// stdysel : 1 bit +// phrst : 1 bit +// +// Total : 85. +module ctrl ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // dds control. + dds_ctrl_o , + + // memory control. + mem_addr_o , + + // gain. + gain_o , + + // Output source selection. + src_o , + + // Steady value selection. + stdy_o , + + // Output enable. + en_o ); + +// Memory address size. +parameter N = 16; + +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 16; + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [84:0] fifo_dout_i; +output [N_DDS*40-1:0] dds_ctrl_o; +output [N-1:0] mem_addr_o; +output [15:0] gain_o; +output [1:0] src_o; +output stdy_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// Fifo dout register. +reg [84:0] fifo_dout_r; + +// Non-stop counter for time calculation (adds N_DDS samples each clock tick). +reg [15:0] cnt_n; +reg [15:0] cnt_n_reg; + +// Pinc/phase. +wire [15:0] pinc_int; +reg [15:0] pinc_r1; +reg [15:0] pinc_r2; +wire [15:0] pinc_N; +reg [15:0] pinc_N_r1; +reg [15:0] pinc_N_r2; +reg [15:0] pinc_N_r3; +reg [15:0] pinc_N_r4; +reg [15:0] pinc_N_r5; +wire [15:0] pinc_Nm; +reg [15:0] pinc_Nm_r1; +reg [15:0] pinc_Nm_r2; +reg [15:0] pinc_Nm_r3; + +wire [15:0] phase_int; +reg [15:0] phase_r1; +reg [15:0] phase_r2; +reg [15:0] phase_r3; +reg [15:0] phase_r4; +reg [15:0] phase_r5; +wire [15:0] phase_0; +reg [15:0] phase_0_r1; + +// Phase vectors. +wire [15:0] phase_v0 [0:N_DDS-1]; +reg [15:0] phase_v0_r1 [0:N_DDS-1]; +reg [15:0] phase_v0_r2 [0:N_DDS-1]; +reg [15:0] phase_v0_r3 [0:N_DDS-1]; +reg [15:0] phase_v0_r4 [0:N_DDS-1]; +wire [15:0] phase_v1 [0:N_DDS-1]; +reg [15:0] phase_v1_r1 [0:N_DDS-1]; + +// sync. +reg sync_reg; +reg sync_reg_r1; +reg sync_reg_r2; +reg sync_reg_r3; +reg sync_reg_r4; +reg sync_reg_r5; +reg sync_reg_r6; +reg sync_reg_r7; + +// Address. +wire [15:0] addr_int; +reg [15:0] addr_cnt; +reg [15:0] addr_cnt_r1; +reg [15:0] addr_cnt_r2; +reg [15:0] addr_cnt_r3; +reg [15:0] addr_cnt_r4; +reg [15:0] addr_cnt_r5; +reg [15:0] addr_cnt_r6; + +// Gain. +wire [15:0] gain_int; +reg [15:0] gain_r1; +reg [15:0] gain_r2; +reg [15:0] gain_r3; +reg [15:0] gain_r4; +reg [15:0] gain_r5; +reg [15:0] gain_r6; +reg [15:0] gain_r7; + +// Number of samples. +wire [15:0] nsamp_int; + +// Output selection. +wire [1:0] outsel_int; +reg [1:0] outsel_r1; +reg [1:0] outsel_r2; +reg [1:0] outsel_r3; +reg [1:0] outsel_r4; +reg [1:0] outsel_r5; +reg [1:0] outsel_r6; +reg [1:0] outsel_r7; + +// Mode. +wire mode_int; + +// Steady value selection. +wire stdysel_int; +reg stdysel_r1; +reg stdysel_r2; +reg stdysel_r3; +reg stdysel_r4; +reg stdysel_r5; +reg stdysel_r6; +reg stdysel_r7; + +// Phase reset. +wire phrst_int; + +// Load enable flag. +wire load_int; +reg load_r; + +// Fifo Read Enable. +reg rd_en_int; +reg rd_en_r1; +reg rd_en_r2; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +reg en_reg_r1; +reg en_reg_r2; +reg en_reg_r3; +reg en_reg_r4; +reg en_reg_r5; +reg en_reg_r6; +reg en_reg_r7; +reg en_reg_r8; + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Non-stop counter for time calculation. + cnt_n <= 0; + cnt_n_reg <= 0; + + // Pinc/phase/sync. + pinc_r1 <= 0; + pinc_r2 <= 0; + pinc_N_r1 <= 0; + pinc_N_r2 <= 0; + pinc_N_r3 <= 0; + pinc_N_r4 <= 0; + pinc_N_r5 <= 0; + pinc_Nm_r1 <= 0; + pinc_Nm_r2 <= 0; + pinc_Nm_r3 <= 0; + + phase_r1 <= 0; + phase_r2 <= 0; + phase_r3 <= 0; + phase_r4 <= 0; + phase_r5 <= 0; + phase_0_r1 <= 0; + + sync_reg <= 0; + sync_reg_r1 <= 0; + sync_reg_r2 <= 0; + sync_reg_r3 <= 0; + sync_reg_r4 <= 0; + sync_reg_r5 <= 0; + sync_reg_r6 <= 0; + sync_reg_r7 <= 0; + + // Address. + addr_cnt <= 0; + addr_cnt_r1 <= 0; + addr_cnt_r2 <= 0; + addr_cnt_r3 <= 0; + addr_cnt_r4 <= 0; + addr_cnt_r5 <= 0; + addr_cnt_r6 <= 0; + + // Gain. + gain_r1 <= 0; + gain_r2 <= 0; + gain_r3 <= 0; + gain_r4 <= 0; + gain_r5 <= 0; + gain_r6 <= 0; + gain_r7 <= 0; + + // Output selection. + outsel_r1 <= 0; + outsel_r2 <= 0; + outsel_r3 <= 0; + outsel_r4 <= 0; + outsel_r5 <= 0; + outsel_r6 <= 0; + outsel_r7 <= 0; + + // Steady value selection. + stdysel_r1 <= 0; + stdysel_r2 <= 0; + stdysel_r3 <= 0; + stdysel_r4 <= 0; + stdysel_r5 <= 0; + stdysel_r6 <= 0; + stdysel_r7 <= 0; + + // Load enable flag. + load_r <= 0; + + // Fifo Read Enable. + rd_en_r1 <= 0; + rd_en_r2 <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + en_reg_r1 <= 0; + en_reg_r2 <= 0; + en_reg_r3 <= 0; + en_reg_r4 <= 0; + en_reg_r5 <= 0; + en_reg_r6 <= 0; + en_reg_r7 <= 0; + en_reg_r8 <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (mode_int || ~fifo_empty_i) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Non-stop counter for time calculation. + if (sync_reg == 1'b1 && phrst_int == 1'b1) + cnt_n <= 0; + else + cnt_n <= cnt_n + N_DDS; + + if (sync_reg_r1 == 1'b1) + cnt_n_reg <= cnt_n; + + // Pinc/phase/sync. + pinc_r1 <= pinc_int; + pinc_r2 <= pinc_r1; + pinc_N_r1 <= pinc_N; + pinc_N_r2 <= pinc_N_r1; + pinc_N_r3 <= pinc_N_r2; + pinc_N_r4 <= pinc_N_r3; + pinc_N_r5 <= pinc_N_r4; + pinc_Nm_r1 <= pinc_Nm; + pinc_Nm_r2 <= pinc_Nm_r1; + pinc_Nm_r3 <= pinc_Nm_r2; + + phase_r1 <= phase_int; + phase_r2 <= phase_r1; + phase_r3 <= phase_r2; + phase_r4 <= phase_r3; + phase_r5 <= phase_r4; + phase_0_r1 <= phase_0; + + sync_reg <= load_r; + sync_reg_r1 <= sync_reg; + sync_reg_r2 <= sync_reg_r1; + sync_reg_r3 <= sync_reg_r2; + sync_reg_r4 <= sync_reg_r3; + sync_reg_r5 <= sync_reg_r4; + sync_reg_r6 <= sync_reg_r5; + sync_reg_r7 <= sync_reg_r6; + + // Address. + if (rd_en_r2) + addr_cnt <= addr_int; + else + addr_cnt <= addr_cnt + 1; + + addr_cnt_r1 <= addr_cnt; + addr_cnt_r2 <= addr_cnt_r1; + addr_cnt_r3 <= addr_cnt_r2; + addr_cnt_r4 <= addr_cnt_r3; + addr_cnt_r5 <= addr_cnt_r4; + addr_cnt_r6 <= addr_cnt_r5; + + // Gain. + gain_r1 <= gain_int; + gain_r2 <= gain_r1; + gain_r3 <= gain_r2; + gain_r4 <= gain_r3; + gain_r5 <= gain_r4; + gain_r6 <= gain_r5; + gain_r7 <= gain_r6; + + // Output selection. + outsel_r1 <= outsel_int; + outsel_r2 <= outsel_r1; + outsel_r3 <= outsel_r2; + outsel_r4 <= outsel_r3; + outsel_r5 <= outsel_r4; + outsel_r6 <= outsel_r5; + outsel_r7 <= outsel_r6; + + // Steady value selection. + stdysel_r1 <= stdysel_int; + stdysel_r2 <= stdysel_r1; + stdysel_r3 <= stdysel_r2; + stdysel_r4 <= stdysel_r3; + stdysel_r5 <= stdysel_r4; + stdysel_r6 <= stdysel_r5; + stdysel_r7 <= stdysel_r6; + + // Load enable flag. + load_r <= load_int; + + // Fifo Read Enable. + rd_en_r1 <= rd_en_int; + rd_en_r2 <= rd_en_r1; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (~mode_int && rd_en_int) + if (~fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + + en_reg_r1 <= en_reg; + en_reg_r2 <= en_reg_r1; + en_reg_r3 <= en_reg_r2; + en_reg_r4 <= en_reg_r3; + en_reg_r5 <= en_reg_r4; + en_reg_r6 <= en_reg_r5; + en_reg_r7 <= en_reg_r6; + en_reg_r8 <= en_reg_r7; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign pinc_int = fifo_dout_r[15:0]; +assign phase_int = fifo_dout_r[31:16]; +assign addr_int = fifo_dout_r[47:32]; +assign gain_int = fifo_dout_r[63:48]; +assign nsamp_int = fifo_dout_r[79:64]; +assign outsel_int = fifo_dout_r[81:80]; +assign mode_int = fifo_dout_r[82]; +assign stdysel_int = fifo_dout_r[83]; +assign phrst_int = fifo_dout_r[84]; + +// Frequency calculation. +assign pinc_N = pinc_r2*N_DDS; + +// Phase calculation. +assign pinc_Nm = pinc_r2*cnt_n_reg; +assign phase_0 = pinc_Nm_r3 + phase_r5; + +// Phase vectors. +generate +genvar i; + for (i=0; i < N_DDS; i = i + 1) begin : GEN_phase + // Registers. + always @(posedge clk) begin + if (~rstn) begin + // v0. + phase_v0_r1[i] <= 0; + phase_v0_r2[i] <= 0; + phase_v0_r3[i] <= 0; + phase_v0_r4[i] <= 0; + + // v1. + phase_v1_r1[i] <= 0; + end + else begin + // v0. + phase_v0_r1[i] <= phase_v0[i]; + phase_v0_r2[i] <= phase_v0_r1[i]; + phase_v0_r3[i] <= phase_v0_r2[i]; + phase_v0_r4[i] <= phase_v0_r3[i]; + + // v1. + phase_v1_r1[i] <= phase_v1[i]; + end + end + + // v0. + assign phase_v0[i] = pinc_r2*i; + + // v1. + assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; + + // dds_ctrl_o output. + assign dds_ctrl_o[i*40 +: 40] = {7'h00,sync_reg_r7,phase_v1_r1[i],pinc_N_r5}; + end +endgenerate + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mem_addr_o = addr_cnt_r6; +assign gain_o = gain_r7; +assign src_o = outsel_r7; +assign stdy_o = stdysel_r7; +assign en_o = en_reg_r8; + +endmodule + diff --git a/firmware/ip/axis_sg_int4_v1/src/data_writer.vhd b/firmware/ip/axis_sg_int4_v1/src/data_writer.vhd new file mode 100644 index 0000000..8fa76e3 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/data_writer.vhd @@ -0,0 +1,200 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity data_writer is + Generic + ( + -- Memory size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in STD_LOGIC; + clk : in STD_LOGIC; + + -- AXI Stream I/F. + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- Memory I/F. + mem_en : out std_logic; + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_di : out std_logic_vector (B-1 downto 0); + + -- Registers. + START_ADDR_REG : in std_logic_vector (31 downto 0); + WE_REG : in std_logic + ); +end data_writer; + +architecture rtl of data_writer is + +-- Synchronizer. +component synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end component; + +-- State machine. +type fsm_state is ( INIT_ST , + READ_START_ADDR_ST , + WAIT_TVALID_ST , + RW_TDATA_ST ); +signal state : fsm_state; + +signal read_start_addr_state : std_logic; +signal rw_tdata_state : std_logic; + +-- WE_REG_resync. +signal WE_REG_resync : std_logic; + +-- Axis registers. +signal tready_i : std_logic; +signal tready_r : std_logic; +signal tdata_r : std_logic_vector(B-1 downto 0); +signal tdata_rr : std_logic_vector(B-1 downto 0); +signal tdata_rrr : std_logic_vector(B-1 downto 0); +signal tvalid_r : std_logic; +signal tvalid_rr : std_logic; +signal tvalid_rrr : std_logic; + +-- Memory address space. +signal mem_addr_full : unsigned (N-1 downto 0); +signal mem_addr_full_r : unsigned (N-1 downto 0); + +begin + +-- WE_REG_resync +WE_REG_resync_i : synchronizer_n + generic map ( + N => 2 + ) + port map ( + rstn => rstn , + clk => clk , + data_in => WE_REG , + data_out => WE_REG_resync + ); + +process (clk) +begin + if ( rising_edge(clk) ) then + if (rstn = '0') then + -- Axis registers. + tready_r <= '0'; + tdata_r <= (others => '0'); + tdata_rr <= (others => '0'); + tdata_rrr <= (others => '0'); + tvalid_r <= '0'; + tvalid_rr <= '0'; + tvalid_rrr <= '0'; + + -- Memory address. + mem_addr_full <= (others => '0'); + mem_addr_full_r <= (others => '0'); + else + -- Axis registers. + tready_r <= tready_i; + tdata_r <= s_axis_tdata; + tvalid_r <= s_axis_tvalid; + + -- Extra registers to account pipe of state machine. + tdata_rr <= tdata_r; + tdata_rrr <= tdata_rr; + tvalid_rr <= tvalid_r; + tvalid_rrr <= tvalid_rr; + + -- Memory address. + if ( read_start_addr_state = '1') then + mem_addr_full <= to_unsigned(to_integer(unsigned(START_ADDR_REG)),mem_addr_full'length); + elsif ( rw_tdata_state = '1' ) then + mem_addr_full <= mem_addr_full + 1; + end if; + mem_addr_full_r <= mem_addr_full; + + end if; + end if; +end process; + +-- Finite state machine. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + state <= INIT_ST; + else + case state is + when INIT_ST => + if ( WE_REG_resync = '1' ) then + state <= READ_START_ADDR_ST; + end if; + + when READ_START_ADDR_ST => + state <= WAIT_TVALID_ST; + + when WAIT_TVALID_ST => + if ( WE_REG_resync = '1') then + if ( tvalid_r = '0' ) then + state <= WAIT_TVALID_ST; + else + state <= RW_TDATA_ST; + end if; + else + state <= INIT_ST; + end if; + + when RW_TDATA_ST => + if ( tvalid_r = '0' ) then + state <= WAIT_TVALID_ST; + end if; + + end case; + end if; + end if; +end process; + +-- Output logic. +process (state) +begin +read_start_addr_state <= '0'; +rw_tdata_state <= '0'; +tready_i <= '0'; + case state is + when INIT_ST => + + when READ_START_ADDR_ST => + read_start_addr_state <= '1'; + + when WAIT_TVALID_ST => + tready_i <= '1'; + + when RW_TDATA_ST => + rw_tdata_state <= '1'; + tready_i <= '1'; + + end case; +end process; + +-- Assign output. +s_axis_tready <= tready_r; + +mem_en <= '1'; +mem_we <= tvalid_rrr; +mem_addr <= std_logic_vector(mem_addr_full_r); +mem_di <= tdata_rrr; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.veo b/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.veo new file mode 100644 index 0000000..c3dea29 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.veo @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:dds_compiler:6.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +dds_compiler_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [39 : 0] s_axis_phase_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file dds_compiler_0.v when simulating +// the core, dds_compiler_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.vho b/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.vho new file mode 100644 index 0000000..4db3fc6 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.vho @@ -0,0 +1,83 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:dds_compiler:6.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT dds_compiler_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(39 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : dds_compiler_0 + PORT MAP ( + aclk => aclk, + s_axis_phase_tvalid => s_axis_phase_tvalid, + s_axis_phase_tdata => s_axis_phase_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file dds_compiler_0.vhd when simulating +-- the core, dds_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 0000000..562a763 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,315 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_compiler_0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 5 + 0 + 0 + 0 + 16 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 10 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 40 + 1 + 1 + zynquplus + Full_Range + 1 + dds_compiler_0 + Not_Required + 256 + Maximal + 3906.25 + Coregen + false + false + false + false + 10 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + false + Auto + Twos_Complement + Speed + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 16 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 20 + TRUE + ../../../../top/top.tmp/axis_sg_int4_v1_v1_0_project/axis_sg_int4_v1_v1_0_project.gen/sources_1/ip/dds_compiler_0 + + . + 2020.2 + GLOBAL + + + + + + + + + + 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+ + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/dds_compiler_v6_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + dds_compiler_v6_0_20 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/dds_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_cmodelsimulation_view_fileset + + cmodel/dds_compiler_v6_0_bitacc_cmodel_lin64.zip + zip + + + cmodel/dds_compiler_v6_0_bitacc_cmodel_nt64.zip + zip + + + + xilinx_vhdltestbench_view_fileset + + demo_tb/tb_dds_compiler_0.vhd + vhdlSource + + + + xilinx_versioninformation_view_fileset + + doc/dds_compiler_v6_0_changelog.txt + text + + + + xilinx_externalfiles_view_fileset + + dds_compiler_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + dds_compiler_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + dds_compiler_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + dds_compiler_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + dds_compiler_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. + + + Component_Name + Component Name + dds_compiler_0 + + + PartsPresent + Configuration Options + Phase_Generator_and_SIN_COS_LUT + + + DDS_Clock_Rate + System Clock + 256 + + + Channels + Number of Channels + 1 + + + Mode_of_Operation + Mode Of Operation + Standard + + + Modulus + Modulus + 9 + + + Parameter_Entry + Parameter Selection + System_Parameters + + + Spurious_Free_Dynamic_Range + Spurious Free Dynamic Range + 96 + + + Frequency_Resolution + Frequency Resolution + 3906.25 + + + Noise_Shaping + Noise Shaping + Auto + + + Phase_Width + Phase Width + 16 + + + Output_Width + Output Width + 16 + + + Phase_Increment + Phase Increment + Streaming + + + Resync + Resync + true + + + Phase_offset + Phase Offset + Streaming + + + Output_Selection + Output Selection + Sine_and_Cosine + + + Negative_Sine + Negative Sine + false + + + Negative_Cosine + Negative Cosine + false + + + Amplitude_Mode + Amplitude Mode + Full_Range + + + Memory_Type + Memory Type + Auto + + + Optimization_Goal + Optimization Goal + Speed + + + DSP48_Use + DSP48 Use + Maximal + + + Has_Phase_Out + Has Phase Out + false + + + DATA_Has_TLAST + DATA Has TLAST + Not_Required + + + Has_TREADY + Output TREADY + false + + + S_PHASE_Has_TUSER + Input + Not_Required + + + S_PHASE_TUSER_Width + User Field Width + 1 + + + M_DATA_Has_TUSER + DATA Output + Not_Required + + + M_PHASE_Has_TUSER + PHASE Output + Not_Required + + + S_CONFIG_Sync_Mode + Synchronization Mode + On_Vector + + + OUTPUT_FORM + Output Form + Twos_Complement + + + Latency_Configuration + Configurable + + + Latency + 10 + + + Has_ARESETn + ARESETn (active low) + false + + + Has_ACLKEN + ACLKEN + false + + + Output_Frequency1 + 0 + + + PINC1 + 0 + + + Phase_Offset_Angles1 + 0 + + + POFF1 + 0 + + + Output_Frequency2 + 0 + + + PINC2 + 0 + + + Phase_Offset_Angles2 + 0 + + + POFF2 + 0 + + + Output_Frequency3 + 0 + + + PINC3 + 0 + + + Phase_Offset_Angles3 + 0 + + + POFF3 + 0 + + + Output_Frequency4 + 0 + + + PINC4 + 0 + + + Phase_Offset_Angles4 + 0 + + + POFF4 + 0 + + + Output_Frequency5 + 0 + + + PINC5 + 0 + + + Phase_Offset_Angles5 + 0 + + + POFF5 + 0 + + + Output_Frequency6 + 0 + + + PINC6 + 0 + + + Phase_Offset_Angles6 + 0 + + + POFF6 + 0 + + + Output_Frequency7 + 0 + + + PINC7 + 0 + + + Phase_Offset_Angles7 + 0 + + + POFF7 + 0 + + + Output_Frequency8 + 0 + + + PINC8 + 0 + + + Phase_Offset_Angles8 + 0 + + + POFF8 + 0 + + + Output_Frequency9 + 0 + + + PINC9 + 0 + + + Phase_Offset_Angles9 + 0 + + + POFF9 + 0 + + + Output_Frequency10 + 0 + + + PINC10 + 0 + + + Phase_Offset_Angles10 + 0 + + + POFF10 + 0 + + + Output_Frequency11 + 0 + + + PINC11 + 0 + + + Phase_Offset_Angles11 + 0 + + + POFF11 + 0 + + + Output_Frequency12 + 0 + + + PINC12 + 0 + + + Phase_Offset_Angles12 + 0 + + + POFF12 + 0 + + + Output_Frequency13 + 0 + + + PINC13 + 0 + + + Phase_Offset_Angles13 + 0 + + + POFF13 + 0 + + + Output_Frequency14 + 0 + + + PINC14 + 0 + + + Phase_Offset_Angles14 + 0 + + + POFF14 + 0 + + + Output_Frequency15 + 0 + + + PINC15 + 0 + + + Phase_Offset_Angles15 + 0 + + + POFF15 + 0 + + + Output_Frequency16 + 0 + + + PINC16 + 0 + + + Phase_Offset_Angles16 + 0 + + + POFF16 + 0 + + + POR_mode + POR Mode + false + + + GUI_Behaviour + Coregen + + + explicit_period + false + + + period + 1 + + + + + DDS Compiler + 20 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/bin2gray.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/bin2gray.vhd new file mode 100644 index 0000000..4ecc09b --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/bin2gray.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end bin2gray; + +architecture rtl of bin2gray is + +signal gray : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +gray(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + gray(I) <= din(I+1) xor din(I); +end generate; + +-- Assign output. +dout <= gray; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/bram_dp.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/bram_dp.vhd new file mode 100644 index 0000000..d57aad1 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/bram_dp.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture rtl of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/bram_simple_dp.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/bram_simple_dp.vhd new file mode 100644 index 0000000..1494332 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/bram_simple_dp.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_simple_dp; + +architecture rtl of bram_simple_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/fifo.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/fifo.vhd new file mode 100644 index 0000000..957362b --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/fifo.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture rtl of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Dual port, single clock BRAM. +component bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- FIFO memory. +mem_i : bram_simple_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_axi.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_dc.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/gray2bin.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/rd2axi.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_sg_int4_v1/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.coe b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.coe new file mode 100644 index 0000000..fd9c445 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = 0.004708,0.005461,0.000000,-0.013987,-0.029332,-0.030123,0.000000,0.065216,0.149630,0.221652,0.250000,0.221652,0.149630,0.065216,0.000000,-0.030123,-0.029332,-0.013987,0.000000,0.005461,0.004708 \ No newline at end of file diff --git a/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.veo b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.veo new file mode 100644 index 0000000..44cd847 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fir_compiler:7.2 +// IP Revision: 15 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fir_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready + .s_axis_data_tdata(s_axis_data_tdata), // input wire [31 : 0] s_axis_data_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [127 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fir_0.v when simulating +// the core, fir_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.vho b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.vho new file mode 100644 index 0000000..be451e1 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fir_compiler:7.2 +-- IP Revision: 15 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT fir_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_data_tvalid : IN STD_LOGIC; + s_axis_data_tready : OUT STD_LOGIC; + s_axis_data_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : fir_0 + PORT MAP ( + aclk => aclk, + s_axis_data_tvalid => s_axis_data_tvalid, + s_axis_data_tready => s_axis_data_tready, + s_axis_data_tdata => s_axis_data_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file fir_0.vhd when simulating +-- the core, fir_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xci b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xci new file mode 100644 index 0000000..e6289dd --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xci @@ -0,0 +1,321 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 16 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 31,31,31,31,31,31,31,31 + 31,31,31,31,31,31,31,31 + fixed + fir_0.mif + 24 + 2 + 0 + 0,0,0,0,0,0,0,0 + 0,0,2,2,4,4,6,6 + 16,16,16,16,16,16,16,16 + 0 + 16 + 6 + 1 + 4 + fir_0 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + -0;-1;-0;-1;-0;-1;-0;-1 + 0,0,0,0,0,0,0,0 + 0,1,0,1,0,1,0,1 + 16,16,16,16,16,16,16,16 + 16,16 + 16 + 1 + ./ + none + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 12 + 2 + 0 + 0 + 128 + 1 + 1 + 1 + 6 + 1 + 21 + 0 + 0 + none;none;none;none + -0;-1;-0;-1;-0;-1;-0;-1 + 16,16,16,16,16,16,16,16 + 1 + 16 + 1 + 0,1,2,3,4,5,6,7 + 1 + 3 + 0 + 0 + 0 + 32 + 1 + zynquplus + 1 + true + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + fir_0.coe + 16 + false + 1 + Signed + Inferred + 16 + 6 + fir_0 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolation + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 4 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Infinity + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Quantize_Only + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + false + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 15 + TRUE + ../../../../top/top.tmp/axis_sg_int4_v1_v1_0_project/axis_sg_int4_v1_v1_0_project.gen/sources_1/ip/fir_0 + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xml b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xml new file mode 100644 index 0000000..57879e2 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xml @@ -0,0 +1,2875 @@ + + + xilinx.com + customized_ip + fir_0 + 1.0 + + + event_s_data_tlast_missing_intf + + + + + + + INTERRUPT + + + event_s_data_tlast_missing + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_data_tlast_unexpected_intf + + + + + + + INTERRUPT + + + event_s_data_tlast_unexpected + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_data_chanid_incorrect_intf + + + + + + + INTERRUPT + + + event_s_data_chanid_incorrect + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_config_tlast_missing_intf + + + + + + + INTERRUPT + + + event_s_config_tlast_missing + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_config_tlast_unexpected_intf + + + + + + + INTERRUPT + + + event_s_config_tlast_unexpected + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_reload_tlast_missing_intf + + + + + + + INTERRUPT + + + event_s_reload_tlast_missing + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_reload_tlast_unexpected_intf + + + + + + + INTERRUPT + + + event_s_reload_tlast_unexpected + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + 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USED_IN_synth_blackbox_stub + xil_defaultlib + + + fir_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + fir_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + constraints/fir_compiler_v7_2.xdc + xdc + fir_compiler_v7_2_15 + + + fir_0.mif + mif + + + hdl/fir_compiler_v7_2_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + fir_compiler_v7_2_15 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/fir_0.vhd + vhdlSource + xil_defaultlib + + + + The Xilinx FIR Compiler LogiCORE is a module for generation of high speed, compact filter implementations that can be configured to implement many different filtering functions. The core is fully synchronous, using a single clock, and is highly parameterizable, allowing designers to control the filter type, data and coefficient widths, the number of filter taps, the number of channels, etc. Multi-rate operation is supported. The core is delivered through the Xilinx Vivado IP Catalog and integrates seamlessly with the Xilinx design flow. + + + Component_Name + fir_0 + + + GUI_Behaviour + Coregen + + + CoefficientSource + COE_File + + + CoefficientVector + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + + + Coefficient_File + fir_0.coe + + + Coefficient_Sets + 1 + + + Coefficient_Reload + false + + + Filter_Type + Interpolation + + + Rate_Change_Type + Integer + + + Interpolation_Rate + 4 + + + Decimation_Rate + 1 + + + Zero_Pack_Factor + 1 + + + Channel_Sequence + Basic + + + Number_Channels + 1 + + + Select_Pattern + All + + + Pattern_List + P4-0,P4-1,P4-2,P4-3,P4-4 + + + Number_Paths + 2 + + + RateSpecification + Input_Sample_Period + + + HardwareOversamplingRate + 1 + + + SamplePeriod + 1 + + + Sample_Frequency + 0.001 + + + Clock_Frequency + 300.0 + + + Coefficient_Sign + Signed + + + Quantization + Quantize_Only + + + Coefficient_Width + 16 + + + BestPrecision + true + + + Coefficient_Fractional_Bits + 16 + + + Coefficient_Structure + Inferred + + + Data_Sign + Signed + + + Data_Width + 16 + + + Data_Fractional_Bits + 0 + + + Output_Rounding_Mode + Symmetric_Rounding_to_Infinity + + + Output_Width + 16 + + + Filter_Architecture + Systolic_Multiply_Accumulate + + + Optimization_Goal + Area + + + Optimization_Selection + None + + + Data_Path_Fanout + false + + + Pre_Adder_Pipeline + false + + + Coefficient_Fanout + false + + + Control_Path_Fanout + false + + + Control_Column_Fanout + false + + + Control_Broadcast_Fanout + false + + + Control_LUT_Pipeline + false + + + No_BRAM_Read_First_Mode + false + + + Optimal_Column_Lengths + false + + + Data_Path_Broadcast + false + + + Disable_Half_Band_Centre_Tap + false + + + No_SRL_Attributes + false + + + Other + false + + + Optimization_List + None + + + Data_Buffer_Type + Automatic + + + Coefficient_Buffer_Type + Automatic + + + Input_Buffer_Type + Automatic + + + Output_Buffer_Type + Automatic + + + Preference_For_Other_Storage + Automatic + + + Multi_Column_Support + Automatic + + + Inter_Column_Pipe_Length + 4 + + + ColumnConfig + 6 + + + DATA_Has_TLAST + Not_Required + + + M_DATA_Has_TREADY + false + + + S_DATA_Has_FIFO + false + + + S_DATA_Has_TUSER + Not_Required + + + M_DATA_Has_TUSER + Not_Required + + + DATA_TUSER_Width + 1 + + + S_CONFIG_Sync_Mode + On_Vector + + + S_CONFIG_Method + Single + + + Num_Reload_Slots + 1 + + + Has_ACLKEN + false + + + Has_ARESETn + false + + + Reset_Data_Vector + true + + + Blank_Output + false + + + Gen_MIF_from_Spec + false + + + Gen_MIF_from_COE + false + + + Reload_File + no_coe_file_loaded + + + Gen_MIF_Files + false + + + DisplayReloadOrder + false + + + Passband_Min + 0.0 + + + Passband_Max + 0.5 + + + Stopband_Min + 0.5 + + + Stopband_Max + 1.0 + + + Filter_Selection + 1 + + + + + FIR Compiler + 15 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_sg_int4_v1/src/latency_reg.v b/firmware/ip/axis_sg_int4_v1/src/latency_reg.v new file mode 100644 index 0000000..687a9f3 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v1/src/tb/gen_gauss.py b/firmware/ip/axis_sg_int4_v1/src/tb/gen_gauss.py new file mode 100644 index 0000000..ea72942 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/tb/gen_gauss.py @@ -0,0 +1,18 @@ +import numpy as np +import matplotlib.pyplot as plt + +def gauss(mu=0, si=0, length=100, maxv=32000): + x = np.arange(0,length) + y = 1/(2*np.pi*si**2)*np.exp(-(x-mu)**2/si**2) + y = y/np.max(y)*maxv + return y + +yi = gauss(mu=300, si=120, length=600) +yq = np.zeros(len(yi)) + +yi = yi.astype(np.int16) +yq = yq.astype(np.int16) + +for ii in range(len(yi)): + print("%d,%d" %(yq[ii],yi[ii])) + diff --git a/firmware/ip/axis_sg_int4_v1/src/tb/tb.sv b/firmware/ip/axis_sg_int4_v1/src/tb/tb.sv new file mode 100644 index 0000000..5f4db0f --- /dev/null +++ b/firmware/ip/axis_sg_int4_v1/src/tb/tb.sv @@ -0,0 +1,495 @@ +// VIP: axi_mst_0 +// DUT: axis_signal_gen_v2 +// IF: s_axi -> axi_mst_0 + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter N = 10; +parameter N_DDS = 4; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +// s0_axis interfase. +reg s0_axis_aclk; +reg s0_axis_aresetn; +reg [31:0] s0_axis_tdata; +wire s0_axis_tready; +reg s0_axis_tvalid; + +reg aresetn; +reg aclk; + +// Dummy clock for debugging. +reg aclk4; + +// s1_axis interfase. +reg [87:0] s1_axis_tdata; +wire s1_axis_tready; +reg s1_axis_tvalid; + +// m_axis interfase. +wire [N_DDS*32-1:0] m_axis_tdata; +reg m_axis_tready = 1; +wire m_axis_tvalid; + +// Waveform Fields. +reg [15:0] freq_r; +reg [15:0] phase_r; +reg [15:0] addr_r; +reg [15:0] gain_r; +reg [15:0] nsamp_r; +reg [1:0] outsel_r; +reg mode_r; +reg stdysel_r; +reg phrst_r; + +// Assignment of data out for debugging. +wire [31:0] dout_ii [0:N_DDS-1]; +reg [31:0] dout_f; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Test bench control. +reg tb_load_mem = 0; +reg tb_load_mem_done = 0; +reg tb_load_wave = 0; +reg tb_load_wave_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m_axis_tdata[32*ii +: 32]; +end +endgenerate +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_sg_int4_v1 + # + ( + .N(N) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // AXIS Slave to load data into memory. + .s0_axis_aclk (s0_axis_aclk ), + .s0_axis_aresetn(s0_axis_aresetn), + .s0_axis_tdata (s0_axis_tdata ), + .s0_axis_tvalid (s0_axis_tvalid ), + .s0_axis_tready (s0_axis_tready ), + + // s1_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // AXIS Slave to queue waveforms. + .s1_axis_tdata (s1_axis_tdata ), + .s1_axis_tvalid (s1_axis_tvalid ), + .s1_axis_tready (s1_axis_tready ), + + // AXIS Master for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +assign s1_axis_tdata = {phrst_r,stdysel_r,mode_r,outsel_r,nsamp_r,gain_r,addr_r,phase_r,freq_r}; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + s0_axis_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + s0_axis_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("############################"); + $display("### Load data into Table ###"); + $display("############################"); + $display("t = %0t", $time); + + /* + ADDR = 0 + */ + + // start_addr. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*0, prot, data_wr, resp); + #10; + + // we. + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); + #10; + + // Load Table. + tb_load_mem <= 1; + wait (tb_load_mem_done); + + #100; + + // we. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); + #10; + + $display("#######################"); + $display("### Queue Waveforms ###"); + $display("#######################"); + $display("t = %0t", $time); + + // Queue waveforms and write output while queuing. + tb_load_wave <= 1; + tb_write_out <= 1; + wait (tb_load_wave_done); + + #30000; + + // Stop writing output data. + tb_write_out <= 0; + + #20000; + +end + +// Load data into memroy. +initial begin + int fd,vali,valq; + bit signed [15:0] ii,qq; + + s0_axis_tvalid <= 0; + s0_axis_tdata <= 0; + + wait (tb_load_mem); + + fd = $fopen("../../../../../tb/gauss.txt","r"); + + wait (s0_axis_tready); + + while($fscanf(fd,"%d,%d", valq,vali) == 2) begin + $display("I,Q: %d, %d", vali,valq); + ii = vali; + qq = valq; + @(posedge s0_axis_aclk); + s0_axis_tvalid <= 1; + s0_axis_tdata <= {qq,ii}; + end + + @(posedge s0_axis_aclk); + s0_axis_tvalid <= 0; + + $fclose(fd); + tb_load_mem_done <= 1; + +end + +// Load waveforms. +initial begin + s1_axis_tvalid <= 0; + freq_r <= 0; + phase_r <= 0; + addr_r <= 0; + gain_r <= 0; + nsamp_r <= 0; + outsel_r <= 0; + mode_r <= 0; + stdysel_r <= 0; + phrst_r <= 0; + + wait (tb_load_wave); + wait (s1_axis_tready); + + /************/ + /* Flat Top */ + /************/ + + @(posedge aclk); + $display("t = %0t", $time); + s1_axis_tvalid <= 1; + freq_r <= freq_calc(100, N_DDS, 15); + addr_r <= 0; + gain_r <= 22000; + nsamp_r <= 300; + outsel_r <= 0; // 0: prod, 1: dds, 2: mem + mode_r <= 0; // 0: nsamp, 1: periodic + + @(posedge aclk); + $display("t = %0t", $time); + s1_axis_tvalid <= 1; + addr_r <= 300; + gain_r <= 11000; + nsamp_r <= 200; + outsel_r <= 1; // 0: prod, 1: dds, 2: mem + mode_r <= 1; // 0: nsamp, 1: periodic + + @(posedge aclk); + s1_axis_tvalid <= 0; + + #15000; + + @(posedge aclk); + $display("t = %0t", $time); + s1_axis_tvalid <= 1; + addr_r <= 300; + gain_r <= 22000; + nsamp_r <= 300; + outsel_r <= 0; // 0: prod, 1: dds, 2: mem + mode_r <= 0; // 0: nsamp, 1: periodic + stdysel_r <= 1; + + /*****************/ + /* Latency Check */ + /*****************/ + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 19); + //phase_r <= 100; + //addr_r <= 10; + //gain_r <= 30000; + //nsamp_r <= 17; + //outsel_r <= 0; // 0: prod, 1: dds, 2: mem + //mode_r <= 0; // 0: nsamp, 1: periodic + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 1); + //phase_r <= 245; + //addr_r <= 300; + //gain_r <= 30000; + //nsamp_r <= 5; + //outsel_r <= 0; // 0: prod, 1: dds, 2: mem + //mode_r <= 0; // 0: nsamp, 1: periodic + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 33); + //phase_r <= 0; + //addr_r <= 5; + //gain_r <= 30000; + //nsamp_r <= 670/N_DDS; + //outsel_r <= 1; // 0: prod, 1: dds, 2: mem + //mode_r <= 0; // 0: nsamp, 1: periodic + //stdysel_r <= 1; // 0: last, 1: zero. + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 22); + //phase_r <= 7689; + //addr_r <= 0; + //gain_r <= 30000; + //nsamp_r <= 70/N_DDS; + //outsel_r <= 2; // 0: prod, 1: dds, 2: mem + //mode_r <= 1; // 0: nsamp, 1: periodic + //stdysel_r <= 1; // 0: last, 1: zero. + + //@(posedge aclk); + //s1_axis_tvalid <= 0; + + //#30000; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 3); + //phase_r <= 0; + //addr_r <= 5; + //gain_r <= 30000; + //nsamp_r <= 670/N_DDS; + //outsel_r <= 1; // 0: prod, 1: dds, 2: mem + //mode_r <= 0; // 0: nsamp, 1: periodic + //stdysel_r <= 1; // 0: last, 1: zero. + + @(posedge aclk); + s1_axis_tvalid <= 0; + tb_load_wave_done <= 1; +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d, imag_d; + + // Output file. + fd = $fopen("../../../../../tb/dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, idx, real, imag"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i + + user.org + user + axis_sg_int4_v2 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s0_axis + + + + + + + TDATA + + + s0_axis_tdata + + + + + TVALID + + + s0_axis_tvalid + + + + + TREADY + + + s0_axis_tready + + + + + + s1_axis + + + + + + + TDATA + + + s1_axis_tdata + + + + + TVALID + + + s1_axis_tvalid + + + + + TREADY + + + s1_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s0_axis_aclk + + + + + + + CLK + + + s0_axis_aclk + + + + + + ASSOCIATED_BUSIF + s0_axis + + + ASSOCIATED_RESET + s0_axis_aresetn + + + + + s0_axis_aresetn + + + + + + + RST + + + s0_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s1_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_sg_int4_v2 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 6650aa41 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_sg_int4_v2 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 6650aa41 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 9465d594 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + 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+ + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + 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src/fir_0/fir_0.coe + coe + + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i + + + src/fir_0/fir_0.xci + xci + CELL_NAME_signal_gen_top_i/signal_gen_i/fir_i + + + src/latency_reg.v + verilogSource + + + src/signal_gen.v + verilogSource + + + src/signal_gen_top.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_int4_v2.v + verilogSource + CHECKSUM_fcc81491 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/fir_0/fir_0.coe + coe + + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i + + + src/fir_0/fir_0.xci + xci + CELL_NAME_signal_gen_top_i/signal_gen_i/fir_i + + + src/latency_reg.v + verilogSource + + + src/signal_gen.v + verilogSource + + + src/signal_gen_top.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_int4_v2.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_sg_int4_v2_v1_0.tcl + tclSource + CHECKSUM_9465d594 + XGUI_VERSION_2 + + + + AXIS Signal Generator with x4 Interpolated Envelope, 32-bit phase+frequency + + + N + N + 12 + + + Component_Name + axis_sg_int4_v2_v1_0 + + + + + + zynquplus + + + /UserIP + + AXIS SG x4 Interpolation, V2 + package_project + 9 + 2024-08-09T19:23:37Z + + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + /home/lstefana/v20.2/ip/axis_sg_int4_v2 + + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/axis_sg_int4_v2/src/axi_slv.vhd b/firmware/ip/axis_sg_int4_v2/src/axi_slv.vhd new file mode 100644 index 0000000..c60ea98 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/axi_slv.vhd @@ -0,0 +1,516 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + START_ADDR_REG : out std_logic_vector (31 downto 0); + WE_REG : out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + -- 0 : START_ADDR_REG : 32-bit. Start address to write into memory. + -- 1 : WE_REG : 1-bit. Enable write into memory. + + -- Output Registers. + START_ADDR_REG <= slv_reg0; + WE_REG <= slv_reg1(0); + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/axis_sg_int4_v2.v b/firmware/ip/axis_sg_int4_v2/src/axis_sg_int4_v2.v new file mode 100644 index 0000000..fa1ffc3 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/axis_sg_int4_v2.v @@ -0,0 +1,197 @@ +// Signal Generator V4. +// s_axi_aclk : clock for s_axi_* +// s0_axis_aclk : clock for s0_axis_* +// aclk : clock for s1_axis_* and m_axis_* +// +module axis_sg_int4_v2 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // AXIS Slave to load memory samples. + s0_axis_aclk , + s0_axis_aresetn , + s0_axis_tdata , + s0_axis_tvalid , + s0_axis_tready , + + // s1_* and m_* reset/clock. + aclk , + aresetn , + + // AXIS Slave to queue waveforms. + s1_axis_tdata , + s1_axis_tvalid , + s1_axis_tready , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +parameter N = 12; + +// Number of parallel dds blocks. +localparam [31:0] N_DDS = 4; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input s0_axis_aclk; +input s0_axis_aresetn; +input [31:0] s0_axis_tdata; +input s0_axis_tvalid; +output s0_axis_tready; + +input aresetn; +input aclk; + +input [159:0] s1_axis_tdata; +input s1_axis_tvalid; +output s1_axis_tready; + +input m_axis_tready; +output m_axis_tvalid; +output [4*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] START_ADDR_REG; +wire WE_REG; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG ), + .WE_REG (WE_REG ) + ); + +signal_gen_top + #( + .N (N ), + .N_DDS (N_DDS ) + ) + signal_gen_top_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // AXIS Slave to load memory samples. + .s0_axis_aresetn (s0_axis_aresetn ), + .s0_axis_aclk (s0_axis_aclk ), + .s0_axis_tdata_i (s0_axis_tdata ), + .s0_axis_tvalid_i (s0_axis_tvalid ), + .s0_axis_tready_o (s0_axis_tready ), + + // AXIS Slave to queue waveforms. + .s1_axis_tdata_i (s1_axis_tdata ), + .s1_axis_tvalid_i (s1_axis_tvalid ), + .s1_axis_tready_o (s1_axis_tready ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_sg_int4_v2/src/bram.v b/firmware/ip/axis_sg_int4_v2/src/bram.v new file mode 100644 index 0000000..018317e --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/bram.v @@ -0,0 +1,33 @@ +module bram (clk,ena,wea,addra,dia,doa); + +// Memory address size. +parameter N = 16; +// Data width. +parameter B = 16; + +input clk; +input ena; +input wea; +input [N-1:0] addra; +input [B-1:0] dia; +output [B-1:0] doa; + +// Ram type. +reg [B-1:0] RAM [0:2**N-1]; +reg [B-1:0] doa; + +always @(posedge clk) +begin + if (ena) + begin + if (wea) begin + RAM[addra] <= dia; + end + else begin + doa <= RAM[addra]; + end + end +end + +endmodule + diff --git a/firmware/ip/axis_sg_int4_v2/src/ctrl.sv b/firmware/ip/axis_sg_int4_v2/src/ctrl.sv new file mode 100644 index 0000000..76767e5 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/ctrl.sv @@ -0,0 +1,497 @@ +//Format of waveform interface: +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// | 159 .. 149 | 148 | 147 | 146 | 145 .. 144 | 143 .. 128 | 127 .. 112 | 111 .. 96 | 95 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// | xxxx | phrst | stdysel | mode | outsel | nsamp | xxxx | gain | xxxx | addr | phase | freq | +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// freq : 32 bits +// phase : 32 bits +// addr : 16 bits +// gain : 16 bits +// nsamp : 16 bits +// outsel : 2 bits +// mode : 1 bit +// stdysel : 1 bit +// phrst : 1 bit +module ctrl ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // dds control. + dds_ctrl_o , + + // memory control. + mem_addr_o , + + // gain. + gain_o , + + // Output source selection. + src_o , + + // Steady value selection. + stdy_o , + + // Output enable. + en_o ); + +// Memory address size. +parameter N = 16; + +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 16; + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [159:0] fifo_dout_i; +output [N_DDS*72-1:0] dds_ctrl_o; +output [N-1:0] mem_addr_o; +output [15:0] gain_o; +output [1:0] src_o; +output stdy_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// Fifo dout register. +reg [159:0] fifo_dout_r; + +// Non-stop counter for time calculation (adds N_DDS samples each clock tick). +reg [31:0] cnt_n; +reg [31:0] cnt_n_reg; + +// Pinc/phase. +wire [31:0] pinc_int; +reg [31:0] pinc_r1; +reg [31:0] pinc_r2; +wire [31:0] pinc_N; +reg [31:0] pinc_N_r1; +reg [31:0] pinc_N_r2; +reg [31:0] pinc_N_r3; +reg [31:0] pinc_N_r4; +reg [31:0] pinc_N_r5; +wire [31:0] pinc_Nm; +reg [31:0] pinc_Nm_r1; +reg [31:0] pinc_Nm_r2; +reg [31:0] pinc_Nm_r3; + +wire [31:0] phase_int; +reg [31:0] phase_r1; +reg [31:0] phase_r2; +reg [31:0] phase_r3; +reg [31:0] phase_r4; +reg [31:0] phase_r5; +wire [31:0] phase_0; +reg [31:0] phase_0_r1; + +// Phase vectors. +wire [31:0] phase_v0 [0:N_DDS-1]; +reg [31:0] phase_v0_r1 [0:N_DDS-1]; +reg [31:0] phase_v0_r2 [0:N_DDS-1]; +reg [31:0] phase_v0_r3 [0:N_DDS-1]; +reg [31:0] phase_v0_r4 [0:N_DDS-1]; +wire [31:0] phase_v1 [0:N_DDS-1]; +reg [31:0] phase_v1_r1 [0:N_DDS-1]; + +// sync. +reg sync_reg; +reg sync_reg_r1; +reg sync_reg_r2; +reg sync_reg_r3; +reg sync_reg_r4; +reg sync_reg_r5; +reg sync_reg_r6; +reg sync_reg_r7; + +// Address. +wire [15:0] addr_int; +reg [15:0] addr_cnt; +reg [15:0] addr_cnt_r1; +reg [15:0] addr_cnt_r2; +reg [15:0] addr_cnt_r3; +reg [15:0] addr_cnt_r4; +reg [15:0] addr_cnt_r5; +reg [15:0] addr_cnt_r6; + +// Gain. +wire [15:0] gain_int; +reg [15:0] gain_r1; +reg [15:0] gain_r2; +reg [15:0] gain_r3; +reg [15:0] gain_r4; +reg [15:0] gain_r5; +reg [15:0] gain_r6; +reg [15:0] gain_r7; + +// Number of samples. +wire [15:0] nsamp_int; + +// Output selection. +wire [1:0] outsel_int; +reg [1:0] outsel_r1; +reg [1:0] outsel_r2; +reg [1:0] outsel_r3; +reg [1:0] outsel_r4; +reg [1:0] outsel_r5; +reg [1:0] outsel_r6; +reg [1:0] outsel_r7; + +// Mode. +wire mode_int; + +// Steady value selection. +wire stdysel_int; +reg stdysel_r1; +reg stdysel_r2; +reg stdysel_r3; +reg stdysel_r4; +reg stdysel_r5; +reg stdysel_r6; +reg stdysel_r7; + +// Phase reset. +wire phrst_int; + +// Load enable flag. +wire load_int; +reg load_r; + +// Fifo Read Enable. +reg rd_en_int; +reg rd_en_r1; +reg rd_en_r2; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +reg en_reg_r1; +reg en_reg_r2; +reg en_reg_r3; +reg en_reg_r4; +reg en_reg_r5; +reg en_reg_r6; +reg en_reg_r7; +reg en_reg_r8; + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Non-stop counter for time calculation. + cnt_n <= 0; + cnt_n_reg <= 0; + + // Pinc/phase/sync. + pinc_r1 <= 0; + pinc_r2 <= 0; + pinc_N_r1 <= 0; + pinc_N_r2 <= 0; + pinc_N_r3 <= 0; + pinc_N_r4 <= 0; + pinc_N_r5 <= 0; + pinc_Nm_r1 <= 0; + pinc_Nm_r2 <= 0; + pinc_Nm_r3 <= 0; + + phase_r1 <= 0; + phase_r2 <= 0; + phase_r3 <= 0; + phase_r4 <= 0; + phase_r5 <= 0; + phase_0_r1 <= 0; + + sync_reg <= 0; + sync_reg_r1 <= 0; + sync_reg_r2 <= 0; + sync_reg_r3 <= 0; + sync_reg_r4 <= 0; + sync_reg_r5 <= 0; + sync_reg_r6 <= 0; + sync_reg_r7 <= 0; + + // Address. + addr_cnt <= 0; + addr_cnt_r1 <= 0; + addr_cnt_r2 <= 0; + addr_cnt_r3 <= 0; + addr_cnt_r4 <= 0; + addr_cnt_r5 <= 0; + addr_cnt_r6 <= 0; + + // Gain. + gain_r1 <= 0; + gain_r2 <= 0; + gain_r3 <= 0; + gain_r4 <= 0; + gain_r5 <= 0; + gain_r6 <= 0; + gain_r7 <= 0; + + // Output selection. + outsel_r1 <= 0; + outsel_r2 <= 0; + outsel_r3 <= 0; + outsel_r4 <= 0; + outsel_r5 <= 0; + outsel_r6 <= 0; + outsel_r7 <= 0; + + // Steady value selection. + stdysel_r1 <= 0; + stdysel_r2 <= 0; + stdysel_r3 <= 0; + stdysel_r4 <= 0; + stdysel_r5 <= 0; + stdysel_r6 <= 0; + stdysel_r7 <= 0; + + // Load enable flag. + load_r <= 0; + + // Fifo Read Enable. + rd_en_r1 <= 0; + rd_en_r2 <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + en_reg_r1 <= 0; + en_reg_r2 <= 0; + en_reg_r3 <= 0; + en_reg_r4 <= 0; + en_reg_r5 <= 0; + en_reg_r6 <= 0; + en_reg_r7 <= 0; + en_reg_r8 <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (mode_int || ~fifo_empty_i) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Non-stop counter for time calculation. + if (sync_reg == 1'b1 && phrst_int == 1'b1) + cnt_n <= 0; + else + cnt_n <= cnt_n + N_DDS; + + if (sync_reg_r1 == 1'b1) + cnt_n_reg <= cnt_n; + + // Pinc/phase/sync. + pinc_r1 <= pinc_int; + pinc_r2 <= pinc_r1; + pinc_N_r1 <= pinc_N; + pinc_N_r2 <= pinc_N_r1; + pinc_N_r3 <= pinc_N_r2; + pinc_N_r4 <= pinc_N_r3; + pinc_N_r5 <= pinc_N_r4; + pinc_Nm_r1 <= pinc_Nm; + pinc_Nm_r2 <= pinc_Nm_r1; + pinc_Nm_r3 <= pinc_Nm_r2; + + phase_r1 <= phase_int; + phase_r2 <= phase_r1; + phase_r3 <= phase_r2; + phase_r4 <= phase_r3; + phase_r5 <= phase_r4; + phase_0_r1 <= phase_0; + + sync_reg <= load_r; + sync_reg_r1 <= sync_reg; + sync_reg_r2 <= sync_reg_r1; + sync_reg_r3 <= sync_reg_r2; + sync_reg_r4 <= sync_reg_r3; + sync_reg_r5 <= sync_reg_r4; + sync_reg_r6 <= sync_reg_r5; + sync_reg_r7 <= sync_reg_r6; + + // Address. + if (rd_en_r2) + addr_cnt <= addr_int; + else + addr_cnt <= addr_cnt + 1; + + addr_cnt_r1 <= addr_cnt; + addr_cnt_r2 <= addr_cnt_r1; + addr_cnt_r3 <= addr_cnt_r2; + addr_cnt_r4 <= addr_cnt_r3; + addr_cnt_r5 <= addr_cnt_r4; + addr_cnt_r6 <= addr_cnt_r5; + + // Gain. + gain_r1 <= gain_int; + gain_r2 <= gain_r1; + gain_r3 <= gain_r2; + gain_r4 <= gain_r3; + gain_r5 <= gain_r4; + gain_r6 <= gain_r5; + gain_r7 <= gain_r6; + + // Output selection. + outsel_r1 <= outsel_int; + outsel_r2 <= outsel_r1; + outsel_r3 <= outsel_r2; + outsel_r4 <= outsel_r3; + outsel_r5 <= outsel_r4; + outsel_r6 <= outsel_r5; + outsel_r7 <= outsel_r6; + + // Steady value selection. + stdysel_r1 <= stdysel_int; + stdysel_r2 <= stdysel_r1; + stdysel_r3 <= stdysel_r2; + stdysel_r4 <= stdysel_r3; + stdysel_r5 <= stdysel_r4; + stdysel_r6 <= stdysel_r5; + stdysel_r7 <= stdysel_r6; + + // Load enable flag. + load_r <= load_int; + + // Fifo Read Enable. + rd_en_r1 <= rd_en_int; + rd_en_r2 <= rd_en_r1; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (~mode_int && rd_en_int) + if (~fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + + en_reg_r1 <= en_reg; + en_reg_r2 <= en_reg_r1; + en_reg_r3 <= en_reg_r2; + en_reg_r4 <= en_reg_r3; + en_reg_r5 <= en_reg_r4; + en_reg_r6 <= en_reg_r5; + en_reg_r7 <= en_reg_r6; + en_reg_r8 <= en_reg_r7; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign pinc_int = fifo_dout_r[31:0]; +assign phase_int = fifo_dout_r[63:32]; +assign addr_int = fifo_dout_r[79:64]; +assign gain_int = fifo_dout_r[111:96]; +assign nsamp_int = fifo_dout_r[143:128]; +assign outsel_int = fifo_dout_r[145:144]; +assign mode_int = fifo_dout_r[146]; +assign stdysel_int = fifo_dout_r[147]; +assign phrst_int = fifo_dout_r[148]; + +// Frequency calculation. +assign pinc_N = pinc_r2*N_DDS; + +// Phase calculation. +assign pinc_Nm = pinc_r2*cnt_n_reg; +assign phase_0 = pinc_Nm_r3 + phase_r5; + +// Phase vectors. +generate +genvar i; + for (i=0; i < N_DDS; i = i + 1) begin : GEN_phase + // Registers. + always @(posedge clk) begin + if (~rstn) begin + // v0. + phase_v0_r1[i] <= 0; + phase_v0_r2[i] <= 0; + phase_v0_r3[i] <= 0; + phase_v0_r4[i] <= 0; + + // v1. + phase_v1_r1[i] <= 0; + end + else begin + // v0. + phase_v0_r1[i] <= phase_v0[i]; + phase_v0_r2[i] <= phase_v0_r1[i]; + phase_v0_r3[i] <= phase_v0_r2[i]; + phase_v0_r4[i] <= phase_v0_r3[i]; + + // v1. + phase_v1_r1[i] <= phase_v1[i]; + end + end + + // v0. + assign phase_v0[i] = pinc_r2*i; + + // v1. + assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; + + // dds_ctrl_o output. + assign dds_ctrl_o[i*72 +: 72] = {7'h00,sync_reg_r7,phase_v1_r1[i],pinc_N_r5}; + end +endgenerate + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mem_addr_o = addr_cnt_r6; +assign gain_o = gain_r7; +assign src_o = outsel_r7; +assign stdy_o = stdysel_r7; +assign en_o = en_reg_r8; + +endmodule + diff --git a/firmware/ip/axis_sg_int4_v2/src/data_writer.vhd b/firmware/ip/axis_sg_int4_v2/src/data_writer.vhd new file mode 100644 index 0000000..8fa76e3 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/data_writer.vhd @@ -0,0 +1,200 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity data_writer is + Generic + ( + -- Memory size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in STD_LOGIC; + clk : in STD_LOGIC; + + -- AXI Stream I/F. + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- Memory I/F. + mem_en : out std_logic; + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_di : out std_logic_vector (B-1 downto 0); + + -- Registers. + START_ADDR_REG : in std_logic_vector (31 downto 0); + WE_REG : in std_logic + ); +end data_writer; + +architecture rtl of data_writer is + +-- Synchronizer. +component synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end component; + +-- State machine. +type fsm_state is ( INIT_ST , + READ_START_ADDR_ST , + WAIT_TVALID_ST , + RW_TDATA_ST ); +signal state : fsm_state; + +signal read_start_addr_state : std_logic; +signal rw_tdata_state : std_logic; + +-- WE_REG_resync. +signal WE_REG_resync : std_logic; + +-- Axis registers. +signal tready_i : std_logic; +signal tready_r : std_logic; +signal tdata_r : std_logic_vector(B-1 downto 0); +signal tdata_rr : std_logic_vector(B-1 downto 0); +signal tdata_rrr : std_logic_vector(B-1 downto 0); +signal tvalid_r : std_logic; +signal tvalid_rr : std_logic; +signal tvalid_rrr : std_logic; + +-- Memory address space. +signal mem_addr_full : unsigned (N-1 downto 0); +signal mem_addr_full_r : unsigned (N-1 downto 0); + +begin + +-- WE_REG_resync +WE_REG_resync_i : synchronizer_n + generic map ( + N => 2 + ) + port map ( + rstn => rstn , + clk => clk , + data_in => WE_REG , + data_out => WE_REG_resync + ); + +process (clk) +begin + if ( rising_edge(clk) ) then + if (rstn = '0') then + -- Axis registers. + tready_r <= '0'; + tdata_r <= (others => '0'); + tdata_rr <= (others => '0'); + tdata_rrr <= (others => '0'); + tvalid_r <= '0'; + tvalid_rr <= '0'; + tvalid_rrr <= '0'; + + -- Memory address. + mem_addr_full <= (others => '0'); + mem_addr_full_r <= (others => '0'); + else + -- Axis registers. + tready_r <= tready_i; + tdata_r <= s_axis_tdata; + tvalid_r <= s_axis_tvalid; + + -- Extra registers to account pipe of state machine. + tdata_rr <= tdata_r; + tdata_rrr <= tdata_rr; + tvalid_rr <= tvalid_r; + tvalid_rrr <= tvalid_rr; + + -- Memory address. + if ( read_start_addr_state = '1') then + mem_addr_full <= to_unsigned(to_integer(unsigned(START_ADDR_REG)),mem_addr_full'length); + elsif ( rw_tdata_state = '1' ) then + mem_addr_full <= mem_addr_full + 1; + end if; + mem_addr_full_r <= mem_addr_full; + + end if; + end if; +end process; + +-- Finite state machine. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + state <= INIT_ST; + else + case state is + when INIT_ST => + if ( WE_REG_resync = '1' ) then + state <= READ_START_ADDR_ST; + end if; + + when READ_START_ADDR_ST => + state <= WAIT_TVALID_ST; + + when WAIT_TVALID_ST => + if ( WE_REG_resync = '1') then + if ( tvalid_r = '0' ) then + state <= WAIT_TVALID_ST; + else + state <= RW_TDATA_ST; + end if; + else + state <= INIT_ST; + end if; + + when RW_TDATA_ST => + if ( tvalid_r = '0' ) then + state <= WAIT_TVALID_ST; + end if; + + end case; + end if; + end if; +end process; + +-- Output logic. +process (state) +begin +read_start_addr_state <= '0'; +rw_tdata_state <= '0'; +tready_i <= '0'; + case state is + when INIT_ST => + + when READ_START_ADDR_ST => + read_start_addr_state <= '1'; + + when WAIT_TVALID_ST => + tready_i <= '1'; + + when RW_TDATA_ST => + rw_tdata_state <= '1'; + tready_i <= '1'; + + end case; +end process; + +-- Assign output. +s_axis_tready <= tready_r; + +mem_en <= '1'; +mem_we <= tvalid_rrr; +mem_addr <= std_logic_vector(mem_addr_full_r); +mem_di <= tdata_rrr; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_sg_int4_v2/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 0000000..aae0f7e --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,476 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_compiler_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 9 + 0 + 0 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 10 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 72 + 1 + 1 + zynquplus + Full_Range + 1 + dds_compiler_0 + Not_Required + 256 + Maximal + 0.06 + Coregen + false + false + false + false + 10 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + false + Auto + Twos_Complement + Speed + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 22 + TRUE + ../../../../qick_fw_sho/qick_tprocv2_216_q3diamond/top/top.tmp/axis_sg_int4_v2_v1_0_project/axis_sg_int4_v2_v1_0_project.gen/sources_1/ip/dds_compiler_0 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/bin2gray.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/bin2gray.vhd new file mode 100644 index 0000000..4ecc09b --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/bin2gray.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end bin2gray; + +architecture rtl of bin2gray is + +signal gray : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +gray(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + gray(I) <= din(I+1) xor din(I); +end generate; + +-- Assign output. +dout <= gray; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/bram_dp.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/bram_dp.vhd new file mode 100644 index 0000000..d57aad1 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/bram_dp.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture rtl of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/bram_simple_dp.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/bram_simple_dp.vhd new file mode 100644 index 0000000..1494332 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/bram_simple_dp.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_simple_dp; + +architecture rtl of bram_simple_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/fifo.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/fifo.vhd new file mode 100644 index 0000000..957362b --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/fifo.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture rtl of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Dual port, single clock BRAM. +component bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- FIFO memory. +mem_i : bram_simple_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/fifo_axi.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/fifo_dc.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/gray2bin.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/rd2axi.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_sg_int4_v2/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/src/fir_0/fir_0.coe b/firmware/ip/axis_sg_int4_v2/src/fir_0/fir_0.coe new file mode 100644 index 0000000..fd9c445 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fir_0/fir_0.coe @@ -0,0 +1,2 @@ +Radix = 10; +CoefData = 0.004708,0.005461,0.000000,-0.013987,-0.029332,-0.030123,0.000000,0.065216,0.149630,0.221652,0.250000,0.221652,0.149630,0.065216,0.000000,-0.030123,-0.029332,-0.013987,0.000000,0.005461,0.004708 \ No newline at end of file diff --git a/firmware/ip/axis_sg_int4_v2/src/fir_0/fir_0.xci b/firmware/ip/axis_sg_int4_v2/src/fir_0/fir_0.xci new file mode 100644 index 0000000..c666491 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/fir_0/fir_0.xci @@ -0,0 +1,475 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fir_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 16 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 31,31,31,31,31,31,31,31 + 31,31,31,31,31,31,31,31 + fixed + fir_0.mif + 24 + 2 + 0 + 0,0,0,0,0,0,0,0 + 0,0,2,2,4,4,6,6 + 16,16,16,16,16,16,16,16 + 0 + 16 + 6 + 1 + 4 + fir_0 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + -0;-1;-0;-1;-0;-1;-0;-1 + 0,0,0,0,0,0,0,0 + 0,1,0,1,0,1,0,1 + 16,16,16,16,16,16,16,16 + 16,16 + 16 + 1 + ./ + none + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 12 + 2 + 0 + 0 + 128 + 1 + 1 + 1 + 6 + 1 + 21 + 0 + 0 + none;none;none;none + -0;-1;-0;-1;-0;-1;-0;-1 + 16,16,16,16,16,16,16,16 + 1 + 16 + 1 + 0,1,2,3,4,5,6,7 + 1 + 3 + 0 + 0 + 0 + 32 + 1 + zynquplus + 1 + true + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + false + fir_0.coe + 16 + false + 1 + Signed + Inferred + 16 + 6 + fir_0 + false + false + false + false + Not_Required + 1 + Automatic + 0 + false + false + Signed + 16 + 1 + false + false + Systolic_Multiply_Accumulate + 1 + Interpolation + Coregen + false + false + false + 1 + false + false + Automatic + 4 + 4 + false + Not_Required + Automatic + false + false + 1 + 1 + 2 + false + Area + None + None + false + Automatic + Symmetric_Rounding_to_Infinity + 16 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + false + Automatic + Quantize_Only + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + false + Not_Required + 1 + 0.001 + All + 1.0 + 0.5 + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 18 + TRUE + ../../../../qick_fw_sho/qick_tprocv2_216_q3diamond/top/top.tmp/axis_sg_int4_v2_v1_0_project/axis_sg_int4_v2_v1_0_project.gen/sources_1/ip/fir_0 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_sg_int4_v2/src/latency_reg.v b/firmware/ip/axis_sg_int4_v2/src/latency_reg.v new file mode 100644 index 0000000..687a9f3 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_int4_v2/xgui/axis_sg_int4_v2_v1_0.tcl b/firmware/ip/axis_sg_int4_v2/xgui/axis_sg_int4_v2_v1_0.tcl new file mode 100644 index 0000000..96e9e44 --- /dev/null +++ b/firmware/ip/axis_sg_int4_v2/xgui/axis_sg_int4_v2_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "N" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + diff --git a/firmware/ip/axis_sg_mixmux8_v1/component.xml b/firmware/ip/axis_sg_mixmux8_v1/component.xml new file mode 100644 index 0000000..2201c3a --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/component.xml @@ -0,0 +1,1070 @@ + + + user.org + user + axis_sg_mixmux8_v1 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_sg_mixmux8_v1 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + c63381eb + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_sg_mixmux8_v1 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + c63381eb + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 429ef1d0 + + + + + xilinx_testbench + Test Bench + :vivado.xilinx.com:simulation.testbench + tb + + xilinx_testbench_view_fileset + + + + viewChecksum + 4813f2bb + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 39 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N_DDS + N Dds + 2 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux8_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i + + + src/axi_slv.v + verilogSource + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/mult_32x32.v + verilogSource + + + src/sg_mux8.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mixmux8_v1.v + verilogSource + CHECKSUM_fbb8f9e5 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux8_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i + + + src/axi_slv.v + verilogSource + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/mult_32x32.v + verilogSource + + + src/sg_mux8.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mixmux8_v1.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_sg_mixmux8_v1_v1_0.tcl + tclSource + CHECKSUM_429ef1d0 + XGUI_VERSION_2 + + + + xilinx_testbench_view_fileset + + src/tb/tb.sv + systemVerilogSource + + + + AXIS SG Mux8, IQ Output, V1. + + + N_DDS + N Dds + 2 + + + Component_Name + axis_sg_mixmux8_v1_v1_0 + + + + + + zynquplus + + + /UserIP + + AXIS SG Mixer-Mux8, V1 + package_project + 5 + 2024-08-05T23:24:03Z + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/axi_slv.v b/firmware/ip/axis_sg_mixmux8_v1/src/axi_slv.v new file mode 100644 index 0000000..a7089bb --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/axi_slv.v @@ -0,0 +1,1072 @@ +`timescale 1 ns / 1 ps + +module axi_slv + ( + input wire s_axi_aclk , + input wire s_axi_aresetn , + + // Write Address Channel. + input wire [7:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + + // Write Data Channel. + input wire [31:0] s_axi_wdata , + input wire [3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + + // Write Response Channel. + output wire [1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + + // Read Address Channel. + input wire [7:0] s_axi_araddr , + input wire [2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + + // Read Data Channel. + output wire [31:0] s_axi_rdata , + output wire [1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , + + // Registers. + output wire [31:0] PINC0_REG , + output wire [31:0] PINC1_REG , + output wire [31:0] PINC2_REG , + output wire [31:0] PINC3_REG , + output wire [31:0] PINC4_REG , + output wire [31:0] PINC5_REG , + output wire [31:0] PINC6_REG , + output wire [31:0] PINC7_REG , + output wire [31:0] POFF0_REG , + output wire [31:0] POFF1_REG , + output wire [31:0] POFF2_REG , + output wire [31:0] POFF3_REG , + output wire [31:0] POFF4_REG , + output wire [31:0] POFF5_REG , + output wire [31:0] POFF6_REG , + output wire [31:0] POFF7_REG , + output wire [31:0] GAIN0_REG , + output wire [31:0] GAIN1_REG , + output wire [31:0] GAIN2_REG , + output wire [31:0] GAIN3_REG , + output wire [31:0] GAIN4_REG , + output wire [31:0] GAIN5_REG , + output wire [31:0] GAIN6_REG , + output wire [31:0] GAIN7_REG , + output wire WE_REG +); + +// Width of S_AXI data bus +localparam integer C_S_AXI_DATA_WIDTH = 32; +// Width of S_AXI address bus +localparam integer C_S_AXI_ADDR_WIDTH = 8; + +// AXI4LITE signals +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr; +reg axi_awready; +reg axi_wready; +reg [1 : 0] axi_bresp; +reg axi_bvalid; +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr; +reg axi_arready; +reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata; +reg [1 : 0] axi_rresp; +reg axi_rvalid; + +// Example-specific design signals +// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH +// ADDR_LSB is used for addressing 32/64 bit registers/memories +// ADDR_LSB = 2 for 32 bits (n downto 2) +// ADDR_LSB = 3 for 64 bits (n downto 3) +localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1; +localparam integer OPT_MEM_ADDR_BITS = 5; +//---------------------------------------------- +//-- Signals for user logic register space example +//------------------------------------------------ +//-- Number of Slave Registers 64 +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg32; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg33; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg34; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg35; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg36; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg37; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg38; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg39; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg40; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg41; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg42; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg43; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg44; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg45; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg46; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg47; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg48; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg49; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg50; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg51; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg52; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg53; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg54; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg55; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg56; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg57; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg58; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg59; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg60; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg61; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg62; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg63; +wire slv_reg_rden; +wire slv_reg_wren; +reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out; +integer byte_index; +reg aw_en; + +// I/O Connections assignments + +assign s_axi_awready = axi_awready; +assign s_axi_wready = axi_wready; +assign s_axi_bresp = axi_bresp; +assign s_axi_bvalid = axi_bvalid; +assign s_axi_arready = axi_arready; +assign s_axi_rdata = axi_rdata; +assign s_axi_rresp = axi_rresp; +assign s_axi_rvalid = axi_rvalid; +// Implement axi_awready generation +// axi_awready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_awready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awready <= 1'b0; + aw_en <= 1'b1; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // slave is ready to accept write address when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_awready <= 1'b1; + aw_en <= 1'b0; + end + else if (s_axi_bready && axi_bvalid) + begin + aw_en <= 1'b1; + axi_awready <= 1'b0; + end + else + begin + axi_awready <= 1'b0; + end + end +end + +// Implement axi_awaddr latching +// This process is used to latch the address when both +// s_axi_awvalid and s_axi_wvalid are valid. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awaddr <= 0; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // Write Address latching + axi_awaddr <= s_axi_awaddr; + end + end +end + +// Implement axi_wready generation +// axi_wready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_wready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_wready <= 1'b0; + end + else + begin + if (~axi_wready && s_axi_wvalid && s_axi_awvalid && aw_en ) + begin + // slave is ready to accept write data when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_wready <= 1'b1; + end + else + begin + axi_wready <= 1'b0; + end + end +end + +// Implement memory mapped register select and write logic generation +// The write data is accepted and written to memory mapped registers when +// axi_awready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. Write strobes are used to +// select byte enables of slave registers while writing. +// These registers are cleared when reset (active low) is applied. +// Slave register write enable is asserted when valid address and data are available +// and the slave is ready to accept the write address and write data. +assign slv_reg_wren = axi_wready && s_axi_wvalid && axi_awready && s_axi_awvalid; + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + slv_reg0 <= 0; + slv_reg1 <= 0; + slv_reg2 <= 0; + slv_reg3 <= 0; + slv_reg4 <= 0; + slv_reg5 <= 0; + slv_reg6 <= 0; + slv_reg7 <= 0; + slv_reg8 <= 0; + slv_reg9 <= 0; + slv_reg10 <= 0; + slv_reg11 <= 0; + slv_reg12 <= 0; + slv_reg13 <= 0; + slv_reg14 <= 0; + slv_reg15 <= 0; + slv_reg16 <= 0; + slv_reg17 <= 0; + slv_reg18 <= 0; + slv_reg19 <= 0; + slv_reg20 <= 0; + slv_reg21 <= 0; + slv_reg22 <= 0; + slv_reg23 <= 0; + slv_reg24 <= 0; + slv_reg25 <= 0; + slv_reg26 <= 0; + slv_reg27 <= 0; + slv_reg28 <= 0; + slv_reg29 <= 0; + slv_reg30 <= 0; + slv_reg31 <= 0; + slv_reg32 <= 0; + slv_reg33 <= 0; + slv_reg34 <= 0; + slv_reg35 <= 0; + slv_reg36 <= 0; + slv_reg37 <= 0; + slv_reg38 <= 0; + slv_reg39 <= 0; + slv_reg40 <= 0; + slv_reg41 <= 0; + slv_reg42 <= 0; + slv_reg43 <= 0; + slv_reg44 <= 0; + slv_reg45 <= 0; + slv_reg46 <= 0; + slv_reg47 <= 0; + slv_reg48 <= 0; + slv_reg49 <= 0; + slv_reg50 <= 0; + slv_reg51 <= 0; + slv_reg52 <= 0; + slv_reg53 <= 0; + slv_reg54 <= 0; + slv_reg55 <= 0; + slv_reg56 <= 0; + slv_reg57 <= 0; + slv_reg58 <= 0; + slv_reg59 <= 0; + slv_reg60 <= 0; + slv_reg61 <= 0; + slv_reg62 <= 0; + slv_reg63 <= 0; + end + else begin + if (slv_reg_wren) + begin + case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 0 + slv_reg0[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h01: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 1 + slv_reg1[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h02: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 2 + slv_reg2[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h03: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 3 + slv_reg3[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h04: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 4 + slv_reg4[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h05: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 5 + slv_reg5[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h06: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 6 + slv_reg6[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h07: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 7 + slv_reg7[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h08: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 8 + slv_reg8[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h09: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 9 + slv_reg9[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 10 + slv_reg10[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 11 + slv_reg11[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 12 + slv_reg12[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 13 + slv_reg13[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 14 + slv_reg14[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 15 + slv_reg15[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h10: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 16 + slv_reg16[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h11: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 17 + slv_reg17[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h12: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 18 + slv_reg18[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h13: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 19 + slv_reg19[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h14: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 20 + slv_reg20[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h15: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 21 + slv_reg21[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h16: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 22 + slv_reg22[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h17: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 23 + slv_reg23[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h18: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 24 + slv_reg24[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h19: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 25 + slv_reg25[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 26 + slv_reg26[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 27 + slv_reg27[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 28 + slv_reg28[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 29 + slv_reg29[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 30 + slv_reg30[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 31 + slv_reg31[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h20: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 32 + slv_reg32[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h21: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 33 + slv_reg33[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h22: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 34 + slv_reg34[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h23: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 35 + slv_reg35[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h24: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 36 + slv_reg36[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h25: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 37 + slv_reg37[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h26: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 38 + slv_reg38[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h27: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 39 + slv_reg39[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h28: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 40 + slv_reg40[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h29: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 41 + slv_reg41[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 42 + slv_reg42[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 43 + slv_reg43[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 44 + slv_reg44[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 45 + slv_reg45[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 46 + slv_reg46[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 47 + slv_reg47[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h30: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 48 + slv_reg48[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h31: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 49 + slv_reg49[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h32: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 50 + slv_reg50[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h33: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 51 + slv_reg51[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h34: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 52 + slv_reg52[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h35: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 53 + slv_reg53[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h36: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 54 + slv_reg54[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h37: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 55 + slv_reg55[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h38: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 56 + slv_reg56[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h39: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 57 + slv_reg57[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 58 + slv_reg58[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 59 + slv_reg59[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 60 + slv_reg60[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 61 + slv_reg61[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 62 + slv_reg62[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 63 + slv_reg63[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + default : begin + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + slv_reg16 <= slv_reg16; + slv_reg17 <= slv_reg17; + slv_reg18 <= slv_reg18; + slv_reg19 <= slv_reg19; + slv_reg20 <= slv_reg20; + slv_reg21 <= slv_reg21; + slv_reg22 <= slv_reg22; + slv_reg23 <= slv_reg23; + slv_reg24 <= slv_reg24; + slv_reg25 <= slv_reg25; + slv_reg26 <= slv_reg26; + slv_reg27 <= slv_reg27; + slv_reg28 <= slv_reg28; + slv_reg29 <= slv_reg29; + slv_reg30 <= slv_reg30; + slv_reg31 <= slv_reg31; + slv_reg32 <= slv_reg32; + slv_reg33 <= slv_reg33; + slv_reg34 <= slv_reg34; + slv_reg35 <= slv_reg35; + slv_reg36 <= slv_reg36; + slv_reg37 <= slv_reg37; + slv_reg38 <= slv_reg38; + slv_reg39 <= slv_reg39; + slv_reg40 <= slv_reg40; + slv_reg41 <= slv_reg41; + slv_reg42 <= slv_reg42; + slv_reg43 <= slv_reg43; + slv_reg44 <= slv_reg44; + slv_reg45 <= slv_reg45; + slv_reg46 <= slv_reg46; + slv_reg47 <= slv_reg47; + slv_reg48 <= slv_reg48; + slv_reg49 <= slv_reg49; + slv_reg50 <= slv_reg50; + slv_reg51 <= slv_reg51; + slv_reg52 <= slv_reg52; + slv_reg53 <= slv_reg53; + slv_reg54 <= slv_reg54; + slv_reg55 <= slv_reg55; + slv_reg56 <= slv_reg56; + slv_reg57 <= slv_reg57; + slv_reg58 <= slv_reg58; + slv_reg59 <= slv_reg59; + slv_reg60 <= slv_reg60; + slv_reg61 <= slv_reg61; + slv_reg62 <= slv_reg62; + slv_reg63 <= slv_reg63; + end + endcase + end + end +end + +// Implement write response logic generation +// The write response and response valid signals are asserted by the slave +// when axi_wready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. +// This marks the acceptance of address and indicates the status of +// write transaction. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_bvalid <= 0; + axi_bresp <= 2'b0; + end + else + begin + if (axi_awready && s_axi_awvalid && ~axi_bvalid && axi_wready && s_axi_wvalid) + begin + // indicates a valid write response is available + axi_bvalid <= 1'b1; + axi_bresp <= 2'b0; // 'OKAY' response + end // work error responses in future + else + begin + if (s_axi_bready && axi_bvalid) + //check if bready is asserted while bvalid is high) + //(there is a possibility that bready is always asserted high) + begin + axi_bvalid <= 1'b0; + end + end + end +end + +// Implement axi_arready generation +// axi_arready is asserted for one s_axi_aclk clock cycle when +// s_axi_arvalid is asserted. axi_awready is +// de-asserted when reset (active low) is asserted. +// The read address is also latched when s_axi_arvalid is +// asserted. axi_araddr is reset to zero on reset assertion. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_arready <= 1'b0; + axi_araddr <= 32'b0; + end + else + begin + if (~axi_arready && s_axi_arvalid) + begin + // indicates that the slave has acceped the valid read address + axi_arready <= 1'b1; + // Read address latching + axi_araddr <= s_axi_araddr; + end + else + begin + axi_arready <= 1'b0; + end + end +end + +// Implement axi_arvalid generation +// axi_rvalid is asserted for one s_axi_aclk clock cycle when both +// s_axi_arvalid and axi_arready are asserted. The slave registers +// data are available on the axi_rdata bus at this instance. The +// assertion of axi_rvalid marks the validity of read data on the +// bus and axi_rresp indicates the status of read transaction.axi_rvalid +// is deasserted on reset (active low). axi_rresp and axi_rdata are +// cleared to zero on reset (active low). +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rvalid <= 0; + axi_rresp <= 0; + end + else + begin + if (axi_arready && s_axi_arvalid && ~axi_rvalid) + begin + // Valid read data is available at the read data bus + axi_rvalid <= 1'b1; + axi_rresp <= 2'b0; // 'OKAY' response + end + else if (axi_rvalid && s_axi_rready) + begin + // Read data is accepted by the master + axi_rvalid <= 1'b0; + end + end +end + +// Implement memory mapped register select and read logic generation +// Slave register read enable is asserted when valid address is available +// and the slave is ready to accept the read address. +assign slv_reg_rden = axi_arready & s_axi_arvalid & ~axi_rvalid; +always @(*) +begin + // Address decoding for reading registers + case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00 : reg_data_out <= slv_reg0; + 6'h01 : reg_data_out <= slv_reg1; + 6'h02 : reg_data_out <= slv_reg2; + 6'h03 : reg_data_out <= slv_reg3; + 6'h04 : reg_data_out <= slv_reg4; + 6'h05 : reg_data_out <= slv_reg5; + 6'h06 : reg_data_out <= slv_reg6; + 6'h07 : reg_data_out <= slv_reg7; + 6'h08 : reg_data_out <= slv_reg8; + 6'h09 : reg_data_out <= slv_reg9; + 6'h0A : reg_data_out <= slv_reg10; + 6'h0B : reg_data_out <= slv_reg11; + 6'h0C : reg_data_out <= slv_reg12; + 6'h0D : reg_data_out <= slv_reg13; + 6'h0E : reg_data_out <= slv_reg14; + 6'h0F : reg_data_out <= slv_reg15; + 6'h10 : reg_data_out <= slv_reg16; + 6'h11 : reg_data_out <= slv_reg17; + 6'h12 : reg_data_out <= slv_reg18; + 6'h13 : reg_data_out <= slv_reg19; + 6'h14 : reg_data_out <= slv_reg20; + 6'h15 : reg_data_out <= slv_reg21; + 6'h16 : reg_data_out <= slv_reg22; + 6'h17 : reg_data_out <= slv_reg23; + 6'h18 : reg_data_out <= slv_reg24; + 6'h19 : reg_data_out <= slv_reg25; + 6'h1A : reg_data_out <= slv_reg26; + 6'h1B : reg_data_out <= slv_reg27; + 6'h1C : reg_data_out <= slv_reg28; + 6'h1D : reg_data_out <= slv_reg29; + 6'h1E : reg_data_out <= slv_reg30; + 6'h1F : reg_data_out <= slv_reg31; + 6'h20 : reg_data_out <= slv_reg32; + 6'h21 : reg_data_out <= slv_reg33; + 6'h22 : reg_data_out <= slv_reg34; + 6'h23 : reg_data_out <= slv_reg35; + 6'h24 : reg_data_out <= slv_reg36; + 6'h25 : reg_data_out <= slv_reg37; + 6'h26 : reg_data_out <= slv_reg38; + 6'h27 : reg_data_out <= slv_reg39; + 6'h28 : reg_data_out <= slv_reg40; + 6'h29 : reg_data_out <= slv_reg41; + 6'h2A : reg_data_out <= slv_reg42; + 6'h2B : reg_data_out <= slv_reg43; + 6'h2C : reg_data_out <= slv_reg44; + 6'h2D : reg_data_out <= slv_reg45; + 6'h2E : reg_data_out <= slv_reg46; + 6'h2F : reg_data_out <= slv_reg47; + 6'h30 : reg_data_out <= slv_reg48; + 6'h31 : reg_data_out <= slv_reg49; + 6'h32 : reg_data_out <= slv_reg50; + 6'h33 : reg_data_out <= slv_reg51; + 6'h34 : reg_data_out <= slv_reg52; + 6'h35 : reg_data_out <= slv_reg53; + 6'h36 : reg_data_out <= slv_reg54; + 6'h37 : reg_data_out <= slv_reg55; + 6'h38 : reg_data_out <= slv_reg56; + 6'h39 : reg_data_out <= slv_reg57; + 6'h3A : reg_data_out <= slv_reg58; + 6'h3B : reg_data_out <= slv_reg59; + 6'h3C : reg_data_out <= slv_reg60; + 6'h3D : reg_data_out <= slv_reg61; + 6'h3E : reg_data_out <= slv_reg62; + 6'h3F : reg_data_out <= slv_reg63; + default : reg_data_out <= 0; + endcase +end + +// Output register or memory read data +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rdata <= 0; + end + else + begin + // When there is a valid read address (s_axi_arvalid) with + // acceptance of read address by the slave (axi_arready), + // output the read dada + if (slv_reg_rden) + begin + axi_rdata <= reg_data_out; // register read data + end + end +end + +assign PINC0_REG = slv_reg0 ; +assign PINC1_REG = slv_reg1 ; +assign PINC2_REG = slv_reg2 ; +assign PINC3_REG = slv_reg3 ; +assign PINC4_REG = slv_reg4 ; +assign PINC5_REG = slv_reg5 ; +assign PINC6_REG = slv_reg6 ; +assign PINC7_REG = slv_reg7 ; +assign POFF0_REG = slv_reg8 ; +assign POFF1_REG = slv_reg9 ; +assign POFF2_REG = slv_reg10 ; +assign POFF3_REG = slv_reg11 ; +assign POFF4_REG = slv_reg12 ; +assign POFF5_REG = slv_reg13 ; +assign POFF6_REG = slv_reg14 ; +assign POFF7_REG = slv_reg15 ; +assign GAIN0_REG = slv_reg16 ; +assign GAIN1_REG = slv_reg17 ; +assign GAIN2_REG = slv_reg18 ; +assign GAIN3_REG = slv_reg19 ; +assign GAIN4_REG = slv_reg20 ; +assign GAIN5_REG = slv_reg21 ; +assign GAIN6_REG = slv_reg22 ; +assign GAIN7_REG = slv_reg23 ; +assign WE_REG = slv_reg24[0] ; + +endmodule diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/axis_sg_mixmux8_v1.v b/firmware/ip/axis_sg_mixmux8_v1/src/axis_sg_mixmux8_v1.v new file mode 100644 index 0000000..94bb1a8 --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/axis_sg_mixmux8_v1.v @@ -0,0 +1,238 @@ +module axis_sg_mixmux8_v1 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // s_* and m_* reset/clock. + aclk , + aresetn , + + // S_AXIS to queue waveforms. + s_axis_tready , + s_axis_tvalid , + s_axis_tdata , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [7:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [7:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [39:0] s_axis_tdata; + +input m_axis_tready; +output m_axis_tvalid; +output [N_DDS*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] PINC0_REG; +wire [31:0] PINC1_REG; +wire [31:0] PINC2_REG; +wire [31:0] PINC3_REG; +wire [31:0] PINC4_REG; +wire [31:0] PINC5_REG; +wire [31:0] PINC6_REG; +wire [31:0] PINC7_REG; +wire [31:0] POFF0_REG; +wire [31:0] POFF1_REG; +wire [31:0] POFF2_REG; +wire [31:0] POFF3_REG; +wire [31:0] POFF4_REG; +wire [31:0] POFF5_REG; +wire [31:0] POFF6_REG; +wire [31:0] POFF7_REG; +wire [15:0] GAIN0_REG; +wire [15:0] GAIN1_REG; +wire [15:0] GAIN2_REG; +wire [15:0] GAIN3_REG; +wire [15:0] GAIN4_REG; +wire [15:0] GAIN5_REG; +wire [15:0] GAIN6_REG; +wire [15:0] GAIN7_REG; +wire WE_REG; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + + // Write Address Channel. + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_awready (s_axi_awready ), + + // Write Data Channel. + .s_axi_wdata (s_axi_wdata ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + .s_axi_wready (s_axi_wready ), + + // Write Response Channel. + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_bready (s_axi_bready ), + + // Read Address Channel. + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_arready (s_axi_arready ), + + // Read Data Channel. + .s_axi_rdata (s_axi_rdata ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_rready (s_axi_rready ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .PINC4_REG (PINC4_REG ), + .PINC5_REG (PINC5_REG ), + .PINC6_REG (PINC6_REG ), + .PINC7_REG (PINC7_REG ), + .POFF0_REG (POFF0_REG ), + .POFF1_REG (POFF1_REG ), + .POFF2_REG (POFF2_REG ), + .POFF3_REG (POFF3_REG ), + .POFF4_REG (POFF4_REG ), + .POFF5_REG (POFF5_REG ), + .POFF6_REG (POFF6_REG ), + .POFF7_REG (POFF7_REG ), + .GAIN0_REG (GAIN0_REG ), + .GAIN1_REG (GAIN1_REG ), + .GAIN2_REG (GAIN2_REG ), + .GAIN3_REG (GAIN3_REG ), + .GAIN4_REG (GAIN4_REG ), + .GAIN5_REG (GAIN5_REG ), + .GAIN6_REG (GAIN6_REG ), + .GAIN7_REG (GAIN7_REG ), + .WE_REG (WE_REG ) + ); + +sg_mux8 + #( + .N_DDS (N_DDS ) + ) + sg_mux8_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready_o (s_axis_tready ), + .s_axis_tvalid_i (s_axis_tvalid ), + .s_axis_tdata_i (s_axis_tdata ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .PINC4_REG (PINC4_REG ), + .PINC5_REG (PINC5_REG ), + .PINC6_REG (PINC6_REG ), + .PINC7_REG (PINC7_REG ), + .POFF0_REG (POFF0_REG ), + .POFF1_REG (POFF1_REG ), + .POFF2_REG (POFF2_REG ), + .POFF3_REG (POFF3_REG ), + .POFF4_REG (POFF4_REG ), + .POFF5_REG (POFF5_REG ), + .POFF6_REG (POFF6_REG ), + .POFF7_REG (POFF7_REG ), + .GAIN0_REG (GAIN0_REG ), + .GAIN1_REG (GAIN1_REG ), + .GAIN2_REG (GAIN2_REG ), + .GAIN3_REG (GAIN3_REG ), + .GAIN4_REG (GAIN4_REG ), + .GAIN5_REG (GAIN5_REG ), + .GAIN6_REG (GAIN6_REG ), + .GAIN7_REG (GAIN7_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/ctrl.sv b/firmware/ip/axis_sg_mixmux8_v1/src/ctrl.sv new file mode 100644 index 0000000..e4d78b0 --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/ctrl.sv @@ -0,0 +1,183 @@ +//Format of waveform interface: +// |----------|---------| +// | 39 .. 32 | 31 .. 0 | +// |----------|---------| +// | mask | nsamp | +// |----------|---------| +// nsamp : 32 bits +// mask : 8 bits +// +// Total : 40. +module ctrl ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // Mask output. + mask_o , + + // Output enable. + en_o ); + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [39:0] fifo_dout_i; +output [7:0] mask_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT0_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +reg rd_en_int; + +// Fifo dout register. +reg [39:0] fifo_dout_r; + +// Number of samples. +wire [31:0] nsamp_int; + +// Mask. +wire [7:0] mask_int; +wire [7:0] mask_la; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +wire en_reg_la; + +// Load register. +reg load_r; + +// Latency for mask. +latency_reg + #( + .N(2), + .B(8) + ) + mask_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (mask_int ), + .dout (mask_la ) + ); + +// Latency for en_reg. +latency_reg + #( + .N(3), + .B(1) + ) + en_reg_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (en_reg ), + .dout (en_reg_la ) + ); + + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + + // Load enable flag. + load_r <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (~fifo_empty_i) + state <= CNT0_ST; + + CNT0_ST: + state <= CNT_ST; + + CNT_ST: + if ( cnt == nsamp_int ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Load enable flag. + load_r <= load_int; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (rd_en_int) + if (!fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT0_ST: + rd_en_int = 0; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign nsamp_int = fifo_dout_r[31:0]; +assign mask_int = fifo_dout_r[39:32]; + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mask_o = mask_la; +assign en_o = en_reg_la; + +endmodule + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_sg_mixmux8_v1/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 0000000..426f115 --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,477 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_compiler_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 9 + 0 + 0 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 10 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 72 + 1 + 1 + zynquplus + Full_Range + 1 + dds_compiler_0 + Not_Required + 256 + Maximal + 0.08 + Coregen + false + false + false + false + 10 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + false + Auto + Twos_Complement + Speed + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 22 + TRUE + ../../../../qick_fw_sho/qick_tprocv2_216_q3diamond/top/top.tmp/axis_sg_mixmux8_v1_v1_0_project/axis_sg_mixmux8_v1_v1_0_project.gen/sources_1/ip/dds_compiler_0 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/dds_top.v b/firmware/ip/axis_sg_mixmux8_v1/src/dds_top.v new file mode 100644 index 0000000..2bea43b --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/dds_top.v @@ -0,0 +1,149 @@ +module dds_top ( + // Reset and clock. + rstn , + clk , + + // DDS output. + dds_dout_o , + + // Registers. + PINC_REG , + POFF_REG , + GAIN_REG , + WE_REG + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input rstn; +input clk; + +output [N_DDS*32-1:0] dds_dout_o; + +input [31:0] PINC_REG; +input [31:0] POFF_REG; +input [15:0] GAIN_REG; +input WE_REG; + +/********************/ +/* Internal signals */ +/********************/ +// DDS input control. +wire [N_DDS*72-1:0] dds_ctrl_int; +reg [N_DDS*72-1:0] dds_ctrl_int_r; + +// DDS output. +wire [31:0] dds_dout [0:N_DDS-1]; +wire [31:0] dds_dout_la [0:N_DDS-1]; + +// Product. +wire signed [15:0] gain; +wire signed [15:0] prod_a_real [0:N_DDS-1]; +wire signed [15:0] prod_a_imag [0:N_DDS-1]; +wire signed [31:0] prod_real [0:N_DDS-1]; +wire signed [31:0] prod_imag [0:N_DDS-1]; +reg [31:0] prod_real_r1[0:N_DDS-1]; +reg [31:0] prod_imag_r1[0:N_DDS-1]; +wire [15:0] prod_real_q [0:N_DDS-1]; +wire [15:0] prod_imag_q [0:N_DDS-1]; +wire [31:0] prod [0:N_DDS-1]; +reg [31:0] prod_r1 [0:N_DDS-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Phase Control block. +phase_ctrl + #( + .N_DDS (N_DDS ) + ) + phase_ctrl_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // dds control. + .dds_ctrl_o (dds_ctrl_int ), + + // Registers. + .PINC_REG (PINC_REG ), + .POFF_REG (POFF_REG ), + .WE_REG (WE_REG ) + ); + +generate +genvar i; + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/fifo/fifo_axi.vhd b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/fifo/fifo_dc.vhd b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/fifo/gray2bin.vhd b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/fifo/rd2axi.vhd b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/latency_reg.v b/firmware/ip/axis_sg_mixmux8_v1/src/latency_reg.v new file mode 100644 index 0000000..4150ef6 --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +(* srl_style = "register" *) reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mixmux8_v1/src/tb/tb.sv b/firmware/ip/axis_sg_mixmux8_v1/src/tb/tb.sv new file mode 100644 index 0000000..8ee720c --- /dev/null +++ b/firmware/ip/axis_sg_mixmux8_v1/src/tb/tb.sv @@ -0,0 +1,359 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter N_DDS = 4; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [7:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [7:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +// s_axis interfase. +wire [39:0] s_axis_tdata; +wire s_axis_tready; +reg s_axis_tvalid; + +// m_axis interfase. +wire [N_DDS*32-1:0] m_axis_tdata; +reg m_axis_tready = 1; +wire m_axis_tvalid; + +// Waveform fields. +reg [31:0] nsamp_r; +reg [7:0] mask_r; + +// Assignment of data out for debugging. +wire [32:0] dout_ii [0:N_DDS-1]; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// TB control. +reg tb_load_wave = 0; +reg tb_load_wave_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m_axis_tdata[16*ii +: 16]; +end +endgenerate + +// M_AXI. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_sg_mixmux8_v1 + # + ( + .N_DDS(N_DDS) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // s_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready (s_axis_tready ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // AXIS Master for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +// Waveform fields. +assign s_axis_tdata = {mask_r,nsamp_r}; + + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("###########################"); + $display("### Program Frequencies ###"); + $display("###########################"); + $display("t = %0t", $time); + + // Register mapping: + // 0-7 : PINC. + // 8-15 : POFF. + // 16-23: GAIN. + // 24 : WE. + + for (int i=0; i<8; i=i+1) begin + // PINCx_REG + data_wr = freq_calc(100, N_DDS, 10+i); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*i, prot, data_wr, resp); + + // POFFx_REG + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(i+8), prot, data_wr, resp); + + // GAINx_REG + data_wr = 20000+1000*i; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(i+16), prot, data_wr, resp); + + end + + //// PINC0/1/2. + //data_wr = freq_calc(100, N_DDS, 1); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*0, prot, data_wr, resp); + + //data_wr = freq_calc(100, N_DDS, 1); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); + + //data_wr = freq_calc(100, N_DDS, 1); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, data_wr, resp); + + //// POFF0/1/2. + //data_wr = phase_calc(0); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(0+8), prot, data_wr, resp); + + //data_wr = phase_calc(0); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(1+8), prot, data_wr, resp); + + //data_wr = phase_calc(180); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(2+8), prot, data_wr, resp); + + //// GAIN0/1/2. + //data_wr = 30000; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(0+16), prot, data_wr, resp); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(1+16), prot, data_wr, resp); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(2+16), prot, data_wr, resp); + + //// 0 gain just for quantization... + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(7+16), prot, 0, resp); + + // WE. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*24, prot, 1, resp); + #10; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*24, prot, 0, resp); + #10; + + $display("#######################"); + $display("### Queue Waveforms ###"); + $display("#######################"); + $display("t = %0t", $time); + + // Queue waveforms and write output while queuing. + tb_load_wave <= 1; + tb_write_out <= 1; + wait (tb_load_wave_done); + + #50000; + #50000; + + // Stop writing output data. + tb_write_out <= 0; + + #20000; + +end + +// Load waveforms. +initial begin + s_axis_tvalid <= 0; + nsamp_r <= 0; + mask_r <= 0; + + wait (tb_load_wave); + wait (s_axis_tready); + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid <= 1; + //nsamp_r <= 550; + //mask_r <= 8'b0000_1111; + + @(posedge aclk); + $display("t = %0t", $time); + s_axis_tvalid <= 1; + nsamp_r <= 3500; + mask_r <= 8'b1111_1111; + + // Phase-coherency test. + // 1 sine wave first. + // 2 sine waves, same phase, same frequency. + // 2 sine waves, 180 out of phase, same frequency. + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid <= 1; + //nsamp_r <= 2500; + //mask_r <= 8'b1000_0001; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid <= 1; + //nsamp_r <= 2500; + //mask_r <= 8'b0000_0011; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid <= 1; + //nsamp_r <= 2500; + //mask_r <= 8'b0000_0101; + + @(posedge aclk); + s_axis_tvalid <= 0; + tb_load_wave_done <= 1; +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d; + + // Output file. + fd = $fopen("../../../../../tb/dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, idx, real"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i + + user.org + user + axis_sg_mux4_v1 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_sg_mux4_v1 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 8e4f9196 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_sg_mux4_v1 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 8e4f9196 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 429ef1d0 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 39 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N_DDS + N Dds + 2 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux4_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/sg_mux4.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mux4.v + verilogSource + CHECKSUM_d597a72a + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux4_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/sg_mux4.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mux4.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_sg_mux4_v1_v1_0.tcl + tclSource + CHECKSUM_429ef1d0 + XGUI_VERSION_2 + + + + AXIS Signal Generator with 4 muxed outputs. + + + N_DDS + N Dds + 2 + + + Component_Name + axis_sg_mux4_v1_v1_0 + + + + + + zynquplus + + + /UserIP + + AXIS SG mux 4 + package_project + 3 + 2022-02-22T20:24:54Z + + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + /home/lstefana/v20.2/ip/axis_sg_mux4_v1 + + + + 2020.2 + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 0000000..7cfbd51 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 8 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 0000000..a53be60 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 8 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..f5a8b15 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,200 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + virtex7 + + + xc7vx485t + ffg1157 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 0000000..024a39d --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4760 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + ARSIZE + + + m_axi_arsize + + + + + ARUSER + + + m_axi_aruser + + + + + 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std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rlast + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_ruser + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axi_rvalid + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axi_rready + + out + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + M_INITIATOR_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + wr_socket + + + width + 32 + + + + + + + 1 + + + + + M_INITIATOR_rd_socket + AXIMM Read Socket + AXIMM Socket for Read + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + rd_socket + + + width + 32 + + + + + + + 1 + + + + + S_TARGET_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + + + + + 1 + + + + + S_TARGET_rd_socket + AXIMM Read Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + + + + + 1 + + + + + + + C_AXI_PROTOCOL + 2 + + + C_AXI_INTERFACE_MODE + 0 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_WDATA_WIDTH + 32 + + + C_AXI_RDATA_WIDTH + 32 + + + C_AXI_WID_WIDTH + 0 + + + C_AXI_RID_WIDTH + 0 + + + C_AXI_AWUSER_WIDTH + 0 + + + C_AXI_ARUSER_WIDTH + 0 + + + C_AXI_WUSER_WIDTH + 0 + + + C_AXI_RUSER_WIDTH + 0 + + + C_AXI_BUSER_WIDTH + 0 + + + C_AXI_SUPPORTS_NARROW + 0 + + + C_AXI_HAS_BURST + 0 + + + C_AXI_HAS_LOCK + 0 + + + C_AXI_HAS_CACHE + 0 + + + C_AXI_HAS_REGION + 0 + + + C_AXI_HAS_PROT + 1 + + + C_AXI_HAS_QOS + 0 + + + C_AXI_HAS_WSTRB + 1 + + + C_AXI_HAS_BRESP + 1 + + + C_AXI_HAS_RRESP + 1 + + + C_AXI_HAS_ARESETN + 1 + + + + + + choice_list_04fafd91 + AXI3 + AXI4 + AXI4LITE + + + choice_list_6240decd + READ_ONLY + READ_WRITE + WRITE_ONLY + + + choice_list_642e7122 + MASTER + PASS_THROUGH + SLAVE + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_0fc128e8 + 0 + 0 + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi_mst_0.vho + vhdlTemplate + + + axi_mst_0.veo + verilogTemplate + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_8 + + + + xilinx_synthesisconstraints_view_fileset + + axi_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_8 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_8 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_8 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_8 + + + + xilinx_externalfiles_view_fileset + + axi_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axi_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axi_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 8 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v1/src/axi_slv.vhd b/firmware/ip/axis_sg_mux4_v1/src/axi_slv.vhd new file mode 100644 index 0000000..bcce170 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/axi_slv.vhd @@ -0,0 +1,525 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + PINC0_REG : out std_logic_vector (15 downto 0); + PINC1_REG : out std_logic_vector (15 downto 0); + PINC2_REG : out std_logic_vector (15 downto 0); + PINC3_REG : out std_logic_vector (15 downto 0); + WE_REG : out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + -- 0 : PINC0_REG : 16-bit. Frequency of output 0. + -- 1 : PINC1_REG : 16-bit. Frequency of output 1. + -- 2 : PINC2_REG : 16-bit. Frequency of output 2. + -- 3 : PINC3_REG : 16-bit. Frequency of output 3. + -- 4 : WE_REG : 1-bit. Register write. + + -- Output Registers. + PINC0_REG <= slv_reg0(15 downto 0); + PINC1_REG <= slv_reg1(15 downto 0); + PINC2_REG <= slv_reg2(15 downto 0); + PINC3_REG <= slv_reg3(15 downto 0); + WE_REG <= slv_reg4(0); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v1/src/axis_sg_mux4.v b/firmware/ip/axis_sg_mux4_v1/src/axis_sg_mux4.v new file mode 100644 index 0000000..5b55552 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/axis_sg_mux4.v @@ -0,0 +1,182 @@ +// Signal Generator V4. +// s_axi_aclk : clock for s_axi_* +// aclk : clock for s_axis_* and m_axis_* +// +module axis_sg_mux4_v1 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // s_* and m_* reset/clock. + aclk , + aresetn , + + // S_AXIS to queue waveforms. + s_axis_tready , + s_axis_tvalid , + s_axis_tdata , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [39:0] s_axis_tdata; + +input m_axis_tready; +output m_axis_tvalid; +output [N_DDS*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [15:0] PINC0_REG; +wire [15:0] PINC1_REG; +wire [15:0] PINC2_REG; +wire [15:0] PINC3_REG; +wire WE_REG; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .WE_REG (WE_REG ) + ); + +sg_mux4 + #( + .N_DDS (N_DDS ) + ) + sg_mux4_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready_o (s_axis_tready ), + .s_axis_tvalid_i (s_axis_tvalid ), + .s_axis_tdata_i (s_axis_tdata ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_sg_mux4_v1/src/ctrl.sv b/firmware/ip/axis_sg_mux4_v1/src/ctrl.sv new file mode 100644 index 0000000..e1ccea9 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/ctrl.sv @@ -0,0 +1,175 @@ +//Format of waveform interface: +// |----------|---------| +// | 39 .. 32 | 31 .. 0 | +// |----------|---------| +// | mask | nsamp | +// |----------|---------| +// nsamp : 32 bits +// mask : 8 bits +// +// Total : 40. +module ctrl ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // Mask output. + mask_o , + + // Output enable. + en_o ); + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [39:0] fifo_dout_i; +output [7:0] mask_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +reg rd_en_int; + +// Fifo dout register. +reg [39:0] fifo_dout_r; + +// Number of samples. +wire [31:0] nsamp_int; + +// Mask. +wire [7:0] mask_int; +wire [7:0] mask_la; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +wire en_reg_la; + +// Load register. +reg load_r; + +// Latency for mask. +latency_reg + #( + .N(2), + .B(8) + ) + mask_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (mask_int ), + .dout (mask_la ) + ); + +// Latency for en_reg. +latency_reg + #( + .N(3), + .B(1) + ) + en_reg_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (en_reg ), + .dout (en_reg_la ) + ); + + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + + // Load enable flag. + load_r <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (~fifo_empty_i) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Load enable flag. + load_r <= load_int; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (rd_en_int) + if (!fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign nsamp_int = fifo_dout_r[31:0]; +assign mask_int = fifo_dout_r[39:32]; + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mask_o = mask_la; +assign en_o = en_reg_la; + +endmodule + diff --git a/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.veo b/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.veo new file mode 100644 index 0000000..c3dea29 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.veo @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:dds_compiler:6.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +dds_compiler_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [39 : 0] s_axis_phase_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file dds_compiler_0.v when simulating +// the core, dds_compiler_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.vho b/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.vho new file mode 100644 index 0000000..4db3fc6 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.vho @@ -0,0 +1,83 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:dds_compiler:6.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT dds_compiler_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(39 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : dds_compiler_0 + PORT MAP ( + aclk => aclk, + s_axis_phase_tvalid => s_axis_phase_tvalid, + s_axis_phase_tdata => s_axis_phase_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file dds_compiler_0.vhd when simulating +-- the core, dds_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 0000000..274be99 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,315 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_compiler_0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 5 + 0 + 0 + 0 + 16 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 10 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 40 + 1 + 1 + zynquplus + Full_Range + 1 + dds_compiler_0 + Not_Required + 256 + Maximal + 3906.25 + Coregen + false + false + false + false + 10 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + false + Auto + Twos_Complement + Speed + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 16 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 20 + TRUE + ../../../../test_axis_sg_int4_v1/top/top.tmp/axis_sg_int4_v1_v1_0_project/axis_sg_int4_v1_v1_0_project.gen/sources_1/ip/dds_compiler_0 + + . + 2020.2 + GLOBAL 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xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + event_s_phase_tlast_missing + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + event_s_phase_tlast_unexpected + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + event_s_phase_chanid_incorrect + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + event_s_config_tlast_missing + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + event_s_config_tlast_unexpected + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + + + C_XDEVICEFAMILY + zynquplus + + + C_MODE_OF_OPERATION + 0 + + + C_MODULUS + 9 + + + C_ACCUMULATOR_WIDTH + 16 + + + C_CHANNELS + 1 + + + C_HAS_PHASE_OUT + 0 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C_HAS_M_PHASE + 0 + + + C_M_PHASE_TDATA_WIDTH + 1 + + + C_M_PHASE_HAS_TUSER + 0 + + + C_M_PHASE_TUSER_WIDTH + 1 + + + C_DEBUG_INTERFACE + 0 + + + C_CHAN_WIDTH + 1 + + + + + + choice_list_0be33969 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + + + choice_list_230272f2 + None + Fixed + Programmable + Streaming + + + choice_list_45db86b7 + Auto + Configurable + + + choice_list_4721e082 + Minimal + Maximal + + + choice_list_950bd3bd + Auto + Area + Speed + + + choice_list_ba6ede68 + Standard + Rasterized + + + choice_list_cd7e1d82 + Coregen + Sysgen + + + choice_list_de3e80a0 + Fixed + Programmable + Streaming + + + choice_list_faa329ca + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + 21 + + + choice_pairs_0079eeec + Twos_Complement + Sign_and_Magnitude + + + choice_pairs_27d1d409 + Auto + Distributed_ROM + Block_ROM + + + choice_pairs_65a5252d + Full_Range + Unit_Circle + + + choice_pairs_6bdc34ae + System_Parameters + Hardware_Parameters + + + choice_pairs_75713637 + Packet_Framing + Not_Required + + + choice_pairs_8b9a47c2 + Auto + None + Phase_Dithering + Taylor_Series_Corrected + + + choice_pairs_944fe41d + Phase_Generator_and_SIN_COS_LUT + Phase_Generator_only + SIN_COS_LUT_only + + + choice_pairs_a54f933f + Sine + Cosine + Sine_and_Cosine + + + choice_pairs_d463c5cb + User_Field + Not_Required + + + choice_pairs_dac1efef + Not_Required + + + choice_pairs_f611af79 + On_Vector + On_Packet + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + dds_compiler_0.vho + vhdlTemplate + + + dds_compiler_0.veo + verilogTemplate + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + hdl/xbip_pipe_v3_0_vh_rfs.vhd + vhdlSource + xbip_pipe_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + hdl/xbip_bram18k_v3_0_vh_rfs.vhd + vhdlSource + xbip_bram18k_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + hdl/mult_gen_v12_0_vh_rfs.vhd + vhdlSource + mult_gen_v12_0_16 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd + vhdlSource + xbip_dsp48_wrapper_v3_0_4 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd + vhdlSource + xbip_dsp48_addsub_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd + vhdlSource + xbip_dsp48_multadd_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/dds_compiler_v6_0_vh_rfs.vhd + vhdlSource + dds_compiler_v6_0_20 + + + + xilinx_synthesisconstraints_view_fileset + + dds_compiler_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/dds_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + hdl/xbip_pipe_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_pipe_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + hdl/xbip_bram18k_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_bram18k_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + hdl/mult_gen_v12_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + mult_gen_v12_0_16 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_wrapper_v3_0_4 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_addsub_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_multadd_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/dds_compiler_v6_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + dds_compiler_v6_0_20 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/dds_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_cmodelsimulation_view_fileset + + cmodel/dds_compiler_v6_0_bitacc_cmodel_lin64.zip + zip + + + cmodel/dds_compiler_v6_0_bitacc_cmodel_nt64.zip + zip + + + + xilinx_vhdltestbench_view_fileset + + demo_tb/tb_dds_compiler_0.vhd + vhdlSource + + + + xilinx_versioninformation_view_fileset + + doc/dds_compiler_v6_0_changelog.txt + text + + + + xilinx_externalfiles_view_fileset + + dds_compiler_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + dds_compiler_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + dds_compiler_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + dds_compiler_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + dds_compiler_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. + + + Component_Name + Component Name + dds_compiler_0 + + + PartsPresent + Configuration Options + Phase_Generator_and_SIN_COS_LUT + + + DDS_Clock_Rate + System Clock + 256 + + + Channels + Number of Channels + 1 + + + Mode_of_Operation + Mode Of Operation + Standard + + + Modulus + Modulus + 9 + + + Parameter_Entry + Parameter Selection + System_Parameters + + + Spurious_Free_Dynamic_Range + Spurious Free Dynamic Range + 96 + + + Frequency_Resolution + Frequency Resolution + 3906.25 + + + Noise_Shaping + Noise Shaping + Auto + + + Phase_Width + Phase Width + 16 + + + Output_Width + Output Width + 16 + + + Phase_Increment + Phase Increment + Streaming + + + Resync + Resync + true + + + Phase_offset + Phase Offset + Streaming + + + Output_Selection + Output Selection + Sine_and_Cosine + + + Negative_Sine + Negative Sine + false + + + Negative_Cosine + Negative Cosine + false + + + Amplitude_Mode + Amplitude Mode + Full_Range + + + Memory_Type + Memory Type + Auto + + + Optimization_Goal + Optimization Goal + Speed + + + DSP48_Use + DSP48 Use + Maximal + + + Has_Phase_Out + Has Phase Out + false + + + DATA_Has_TLAST + DATA Has TLAST + Not_Required + + + Has_TREADY + Output TREADY + false + + + S_PHASE_Has_TUSER + Input + Not_Required + + + S_PHASE_TUSER_Width + User Field Width + 1 + + + M_DATA_Has_TUSER + DATA Output + Not_Required + + + M_PHASE_Has_TUSER + PHASE Output + Not_Required + + + S_CONFIG_Sync_Mode + Synchronization Mode + On_Vector + + + OUTPUT_FORM + Output Form + Twos_Complement + + + Latency_Configuration + Configurable + + + Latency + 10 + + + Has_ARESETn + ARESETn (active low) + false + + + Has_ACLKEN + ACLKEN + false + + + Output_Frequency1 + 0 + + + PINC1 + 0 + + + Phase_Offset_Angles1 + 0 + + + POFF1 + 0 + + + Output_Frequency2 + 0 + + + PINC2 + 0 + + + Phase_Offset_Angles2 + 0 + + + POFF2 + 0 + + + Output_Frequency3 + 0 + + + PINC3 + 0 + + + Phase_Offset_Angles3 + 0 + + + POFF3 + 0 + + + Output_Frequency4 + 0 + + + PINC4 + 0 + + + Phase_Offset_Angles4 + 0 + + + POFF4 + 0 + + + Output_Frequency5 + 0 + + + PINC5 + 0 + + + Phase_Offset_Angles5 + 0 + + + POFF5 + 0 + + + Output_Frequency6 + 0 + + + PINC6 + 0 + + + Phase_Offset_Angles6 + 0 + + + POFF6 + 0 + + + Output_Frequency7 + 0 + + + PINC7 + 0 + + + Phase_Offset_Angles7 + 0 + + + POFF7 + 0 + + + Output_Frequency8 + 0 + + + PINC8 + 0 + + + Phase_Offset_Angles8 + 0 + + + POFF8 + 0 + + + Output_Frequency9 + 0 + + + PINC9 + 0 + + + Phase_Offset_Angles9 + 0 + + + POFF9 + 0 + + + Output_Frequency10 + 0 + + + PINC10 + 0 + + + Phase_Offset_Angles10 + 0 + + + POFF10 + 0 + + + Output_Frequency11 + 0 + + + PINC11 + 0 + + + Phase_Offset_Angles11 + 0 + + + POFF11 + 0 + + + Output_Frequency12 + 0 + + + PINC12 + 0 + + + Phase_Offset_Angles12 + 0 + + + POFF12 + 0 + + + Output_Frequency13 + 0 + + + PINC13 + 0 + + + Phase_Offset_Angles13 + 0 + + + POFF13 + 0 + + + Output_Frequency14 + 0 + + + PINC14 + 0 + + + Phase_Offset_Angles14 + 0 + + + POFF14 + 0 + + + Output_Frequency15 + 0 + + + PINC15 + 0 + + + Phase_Offset_Angles15 + 0 + + + POFF15 + 0 + + + Output_Frequency16 + 0 + + + PINC16 + 0 + + + Phase_Offset_Angles16 + 0 + + + POFF16 + 0 + + + POR_mode + POR Mode + false + + + GUI_Behaviour + Coregen + + + explicit_period + false + + + period + 1 + + + + + DDS Compiler + 20 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v1/src/dds_top.v b/firmware/ip/axis_sg_mux4_v1/src/dds_top.v new file mode 100644 index 0000000..587b63d --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/dds_top.v @@ -0,0 +1,120 @@ +module dds_top ( + // Reset and clock. + rstn , + clk , + + // DDS output. + dds_dout_o , + + // Registers. + PINC_REG , + WE_REG + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input rstn; +input clk; + +output [N_DDS*32-1:0] dds_dout_o; + +input [15:0] PINC_REG; +input WE_REG; + +/********************/ +/* Internal signals */ +/********************/ +// DDS input control. +reg dds_tvalid_r; +wire [N_DDS*40-1:0] dds_ctrl_int; +reg [N_DDS*40-1:0] dds_ctrl_int_r; + +// DDS output. +wire [31:0] dds_dout [0:N_DDS-1]; +wire [31:0] dds_dout_la [0:N_DDS-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Phase Control block. +phase_ctrl + #( + .N_DDS (N_DDS ) + ) + phase_ctrl_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // dds control. + .dds_ctrl_o (dds_ctrl_int ), + + // Registers. + .PINC_REG (PINC_REG ), + .WE_REG (WE_REG ) + ); + +generate +genvar i; + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_axi.vhd b/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_dc.vhd b/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v1/src/fifo/gray2bin.vhd b/firmware/ip/axis_sg_mux4_v1/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v1/src/fifo/rd2axi.vhd b/firmware/ip/axis_sg_mux4_v1/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_sg_mux4_v1/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v1/src/latency_reg.v b/firmware/ip/axis_sg_mux4_v1/src/latency_reg.v new file mode 100644 index 0000000..687a9f3 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v1/src/tb/dout.csv b/firmware/ip/axis_sg_mux4_v1/src/tb/dout.csv new file mode 100644 index 0000000..1a8273e --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v1/src/tb/dout.csv @@ -0,0 +1,3685 @@ +valid, idx, real, imag +0, 0, 0, 0 +0, 1, 0, 0 +0, 0, 0, 0 +0, 1, 0, 0 +0, 0, 0, 0 +0, 1, 0, 0 +0, 0, 0, 0 +0, 1, 0, 0 +0, 0, 0, 0 +0, 1, 0, 0 +0, 0, 0, 0 +0, 1, 0, 0 +0, 0, 0, 0 +0, 1, 0, 0 +0, 0, 0, 0 +0, 1, 0, 0 +0, 0, 0, 0 +0, 1, 0, 0 +1, 0, -805, 14828 +1, 1, 8879, -3717 +1, 0, -675, 3630 +1, 1, 17647, 5713 +1, 0, 870, 4187 +1, 1, 5189, 17839 +1, 0, -4817, -1555 +1, 1, -10640, 5836 +1, 0, 3871, -14318 +1, 1, -2114, -11642 +1, 0, 22534, -7325 +1, 1, 13309, -8091 +1, 0, 20072, 13037 +1, 1, 13562, 688 +1, 0, 2867, 13990 +1, 1, 14420, -86 +1, 0, 2527, 1842 +1, 1, 22542, 8458 +1, 0, 11583, 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[31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +// s_axis interfase. +wire [39:0] s_axis_tdata; +wire s_axis_tready; +reg s_axis_tvalid; + +// m_axis interfase. +wire [N_DDS*32-1:0] m_axis_tdata; +reg m_axis_tready = 1; +wire m_axis_tvalid; + +// Waveform fields. +reg [31:0] nsamp_r; +reg [7:0] mask_r; + +// Assignment of data out for debugging. +wire [31:0] dout_ii [0:N_DDS-1]; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// TB control. +reg tb_load_wave = 0; +reg tb_load_wave_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m_axis_tdata[32*ii +: 32]; +end +endgenerate + +// M_AXI. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_sg_mux4_v1 + # + ( + .N_DDS(N_DDS) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // s_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready (s_axis_tready ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // AXIS Master for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +// Waveform fields. +assign s_axis_tdata = {mask_r,nsamp_r}; + + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("###########################"); + $display("### Program Frequencies ###"); + $display("###########################"); + $display("t = %0t", $time); + + // PINC0_REG + data_wr = freq_calc(100, N_DDS, 1); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*0, prot, data_wr, resp); + #10; + + // PINC1_REG + data_wr = freq_calc(100, N_DDS, 11); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); + #10; + + // PINC2_REG + data_wr = freq_calc(100, N_DDS, 27); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, data_wr, resp); + #10; + + // PINC3_REG + data_wr = freq_calc(100, N_DDS, 115); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); + #10; + + // we. + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); + #10; + + // we. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); + #10; + + $display("#######################"); + $display("### Queue Waveforms ###"); + $display("#######################"); + $display("t = %0t", $time); + + // Queue waveforms and write output while queuing. + tb_load_wave <= 1; + tb_write_out <= 1; + wait (tb_load_wave_done); + + #30000; + + // Stop writing output data. + tb_write_out <= 0; + + #20000; + +end + +// Load waveforms. +initial begin + s_axis_tvalid <= 0; + nsamp_r <= 0; + mask_r <= 0; + + wait (tb_load_wave); + wait (s_axis_tready); + + @(posedge aclk); + $display("t = %0t", $time); + s_axis_tvalid <= 1; + nsamp_r <= 550; + mask_r <= 8'b0000_1111; + + @(posedge aclk); + $display("t = %0t", $time); + s_axis_tvalid <= 1; + nsamp_r <= 350; + mask_r <= 8'b0000_1111; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid_i <= 1; + //nsamp_r <= 25; + //mask_r <= 8'b0000_0010; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid_i <= 1; + //nsamp_r <= 35; + //mask_r <= 8'b0000_0100; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid_i <= 1; + //nsamp_r <= 63; + //mask_r <= 8'b0000_1000; + + @(posedge aclk); + s_axis_tvalid <= 0; + tb_load_wave_done <= 1; +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d, imag_d; + + // Output file. + fd = $fopen("../../../../../tb/dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, idx, real, imag"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i + + user.org + user + axis_sg_mux4_v2 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_sg_mux4_v2 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 5ea64aa6 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_sg_mux4_v2 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 5ea64aa6 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 429ef1d0 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 39 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N_DDS + N Dds + 2 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux4_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/sg_mux4.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mux4.v + verilogSource + CHECKSUM_0b7ef357 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux4_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/sg_mux4.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mux4.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_sg_mux4_v2_v1_0.tcl + tclSource + CHECKSUM_429ef1d0 + XGUI_VERSION_2 + + + + AXIS Signal Generator with 4 muxed outputs, 32-bit DDS and individual Gain. + + + N_DDS + N Dds + 2 + + + Component_Name + axis_sg_mux4_v1_v1_0 + + + + + + zynquplus + + + /UserIP + + AXIS SG mux 4 V2 + package_project + 2 + 2022-05-12T19:42:38Z + + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + /home/lstefana/ZCU216/q3diamond/ip/axis_sg_mux4_v2 + + + + 2020.2 + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 0000000..7cfbd51 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 8 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 0000000..a53be60 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 8 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..ac9cf04 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,200 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 0000000..c2c5156 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4760 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + ARSIZE + + + m_axi_arsize + + + + + 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+ + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_8 + + + + xilinx_externalfiles_view_fileset + + axi_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axi_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axi_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 8 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v2/src/axi_slv.vhd b/firmware/ip/axis_sg_mux4_v2/src/axi_slv.vhd new file mode 100644 index 0000000..c92dcb1 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/axi_slv.vhd @@ -0,0 +1,537 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + PINC0_REG : out std_logic_vector (31 downto 0); + PINC1_REG : out std_logic_vector (31 downto 0); + PINC2_REG : out std_logic_vector (31 downto 0); + PINC3_REG : out std_logic_vector (31 downto 0); + GAIN0_REG : out std_logic_vector (15 downto 0); + GAIN1_REG : out std_logic_vector (15 downto 0); + GAIN2_REG : out std_logic_vector (15 downto 0); + GAIN3_REG : out std_logic_vector (15 downto 0); + WE_REG : out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + -- 0 : PINC0_REG : 32-bit. Frequency of output 0. + -- 1 : PINC1_REG : 32-bit. Frequency of output 1. + -- 2 : PINC2_REG : 32-bit. Frequency of output 2. + -- 3 : PINC3_REG : 32-bit. Frequency of output 3. + -- 4 : GAIN0_REG : 16-bit. Frequency of output 0. + -- 5 : GAIN1_REG : 16-bit. Frequency of output 1. + -- 6 : GAIN2_REG : 16-bit. Frequency of output 2. + -- 7 : GAIN3_REG : 16-bit. Frequency of output 3. + -- 8 : WE_REG : 1-bit. Register write. + + -- Output Registers. + PINC0_REG <= slv_reg0(31 downto 0); + PINC1_REG <= slv_reg1(31 downto 0); + PINC2_REG <= slv_reg2(31 downto 0); + PINC3_REG <= slv_reg3(31 downto 0); + GAIN0_REG <= slv_reg4(15 downto 0); + GAIN1_REG <= slv_reg5(15 downto 0); + GAIN2_REG <= slv_reg6(15 downto 0); + GAIN3_REG <= slv_reg7(15 downto 0); + WE_REG <= slv_reg8(0); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v2/src/axis_sg_mux4.v b/firmware/ip/axis_sg_mux4_v2/src/axis_sg_mux4.v new file mode 100644 index 0000000..b28a748 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/axis_sg_mux4.v @@ -0,0 +1,194 @@ +// Signal Generator V4. +// s_axi_aclk : clock for s_axi_* +// aclk : clock for s_axis_* and m_axis_* +// +module axis_sg_mux4_v2 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // s_* and m_* reset/clock. + aclk , + aresetn , + + // S_AXIS to queue waveforms. + s_axis_tready , + s_axis_tvalid , + s_axis_tdata , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [39:0] s_axis_tdata; + +input m_axis_tready; +output m_axis_tvalid; +output [N_DDS*32-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] PINC0_REG; +wire [31:0] PINC1_REG; +wire [31:0] PINC2_REG; +wire [31:0] PINC3_REG; +wire [15:0] GAIN0_REG; +wire [15:0] GAIN1_REG; +wire [15:0] GAIN2_REG; +wire [15:0] GAIN3_REG; +wire WE_REG; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .GAIN0_REG (GAIN0_REG ), + .GAIN1_REG (GAIN1_REG ), + .GAIN2_REG (GAIN2_REG ), + .GAIN3_REG (GAIN3_REG ), + .WE_REG (WE_REG ) + ); + +sg_mux4 + #( + .N_DDS (N_DDS ) + ) + sg_mux4_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready_o (s_axis_tready ), + .s_axis_tvalid_i (s_axis_tvalid ), + .s_axis_tdata_i (s_axis_tdata ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .GAIN0_REG (GAIN0_REG ), + .GAIN1_REG (GAIN1_REG ), + .GAIN2_REG (GAIN2_REG ), + .GAIN3_REG (GAIN3_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_sg_mux4_v2/src/ctrl.sv b/firmware/ip/axis_sg_mux4_v2/src/ctrl.sv new file mode 100644 index 0000000..e1ccea9 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/ctrl.sv @@ -0,0 +1,175 @@ +//Format of waveform interface: +// |----------|---------| +// | 39 .. 32 | 31 .. 0 | +// |----------|---------| +// | mask | nsamp | +// |----------|---------| +// nsamp : 32 bits +// mask : 8 bits +// +// Total : 40. +module ctrl ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // Mask output. + mask_o , + + // Output enable. + en_o ); + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [39:0] fifo_dout_i; +output [7:0] mask_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +reg rd_en_int; + +// Fifo dout register. +reg [39:0] fifo_dout_r; + +// Number of samples. +wire [31:0] nsamp_int; + +// Mask. +wire [7:0] mask_int; +wire [7:0] mask_la; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +wire en_reg_la; + +// Load register. +reg load_r; + +// Latency for mask. +latency_reg + #( + .N(2), + .B(8) + ) + mask_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (mask_int ), + .dout (mask_la ) + ); + +// Latency for en_reg. +latency_reg + #( + .N(3), + .B(1) + ) + en_reg_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (en_reg ), + .dout (en_reg_la ) + ); + + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + + // Load enable flag. + load_r <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (~fifo_empty_i) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Load enable flag. + load_r <= load_int; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (rd_en_int) + if (!fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign nsamp_int = fifo_dout_r[31:0]; +assign mask_int = fifo_dout_r[39:32]; + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mask_o = mask_la; +assign en_o = en_reg_la; + +endmodule + diff --git a/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.veo b/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.veo new file mode 100644 index 0000000..c3dea29 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.veo @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:dds_compiler:6.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +dds_compiler_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [39 : 0] s_axis_phase_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file dds_compiler_0.v when simulating +// the core, dds_compiler_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.vho b/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.vho new file mode 100644 index 0000000..4db3fc6 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.vho @@ -0,0 +1,83 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:dds_compiler:6.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT dds_compiler_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(39 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : dds_compiler_0 + PORT MAP ( + aclk => aclk, + s_axis_phase_tvalid => s_axis_phase_tvalid, + s_axis_phase_tdata => s_axis_phase_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file dds_compiler_0.vhd when simulating +-- the core, dds_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 0000000..6ae4d16 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,315 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_compiler_0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 9 + 0 + 0 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 10 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 72 + 1 + 1 + zynquplus + Full_Range + 1 + dds_compiler_0 + Not_Required + 256 + Maximal + 0.08 + Coregen + false + false + false + false + 10 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + false + Auto + Twos_Complement + Speed + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine_and_Cosine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 20 + TRUE + ../../../../test_axis_sg_int4_v1/top/top.tmp/axis_sg_int4_v1_v1_0_project/axis_sg_int4_v1_v1_0_project.gen/sources_1/ip/dds_compiler_0 + + . + 2020.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xml b/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xml new file mode 100644 index 0000000..251c392 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xml @@ -0,0 +1,3237 @@ + + + xilinx.com + customized_ip + dds_compiler_0 + 1.0 + + + event_pinc_invalid_intf + + + + + + + INTERRUPT + + + event_pinc_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_poff_invalid_intf + + + + + + + INTERRUPT + + + event_poff_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_phase_in_invalid_intf + + + + + + + INTERRUPT + + + event_phase_in_invalid + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + event_s_phase_tlast_missing_intf + + + + + + + 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xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + hdl/xbip_bram18k_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_bram18k_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + hdl/mult_gen_v12_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + mult_gen_v12_0_16 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_wrapper_v3_0_4 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_addsub_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_multadd_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/dds_compiler_v6_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + dds_compiler_v6_0_20 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/dds_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_cmodelsimulation_view_fileset + + cmodel/dds_compiler_v6_0_bitacc_cmodel_lin64.zip + zip + + + cmodel/dds_compiler_v6_0_bitacc_cmodel_nt64.zip + zip + + + + xilinx_vhdltestbench_view_fileset + + demo_tb/tb_dds_compiler_0.vhd + vhdlSource + + + + xilinx_versioninformation_view_fileset + + doc/dds_compiler_v6_0_changelog.txt + text + + + + xilinx_externalfiles_view_fileset + + dds_compiler_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + dds_compiler_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + dds_compiler_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + dds_compiler_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + dds_compiler_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. + + + Component_Name + Component Name + dds_compiler_0 + + + PartsPresent + Configuration Options + Phase_Generator_and_SIN_COS_LUT + + + DDS_Clock_Rate + System Clock + 256 + + + Channels + Number of Channels + 1 + + + Mode_of_Operation + Mode Of Operation + Standard + + + Modulus + Modulus + 9 + + + Parameter_Entry + Parameter Selection + System_Parameters + + + Spurious_Free_Dynamic_Range + Spurious Free Dynamic Range + 96 + + + Frequency_Resolution + Frequency Resolution + 3906.25 + + + Noise_Shaping + Noise Shaping + Auto + + + Phase_Width + Phase Width + 16 + + + Output_Width + Output Width + 16 + + + Phase_Increment + Phase Increment + Streaming + + + Resync + Resync + true + + + Phase_offset + Phase Offset + Streaming + + + Output_Selection + Output Selection + Sine_and_Cosine + + + Negative_Sine + Negative Sine + false + + + Negative_Cosine + Negative Cosine + false + + + Amplitude_Mode + Amplitude Mode + Full_Range + + + Memory_Type + Memory Type + Auto + + + Optimization_Goal + Optimization Goal + Speed + + + DSP48_Use + DSP48 Use + Maximal + + + Has_Phase_Out + Has Phase Out + false + + + DATA_Has_TLAST + DATA Has TLAST + Not_Required + + + Has_TREADY + Output TREADY + false + + + S_PHASE_Has_TUSER + Input + Not_Required + + + S_PHASE_TUSER_Width + User Field Width + 1 + + + M_DATA_Has_TUSER + DATA Output + Not_Required + + + M_PHASE_Has_TUSER + PHASE Output + Not_Required + + + S_CONFIG_Sync_Mode + Synchronization Mode + On_Vector + + + OUTPUT_FORM + Output Form + Twos_Complement + + + Latency_Configuration + Configurable + + + Latency + 10 + + + Has_ARESETn + ARESETn (active low) + false + + + Has_ACLKEN + ACLKEN + false + + + Output_Frequency1 + 0 + + + PINC1 + 0 + + + Phase_Offset_Angles1 + 0 + + + POFF1 + 0 + + + Output_Frequency2 + 0 + + + PINC2 + 0 + + + Phase_Offset_Angles2 + 0 + + + POFF2 + 0 + + + Output_Frequency3 + 0 + + + PINC3 + 0 + + + Phase_Offset_Angles3 + 0 + + + POFF3 + 0 + + + Output_Frequency4 + 0 + + + PINC4 + 0 + + + Phase_Offset_Angles4 + 0 + + + POFF4 + 0 + + + Output_Frequency5 + 0 + + + PINC5 + 0 + + + Phase_Offset_Angles5 + 0 + + + POFF5 + 0 + + + Output_Frequency6 + 0 + + + PINC6 + 0 + + + Phase_Offset_Angles6 + 0 + + + POFF6 + 0 + + + Output_Frequency7 + 0 + + + PINC7 + 0 + + + Phase_Offset_Angles7 + 0 + + + POFF7 + 0 + + + Output_Frequency8 + 0 + + + PINC8 + 0 + + + Phase_Offset_Angles8 + 0 + + + POFF8 + 0 + + + Output_Frequency9 + 0 + + + PINC9 + 0 + + + Phase_Offset_Angles9 + 0 + + + POFF9 + 0 + + + Output_Frequency10 + 0 + + + PINC10 + 0 + + + Phase_Offset_Angles10 + 0 + + + POFF10 + 0 + + + Output_Frequency11 + 0 + + + PINC11 + 0 + + + Phase_Offset_Angles11 + 0 + + + POFF11 + 0 + + + Output_Frequency12 + 0 + + + PINC12 + 0 + + + Phase_Offset_Angles12 + 0 + + + POFF12 + 0 + + + Output_Frequency13 + 0 + + + PINC13 + 0 + + + Phase_Offset_Angles13 + 0 + + + POFF13 + 0 + + + Output_Frequency14 + 0 + + + PINC14 + 0 + + + Phase_Offset_Angles14 + 0 + + + POFF14 + 0 + + + Output_Frequency15 + 0 + + + PINC15 + 0 + + + Phase_Offset_Angles15 + 0 + + + POFF15 + 0 + + + Output_Frequency16 + 0 + + + PINC16 + 0 + + + Phase_Offset_Angles16 + 0 + + + POFF16 + 0 + + + POR_mode + POR Mode + false + + + GUI_Behaviour + Coregen + + + explicit_period + false + + + period + 1 + + + + + DDS Compiler + 20 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v2/src/dds_top.v b/firmware/ip/axis_sg_mux4_v2/src/dds_top.v new file mode 100644 index 0000000..c940d26 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/dds_top.v @@ -0,0 +1,163 @@ +module dds_top ( + // Reset and clock. + rstn , + clk , + + // DDS output. + dds_dout_o , + + // Registers. + PINC_REG , + GAIN_REG , + WE_REG + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input rstn; +input clk; + +output [N_DDS*32-1:0] dds_dout_o; + +input [31:0] PINC_REG; +input [15:0] GAIN_REG; +input WE_REG; + +/********************/ +/* Internal signals */ +/********************/ +// DDS input control. +reg dds_tvalid_r; +wire [N_DDS*72-1:0] dds_ctrl_int; +reg [N_DDS*72-1:0] dds_ctrl_int_r; + +// DDS output. +wire [31:0] dds_dout [0:N_DDS-1]; +wire [31:0] dds_dout_la [0:N_DDS-1]; + +// Product. +wire signed [15:0] gain; +wire signed [15:0] prod_a_real [0:N_DDS-1]; +wire signed [15:0] prod_a_imag [0:N_DDS-1]; +wire signed [31:0] prod_real [0:N_DDS-1]; +wire signed [31:0] prod_imag [0:N_DDS-1]; +reg [31:0] prod_real_r1[0:N_DDS-1]; +reg [31:0] prod_imag_r1[0:N_DDS-1]; +wire [15:0] prod_real_q [0:N_DDS-1]; +wire [15:0] prod_imag_q [0:N_DDS-1]; +wire [31:0] prod [0:N_DDS-1]; +reg [31:0] prod_r1 [0:N_DDS-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Phase Control block. +phase_ctrl + #( + .N_DDS (N_DDS ) + ) + phase_ctrl_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // dds control. + .dds_ctrl_o (dds_ctrl_int ), + + // Registers. + .PINC_REG (PINC_REG ), + .WE_REG (WE_REG ) + ); + +generate +genvar i; + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_axi.vhd b/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_dc.vhd b/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v2/src/fifo/gray2bin.vhd b/firmware/ip/axis_sg_mux4_v2/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v2/src/fifo/rd2axi.vhd b/firmware/ip/axis_sg_mux4_v2/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v2/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_sg_mux4_v2/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v2/src/latency_reg.v b/firmware/ip/axis_sg_mux4_v2/src/latency_reg.v new file mode 100644 index 0000000..687a9f3 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v2/src/tb/tb.sv b/firmware/ip/axis_sg_mux4_v2/src/tb/tb.sv new file mode 100644 index 0000000..5dce62b --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v2/src/tb/tb.sv @@ -0,0 +1,340 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter N_DDS = 2; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +// s_axis interfase. +wire [39:0] s_axis_tdata; +wire s_axis_tready; +reg s_axis_tvalid; + +// m_axis interfase. +wire [N_DDS*32-1:0] m_axis_tdata; +reg m_axis_tready = 1; +wire m_axis_tvalid; + +// Waveform fields. +reg [31:0] nsamp_r; +reg [7:0] mask_r; + +// Assignment of data out for debugging. +wire [31:0] dout_ii [0:N_DDS-1]; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// TB control. +reg tb_load_wave = 0; +reg tb_load_wave_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m_axis_tdata[32*ii +: 32]; +end +endgenerate + +// M_AXI. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_sg_mux4_v1 + # + ( + .N_DDS(N_DDS) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // s_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready (s_axis_tready ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // AXIS Master for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +// Waveform fields. +assign s_axis_tdata = {mask_r,nsamp_r}; + + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("###########################"); + $display("### Program Frequencies ###"); + $display("###########################"); + $display("t = %0t", $time); + + // PINC0_REG + data_wr = freq_calc(100, N_DDS, 1); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*0, prot, data_wr, resp); + #10; + + // PINC1_REG + data_wr = freq_calc(100, N_DDS, 11); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); + #10; + + // PINC2_REG + data_wr = freq_calc(100, N_DDS, 27); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, data_wr, resp); + #10; + + // PINC3_REG + data_wr = freq_calc(100, N_DDS, 115); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); + #10; + + // GAIN0_REG + data_wr = 32000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); + #10; + + // GAIN1_REG + data_wr = 25000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*5, prot, data_wr, resp); + #10; + + // GAIN2_REG + data_wr = 10000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*6, prot, data_wr, resp); + #10; + + // GAIN3_REG + data_wr = 1000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*7, prot, data_wr, resp); + #10; + + // we. + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*8, prot, data_wr, resp); + #10; + + // we. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*8, prot, data_wr, resp); + #10; + + $display("#######################"); + $display("### Queue Waveforms ###"); + $display("#######################"); + $display("t = %0t", $time); + + // Queue waveforms and write output while queuing. + tb_load_wave <= 1; + tb_write_out <= 1; + wait (tb_load_wave_done); + + #30000; + + // Stop writing output data. + tb_write_out <= 0; + + #20000; + +end + +// Load waveforms. +initial begin + s_axis_tvalid <= 0; + nsamp_r <= 0; + mask_r <= 0; + + wait (tb_load_wave); + wait (s_axis_tready); + + @(posedge aclk); + $display("t = %0t", $time); + s_axis_tvalid <= 1; + nsamp_r <= 550; + mask_r <= 8'b0000_1111; + + @(posedge aclk); + $display("t = %0t", $time); + s_axis_tvalid <= 1; + nsamp_r <= 350; + mask_r <= 8'b0000_1111; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid_i <= 1; + //nsamp_r <= 25; + //mask_r <= 8'b0000_0010; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid_i <= 1; + //nsamp_r <= 35; + //mask_r <= 8'b0000_0100; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid_i <= 1; + //nsamp_r <= 63; + //mask_r <= 8'b0000_1000; + + @(posedge aclk); + s_axis_tvalid <= 0; + tb_load_wave_done <= 1; +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d, imag_d; + + // Output file. + fd = $fopen("../../../../../tb/dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, idx, real, imag"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i + + user.org + user + axis_sg_mux4_v3 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_sg_mux4_v3 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + a303c385 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_sg_mux4_v3 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + a303c385 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 429ef1d0 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 39 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N_DDS + N Dds + 2 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux4_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/sg_mux4.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mux4_v3.v + verilogSource + CHECKSUM_e34aa402 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux4_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/sg_mux4.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mux4_v3.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_sg_mux4_v3_v1_0.tcl + tclSource + CHECKSUM_429ef1d0 + XGUI_VERSION_2 + + + + AXIS SG Mux4, Real Output, V3. + + + N_DDS + N Dds + 2 + + + Component_Name + axis_sg_mux4_v3_v1_0 + + + + + + zynquplus + + + /UserIP + + AXIS SG Mux4, V3 + package_project + 2 + 2024-01-25T16:25:58Z + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v3/src/axi_mst_0.xcix b/firmware/ip/axis_sg_mux4_v3/src/axi_mst_0.xcix new file mode 100644 index 0000000..212338d Binary files /dev/null and b/firmware/ip/axis_sg_mux4_v3/src/axi_mst_0.xcix differ diff --git a/firmware/ip/axis_sg_mux4_v3/src/axi_slv.vhd b/firmware/ip/axis_sg_mux4_v3/src/axi_slv.vhd new file mode 100644 index 0000000..c92dcb1 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/axi_slv.vhd @@ -0,0 +1,537 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + PINC0_REG : out std_logic_vector (31 downto 0); + PINC1_REG : out std_logic_vector (31 downto 0); + PINC2_REG : out std_logic_vector (31 downto 0); + PINC3_REG : out std_logic_vector (31 downto 0); + GAIN0_REG : out std_logic_vector (15 downto 0); + GAIN1_REG : out std_logic_vector (15 downto 0); + GAIN2_REG : out std_logic_vector (15 downto 0); + GAIN3_REG : out std_logic_vector (15 downto 0); + WE_REG : out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + -- 0 : PINC0_REG : 32-bit. Frequency of output 0. + -- 1 : PINC1_REG : 32-bit. Frequency of output 1. + -- 2 : PINC2_REG : 32-bit. Frequency of output 2. + -- 3 : PINC3_REG : 32-bit. Frequency of output 3. + -- 4 : GAIN0_REG : 16-bit. Frequency of output 0. + -- 5 : GAIN1_REG : 16-bit. Frequency of output 1. + -- 6 : GAIN2_REG : 16-bit. Frequency of output 2. + -- 7 : GAIN3_REG : 16-bit. Frequency of output 3. + -- 8 : WE_REG : 1-bit. Register write. + + -- Output Registers. + PINC0_REG <= slv_reg0(31 downto 0); + PINC1_REG <= slv_reg1(31 downto 0); + PINC2_REG <= slv_reg2(31 downto 0); + PINC3_REG <= slv_reg3(31 downto 0); + GAIN0_REG <= slv_reg4(15 downto 0); + GAIN1_REG <= slv_reg5(15 downto 0); + GAIN2_REG <= slv_reg6(15 downto 0); + GAIN3_REG <= slv_reg7(15 downto 0); + WE_REG <= slv_reg8(0); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v3/src/axis_sg_mux4_v3.v b/firmware/ip/axis_sg_mux4_v3/src/axis_sg_mux4_v3.v new file mode 100644 index 0000000..c537317 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/axis_sg_mux4_v3.v @@ -0,0 +1,194 @@ +// Signal Generator V4. +// s_axi_aclk : clock for s_axi_* +// aclk : clock for s_axis_* and m_axis_* +// +module axis_sg_mux4_v3 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // s_* and m_* reset/clock. + aclk , + aresetn , + + // S_AXIS to queue waveforms. + s_axis_tready , + s_axis_tvalid , + s_axis_tdata , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [39:0] s_axis_tdata; + +input m_axis_tready; +output m_axis_tvalid; +output [N_DDS*16-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] PINC0_REG; +wire [31:0] PINC1_REG; +wire [31:0] PINC2_REG; +wire [31:0] PINC3_REG; +wire [15:0] GAIN0_REG; +wire [15:0] GAIN1_REG; +wire [15:0] GAIN2_REG; +wire [15:0] GAIN3_REG; +wire WE_REG; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .GAIN0_REG (GAIN0_REG ), + .GAIN1_REG (GAIN1_REG ), + .GAIN2_REG (GAIN2_REG ), + .GAIN3_REG (GAIN3_REG ), + .WE_REG (WE_REG ) + ); + +sg_mux4 + #( + .N_DDS (N_DDS ) + ) + sg_mux4_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready_o (s_axis_tready ), + .s_axis_tvalid_i (s_axis_tvalid ), + .s_axis_tdata_i (s_axis_tdata ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .GAIN0_REG (GAIN0_REG ), + .GAIN1_REG (GAIN1_REG ), + .GAIN2_REG (GAIN2_REG ), + .GAIN3_REG (GAIN3_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_sg_mux4_v3/src/ctrl.sv b/firmware/ip/axis_sg_mux4_v3/src/ctrl.sv new file mode 100644 index 0000000..e1ccea9 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/ctrl.sv @@ -0,0 +1,175 @@ +//Format of waveform interface: +// |----------|---------| +// | 39 .. 32 | 31 .. 0 | +// |----------|---------| +// | mask | nsamp | +// |----------|---------| +// nsamp : 32 bits +// mask : 8 bits +// +// Total : 40. +module ctrl ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // Mask output. + mask_o , + + // Output enable. + en_o ); + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [39:0] fifo_dout_i; +output [7:0] mask_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +reg rd_en_int; + +// Fifo dout register. +reg [39:0] fifo_dout_r; + +// Number of samples. +wire [31:0] nsamp_int; + +// Mask. +wire [7:0] mask_int; +wire [7:0] mask_la; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +wire en_reg_la; + +// Load register. +reg load_r; + +// Latency for mask. +latency_reg + #( + .N(2), + .B(8) + ) + mask_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (mask_int ), + .dout (mask_la ) + ); + +// Latency for en_reg. +latency_reg + #( + .N(3), + .B(1) + ) + en_reg_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (en_reg ), + .dout (en_reg_la ) + ); + + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + + // Load enable flag. + load_r <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (~fifo_empty_i) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Load enable flag. + load_r <= load_int; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (rd_en_int) + if (!fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign nsamp_int = fifo_dout_r[31:0]; +assign mask_int = fifo_dout_r[39:32]; + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mask_o = mask_la; +assign en_o = en_reg_la; + +endmodule + diff --git a/firmware/ip/axis_sg_mux4_v3/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_sg_mux4_v3/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 0000000..3d3cffb --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,477 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_compiler_0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 2 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 9 + 0 + 0 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 10 + 1 + 0 + 9 + 0 + 16 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 0 + 1 + 0 + 1 + 0 + 72 + 1 + 1 + zynquplus + Full_Range + 1 + dds_compiler_0 + Not_Required + 256 + Maximal + 0.08 + Coregen + false + false + false + false + 10 + Configurable + Not_Required + Not_Required + Auto + Standard + 9 + false + false + Auto + Twos_Complement + Speed + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Sine + 16 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + System_Parameters + Phase_Generator_and_SIN_COS_LUT + Streaming + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32 + Streaming + true + On_Vector + Not_Required + 1 + 96 + false + 1 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 22 + TRUE + ../../../project_1/project_1.gen/sources_1/ip/dds_compiler_0 + + . + 2022.1 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux4_v3/src/dds_top.v b/firmware/ip/axis_sg_mux4_v3/src/dds_top.v new file mode 100644 index 0000000..635b09b --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/dds_top.v @@ -0,0 +1,138 @@ +module dds_top ( + // Reset and clock. + rstn , + clk , + + // DDS output. + dds_dout_o , + + // Registers. + PINC_REG , + GAIN_REG , + WE_REG + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input rstn; +input clk; + +output [N_DDS*16-1:0] dds_dout_o; + +input [31:0] PINC_REG; +input [15:0] GAIN_REG; +input WE_REG; + +/********************/ +/* Internal signals */ +/********************/ +// DDS input control. +wire [N_DDS*72-1:0] dds_ctrl_int; +reg [N_DDS*72-1:0] dds_ctrl_int_r; + +// DDS output. +wire [15:0] dds_dout [0:N_DDS-1]; +wire [15:0] dds_dout_la [0:N_DDS-1]; + +// Product. +wire signed [15:0] gain; +wire signed [15:0] prod_a_real [0:N_DDS-1]; +wire signed [31:0] prod_real [0:N_DDS-1]; +reg [31:0] prod_real_r1[0:N_DDS-1]; +wire [15:0] prod_real_q [0:N_DDS-1]; +wire [15:0] prod [0:N_DDS-1]; +reg [15:0] prod_r1 [0:N_DDS-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Phase Control block. +phase_ctrl + #( + .N_DDS (N_DDS ) + ) + phase_ctrl_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // dds control. + .dds_ctrl_o (dds_ctrl_int ), + + // Registers. + .PINC_REG (PINC_REG ), + .WE_REG (WE_REG ) + ); + +generate +genvar i; + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v3/src/fifo/fifo_axi.vhd b/firmware/ip/axis_sg_mux4_v3/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v3/src/fifo/fifo_dc.vhd b/firmware/ip/axis_sg_mux4_v3/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_sg_mux4_v3/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_sg_mux4_v3/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v3/src/fifo/gray2bin.vhd b/firmware/ip/axis_sg_mux4_v3/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v3/src/fifo/rd2axi.vhd b/firmware/ip/axis_sg_mux4_v3/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v3/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_sg_mux4_v3/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v3/src/latency_reg.v b/firmware/ip/axis_sg_mux4_v3/src/latency_reg.v new file mode 100644 index 0000000..4150ef6 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +(* srl_style = "register" *) reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux4_v3/src/tb/tb.sv b/firmware/ip/axis_sg_mux4_v3/src/tb/tb.sv new file mode 100644 index 0000000..f729a46 --- /dev/null +++ b/firmware/ip/axis_sg_mux4_v3/src/tb/tb.sv @@ -0,0 +1,339 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter N_DDS = 16; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +// s_axis interfase. +wire [39:0] s_axis_tdata; +wire s_axis_tready; +reg s_axis_tvalid; + +// m_axis interfase. +wire [N_DDS*16-1:0] m_axis_tdata; +reg m_axis_tready = 1; +wire m_axis_tvalid; + +// Waveform fields. +reg [31:0] nsamp_r; +reg [7:0] mask_r; + +// Assignment of data out for debugging. +wire [15:0] dout_ii [0:N_DDS-1]; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// TB control. +reg tb_load_wave = 0; +reg tb_load_wave_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m_axis_tdata[16*ii +: 16]; +end +endgenerate + +// M_AXI. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_sg_mux4_v3 + # + ( + .N_DDS(N_DDS) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // s_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready (s_axis_tready ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // AXIS Master for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +// Waveform fields. +assign s_axis_tdata = {mask_r,nsamp_r}; + + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("###########################"); + $display("### Program Frequencies ###"); + $display("###########################"); + $display("t = %0t", $time); + + // PINC0_REG + data_wr = freq_calc(100, N_DDS, 1); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*0, prot, data_wr, resp); + #10; + + // PINC1_REG + data_wr = freq_calc(100, N_DDS, 11); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); + #10; + + // PINC2_REG + data_wr = freq_calc(100, N_DDS, 27); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, data_wr, resp); + #10; + + // PINC3_REG + data_wr = freq_calc(100, N_DDS, 115); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); + #10; + + // GAIN0_REG + data_wr = 32000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); + #10; + + // GAIN1_REG + data_wr = 25000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*5, prot, data_wr, resp); + #10; + + // GAIN2_REG + data_wr = 10000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*6, prot, data_wr, resp); + #10; + + // GAIN3_REG + data_wr = 1000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*7, prot, data_wr, resp); + #10; + + // we. + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*8, prot, data_wr, resp); + #10; + + // we. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*8, prot, data_wr, resp); + #10; + + $display("#######################"); + $display("### Queue Waveforms ###"); + $display("#######################"); + $display("t = %0t", $time); + + // Queue waveforms and write output while queuing. + tb_load_wave <= 1; + tb_write_out <= 1; + wait (tb_load_wave_done); + + #30000; + + // Stop writing output data. + tb_write_out <= 0; + + #20000; + +end + +// Load waveforms. +initial begin + s_axis_tvalid <= 0; + nsamp_r <= 0; + mask_r <= 0; + + wait (tb_load_wave); + wait (s_axis_tready); + + @(posedge aclk); + $display("t = %0t", $time); + s_axis_tvalid <= 1; + nsamp_r <= 550; + mask_r <= 8'b0000_1111; + + @(posedge aclk); + $display("t = %0t", $time); + s_axis_tvalid <= 1; + nsamp_r <= 350; + mask_r <= 8'b0000_1111; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid_i <= 1; + //nsamp_r <= 25; + //mask_r <= 8'b0000_0010; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid_i <= 1; + //nsamp_r <= 35; + //mask_r <= 8'b0000_0100; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid_i <= 1; + //nsamp_r <= 63; + //mask_r <= 8'b0000_1000; + + @(posedge aclk); + s_axis_tvalid <= 0; + tb_load_wave_done <= 1; +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d; + + // Output file. + fd = $fopen("../../../../../tb/dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, idx, real"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i + + user.org + user + axis_sg_mux8_v1 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_sg_mux8_v1 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + a2c53958 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_sg_mux8_v1 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + a2c53958 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 429ef1d0 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 39 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N_DDS + N Dds + 2 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux8_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/axi_slv.v + verilogSource + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/mult_32x32.v + verilogSource + + + src/sg_mux8.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mux8_v1.v + verilogSource + CHECKSUM_93286a60 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_sg_mux8_i/GEN_out[0].dds_top_i/GEN_dds[0].dds_i/dds_compiler_0 + + + src/axi_slv.v + verilogSource + + + src/dds_top.v + verilogSource + + + src/latency_reg.v + verilogSource + + + src/mult_32x32.v + verilogSource + + + src/sg_mux8.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/phase_ctrl.sv + systemVerilogSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_sg_mux8_v1.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_sg_mux8_v1_v1_0.tcl + tclSource + CHECKSUM_429ef1d0 + XGUI_VERSION_2 + + + + AXIS SG Mux8, Real Output, V1. + + + N_DDS + N Dds + 2 + + + Component_Name + axis_sg_mux8_v1_v1_0 + + + + + + zynquplus + + + /UserIP + + AXIS SG Mux8, V1 + package_project + 2 + 2024-04-05T19:49:55Z + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/axis_sg_mux8_v1/src/axi_mst_0.xcix b/firmware/ip/axis_sg_mux8_v1/src/axi_mst_0.xcix new file mode 100644 index 0000000..f737726 Binary files /dev/null and b/firmware/ip/axis_sg_mux8_v1/src/axi_mst_0.xcix differ diff --git a/firmware/ip/axis_sg_mux8_v1/src/axi_slv.v b/firmware/ip/axis_sg_mux8_v1/src/axi_slv.v new file mode 100644 index 0000000..a7089bb --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/axi_slv.v @@ -0,0 +1,1072 @@ +`timescale 1 ns / 1 ps + +module axi_slv + ( + input wire s_axi_aclk , + input wire s_axi_aresetn , + + // Write Address Channel. + input wire [7:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + + // Write Data Channel. + input wire [31:0] s_axi_wdata , + input wire [3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + + // Write Response Channel. + output wire [1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + + // Read Address Channel. + input wire [7:0] s_axi_araddr , + input wire [2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + + // Read Data Channel. + output wire [31:0] s_axi_rdata , + output wire [1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , + + // Registers. + output wire [31:0] PINC0_REG , + output wire [31:0] PINC1_REG , + output wire [31:0] PINC2_REG , + output wire [31:0] PINC3_REG , + output wire [31:0] PINC4_REG , + output wire [31:0] PINC5_REG , + output wire [31:0] PINC6_REG , + output wire [31:0] PINC7_REG , + output wire [31:0] POFF0_REG , + output wire [31:0] POFF1_REG , + output wire [31:0] POFF2_REG , + output wire [31:0] POFF3_REG , + output wire [31:0] POFF4_REG , + output wire [31:0] POFF5_REG , + output wire [31:0] POFF6_REG , + output wire [31:0] POFF7_REG , + output wire [31:0] GAIN0_REG , + output wire [31:0] GAIN1_REG , + output wire [31:0] GAIN2_REG , + output wire [31:0] GAIN3_REG , + output wire [31:0] GAIN4_REG , + output wire [31:0] GAIN5_REG , + output wire [31:0] GAIN6_REG , + output wire [31:0] GAIN7_REG , + output wire WE_REG +); + +// Width of S_AXI data bus +localparam integer C_S_AXI_DATA_WIDTH = 32; +// Width of S_AXI address bus +localparam integer C_S_AXI_ADDR_WIDTH = 8; + +// AXI4LITE signals +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr; +reg axi_awready; +reg axi_wready; +reg [1 : 0] axi_bresp; +reg axi_bvalid; +reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr; +reg axi_arready; +reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata; +reg [1 : 0] axi_rresp; +reg axi_rvalid; + +// Example-specific design signals +// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH +// ADDR_LSB is used for addressing 32/64 bit registers/memories +// ADDR_LSB = 2 for 32 bits (n downto 2) +// ADDR_LSB = 3 for 64 bits (n downto 3) +localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1; +localparam integer OPT_MEM_ADDR_BITS = 5; +//---------------------------------------------- +//-- Signals for user logic register space example +//------------------------------------------------ +//-- Number of Slave Registers 64 +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg32; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg33; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg34; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg35; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg36; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg37; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg38; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg39; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg40; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg41; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg42; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg43; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg44; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg45; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg46; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg47; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg48; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg49; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg50; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg51; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg52; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg53; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg54; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg55; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg56; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg57; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg58; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg59; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg60; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg61; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg62; +reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg63; +wire slv_reg_rden; +wire slv_reg_wren; +reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out; +integer byte_index; +reg aw_en; + +// I/O Connections assignments + +assign s_axi_awready = axi_awready; +assign s_axi_wready = axi_wready; +assign s_axi_bresp = axi_bresp; +assign s_axi_bvalid = axi_bvalid; +assign s_axi_arready = axi_arready; +assign s_axi_rdata = axi_rdata; +assign s_axi_rresp = axi_rresp; +assign s_axi_rvalid = axi_rvalid; +// Implement axi_awready generation +// axi_awready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_awready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awready <= 1'b0; + aw_en <= 1'b1; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // slave is ready to accept write address when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_awready <= 1'b1; + aw_en <= 1'b0; + end + else if (s_axi_bready && axi_bvalid) + begin + aw_en <= 1'b1; + axi_awready <= 1'b0; + end + else + begin + axi_awready <= 1'b0; + end + end +end + +// Implement axi_awaddr latching +// This process is used to latch the address when both +// s_axi_awvalid and s_axi_wvalid are valid. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_awaddr <= 0; + end + else + begin + if (~axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) + begin + // Write Address latching + axi_awaddr <= s_axi_awaddr; + end + end +end + +// Implement axi_wready generation +// axi_wready is asserted for one s_axi_aclk clock cycle when both +// s_axi_awvalid and s_axi_wvalid are asserted. axi_wready is +// de-asserted when reset is low. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_wready <= 1'b0; + end + else + begin + if (~axi_wready && s_axi_wvalid && s_axi_awvalid && aw_en ) + begin + // slave is ready to accept write data when + // there is a valid write address and write data + // on the write address and data bus. This design + // expects no outstanding transactions. + axi_wready <= 1'b1; + end + else + begin + axi_wready <= 1'b0; + end + end +end + +// Implement memory mapped register select and write logic generation +// The write data is accepted and written to memory mapped registers when +// axi_awready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. Write strobes are used to +// select byte enables of slave registers while writing. +// These registers are cleared when reset (active low) is applied. +// Slave register write enable is asserted when valid address and data are available +// and the slave is ready to accept the write address and write data. +assign slv_reg_wren = axi_wready && s_axi_wvalid && axi_awready && s_axi_awvalid; + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + slv_reg0 <= 0; + slv_reg1 <= 0; + slv_reg2 <= 0; + slv_reg3 <= 0; + slv_reg4 <= 0; + slv_reg5 <= 0; + slv_reg6 <= 0; + slv_reg7 <= 0; + slv_reg8 <= 0; + slv_reg9 <= 0; + slv_reg10 <= 0; + slv_reg11 <= 0; + slv_reg12 <= 0; + slv_reg13 <= 0; + slv_reg14 <= 0; + slv_reg15 <= 0; + slv_reg16 <= 0; + slv_reg17 <= 0; + slv_reg18 <= 0; + slv_reg19 <= 0; + slv_reg20 <= 0; + slv_reg21 <= 0; + slv_reg22 <= 0; + slv_reg23 <= 0; + slv_reg24 <= 0; + slv_reg25 <= 0; + slv_reg26 <= 0; + slv_reg27 <= 0; + slv_reg28 <= 0; + slv_reg29 <= 0; + slv_reg30 <= 0; + slv_reg31 <= 0; + slv_reg32 <= 0; + slv_reg33 <= 0; + slv_reg34 <= 0; + slv_reg35 <= 0; + slv_reg36 <= 0; + slv_reg37 <= 0; + slv_reg38 <= 0; + slv_reg39 <= 0; + slv_reg40 <= 0; + slv_reg41 <= 0; + slv_reg42 <= 0; + slv_reg43 <= 0; + slv_reg44 <= 0; + slv_reg45 <= 0; + slv_reg46 <= 0; + slv_reg47 <= 0; + slv_reg48 <= 0; + slv_reg49 <= 0; + slv_reg50 <= 0; + slv_reg51 <= 0; + slv_reg52 <= 0; + slv_reg53 <= 0; + slv_reg54 <= 0; + slv_reg55 <= 0; + slv_reg56 <= 0; + slv_reg57 <= 0; + slv_reg58 <= 0; + slv_reg59 <= 0; + slv_reg60 <= 0; + slv_reg61 <= 0; + slv_reg62 <= 0; + slv_reg63 <= 0; + end + else begin + if (slv_reg_wren) + begin + case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 0 + slv_reg0[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h01: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 1 + slv_reg1[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h02: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 2 + slv_reg2[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h03: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 3 + slv_reg3[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h04: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 4 + slv_reg4[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h05: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 5 + slv_reg5[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h06: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 6 + slv_reg6[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h07: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 7 + slv_reg7[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h08: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 8 + slv_reg8[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h09: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 9 + slv_reg9[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 10 + slv_reg10[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 11 + slv_reg11[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 12 + slv_reg12[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 13 + slv_reg13[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 14 + slv_reg14[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h0F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 15 + slv_reg15[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h10: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 16 + slv_reg16[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h11: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 17 + slv_reg17[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h12: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 18 + slv_reg18[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h13: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 19 + slv_reg19[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h14: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 20 + slv_reg20[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h15: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 21 + slv_reg21[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h16: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 22 + slv_reg22[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h17: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 23 + slv_reg23[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h18: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 24 + slv_reg24[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h19: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 25 + slv_reg25[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 26 + slv_reg26[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 27 + slv_reg27[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 28 + slv_reg28[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 29 + slv_reg29[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 30 + slv_reg30[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h1F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 31 + slv_reg31[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h20: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 32 + slv_reg32[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h21: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 33 + slv_reg33[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h22: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 34 + slv_reg34[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h23: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 35 + slv_reg35[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h24: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 36 + slv_reg36[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h25: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 37 + slv_reg37[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h26: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 38 + slv_reg38[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h27: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 39 + slv_reg39[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h28: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 40 + slv_reg40[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h29: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 41 + slv_reg41[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 42 + slv_reg42[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 43 + slv_reg43[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 44 + slv_reg44[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 45 + slv_reg45[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 46 + slv_reg46[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h2F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 47 + slv_reg47[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h30: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 48 + slv_reg48[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h31: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 49 + slv_reg49[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h32: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 50 + slv_reg50[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h33: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 51 + slv_reg51[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h34: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 52 + slv_reg52[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h35: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 53 + slv_reg53[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h36: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 54 + slv_reg54[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h37: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 55 + slv_reg55[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h38: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 56 + slv_reg56[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h39: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 57 + slv_reg57[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 58 + slv_reg58[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 59 + slv_reg59[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 60 + slv_reg60[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 61 + slv_reg61[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 62 + slv_reg62[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + 6'h3F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( s_axi_wstrb[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 63 + slv_reg63[(byte_index*8) +: 8] <= s_axi_wdata[(byte_index*8) +: 8]; + end + default : begin + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + slv_reg16 <= slv_reg16; + slv_reg17 <= slv_reg17; + slv_reg18 <= slv_reg18; + slv_reg19 <= slv_reg19; + slv_reg20 <= slv_reg20; + slv_reg21 <= slv_reg21; + slv_reg22 <= slv_reg22; + slv_reg23 <= slv_reg23; + slv_reg24 <= slv_reg24; + slv_reg25 <= slv_reg25; + slv_reg26 <= slv_reg26; + slv_reg27 <= slv_reg27; + slv_reg28 <= slv_reg28; + slv_reg29 <= slv_reg29; + slv_reg30 <= slv_reg30; + slv_reg31 <= slv_reg31; + slv_reg32 <= slv_reg32; + slv_reg33 <= slv_reg33; + slv_reg34 <= slv_reg34; + slv_reg35 <= slv_reg35; + slv_reg36 <= slv_reg36; + slv_reg37 <= slv_reg37; + slv_reg38 <= slv_reg38; + slv_reg39 <= slv_reg39; + slv_reg40 <= slv_reg40; + slv_reg41 <= slv_reg41; + slv_reg42 <= slv_reg42; + slv_reg43 <= slv_reg43; + slv_reg44 <= slv_reg44; + slv_reg45 <= slv_reg45; + slv_reg46 <= slv_reg46; + slv_reg47 <= slv_reg47; + slv_reg48 <= slv_reg48; + slv_reg49 <= slv_reg49; + slv_reg50 <= slv_reg50; + slv_reg51 <= slv_reg51; + slv_reg52 <= slv_reg52; + slv_reg53 <= slv_reg53; + slv_reg54 <= slv_reg54; + slv_reg55 <= slv_reg55; + slv_reg56 <= slv_reg56; + slv_reg57 <= slv_reg57; + slv_reg58 <= slv_reg58; + slv_reg59 <= slv_reg59; + slv_reg60 <= slv_reg60; + slv_reg61 <= slv_reg61; + slv_reg62 <= slv_reg62; + slv_reg63 <= slv_reg63; + end + endcase + end + end +end + +// Implement write response logic generation +// The write response and response valid signals are asserted by the slave +// when axi_wready, s_axi_wvalid, axi_wready and s_axi_wvalid are asserted. +// This marks the acceptance of address and indicates the status of +// write transaction. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_bvalid <= 0; + axi_bresp <= 2'b0; + end + else + begin + if (axi_awready && s_axi_awvalid && ~axi_bvalid && axi_wready && s_axi_wvalid) + begin + // indicates a valid write response is available + axi_bvalid <= 1'b1; + axi_bresp <= 2'b0; // 'OKAY' response + end // work error responses in future + else + begin + if (s_axi_bready && axi_bvalid) + //check if bready is asserted while bvalid is high) + //(there is a possibility that bready is always asserted high) + begin + axi_bvalid <= 1'b0; + end + end + end +end + +// Implement axi_arready generation +// axi_arready is asserted for one s_axi_aclk clock cycle when +// s_axi_arvalid is asserted. axi_awready is +// de-asserted when reset (active low) is asserted. +// The read address is also latched when s_axi_arvalid is +// asserted. axi_araddr is reset to zero on reset assertion. + +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_arready <= 1'b0; + axi_araddr <= 32'b0; + end + else + begin + if (~axi_arready && s_axi_arvalid) + begin + // indicates that the slave has acceped the valid read address + axi_arready <= 1'b1; + // Read address latching + axi_araddr <= s_axi_araddr; + end + else + begin + axi_arready <= 1'b0; + end + end +end + +// Implement axi_arvalid generation +// axi_rvalid is asserted for one s_axi_aclk clock cycle when both +// s_axi_arvalid and axi_arready are asserted. The slave registers +// data are available on the axi_rdata bus at this instance. The +// assertion of axi_rvalid marks the validity of read data on the +// bus and axi_rresp indicates the status of read transaction.axi_rvalid +// is deasserted on reset (active low). axi_rresp and axi_rdata are +// cleared to zero on reset (active low). +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rvalid <= 0; + axi_rresp <= 0; + end + else + begin + if (axi_arready && s_axi_arvalid && ~axi_rvalid) + begin + // Valid read data is available at the read data bus + axi_rvalid <= 1'b1; + axi_rresp <= 2'b0; // 'OKAY' response + end + else if (axi_rvalid && s_axi_rready) + begin + // Read data is accepted by the master + axi_rvalid <= 1'b0; + end + end +end + +// Implement memory mapped register select and read logic generation +// Slave register read enable is asserted when valid address is available +// and the slave is ready to accept the read address. +assign slv_reg_rden = axi_arready & s_axi_arvalid & ~axi_rvalid; +always @(*) +begin + // Address decoding for reading registers + case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) + 6'h00 : reg_data_out <= slv_reg0; + 6'h01 : reg_data_out <= slv_reg1; + 6'h02 : reg_data_out <= slv_reg2; + 6'h03 : reg_data_out <= slv_reg3; + 6'h04 : reg_data_out <= slv_reg4; + 6'h05 : reg_data_out <= slv_reg5; + 6'h06 : reg_data_out <= slv_reg6; + 6'h07 : reg_data_out <= slv_reg7; + 6'h08 : reg_data_out <= slv_reg8; + 6'h09 : reg_data_out <= slv_reg9; + 6'h0A : reg_data_out <= slv_reg10; + 6'h0B : reg_data_out <= slv_reg11; + 6'h0C : reg_data_out <= slv_reg12; + 6'h0D : reg_data_out <= slv_reg13; + 6'h0E : reg_data_out <= slv_reg14; + 6'h0F : reg_data_out <= slv_reg15; + 6'h10 : reg_data_out <= slv_reg16; + 6'h11 : reg_data_out <= slv_reg17; + 6'h12 : reg_data_out <= slv_reg18; + 6'h13 : reg_data_out <= slv_reg19; + 6'h14 : reg_data_out <= slv_reg20; + 6'h15 : reg_data_out <= slv_reg21; + 6'h16 : reg_data_out <= slv_reg22; + 6'h17 : reg_data_out <= slv_reg23; + 6'h18 : reg_data_out <= slv_reg24; + 6'h19 : reg_data_out <= slv_reg25; + 6'h1A : reg_data_out <= slv_reg26; + 6'h1B : reg_data_out <= slv_reg27; + 6'h1C : reg_data_out <= slv_reg28; + 6'h1D : reg_data_out <= slv_reg29; + 6'h1E : reg_data_out <= slv_reg30; + 6'h1F : reg_data_out <= slv_reg31; + 6'h20 : reg_data_out <= slv_reg32; + 6'h21 : reg_data_out <= slv_reg33; + 6'h22 : reg_data_out <= slv_reg34; + 6'h23 : reg_data_out <= slv_reg35; + 6'h24 : reg_data_out <= slv_reg36; + 6'h25 : reg_data_out <= slv_reg37; + 6'h26 : reg_data_out <= slv_reg38; + 6'h27 : reg_data_out <= slv_reg39; + 6'h28 : reg_data_out <= slv_reg40; + 6'h29 : reg_data_out <= slv_reg41; + 6'h2A : reg_data_out <= slv_reg42; + 6'h2B : reg_data_out <= slv_reg43; + 6'h2C : reg_data_out <= slv_reg44; + 6'h2D : reg_data_out <= slv_reg45; + 6'h2E : reg_data_out <= slv_reg46; + 6'h2F : reg_data_out <= slv_reg47; + 6'h30 : reg_data_out <= slv_reg48; + 6'h31 : reg_data_out <= slv_reg49; + 6'h32 : reg_data_out <= slv_reg50; + 6'h33 : reg_data_out <= slv_reg51; + 6'h34 : reg_data_out <= slv_reg52; + 6'h35 : reg_data_out <= slv_reg53; + 6'h36 : reg_data_out <= slv_reg54; + 6'h37 : reg_data_out <= slv_reg55; + 6'h38 : reg_data_out <= slv_reg56; + 6'h39 : reg_data_out <= slv_reg57; + 6'h3A : reg_data_out <= slv_reg58; + 6'h3B : reg_data_out <= slv_reg59; + 6'h3C : reg_data_out <= slv_reg60; + 6'h3D : reg_data_out <= slv_reg61; + 6'h3E : reg_data_out <= slv_reg62; + 6'h3F : reg_data_out <= slv_reg63; + default : reg_data_out <= 0; + endcase +end + +// Output register or memory read data +always @( posedge s_axi_aclk ) +begin + if ( s_axi_aresetn == 1'b0 ) + begin + axi_rdata <= 0; + end + else + begin + // When there is a valid read address (s_axi_arvalid) with + // acceptance of read address by the slave (axi_arready), + // output the read dada + if (slv_reg_rden) + begin + axi_rdata <= reg_data_out; // register read data + end + end +end + +assign PINC0_REG = slv_reg0 ; +assign PINC1_REG = slv_reg1 ; +assign PINC2_REG = slv_reg2 ; +assign PINC3_REG = slv_reg3 ; +assign PINC4_REG = slv_reg4 ; +assign PINC5_REG = slv_reg5 ; +assign PINC6_REG = slv_reg6 ; +assign PINC7_REG = slv_reg7 ; +assign POFF0_REG = slv_reg8 ; +assign POFF1_REG = slv_reg9 ; +assign POFF2_REG = slv_reg10 ; +assign POFF3_REG = slv_reg11 ; +assign POFF4_REG = slv_reg12 ; +assign POFF5_REG = slv_reg13 ; +assign POFF6_REG = slv_reg14 ; +assign POFF7_REG = slv_reg15 ; +assign GAIN0_REG = slv_reg16 ; +assign GAIN1_REG = slv_reg17 ; +assign GAIN2_REG = slv_reg18 ; +assign GAIN3_REG = slv_reg19 ; +assign GAIN4_REG = slv_reg20 ; +assign GAIN5_REG = slv_reg21 ; +assign GAIN6_REG = slv_reg22 ; +assign GAIN7_REG = slv_reg23 ; +assign WE_REG = slv_reg24[0] ; + +endmodule diff --git a/firmware/ip/axis_sg_mux8_v1/src/axis_sg_mux8_v1.v b/firmware/ip/axis_sg_mux8_v1/src/axis_sg_mux8_v1.v new file mode 100644 index 0000000..c5ff09e --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/axis_sg_mux8_v1.v @@ -0,0 +1,238 @@ +module axis_sg_mux8_v1 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // s_* and m_* reset/clock. + aclk , + aresetn , + + // S_AXIS to queue waveforms. + s_axis_tready , + s_axis_tvalid , + s_axis_tdata , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [7:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [7:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input aresetn; +input aclk; + +output s_axis_tready; +input s_axis_tvalid; +input [39:0] s_axis_tdata; + +input m_axis_tready; +output m_axis_tvalid; +output [N_DDS*16-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] PINC0_REG; +wire [31:0] PINC1_REG; +wire [31:0] PINC2_REG; +wire [31:0] PINC3_REG; +wire [31:0] PINC4_REG; +wire [31:0] PINC5_REG; +wire [31:0] PINC6_REG; +wire [31:0] PINC7_REG; +wire [31:0] POFF0_REG; +wire [31:0] POFF1_REG; +wire [31:0] POFF2_REG; +wire [31:0] POFF3_REG; +wire [31:0] POFF4_REG; +wire [31:0] POFF5_REG; +wire [31:0] POFF6_REG; +wire [31:0] POFF7_REG; +wire [15:0] GAIN0_REG; +wire [15:0] GAIN1_REG; +wire [15:0] GAIN2_REG; +wire [15:0] GAIN3_REG; +wire [15:0] GAIN4_REG; +wire [15:0] GAIN5_REG; +wire [15:0] GAIN6_REG; +wire [15:0] GAIN7_REG; +wire WE_REG; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + + // Write Address Channel. + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_awready (s_axi_awready ), + + // Write Data Channel. + .s_axi_wdata (s_axi_wdata ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + .s_axi_wready (s_axi_wready ), + + // Write Response Channel. + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_bready (s_axi_bready ), + + // Read Address Channel. + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_arready (s_axi_arready ), + + // Read Data Channel. + .s_axi_rdata (s_axi_rdata ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_rready (s_axi_rready ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .PINC4_REG (PINC4_REG ), + .PINC5_REG (PINC5_REG ), + .PINC6_REG (PINC6_REG ), + .PINC7_REG (PINC7_REG ), + .POFF0_REG (POFF0_REG ), + .POFF1_REG (POFF1_REG ), + .POFF2_REG (POFF2_REG ), + .POFF3_REG (POFF3_REG ), + .POFF4_REG (POFF4_REG ), + .POFF5_REG (POFF5_REG ), + .POFF6_REG (POFF6_REG ), + .POFF7_REG (POFF7_REG ), + .GAIN0_REG (GAIN0_REG ), + .GAIN1_REG (GAIN1_REG ), + .GAIN2_REG (GAIN2_REG ), + .GAIN3_REG (GAIN3_REG ), + .GAIN4_REG (GAIN4_REG ), + .GAIN5_REG (GAIN5_REG ), + .GAIN6_REG (GAIN6_REG ), + .GAIN7_REG (GAIN7_REG ), + .WE_REG (WE_REG ) + ); + +sg_mux8 + #( + .N_DDS (N_DDS ) + ) + sg_mux8_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready_o (s_axis_tready ), + .s_axis_tvalid_i (s_axis_tvalid ), + .s_axis_tdata_i (s_axis_tdata ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .PINC0_REG (PINC0_REG ), + .PINC1_REG (PINC1_REG ), + .PINC2_REG (PINC2_REG ), + .PINC3_REG (PINC3_REG ), + .PINC4_REG (PINC4_REG ), + .PINC5_REG (PINC5_REG ), + .PINC6_REG (PINC6_REG ), + .PINC7_REG (PINC7_REG ), + .POFF0_REG (POFF0_REG ), + .POFF1_REG (POFF1_REG ), + .POFF2_REG (POFF2_REG ), + .POFF3_REG (POFF3_REG ), + .POFF4_REG (POFF4_REG ), + .POFF5_REG (POFF5_REG ), + .POFF6_REG (POFF6_REG ), + .POFF7_REG (POFF7_REG ), + .GAIN0_REG (GAIN0_REG ), + .GAIN1_REG (GAIN1_REG ), + .GAIN2_REG (GAIN2_REG ), + .GAIN3_REG (GAIN3_REG ), + .GAIN4_REG (GAIN4_REG ), + .GAIN5_REG (GAIN5_REG ), + .GAIN6_REG (GAIN6_REG ), + .GAIN7_REG (GAIN7_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_sg_mux8_v1/src/ctrl.sv b/firmware/ip/axis_sg_mux8_v1/src/ctrl.sv new file mode 100644 index 0000000..e4d78b0 --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/ctrl.sv @@ -0,0 +1,183 @@ +//Format of waveform interface: +// |----------|---------| +// | 39 .. 32 | 31 .. 0 | +// |----------|---------| +// | mask | nsamp | +// |----------|---------| +// nsamp : 32 bits +// mask : 8 bits +// +// Total : 40. +module ctrl ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // Mask output. + mask_o , + + // Output enable. + en_o ); + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [39:0] fifo_dout_i; +output [7:0] mask_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT0_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +reg rd_en_int; + +// Fifo dout register. +reg [39:0] fifo_dout_r; + +// Number of samples. +wire [31:0] nsamp_int; + +// Mask. +wire [7:0] mask_int; +wire [7:0] mask_la; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +wire en_reg_la; + +// Load register. +reg load_r; + +// Latency for mask. +latency_reg + #( + .N(2), + .B(8) + ) + mask_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (mask_int ), + .dout (mask_la ) + ); + +// Latency for en_reg. +latency_reg + #( + .N(3), + .B(1) + ) + en_reg_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (en_reg ), + .dout (en_reg_la ) + ); + + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + + // Load enable flag. + load_r <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (~fifo_empty_i) + state <= CNT0_ST; + + CNT0_ST: + state <= CNT_ST; + + CNT_ST: + if ( cnt == nsamp_int ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Load enable flag. + load_r <= load_int; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (rd_en_int) + if (!fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT0_ST: + rd_en_int = 0; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign nsamp_int = fifo_dout_r[31:0]; +assign mask_int = fifo_dout_r[39:32]; + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mask_o = mask_la; +assign en_o = en_reg_la; + +endmodule + diff --git a/firmware/ip/axis_sg_mux8_v1/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_sg_mux8_v1/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 0000000..194dafd --- /dev/null +++ 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0000000..aa93fc7 --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/dds_top.v @@ -0,0 +1,141 @@ +module dds_top ( + // Reset and clock. + rstn , + clk , + + // DDS output. + dds_dout_o , + + // Registers. + PINC_REG , + POFF_REG , + GAIN_REG , + WE_REG + ); + +/**************/ +/* Parameters */ +/**************/ +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 2; + +/*********/ +/* Ports */ +/*********/ +input rstn; +input clk; + +output [N_DDS*16-1:0] dds_dout_o; + +input [31:0] PINC_REG; +input [31:0] POFF_REG; +input [15:0] GAIN_REG; +input WE_REG; + +/********************/ +/* Internal signals */ +/********************/ +// DDS input control. +wire [N_DDS*72-1:0] dds_ctrl_int; +reg [N_DDS*72-1:0] dds_ctrl_int_r; + +// DDS output. +wire [15:0] dds_dout [0:N_DDS-1]; +wire [15:0] dds_dout_la [0:N_DDS-1]; + +// Product. +wire signed [15:0] gain; +wire signed [15:0] prod_a_real [0:N_DDS-1]; +wire signed [31:0] prod_real [0:N_DDS-1]; +reg [31:0] prod_real_r1[0:N_DDS-1]; +wire [15:0] prod_real_q [0:N_DDS-1]; +wire [15:0] prod [0:N_DDS-1]; +reg [15:0] prod_r1 [0:N_DDS-1]; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Phase Control block. +phase_ctrl + #( + .N_DDS (N_DDS ) + ) + phase_ctrl_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // dds control. + .dds_ctrl_o (dds_ctrl_int ), + + // Registers. + .PINC_REG (PINC_REG ), + .POFF_REG (POFF_REG ), + .WE_REG (WE_REG ) + ); + +generate +genvar i; + for (i=0; i N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux8_v1/src/fifo/fifo_axi.vhd b/firmware/ip/axis_sg_mux8_v1/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux8_v1/src/fifo/fifo_dc.vhd b/firmware/ip/axis_sg_mux8_v1/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_sg_mux8_v1/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_sg_mux8_v1/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux8_v1/src/fifo/gray2bin.vhd b/firmware/ip/axis_sg_mux8_v1/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux8_v1/src/fifo/rd2axi.vhd b/firmware/ip/axis_sg_mux8_v1/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_sg_mux8_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_sg_mux8_v1/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux8_v1/src/latency_reg.v b/firmware/ip/axis_sg_mux8_v1/src/latency_reg.v new file mode 100644 index 0000000..4150ef6 --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +(* srl_style = "register" *) reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_sg_mux8_v1/src/synth/xdcs/top_sg_mux8.xdc b/firmware/ip/axis_sg_mux8_v1/src/synth/xdcs/top_sg_mux8.xdc new file mode 100644 index 0000000..f6cc48a --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/synth/xdcs/top_sg_mux8.xdc @@ -0,0 +1,66 @@ +create_clock -period 1.000 -name aclk -waveform {0.000 0.500} [get_ports aclk] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {GAIN0_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {GAIN0_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {GAIN1_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {GAIN1_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {GAIN2_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {GAIN2_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {GAIN3_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {GAIN3_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {GAIN4_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {GAIN4_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {GAIN5_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {GAIN5_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {GAIN6_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {GAIN6_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {GAIN7_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {GAIN7_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {PINC0_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {PINC0_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {PINC1_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {PINC1_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {PINC2_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {PINC2_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {PINC3_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {PINC3_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {PINC4_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {PINC4_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {PINC5_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {PINC5_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {PINC6_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {PINC6_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {PINC7_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {PINC7_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {POFF0_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {POFF0_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {POFF1_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {POFF1_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {POFF2_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {POFF2_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {POFF3_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {POFF3_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {POFF4_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {POFF4_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {POFF5_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {POFF5_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {POFF6_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {POFF6_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {POFF7_REG[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {POFF7_REG[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports {s_axis_tdata_i[*]}] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports {s_axis_tdata_i[*]}] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports WE_REG] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports WE_REG] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports aresetn] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports aresetn] +set_input_delay -clock [get_clocks aclk] -min -add_delay 0.100 [get_ports s_axis_tvalid_i] +set_input_delay -clock [get_clocks aclk] -max -add_delay 0.200 [get_ports s_axis_tvalid_i] +set _xlnx_shared_i0 [get_ports {m_axis_tdata_o[*]}] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.090 $_xlnx_shared_i0 +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 $_xlnx_shared_i0 +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.090 [get_ports m_axis_tvalid_o] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports m_axis_tvalid_o] +set_output_delay -clock [get_clocks aclk] -min -add_delay 0.090 [get_ports s_axis_tready_o] +set_output_delay -clock [get_clocks aclk] -max -add_delay 0.300 [get_ports s_axis_tready_o] + +set_false_path -to [all_outputs] diff --git a/firmware/ip/axis_sg_mux8_v1/src/tb/tb.sv b/firmware/ip/axis_sg_mux8_v1/src/tb/tb.sv new file mode 100644 index 0000000..f879613 --- /dev/null +++ b/firmware/ip/axis_sg_mux8_v1/src/tb/tb.sv @@ -0,0 +1,359 @@ +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter N_DDS = 16; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [7:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [7:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +reg aresetn; +reg aclk; + +// s_axis interfase. +wire [39:0] s_axis_tdata; +wire s_axis_tready; +reg s_axis_tvalid; + +// m_axis interfase. +wire [N_DDS*16-1:0] m_axis_tdata; +reg m_axis_tready = 1; +wire m_axis_tvalid; + +// Waveform fields. +reg [31:0] nsamp_r; +reg [7:0] mask_r; + +// Assignment of data out for debugging. +wire [15:0] dout_ii [0:N_DDS-1]; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// TB control. +reg tb_load_wave = 0; +reg tb_load_wave_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m_axis_tdata[16*ii +: 16]; +end +endgenerate + +// M_AXI. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_sg_mux8_v1 + # + ( + .N_DDS(N_DDS) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // s_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS to queue waveforms. + .s_axis_tready (s_axis_tready ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // AXIS Master for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +// Waveform fields. +assign s_axis_tdata = {mask_r,nsamp_r}; + + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("###########################"); + $display("### Program Frequencies ###"); + $display("###########################"); + $display("t = %0t", $time); + + // Register mapping: + // 0-7 : PINC. + // 8-15 : POFF. + // 16-23: GAIN. + // 24 : WE. + + for (int i=0; i<8; i=i+1) begin + // PINCx_REG + data_wr = freq_calc(100, N_DDS, 10+i); + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*i, prot, data_wr, resp); + + // POFFx_REG + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(i+8), prot, data_wr, resp); + + // GAINx_REG + data_wr = 20000+1000*i; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(i+16), prot, data_wr, resp); + + end + + //// PINC0/1/2. + //data_wr = freq_calc(100, N_DDS, 1); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*0, prot, data_wr, resp); + + //data_wr = freq_calc(100, N_DDS, 1); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); + + //data_wr = freq_calc(100, N_DDS, 1); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, data_wr, resp); + + //// POFF0/1/2. + //data_wr = phase_calc(0); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(0+8), prot, data_wr, resp); + + //data_wr = phase_calc(0); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(1+8), prot, data_wr, resp); + + //data_wr = phase_calc(180); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(2+8), prot, data_wr, resp); + + //// GAIN0/1/2. + //data_wr = 30000; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(0+16), prot, data_wr, resp); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(1+16), prot, data_wr, resp); + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(2+16), prot, data_wr, resp); + + //// 0 gain just for quantization... + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*(7+16), prot, 0, resp); + + // WE. + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*24, prot, 1, resp); + #10; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*24, prot, 0, resp); + #10; + + $display("#######################"); + $display("### Queue Waveforms ###"); + $display("#######################"); + $display("t = %0t", $time); + + // Queue waveforms and write output while queuing. + tb_load_wave <= 1; + tb_write_out <= 1; + wait (tb_load_wave_done); + + #50000; + #50000; + + // Stop writing output data. + tb_write_out <= 0; + + #20000; + +end + +// Load waveforms. +initial begin + s_axis_tvalid <= 0; + nsamp_r <= 0; + mask_r <= 0; + + wait (tb_load_wave); + wait (s_axis_tready); + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid <= 1; + //nsamp_r <= 550; + //mask_r <= 8'b0000_1111; + + @(posedge aclk); + $display("t = %0t", $time); + s_axis_tvalid <= 1; + nsamp_r <= 3500; + mask_r <= 8'b1111_1111; + + // Phase-coherency test. + // 1 sine wave first. + // 2 sine waves, same phase, same frequency. + // 2 sine waves, 180 out of phase, same frequency. + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid <= 1; + //nsamp_r <= 2500; + //mask_r <= 8'b1000_0001; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid <= 1; + //nsamp_r <= 2500; + //mask_r <= 8'b0000_0011; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s_axis_tvalid <= 1; + //nsamp_r <= 2500; + //mask_r <= 8'b0000_0101; + + @(posedge aclk); + s_axis_tvalid <= 0; + tb_load_wave_done <= 1; +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d; + + // Output file. + fd = $fopen("../../../../../tb/dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, idx, real"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i + + user.org + user + axis_signal_gen_v4 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s0_axis + + + + + + + TDATA + + + s0_axis_tdata + + + + + TVALID + + + s0_axis_tvalid + + + + + TREADY + + + s0_axis_tready + + + + + + s1_axis + + + + + + + TDATA + + + s1_axis_tdata + + + + + TVALID + + + s1_axis_tvalid + + + + + TREADY + + + s1_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s0_axis_aclk + + + + + + + CLK + + + s0_axis_aclk + + + + + + ASSOCIATED_BUSIF + s0_axis + + + ASSOCIATED_RESET + s0_axis_aresetn + + + + + s0_axis_aresetn + + + + + + + RST + + + s0_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s1_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_signal_gen_v4 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 203ec419 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_signal_gen_v4 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 203ec419 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + e51fb623 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s0_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_tdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s0_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_axis_tdata + + in + + 159 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s1_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 255 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N + N + 12 + + + N_DDS + N Dds + 16 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + + + src/signal_gen.v + verilogSource + + + src/signal_gen_top.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_signal_gen_v4.v + verilogSource + CHECKSUM_084788a4 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dds_compiler_0/dds_compiler_0.xci + xci + + + src/signal_gen.v + verilogSource + + + src/signal_gen_top.v + verilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/axis_signal_gen_v4.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_signal_gen_v4_v1_0.tcl + tclSource + CHECKSUM_e51fb623 + XGUI_VERSION_2 + + + + AXIS Signal Generator V4 with 32-bit resolution, IQ envelope and dithering. + + + N + N + 12 + + + N_DDS + N Dds + 16 + + + Component_Name + axis_signal_gen_v4_v1_0 + + + + + + zynquplus + + + /UserIP + + AXIS Signal Generator V4 + package_project + 14 + 2021-07-21T20:01:35Z + + /home/lstefana/v19.1/ip/axis_signal_gen_v4 + /home/lstefana/v19.1/ip/axis_signal_gen_v4 + /home/lstefana/v19.1/ip/axis_signal_gen_v4 + /home/lstefana/v19.1/ip/axis_signal_gen_v4 + /home/lstefana/v19.1/ip/axis_signal_gen_v4 + /home/lstefana/v19.1/ip/axis_signal_gen_v4 + /home/lstefana/v19.1/ip/axis_signal_gen_v4 + /home/lstefana/v19.1/ip/axis_signal_gen_v4 + /home/lstefana/v19.1/ip/axis_signal_gen_v4 + /home/lstefana/v19.1/ip/axis_signal_gen_v4 + /home/lstefana/v19.1/ip/axis_signal_gen_v4 + /home/lstefana/v19.1/ip/axis_signal_gen_v4 + /home/lstefana/v19.1/ip/axis_signal_gen_v4 + /home/lstefana/v19.1/ip/axis_signal_gen_v4 + /home/lstefana/v19.1/ip/axis_signal_gen_v4 + /home/lstefana/v19.1/ip/axis_signal_gen_v4 + /home/lstefana/v19.1/ip/axis_signal_gen_v4 + /home/lstefana/v19.1/ip/axis_signal_gen_v4 + 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/home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + /home/lstefana/qsystem_2/ip/axis_signal_gen_v4 + + + + 2019.1 + + + + + + + + + diff --git a/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 0000000..5f33135 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 5 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 0000000..5c4d9a9 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 5 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..34f0b12 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,187 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 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Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + + + + + 1 + + + + + S_TARGET_rd_socket + AXIMM Read Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + + + + + 1 + + + + + + + C_AXI_PROTOCOL + 2 + + + C_AXI_INTERFACE_MODE + 0 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_WDATA_WIDTH + 32 + + + C_AXI_RDATA_WIDTH + 32 + + + C_AXI_WID_WIDTH + 0 + + + C_AXI_RID_WIDTH + 0 + + + C_AXI_AWUSER_WIDTH + 0 + + + C_AXI_ARUSER_WIDTH + 0 + + + C_AXI_WUSER_WIDTH + 0 + + + C_AXI_RUSER_WIDTH + 0 + + + C_AXI_BUSER_WIDTH + 0 + + + C_AXI_SUPPORTS_NARROW + 0 + + + C_AXI_HAS_BURST + 0 + + + C_AXI_HAS_LOCK + 0 + + + C_AXI_HAS_CACHE + 0 + + + C_AXI_HAS_REGION + 0 + + + C_AXI_HAS_PROT + 1 + + + C_AXI_HAS_QOS + 0 + + + C_AXI_HAS_WSTRB + 1 + + + C_AXI_HAS_BRESP + 1 + + + C_AXI_HAS_RRESP + 1 + + + C_AXI_HAS_ARESETN + 1 + + + + + + choice_list_04fafd91 + AXI3 + AXI4 + AXI4LITE + + + choice_list_6240decd + READ_ONLY + READ_WRITE + WRITE_ONLY + + + choice_list_642e7122 + MASTER + PASS_THROUGH + SLAVE + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_0fc128e8 + 0 + 0 + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi_mst_0.vho + vhdlTemplate + + + axi_mst_0.veo + verilogTemplate + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_5 + + + + xilinx_synthesisconstraints_view_fileset + + axi_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_5 + + + + xilinx_externalfiles_view_fileset + + axi_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axi_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axi_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_5 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_5 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_5 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 5 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.1 + + + + + + + + + + diff --git a/firmware/ip/axis_signal_gen_v4/src/axi_slv.vhd b/firmware/ip/axis_signal_gen_v4/src/axi_slv.vhd new file mode 100644 index 0000000..f1fb775 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/axi_slv.vhd @@ -0,0 +1,522 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + START_ADDR_REG : out std_logic_vector (31 downto 0); + WE_REG : out std_logic; + RNDQ_REG : out std_logic_vector (31 downto 0); + OUTSEL_REG : out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + -- 0 : START_ADDR_REG : 32-bit. Start address to write into memory. + -- 1 : WE_REG : 1-bit. Enable write into memory. + -- 2 : RNDQ_REG : 32-bit. Noise amplitude for dithering. + -- 3 : OUTSEL_REG : 1-bit. Select real/imaginary output from block. + + -- Output Registers. + START_ADDR_REG <= slv_reg0; + WE_REG <= slv_reg1(0); + RNDQ_REG <= slv_reg2; + OUTSEL_REG <= slv_reg3(0); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v4/src/axis_signal_gen_v4.v b/firmware/ip/axis_signal_gen_v4/src/axis_signal_gen_v4.v new file mode 100644 index 0000000..080beb3 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/axis_signal_gen_v4.v @@ -0,0 +1,204 @@ +// Signal Generator V4. +// s_axi_aclk : clock for s_axi_* +// s0_axis_aclk : clock for s0_axis_* +// aclk : clock for s1_axis_* and m_axis_* +// +module axis_signal_gen_v4 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // AXIS Slave to load memory samples. + s0_axis_aclk , + s0_axis_aresetn , + s0_axis_tdata , + s0_axis_tvalid , + s0_axis_tready , + + // s1_* and m_* reset/clock. + aclk , + aresetn , + + // AXIS Slave to queue waveforms. + s1_axis_tdata , + s1_axis_tvalid , + s1_axis_tready , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +parameter N = 12; + +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 16; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input s0_axis_aclk; +input s0_axis_aresetn; +input [31:0] s0_axis_tdata; +input s0_axis_tvalid; +output s0_axis_tready; + +input aresetn; +input aclk; + +input [159:0] s1_axis_tdata; +input s1_axis_tvalid; +output s1_axis_tready; + +input m_axis_tready; +output m_axis_tvalid; +output [N_DDS*16-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] START_ADDR_REG; +wire WE_REG; +wire [31:0] RNDQ_REG; +wire OUTSEL_REG; + + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG ), + .WE_REG (WE_REG ), + .RNDQ_REG (RNDQ_REG ), + .OUTSEL_REG (OUTSEL_REG ) + ); + +signal_gen_top + #( + .N (N ), + .N_DDS (N_DDS ) + ) + signal_gen_top_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // AXIS Slave to load memory samples. + .s0_axis_aresetn (s0_axis_aresetn ), + .s0_axis_aclk (s0_axis_aclk ), + .s0_axis_tdata_i (s0_axis_tdata ), + .s0_axis_tvalid_i (s0_axis_tvalid ), + .s0_axis_tready_o (s0_axis_tready ), + + // AXIS Slave to queue waveforms. + .s1_axis_tdata_i (s1_axis_tdata ), + .s1_axis_tvalid_i (s1_axis_tvalid ), + .s1_axis_tready_o (s1_axis_tready ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG ), + .WE_REG (WE_REG ), + .RNDQ_REG (RNDQ_REG ), + .OUTSEL_REG (OUTSEL_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v4/src/bram.v b/firmware/ip/axis_signal_gen_v4/src/bram.v new file mode 100644 index 0000000..018317e --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/bram.v @@ -0,0 +1,33 @@ +module bram (clk,ena,wea,addra,dia,doa); + +// Memory address size. +parameter N = 16; +// Data width. +parameter B = 16; + +input clk; +input ena; +input wea; +input [N-1:0] addra; +input [B-1:0] dia; +output [B-1:0] doa; + +// Ram type. +reg [B-1:0] RAM [0:2**N-1]; +reg [B-1:0] doa; + +always @(posedge clk) +begin + if (ena) + begin + if (wea) begin + RAM[addra] <= dia; + end + else begin + doa <= RAM[addra]; + end + end +end + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v4/src/ctrl.sv b/firmware/ip/axis_signal_gen_v4/src/ctrl.sv new file mode 100644 index 0000000..dbc81a3 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/ctrl.sv @@ -0,0 +1,406 @@ +//Format of waveform interface: +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// | 159 .. 149 | 148 | 147 | 146 | 145 .. 144 | 143 .. 128 | 127 .. 112 | 111 .. 96 | 95 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// | xxxx | phrst | stdysel | mode | outsel | nsamp | xxxx | gain | xxxx | addr | phase | freq | +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// freq : 32 bits +// phase : 32 bits +// addr : 16 bits +// gain : 16 bits +// nsamp : 16 bits +// outsel : 2 bits +// mode : 1 bit +// stdysel : 1 bit +// phrst : 1 bit +module ctrl ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // dds control. + dds_ctrl_o , + + // memory control. + mem_addr_o , + + // gain. + gain_o , + + // Output source selection. + src_o , + + // Steady value selection. + stdy_o , + + // Output enable. + en_o ); + +// Memory address size. +parameter N = 16; + +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 16; + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [159:0] fifo_dout_i; +output [N_DDS*72-1:0] dds_ctrl_o; +output [N-1:0] mem_addr_o; +output [15:0] gain_o; +output [1:0] src_o; +output stdy_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// Fifo dout register. +reg [159:0] fifo_dout_r; + +// Non-stop counter for time calculation (adds N_DDS samples each clock tick). +reg [31:0] cnt_n; +reg [31:0] cnt_n_reg; + +// Pinc/phase. +wire [31:0] pinc_int; +reg [31:0] pinc_r1; +wire [31:0] pinc_N; +reg [31:0] pinc_N_r1; +reg [31:0] pinc_N_r2; +reg [31:0] pinc_N_r3; +wire [31:0] pinc_Nm; +reg [31:0] pinc_Nm_r1; + +wire [31:0] phase_int; +reg [31:0] phase_r1; +reg [31:0] phase_r2; +wire [31:0] phase_0; +reg [31:0] phase_0_r1; + +// Phase vectors. +wire [31:0] phase_v0 [0:N_DDS-1]; +reg [31:0] phase_v0_r1 [0:N_DDS-1]; +reg [31:0] phase_v0_r2 [0:N_DDS-1]; +wire [31:0] phase_v1 [0:N_DDS-1]; +reg [31:0] phase_v1_r1 [0:N_DDS-1]; + +// sync. +reg sync_reg; +reg sync_reg_r1; +reg sync_reg_r2; +reg sync_reg_r3; +reg sync_reg_r4; + +// Address. +wire [15:0] addr_int; +reg [15:0] addr_cnt; +reg [15:0] addr_cnt_r1; +reg [15:0] addr_cnt_r2; +reg [15:0] addr_cnt_r3; + +// Gain. +wire [15:0] gain_int; +reg [15:0] gain_r1; +reg [15:0] gain_r2; +reg [15:0] gain_r3; +reg [15:0] gain_r4; + +// Number of samples. +wire [15:0] nsamp_int; + +// Output selection. +wire [1:0] outsel_int; +reg [1:0] outsel_r1; +reg [1:0] outsel_r2; +reg [1:0] outsel_r3; +reg [1:0] outsel_r4; + +// Mode. +wire mode_int; + +// Steady value selection. +wire stdysel_int; +reg stdysel_r1; +reg stdysel_r2; +reg stdysel_r3; +reg stdysel_r4; + +// Load enable flag. +wire load_int; +reg load_r; + +// Fifo Read Enable. +reg rd_en_int; +reg rd_en_r1; +reg rd_en_r2; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +reg en_reg_r1; +reg en_reg_r2; +reg en_reg_r3; +reg en_reg_r4; +reg en_reg_r5; + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Non-stop counter for time calculation. + cnt_n <= 0; + cnt_n_reg <= 0; + + // Pinc/phase/sync. + pinc_r1 <= 0; + pinc_N_r1 <= 0; + pinc_N_r2 <= 0; + pinc_N_r3 <= 0; + pinc_Nm_r1 <= 0; + + phase_r1 <= 0; + phase_r2 <= 0; + phase_0_r1 <= 0; + + sync_reg <= 0; + sync_reg_r1 <= 0; + sync_reg_r2 <= 0; + sync_reg_r3 <= 0; + sync_reg_r4 <= 0; + + // Address. + addr_cnt <= 0; + addr_cnt_r1 <= 0; + addr_cnt_r2 <= 0; + addr_cnt_r3 <= 0; + + // Gain. + gain_r1 <= 0; + gain_r2 <= 0; + gain_r3 <= 0; + gain_r4 <= 0; + + // Output selection. + outsel_r1 <= 0; + outsel_r2 <= 0; + outsel_r3 <= 0; + outsel_r4 <= 0; + + // Steady value selection. + stdysel_r1 <= 0; + stdysel_r2 <= 0; + stdysel_r3 <= 0; + stdysel_r4 <= 0; + + // Load enable flag. + load_r <= 0; + + // Fifo Read Enable. + rd_en_r1 <= 0; + rd_en_r2 <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + en_reg_r1 <= 0; + en_reg_r2 <= 0; + en_reg_r3 <= 0; + en_reg_r4 <= 0; + en_reg_r5 <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (mode_int || ~fifo_empty_i) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Non-stop counter for time calculation. + cnt_n <= cnt_n + N_DDS; + if (sync_reg) + cnt_n_reg <= cnt_n; + + // Pinc/phase/sync. + pinc_r1 <= pinc_int; + pinc_N_r1 <= pinc_N; + pinc_N_r2 <= pinc_N_r1; + pinc_N_r3 <= pinc_N_r2; + pinc_Nm_r1 <= pinc_Nm; + + phase_r1 <= phase_int; + phase_r2 <= phase_r1; + phase_0_r1 <= phase_0; + + sync_reg <= load_r; + sync_reg_r1 <= sync_reg; + sync_reg_r2 <= sync_reg_r1; + sync_reg_r3 <= sync_reg_r2; + sync_reg_r4 <= sync_reg_r3; + + // Address. + if (rd_en_r2) + addr_cnt <= addr_int; + else + addr_cnt <= addr_cnt + 1; + + addr_cnt_r1 <= addr_cnt; + addr_cnt_r2 <= addr_cnt_r1; + addr_cnt_r3 <= addr_cnt_r2; + + // Gain. + gain_r1 <= gain_int; + gain_r2 <= gain_r1; + gain_r3 <= gain_r2; + gain_r4 <= gain_r3; + + // Output selection. + outsel_r1 <= outsel_int; + outsel_r2 <= outsel_r1; + outsel_r3 <= outsel_r2; + outsel_r4 <= outsel_r3; + + // Steady value selection. + stdysel_r1 <= stdysel_int; + stdysel_r2 <= stdysel_r1; + stdysel_r3 <= stdysel_r2; + stdysel_r4 <= stdysel_r3; + + // Load enable flag. + load_r <= load_int; + + // Fifo Read Enable. + rd_en_r1 <= rd_en_int; + rd_en_r2 <= rd_en_r1; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (~mode_int && rd_en_int) + if (~fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + + en_reg_r1 <= en_reg; + en_reg_r2 <= en_reg_r1; + en_reg_r3 <= en_reg_r2; + en_reg_r4 <= en_reg_r3; + en_reg_r5 <= en_reg_r4; + + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign pinc_int = fifo_dout_r[31:0]; +assign phase_int = fifo_dout_r[63:32]; +assign addr_int = fifo_dout_r[79:64]; +assign gain_int = fifo_dout_r[111:96]; +assign nsamp_int = fifo_dout_r[143:128]; +assign outsel_int = fifo_dout_r[145:144]; +assign mode_int = fifo_dout_r[146]; +assign stdysel_int = fifo_dout_r[147]; + +// Frequency calculation. +assign pinc_N = pinc_r1*N_DDS; + +// Phase calculation. +assign pinc_Nm = pinc_r1*cnt_n_reg; +assign phase_0 = pinc_Nm_r1 + phase_r2; + +// Phase vectors. +generate +genvar i; + for (i=0; i < N_DDS; i = i + 1) begin : GEN_phase + // Registers. + always @(posedge clk) begin + if (~rstn) begin + // v0. + phase_v0_r1[i] <= 0; + phase_v0_r2[i] <= 0; + + // v1. + phase_v1_r1[i] <= 0; + end + else begin + // v0. + phase_v0_r1[i] <= phase_v0[i]; + phase_v0_r2[i] <= phase_v0_r1[i]; + + // v1. + phase_v1_r1[i] <= phase_v1[i]; + end + end + + // v0. + assign phase_v0[i] = pinc_r1*i; + + // v1. + assign phase_v1[i] = phase_v0_r2[i] + phase_0_r1; + + // dds_ctrl_o output. + assign dds_ctrl_o[i*72 +: 72] = {7'h00,sync_reg_r4,phase_v1_r1[i],pinc_N_r3}; + end +endgenerate + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mem_addr_o = addr_cnt_r3; +assign gain_o = gain_r4; +assign src_o = outsel_r4; +assign stdy_o = stdysel_r4; +assign en_o = en_reg_r5; + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v4/src/data_writer.vhd b/firmware/ip/axis_signal_gen_v4/src/data_writer.vhd new file mode 100644 index 0000000..cbf1912 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/data_writer.vhd @@ -0,0 +1,226 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity data_writer is + Generic + ( + -- Number of tables. + NT : Integer := 16; + -- Address map of each table. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in STD_LOGIC; + clk : in STD_LOGIC; + + -- AXI Stream I/F. + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- Memory I/F. + mem_en : out std_logic_vector (NT-1 downto 0); + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_di : out std_logic_vector (B-1 downto 0); + + -- Registers. + START_ADDR_REG : in std_logic_vector (31 downto 0); + WE_REG : in std_logic + ); +end data_writer; + +architecture rtl of data_writer is + +-- Log2 of number of tables. +constant NT_LOG2 : Integer := Integer(ceil(log2(real(NT)))); + +-- Synchronizer. +component synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end component; + +-- State machine. +type fsm_state is ( INIT_ST , + READ_START_ADDR_ST , + WAIT_TVALID_ST , + RW_TDATA_ST ); +signal state : fsm_state; + +signal read_start_addr_state : std_logic; +signal rw_tdata_state : std_logic; + +-- WE_REG_resync. +signal WE_REG_resync : std_logic; + +-- Axis registers. +signal tready_i : std_logic; +signal tready_r : std_logic; +signal tdata_r : std_logic_vector(B-1 downto 0); +signal tdata_rr : std_logic_vector(B-1 downto 0); +signal tdata_rrr : std_logic_vector(B-1 downto 0); +signal tvalid_r : std_logic; +signal tvalid_rr : std_logic; +signal tvalid_rrr : std_logic; + +-- Memory Enable. +signal mem_en_i : std_logic_vector (NT-1 downto 0); +signal mem_en_r : std_logic_vector (NT-1 downto 0); + +-- Memory address space. +signal mem_addr_full : unsigned (NT_LOG2+N-1 downto 0); +signal mem_addr_low : unsigned (NT_LOG2-1 downto 0); +signal mem_addr_high : unsigned (N-1 downto 0); +signal mem_addr_high_r : unsigned (N-1 downto 0); + +begin + +-- WE_REG_resync +WE_REG_resync_i : synchronizer_n + generic map ( + N => 2 + ) + port map ( + rstn => rstn , + clk => clk , + data_in => WE_REG , + data_out => WE_REG_resync + ); + +-- Enable logic generation. +GEN: for I in 0 to NT-1 generate + + mem_en_i(I) <= '1' when mem_addr_low = to_unsigned(I,mem_addr_low'length) else + '0'; + +end generate GEN; + +process (clk) +begin + if ( rising_edge(clk) ) then + if (rstn = '0') then + -- Axis registers. + tready_r <= '0'; + tdata_r <= (others => '0'); + tdata_rr <= (others => '0'); + tdata_rrr <= (others => '0'); + tvalid_r <= '0'; + tvalid_rr <= '0'; + tvalid_rrr <= '0'; + + -- Memory address. + mem_addr_full <= (others => '0'); + mem_addr_high_r <= (others => '0'); + mem_en_r <= (others => '0'); + + else + -- Axis registers. + tready_r <= tready_i; + tdata_r <= s_axis_tdata; + tvalid_r <= s_axis_tvalid; + + -- Extra registers to account pipe of state machine. + tdata_rr <= tdata_r; + tdata_rrr <= tdata_rr; + tvalid_rr <= tvalid_r; + tvalid_rrr <= tvalid_rr; + + -- Memory address. + if ( read_start_addr_state = '1') then + mem_addr_full <= to_unsigned(to_integer(unsigned(START_ADDR_REG)),mem_addr_full'length); + elsif ( rw_tdata_state = '1' ) then + mem_addr_full <= mem_addr_full + 1; + end if; + mem_addr_high_r <= mem_addr_high; + mem_en_r <= mem_en_i; + + end if; + end if; +end process; + +-- Address computation. +mem_addr_low <= mem_addr_full(NT_LOG2-1 downto 0); +mem_addr_high <= mem_addr_full(NT_LOG2+N-1 downto NT_LOG2); + +-- Finite state machine. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + state <= INIT_ST; + else + case state is + when INIT_ST => + if ( WE_REG_resync = '1' ) then + state <= READ_START_ADDR_ST; + end if; + + when READ_START_ADDR_ST => + state <= WAIT_TVALID_ST; + + when WAIT_TVALID_ST => + if ( WE_REG_resync = '1') then + if ( tvalid_r = '0' ) then + state <= WAIT_TVALID_ST; + else + state <= RW_TDATA_ST; + end if; + else + state <= INIT_ST; + end if; + + when RW_TDATA_ST => + if ( tvalid_r = '0' ) then + state <= WAIT_TVALID_ST; + end if; + + end case; + end if; + end if; +end process; + +-- Output logic. +process (state) +begin +read_start_addr_state <= '0'; +rw_tdata_state <= '0'; +tready_i <= '0'; + case state is + when INIT_ST => + + when READ_START_ADDR_ST => + read_start_addr_state <= '1'; + + when WAIT_TVALID_ST => + tready_i <= '1'; + + when RW_TDATA_ST => + rw_tdata_state <= '1'; + tready_i <= '1'; + + end case; +end process; + +-- Assign output. +s_axis_tready <= tready_r; + +mem_en <= mem_en_r; +mem_we <= tvalid_rrr; +mem_addr <= std_logic_vector(mem_addr_high_r); +mem_di <= tdata_rrr; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.veo b/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.veo new file mode 100644 index 0000000..894ecd6 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.veo @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:dds_compiler:6.0 +// IP Revision: 18 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +dds_compiler_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [71 : 0] s_axis_phase_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file dds_compiler_0.v when simulating +// the core, dds_compiler_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.vho b/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.vho new file mode 100644 index 0000000..e65044c --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.vho @@ -0,0 +1,83 @@ +-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:dds_compiler:6.0 +-- IP Revision: 18 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT dds_compiler_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : dds_compiler_0 + PORT MAP ( + aclk => aclk, + s_axis_phase_tvalid => s_axis_phase_tvalid, + s_axis_phase_tdata => s_axis_phase_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file dds_compiler_0.vhd when simulating +-- the core, dds_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 0000000..47bc665 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,306 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_compiler_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 9 + 0 + 0 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 8 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 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xilinx_vhdlsynthesis_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + + xilinx_vhdlsynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + + xilinx_vhdlsynthesis_view_fileset + + + + GENtimestamp + Fri Jul 16 15:22:39 UTC 2021 + + + outputProductCRC + 9:c041be49 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:c041be49 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + dds_compiler_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Fri Jul 16 15:22:39 UTC 2021 + + + outputProductCRC + 9:c041be49 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + dds_compiler_v6_0_18 + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + GENtimestamp + Fri Jul 16 15:22:39 UTC 2021 + + + outputProductCRC + 9:0147f840 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + 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choice_list_950bd3bd + Auto + Area + Speed + + + choice_list_ba6ede68 + Standard + Rasterized + + + choice_list_cd7e1d82 + Coregen + Sysgen + + + choice_list_de3e80a0 + Fixed + Programmable + Streaming + + + choice_list_faa329ca + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + 21 + + + choice_pairs_0079eeec + Twos_Complement + Sign_and_Magnitude + + + choice_pairs_27d1d409 + Auto + Distributed_ROM + Block_ROM + + + choice_pairs_65a5252d + Full_Range + Unit_Circle + + + choice_pairs_6bdc34ae + System_Parameters + Hardware_Parameters + + + choice_pairs_75713637 + Packet_Framing + Not_Required + + + choice_pairs_8b9a47c2 + Auto + None + Phase_Dithering + Taylor_Series_Corrected + + + choice_pairs_944fe41d + Phase_Generator_and_SIN_COS_LUT + Phase_Generator_only + SIN_COS_LUT_only + + + choice_pairs_a54f933f + Sine + Cosine + Sine_and_Cosine + + + choice_pairs_d463c5cb + User_Field + Not_Required + + + choice_pairs_dac1efef + Not_Required + + + choice_pairs_f611af79 + On_Vector + On_Packet + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + dds_compiler_0.vho + vhdlTemplate + + + dds_compiler_0.veo + verilogTemplate + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + hdl/xbip_pipe_v3_0_vh_rfs.vhd + vhdlSource + xbip_pipe_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + hdl/xbip_bram18k_v3_0_vh_rfs.vhd + vhdlSource + xbip_bram18k_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + hdl/mult_gen_v12_0_vh_rfs.vhd + vhdlSource + mult_gen_v12_0_15 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd + vhdlSource + xbip_dsp48_wrapper_v3_0_4 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd + vhdlSource + xbip_dsp48_addsub_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd + vhdlSource + xbip_dsp48_multadd_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/dds_compiler_v6_0_vh_rfs.vhd + vhdlSource + dds_compiler_v6_0_18 + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/dds_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + hdl/xbip_pipe_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_pipe_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + hdl/xbip_bram18k_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_bram18k_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + hdl/mult_gen_v12_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + mult_gen_v12_0_15 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_wrapper_v3_0_4 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_addsub_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_multadd_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/dds_compiler_v6_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + dds_compiler_v6_0_18 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/dds_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_cmodelsimulation_view_fileset + + cmodel/dds_compiler_v6_0_bitacc_cmodel_lin64.zip + zip + + + cmodel/dds_compiler_v6_0_bitacc_cmodel_nt64.zip + zip + + + + xilinx_vhdltestbench_view_fileset + + demo_tb/tb_dds_compiler_0.vhd + vhdlSource + + + + xilinx_versioninformation_view_fileset + + doc/dds_compiler_v6_0_changelog.txt + text + + + + The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. + + + Component_Name + Component Name + dds_compiler_0 + + + PartsPresent + Configuration Options + Phase_Generator_and_SIN_COS_LUT + + + DDS_Clock_Rate + System Clock + 256 + + + Channels + Number of Channels + 1 + + + Mode_of_Operation + Mode Of Operation + Standard + + + Modulus + Modulus + 9 + + + Parameter_Entry + Parameter Selection + System_Parameters + + + Spurious_Free_Dynamic_Range + Spurious Free Dynamic Range + 96 + + + Frequency_Resolution + Frequency Resolution + 0.06 + + + Noise_Shaping + Noise Shaping + Auto + + + Phase_Width + Phase Width + 32 + + + Output_Width + Output Width + 16 + + + Phase_Increment + Phase Increment + Streaming + + + Resync + Resync + true + + + Phase_offset + Phase Offset + Streaming + + + Output_Selection + Output Selection + Sine_and_Cosine + + + Negative_Sine + Negative Sine + false + + + Negative_Cosine + Negative Cosine + false + + + Amplitude_Mode + Amplitude Mode + Full_Range + + + Memory_Type + Memory Type + Auto + + + Optimization_Goal + Optimization Goal + Speed + + + DSP48_Use + DSP48 Use + Maximal + + + Has_Phase_Out + Has Phase Out + false + + + DATA_Has_TLAST + DATA Has TLAST + Not_Required + + + Has_TREADY + Output TREADY + false + + + S_PHASE_Has_TUSER + Input + Not_Required + + + S_PHASE_TUSER_Width + User Field Width + 1 + + + M_DATA_Has_TUSER + DATA Output + Not_Required + + + M_PHASE_Has_TUSER + PHASE Output + Not_Required + + + S_CONFIG_Sync_Mode + Synchronization Mode + On_Vector + + + OUTPUT_FORM + Output Form + Twos_Complement + + + Latency_Configuration + Configurable + + + Latency + 8 + + + Has_ARESETn + ARESETn (active low) + false + + + Has_ACLKEN + ACLKEN + false + + + Output_Frequency1 + 0 + + + PINC1 + 0 + + + Phase_Offset_Angles1 + 0 + + + POFF1 + 0 + + + Output_Frequency2 + 0 + + + PINC2 + 0 + + + Phase_Offset_Angles2 + 0 + + + POFF2 + 0 + + + Output_Frequency3 + 0 + + + PINC3 + 0 + + + Phase_Offset_Angles3 + 0 + + + POFF3 + 0 + + + Output_Frequency4 + 0 + + + PINC4 + 0 + + + Phase_Offset_Angles4 + 0 + + + POFF4 + 0 + + + Output_Frequency5 + 0 + + + PINC5 + 0 + + + Phase_Offset_Angles5 + 0 + + + POFF5 + 0 + + + Output_Frequency6 + 0 + + + PINC6 + 0 + + + Phase_Offset_Angles6 + 0 + + + POFF6 + 0 + + + Output_Frequency7 + 0 + + + PINC7 + 0 + + + Phase_Offset_Angles7 + 0 + + + POFF7 + 0 + + + Output_Frequency8 + 0 + + + PINC8 + 0 + + + Phase_Offset_Angles8 + 0 + + + POFF8 + 0 + + + Output_Frequency9 + 0 + + + PINC9 + 0 + + + Phase_Offset_Angles9 + 0 + + + POFF9 + 0 + + + Output_Frequency10 + 0 + + + PINC10 + 0 + + + Phase_Offset_Angles10 + 0 + + + POFF10 + 0 + + + Output_Frequency11 + 0 + + + PINC11 + 0 + + + Phase_Offset_Angles11 + 0 + + + POFF11 + 0 + + + Output_Frequency12 + 0 + + + PINC12 + 0 + + + Phase_Offset_Angles12 + 0 + + + POFF12 + 0 + + + Output_Frequency13 + 0 + + + PINC13 + 0 + + + Phase_Offset_Angles13 + 0 + + + POFF13 + 0 + + + Output_Frequency14 + 0 + + + PINC14 + 0 + + + Phase_Offset_Angles14 + 0 + + + POFF14 + 0 + + + Output_Frequency15 + 0 + + + PINC15 + 0 + + + Phase_Offset_Angles15 + 0 + + + POFF15 + 0 + + + Output_Frequency16 + 0 + + + PINC16 + 0 + + + Phase_Offset_Angles16 + 0 + + + POFF16 + 0 + + + POR_mode + POR Mode + false + + + GUI_Behaviour + Coregen + + + explicit_period + false + + + period + 1 + + + + + DDS Compiler + 18 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.1 + + + + + + + + diff --git a/firmware/ip/axis_signal_gen_v4/src/dither.v b/firmware/ip/axis_signal_gen_v4/src/dither.v new file mode 100644 index 0000000..fabedf4 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/dither.v @@ -0,0 +1,80 @@ +module dither + #( + parameter N = 8, // Bits of input. + parameter M = 6, // Bits of output. + parameter SEED = 0 // Random Number Generator. + ) + ( + input rstn , + input clk , + input [N-1:0] din , + output [M-1:0] dout , + + // Registers. + input [N-1:0] RNDQ_REG + ); + +// Random number. +wire signed [N-1:0] rnd_int; +wire signed [N-1:0] rnd_q; +reg signed [N:0] rnd_r1; +reg signed [N:0] rnd_r2; +reg signed [N:0] rnd_r3; +reg signed [N:0] rnd_r4; + +// Signal + Noise. +wire signed [N:0] x; +wire signed [N:0] y; +wire signed [N:0] q; +reg signed [M-1:0] q_r; + +// Random Number Generator. +random_gen + #( + .W (N ), + .SEED (SEED ) + ) + random_gen_i + ( + .rstn (rstn ), + .clk (clk ), + .dout (rnd_int ) + ); + +// Noise (divide to lower amplitude). +assign rnd_q = rnd_int >>> RNDQ_REG; + +// Signal + Noise. +assign x = {din[N-1],din}; +assign y = x + rnd_r4; +assign q = y >>> (N+1-M); + +// Registes. +always @(posedge clk) begin + if (~rstn) begin + // Random number. + rnd_r1 <= 0; + rnd_r2 <= 0; + rnd_r3 <= 0; + rnd_r4 <= 0; + + // Signal + Noise. + q_r <= 0; + end + else begin + // Random number. + rnd_r1 <= {rnd_q[N-1],rnd_q}; + rnd_r2 <= rnd_r1; + rnd_r3 <= rnd_r2; + rnd_r4 <= rnd_r3; + + // Signal + Noise. + q_r <= q[0 +: M]; + end +end + +// Assign outputs. +assign dout = q_r; + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v4/src/fifo/bin2gray.vhd b/firmware/ip/axis_signal_gen_v4/src/fifo/bin2gray.vhd new file mode 100644 index 0000000..4ecc09b --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/fifo/bin2gray.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end bin2gray; + +architecture rtl of bin2gray is + +signal gray : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +gray(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + gray(I) <= din(I+1) xor din(I); +end generate; + +-- Assign output. +dout <= gray; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v4/src/fifo/bram_dp.vhd b/firmware/ip/axis_signal_gen_v4/src/fifo/bram_dp.vhd new file mode 100644 index 0000000..d57aad1 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/fifo/bram_dp.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture rtl of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v4/src/fifo/bram_simple_dp.vhd b/firmware/ip/axis_signal_gen_v4/src/fifo/bram_simple_dp.vhd new file mode 100644 index 0000000..1494332 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/fifo/bram_simple_dp.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_simple_dp; + +architecture rtl of bram_simple_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v4/src/fifo/fifo.vhd b/firmware/ip/axis_signal_gen_v4/src/fifo/fifo.vhd new file mode 100644 index 0000000..957362b --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/fifo/fifo.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture rtl of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Dual port, single clock BRAM. +component bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- FIFO memory. +mem_i : bram_simple_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_axi.vhd b/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_dc.vhd b/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v4/src/fifo/gray2bin.vhd b/firmware/ip/axis_signal_gen_v4/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v4/src/fifo/rd2axi.vhd b/firmware/ip/axis_signal_gen_v4/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v4/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_signal_gen_v4/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v4/src/random_gen.v b/firmware/ip/axis_signal_gen_v4/src/random_gen.v new file mode 100644 index 0000000..e67cd42 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/random_gen.v @@ -0,0 +1,137 @@ +module random_gen + #( + parameter W = 16 , + parameter SEED = 0 + ) + ( + input rstn , + input clk , + output [W-1 : 0] dout + ); + +reg [W-1 : 0] rand_out; +reg [W-1 : 0] rand_ff; + +reg [W-1 : 0] dout_r1; +reg [W-1 : 0] dout_r2; +reg [W-1 : 0] dout_r3; +reg [W-1 : 0] dout_r4; + +localparam seed_int = 24'b 0110_0011_0111_0110_1001_1101 + SEED; + +// LFSR. +always @(posedge clk) begin + if(rstn == 1'b 0) begin + rand_ff[W-1 :0] <= seed_int; // seed for pseudo random number sequencer + rand_out <= {W-1{1'b 0}}; + end + else begin + case (W) + 24 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[7] ^ rand_ff[2] ^ rand_ff[1] ^ rand_ff[0]) , rand_ff[W-1 : 1] }; // x^24 + x^23 + x^22 + x^17 + + rand_out <= rand_ff; + end + 23 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[5] ^ rand_ff[0] ) , rand_ff[W-1 : 1] }; // x^23+ x^18 + + rand_out <= rand_ff; + end + 22 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[1] ^ rand_ff[0] ) , rand_ff[W-1 : 1] }; // x^22+ x^21 + + rand_out <= rand_ff; + end + 21 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[2] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^21+ x^19 + + rand_out <= rand_ff; + end + 20 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[3] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^20+ x^17 + + rand_out <= rand_ff; + end + 19 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[15] ^ rand_ff[13] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^19 + x^5 + x^2 + 1 + rand_out <= rand_ff; + end + 18 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[7] ^ rand_ff[0] ) , rand_ff[W-1 : 1] }; // x^18 + x^11 + + rand_out <= rand_ff; + end + 17 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[3] ^ rand_ff[0] ) , rand_ff[W-1 : 1] }; // x^17 + x^14 + + rand_out <= rand_ff; + end + 16 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[5] ^ rand_ff[3] ^ rand_ff[2] ^ rand_ff[0]) , rand_ff[W-1 : 1] }; // x^16 + x^14 + x^13 + x^11 + + rand_out <= rand_ff; + end + 15 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[1] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^15 + x^14 + + rand_out <= rand_ff; + end + 14 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[12] ^ rand_ff[2] ^ rand_ff[1] ^ rand_ff[0]), rand_ff[W-1 : 1] }; // x^14 + x^13 + x^12 + x^2 + + rand_out <= rand_ff; + end + 13 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[5] ^ rand_ff[2] ^ rand_ff[1] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^13 + x^12 + x^11 + x^8 + + rand_out <= rand_ff; + end + 12 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[8] ^ rand_ff[2] ^ rand_ff[1] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^12 + x^11 + x^10 + x^4 + + rand_out <= rand_ff; + end + 11 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[1] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^11 + x^9 + + rand_out <= rand_ff; + end + 10 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[3] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^10 + x^7 + + rand_out <= rand_ff; + end + 9 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[4] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^9 + x^5 + + rand_out <= rand_ff; + end + 8 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[4] ^ rand_ff[3] ^ rand_ff[2] ^ rand_ff[0]), rand_ff[W-1 : 1] }; // x^8 + x^6 + x^5 + x^4 + + rand_out <= rand_ff; + end + 7 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[1] ^ rand_ff[0] ) , rand_ff[W-1 : 1] }; // x^7 + x^6 + + rand_out <= rand_ff; + end + 6 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[1] ^ rand_ff[0] ) , rand_ff[W-1 : 1] }; // x^6 + x^5 + + rand_out <= rand_ff; + end + 5 : begin + rand_ff[W-1 : 0] <= { ( rand_ff[2] ^ rand_ff[0] ), rand_ff[W-1 : 1] }; // x^5 + x^3 + + rand_out <= rand_ff; + end + default : begin + rand_ff[W-1 : 0] <= { (rand_ff[1] ^ rand_ff[0]) , rand_ff[W-1 : 0]}; // x^4 + x^3 + + rand_out <= rand_ff; + end + endcase + end +end + +// Output register. +always @(posedge clk) begin + if (rstn == 1'b0) begin + dout_r1 <= 0; + dout_r2 <= 0; + dout_r3 <= 0; + dout_r4 <= 0; + end + else begin + dout_r1 <= rand_out; + dout_r2 <= dout_r1; + dout_r3 <= dout_r2; + dout_r4 <= dout_r3; + end +end + +assign dout = dout_r4; + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v4/src/signal_gen.v b/firmware/ip/axis_signal_gen_v4/src/signal_gen.v new file mode 100644 index 0000000..6fc6f42 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/signal_gen.v @@ -0,0 +1,639 @@ +module signal_gen ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // Memory interface. + mem_addr_o , + mem_dout_real_i , + mem_dout_imag_i , + + // M_AXIS for output. + m_axis_tready_i , + m_axis_tvalid_o , + m_axis_tdata_o , + + // Registers. + RNDQ_REG , + OUTSEL_REG + ); + +/**************/ +/* Parameters */ +/**************/ +// Memory address size. +parameter N = 16; + +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 16; + +/*********/ +/* Ports */ +/*********/ +input rstn; +input clk; + +output fifo_rd_en_o; +input fifo_empty_i; +input [159:0] fifo_dout_i; + +output [N-1:0] mem_addr_o; +input [N_DDS*16-1:0] mem_dout_real_i; +input [N_DDS*16-1:0] mem_dout_imag_i; + +input m_axis_tready_i; +output m_axis_tvalid_o; +output [N_DDS*16-1:0] m_axis_tdata_o; + +input [31:0] RNDQ_REG; +input OUTSEL_REG; + +/********************/ +/* Internal signals */ +/********************/ +// Memory address. +wire [N-1:0] mem_addr_int; +reg [N-1:0] mem_addr_int_r; + +// DDS input control. +reg dds_tvalid_r; +wire [N_DDS*72-1:0] dds_ctrl_int; +reg [N_DDS*72-1:0] dds_ctrl_int_r; + +// DDS output. +wire [31:0] dds_dout [0:N_DDS-1]; +reg [31:0] dds_dout_r1 [0:N_DDS-1]; +reg [31:0] dds_dout_r2 [0:N_DDS-1]; +reg [31:0] dds_dout_r3 [0:N_DDS-1]; +reg [31:0] dds_dout_r4 [0:N_DDS-1]; +reg [31:0] dds_dout_r5 [0:N_DDS-1]; +reg [31:0] dds_dout_r6 [0:N_DDS-1]; + +// Memory data. +reg [15:0] mem_dout_real_r1 [0:N_DDS-1]; +reg [15:0] mem_dout_real_r2 [0:N_DDS-1]; +reg [15:0] mem_dout_real_r3 [0:N_DDS-1]; +reg [15:0] mem_dout_real_r4 [0:N_DDS-1]; +reg [15:0] mem_dout_real_r5 [0:N_DDS-1]; +reg [15:0] mem_dout_real_r6 [0:N_DDS-1]; +reg [15:0] mem_dout_real_r7 [0:N_DDS-1]; +reg [15:0] mem_dout_real_r8 [0:N_DDS-1]; +reg [15:0] mem_dout_real_r9 [0:N_DDS-1]; +reg signed [15:0] mem_dout_real_r10_a [0:N_DDS-1]; +reg [15:0] mem_dout_real_r10_b [0:N_DDS-1]; +reg [15:0] mem_dout_real_r11 [0:N_DDS-1]; +reg [15:0] mem_dout_real_r12 [0:N_DDS-1]; +reg [15:0] mem_dout_real_r13 [0:N_DDS-1]; +reg [15:0] mem_dout_imag_r1 [0:N_DDS-1]; +reg [15:0] mem_dout_imag_r2 [0:N_DDS-1]; +reg [15:0] mem_dout_imag_r3 [0:N_DDS-1]; +reg [15:0] mem_dout_imag_r4 [0:N_DDS-1]; +reg [15:0] mem_dout_imag_r5 [0:N_DDS-1]; +reg [15:0] mem_dout_imag_r6 [0:N_DDS-1]; +reg [15:0] mem_dout_imag_r7 [0:N_DDS-1]; +reg [15:0] mem_dout_imag_r8 [0:N_DDS-1]; +reg [15:0] mem_dout_imag_r9 [0:N_DDS-1]; +reg signed [15:0] mem_dout_imag_r10_a [0:N_DDS-1]; +reg [15:0] mem_dout_imag_r10_b [0:N_DDS-1]; +reg [15:0] mem_dout_imag_r11 [0:N_DDS-1]; +reg [15:0] mem_dout_imag_r12 [0:N_DDS-1]; +reg [15:0] mem_dout_imag_r13 [0:N_DDS-1]; + +// Product. +wire signed [15:0] prod_a_real [0:N_DDS-1]; +wire signed [15:0] prod_a_imag [0:N_DDS-1]; +wire signed [15:0] prod_b_real [0:N_DDS-1]; +wire signed [15:0] prod_b_imag [0:N_DDS-1]; +wire signed [31:0] prod_y_full_real_a [0:N_DDS-1]; +wire signed [31:0] prod_y_full_real_b [0:N_DDS-1]; +reg signed [31:0] prod_y_full_real_a_r[0:N_DDS-1]; +reg signed [31:0] prod_y_full_real_b_r[0:N_DDS-1]; +wire signed [31:0] prod_y_full_imag_a [0:N_DDS-1]; +wire signed [31:0] prod_y_full_imag_b [0:N_DDS-1]; +reg signed [31:0] prod_y_full_imag_a_r[0:N_DDS-1]; +reg signed [31:0] prod_y_full_imag_b_r[0:N_DDS-1]; +wire signed [31:0] prod_y_full_real [0:N_DDS-1]; +wire signed [31:0] prod_y_full_imag [0:N_DDS-1]; +wire [15:0] prod_y_real [0:N_DDS-1]; +wire [15:0] prod_y_imag [0:N_DDS-1]; +wire [31:0] prod_y [0:N_DDS-1]; +reg [31:0] prod_y_r1 [0:N_DDS-1]; +reg [31:0] prod_y_r2 [0:N_DDS-1]; + +// Muxed output. +wire [31:0] dout_mux [0:N_DDS-1]; +reg [31:0] dout_mux_r1 [0:N_DDS-1]; +reg [31:0] dout_mux_r2 [0:N_DDS-1]; + +// Product with Gain. +wire [15:0] gain_int; +reg [15:0] gain_int_r1; +reg [15:0] gain_int_r2; +reg [15:0] gain_int_r3; +reg [15:0] gain_int_r4; +reg [15:0] gain_int_r5; +reg [15:0] gain_int_r6; +reg [15:0] gain_int_r7; +reg [15:0] gain_int_r8; +reg [15:0] gain_int_r9; +reg [15:0] gain_int_r10; +reg [15:0] gain_int_r11; +reg [15:0] gain_int_r12; +reg [15:0] gain_int_r13; +reg [15:0] gain_int_r14; +reg [15:0] gain_int_r15; +reg [15:0] gain_int_r16; +reg signed [15:0] gain_int_r17; +wire signed [15:0] prodg_a_real [0:N_DDS-1]; +wire signed [15:0] prodg_a_imag [0:N_DDS-1]; +wire signed [31:0] prodg_y_full_real [0:N_DDS-1]; +wire signed [31:0] prodg_y_full_imag [0:N_DDS-1]; +reg [31:0] prodg_y_full_real_r [0:N_DDS-1]; +reg [31:0] prodg_y_full_imag_r [0:N_DDS-1]; +reg [15:0] round_r_real [0:N_DDS-1]; +reg [15:0] round_r_imag [0:N_DDS-1]; + +// Mux for real/imaginary part selection. +wire [15:0] round_r_mux [0:N_DDS-1]; + +// Output source selection. +wire [1:0] src_int; +reg [1:0] src_int_r1; +reg [1:0] src_int_r2; +reg [1:0] src_int_r3; +reg [1:0] src_int_r4; +reg [1:0] src_int_r5; +reg [1:0] src_int_r6; +reg [1:0] src_int_r7; +reg [1:0] src_int_r8; +reg [1:0] src_int_r9; +reg [1:0] src_int_r10; +reg [1:0] src_int_r11; +reg [1:0] src_int_r12; +reg [1:0] src_int_r13; +reg [1:0] src_int_r14; +reg [1:0] src_int_r15; + +// Steady value selection. +wire stdy_int; +reg stdy_int_r1; +reg stdy_int_r2; +reg stdy_int_r3; +reg stdy_int_r4; +reg stdy_int_r5; +reg stdy_int_r6; +reg stdy_int_r7; +reg stdy_int_r8; +reg stdy_int_r9; +reg stdy_int_r10; +reg stdy_int_r11; +reg stdy_int_r12; +reg stdy_int_r13; +reg stdy_int_r14; +reg stdy_int_r15; +reg stdy_int_r16; +reg stdy_int_r17; +reg stdy_int_r18; +reg stdy_int_r19; + +// Output enable. +wire en_int; +reg en_int_r1; +reg en_int_r2; +reg en_int_r3; +reg en_int_r4; +reg en_int_r5; +reg en_int_r6; +reg en_int_r7; +reg en_int_r8; +reg en_int_r9; +reg en_int_r10; +reg en_int_r11; +reg en_int_r12; +reg en_int_r13; +reg en_int_r14; +reg en_int_r15; +reg en_int_r16; +reg en_int_r17; +reg en_int_r18; +reg en_int_r19; + +// Output selection mux. +wire outmux_sel; + +/**********************/ +/* Begin Architecture */ +/**********************/ +// Control block. +ctrl + #( + .N (N ), + .N_DDS (N_DDS ) + ) + ctrl_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Fifo interface. + .fifo_rd_en_o (fifo_rd_en_o ), + .fifo_empty_i (fifo_empty_i ), + .fifo_dout_i (fifo_dout_i ), + + // dds control. + .dds_ctrl_o (dds_ctrl_int ), + + // memory control. + .mem_addr_o (mem_addr_int ), + + // gain. + .gain_o (gain_int ), + + // Output source selection. + .src_o (src_int ), + + // Steady value selection. + .stdy_o (stdy_int ), + + // Output enable. + .en_o (en_int ) + ); + + + +generate +genvar i; + for (i=0; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v4/src/tb/gauss.txt b/firmware/ip/axis_signal_gen_v4/src/tb/gauss.txt new file mode 100644 index 0000000..68d9265 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/tb/gauss.txt @@ -0,0 +1,512 @@ +57,0 +60,0 +62,0 +65,0 +68,0 +71,0 +74,0 +77,0 +80,0 +83,0 +87,0 +90,0 +94,0 +98,0 +102,0 +106,0 +110,0 +115,0 +119,0 +124,0 +129,0 +134,0 +140,0 +145,0 +151,0 +157,0 +163,0 +169,0 +176,0 +182,0 +189,0 +197,0 +204,0 +212,0 +220,0 +228,0 +237,0 +246,0 +255,0 +264,0 +274,0 +284,0 +294,0 +305,0 +316,0 +328,0 +339,0 +352,0 +364,0 +377,0 +390,0 +404,0 +418,0 +433,0 +448,0 +464,0 +480,0 +496,0 +513,0 +531,0 +549,0 +568,0 +587,0 +606,0 +627,0 +647,0 +669,0 +691,0 +714,0 +737,0 +761,0 +786,0 +811,0 +837,0 +864,0 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+import numpy as np +import matplotlib.pyplot as plt + +def gauss(mu=0, si=0, length=100, maxv=30000): + x = np.arange(0,length) + y = 1/(2*np.pi*si**2)*np.exp(-(x-mu)**2/si**2) + y = y/np.max(y)*maxv + return y + +yq = gauss(mu=300, si=120, length=512) +yi = np.zeros(len(yq)) + +yi = yi.astype(np.int16) +yq = yq.astype(np.int16) + +for ii in range(len(yi)): + print("%d,%d" %(yq[ii],yi[ii])) + diff --git a/firmware/ip/axis_signal_gen_v4/src/tb/gen_ramp.py b/firmware/ip/axis_signal_gen_v4/src/tb/gen_ramp.py new file mode 100644 index 0000000..71d11e7 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/tb/gen_ramp.py @@ -0,0 +1,19 @@ +import numpy as np +import matplotlib.pyplot as plt + +def triang(length=100, maxv=30000): + y1 = np.arange(0,length/2) + y2 = np.flip(y1,0) + y = np.concatenate((y1,y2)) + y = y/np.max(y)*maxv + return y + +yq = triang(length=512) +yi = yq + +yi = yi.astype(np.int16) +yq = yq.astype(np.int16) + +for ii in range(len(yi)): + print("%d,%d" %(yq[ii],yi[ii])) + diff --git a/firmware/ip/axis_signal_gen_v4/src/tb/ramp.txt b/firmware/ip/axis_signal_gen_v4/src/tb/ramp.txt new file mode 100644 index 0000000..32bfe92 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/tb/ramp.txt @@ -0,0 +1,512 @@ +0,0 +117,117 +235,235 +352,352 +470,470 +588,588 +705,705 +823,823 +941,941 +1058,1058 +1176,1176 +1294,1294 +1411,1411 +1529,1529 +1647,1647 +1764,1764 +1882,1882 +2000,2000 +2117,2117 +2235,2235 +2352,2352 +2470,2470 +2588,2588 +2705,2705 +2823,2823 +2941,2941 +3058,3058 +3176,3176 +3294,3294 +3411,3411 +3529,3529 +3647,3647 +3764,3764 +3882,3882 +4000,4000 +4117,4117 +4235,4235 +4352,4352 +4470,4470 +4588,4588 +4705,4705 +4823,4823 +4941,4941 +5058,5058 +5176,5176 +5294,5294 +5411,5411 +5529,5529 +5647,5647 +5764,5764 +5882,5882 +6000,6000 +6117,6117 +6235,6235 +6352,6352 +6470,6470 +6588,6588 +6705,6705 +6823,6823 +6941,6941 +7058,7058 +7176,7176 +7294,7294 +7411,7411 +7529,7529 +7647,7647 +7764,7764 +7882,7882 +8000,8000 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+5882,5882 +5764,5764 +5647,5647 +5529,5529 +5411,5411 +5294,5294 +5176,5176 +5058,5058 +4941,4941 +4823,4823 +4705,4705 +4588,4588 +4470,4470 +4352,4352 +4235,4235 +4117,4117 +4000,4000 +3882,3882 +3764,3764 +3647,3647 +3529,3529 +3411,3411 +3294,3294 +3176,3176 +3058,3058 +2941,2941 +2823,2823 +2705,2705 +2588,2588 +2470,2470 +2352,2352 +2235,2235 +2117,2117 +2000,2000 +1882,1882 +1764,1764 +1647,1647 +1529,1529 +1411,1411 +1294,1294 +1176,1176 +1058,1058 +941,941 +823,823 +705,705 +588,588 +470,470 +352,352 +235,235 +117,117 +0,0 diff --git a/firmware/ip/axis_signal_gen_v4/src/tb/tb.sv b/firmware/ip/axis_signal_gen_v4/src/tb/tb.sv new file mode 100644 index 0000000..da66249 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v4/src/tb/tb.sv @@ -0,0 +1,412 @@ +// VIP: axi_mst_0 +// DUT: axis_signal_gen_v2 +// IF: s_axi -> axi_mst_0 + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter N = 10; +parameter N_DDS = 16; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +// s0_axis interfase. +reg s0_axis_aclk; +reg s0_axis_aresetn; +reg [31:0] s0_axis_tdata; +wire s0_axis_tready; +reg s0_axis_tvalid; + +reg aresetn; +reg aclk; + +// s1_axis interfase. +reg [159:0] s1_axis_tdata; +wire s1_axis_tready; +reg s1_axis_tvalid; + +// m_axis interfase. +wire [N_DDS*16-1:0] m_axis_tdata; +reg m_axis_tready = 1; +wire m_axis_tvalid; + +// Waveform Fields. +reg [31:0] freq_r; +reg [31:0] phase_r; +reg [15:0] addr_r; +reg [15:0] gain_r; +reg [15:0] nsamp_r; +reg [1:0] outsel_r; +reg mode_r; +reg stdysel_r; +reg phrst_r; + +// Assignment of data out for debugging. +wire [15:0] dout_ii [0:N_DDS-1]; + +// AXI VIP master address. +xil_axi_ulong addr_start_addr = 32'h40000000; // 0 +xil_axi_ulong addr_we = 32'h40000004; // 1 +xil_axi_ulong addr_rndq = 32'h40000008; // 2 +xil_axi_ulong addr_outsel = 32'h4000000c; // 3 + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Test bench control. +reg tb_load_mem = 0; +reg tb_load_mem_done = 0; +reg tb_load_wave = 0; +reg tb_load_wave_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m_axis_tdata[16*ii +: 16]; +end +endgenerate +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_signal_gen_v4 + # + ( + .N (N ), + .N_DDS (N_DDS ) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // AXIS Slave to load data into memory. + .s0_axis_aclk (s0_axis_aclk ), + .s0_axis_aresetn(s0_axis_aresetn), + .s0_axis_tdata (s0_axis_tdata ), + .s0_axis_tvalid (s0_axis_tvalid ), + .s0_axis_tready (s0_axis_tready ), + + // s1_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // AXIS Slave to queue waveforms. + .s1_axis_tdata (s1_axis_tdata ), + .s1_axis_tvalid (s1_axis_tvalid ), + .s1_axis_tready (s1_axis_tready ), + + // AXIS Master for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +assign s1_axis_tdata = {{10{1'b0}},phrst_r,stdysel_r,mode_r,outsel_r,nsamp_r,{16{1'b0}},gain_r,{16{1'b0}},addr_r,phase_r,freq_r}; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + s0_axis_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + s0_axis_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("############################"); + $display("### Load data into Table ###"); + $display("############################"); + $display("t = %0t", $time); + + /* + ADDR = 0 + */ + + // start_addr. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_start_addr, prot, data_wr, resp); + #10; + + // we. + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_we, prot, data_wr, resp); + #10; + + // Load Table. + tb_load_mem <= 1; + wait (tb_load_mem_done); + + #100; + + // we. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_we, prot, data_wr, resp); + #10; + + $display("############################"); + $display("### Output selection reg ###"); + $display("############################"); + $display("t = %0t", $time); + + /* + OUTSEL = 0 (real part). + */ + + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_outsel, prot, data_wr, resp); + #10; + + #1000; + + $display("#######################"); + $display("### Queue Waveforms ###"); + $display("#######################"); + $display("t = %0t", $time); + + // Queue waveforms and write output while queuing. + tb_load_wave <= 1; + tb_write_out <= 1; + wait (tb_load_wave_done); + + #3000; + + // Stop writing output data. + tb_write_out <= 0; + + #20000; + +end + +// Load data into memroy. +initial begin + int fd,vali,valq; + bit signed [15:0] ii,qq; + + s0_axis_tvalid <= 0; + s0_axis_tdata <= 0; + + wait (tb_load_mem); + + //fd = $fopen("../../../../../tb/gauss.txt","r"); + fd = $fopen("../../../../../tb/ramp.txt","r"); + + wait (s0_axis_tready); + + while($fscanf(fd,"%d,%d", valq,vali) == 2) begin + $display("I,Q: %d, %d", vali,valq); + ii = vali; + qq = valq; + @(posedge s0_axis_aclk); + s0_axis_tvalid <= 1; + s0_axis_tdata <= {qq,ii}; + end + + @(posedge s0_axis_aclk); + s0_axis_tvalid <= 0; + + $fclose(fd); + tb_load_mem_done <= 1; + +end + +// Load waveforms. +initial begin + s1_axis_tvalid <= 0; + freq_r <= 0; + phase_r <= 0; + addr_r <= 0; + gain_r <= 0; + nsamp_r <= 0; + outsel_r <= 0; + mode_r <= 0; + stdysel_r <= 0; + phrst_r <= 0; + + wait (tb_load_wave); + wait (s1_axis_tready); + + @(posedge aclk); + $display("t = %0t", $time); + s1_axis_tvalid <= 1; + freq_r <= freq_calc(100, N_DDS, 34); + phase_r <= 0; + addr_r <= 0; + gain_r <= 30000; + nsamp_r <= 128/N_DDS; + outsel_r <= 2; // 0: prod, 1: dds, 2: mem + mode_r <= 0; // 0: nsamp, 1: periodic + stdysel_r <= 1; // 0: last, 1: zero. + + @(posedge aclk); + s1_axis_tvalid <= 0; + + #200; + + @(posedge aclk); + $display("t = %0t", $time); + s1_axis_tvalid <= 1; + gain_r <= 10000; + nsamp_r <= 620/N_DDS; + + //@(posedge aclk); + //s1_axis_tvalid <= 0; + + //#10000; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //nsamp_r <= 920/N_DDS; + + @(posedge aclk); + s1_axis_tvalid <= 0; + tb_load_wave_done <= 1; +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d, imag_d; + + // Output file. + fd = $fopen("../../../../../tb/dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, idx, real, imag"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i + + user.org + user + axis_signal_gen_v5 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s0_axis + + + + + + + TDATA + + + s0_axis_tdata + + + + + TVALID + + + s0_axis_tvalid + + + + + TREADY + + + s0_axis_tready + + + + + + s1_axis + + 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xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 6b2d8ce5 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + e51fb623 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + 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/home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + /home/lstefana/v20.2/ip/axis_signal_gen_v5 + + + + 2020.2 + + + + + + + + + diff --git a/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 0000000..7cfbd51 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 8 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 0000000..a53be60 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 8 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..ac9cf04 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,200 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + zynquplusRFSOC + xilinx.com:zcu216:part0:2.0 + + xczu49dr + ffvf1760 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 0000000..fa530b1 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4760 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + ARSIZE + + + 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axi_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_8 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_8 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_8 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_8 + + + + xilinx_externalfiles_view_fileset + + axi_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axi_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axi_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 8 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + + + diff --git a/firmware/ip/axis_signal_gen_v5/src/axi_slv.vhd b/firmware/ip/axis_signal_gen_v5/src/axi_slv.vhd new file mode 100644 index 0000000..c60ea98 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/axi_slv.vhd @@ -0,0 +1,516 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + START_ADDR_REG : out std_logic_vector (31 downto 0); + WE_REG : out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + -- 0 : START_ADDR_REG : 32-bit. Start address to write into memory. + -- 1 : WE_REG : 1-bit. Enable write into memory. + + -- Output Registers. + START_ADDR_REG <= slv_reg0; + WE_REG <= slv_reg1(0); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/axis_signal_gen_v5.v b/firmware/ip/axis_signal_gen_v5/src/axis_signal_gen_v5.v new file mode 100644 index 0000000..240bff6 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/axis_signal_gen_v5.v @@ -0,0 +1,198 @@ +// Signal Generator V4. +// s_axi_aclk : clock for s_axi_* +// s0_axis_aclk : clock for s0_axis_* +// aclk : clock for s1_axis_* and m_axis_* +// +module axis_signal_gen_v5 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // AXIS Slave to load memory samples. + s0_axis_aclk , + s0_axis_aresetn , + s0_axis_tdata , + s0_axis_tvalid , + s0_axis_tready , + + // s1_* and m_* reset/clock. + aclk , + aresetn , + + // AXIS Slave to queue waveforms. + s1_axis_tdata , + s1_axis_tvalid , + s1_axis_tready , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +parameter N = 12; + +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 16; + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input s0_axis_aclk; +input s0_axis_aresetn; +input [31:0] s0_axis_tdata; +input s0_axis_tvalid; +output s0_axis_tready; + +input aresetn; +input aclk; + +input [159:0] s1_axis_tdata; +input s1_axis_tvalid; +output s1_axis_tready; + +input m_axis_tready; +output m_axis_tvalid; +output [N_DDS*16-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] START_ADDR_REG; +wire WE_REG; + + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG ), + .WE_REG (WE_REG ) + ); + +signal_gen_top + #( + .N (N ), + .N_DDS (N_DDS ) + ) + signal_gen_top_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // AXIS Slave to load memory samples. + .s0_axis_aresetn (s0_axis_aresetn ), + .s0_axis_aclk (s0_axis_aclk ), + .s0_axis_tdata_i (s0_axis_tdata ), + .s0_axis_tvalid_i (s0_axis_tvalid ), + .s0_axis_tready_o (s0_axis_tready ), + + // AXIS Slave to queue waveforms. + .s1_axis_tdata_i (s1_axis_tdata ), + .s1_axis_tvalid_i (s1_axis_tvalid ), + .s1_axis_tready_o (s1_axis_tready ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v5/src/bram.v b/firmware/ip/axis_signal_gen_v5/src/bram.v new file mode 100644 index 0000000..018317e --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/bram.v @@ -0,0 +1,33 @@ +module bram (clk,ena,wea,addra,dia,doa); + +// Memory address size. +parameter N = 16; +// Data width. +parameter B = 16; + +input clk; +input ena; +input wea; +input [N-1:0] addra; +input [B-1:0] dia; +output [B-1:0] doa; + +// Ram type. +reg [B-1:0] RAM [0:2**N-1]; +reg [B-1:0] doa; + +always @(posedge clk) +begin + if (ena) + begin + if (wea) begin + RAM[addra] <= dia; + end + else begin + doa <= RAM[addra]; + end + end +end + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v5/src/ctrl.sv b/firmware/ip/axis_signal_gen_v5/src/ctrl.sv new file mode 100644 index 0000000..7cc6a09 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/ctrl.sv @@ -0,0 +1,466 @@ +//Format of waveform interface: +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// | 159 .. 149 | 148 | 147 | 146 | 145 .. 144 | 143 .. 128 | 127 .. 112 | 111 .. 96 | 95 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// | xxxx | phrst | stdysel | mode | outsel | nsamp | xxxx | gain | xxxx | addr | phase | freq | +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// freq : 32 bits +// phase : 32 bits +// addr : 16 bits +// gain : 16 bits +// nsamp : 16 bits +// outsel : 2 bits +// mode : 1 bit +// stdysel : 1 bit +// phrst : 1 bit +module ctrl ( + // Reset and clock. + rstn , + clk , + + // Fifo interface. + fifo_rd_en_o , + fifo_empty_i , + fifo_dout_i , + + // dds control. + dds_ctrl_o , + + // memory control. + mem_addr_o , + + // gain. + gain_o , + + // Output source selection. + src_o , + + // Steady value selection. + stdy_o , + + // Output enable. + en_o ); + +// Memory address size. +parameter N = 16; + +// Number of parallel dds blocks. +parameter [31:0] N_DDS = 16; + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [159:0] fifo_dout_i; +output [N_DDS*72-1:0] dds_ctrl_o; +output [N-1:0] mem_addr_o; +output [15:0] gain_o; +output [1:0] src_o; +output stdy_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// Fifo dout register. +reg [159:0] fifo_dout_r; + +// Non-stop counter for time calculation (adds N_DDS samples each clock tick). +reg [15:0] cnt_n; +reg [15:0] cnt_n_reg; + +// Pinc/phase. +wire [31:0] pinc_int; +reg [31:0] pinc_r1; +wire [31:0] pinc_N; +reg [31:0] pinc_N_r1; +reg [31:0] pinc_N_r2; +reg [31:0] pinc_N_r3; +reg [31:0] pinc_N_r4; +reg [31:0] pinc_N_r5; +wire [31:0] pinc_Nm; +reg [31:0] pinc_Nm_r1; +reg [31:0] pinc_Nm_r2; +reg [31:0] pinc_Nm_r3; + +wire [31:0] phase_int; +reg [31:0] phase_r1; +reg [31:0] phase_r2; +reg [31:0] phase_r3; +reg [31:0] phase_r4; +wire [31:0] phase_0; +reg [31:0] phase_0_r1; + +// Phase vectors. +wire [31:0] phase_v0 [0:N_DDS-1]; +reg [31:0] phase_v0_r1 [0:N_DDS-1]; +reg [31:0] phase_v0_r2 [0:N_DDS-1]; +reg [31:0] phase_v0_r3 [0:N_DDS-1]; +reg [31:0] phase_v0_r4 [0:N_DDS-1]; +wire [31:0] phase_v1 [0:N_DDS-1]; +reg [31:0] phase_v1_r1 [0:N_DDS-1]; + +// sync. +reg sync_reg; +reg sync_reg_r1; +reg sync_reg_r2; +reg sync_reg_r3; +reg sync_reg_r4; +reg sync_reg_r5; +reg sync_reg_r6; + +// Address. +wire [15:0] addr_int; +reg [15:0] addr_cnt; +reg [15:0] addr_cnt_r1; +reg [15:0] addr_cnt_r2; +reg [15:0] addr_cnt_r3; +reg [15:0] addr_cnt_r4; +reg [15:0] addr_cnt_r5; + +// Gain. +wire [15:0] gain_int; +reg [15:0] gain_r1; +reg [15:0] gain_r2; +reg [15:0] gain_r3; +reg [15:0] gain_r4; +reg [15:0] gain_r5; +reg [15:0] gain_r6; + +// Number of samples. +wire [15:0] nsamp_int; + +// Output selection. +wire [1:0] outsel_int; +reg [1:0] outsel_r1; +reg [1:0] outsel_r2; +reg [1:0] outsel_r3; +reg [1:0] outsel_r4; +reg [1:0] outsel_r5; +reg [1:0] outsel_r6; + +// Mode. +wire mode_int; + +// Steady value selection. +wire stdysel_int; +reg stdysel_r1; +reg stdysel_r2; +reg stdysel_r3; +reg stdysel_r4; +reg stdysel_r5; +reg stdysel_r6; + +// Load enable flag. +wire load_int; +reg load_r; + +// Fifo Read Enable. +reg rd_en_int; +reg rd_en_r1; +reg rd_en_r2; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +reg en_reg_r1; +reg en_reg_r2; +reg en_reg_r3; +reg en_reg_r4; +reg en_reg_r5; +reg en_reg_r6; +reg en_reg_r7; + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Non-stop counter for time calculation. + cnt_n <= 0; + cnt_n_reg <= 0; + + // Pinc/phase/sync. + pinc_r1 <= 0; + pinc_N_r1 <= 0; + pinc_N_r2 <= 0; + pinc_N_r3 <= 0; + pinc_N_r4 <= 0; + pinc_N_r5 <= 0; + pinc_Nm_r1 <= 0; + pinc_Nm_r2 <= 0; + pinc_Nm_r3 <= 0; + + phase_r1 <= 0; + phase_r2 <= 0; + phase_r3 <= 0; + phase_r4 <= 0; + phase_0_r1 <= 0; + + sync_reg <= 0; + sync_reg_r1 <= 0; + sync_reg_r2 <= 0; + sync_reg_r3 <= 0; + sync_reg_r4 <= 0; + sync_reg_r5 <= 0; + sync_reg_r6 <= 0; + + // Address. + addr_cnt <= 0; + addr_cnt_r1 <= 0; + addr_cnt_r2 <= 0; + addr_cnt_r3 <= 0; + addr_cnt_r4 <= 0; + addr_cnt_r5 <= 0; + + // Gain. + gain_r1 <= 0; + gain_r2 <= 0; + gain_r3 <= 0; + gain_r4 <= 0; + gain_r5 <= 0; + gain_r6 <= 0; + + // Output selection. + outsel_r1 <= 0; + outsel_r2 <= 0; + outsel_r3 <= 0; + outsel_r4 <= 0; + outsel_r5 <= 0; + outsel_r6 <= 0; + + // Steady value selection. + stdysel_r1 <= 0; + stdysel_r2 <= 0; + stdysel_r3 <= 0; + stdysel_r4 <= 0; + stdysel_r5 <= 0; + stdysel_r6 <= 0; + + // Load enable flag. + load_r <= 0; + + // Fifo Read Enable. + rd_en_r1 <= 0; + rd_en_r2 <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + en_reg_r1 <= 0; + en_reg_r2 <= 0; + en_reg_r3 <= 0; + en_reg_r4 <= 0; + en_reg_r5 <= 0; + en_reg_r6 <= 0; + en_reg_r7 <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (mode_int || ~fifo_empty_i) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Non-stop counter for time calculation. + cnt_n <= cnt_n + N_DDS; + if (sync_reg) + cnt_n_reg <= cnt_n; + + // Pinc/phase/sync. + pinc_r1 <= pinc_int; + pinc_N_r1 <= pinc_N; + pinc_N_r2 <= pinc_N_r1; + pinc_N_r3 <= pinc_N_r2; + pinc_N_r4 <= pinc_N_r3; + pinc_N_r5 <= pinc_N_r4; + pinc_Nm_r1 <= pinc_Nm; + pinc_Nm_r2 <= pinc_Nm_r1; + pinc_Nm_r3 <= pinc_Nm_r2; + + phase_r1 <= phase_int; + phase_r2 <= phase_r1; + phase_r3 <= phase_r2; + phase_r4 <= phase_r3; + phase_0_r1 <= phase_0; + + sync_reg <= load_r; + sync_reg_r1 <= sync_reg; + sync_reg_r2 <= sync_reg_r1; + sync_reg_r3 <= sync_reg_r2; + sync_reg_r4 <= sync_reg_r3; + sync_reg_r5 <= sync_reg_r4; + sync_reg_r6 <= sync_reg_r5; + + // Address. + if (rd_en_r2) + addr_cnt <= addr_int; + else + addr_cnt <= addr_cnt + 1; + + addr_cnt_r1 <= addr_cnt; + addr_cnt_r2 <= addr_cnt_r1; + addr_cnt_r3 <= addr_cnt_r2; + addr_cnt_r4 <= addr_cnt_r3; + addr_cnt_r5 <= addr_cnt_r4; + + // Gain. + gain_r1 <= gain_int; + gain_r2 <= gain_r1; + gain_r3 <= gain_r2; + gain_r4 <= gain_r3; + gain_r5 <= gain_r4; + gain_r6 <= gain_r5; + + // Output selection. + outsel_r1 <= outsel_int; + outsel_r2 <= outsel_r1; + outsel_r3 <= outsel_r2; + outsel_r4 <= outsel_r3; + outsel_r5 <= outsel_r4; + outsel_r6 <= outsel_r5; + + // Steady value selection. + stdysel_r1 <= stdysel_int; + stdysel_r2 <= stdysel_r1; + stdysel_r3 <= stdysel_r2; + stdysel_r4 <= stdysel_r3; + stdysel_r5 <= stdysel_r3; + stdysel_r6 <= stdysel_r3; + + // Load enable flag. + load_r <= load_int; + + // Fifo Read Enable. + rd_en_r1 <= rd_en_int; + rd_en_r2 <= rd_en_r1; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (~mode_int && rd_en_int) + if (~fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + + en_reg_r1 <= en_reg; + en_reg_r2 <= en_reg_r1; + en_reg_r3 <= en_reg_r2; + en_reg_r4 <= en_reg_r3; + en_reg_r5 <= en_reg_r4; + en_reg_r6 <= en_reg_r5; + en_reg_r7 <= en_reg_r6; + + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign pinc_int = fifo_dout_r[31:0]; +assign phase_int = fifo_dout_r[63:32]; +assign addr_int = fifo_dout_r[79:64]; +assign gain_int = fifo_dout_r[111:96]; +assign nsamp_int = fifo_dout_r[143:128]; +assign outsel_int = fifo_dout_r[145:144]; +assign mode_int = fifo_dout_r[146]; +assign stdysel_int = fifo_dout_r[147]; + +// Frequency calculation. +assign pinc_N = pinc_r1*N_DDS; + +// Phase calculation. +assign pinc_Nm = pinc_r1*cnt_n_reg; +assign phase_0 = pinc_Nm_r3 + phase_r4; + +// Phase vectors. +generate +genvar i; + for (i=0; i < N_DDS; i = i + 1) begin : GEN_phase + // Registers. + always @(posedge clk) begin + if (~rstn) begin + // v0. + phase_v0_r1[i] <= 0; + phase_v0_r2[i] <= 0; + phase_v0_r3[i] <= 0; + phase_v0_r4[i] <= 0; + + // v1. + phase_v1_r1[i] <= 0; + end + else begin + // v0. + phase_v0_r1[i] <= phase_v0[i]; + phase_v0_r2[i] <= phase_v0_r1[i]; + phase_v0_r3[i] <= phase_v0_r2[i]; + phase_v0_r4[i] <= phase_v0_r3[i]; + + // v1. + phase_v1_r1[i] <= phase_v1[i]; + end + end + + // v0. + assign phase_v0[i] = pinc_r1*i; + + // v1. + assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; + + // dds_ctrl_o output. + assign dds_ctrl_o[i*72 +: 72] = {7'h00,sync_reg_r6,phase_v1_r1[i],pinc_N_r5}; + end +endgenerate + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mem_addr_o = addr_cnt_r5; +assign gain_o = gain_r6; +assign src_o = outsel_r6; +assign stdy_o = stdysel_r6; +assign en_o = en_reg_r7; + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v5/src/data_writer.vhd b/firmware/ip/axis_signal_gen_v5/src/data_writer.vhd new file mode 100644 index 0000000..cbf1912 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/data_writer.vhd @@ -0,0 +1,226 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity data_writer is + Generic + ( + -- Number of tables. + NT : Integer := 16; + -- Address map of each table. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in STD_LOGIC; + clk : in STD_LOGIC; + + -- AXI Stream I/F. + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- Memory I/F. + mem_en : out std_logic_vector (NT-1 downto 0); + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_di : out std_logic_vector (B-1 downto 0); + + -- Registers. + START_ADDR_REG : in std_logic_vector (31 downto 0); + WE_REG : in std_logic + ); +end data_writer; + +architecture rtl of data_writer is + +-- Log2 of number of tables. +constant NT_LOG2 : Integer := Integer(ceil(log2(real(NT)))); + +-- Synchronizer. +component synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end component; + +-- State machine. +type fsm_state is ( INIT_ST , + READ_START_ADDR_ST , + WAIT_TVALID_ST , + RW_TDATA_ST ); +signal state : fsm_state; + +signal read_start_addr_state : std_logic; +signal rw_tdata_state : std_logic; + +-- WE_REG_resync. +signal WE_REG_resync : std_logic; + +-- Axis registers. +signal tready_i : std_logic; +signal tready_r : std_logic; +signal tdata_r : std_logic_vector(B-1 downto 0); +signal tdata_rr : std_logic_vector(B-1 downto 0); +signal tdata_rrr : std_logic_vector(B-1 downto 0); +signal tvalid_r : std_logic; +signal tvalid_rr : std_logic; +signal tvalid_rrr : std_logic; + +-- Memory Enable. +signal mem_en_i : std_logic_vector (NT-1 downto 0); +signal mem_en_r : std_logic_vector (NT-1 downto 0); + +-- Memory address space. +signal mem_addr_full : unsigned (NT_LOG2+N-1 downto 0); +signal mem_addr_low : unsigned (NT_LOG2-1 downto 0); +signal mem_addr_high : unsigned (N-1 downto 0); +signal mem_addr_high_r : unsigned (N-1 downto 0); + +begin + +-- WE_REG_resync +WE_REG_resync_i : synchronizer_n + generic map ( + N => 2 + ) + port map ( + rstn => rstn , + clk => clk , + data_in => WE_REG , + data_out => WE_REG_resync + ); + +-- Enable logic generation. +GEN: for I in 0 to NT-1 generate + + mem_en_i(I) <= '1' when mem_addr_low = to_unsigned(I,mem_addr_low'length) else + '0'; + +end generate GEN; + +process (clk) +begin + if ( rising_edge(clk) ) then + if (rstn = '0') then + -- Axis registers. + tready_r <= '0'; + tdata_r <= (others => '0'); + tdata_rr <= (others => '0'); + tdata_rrr <= (others => '0'); + tvalid_r <= '0'; + tvalid_rr <= '0'; + tvalid_rrr <= '0'; + + -- Memory address. + mem_addr_full <= (others => '0'); + mem_addr_high_r <= (others => '0'); + mem_en_r <= (others => '0'); + + else + -- Axis registers. + tready_r <= tready_i; + tdata_r <= s_axis_tdata; + tvalid_r <= s_axis_tvalid; + + -- Extra registers to account pipe of state machine. + tdata_rr <= tdata_r; + tdata_rrr <= tdata_rr; + tvalid_rr <= tvalid_r; + tvalid_rrr <= tvalid_rr; + + -- Memory address. + if ( read_start_addr_state = '1') then + mem_addr_full <= to_unsigned(to_integer(unsigned(START_ADDR_REG)),mem_addr_full'length); + elsif ( rw_tdata_state = '1' ) then + mem_addr_full <= mem_addr_full + 1; + end if; + mem_addr_high_r <= mem_addr_high; + mem_en_r <= mem_en_i; + + end if; + end if; +end process; + +-- Address computation. +mem_addr_low <= mem_addr_full(NT_LOG2-1 downto 0); +mem_addr_high <= mem_addr_full(NT_LOG2+N-1 downto NT_LOG2); + +-- Finite state machine. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + state <= INIT_ST; + else + case state is + when INIT_ST => + if ( WE_REG_resync = '1' ) then + state <= READ_START_ADDR_ST; + end if; + + when READ_START_ADDR_ST => + state <= WAIT_TVALID_ST; + + when WAIT_TVALID_ST => + if ( WE_REG_resync = '1') then + if ( tvalid_r = '0' ) then + state <= WAIT_TVALID_ST; + else + state <= RW_TDATA_ST; + end if; + else + state <= INIT_ST; + end if; + + when RW_TDATA_ST => + if ( tvalid_r = '0' ) then + state <= WAIT_TVALID_ST; + end if; + + end case; + end if; + end if; +end process; + +-- Output logic. +process (state) +begin +read_start_addr_state <= '0'; +rw_tdata_state <= '0'; +tready_i <= '0'; + case state is + when INIT_ST => + + when READ_START_ADDR_ST => + read_start_addr_state <= '1'; + + when WAIT_TVALID_ST => + tready_i <= '1'; + + when RW_TDATA_ST => + rw_tdata_state <= '1'; + tready_i <= '1'; + + end case; +end process; + +-- Assign output. +s_axis_tready <= tready_r; + +mem_en <= mem_en_r; +mem_we <= tvalid_rrr; +mem_addr <= std_logic_vector(mem_addr_high_r); +mem_di <= tdata_rrr; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.veo b/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.veo new file mode 100644 index 0000000..894ecd6 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.veo @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:dds_compiler:6.0 +// IP Revision: 18 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +dds_compiler_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [71 : 0] s_axis_phase_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file dds_compiler_0.v when simulating +// the core, dds_compiler_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.vho b/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.vho new file mode 100644 index 0000000..e65044c --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.vho @@ -0,0 +1,83 @@ +-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:dds_compiler:6.0 +-- IP Revision: 18 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT dds_compiler_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : dds_compiler_0 + PORT MAP ( + aclk => aclk, + s_axis_phase_tvalid => s_axis_phase_tvalid, + s_axis_phase_tdata => s_axis_phase_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file dds_compiler_0.vhd when simulating +-- the core, dds_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 0000000..825c317 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,318 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dds_compiler_0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 9 + 0 + 0 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 10 + 1 + 0 + 9 + 0 + 32 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 2 + 0 + 16 + 14 + 3 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + 3 + 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+ + choice_pairs_a54f933f + Sine + Cosine + Sine_and_Cosine + + + choice_pairs_d463c5cb + User_Field + Not_Required + + + choice_pairs_dac1efef + Not_Required + + + choice_pairs_f611af79 + On_Vector + On_Packet + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + dds_compiler_0.vho + vhdlTemplate + + + dds_compiler_0.veo + verilogTemplate + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset + + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + hdl/xbip_pipe_v3_0_vh_rfs.vhd + vhdlSource + xbip_pipe_v3_0_6 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + hdl/xbip_bram18k_v3_0_vh_rfs.vhd + vhdlSource + xbip_bram18k_v3_0_6 + + + + + + + + + + + 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+ + hdl/xbip_utils_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_utils_v3_0_10 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_utils_2_0__ref_view_fileset + + hdl/axi_utils_v2_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_utils_v2_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset + + hdl/xbip_pipe_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_pipe_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset + + hdl/xbip_bram18k_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_bram18k_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + hdl/mult_gen_v12_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + mult_gen_v12_0_15 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_wrapper_3_0__ref_view_fileset + + hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_wrapper_v3_0_4 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_addsub_3_0__ref_view_fileset + + hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_addsub_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_xbip_dsp48_multadd_3_0__ref_view_fileset + + hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + xbip_dsp48_multadd_v3_0_6 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/dds_compiler_v6_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + dds_compiler_v6_0_18 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/dds_compiler_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_cmodelsimulation_view_fileset + + cmodel/dds_compiler_v6_0_bitacc_cmodel_lin64.zip + zip + + + cmodel/dds_compiler_v6_0_bitacc_cmodel_nt64.zip + zip + + + + xilinx_vhdltestbench_view_fileset + + demo_tb/tb_dds_compiler_0.vhd + vhdlSource + + + + xilinx_versioninformation_view_fileset + + doc/dds_compiler_v6_0_changelog.txt + text + + + + The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. + + + Component_Name + Component Name + dds_compiler_0 + + + PartsPresent + Configuration Options + Phase_Generator_and_SIN_COS_LUT + + + DDS_Clock_Rate + System Clock + 256 + + + Channels + Number of Channels + 1 + + + Mode_of_Operation + Mode Of Operation + Standard + + + Modulus + Modulus + 9 + + + Parameter_Entry + Parameter Selection + System_Parameters + + + Spurious_Free_Dynamic_Range + Spurious Free Dynamic Range + 96 + + + Frequency_Resolution + Frequency Resolution + 0.06 + + + Noise_Shaping + Noise Shaping + Auto + + + Phase_Width + Phase Width + 32 + + + Output_Width + Output Width + 16 + + + Phase_Increment + Phase Increment + Streaming + + + Resync + Resync + true + + + Phase_offset + Phase Offset + Streaming + + + Output_Selection + Output Selection + Sine_and_Cosine + + + Negative_Sine + Negative Sine + false + + + Negative_Cosine + Negative Cosine + false + + + Amplitude_Mode + Amplitude Mode + Full_Range + + + Memory_Type + Memory Type + Auto + + + Optimization_Goal + Optimization Goal + Speed + + + DSP48_Use + DSP48 Use + Maximal + + + Has_Phase_Out + Has Phase Out + false + + + DATA_Has_TLAST + DATA Has TLAST + Not_Required + + + Has_TREADY + Output TREADY + false + + + S_PHASE_Has_TUSER + Input + Not_Required + + + S_PHASE_TUSER_Width + User Field Width + 1 + + + M_DATA_Has_TUSER + DATA Output + Not_Required + + + M_PHASE_Has_TUSER + PHASE Output + Not_Required + + + S_CONFIG_Sync_Mode + Synchronization Mode + On_Vector + + + OUTPUT_FORM + Output Form + Twos_Complement + + + Latency_Configuration + Configurable + + + Latency + 2 + + + Has_ARESETn + ARESETn (active low) + false + + + Has_ACLKEN + ACLKEN + false + + + Output_Frequency1 + 0 + + + PINC1 + 0 + + + Phase_Offset_Angles1 + 0 + + + POFF1 + 0 + + + Output_Frequency2 + 0 + + + PINC2 + 0 + + + Phase_Offset_Angles2 + 0 + + + POFF2 + 0 + + + Output_Frequency3 + 0 + + + PINC3 + 0 + + + Phase_Offset_Angles3 + 0 + + + POFF3 + 0 + + + Output_Frequency4 + 0 + + + PINC4 + 0 + + + Phase_Offset_Angles4 + 0 + + + POFF4 + 0 + + + Output_Frequency5 + 0 + + + PINC5 + 0 + + + Phase_Offset_Angles5 + 0 + + + POFF5 + 0 + + + Output_Frequency6 + 0 + + + PINC6 + 0 + + + Phase_Offset_Angles6 + 0 + + + POFF6 + 0 + + + Output_Frequency7 + 0 + + + PINC7 + 0 + + + Phase_Offset_Angles7 + 0 + + + POFF7 + 0 + + + Output_Frequency8 + 0 + + + PINC8 + 0 + + + Phase_Offset_Angles8 + 0 + + + POFF8 + 0 + + + Output_Frequency9 + 0 + + + PINC9 + 0 + + + Phase_Offset_Angles9 + 0 + + + POFF9 + 0 + + + Output_Frequency10 + 0 + + + PINC10 + 0 + + + Phase_Offset_Angles10 + 0 + + + POFF10 + 0 + + + Output_Frequency11 + 0 + + + PINC11 + 0 + + + Phase_Offset_Angles11 + 0 + + + POFF11 + 0 + + + Output_Frequency12 + 0 + + + PINC12 + 0 + + + Phase_Offset_Angles12 + 0 + + + POFF12 + 0 + + + Output_Frequency13 + 0 + + + PINC13 + 0 + + + Phase_Offset_Angles13 + 0 + + + POFF13 + 0 + + + Output_Frequency14 + 0 + + + PINC14 + 0 + + + Phase_Offset_Angles14 + 0 + + + POFF14 + 0 + + + Output_Frequency15 + 0 + + + PINC15 + 0 + + + Phase_Offset_Angles15 + 0 + + + POFF15 + 0 + + + Output_Frequency16 + 0 + + + PINC16 + 0 + + + Phase_Offset_Angles16 + 0 + + + POFF16 + 0 + + + POR_mode + POR Mode + false + + + GUI_Behaviour + Coregen + + + explicit_period + false + + + period + 1 + + + + + DDS Compiler + 18 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.1 + + + + + + + + diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/bin2gray.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/bin2gray.vhd new file mode 100644 index 0000000..4ecc09b --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/bin2gray.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end bin2gray; + +architecture rtl of bin2gray is + +signal gray : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +gray(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + gray(I) <= din(I+1) xor din(I); +end generate; + +-- Assign output. +dout <= gray; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/bram_dp.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/bram_dp.vhd new file mode 100644 index 0000000..d57aad1 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/bram_dp.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture rtl of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/bram_simple_dp.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/bram_simple_dp.vhd new file mode 100644 index 0000000..1494332 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/bram_simple_dp.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_simple_dp; + +architecture rtl of bram_simple_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/fifo.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/fifo.vhd new file mode 100644 index 0000000..957362b --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/fifo.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture rtl of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Dual port, single clock BRAM. +component bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- FIFO memory. +mem_i : bram_simple_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_axi.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_dc.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/gray2bin.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/rd2axi.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_signal_gen_v5/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/latency_reg.v b/firmware/ip/axis_signal_gen_v5/src/latency_reg.v new file mode 100644 index 0000000..687a9f3 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v5/src/tb/dout.csv b/firmware/ip/axis_signal_gen_v5/src/tb/dout.csv new file mode 100644 index 0000000..0ecffa5 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/tb/dout.csv @@ -0,0 +1,20013 @@ +valid, idx, real, imag +0, 0, 0 +0, 1, 0 +0, 2, 0 +0, 3, 0 +0, 0, 0 +0, 1, 0 +0, 2, 0 +0, 3, 0 +0, 0, 0 +0, 1, 0 +0, 2, 0 +0, 3, 0 +0, 0, 0 +0, 1, 0 +0, 2, 0 +0, 3, 0 +0, 0, 0 +0, 1, 0 +0, 2, 0 +0, 3, 0 +0, 0, 0 +0, 1, 0 +0, 2, 0 +0, 3, 0 +0, 0, 0 +0, 1, 0 +0, 2, 0 +0, 3, 0 +0, 0, 0 +0, 1, 0 +0, 2, 0 +0, 3, 0 +0, 0, 0 +0, 1, 0 +0, 2, 0 +0, 3, 0 +0, 0, 0 +0, 1, 0 +0, 2, 0 +0, 3, 0 +0, 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index 0000000..88ba683 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/tb/gen_gauss.py @@ -0,0 +1,18 @@ +import numpy as np +import matplotlib.pyplot as plt + +def gauss(mu=0, si=0, length=100, maxv=30000): + x = np.arange(0,length) + y = 1/(2*np.pi*si**2)*np.exp(-(x-mu)**2/si**2) + y = y/np.max(y)*maxv + return y + +yq = gauss(mu=300, si=120, length=512) +yi = np.zeros(len(yq)) + +yi = yi.astype(np.int16) +yq = yq.astype(np.int16) + +for ii in range(len(yi)): + print("%d,%d" %(yq[ii],yi[ii])) + diff --git a/firmware/ip/axis_signal_gen_v5/src/tb/tb.sv b/firmware/ip/axis_signal_gen_v5/src/tb/tb.sv new file mode 100644 index 0000000..929571d --- /dev/null +++ b/firmware/ip/axis_signal_gen_v5/src/tb/tb.sv @@ -0,0 +1,427 @@ +// VIP: axi_mst_0 +// DUT: axis_signal_gen_v2 +// IF: s_axi -> axi_mst_0 + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter N = 10; +parameter N_DDS = 4; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +// s0_axis interfase. +reg s0_axis_aclk; +reg s0_axis_aresetn; +reg [31:0] s0_axis_tdata; +wire s0_axis_tready; +reg s0_axis_tvalid; + +reg aresetn; +reg aclk; + +// s1_axis interfase. +reg [159:0] s1_axis_tdata; +wire s1_axis_tready; +reg s1_axis_tvalid; + +// m_axis interfase. +wire [N_DDS*16-1:0] m_axis_tdata; +reg m_axis_tready = 1; +wire m_axis_tvalid; + +// Waveform Fields. +reg [31:0] freq_r; +reg [31:0] phase_r; +reg [15:0] addr_r; +reg [15:0] gain_r; +reg [15:0] nsamp_r; +reg [1:0] outsel_r; +reg mode_r; +reg stdysel_r; +reg phrst_r; + +// Assignment of data out for debugging. +wire [15:0] dout_ii [0:N_DDS-1]; + +// AXI VIP master address. +xil_axi_ulong addr_start_addr = 32'h40000000; // 0 +xil_axi_ulong addr_we = 32'h40000004; // 1 + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Test bench control. +reg tb_load_mem = 0; +reg tb_load_mem_done = 0; +reg tb_load_wave = 0; +reg tb_load_wave_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m_axis_tdata[16*ii +: 16]; +end +endgenerate +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_signal_gen_v5 + # + ( + .N (N ), + .N_DDS (N_DDS ) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // AXIS Slave to load data into memory. + .s0_axis_aclk (s0_axis_aclk ), + .s0_axis_aresetn(s0_axis_aresetn), + .s0_axis_tdata (s0_axis_tdata ), + .s0_axis_tvalid (s0_axis_tvalid ), + .s0_axis_tready (s0_axis_tready ), + + // s1_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // AXIS Slave to queue waveforms. + .s1_axis_tdata (s1_axis_tdata ), + .s1_axis_tvalid (s1_axis_tvalid ), + .s1_axis_tready (s1_axis_tready ), + + // AXIS Master for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +assign s1_axis_tdata = {{10{1'b0}},phrst_r,stdysel_r,mode_r,outsel_r,nsamp_r,{16{1'b0}},gain_r,{16{1'b0}},addr_r,phase_r,freq_r}; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + s0_axis_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + s0_axis_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("############################"); + $display("### Load data into Table ###"); + $display("############################"); + $display("t = %0t", $time); + + /* + ADDR = 0 + */ + + // start_addr. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_start_addr, prot, data_wr, resp); + #10; + + // we. + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_we, prot, data_wr, resp); + #10; + + // Load Table. + tb_load_mem <= 1; + wait (tb_load_mem_done); + + #100; + + // we. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_we, prot, data_wr, resp); + #10; + + #1000; + + $display("#######################"); + $display("### Queue Waveforms ###"); + $display("#######################"); + $display("t = %0t", $time); + + // Queue waveforms and write output while queuing. + tb_load_wave <= 1; + tb_write_out <= 1; + wait (tb_load_wave_done); + + #30000; + + // Stop writing output data. + tb_write_out <= 0; + + #20000; + +end + +// Load data into memroy. +initial begin + int fd,vali,valq; + bit signed [15:0] ii,qq; + + s0_axis_tvalid <= 0; + s0_axis_tdata <= 0; + + wait (tb_load_mem); + + fd = $fopen("../../../../../tb/gauss.txt","r"); + + wait (s0_axis_tready); + + while($fscanf(fd,"%d,%d", valq,vali) == 2) begin + $display("I,Q: %d, %d", vali,valq); + ii = vali; + qq = valq; + @(posedge s0_axis_aclk); + s0_axis_tvalid <= 1; + s0_axis_tdata <= {qq,ii}; + end + + @(posedge s0_axis_aclk); + s0_axis_tvalid <= 0; + + $fclose(fd); + tb_load_mem_done <= 1; + +end + +// Load waveforms. +initial begin + s1_axis_tvalid <= 0; + freq_r <= 0; + phase_r <= 0; + addr_r <= 0; + gain_r <= 0; + nsamp_r <= 0; + outsel_r <= 0; + mode_r <= 0; + stdysel_r <= 0; + phrst_r <= 0; + + wait (tb_load_wave); + wait (s1_axis_tready); + + @(posedge aclk); + $display("t = %0t", $time); + s1_axis_tvalid <= 1; + freq_r <= freq_calc(100, N_DDS, 4); // 120 MHz. + phase_r <= 0; + addr_r <= 22; + gain_r <= 12000; + nsamp_r <= 123; + outsel_r <= 1; // 0: prod, 1: dds, 2: mem + mode_r <= 0; // 0: nsamp, 1: periodic + stdysel_r <= 0; // 0: last, 1: zero. + + @(posedge aclk); + $display("t = %0t", $time); + s1_axis_tvalid <= 1; + freq_r <= freq_calc(100, N_DDS, 13); + phase_r <= 0; + addr_r <= 0; + gain_r <= 30000; + nsamp_r <= 512/N_DDS; + outsel_r <= 0; // 0: prod, 1: dds, 2: mem + mode_r <= 0; // 0: nsamp, 1: periodic + stdysel_r <= 0; // 0: last, 1: zero. + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 33); + //phase_r <= 0; + //addr_r <= 5; + //gain_r <= 30000; + //nsamp_r <= 670/N_DDS; + //outsel_r <= 1; // 0: prod, 1: dds, 2: mem + //mode_r <= 0; // 0: nsamp, 1: periodic + //stdysel_r <= 1; // 0: last, 1: zero. + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 22); + //phase_r <= 7689; + //addr_r <= 0; + //gain_r <= 30000; + //nsamp_r <= 70/N_DDS; + //outsel_r <= 2; // 0: prod, 1: dds, 2: mem + //mode_r <= 1; // 0: nsamp, 1: periodic + //stdysel_r <= 1; // 0: last, 1: zero. + + //@(posedge aclk); + //s1_axis_tvalid <= 0; + + //#30000; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 3); + //phase_r <= 0; + //addr_r <= 5; + //gain_r <= 30000; + //nsamp_r <= 670/N_DDS; + //outsel_r <= 1; // 0: prod, 1: dds, 2: mem + //mode_r <= 0; // 0: nsamp, 1: periodic + //stdysel_r <= 1; // 0: last, 1: zero. + + @(posedge aclk); + s1_axis_tvalid <= 0; + tb_load_wave_done <= 1; +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d; + + // Output file. + fd = $fopen("../../../../../tb/dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, idx, real"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i + + user.org + user + axis_signal_gen_v6 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s0_axis + + + + + + + TDATA + + + s0_axis_tdata + + + + + TVALID + + + s0_axis_tvalid + + + + + TREADY + + + s0_axis_tready + + + + + + s1_axis + + + + + + + TDATA + + + s1_axis_tdata + + + + + TVALID + + + s1_axis_tvalid + + + + + TREADY + + + s1_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s0_axis_aclk + + + + + + + CLK + + + s0_axis_aclk + + + + + + ASSOCIATED_BUSIF + s0_axis + + + ASSOCIATED_RESET + s0_axis_aresetn + + + + + s0_axis_aresetn + + + + + + + RST + + + s0_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_axis:s1_axis + + + ASSOCIATED_RESET + aresetn + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_signal_gen_v6 + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 50561f1b + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_signal_gen_v6 + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 50561f1b + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + d9c2185d + + + + + xilinx_testbench + Test Bench + :vivado.xilinx.com:simulation.testbench + tb + + xilinx_testbench_view_fileset + + + + viewChecksum + d48a8e69 + + + + + + + s_axi_aclk + + in + + + std_logic + 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vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/dds_compiler_0/dds_compiler_0.xci + xci + CELL_NAME_signal_gen_top_i/signal_gen_i/GEN_dds[0].genblk1.dds_i + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_signal_gen_v6_v1_0.tcl + tclSource + CHECKSUM_d9c2185d + XGUI_VERSION_2 + + + + xilinx_testbench_view_fileset + + src/tb/tb.sv + systemVerilogSource + USED_IN_simulation + USED_IN_testbench + xil_defaultlib + + + src/tb/axi_mst_0/axi_mst_0.xci + xci + + + src/tb/tb_behav_waves.wcfg + unknown + USED_IN_simulation + USED_IN_testbench + + + src/tb/gauss.txt + text + + + + AXIS Signal Generator V6, Phase coherent with Phase reset. + + + N + N + 12 + + + N_DDS + N Dds + 16 + + + Component_Name + axis_signal_gen_v6_v1_0 + + + GEN_DDS + Gen Dds + TRUE + + + ENVELOPE_TYPE + Envelope Type + COMPLEX + + + + + + zynquplus + + + /UserIP + + AXIS Signal Generator V6 + package_project + 6 + 2025-05-30T17:01:46Z + + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + /home/lstefana/v20.2/ip/axis_signal_gen_v6 + + + + 2023.1 + + + + + + + + + diff --git a/firmware/ip/axis_signal_gen_v6/src/axi_slv.vhd b/firmware/ip/axis_signal_gen_v6/src/axi_slv.vhd new file mode 100644 index 0000000..cb62041 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/axi_slv.vhd @@ -0,0 +1,516 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + START_ADDR_REG : out std_logic_vector (31 downto 0); + WE_REG : out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + -- 0 : START_ADDR_REG : 32-bit. Start address to write into memory. + -- 1 : WE_REG : 1-bit. Enable write into memory. + + -- Output Registers. + START_ADDR_REG <= slv_reg0; + WE_REG <= slv_reg1(0); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v6/src/axis_signal_gen_v6.v b/firmware/ip/axis_signal_gen_v6/src/axis_signal_gen_v6.v new file mode 100644 index 0000000..f56d008 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/axis_signal_gen_v6.v @@ -0,0 +1,210 @@ +// Signal Generator V4. +// s_axi_aclk : clock for s_axi_* +// s0_axis_aclk : clock for s0_axis_* +// aclk : clock for s1_axis_* and m_axis_* +// +module axis_signal_gen_v6 + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // AXIS Slave to load memory samples. + s0_axis_aclk , + s0_axis_aresetn , + s0_axis_tdata , + s0_axis_tvalid , + s0_axis_tready , + + // s1_* and m_* reset/clock. + aclk , + aresetn , + + // AXIS Slave to queue waveforms. + s1_axis_tdata , + s1_axis_tvalid , + s1_axis_tready , + + // AXIS Master for output. + m_axis_tready , + m_axis_tvalid , + m_axis_tdata + ); + +/**************/ +/* Parameters */ +/**************/ +// Envelope Table Memory Size (in 2**N words) +parameter N = 12; + +// Number of parallel DDS blocks. +parameter N_DDS = 16; + +// True: Generate DDS for Envelope Upconversion. False: Remove DDS for Baseband Envelope only +parameter GEN_DDS = "TRUE"; +//parameter GEN_DDS = "FALSE"; + +// COMPLEX: Allow Complex Envelope generation. REAL: Allow only Real envelope generation +//parameter ENVELOPE_TYPE = "REAL"; +parameter ENVELOPE_TYPE = "COMPLEX"; + + +/*********/ +/* Ports */ +/*********/ +input s_axi_aclk; +input s_axi_aresetn; + +input [5:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [5:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input s0_axis_aclk; +input s0_axis_aresetn; +input [31:0] s0_axis_tdata; +input s0_axis_tvalid; +output s0_axis_tready; + +input aresetn; +input aclk; + +input [159:0] s1_axis_tdata; +input s1_axis_tvalid; +output s1_axis_tready; + +input m_axis_tready; +output m_axis_tvalid; +output [N_DDS*16-1:0] m_axis_tdata; + +/********************/ +/* Internal signals */ +/********************/ +// Registers. +wire [31:0] START_ADDR_REG; +wire WE_REG; + + +/**********************/ +/* Begin Architecture */ +/**********************/ +// AXI Slave. +axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG), + .WE_REG (WE_REG ) + ); + +signal_gen_top + #( + .N (N ), + .N_DDS (N_DDS ), + .GEN_DDS (GEN_DDS ), + .ENVELOPE_TYPE (ENVELOPE_TYPE ) + ) + signal_gen_top_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // AXIS Slave to load memory samples. + .s0_axis_aresetn (s0_axis_aresetn ), + .s0_axis_aclk (s0_axis_aclk ), + .s0_axis_tdata_i (s0_axis_tdata ), + .s0_axis_tvalid_i (s0_axis_tvalid ), + .s0_axis_tready_o (s0_axis_tready ), + + // AXIS Slave to queue waveforms. + .s1_axis_tdata_i (s1_axis_tdata ), + .s1_axis_tvalid_i (s1_axis_tvalid ), + .s1_axis_tready_o (s1_axis_tready ), + + // M_AXIS for output. + .m_axis_tready_i (m_axis_tready ), + .m_axis_tvalid_o (m_axis_tvalid ), + .m_axis_tdata_o (m_axis_tdata ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG ), + .WE_REG (WE_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v6/src/ctrl.sv b/firmware/ip/axis_signal_gen_v6/src/ctrl.sv new file mode 100644 index 0000000..bd04d5a --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/ctrl.sv @@ -0,0 +1,498 @@ +//Format of waveform interface: +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// | 159 .. 149 | 148 | 147 | 146 | 145 .. 144 | 143 .. 128 | 127 .. 112 | 111 .. 96 | 95 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// | xxxx | phrst | stdysel | mode | outsel | nsamp | xxxx | gain | xxxx | addr | phase | freq | +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// freq : 32 bits +// phase : 32 bits +// addr : 16 bits +// gain : 16 bits +// nsamp : 16 bits +// outsel : 2 bits +// mode : 1 bit +// stdysel : 1 bit +// phrst : 1 bit +module ctrl ( + // Reset and clock. + rstn, + clk, + + // Fifo interface. + fifo_rd_en_o, + fifo_empty_i, + fifo_dout_i, + + // dds control. + dds_ctrl_o, + + // memory control. + mem_addr_o, + + // gain. + gain_o, + + // Output source selection. + src_o, + + // Steady value selection. + stdy_o, + + // Output enable. + en_o +); + +// Memory address size. +parameter N = 16; + +// Number of parallel dds blocks. +parameter N_DDS = 16; + +// Ports. +input rstn; +input clk; +output fifo_rd_en_o; +input fifo_empty_i; +input [159:0] fifo_dout_i; +output [N_DDS*72-1:0] dds_ctrl_o; +output [N-1:0] mem_addr_o; +output [15:0] gain_o; +output [1:0] src_o; +output stdy_o; +output en_o; + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// Fifo dout register. +reg [159:0] fifo_dout_r; + +// Non-stop counter for time calculation (adds N_DDS samples each clock tick). +reg [31:0] cnt_n; +reg [31:0] cnt_n_reg; + +// Pinc/phase. +wire [31:0] pinc_int; +reg [31:0] pinc_r1; +reg [31:0] pinc_r2; +wire [31:0] pinc_N; +reg [31:0] pinc_N_r1; +reg [31:0] pinc_N_r2; +reg [31:0] pinc_N_r3; +reg [31:0] pinc_N_r4; +reg [31:0] pinc_N_r5; +wire [31:0] pinc_Nm; +reg [31:0] pinc_Nm_r1; +reg [31:0] pinc_Nm_r2; +reg [31:0] pinc_Nm_r3; + +wire [31:0] phase_int; +reg [31:0] phase_r1; +reg [31:0] phase_r2; +reg [31:0] phase_r3; +reg [31:0] phase_r4; +reg [31:0] phase_r5; +wire [31:0] phase_0; +reg [31:0] phase_0_r1; + +// Phase vectors. +wire [31:0] phase_v0 [0:N_DDS-1]; +reg [31:0] phase_v0_r1 [0:N_DDS-1]; +reg [31:0] phase_v0_r2 [0:N_DDS-1]; +reg [31:0] phase_v0_r3 [0:N_DDS-1]; +reg [31:0] phase_v0_r4 [0:N_DDS-1]; +wire [31:0] phase_v1 [0:N_DDS-1]; +reg [31:0] phase_v1_r1 [0:N_DDS-1]; + +// sync. +reg sync_reg; +reg sync_reg_r1; +reg sync_reg_r2; +reg sync_reg_r3; +reg sync_reg_r4; +reg sync_reg_r5; +reg sync_reg_r6; +reg sync_reg_r7; + +// Address. +wire [15:0] addr_int; +reg [15:0] addr_cnt; +reg [15:0] addr_cnt_r1; +reg [15:0] addr_cnt_r2; +reg [15:0] addr_cnt_r3; +reg [15:0] addr_cnt_r4; +reg [15:0] addr_cnt_r5; +reg [15:0] addr_cnt_r6; + +// Gain. +wire [15:0] gain_int; +reg [15:0] gain_r1; +reg [15:0] gain_r2; +reg [15:0] gain_r3; +reg [15:0] gain_r4; +reg [15:0] gain_r5; +reg [15:0] gain_r6; +reg [15:0] gain_r7; + +// Number of samples. +wire [15:0] nsamp_int; + +// Output selection. +wire [1:0] outsel_int; +reg [1:0] outsel_r1; +reg [1:0] outsel_r2; +reg [1:0] outsel_r3; +reg [1:0] outsel_r4; +reg [1:0] outsel_r5; +reg [1:0] outsel_r6; +reg [1:0] outsel_r7; + +// Mode. +wire mode_int; + +// Steady value selection. +wire stdysel_int; +reg stdysel_r1; +reg stdysel_r2; +reg stdysel_r3; +reg stdysel_r4; +reg stdysel_r5; +reg stdysel_r6; +reg stdysel_r7; + +// Phase reset. +wire phrst_int; + +// Load enable flag. +wire load_int; +reg load_r; + +// Fifo Read Enable. +reg rd_en_int; +reg rd_en_r1; +reg rd_en_r2; + +// Counter. +reg [31:0] cnt; + +// Output enable register. +reg en_reg; +reg en_reg_r1; +reg en_reg_r2; +reg en_reg_r3; +reg en_reg_r4; +reg en_reg_r5; +reg en_reg_r6; +reg en_reg_r7; +reg en_reg_r8; + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo dout register. + fifo_dout_r <= 0; + + // Non-stop counter for time calculation. + cnt_n <= 0; + cnt_n_reg <= 0; + + // Pinc/phase/sync. + pinc_r1 <= 0; + pinc_r2 <= 0; + pinc_N_r1 <= 0; + pinc_N_r2 <= 0; + pinc_N_r3 <= 0; + pinc_N_r4 <= 0; + pinc_N_r5 <= 0; + pinc_Nm_r1 <= 0; + pinc_Nm_r2 <= 0; + pinc_Nm_r3 <= 0; + + phase_r1 <= 0; + phase_r2 <= 0; + phase_r3 <= 0; + phase_r4 <= 0; + phase_r5 <= 0; + phase_0_r1 <= 0; + + sync_reg <= 0; + sync_reg_r1 <= 0; + sync_reg_r2 <= 0; + sync_reg_r3 <= 0; + sync_reg_r4 <= 0; + sync_reg_r5 <= 0; + sync_reg_r6 <= 0; + sync_reg_r7 <= 0; + + // Address. + addr_cnt <= 0; + addr_cnt_r1 <= 0; + addr_cnt_r2 <= 0; + addr_cnt_r3 <= 0; + addr_cnt_r4 <= 0; + addr_cnt_r5 <= 0; + addr_cnt_r6 <= 0; + + // Gain. + gain_r1 <= 0; + gain_r2 <= 0; + gain_r3 <= 0; + gain_r4 <= 0; + gain_r5 <= 0; + gain_r6 <= 0; + gain_r7 <= 0; + + // Output selection. + outsel_r1 <= 0; + outsel_r2 <= 0; + outsel_r3 <= 0; + outsel_r4 <= 0; + outsel_r5 <= 0; + outsel_r6 <= 0; + outsel_r7 <= 0; + + // Steady value selection. + stdysel_r1 <= 0; + stdysel_r2 <= 0; + stdysel_r3 <= 0; + stdysel_r4 <= 0; + stdysel_r5 <= 0; + stdysel_r6 <= 0; + stdysel_r7 <= 0; + + // Load enable flag. + load_r <= 0; + + // Fifo Read Enable. + rd_en_r1 <= 0; + rd_en_r2 <= 0; + + // Counter. + cnt <= 0; + + // Output enable register. + en_reg <= 0; + en_reg_r1 <= 0; + en_reg_r2 <= 0; + en_reg_r3 <= 0; + en_reg_r4 <= 0; + en_reg_r5 <= 0; + en_reg_r6 <= 0; + en_reg_r7 <= 0; + en_reg_r8 <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (mode_int || ~fifo_empty_i) + state <= CNT_ST; + CNT_ST: + if ( cnt == nsamp_int-2 ) + state <= READ_ST; + endcase + + // Fifo dout register. + if (load_r) + fifo_dout_r <= fifo_dout_i; + + // Non-stop counter for time calculation. + if (sync_reg == 1'b1 && phrst_int == 1'b1) + cnt_n <= 0; + else + cnt_n <= cnt_n + N_DDS; + + if (sync_reg_r1 == 1'b1) + cnt_n_reg <= cnt_n; + + // Pinc/phase/sync. + pinc_r1 <= pinc_int; + pinc_r2 <= pinc_r1; + pinc_N_r1 <= pinc_N; + pinc_N_r2 <= pinc_N_r1; + pinc_N_r3 <= pinc_N_r2; + pinc_N_r4 <= pinc_N_r3; + pinc_N_r5 <= pinc_N_r4; + pinc_Nm_r1 <= pinc_Nm; + pinc_Nm_r2 <= pinc_Nm_r1; + pinc_Nm_r3 <= pinc_Nm_r2; + + phase_r1 <= phase_int; + phase_r2 <= phase_r1; + phase_r3 <= phase_r2; + phase_r4 <= phase_r3; + phase_r5 <= phase_r4; + phase_0_r1 <= phase_0; + + sync_reg <= load_r; + sync_reg_r1 <= sync_reg; + sync_reg_r2 <= sync_reg_r1; + sync_reg_r3 <= sync_reg_r2; + sync_reg_r4 <= sync_reg_r3; + sync_reg_r5 <= sync_reg_r4; + sync_reg_r6 <= sync_reg_r5; + sync_reg_r7 <= sync_reg_r6; + + // Address. + if (rd_en_r2) + addr_cnt <= addr_int; + else + addr_cnt <= addr_cnt + 1; + + addr_cnt_r1 <= addr_cnt; + addr_cnt_r2 <= addr_cnt_r1; + addr_cnt_r3 <= addr_cnt_r2; + addr_cnt_r4 <= addr_cnt_r3; + addr_cnt_r5 <= addr_cnt_r4; + addr_cnt_r6 <= addr_cnt_r5; + + // Gain. + gain_r1 <= gain_int; + gain_r2 <= gain_r1; + gain_r3 <= gain_r2; + gain_r4 <= gain_r3; + gain_r5 <= gain_r4; + gain_r6 <= gain_r5; + gain_r7 <= gain_r6; + + // Output selection. + outsel_r1 <= outsel_int; + outsel_r2 <= outsel_r1; + outsel_r3 <= outsel_r2; + outsel_r4 <= outsel_r3; + outsel_r5 <= outsel_r4; + outsel_r6 <= outsel_r5; + outsel_r7 <= outsel_r6; + + // Steady value selection. + stdysel_r1 <= stdysel_int; + stdysel_r2 <= stdysel_r1; + stdysel_r3 <= stdysel_r2; + stdysel_r4 <= stdysel_r3; + stdysel_r5 <= stdysel_r4; + stdysel_r6 <= stdysel_r5; + stdysel_r7 <= stdysel_r6; + + // Load enable flag. + load_r <= load_int; + + // Fifo Read Enable. + rd_en_r1 <= rd_en_int; + rd_en_r2 <= rd_en_r1; + + // Counter. + if (rd_en_int) + cnt <= 0; + else + cnt <= cnt + 1; + + // Output enable register. + if (~mode_int && rd_en_int) + if (~fifo_empty_i) + en_reg <= 1; + else + en_reg <= 0; + + en_reg_r1 <= en_reg; + en_reg_r2 <= en_reg_r1; + en_reg_r3 <= en_reg_r2; + en_reg_r4 <= en_reg_r3; + en_reg_r5 <= en_reg_r4; + en_reg_r6 <= en_reg_r5; + en_reg_r7 <= en_reg_r6; + en_reg_r8 <= en_reg_r7; + end +end + +// FSM outputs. +always_comb begin + // Default. + rd_en_int = 0; + + case (state) + READ_ST: + rd_en_int = 1; + + CNT_ST: + rd_en_int = 0; + endcase +end + +// Fifo output fields. +assign pinc_int = fifo_dout_r[31:0]; +assign phase_int = fifo_dout_r[63:32]; +assign addr_int = fifo_dout_r[79:64]; +assign gain_int = fifo_dout_r[111:96]; +assign nsamp_int = fifo_dout_r[143:128]; +assign outsel_int = fifo_dout_r[145:144]; +assign mode_int = fifo_dout_r[146]; +assign stdysel_int = fifo_dout_r[147]; +assign phrst_int = fifo_dout_r[148]; + +// Frequency calculation. +assign pinc_N = pinc_r2*N_DDS; + +// Phase calculation. +assign pinc_Nm = pinc_r2*cnt_n_reg; +assign phase_0 = pinc_Nm_r3 + phase_r5; + +// Phase vectors. +generate +genvar i; + for (i=0; i < N_DDS; i = i + 1) begin : GEN_phase + // Registers. + always @(posedge clk) begin + if (~rstn) begin + // v0. + phase_v0_r1[i] <= 0; + phase_v0_r2[i] <= 0; + phase_v0_r3[i] <= 0; + phase_v0_r4[i] <= 0; + + // v1. + phase_v1_r1[i] <= 0; + end + else begin + // v0. + phase_v0_r1[i] <= phase_v0[i]; + phase_v0_r2[i] <= phase_v0_r1[i]; + phase_v0_r3[i] <= phase_v0_r2[i]; + phase_v0_r4[i] <= phase_v0_r3[i]; + + // v1. + phase_v1_r1[i] <= phase_v1[i]; + end + end + + // v0. + assign phase_v0[i] = pinc_r2*i; + + // v1. + assign phase_v1[i] = phase_v0_r4[i] + phase_0_r1; + + // dds_ctrl_o output. + assign dds_ctrl_o[i*72 +: 72] = {7'h00,sync_reg_r7,phase_v1_r1[i],pinc_N_r5}; + end +endgenerate + +// load_int. +assign load_int = rd_en_int & ~fifo_empty_i; + +// Assign outputs. +assign fifo_rd_en_o = rd_en_int; +assign mem_addr_o = addr_cnt_r6; +assign gain_o = gain_r7; +assign src_o = outsel_r7; +assign stdy_o = stdysel_r7; +assign en_o = en_reg_r8; + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v6/src/data_writer.vhd b/firmware/ip/axis_signal_gen_v6/src/data_writer.vhd new file mode 100644 index 0000000..e38b1c4 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/data_writer.vhd @@ -0,0 +1,226 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity data_writer is + Generic + ( + -- Number of tables. + NT : Integer := 16; + -- Address map of each table. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in STD_LOGIC; + clk : in STD_LOGIC; + + -- AXI Stream I/F. + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- Memory I/F. + mem_en : out std_logic_vector (NT-1 downto 0); + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_di : out std_logic_vector (B-1 downto 0); + + -- Registers. + START_ADDR_REG : in std_logic_vector (31 downto 0); + WE_REG : in std_logic + ); +end data_writer; + +architecture rtl of data_writer is + +-- Log2 of number of tables. +constant NT_LOG2 : Integer := Integer(ceil(log2(real(NT)))); + +-- Synchronizer. +component synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end component; + +-- State machine. +type fsm_state is ( INIT_ST , + READ_START_ADDR_ST , + WAIT_TVALID_ST , + RW_TDATA_ST ); +signal state : fsm_state; + +signal read_start_addr_state : std_logic; +signal rw_tdata_state : std_logic; + +-- WE_REG_resync. +signal WE_REG_resync : std_logic; + +-- Axis registers. +signal tready_i : std_logic; +signal tready_r : std_logic; +signal tdata_r : std_logic_vector(B-1 downto 0); +signal tdata_rr : std_logic_vector(B-1 downto 0); +signal tdata_rrr : std_logic_vector(B-1 downto 0); +signal tvalid_r : std_logic; +signal tvalid_rr : std_logic; +signal tvalid_rrr : std_logic; + +-- Memory Enable. +signal mem_en_i : std_logic_vector (NT-1 downto 0); +signal mem_en_r : std_logic_vector (NT-1 downto 0); + +-- Memory address space. +signal mem_addr_full : unsigned (NT_LOG2+N-1 downto 0); +signal mem_addr_low : unsigned (NT_LOG2-1 downto 0); +signal mem_addr_high : unsigned (N-1 downto 0); +signal mem_addr_high_r : unsigned (N-1 downto 0); + +begin + +-- WE_REG_resync +WE_REG_resync_i : synchronizer_n + generic map ( + N => 2 + ) + port map ( + rstn => rstn , + clk => clk , + data_in => WE_REG , + data_out => WE_REG_resync + ); + +-- Enable logic generation. +GEN: for I in 0 to NT-1 generate + + mem_en_i(I) <= '1' when mem_addr_low = to_unsigned(I,mem_addr_low'length) else + '0'; + +end generate GEN; + +process (clk) +begin + if ( rising_edge(clk) ) then + if (rstn = '0') then + -- Axis registers. + tready_r <= '0'; + tdata_r <= (others => '0'); + tdata_rr <= (others => '0'); + tdata_rrr <= (others => '0'); + tvalid_r <= '0'; + tvalid_rr <= '0'; + tvalid_rrr <= '0'; + + -- Memory address. + mem_addr_full <= (others => '0'); + mem_addr_high_r <= (others => '0'); + mem_en_r <= (others => '0'); + + else + -- Axis registers. + tready_r <= tready_i; + tdata_r <= s_axis_tdata; + tvalid_r <= s_axis_tvalid; + + -- Extra registers to account pipe of state machine. + tdata_rr <= tdata_r; + tdata_rrr <= tdata_rr; + tvalid_rr <= tvalid_r; + tvalid_rrr <= tvalid_rr; + + -- Memory address. + if ( read_start_addr_state = '1') then + mem_addr_full <= to_unsigned(to_integer(unsigned(START_ADDR_REG)),mem_addr_full'length); + elsif ( rw_tdata_state = '1' ) then + mem_addr_full <= mem_addr_full + 1; + end if; + mem_addr_high_r <= mem_addr_high; + mem_en_r <= mem_en_i; + + end if; + end if; +end process; + +-- Address computation. +mem_addr_low <= mem_addr_full(NT_LOG2-1 downto 0); +mem_addr_high <= mem_addr_full(NT_LOG2+N-1 downto NT_LOG2); + +-- Finite state machine. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + state <= INIT_ST; + else + case state is + when INIT_ST => + if ( WE_REG_resync = '1' ) then + state <= READ_START_ADDR_ST; + end if; + + when READ_START_ADDR_ST => + state <= WAIT_TVALID_ST; + + when WAIT_TVALID_ST => + if ( WE_REG_resync = '1') then + if ( tvalid_r = '0' ) then + state <= WAIT_TVALID_ST; + else + state <= RW_TDATA_ST; + end if; + else + state <= INIT_ST; + end if; + + when RW_TDATA_ST => + if ( tvalid_r = '0' ) then + state <= WAIT_TVALID_ST; + end if; + + end case; + end if; + end if; +end process; + +-- Output logic. +process (state) +begin +read_start_addr_state <= '0'; +rw_tdata_state <= '0'; +tready_i <= '0'; + case state is + when INIT_ST => + + when READ_START_ADDR_ST => + read_start_addr_state <= '1'; + + when WAIT_TVALID_ST => + tready_i <= '1'; + + when RW_TDATA_ST => + rw_tdata_state <= '1'; + tready_i <= '1'; + + end case; +end process; + +-- Assign output. +s_axis_tready <= tready_r; + +mem_en <= mem_en_r; +mem_we <= tvalid_rrr; +mem_addr <= std_logic_vector(mem_addr_high_r); +mem_di <= tdata_rrr; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.veo b/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.veo new file mode 100644 index 0000000..894ecd6 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.veo @@ -0,0 +1,69 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:dds_compiler:6.0 +// IP Revision: 18 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +dds_compiler_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid + .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [71 : 0] s_axis_phase_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [31 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file dds_compiler_0.v when simulating +// the core, dds_compiler_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.vho b/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.vho new file mode 100644 index 0000000..e65044c --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.vho @@ -0,0 +1,83 @@ +-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:dds_compiler:6.0 +-- IP Revision: 18 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT dds_compiler_0 + PORT ( + aclk : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : dds_compiler_0 + PORT MAP ( + aclk => aclk, + s_axis_phase_tvalid => s_axis_phase_tvalid, + s_axis_phase_tdata => s_axis_phase_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file dds_compiler_0.vhd when simulating +-- the core, dds_compiler_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.xci new file mode 100644 index 0000000..1a5bc85 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/dds_compiler_0/dds_compiler_0.xci @@ -0,0 +1,357 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "dds_compiler_0", + "component_reference": "xilinx.com:ip:dds_compiler:6.0", + "ip_revision": "22", + "gen_directory": "../../../../projects/qick_tprocv2_216_rfbv2_issue28/top/top.tmp/axis_signal_gen_v6_v1_0_project/axis_signal_gen_v6_v1_0_project.gen/sources_1/ip/dds_compiler_0", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "dds_compiler_0", "resolve_type": "user", "usage": "all" } ], + "PartsPresent": [ { "value": "Phase_Generator_and_SIN_COS_LUT", "value_src": "user", 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cmodel/dds_compiler_v6_0_bitacc_cmodel_lin64.zip + zip + + + cmodel/dds_compiler_v6_0_bitacc_cmodel_nt64.zip + zip + + + + xilinx_vhdltestbench_view_fileset + + demo_tb/tb_dds_compiler_0.vhd + vhdlSource + + + + xilinx_versioninformation_view_fileset + + doc/dds_compiler_v6_0_changelog.txt + text + + + + The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences. + + + Component_Name + Component Name + dds_compiler_0 + + + PartsPresent + Configuration Options + Phase_Generator_and_SIN_COS_LUT + + + DDS_Clock_Rate + System Clock + 256 + + + Channels + Number of Channels + 1 + + + Mode_of_Operation + Mode Of Operation + Standard + + + Modulus + Modulus + 9 + + + Parameter_Entry + Parameter Selection + System_Parameters + + + Spurious_Free_Dynamic_Range + Spurious Free Dynamic Range + 96 + + + Frequency_Resolution + Frequency Resolution + 0.06 + + + Noise_Shaping + Noise Shaping + Auto + + + Phase_Width + Phase Width + 32 + + + Output_Width + Output Width + 16 + + + Phase_Increment + Phase Increment + Streaming + + + Resync + Resync + true + + + Phase_offset + Phase Offset + Streaming + + + Output_Selection + Output Selection + Sine_and_Cosine + + + Negative_Sine + Negative Sine + false + + + Negative_Cosine + Negative Cosine + false + + + Amplitude_Mode + Amplitude Mode + Full_Range + + + Memory_Type + Memory Type + Auto + + + Optimization_Goal + Optimization Goal + Speed + + + DSP48_Use + DSP48 Use + Maximal + + + Has_Phase_Out + Has Phase Out + false + + + DATA_Has_TLAST + DATA Has TLAST + Not_Required + + + Has_TREADY + Output TREADY + false + + + S_PHASE_Has_TUSER + Input + Not_Required + + + S_PHASE_TUSER_Width + User Field Width + 1 + + + M_DATA_Has_TUSER + DATA Output + Not_Required + + + M_PHASE_Has_TUSER + PHASE Output + Not_Required + + + S_CONFIG_Sync_Mode + Synchronization Mode + On_Vector + + + OUTPUT_FORM + Output Form + Twos_Complement + + + Latency_Configuration + Configurable + + + Latency + 2 + + + Has_ARESETn + ARESETn (active low) + false + + + Has_ACLKEN + ACLKEN + false + + + Output_Frequency1 + 0 + + + PINC1 + 0 + + + Phase_Offset_Angles1 + 0 + + + POFF1 + 0 + + + Output_Frequency2 + 0 + + + PINC2 + 0 + + + Phase_Offset_Angles2 + 0 + + + POFF2 + 0 + + + Output_Frequency3 + 0 + + + PINC3 + 0 + + + Phase_Offset_Angles3 + 0 + + + POFF3 + 0 + + + Output_Frequency4 + 0 + + + PINC4 + 0 + + + Phase_Offset_Angles4 + 0 + + + POFF4 + 0 + + + Output_Frequency5 + 0 + + + PINC5 + 0 + + + Phase_Offset_Angles5 + 0 + + + POFF5 + 0 + + + Output_Frequency6 + 0 + + + PINC6 + 0 + + + Phase_Offset_Angles6 + 0 + + + POFF6 + 0 + + + Output_Frequency7 + 0 + + + PINC7 + 0 + + + Phase_Offset_Angles7 + 0 + + + POFF7 + 0 + + + Output_Frequency8 + 0 + + + PINC8 + 0 + + + Phase_Offset_Angles8 + 0 + + + POFF8 + 0 + + + Output_Frequency9 + 0 + + + PINC9 + 0 + + + Phase_Offset_Angles9 + 0 + + + POFF9 + 0 + + + Output_Frequency10 + 0 + + + PINC10 + 0 + + + Phase_Offset_Angles10 + 0 + + + POFF10 + 0 + + + Output_Frequency11 + 0 + + + PINC11 + 0 + + + Phase_Offset_Angles11 + 0 + + + POFF11 + 0 + + + Output_Frequency12 + 0 + + + PINC12 + 0 + + + Phase_Offset_Angles12 + 0 + + + POFF12 + 0 + + + Output_Frequency13 + 0 + + + PINC13 + 0 + + + Phase_Offset_Angles13 + 0 + + + POFF13 + 0 + + + Output_Frequency14 + 0 + + + PINC14 + 0 + + + Phase_Offset_Angles14 + 0 + + + POFF14 + 0 + + + Output_Frequency15 + 0 + + + PINC15 + 0 + + + Phase_Offset_Angles15 + 0 + + + POFF15 + 0 + + + Output_Frequency16 + 0 + + + PINC16 + 0 + + + Phase_Offset_Angles16 + 0 + + + POFF16 + 0 + + + POR_mode + POR Mode + false + + + GUI_Behaviour + Coregen + + + explicit_period + false + + + period + 1 + + + + + DDS Compiler + 18 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.1 + + + + + + + + diff --git a/firmware/ip/axis_signal_gen_v6/src/fifo/bin2gray.vhd b/firmware/ip/axis_signal_gen_v6/src/fifo/bin2gray.vhd new file mode 100644 index 0000000..e3861bc --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/fifo/bin2gray.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end bin2gray; + +architecture rtl of bin2gray is + +signal gray : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +gray(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + gray(I) <= din(I+1) xor din(I); +end generate; + +-- Assign output. +dout <= gray; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v6/src/fifo/bram_dp.vhd b/firmware/ip/axis_signal_gen_v6/src/fifo/bram_dp.vhd new file mode 100644 index 0000000..d57aad1 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/fifo/bram_dp.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture rtl of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v6/src/fifo/bram_simple_dp.vhd b/firmware/ip/axis_signal_gen_v6/src/fifo/bram_simple_dp.vhd new file mode 100644 index 0000000..0a24b90 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/fifo/bram_simple_dp.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_simple_dp; + +architecture rtl of bram_simple_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v6/src/fifo/fifo.vhd b/firmware/ip/axis_signal_gen_v6/src/fifo/fifo.vhd new file mode 100644 index 0000000..382d8e6 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/fifo/fifo.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture rtl of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Dual port, single clock BRAM. +component bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- FIFO memory. +mem_i : bram_simple_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v6/src/fifo/fifo_axi.vhd b/firmware/ip/axis_signal_gen_v6/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..46ec5c4 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v6/src/fifo/fifo_dc.vhd b/firmware/ip/axis_signal_gen_v6/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..5b14e97 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_signal_gen_v6/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_signal_gen_v6/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..4515d28 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v6/src/fifo/gray2bin.vhd b/firmware/ip/axis_signal_gen_v6/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..8509da8 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v6/src/fifo/rd2axi.vhd b/firmware/ip/axis_signal_gen_v6/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..92d267d --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v6/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_signal_gen_v6/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..3d34811 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v6/src/latency_reg.v b/firmware/ip/axis_signal_gen_v6/src/latency_reg.v new file mode 100644 index 0000000..169060e --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/latency_reg.v @@ -0,0 +1,61 @@ +module latency_reg + ( + rstn , + clk , + + din , + dout + ); + +// Parameters. +parameter N = 2; // Latency. +parameter B = 8; // Data width. + +// Ports. +input rstn; +input clk; +input [B-1:0] din; +output [B-1:0] dout; + +// Shift register. +reg [B-1:0] shift_r [0:N-1]; + +generate +genvar i; + for (i=1; i> 1; // divide by 2 to match product path scaling + assign dds_la_mux[i][15:0] = (2**15)-1; + end + + // Muxed output. + assign dout_mux[i] = (src_la == 0)? prod_y_mux[i] : + (src_la == 1)? dds_la_mux[i] : + (src_la == 2)? mem_la_mux[i] : + 16'h0000; + // Product with Gain. + assign prodg_a_real[i] = dout_mux_la[i]; + assign prodg_y_full_real[i] = prodg_a_real[i]*gain_la; + + // Rounding. + assign round[i] = prodg_y_full_real_r[i][30 -: 16]; + + /***********/ + /* Outputs */ + /***********/ + assign m_axis_tdata_o[i*16 +: 16] = (en_la_r == 1'b1)? round_r[i] : + (stdy_la == 1'b0)? last_r[i] : + 16'h0000; + end +endgenerate + +// Latency for source selection. +latency_reg + #( + .N(16), + .B(2) + ) + src_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (src_int ), + .dout (src_la ) + ); + +// Latency for gain. +latency_reg + #( + .N(18), + .B(16) + ) + gain_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (gain_int ), + .dout (gain_la ) + ); + +// Latency for steady value selection. +latency_reg + #( + .N(20), + .B(1) + ) + stdy_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (stdy_int ), + .dout (stdy_la ) + ); + +// Latency for output enable. +latency_reg + #( + .N(19), + .B(1) + ) + en_latency_reg_i + ( + .rstn (rstn ), + .clk (clk ), + + .din (en_int ), + .dout (en_la ) + ); + +// Registers. +generate +if (GEN_DDS == "TRUE") begin + always @(posedge clk) begin + if (~rstn) begin + // DDS intput control. + dds_tvalid_r <= 0; + dds_ctrl_int_r <= 0; + end + else begin + // DDS intput control. + dds_tvalid_r <= 1; + dds_ctrl_int_r <= dds_ctrl_int; + end + end +end +endgenerate +always @(posedge clk) begin + if (~rstn) begin + // Memory address. + mem_addr_int_r <= 0; + // Output enable. + en_la_r <= 0; + end + else begin + // Memory address. + mem_addr_int_r <= mem_addr_int; + // Output enable. + en_la_r <= en_la; + end +end + +// Outputs. +assign mem_addr_o = mem_addr_int_r; +assign m_axis_tvalid_o = en_la_r; + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v6/src/signal_gen_top.v b/firmware/ip/axis_signal_gen_v6/src/signal_gen_top.v new file mode 100644 index 0000000..1980935 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/signal_gen_top.v @@ -0,0 +1,255 @@ +module signal_gen_top + ( + // Reset and clock. + aresetn , + aclk , + + // AXIS Slave to load memory samples. + s0_axis_aresetn , + s0_axis_aclk , + s0_axis_tdata_i , + s0_axis_tvalid_i , + s0_axis_tready_o , + + // AXIS Slave to queue waveforms. + s1_axis_tdata_i , + s1_axis_tvalid_i , + s1_axis_tready_o , + + // M_AXIS for output. + m_axis_tready_i , + m_axis_tvalid_o , + m_axis_tdata_o , + + // Registers. + START_ADDR_REG , + WE_REG + ); + +/**************/ +/* Parameters */ +/**************/ +// Memory address size. +parameter N = 16; + +// Number of parallel dds blocks. +parameter N_DDS = 16; + +// True: Generate DDS for Envelope Upconversion. False: Remove DDS for Baseband Envelope only +parameter GEN_DDS = "TRUE"; + +// COMPLEX: Allow Complex Envelope generation. REAL: Allow only Real envelope generation +parameter ENVELOPE_TYPE = "COMPLEX"; + +/*********/ +/* Ports */ +/*********/ +input aresetn; +input aclk; + +input s0_axis_aresetn; +input s0_axis_aclk; +input [31:0] s0_axis_tdata_i; +input s0_axis_tvalid_i; +output s0_axis_tready_o; + +input [159:0] s1_axis_tdata_i; +input s1_axis_tvalid_i; +output s1_axis_tready_o; + +input m_axis_tready_i; +output m_axis_tvalid_o; +output [N_DDS*16-1:0] m_axis_tdata_o; + +input [31:0] START_ADDR_REG; +input WE_REG; + +/********************/ +/* Internal signals */ +/********************/ +// Fifo. +wire fifo_wr_en; +wire [159:0] fifo_din; +wire fifo_rd_en; +wire [159:0] fifo_dout; +wire fifo_full; +wire fifo_empty; + +// Memory. +wire [N_DDS-1:0] mem_ena; +wire mem_wea; +wire [N-1:0] mem_addra; +wire [31:0] mem_dia; +wire [N-1:0] mem_addrb; +wire [N_DDS*16-1:0] mem_dob_real; +wire [N_DDS*16-1:0] mem_dob_imag; + +/**********************/ +/* Begin Architecture */ +/**********************/ + +// Fifo. +fifo + #( + // Data width. + .B (160), + + // Fifo depth. + .N (16) + ) + fifo_i + ( + .rstn (aresetn ), + .clk (aclk ), + + // Write I/F. + .wr_en (fifo_wr_en ), + .din (fifo_din ), + + // Read I/F. + .rd_en (fifo_rd_en ), + .dout (fifo_dout ), + + // Flags. + .full (fifo_full ), + .empty (fifo_empty ) + ); + +assign fifo_wr_en = s1_axis_tvalid_i; +assign fifo_din = s1_axis_tdata_i; + +// Data writer. +data_writer + #( + // Number of tables. + .NT (N_DDS ), + // Address map of memory. + .N (N ), + // Data width. + .B (32 ) + ) + data_writer_i + ( + .rstn (s0_axis_aresetn ), + .clk (s0_axis_aclk ), + + // AXI Stream I/F. + .s_axis_tready (s0_axis_tready_o ), + .s_axis_tdata (s0_axis_tdata_i ), + .s_axis_tvalid (s0_axis_tvalid_i ), + + // Memory I/F. + .mem_en (mem_ena ), + .mem_we (mem_wea ), + .mem_addr (mem_addra ), + .mem_di (mem_dia ), + + // Registers. + .START_ADDR_REG (START_ADDR_REG ), + .WE_REG (WE_REG ) + ); + +generate + genvar i; + for (i=0; i '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_signal_gen_v6/src/tb/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_signal_gen_v6/src/tb/axi_mst_0/axi_mst_0.veo new file mode 100644 index 0000000..5653a79 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/tb/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 14 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_signal_gen_v6/src/tb/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_signal_gen_v6/src/tb/axi_mst_0/axi_mst_0.vho new file mode 100644 index 0000000..4ca1788 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/tb/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,116 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 14 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. 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xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_14 + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi_mst_0.vho + vhdlTemplate + + + axi_mst_0.veo + verilogTemplate + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_14 + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_14 + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + VIP_PKG_NAME + VIP_PKG_NAME + 0 + + + + + AXI Verification IP + + xtlm + xtlm_ipc_v1_0 + protobuf + + 14 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + + + + + + + + diff --git a/firmware/ip/axis_signal_gen_v6/src/tb/axi_mst_0/axi_mst_0_ooc.xdc b/firmware/ip/axis_signal_gen_v6/src/tb/axi_mst_0/axi_mst_0_ooc.xdc new file mode 100644 index 0000000..bb1ff41 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/tb/axi_mst_0/axi_mst_0_ooc.xdc @@ -0,0 +1,57 @@ +# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of AMD and is protected under U.S. and international copyright +# and other intellectual property laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# AMD, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) AMD shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or AMD had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# AMD products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of AMD products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# DO NOT MODIFY THIS FILE. +# ######################################################### +# +# This XDC is used only in OOC mode for synthesis, implementation +# +# ######################################################### + + +create_clock -period 10 -name aclk [get_ports aclk] + + diff --git a/firmware/ip/axis_signal_gen_v6/src/tb/gauss.txt b/firmware/ip/axis_signal_gen_v6/src/tb/gauss.txt new file mode 100644 index 0000000..68d9265 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/tb/gauss.txt @@ -0,0 +1,512 @@ +57,0 +60,0 +62,0 +65,0 +68,0 +71,0 +74,0 +77,0 +80,0 +83,0 +87,0 +90,0 +94,0 +98,0 +102,0 +106,0 +110,0 +115,0 +119,0 +124,0 +129,0 +134,0 +140,0 +145,0 +151,0 +157,0 +163,0 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+1814,0 +1764,0 +1715,0 +1667,0 +1620,0 +1574,0 +1530,0 +1486,0 +1444,0 +1403,0 +1362,0 diff --git a/firmware/ip/axis_signal_gen_v6/src/tb/gen_gauss.py b/firmware/ip/axis_signal_gen_v6/src/tb/gen_gauss.py new file mode 100644 index 0000000..89bb7b7 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/tb/gen_gauss.py @@ -0,0 +1,22 @@ +import numpy as np +import matplotlib.pyplot as plt + +def gauss(mu=0, si=0, length=100, maxv=30000): + x = np.arange(0,length) + y = 1/(2*np.pi*si**2)*np.exp(-(x-mu)**2/si**2) + y = y/np.max(y)*maxv + return y + +yq = gauss(mu=300, si=120, length=512) +yi = np.zeros(len(yq)) + +yi = yi.astype(np.int16) +yq = yq.astype(np.int16) + +for ii in range(len(yi)): + print("%d,%d" %(yq[ii],yi[ii])) + +# plt.figure() +# plt.plot(yq) +# plt.show() + diff --git a/firmware/ip/axis_signal_gen_v6/src/tb/tb.sv b/firmware/ip/axis_signal_gen_v6/src/tb/tb.sv new file mode 100644 index 0000000..9697977 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/tb/tb.sv @@ -0,0 +1,531 @@ +// VIP: axi_mst_0 +// DUT: axis_signal_gen_v2 +// IF: s_axi -> axi_mst_0 + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +module tb(); + +// DUT generics. +parameter N = 10; +parameter N_DDS = 4; + +// s_axi interfase. +reg s_axi_aclk; +reg s_axi_aresetn; +wire [5:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arready; +wire s_axi_arvalid; +wire [5:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awready; +wire s_axi_awvalid; +wire s_axi_bready; +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire [31:0] s_axi_rdata; +wire s_axi_rready; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire [31:0] s_axi_wdata; +wire s_axi_wready; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; + +// s0_axis interfase. +reg s0_axis_aclk; +reg s0_axis_aresetn; +reg [31:0] s0_axis_tdata; +wire s0_axis_tready; +reg s0_axis_tvalid; + +reg aresetn; +reg aclk; + +// Dummy clock for debugging. +reg aclk4; + +// s1_axis interfase. +reg [159:0] s1_axis_tdata; +wire s1_axis_tready; +reg s1_axis_tvalid; + +// m_axis interfase. +wire [N_DDS*16-1:0] m_axis_tdata; +reg m_axis_tready = 1; +wire m_axis_tvalid; + +// Waveform Fields. +reg [31:0] freq_r; +reg [31:0] phase_r; +reg [15:0] addr_r; +reg [15:0] gain_r; +reg [15:0] nsamp_r; +reg [1:0] outsel_r; +reg mode_r; +reg stdysel_r; +reg phrst_r; + +// Assignment of data out for debugging. +wire [15:0] dout_ii [0:N_DDS-1]; +reg [15:0] dout_f; + +// AXI VIP master address. +xil_axi_ulong addr_start_addr = 32'h40000000; // 0 +xil_axi_ulong addr_we = 32'h40000004; // 1 + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Test bench control. +reg tb_load_mem = 0; +reg tb_load_mem_done = 0; +reg tb_load_wave = 0; +reg tb_load_wave_done = 0; +reg tb_write_out = 0; + +// Debug. +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dout_ii[ii] = m_axis_tdata[16*ii +: 16]; +end +endgenerate +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +axis_signal_gen_v6 + # + ( + .N (N ), + .N_DDS (N_DDS ), + .GEN_DDS ("FALSE" ), + .ENVELOPE_TYPE ("REAL" ) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // AXIS Slave to load data into memory. + .s0_axis_aclk (s0_axis_aclk ), + .s0_axis_aresetn(s0_axis_aresetn), + .s0_axis_tdata (s0_axis_tdata ), + .s0_axis_tvalid (s0_axis_tvalid ), + .s0_axis_tready (s0_axis_tready ), + + // s1_* and m_* reset/clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // AXIS Slave to queue waveforms. + .s1_axis_tdata (s1_axis_tdata ), + .s1_axis_tvalid (s1_axis_tvalid ), + .s1_axis_tready (s1_axis_tready ), + + // AXIS Master for output data. + .m_axis_tready (m_axis_tready ), + .m_axis_tvalid (m_axis_tvalid ), + .m_axis_tdata (m_axis_tdata ) + ); + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; + +assign s1_axis_tdata = {{10{1'b0}},phrst_r,stdysel_r,mode_r,outsel_r,nsamp_r,{16{1'b0}},gain_r,{16{1'b0}},addr_r,phase_r,freq_r}; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + s0_axis_aresetn <= 0; + aresetn <= 0; + #500; + s_axi_aresetn <= 1; + s0_axis_aresetn <= 1; + aresetn <= 1; + + #1000; + + $display("############################"); + $display("### Load data into Table ###"); + $display("############################"); + $display("t = %0t", $time); + + /* + ADDR = 0 + */ + + // start_addr. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_start_addr, prot, data_wr, resp); + #10; + + // we. + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_we, prot, data_wr, resp); + #10; + + // Load Envelope Table Memory. + tb_load_mem <= 1; + wait (tb_load_mem_done); + + #100; + + // we. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(addr_we, prot, data_wr, resp); + #10; + + #1000; + + $display("#######################"); + $display("### Queue Waveforms ###"); + $display("#######################"); + $display("t = %0t", $time); + + // Queue waveforms and write output while queuing. + tb_load_wave <= 1; + tb_write_out <= 1; + wait (tb_load_wave_done); + + #10us; + + // Stop writing output data. + tb_write_out <= 0; + + #5us; + + $finish(); + +end + +// Load pulse data into memory. +initial begin + int fd,vali,valq; + bit signed [15:0] ii,qq; + + s0_axis_tvalid <= 0; + s0_axis_tdata <= 0; + + wait (tb_load_mem); + + // File must be in the same directory from where the simulation is run + fd = $fopen("./gauss.txt","r"); + + wait (s0_axis_tready); + + while($fscanf(fd,"%d,%d", vali,valq) == 2) begin + $display("I,Q: %d, %d", vali,valq); + ii = vali; + qq = valq; + @(posedge s0_axis_aclk); + s0_axis_tvalid <= 1; + s0_axis_tdata <= {qq,ii}; + end + + @(posedge s0_axis_aclk); + s0_axis_tvalid <= 0; + + $fclose(fd); + tb_load_mem_done <= 1; +end + + +// Load waveforms. +initial begin + s1_axis_tvalid <= 0; + freq_r <= 0; + phase_r <= 0; + addr_r <= 0; + gain_r <= 0; + nsamp_r <= 0; + outsel_r <= 0; + mode_r <= 0; + stdysel_r <= 0; + phrst_r <= 0; + + wait (tb_load_wave); + wait (s1_axis_tready); + +// @(posedge aclk); +// $display("t = %0t", $time); +// s1_axis_tvalid <= 1; +// freq_r <= freq_calc(100, N_DDS, 4); // 120 MHz. +// phase_r <= 0; +// addr_r <= 22; +// gain_r <= 12000; +// nsamp_r <= 80; +// outsel_r <= 1; // 0: prod, 1: dds, 2: mem +// mode_r <= 0; // 0: nsamp, 1: periodic +// stdysel_r <= 0; // 0: last, 1: zero. +// phrst_r <= 0; + + @(posedge aclk); + $display("t = %0t", $time); + s1_axis_tvalid <= 1; + freq_r <= freq_calc(0, N_DDS, 4); // 120 MHz. + phase_r <= 0; + addr_r <= 22; + gain_r <= 12000; + nsamp_r <= 80; + outsel_r <= 0; // 0: prod, 1: dds, 2: mem + mode_r <= 0; // 0: nsamp, 1: periodic + stdysel_r <= 0; // 0: last, 1: zero. + phrst_r <= 0; + + #5us; + + @(posedge aclk); + $display("t = %0t", $time); + s1_axis_tvalid <= 1; + freq_r <= freq_calc(0, N_DDS, 4); // 120 MHz. + phase_r <= 0; + addr_r <= 22; + gain_r <= 12000; + nsamp_r <= 80; + outsel_r <= 1; // 0: prod, 1: dds, 2: mem + mode_r <= 0; // 0: nsamp, 1: periodic + stdysel_r <= 0; // 0: last, 1: zero. + phrst_r <= 0; + + #5us; + + @(posedge aclk); + $display("t = %0t", $time); + s1_axis_tvalid <= 1; + freq_r <= freq_calc(0, N_DDS, 4); // 120 MHz. + phase_r <= 0; + addr_r <= 22; + gain_r <= 12000; + nsamp_r <= 80; + outsel_r <= 2; // 0: prod, 1: dds, 2: mem + mode_r <= 0; // 0: nsamp, 1: periodic + stdysel_r <= 0; // 0: last, 1: zero. + phrst_r <= 0; + + #5us; + +// @(posedge aclk); +// $display("t = %0t", $time); +// s1_axis_tvalid <= 1; +// freq_r <= freq_calc(100, N_DDS, 4); // 120 MHz. +// phase_r <= 0; +// addr_r <= 22; +// gain_r <= 12000; +// nsamp_r <= 123; +// outsel_r <= 1; // 0: prod, 1: dds, 2: mem +// mode_r <= 0; // 0: nsamp, 1: periodic +// stdysel_r <= 0; // 0: last, 1: zero. +// phrst_r <= 1; + +// @(posedge aclk); +// s1_axis_tvalid <= 0; + +// #5us; + +// @(posedge aclk); +// $display("t = %0t", $time); +// s1_axis_tvalid <= 1; +// freq_r <= freq_calc(100, N_DDS, 13); +// phase_r <= 0; +// addr_r <= 0; +// gain_r <= 30000; +// nsamp_r <= 400/N_DDS; +// outsel_r <= 0; // 0: prod, 1: dds, 2: mem +// mode_r <= 0; // 0: nsamp, 1: periodic +// stdysel_r <= 1; // 0: last, 1: zero. +// phrst_r <= 0; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 33); + //phase_r <= 0; + //addr_r <= 5; + //gain_r <= 30000; + //nsamp_r <= 670/N_DDS; + //outsel_r <= 1; // 0: prod, 1: dds, 2: mem + //mode_r <= 0; // 0: nsamp, 1: periodic + //stdysel_r <= 1; // 0: last, 1: zero. + +// @(posedge aclk); +// $display("t = %0t", $time); +// s1_axis_tvalid <= 1; +// freq_r <= freq_calc(100, N_DDS, 22); +// phase_r <= 7689; +// addr_r <= 0; +// gain_r <= 30000; +// nsamp_r <= 70/N_DDS; +// outsel_r <= 2; // 0: prod, 1: dds, 2: mem +// mode_r <= 1; // 0: nsamp, 1: periodic +// stdysel_r <= 1; // 0: last, 1: zero. + +// @(posedge aclk); +// s1_axis_tvalid <= 0; + + //#30000; + + //@(posedge aclk); + //$display("t = %0t", $time); + //s1_axis_tvalid <= 1; + //freq_r <= freq_calc(100, N_DDS, 3); + //phase_r <= 0; + //addr_r <= 5; + //gain_r <= 30000; + //nsamp_r <= 670/N_DDS; + //outsel_r <= 1; // 0: prod, 1: dds, 2: mem + //mode_r <= 0; // 0: nsamp, 1: periodic + //stdysel_r <= 1; // 0: last, 1: zero. + + @(posedge aclk); + s1_axis_tvalid <= 0; + tb_load_wave_done <= 1; +end + +// Write output into file. +initial begin + int fd; + int i; + shortint real_d; + + // Output file. + fd = $fopen("./dout.csv","w"); + + // Data format. + $fdisplay(fd, "valid, idx, real"); + + wait (tb_write_out); + + while (tb_write_out) begin + @(posedge aclk); + for (i=0; i + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LOAD_MEMORY + label + + tb_load_mem + tb_load_mem + + + s0_axis_tready + s0_axis_tready + + + s0_axis_tvalid + s0_axis_tvalid + + + s0_axis_tdata[31:0] + s0_axis_tdata[31:0] + + + New Virtual Bus 13 + label + SIGNEDDECRADIX + STYLE_ANALOG + 100 + + [15] + [15] + + + [14] + [14] + + + [13] + [13] + + + [12] + [12] + + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + New Virtual Bus 12 + label + SIGNEDDECRADIX + STYLE_ANALOG + 100 + + [31] + [31] + + + [30] + [30] + + + [29] + [29] + + + [28] + [28] + + + [27] + [27] + + + [26] + [26] + + + [25] + [25] + + + [24] + [24] + + + [23] + [23] + + + [22] + [22] + + + [21] + [21] + + + [20] + [20] + + + [19] + [19] + + + [18] + [18] + + + [17] + [17] + + + [16] + [16] + + + + tb_load_mem_done + tb_load_mem_done + + + + LOAD_WAVEFORM + label + + + tb_load_wave + tb_load_wave + + + freq_r[31:0] + freq_r[31:0] + UNSIGNEDDECRADIX + + + phase_r[31:0] + phase_r[31:0] + UNSIGNEDDECRADIX + + + addr_r[15:0] + addr_r[15:0] + UNSIGNEDDECRADIX + + + gain_r[15:0] + gain_r[15:0] + UNSIGNEDDECRADIX + + + nsamp_r[15:0] + nsamp_r[15:0] + UNSIGNEDDECRADIX + + + outsel_r[1:0] + outsel_r[1:0] + UNSIGNEDDECRADIX + + + mode_r + mode_r + + + stdysel_r + stdysel_r + + + phrst_r + phrst_r + + + s1_axis_tready + s1_axis_tready + + + s1_axis_tvalid + s1_axis_tvalid + + + s1_axis_tdata[159:0] + s1_axis_tdata[159:0] + + + tb_load_wave_done + tb_load_wave_done + + + + tb_write_out + tb_write_out + + + SG_DATA_WRITER + label + + rstn + rstn + + + clk + clk + + + state + state + + + + SG_FIFO_IN + label + + rstn + rstn + + + clk + clk + + + wr_en + wr_en + + + din[159:0] + din[159:0] + + + full + full + + + rd_en + rd_en + + + dout[159:0] + dout[159:0] + + + empty + empty + + + + DDSs_COMPILER + label + + DDS_0 + label + + + dds_0_imag + label + SIGNEDDECRADIX + STYLE_ANALOG + 100 + + + dds_0_real + label + SIGNEDDECRADIX + STYLE_ANALOG + 100 + + + + DDS_1 + label + + + DDS_2 + label + + + DDS_3 + label + + + + CTRL + label + + fifo_rd_en_o + fifo_rd_en_o + + + fifo_empty_i + fifo_empty_i + + + fifo_dout_i[159:0] + fifo_dout_i[159:0] + + + cnt_n[31:0] + cnt_n[31:0] + UNSIGNEDDECRADIX + + + cnt_n_reg[31:0] + cnt_n_reg[31:0] + UNSIGNEDDECRADIX + + + state[31:0] + state[31:0] + + + mem_addr_o[9:0] + mem_addr_o[9:0] + + + gain_o[15:0] + gain_o[15:0] + UNSIGNEDDECRADIX + + + src_o[1:0] + src_o[1:0] + + + stdy_o + stdy_o + + + en_o + en_o + + + + SIGNAL_PATH + label + + + [0][15:0] + [0][15:0] + SIGNEDDECRADIX + STYLE_ANALOG + 100 + ANALOG_YRANGETYPE_AUTO + 0.000000 + 0.000000 + ANALOG_INTERPOLATION_HOLD + ANALOG_OFFSCALE_HIDE + 0.000000 + + + [0][15:0] + [0][15:0] + SIGNEDDECRADIX + STYLE_ANALOG + 100 + ANALOG_YRANGETYPE_AUTO + 0.000000 + 0.000000 + ANALOG_INTERPOLATION_HOLD + ANALOG_OFFSCALE_HIDE + 0.000000 + + + + M_AXIS_OUT + label + + m_axis_tready_i + m_axis_tready_i + + + m_axis_tvalid_o + m_axis_tvalid_o + + + m_axis_tdata_o[63:0] + m_axis_tdata_o[63:0] + + + dout_ii[0:3][15:0] + dout_ii[0:3][15:0] + + + + diff --git a/firmware/ip/axis_signal_gen_v6/src/tb/tb_ctrl.sv b/firmware/ip/axis_signal_gen_v6/src/tb/tb_ctrl.sv new file mode 100644 index 0000000..b6606c5 --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/tb/tb_ctrl.sv @@ -0,0 +1,188 @@ +module tb(); + +// Memory address size. +parameter N = 16; + +// Number of parallel dds blocks. +parameter N_DDS = 2; + +// Ports. +reg rstn; +reg clk; + +wire fifo_rd_en_o; +reg fifo_empty_i; +wire[159:0] fifo_dout_i; +wire[N_DDS*72-1:0] dds_ctrl_o; +wire[N-1:0] mem_addr_o; +wire[15:0] gain_o; +wire[1:0] src_o; +wire stdy_o; +wire en_o; + +// Fifo signals. +reg fifo_wr_en; +wire[159:0] fifo_din; +wire fifo_full; + +// Fifo Fields. +reg [31:0] freq_r; +reg [31:0] phase_r; +reg [15:0] addr_r; +reg [15:0] gain_r; +reg [15:0] nsamp_r; +reg [1:0] outsel_r; +reg mode_r; +reg stdysel_r; +reg phrst_r; + +// Assignment of DDSs for debugging. +wire [71:0] dds_ctrl_ii [0:N_DDS-1]; + +integer i; + +generate +genvar ii; +for (ii = 0; ii < N_DDS; ii = ii + 1) begin : GEN_debug + assign dds_ctrl_ii[ii] = dds_ctrl_o[72*ii +: 72]; +end +endgenerate + +// Fifo. +fifo + #( + // Data width. + .B (160), + + // Fifo depth. + .N (16) + ) + fifo_i + ( + .rstn (rstn ), + .clk (clk ), + + // Write I/F. + .wr_en (fifo_wr_en ), + .din (fifo_din ), + + // Read I/F. + .rd_en (fifo_rd_en_o ), + .dout (fifo_dout_i ), + + // Flags. + .full (fifo_full ), + .empty (fifo_empty_i ) + ); + +// DUT. +ctrl + #( + .N (N ), + .N_DDS (N_DDS ) + ) + DUT + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Fifo interface. + .fifo_rd_en_o (fifo_rd_en_o ), + .fifo_empty_i (fifo_empty_i ), + .fifo_dout_i (fifo_dout_i ), + + // dds control. + .dds_ctrl_o (dds_ctrl_o ), + + // memory control. + .mem_addr_o (mem_addr_o ), + + // gain. + .gain_o (gain_o ), + + // Output source selection. + .src_o (src_o ), + + // Steady value selection. + .stdy_o (stdy_o ), + + // Output enable. + .en_o (en_o ) + ); + +assign fifo_din = { {11{1'b0}} , + phrst_r , + stdysel_r , + mode_r , + outsel_r , + nsamp_r , + {16{1'b0}} , + gain_r , + {16{1'b0}} , + addr_r , + phase_r , + freq_r }; + +initial begin + rstn <= 0; + fifo_wr_en <= 0; + freq_r <= 0; + phase_r <= 0; + addr_r <= 0; + gain_r <= 0; + nsamp_r <= 0; + outsel_r <= 0; + mode_r <= 0; + stdysel_r <= 0; + phrst_r <= 0; + #200; + rstn <= 1; + + #200; + + @(posedge clk); + fifo_wr_en <= 1; + freq_r <= 100; + phase_r <= 0; + addr_r <= 50; + gain_r <= 40; + nsamp_r <= 10; + outsel_r <= 2; + mode_r <= 1; + stdysel_r <= 0; + phrst_r <= 1; + + @(posedge clk); + fifo_wr_en <= 0; + + #1000; + + @(posedge clk); + fifo_wr_en <= 1; + freq_r <= 3516; + phase_r <= 2345; + addr_r <= 5; + gain_r <= 4; + nsamp_r <= 5; + outsel_r <= 2; + mode_r <= 0; + stdysel_r <= 1; + phrst_r <= 0; + + @(posedge clk); + fifo_wr_en <= 0; + + #10000; + +end + +always begin + clk <= 0; + #10; + clk <= 1; + #10; +end + +endmodule + diff --git a/firmware/ip/axis_signal_gen_v6/src/timing.xdc b/firmware/ip/axis_signal_gen_v6/src/timing.xdc new file mode 100644 index 0000000..49ab49c --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/src/timing.xdc @@ -0,0 +1,10 @@ +create_clock -period 10.000 -name s_axi_aclk -waveform {0.000 5.000} [get_ports s_axi_aclk] +create_clock -period 2.000 -name aclk -waveform {0.000 1.000} [get_ports aclk] +create_clock -period 10.000 -name s0_axis_aclk -waveform {0.000 5.000} [get_ports s0_axis_aclk] + +set_clock_groups -asynchronous -group [get_clocks aclk] -group [get_clocks s0_axis_aclk] -group [get_clocks s_axi_aclk] + + + +set _xlnx_shared_i0 [get_ports s1_axis_t*] +set_false_path -from $_xlnx_shared_i0 diff --git a/firmware/ip/axis_signal_gen_v6/xgui/axis_signal_gen_v6_v1_0.tcl b/firmware/ip/axis_signal_gen_v6/xgui/axis_signal_gen_v6_v1_0.tcl new file mode 100644 index 0000000..ce6168d --- /dev/null +++ b/firmware/ip/axis_signal_gen_v6/xgui/axis_signal_gen_v6_v1_0.tcl @@ -0,0 +1,71 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + set N [ipgui::add_param $IPINST -name "N" -parent ${Page_0}] + set_property tooltip {Envelope Memory Size in 2^N Words} ${N} + ipgui::add_param $IPINST -name "N_DDS" -parent ${Page_0} + ipgui::add_param $IPINST -name "GEN_DDS" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "ENVELOPE_TYPE" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.ENVELOPE_TYPE { PARAM_VALUE.ENVELOPE_TYPE } { + # Procedure called to update ENVELOPE_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ENVELOPE_TYPE { PARAM_VALUE.ENVELOPE_TYPE } { + # Procedure called to validate ENVELOPE_TYPE + return true +} + +proc update_PARAM_VALUE.GEN_DDS { PARAM_VALUE.GEN_DDS } { + # Procedure called to update GEN_DDS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.GEN_DDS { PARAM_VALUE.GEN_DDS } { + # Procedure called to validate GEN_DDS + return true +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + +proc update_PARAM_VALUE.N_DDS { PARAM_VALUE.N_DDS } { + # Procedure called to update N_DDS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N_DDS { PARAM_VALUE.N_DDS } { + # Procedure called to validate N_DDS + return true +} + + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + +proc update_MODELPARAM_VALUE.N_DDS { MODELPARAM_VALUE.N_DDS PARAM_VALUE.N_DDS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N_DDS}] ${MODELPARAM_VALUE.N_DDS} +} + +proc update_MODELPARAM_VALUE.GEN_DDS { MODELPARAM_VALUE.GEN_DDS PARAM_VALUE.GEN_DDS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.GEN_DDS}] ${MODELPARAM_VALUE.GEN_DDS} +} + +proc update_MODELPARAM_VALUE.ENVELOPE_TYPE { MODELPARAM_VALUE.ENVELOPE_TYPE PARAM_VALUE.ENVELOPE_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ENVELOPE_TYPE}] ${MODELPARAM_VALUE.ENVELOPE_TYPE} +} + diff --git a/firmware/ip/axis_terminator/component.xml b/firmware/ip/axis_terminator/component.xml new file mode 100644 index 0000000..b75874e --- /dev/null +++ b/firmware/ip/axis_terminator/component.xml @@ -0,0 +1,368 @@ + + + user.org + user + axis_terminator + 1.0 + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TSTRB + + + s_axis_tstrb + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axis_aresetn + + + + + + + RST + + + s_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axis_aclk + + + + + + + CLK + + + s_axis_aclk + + + + + + ASSOCIATED_BUSIF + s_axis + + + ASSOCIATED_RESET + s_axis_aresetn + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + axis_terminator + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + d2deb9f7 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + axis_terminator + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + d2deb9f7 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 35ebc586 + + + + + + + s_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axis_tstrb + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axis_tlast + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + DATA_WIDTH + Data Width + 16 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/axis_terminator.vhd + vhdlSource + CHECKSUM_d2deb9f7 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/axis_terminator.vhd + vhdlSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_terminator_v1_0.tcl + tclSource + CHECKSUM_35ebc586 + XGUI_VERSION_2 + + + + AXIS Terminator block. + + + DATA_WIDTH + Data Width + 16 + + + Component_Name + axis_terminator_v1_0 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + kintexuplus + kintexu + + + /UserIP + + AXIS Terminator + package_project + 2 + 2019-08-16T18:41:23Z + + /home/lstefana/v18.3/ip/axis_terminator + /home/lstefana/v18.3/ip/axis_terminator + /home/lstefana/v18.3/ip/axis_terminator + /home/lstefana/v18.3/ip/axis_terminator + /home/lstefana/v18.3/ip/axis_terminator + /home/lstefana/v18.3/ip/axis_terminator + /home/lstefana/v18.3/ip/axis_terminator + + + + 2018.3 + + + + + + + + diff --git a/firmware/ip/axis_terminator/src/axis_terminator.vhd b/firmware/ip/axis_terminator/src/axis_terminator.vhd new file mode 100644 index 0000000..90824d6 --- /dev/null +++ b/firmware/ip/axis_terminator/src/axis_terminator.vhd @@ -0,0 +1,31 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity axis_terminator is + generic + ( + -- Data width. + DATA_WIDTH : Integer := 16 + ); + port + ( + -- AXIS Slave I/F. + s_axis_aclk : in std_logic; + s_axis_aresetn : in std_logic; + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + s_axis_tstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic + ); +end axis_terminator; + +architecture rtl of axis_terminator is + +begin + +s_axis_tready <= '1'; + +end rtl; + diff --git a/firmware/ip/axis_terminator/xgui/axis_terminator_v1_0.tcl b/firmware/ip/axis_terminator/xgui/axis_terminator_v1_0.tcl new file mode 100644 index 0000000..55a2622 --- /dev/null +++ b/firmware/ip/axis_terminator/xgui/axis_terminator_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + diff --git a/firmware/ip/axis_tmux_v1/axis_tmux_v1_0.xcix b/firmware/ip/axis_tmux_v1/axis_tmux_v1_0.xcix new file mode 100644 index 0000000..2bd23d6 Binary files /dev/null and b/firmware/ip/axis_tmux_v1/axis_tmux_v1_0.xcix differ diff --git a/firmware/ip/axis_tmux_v1/component.xml b/firmware/ip/axis_tmux_v1/component.xml new file mode 100644 index 0000000..cb84258 --- /dev/null +++ b/firmware/ip/axis_tmux_v1/component.xml @@ -0,0 +1,797 @@ + + + user.org + user + axis_tmux_v1 + 1.0 + + + m0_axis + + + + + + + TDATA + + + m0_axis_tdata + + + + + TVALID + + + m0_axis_tvalid + + + + + + m1_axis + + + + + + + TDATA + + + m1_axis_tdata + + + + + TVALID + + + m1_axis_tvalid + + + + + + + true + + + + + + m2_axis + + + + + + + TDATA + + + m2_axis_tdata + + + + + TVALID + + + m2_axis_tvalid + + + + + + + false + + + + + + m3_axis + + + + + + + TDATA + + + m3_axis_tdata + + + + + TVALID + + + m3_axis_tvalid + + + + + + + false + + + + + + m4_axis + + + + true + + + + TDATA + + + m4_axis_tdata + + + + + TVALID + + + m4_axis_tvalid + + + + + + + false + + + + + + m5_axis + + + + + + + TDATA + + + m5_axis_tdata + + + + + TVALID + + + m5_axis_tvalid + + + + + + + false + + + + + + m6_axis + + + + + + + TDATA + + + m6_axis_tdata + + + + + TVALID + + + m6_axis_tvalid + + + + + + + false + + + + + + m7_axis + + + + + + + TDATA + + + m7_axis_tdata + + + + + TVALID + + + m7_axis_tvalid + + + + + + + false + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m0_axis:m1_axis:m2_axis:m3_axis:m4_axis:m5_axis:m6_axis:m7_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axis_tmux_v1 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 49caebd3 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axis_tmux_v1 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 49caebd3 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 5752b26c + + + + + + + aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m0_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tdata + + out + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tdata + + out + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m2_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m2_axis_tdata + + out + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m3_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m3_axis_tdata + + out + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m4_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m4_axis_tdata + + out + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m5_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m5_axis_tdata + + out + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m6_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m6_axis_tdata + + out + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m7_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m7_axis_tdata + + out + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N + N + 2 + + + B + B + 16 + + + + + + choice_list_2a885f8d + 2 + 3 + 4 + 5 + 6 + 7 + 8 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/tmux.sv + systemVerilogSource + + + src/axis_tmux_v1.sv + systemVerilogSource + CHECKSUM_625dc80f + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/tmux.sv + systemVerilogSource + + + src/axis_tmux_v1.sv + systemVerilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_tmux_v1_v1_0.tcl + tclSource + CHECKSUM_5752b26c + XGUI_VERSION_2 + + + + AXIS tMux for tProcessor, V1. + + + N + N + 2 + + + B + B + 16 + + + Component_Name + axis_tmux_v1_v1_0 + + + + + + zynquplus + + + /UserIP + + AXIS tMux V1 + package_project + 3 + 2024-08-05T21:30:41Z + + + 2022.1 + + + + + + + + diff --git a/firmware/ip/axis_tmux_v1/src/axis_tmux_v1.sv b/firmware/ip/axis_tmux_v1/src/axis_tmux_v1.sv new file mode 100644 index 0000000..0ee228b --- /dev/null +++ b/firmware/ip/axis_tmux_v1/src/axis_tmux_v1.sv @@ -0,0 +1,94 @@ +module axis_tmux_v1 + #( + // Number of outputs. + parameter N = 8, + + // Number of data bits. + parameter B = 16 + ) + ( + // Reset and clock. + input wire aresetn , + input wire aclk , + + // S_AXIS for input data. + output wire s_axis_tready , + input wire s_axis_tvalid , + input wire [B-1:0] s_axis_tdata , + + // M_AXIS for output data. + output wire m0_axis_tvalid , + output wire [B-1:0] m0_axis_tdata , + + output wire m1_axis_tvalid , + output wire [B-1:0] m1_axis_tdata , + + output wire m2_axis_tvalid , + output wire [B-1:0] m2_axis_tdata , + + output wire m3_axis_tvalid , + output wire [B-1:0] m3_axis_tdata , + + output wire m4_axis_tvalid , + output wire [B-1:0] m4_axis_tdata , + + output wire m5_axis_tvalid , + output wire [B-1:0] m5_axis_tdata , + + output wire m6_axis_tvalid , + output wire [B-1:0] m6_axis_tdata , + + output wire m7_axis_tvalid , + output wire [B-1:0] m7_axis_tdata + ); + +/**********************/ +/* Begin Architecture */ +/**********************/ +tmux + #( + // Number of outputs. + .N(N), + + // Number of data bits. + .B(B) + ) + tmux_i + ( + // Reset and clock. + .aresetn (aresetn ), + .aclk (aclk ), + + // S_AXIS for input data. + .s_axis_tready (s_axis_tready ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tdata (s_axis_tdata ), + + // M_AXIS for output data. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tdata (m0_axis_tdata ), + + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tdata (m1_axis_tdata ), + + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tdata (m2_axis_tdata ), + + .m3_axis_tvalid (m3_axis_tvalid ), + .m3_axis_tdata (m3_axis_tdata ), + + .m4_axis_tvalid (m4_axis_tvalid ), + .m4_axis_tdata (m4_axis_tdata ), + + .m5_axis_tvalid (m5_axis_tvalid ), + .m5_axis_tdata (m5_axis_tdata ), + + .m6_axis_tvalid (m6_axis_tvalid ), + .m6_axis_tdata (m6_axis_tdata ), + + .m7_axis_tvalid (m7_axis_tvalid ), + .m7_axis_tdata (m7_axis_tdata ) + ); + +endmodule + diff --git a/firmware/ip/axis_tmux_v1/src/tb.sv b/firmware/ip/axis_tmux_v1/src/tb.sv new file mode 100644 index 0000000..e07aa64 --- /dev/null +++ b/firmware/ip/axis_tmux_v1/src/tb.sv @@ -0,0 +1,150 @@ +module tb; + +// Number of outputs. +parameter N = 8 ; + +// Number of data bits. +parameter B = 32 ; + +// Reset and clock. +reg aresetn ; +reg aclk ; + +// S_AXIS for input data. +wire s_axis_tready ; +reg s_axis_tvalid ; +wire [B-1:0] s_axis_tdata ; + +// M_AXIS for output data. +wire m0_axis_tvalid ; +wire [B-1:0] m0_axis_tdata ; + +wire m1_axis_tvalid ; +wire [B-1:0] m1_axis_tdata ; + +wire m2_axis_tvalid ; +wire [B-1:0] m2_axis_tdata ; + +wire m3_axis_tvalid ; +wire [B-1:0] m3_axis_tdata ; + +wire m4_axis_tvalid ; +wire [B-1:0] m4_axis_tdata ; + +wire m5_axis_tvalid ; +wire [B-1:0] m5_axis_tdata ; + +wire m6_axis_tvalid ; +wire [B-1:0] m6_axis_tdata ; + +wire m7_axis_tvalid ; +wire [B-1:0] m7_axis_tdata ; + +// Sel/data. +reg [7:0] sel_r ; +reg [23:0] data_r ; + +// Input sel/data. +assign s_axis_tdata = {sel_r, data_r}; + +// DUT. +axis_tmux_v1 + #( + // Number of outputs. + .N(N), + + // Number of data bits. + .B(B) + ) + DUT + ( + // Reset and clock. + .aresetn , + .aclk , + + // S_AXIS for input data. + .s_axis_tready , + .s_axis_tvalid , + .s_axis_tdata , + + // M_AXIS for output data. + .m0_axis_tvalid , + .m0_axis_tdata , + + .m1_axis_tvalid , + .m1_axis_tdata , + + .m2_axis_tvalid , + .m2_axis_tdata , + + .m3_axis_tvalid , + .m3_axis_tdata , + + .m4_axis_tvalid , + .m4_axis_tdata , + + .m5_axis_tvalid , + .m5_axis_tdata , + + .m6_axis_tvalid , + .m6_axis_tdata , + + .m7_axis_tvalid , + .m7_axis_tdata + ); + +// Main TB. +initial begin + aresetn <= 0; + s_axis_tvalid <= 0; + sel_r <= 0; + data_r <= 0; + #300; + aresetn <= 1; + + #1000; + + for (int i=0; i + + user.org + user + axis_tproc64x32_x8 + 1.0 + + + m0_axis + + + + + + + TDATA + + + m0_axis_tdata + + + + + TLAST + + + m0_axis_tlast + + + + + TVALID + + + m0_axis_tvalid + + + + + TREADY + + + m0_axis_tready + + + + + + m1_axis + + + + + + + TDATA + + + m1_axis_tdata + + + + + TVALID + + + m1_axis_tvalid + + + + + TREADY + + + m1_axis_tready + + + + + + m2_axis + + + + + + + TDATA + + + m2_axis_tdata + + + + + TVALID + + + m2_axis_tvalid + + + + + TREADY + + + m2_axis_tready + + + + + + m3_axis + + + + + + + TDATA + + + m3_axis_tdata + + + + + TVALID + + + m3_axis_tvalid + + + + + TREADY + + + m3_axis_tready + + + + + + m4_axis + + + + + + + TDATA + + + m4_axis_tdata + + + + + TVALID + + + m4_axis_tvalid + + + + + TREADY + + + m4_axis_tready + + + + + + m5_axis + + + + + + + TDATA + + + m5_axis_tdata + + + + + TVALID + + + m5_axis_tvalid + + + + + TREADY + + + m5_axis_tready + + + + + + m6_axis + + + + + + + TDATA + + + m6_axis_tdata + + + + + TVALID + + + m6_axis_tvalid + + + + + TREADY + + + m6_axis_tready + + + + + + m7_axis + + + + + + + TDATA + + + m7_axis_tdata + + + + + TVALID + + + m7_axis_tvalid + + + + + TREADY + + + m7_axis_tready + + + + + + m8_axis + + + + + + + TDATA + + + m8_axis_tdata + + + + + TVALID + + + m8_axis_tvalid + + + + + TREADY + + + m8_axis_tready + + + + + + s0_axis + + + + + + + TDATA + + + s0_axis_tdata + + + + + TLAST + + + s0_axis_tlast + + + + + TVALID + + + s0_axis_tvalid + + + + + TREADY + + + s0_axis_tready + + + + + + s1_axis + + + + + + + TDATA + + + s1_axis_tdata + + + + + TVALID + + + s1_axis_tvalid + + + + + TREADY + + + s1_axis_tready + + + + + + s2_axis + + + + + + + TDATA + + + s2_axis_tdata + + + + + TVALID + + + s2_axis_tvalid + + + + + TREADY + + + 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vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/alu/math.vhd + vhdlSource + + + src/regfile/regfile.vhd + vhdlSource + + + src/regfile/regfile_8p.vhd + vhdlSource + + + src/s_axis_read.vhd + vhdlSource + + + src/stack.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/timed_ictrl.vhd + vhdlSource + + + src/axis_tproc64x32_x8.v + verilogSource + CHECKSUM_0fbcd688 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/alu/alu.v + verilogSource + + + src/data_mem/axis_read.v + verilogSource + + + src/data_mem/axis_write.v + verilogSource + + + src/data_mem/data_mem.v + verilogSource + + + src/data_mem/data_mem_ctrl.v + verilogSource + + + src/data_mem/mem_rw.v + verilogSource + + + src/tproc64x32_x8.v + verilogSource + + + src/axi_slv_custom.sv + systemVerilogSource + + + src/ctrl.sv + systemVerilogSource + + + src/alu/bitw.vhd + vhdlSource + + + src/bram.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/cond.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/alu/math.vhd + vhdlSource + + + src/regfile/regfile.vhd + vhdlSource + + + src/regfile/regfile_8p.vhd + vhdlSource + + + src/s_axis_read.vhd + vhdlSource + + + src/stack.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/timed_ictrl.vhd + vhdlSource + + + src/axis_tproc64x32_x8.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_tproc64x32_x8_v1_0.tcl + tclSource + CHECKSUM_9f9e4535 + XGUI_VERSION_2 + + + + AXIS tProcessor, 64-bit Instructions, 32-bit registers, 4 input channels, 8 output channels. + + + PMEM_N + Pmem N + 16 + + + DMEM_N + Dmem N + 10 + + + Component_Name + axis_tproc64x32_x8_v1_0 + + + + + + /UserIP + + AXIS tProcessor 64x32, 8 channels V1. + level_2 + package_project + 4 + 2023-08-08T16:38:04Z + + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + /home/lstefana/v19.1/ip/axis_tproc64x32_x8_v1 + + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/alu/alu.v b/firmware/ip/axis_tproc64x32_x8_v1/src/alu/alu.v new file mode 100644 index 0000000..490dced --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/alu/alu.v @@ -0,0 +1,140 @@ +// ALU block integrating math and bitw. +// +// 0000 : din_a and din_b +// 0001 : din_a or din_b +// 0010 : din_a xor din_b +// 0011 : not(din_a) +// 0100 : din_a << din_b +// 0101 : din_a >> din_b +// 1000 : din_a + din_b +// 1001 : din_a - din_b +// 1010 : din_a * din_b + +module alu + ( + // Clock and reset. + clk , + rstn , + + // Input operands. + din_a , + din_b , + + // Operation. + op , + + // Zero detection. + zero_a , + zero_b , + + // Output. + dout + ); + +// Data width. +parameter B = 16; + +// Ports. +input clk; +input rstn; + +input [B-1:0] din_a; +input [B-1:0] din_b; + +input [3:0] op; + +output zero_a; +output zero_b; + +output [B-1:0] dout; + +// Registers to account latency. +reg [3:0] op_r; +reg [3:0] op_rr; +reg [3:0] op_rrr; + +// Operation. +wire [3:0] oper_i; +wire sel; + +// Outputs. +wire [B-1:0] math_dout; +wire [B-1:0] bitw_dout; + +// Math block. +math + #( + // Data width. + .B(B) + ) + math_i + ( + // Clock and reset. + .clk (clk ), + .rstn (rstn ), + + // Input operands. + .din_a (din_a ), + .din_b (din_b ), + + // Operation. + .op (oper_i ), + + // Zero detection. + .zero_a (zero_a ), + .zero_b (zero_b ), + + // Output. + .dout (math_dout ) + ); + +// Bitw block. +bitw + #( + // Data width. + .B(B) + ) + bitw_i + ( + // Clock and reset. + .clk (clk ), + .rstn (rstn ), + + // Input operands. + .din_a (din_a ), + .din_b (din_b ), + + // Operation. + .op (oper_i ), + + // Output. + .dout (bitw_dout ) + ); + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // Registers to account latency. + op_r <= 0; + op_rr <= 0; + op_rrr <= 0; + + end else + // Registers to account latency. + op_r <= op; + op_rr <= op_r; + op_rrr <= op_rr; + begin + + end +end + +// Operation. +assign oper_i = {1'b0,op[2:0]}; +assign sel = op_rrr[3]; + +// Output mux. +assign dout = (sel == 0)? bitw_dout : math_dout; + +endmodule + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/alu/bitw.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/alu/bitw.vhd new file mode 100644 index 0000000..2487155 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/alu/bitw.vhd @@ -0,0 +1,135 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +-- Bit-wise operations block. + +-- It operates on two inputs. +-- Operations are: +-- 0000 : din_a and din_b +-- 0001 : din_a or din_b +-- 0010 : din_a xor din_b +-- 0011 : not(din_b) +-- 0100 : din_a << din_b +-- 0101 : din_a >> din_b +-- +-- Latency is 3 clocks. + +entity bitw is + Generic ( + -- Data width. + B : Integer := 16 + ); + Port ( + -- Clock and reset. + clk : in std_logic; + rstn : in std_logic; + + -- Input operands. + din_a : in std_logic_vector (B-1 downto 0); + din_b : in std_logic_vector (B-1 downto 0); + + -- Operation. + op : in std_logic_vector (3 downto 0); + + -- Output. + dout : out std_logic_vector (B-1 downto 0) + ); +end bitw; + +architecture rtl of bitw is + +-- Number of bits of B. +constant B_LOG2 : Integer := Integer(ceil(log2(real(B)))); + +-- Input registers. +signal din_a_r : std_logic_vector (B-1 downto 0); +signal din_b_r : std_logic_vector (B-1 downto 0); +signal op_r : std_logic_vector (3 downto 0); + +-- Operations. +signal and_i : std_logic_vector (B-1 downto 0); +signal or_i : std_logic_vector (B-1 downto 0); +signal xor_i : std_logic_vector (B-1 downto 0); +signal not_i : std_logic_vector (B-1 downto 0); + +-- Shift. +type vect_t is array (B-1 downto 0) of std_logic_vector (B-1 downto 0); +signal ls_i : vect_t; +signal rs_i : vect_t; +signal ls_mux : std_logic_vector (B-1 downto 0); +signal rs_mux : std_logic_vector (B-1 downto 0); +signal shift_n : unsigned(B_LOG2-1 downto 0); + +-- Output mux. +signal dout_mux : std_logic_vector (B-1 downto 0); +signal dout_r : std_logic_vector (B-1 downto 0); +signal dout_rr : std_logic_vector (B-1 downto 0); + +begin + +-- Registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + -- Input registers. + din_a_r <= (others => '0'); + din_b_r <= (others => '0'); + op_r <= (others => '0'); + + -- Output mux. + dout_r <= (others => '0'); + dout_rr <= (others => '0'); + else + -- Input registers. + din_a_r <= din_a; + din_b_r <= din_b; + op_r <= op; + + -- Output mux. + dout_r <= dout_mux; + dout_rr <= dout_r; + end if; + end if; +end process; + +-- Operations. +and_i <= din_a_r and din_b_r; +or_i <= din_a_r or din_b_r; +xor_i <= din_a_r xor din_b_r; +not_i <= not(din_b_r); + +-- Shift. +GEN_shift: for I in 0 to B-1 generate + -- Zeros for padding before/after. + signal zeros_tmp : std_logic_vector (I-1 downto 0) := (others => '0'); +begin + ls_i(I) <= din_a_r(B-I-1 downto 0) & zeros_tmp; + rs_i(I) <= zeros_tmp & din_a_r(B-1 downto I); +end generate GEN_shift; + +-- Left shift selection mux. +ls_mux <= ls_i(to_integer(shift_n)); + +-- Right shift selection mux. +rs_mux <= rs_i(to_integer(shift_n)); + +-- Shift amount. +shift_n <= unsigned(din_b(B_LOG2-1 downto 0)); + +-- Output mux. +dout_mux <= and_i when op_r = "0000" else + or_i when op_r = "0001" else + xor_i when op_r = "0010" else + not_i when op_r = "0011" else + ls_mux when op_r = "0100" else + rs_mux when op_r = "0101" else + (others => '0'); + +-- Assign outputs. +dout <= dout_rr; + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/alu/math.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/alu/math.vhd new file mode 100644 index 0000000..eeab7f8 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/alu/math.vhd @@ -0,0 +1,108 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Mathematical block. + +-- It operates on two inputs. +-- Operations are: +-- 0000 : din_a + din_b +-- 0001 : din_a - din_b +-- 0010 : din_a * din_b + +-- Product: takes B/2 lower bits from din_a and din_b. + +-- Zero detection does not have any latency. +-- Output latency is 3 clocks. + +entity math is + Generic ( + -- Data width. + B : Integer := 16 + ); + Port ( + -- Clock and reset. + clk : in std_logic; + rstn : in std_logic; + + -- Input operands. + din_a : in std_logic_vector (B-1 downto 0); + din_b : in std_logic_vector (B-1 downto 0); + + -- Operation. + op : in std_logic_vector (3 downto 0); + + -- Zero detection. + zero_a : out std_logic; + zero_b : out std_logic; + + -- Output. + dout : out std_logic_vector (B-1 downto 0) + ); +end math; + +architecture rtl of math is + +-- Input registers. +signal din_a_r : signed (B-1 downto 0); +signal din_b_r : signed (B-1 downto 0); +signal op_r : std_logic_vector (3 downto 0); + +-- Operations. +signal add_i : signed (B-1 downto 0); +signal sub_i : signed (B-1 downto 0); +signal prod_i : signed (B-1 downto 0); + +-- Muxed output. +signal dout_mux : std_logic_vector (B-1 downto 0); + +-- Output registers. +signal dout_r : std_logic_vector (B-1 downto 0); +signal dout_rr : std_logic_vector (B-1 downto 0); + +begin + +-- Registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + -- Input registers. + din_a_r <= (others => '0'); + din_b_r <= (others => '0'); + op_r <= (others => '0'); + + -- Output registers. + dout_r <= (others => '0'); + dout_rr <= (others => '0'); + else + -- Input registers. + din_a_r <= signed(din_a); + din_b_r <= signed(din_b); + op_r <= op; + + -- Output registers. + dout_r <= dout_mux; + dout_rr <= dout_r; + end if; + end if; +end process; + +-- Operations. +add_i <= din_a_r + din_b_r; +sub_i <= din_a_r - din_b_r; +prod_i <= din_a_r(B/2-1 downto 0)*din_b_r(B/2-1 downto 0); + +-- Muxed output. +dout_mux <= std_logic_vector(add_i) when op_r = "0000" else + std_logic_vector(sub_i) when op_r = "0001" else + std_logic_vector(prod_i)when op_r = "0010" else + (others => '0'); + +-- Assign outputs. +zero_a <= '1' when signed(din_a) = 0 else '0'; +zero_b <= '1' when signed(din_b) = 0 else '0'; +dout <= dout_rr; + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 0000000..5f33135 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 5 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 0000000..5c4d9a9 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,115 @@ +-- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 5 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..34f0b12 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,187 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + virtex7 + + + xc7vx485t + ffg1157 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.xml b/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.xml new file mode 100644 index 0000000..f2fccc7 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/axi_mst_0/axi_mst_0.xml @@ -0,0 +1,4751 @@ + + + xilinx.com + customized_ip + axi_mst_0 + 1.0 + + + M_AXI + + + + + + + + + ARADDR + + + m_axi_araddr + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARID + + + m_axi_arid + + + + + ARLEN + + + m_axi_arlen + + + + + ARLOCK + + + m_axi_arlock + + + + + ARPROT + + + m_axi_arprot + + + + + ARQOS + + + m_axi_arqos + + + + + ARREADY + + + m_axi_arready + + + + + ARREGION + + + m_axi_arregion + + + + + ARSIZE + + + m_axi_arsize + + + + + ARUSER + + + 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systemVerilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_5 + + + + xilinx_externalfiles_view_fileset + + axi_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axi_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axi_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axi_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_5 + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_5 + + + sysc/axi_vip.h + systemCSource + true + axi_vip_v1_1_5 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + + + AXI Verification IP + + xtlm + + 5 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.1 + + + + + + + + + + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/axi_slv_custom.sv b/firmware/ip/axis_tproc64x32_x8_v1/src/axi_slv_custom.sv new file mode 100644 index 0000000..9369730 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/axi_slv_custom.sv @@ -0,0 +1,434 @@ +// Custom axi-lite slave block with limited functionality: +// +// * Address map is DATA_WIDTH based, not byte based. +// * Strobe not implemented. Always full access. +// +// The slave supports a maximum of 16-bit address space. The lower portion +// is reserved for registers, the upper portion for external memory. +// Registers: 64 registers, 32-bit each (4 bytes), gives 256 bytes. +// +// AXI RRESP/BRESP: when the external memory arbiter is executing a stream +// operation, memory is busy and cannot be accesses with single read/write +// modes. In this case, the axi slave will return with an error code: +// RRESP/BRESP = 2'b10 (SLVERR, see AXI specification). +// +// In any other access, if the operation is executed properly, the axi slave +// block will return a OKAY standard code: +// RRESP/BRESP = 2'b00 (OKAY, see AXI specification). +// +// This allows to avoid dead-locks due to the bus already taken. +// +module axi_slv_custom ( + // Reset and clock. + aclk_i , + aresetn_i , + + // Write Address Channel. + awaddr_i , + awprot_i , + awvalid_i , + awready_o , + + // Write Data Channel. + wdata_i , + wstrb_i , + wvalid_i , + wready_o , + + // Write Response Channel. + bresp_o , + bvalid_o , + bready_i , + + // Read Address Channel. + araddr_i , + arprot_i , + arvalid_i , + arready_o , + + // Read Data Channel. + rdata_o , + rresp_o , + rvalid_o , + rready_i , + + // Single Access Handshake. + busy_i , + oper_o , + addr_o , + dwrite_o , + dread_i , + exec_o , + exec_ack_i , + + // Registers. + START_SRC_REG , + START_REG , + MEM_MODE_REG , + MEM_START_REG , + MEM_ADDR_REG , + MEM_LEN_REG +); + +// Parameters. +localparam DATA_WIDTH = 32; +localparam DATA_WIDTH_BYTE = DATA_WIDTH/8; +localparam DATA_WIDTH_BYTE_LOG2 = $clog2(DATA_WIDTH_BYTE); +localparam NREG = 64; +localparam NREG_BYTE = NREG*DATA_WIDTH_BYTE; + +// Ports. +input aclk_i; +input aresetn_i; + +input [31:0] awaddr_i; +input [2:0] awprot_i; +input awvalid_i; +output reg awready_o; + +input [DATA_WIDTH-1:0] wdata_i; +input [DATA_WIDTH/8-1:0] wstrb_i; +input wvalid_i; +output reg wready_o; + +output [1:0] bresp_o; +output reg bvalid_o; +input bready_i; + +input [31:0] araddr_i; +input [2:0] arprot_i; +input arvalid_i; +output reg arready_o; + +output [DATA_WIDTH-1:0] rdata_o; +output [1:0] rresp_o; +output reg rvalid_o; +input rready_i; + +input busy_i; +output reg oper_o; +output [31:0] addr_o; +output [DATA_WIDTH-1:0] dwrite_o; +input [DATA_WIDTH-1:0] dread_i; +output reg exec_o; +input exec_ack_i; + +output START_SRC_REG; +output START_REG; +output MEM_MODE_REG; +output MEM_START_REG; +output [31:0] MEM_ADDR_REG; +output [31:0] MEM_LEN_REG; + +// States. +typedef enum { INIT_ST , + AWADDR_ST , // Address Write State. + WDATA_ST , // Write Data State. + BRESP_ST , // Write Response State. + ARADDR_ST , // Address Read State. + RDATA_ST , // Read Data State. + REG_WR_ST , // Lower address, write internal register map. + MEM_WR_ST , // Higher address, write external memory. + REG_RD_ST , // Lower address, read internal register map. + MEM_RD_ST , // Higher address, read external memory. + WR_ACK_ST , // Wait acknowledge from single write access interface. + RD_ACK_ST , // Wait acknowledge from single read access interface. + BRESP_OK_ST , // Set BRESP OKAY response register. + BRESP_ERR_ST , // Set BRESP SLVERR response register. + RRESP_OK_ST , // Set RRESP OKAY response register. + RRESP_ERR_ST // Set RRESP SLVERR response register. + } state_t; + +(* fsm_encoding = "one_hot" *) state_t state; + +// Flags. +reg reg_rw; // 0: register read, 1: register write. +reg sel_int; // 0: register, 1: external memory. +reg data_en; // Enable data register. +reg addr_sel; // 0: awaddr, 1: araddr. + +// Address register. +reg [31:0] addr_r; +wire [31:0] addr_mux; + +// Output memory address computation. +wire [31:0] addr_out; + +// Data registers. +reg [DATA_WIDTH-1:0] wdata_r; +reg [DATA_WIDTH-1:0] data_r; +wire [DATA_WIDTH-1:0] data_mux; + +// Resp register. +reg [1:0] resp_r; +reg resp_en; +reg [1:0] resp_int; // 2'b00: OKAY, 2'b10: SLVERR. + +// Register map. +reg [DATA_WIDTH-1:0] reg0; +reg [DATA_WIDTH-1:0] reg1; +reg [DATA_WIDTH-1:0] reg2; +reg [DATA_WIDTH-1:0] reg3; +reg [DATA_WIDTH-1:0] reg4; +reg [DATA_WIDTH-1:0] reg5; +reg [DATA_WIDTH-1:0] reg6; +reg [DATA_WIDTH-1:0] reg7; +wire [DATA_WIDTH-1:0] reg_int; // Selected register. + +// Registers. +always @(posedge aclk_i) begin + if (~aresetn_i) begin + // State register. + state <= INIT_ST; + + // Address register. + addr_r <= 0; + + // Data registers. + wdata_r <= 0; + data_r <= 0; + + // Resp register. + resp_r <= 0; + + // Register map. + reg0 <= 0; + reg1 <= 0; + reg2 <= 0; + reg3 <= 0; + reg4 <= 0; + reg5 <= 0; + reg6 <= 0; + reg7 <= 0; + end + else begin + // State register. + case (state) + INIT_ST: + if (awvalid_i) + state <= AWADDR_ST; + else if (arvalid_i) + state <= ARADDR_ST; + + AWADDR_ST: + state <= WDATA_ST; + + WDATA_ST: + if (wvalid_i) + if (addr_r < NREG_BYTE) + // Lower address map, register write. + state <= REG_WR_ST; + else + // Higher address map, memory write. + if (busy_i) + state <= BRESP_ERR_ST; + else + state <= MEM_WR_ST; + + BRESP_ST: + if (bready_i) + state <= INIT_ST; + + ARADDR_ST: + if (araddr_i < NREG_BYTE) + // Lower address map, register read. + state <= REG_RD_ST; + else + // Higher address map, memory read. + if (busy_i) + state <= RRESP_ERR_ST; + else + state <= MEM_RD_ST; + + RDATA_ST: + if (rready_i) + state <= INIT_ST; + + REG_WR_ST: + state <= BRESP_OK_ST; + + MEM_WR_ST: + if (exec_ack_i) + state <= WR_ACK_ST; + + REG_RD_ST: + state <= RRESP_OK_ST; + + MEM_RD_ST: + if (exec_ack_i) + state <= RD_ACK_ST; + + WR_ACK_ST: + if (~exec_ack_i) + state <= BRESP_OK_ST; + + RD_ACK_ST: + if (~exec_ack_i) + state <= RRESP_OK_ST; + + BRESP_OK_ST: + state <= BRESP_ST; + + BRESP_ERR_ST: + state <= BRESP_ST; + + RRESP_OK_ST: + state <= RDATA_ST; + + RRESP_ERR_ST: + state <= RDATA_ST; + + endcase + + // Address register. + if ((awvalid_i && awready_o) || (arvalid_i && arready_o)) + addr_r <= addr_mux; + + // Data registers. + if (wvalid_i && wready_o) + wdata_r <= wdata_i; + + if (data_en) + data_r <= data_mux; + + // Resp register. + if (resp_en) + resp_r <= resp_int; + + // Register write. + if (reg_rw) + case (addr_r) + 0: reg0 <= wdata_r; + 4: reg1 <= wdata_r; + 8: reg2 <= wdata_r; + 12: reg3 <= wdata_r; + 16: reg4 <= wdata_r; + 20: reg5 <= wdata_r; + 24: reg6 <= wdata_r; + 28: reg7 <= wdata_r; + endcase + end +end + +// FSM outputs. +always_comb begin + // Default value. + awready_o = 0; + wready_o = 0; + bvalid_o = 0; + arready_o = 0; + rvalid_o = 0; + oper_o = 0; // 0: read, 1: write. + exec_o = 0; + reg_rw = 0; + sel_int = 0; + data_en = 0; + addr_sel = 0; + resp_en = 0; + resp_int = 0; + + case (state) + //INIT_ST: + + AWADDR_ST: begin + awready_o = 1; + addr_sel = 0; + end + + WDATA_ST: + wready_o = 1; + + BRESP_ST: + bvalid_o = 1; + + ARADDR_ST: begin + arready_o = 1; + addr_sel = 1; + end + + RDATA_ST: + rvalid_o = 1; + + REG_WR_ST: + reg_rw = 1; + + MEM_WR_ST: begin + oper_o = 1; + exec_o = 1; + end + + REG_RD_ST: begin + reg_rw = 0; + sel_int = 0; + data_en = 1; + end + + MEM_RD_ST: begin + oper_o = 0; + exec_o = 1; + sel_int = 1; + data_en = 1; + end + + //WR_ACK_ST: + + //RD_ACK_ST: + + BRESP_OK_ST: begin + resp_en = 1; + resp_int = 2'b00; + end + + BRESP_ERR_ST: begin + resp_en = 1; + resp_int = 2'b10; + end + + RRESP_OK_ST: begin + resp_en = 1; + resp_int = 2'b00; + end + + RRESP_ERR_ST: begin + resp_en = 1; + resp_int = 2'b10; + end + + endcase +end + +// Output memory address computation. +assign addr_out = addr_r - NREG_BYTE; + +// Address mux. +assign addr_mux = (addr_sel == 0)? awaddr_i : araddr_i; + +// Data mux. +assign data_mux = (sel_int == 0)? reg_int : dread_i; + +// Mux for register. +assign reg_int = (addr_r == 0)? reg0 : + (addr_r == 4)? reg1 : + (addr_r == 8)? reg2 : + (addr_r == 12)? reg3 : + (addr_r == 16)? reg4 : + (addr_r == 20)? reg5 : + (addr_r == 24)? reg6 : + (addr_r == 28)? reg7 : + 0; + +// Assign outputs. +assign bresp_o = resp_r; +assign rresp_o = resp_r; +assign rdata_o = data_r; +assign addr_o = addr_out[31:DATA_WIDTH_BYTE_LOG2]; // Byte to Sample-based. +assign dwrite_o = wdata_r; +assign START_SRC_REG = reg0[0]; +assign START_REG = reg1[0]; +assign MEM_MODE_REG = reg2[0]; +assign MEM_START_REG = reg3[0]; +assign MEM_ADDR_REG = reg4; +assign MEM_LEN_REG = reg5; + +endmodule + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.veo b/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.veo new file mode 100644 index 0000000..40fe937 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.veo @@ -0,0 +1,71 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi4stream_vip:1.1 +// IP Revision: 5 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axis_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axis_tvalid(m_axis_tvalid), // output wire [0 : 0] m_axis_tvalid + .m_axis_tready(m_axis_tready), // input wire [0 : 0] m_axis_tready + .m_axis_tdata(m_axis_tdata), // output wire [31 : 0] m_axis_tdata + .m_axis_tstrb(m_axis_tstrb), // output wire [3 : 0] m_axis_tstrb + .m_axis_tlast(m_axis_tlast) // output wire [0 : 0] m_axis_tlast +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axis_mst_0.v when simulating +// the core, axis_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.vho b/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.vho new file mode 100644 index 0000000..a9ea647 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.vho @@ -0,0 +1,87 @@ +-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi4stream_vip:1.1 +-- IP Revision: 5 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axis_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axis_tvalid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + m_axis_tready : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axis_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axis_tlast : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axis_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axis_tvalid => m_axis_tvalid, + m_axis_tready => m_axis_tready, + m_axis_tdata => m_axis_tdata, + m_axis_tstrb => m_axis_tstrb, + m_axis_tlast => m_axis_tlast + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axis_mst_0.vhd when simulating +-- the core, axis_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.xci b/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.xci new file mode 100644 index 0000000..4d57aef --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.xci @@ -0,0 +1,105 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axis_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 1 + 1 + 1 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 32 + 0 + 1 + 0 + 0 + 0b00000000000000000000000000010111 + 0 + 0 + axis_mst_0 + 0 + 1 + 0 + 1 + 1 + 1 + 0 + MASTER + 4 + 0 + 0 + 0 + 0 + virtex7 + + + xc7vx485t + ffg1157 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.xml b/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.xml new file mode 100644 index 0000000..6fbde64 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/axis_mst_0/axis_mst_0.xml @@ -0,0 +1,1548 @@ + + + xilinx.com + customized_ip + axis_mst_0 + 1.0 + + + M_AXIS + + + + + + + TDATA + + + m_axis_tdata + + + + + TDEST + + + m_axis_tdest + + + + + TID + + + m_axis_tid + + + + + TKEEP + + + m_axis_tkeep + + + + + TLAST + + + m_axis_tlast + + + + + TREADY + + + m_axis_tready + + + + + TSTRB + + + m_axis_tstrb + + + + + TUSER + + + m_axis_tuser + + + + + TVALID + + + m_axis_tvalid + + + + + + TDATA_NUM_BYTES + 4 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 1 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + true + + + + + + S_AXIS + + + + + + + TDATA + + + s_axis_tdata + + + + + TDEST + + + s_axis_tdest + + + + + TID + + + s_axis_tid + + + + + TKEEP + + + s_axis_tkeep + + + + + TLAST + + + s_axis_tlast + + + + + TREADY + + + s_axis_tready + + + + + TSTRB + + + s_axis_tstrb + + + + + TUSER + + + s_axis_tuser + + + + + TVALID + + + s_axis_tvalid + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + RESET + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + true + + + + + + ACLKEN + + + + + + + CE + + + aclken + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + + + + false + + + + + + CLOCK + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + M_AXIS:S_AXIS + + + ASSOCIATED_RESET + aresetn + + + FREQ_HZ + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog + + xilinx_veriloginstantiationtemplate_view_fileset + + + + GENtimestamp + Mon May 17 17:06:15 UTC 2021 + + + outputProductCRC + 9:570acbbb + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + axi4stream_vip_v1_1_5_top + + xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset + + + xilinx_verilogsynthesis_view_fileset + + + + GENtimestamp + Mon May 17 17:06:15 UTC 2021 + + + outputProductCRC + 9:570acbbb + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + xilinx_synthesisconstraints_view_fileset + + + + GENtimestamp + Mon May 17 17:06:15 UTC 2021 + + + outputProductCRC + 9:570acbbb + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + axis_mst_0 + + xilinx_verilogsynthesiswrapper_view_fileset + + + + GENtimestamp + Mon May 17 17:06:15 UTC 2021 + + + outputProductCRC + 9:570acbbb + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + axi4stream_vip_v1_1_5_top + + xilinx_versioninformation_view_fileset + + + + GENtimestamp + Mon May 17 17:06:15 UTC 2021 + + + outputProductCRC + 9:570acbbb + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Mon May 17 17:06:53 UTC 2021 + + + outputProductCRC + 9:570acbbb + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + axi4stream_vip_v1_1_5_top + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset + + + xilinx_verilogbehavioralsimulation_view_fileset + + + + GENtimestamp + Thu May 20 20:20:31 UTC 2021 + + + outputProductCRC + 9:f56db358 + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + axis_mst_0 + + xilinx_verilogsimulationwrapper_view_fileset + + + + GENtimestamp + Thu May 20 20:20:31 UTC 2021 + + + outputProductCRC + 9:f56db358 + + + + + + + aclk + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + aresetn + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 1 + + + + + + true + + + + + + aclken + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 1 + + + + + + false + + + + + + s_axis_tvalid + + in + + 0 + 0 + + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axis_tready + + out + + 0 + 0 + + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + s_axis_tdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axis_tstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axis_tkeep + + in + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + 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false + + + + + + + + C_AXI4STREAM_SIGNAL_SET + 0b00000000000000000000000000010111 + + + C_AXI4STREAM_INTERFACE_MODE + 0 + + + C_AXI4STREAM_DATA_WIDTH + 32 + + + C_AXI4STREAM_USER_BITS_PER_BYTE + 0 + + + C_AXI4STREAM_ID_WIDTH + 0 + + + C_AXI4STREAM_DEST_WIDTH + 0 + + + C_AXI4STREAM_USER_WIDTH + 0 + + + C_AXI4STREAM_HAS_ARESETN + 1 + + + + + + choice_list_642e7122 + MASTER + PASS_THROUGH + SLAVE + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_2d96f706 + 0 + 1 + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axis_mst_0.vho + vhdlTemplate + + + axis_mst_0.veo + verilogTemplate + + + + xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset + + hdl/axis_infrastructure_v1_1_0.vh + verilogSource + true + axis_infrastructure_v1_1_0 + + + hdl/axis_infrastructure_v1_1_vl_rfs.v + verilogSource + axis_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi4stream_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi4stream_vip_v1_1_5 + + + + xilinx_synthesisconstraints_view_fileset + + axis_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axis_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/axi4stream_vip_v1_1_changelog.txt + text + axi4stream_vip_v1_1_5 + + + + xilinx_externalfiles_view_fileset + + axis_mst_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axis_mst_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axis_mst_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axis_mst_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axis_mst_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset + + hdl/axis_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axis_infrastructure_v1_1_0 + + + hdl/axis_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axis_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axis_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi4stream_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi4stream_vip_v1_1_5 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axis_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + The AXI4-Stream Verification IP. + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + TDATA_NUM_BYTES + TDATA WIDTH(BYTES) + 4 + + + USER_BITS_PER_BYTE + TUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_TUSER_BITS_PER_BYTE + HAS TUSER_BITS_PER_BYTE + 0 + + + TID_WIDTH + TID WIDTH(BITS) + 0 + + + TDEST_WIDTH + TDEST WIDTH(BITS) + 0 + + + TUSER_WIDTH + TUSER WIDTH(BITS) + 0 + + + HAS_TREADY + ENABLE TREADY + 1 + + + HAS_TSTRB + ENABLE TSTRB + 1 + + + HAS_TKEEP + ENABLE TKEEP + 0 + + + HAS_TLAST + ENABLE TLAST + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + Component_Name + axis_mst_0 + + + + + AXI4-Stream Verification IP + + XPM_CDC + + 5 + true + + + + + + + + + + + + + + 2019.1 + + + + + + + + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.veo b/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.veo new file mode 100644 index 0000000..5072ea6 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.veo @@ -0,0 +1,71 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi4stream_vip:1.1 +// IP Revision: 5 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axis_slv_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .s_axis_tvalid(s_axis_tvalid), // input wire [0 : 0] s_axis_tvalid + .s_axis_tready(s_axis_tready), // output wire [0 : 0] s_axis_tready + .s_axis_tdata(s_axis_tdata), // input wire [31 : 0] s_axis_tdata + .s_axis_tstrb(s_axis_tstrb), // input wire [3 : 0] s_axis_tstrb + .s_axis_tlast(s_axis_tlast) // input wire [0 : 0] s_axis_tlast +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axis_slv_0.v when simulating +// the core, axis_slv_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.vho b/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.vho new file mode 100644 index 0000000..b633a5a --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.vho @@ -0,0 +1,87 @@ +-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi4stream_vip:1.1 +-- IP Revision: 5 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axis_slv_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + s_axis_tvalid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_tready : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axis_tstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axis_tlast : IN STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axis_slv_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + s_axis_tvalid => s_axis_tvalid, + s_axis_tready => s_axis_tready, + s_axis_tdata => s_axis_tdata, + s_axis_tstrb => s_axis_tstrb, + s_axis_tlast => s_axis_tlast + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axis_slv_0.vhd when simulating +-- the core, axis_slv_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.xci b/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.xci new file mode 100644 index 0000000..6c4cc2c --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.xci @@ -0,0 +1,105 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axis_slv_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 1 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + 32 + 0 + 1 + 0 + 2 + 0b00000000000000000000000000010111 + 0 + 0 + axis_slv_0 + 0 + 1 + 0 + 1 + 1 + 1 + 0 + SLAVE + 4 + 0 + 0 + 0 + 0 + virtex7 + + + xc7vx485t + ffg1157 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.xml b/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.xml new file mode 100644 index 0000000..323d46d --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/axis_slv_0/axis_slv_0.xml @@ -0,0 +1,1548 @@ + + + xilinx.com + customized_ip + axis_slv_0 + 1.0 + + + M_AXIS + + + + + + + TDATA + + + m_axis_tdata + + + + + TDEST + + + m_axis_tdest + + + + + TID + + + m_axis_tid + + + + + TKEEP + + + m_axis_tkeep + + + + + TLAST + + + m_axis_tlast + + + + + TREADY + + + m_axis_tready + + + + + TSTRB + + + m_axis_tstrb + + + + + TUSER + + + m_axis_tuser + + + + + TVALID + + + m_axis_tvalid + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + S_AXIS + + + + + + + TDATA + + + s_axis_tdata + + + + + TDEST + + + s_axis_tdest + + + + + TID + + + s_axis_tid + + + + + TKEEP + + + s_axis_tkeep + + + + + TLAST + + + s_axis_tlast + + + + + TREADY + + + s_axis_tready + + + + + TSTRB + + + s_axis_tstrb + + + + + TUSER + + + s_axis_tuser + + + + + TVALID + + + s_axis_tvalid + + + + + + TDATA_NUM_BYTES + 4 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 1 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + true + + + + + + RESET + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + true + + + + + + ACLKEN + + + + + + + CE + + + aclken + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + + + + false + + + + + + CLOCK + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + M_AXIS:S_AXIS + + + ASSOCIATED_RESET + aresetn + + + FREQ_HZ + 100000000 + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog + + xilinx_veriloginstantiationtemplate_view_fileset + + + + GENtimestamp + Mon May 17 17:06:36 UTC 2021 + + + outputProductCRC + 9:85eb7414 + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + axi4stream_vip_v1_1_5_top + + xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset + + + xilinx_verilogsynthesis_view_fileset + + + + GENtimestamp + Mon May 17 17:06:36 UTC 2021 + + + outputProductCRC + 9:85eb7414 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + xilinx_synthesisconstraints_view_fileset + + + + GENtimestamp + Mon May 17 17:06:36 UTC 2021 + + + outputProductCRC + 9:85eb7414 + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + axis_slv_0 + + xilinx_verilogsynthesiswrapper_view_fileset + + + + GENtimestamp + Mon May 17 17:06:36 UTC 2021 + + + outputProductCRC + 9:85eb7414 + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + axi4stream_vip_v1_1_5_top + + xilinx_versioninformation_view_fileset + + + + GENtimestamp + Mon May 17 17:06:36 UTC 2021 + + + outputProductCRC + 9:85eb7414 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Mon May 17 17:07:13 UTC 2021 + + + outputProductCRC + 9:85eb7414 + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + axi4stream_vip_v1_1_5_top + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset + + + xilinx_verilogbehavioralsimulation_view_fileset + + + + GENtimestamp + Thu May 20 20:20:30 UTC 2021 + + + outputProductCRC + 9:20954771 + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + axis_slv_0 + + xilinx_verilogsimulationwrapper_view_fileset + + + + GENtimestamp + Thu May 20 20:20:30 UTC 2021 + + + outputProductCRC + 9:20954771 + + + + + + + aclk + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + aresetn + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 1 + + + + + + true + + + + + + aclken + + in + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 1 + + + + + + false + + + + + + s_axis_tvalid + + in + + 0 + 0 + + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axis_tready + + out + + 0 + 0 + + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + s_axis_tdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axis_tstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axis_tkeep + + in + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axis_tlast + + in + + 0 + 0 + + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axis_tid + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axis_tdest + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axis_tuser + + in + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axis_tvalid + + out + + 0 + 0 + + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axis_tready + + in + + 0 + 0 + + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axis_tstrb + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0xF + + + + + + false + + + + + + m_axis_tkeep + + out + + 3 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axis_tlast + + out + + 0 + 0 + + + + std_logic + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axis_tid + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axis_tdest + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axis_tuser + + out + + 0 + 0 + + + + std_logic_vector + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + + + C_AXI4STREAM_SIGNAL_SET + 0b00000000000000000000000000010111 + + + C_AXI4STREAM_INTERFACE_MODE + 2 + + + C_AXI4STREAM_DATA_WIDTH + 32 + + + C_AXI4STREAM_USER_BITS_PER_BYTE + 0 + + + C_AXI4STREAM_ID_WIDTH + 0 + + + C_AXI4STREAM_DEST_WIDTH + 0 + + + C_AXI4STREAM_USER_WIDTH + 0 + + + C_AXI4STREAM_HAS_ARESETN + 1 + + + + + + choice_list_642e7122 + MASTER + PASS_THROUGH + SLAVE + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_2d96f706 + 0 + 1 + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axis_slv_0.vho + vhdlTemplate + + + axis_slv_0.veo + verilogTemplate + + + + xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset + + hdl/axis_infrastructure_v1_1_0.vh + verilogSource + true + axis_infrastructure_v1_1_0 + + + hdl/axis_infrastructure_v1_1_vl_rfs.v + verilogSource + axis_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi4stream_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi4stream_vip_v1_1_5 + + + + xilinx_synthesisconstraints_view_fileset + + axis_slv_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axis_slv_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/axi4stream_vip_v1_1_changelog.txt + text + axi4stream_vip_v1_1_5 + + + + xilinx_externalfiles_view_fileset + + axis_slv_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + axis_slv_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axis_slv_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + axis_slv_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + axis_slv_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset + + hdl/axis_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axis_infrastructure_v1_1_0 + + + hdl/axis_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axis_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axis_slv_0_pkg.sv + systemVerilogSource + + + hdl/axi4stream_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi4stream_vip_v1_1_5 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axis_slv_0.sv + systemVerilogSource + xil_defaultlib + + + + The AXI4-Stream Verification IP. + + + INTERFACE_MODE + INTERFACE MODE + SLAVE + + + TDATA_NUM_BYTES + TDATA WIDTH(BYTES) + 4 + + + USER_BITS_PER_BYTE + TUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_TUSER_BITS_PER_BYTE + HAS TUSER_BITS_PER_BYTE + 0 + + + TID_WIDTH + TID WIDTH(BITS) + 0 + + + TDEST_WIDTH + TDEST WIDTH(BITS) + 0 + + + TUSER_WIDTH + TUSER WIDTH(BITS) + 0 + + + HAS_TREADY + ENABLE TREADY + 1 + + + HAS_TSTRB + ENABLE TSTRB + 1 + + + HAS_TKEEP + ENABLE TKEEP + 0 + + + HAS_TLAST + ENABLE TLAST + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + Component_Name + axis_slv_0 + + + + + AXI4-Stream Verification IP + + XPM_CDC + + 5 + true + + + + + + + + + + + + + + 2019.1 + + + + + + + + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/axis_tproc64x32_x8.v b/firmware/ip/axis_tproc64x32_x8_v1/src/axis_tproc64x32_x8.v new file mode 100644 index 0000000..d6e10e6 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/axis_tproc64x32_x8.v @@ -0,0 +1,482 @@ +module axis_tproc64x32_x8 +( + /////////////////////// + // s_axi_aclk domain // + /////////////////////// + s_axi_aclk , + s_axi_aresetn , + + // AXI Slave I/F for configuration. + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // Slave AXIS for writing into Data Memory. + s0_axis_aclk , // For IF only, not connected. + s0_axis_aresetn , // For IF only, not connected. + s0_axis_tdata , + s0_axis_tlast , + s0_axis_tvalid , + s0_axis_tready , + + // Master AXIS 0 to read from Data Memory. + m0_axis_aclk , // For IF only, not connected. + m0_axis_aresetn , // For IF only, not connected. + m0_axis_tdata , + m0_axis_tlast , + m0_axis_tvalid , + m0_axis_tready , + + ///////////////// + // aclk domain // + ///////////////// + aclk , + aresetn , + + // Start/stop. + start , + + // Program Memory Interface. + pmem_addr , + pmem_do , + + // Slave AXIS 0: "read" on tProcessor. + s1_axis_tdata , + s1_axis_tvalid , + s1_axis_tready , + + // Slave AXIS 1: "read" on tProcessor. + s2_axis_tdata , + s2_axis_tvalid , + s2_axis_tready , + + // Slave AXIS 2: "read" on tProcessor. + s3_axis_tdata , + s3_axis_tvalid , + s3_axis_tready , + + // Slave AXIS 3: "read" on tProcessor. + s4_axis_tdata , + s4_axis_tvalid , + s4_axis_tready , + + // Master AXIS 1 for Channel 0. + m1_axis_tdata , + m1_axis_tvalid , + m1_axis_tready , + + // Master AXIS 2 for Channel 1. + m2_axis_tdata , + m2_axis_tvalid , + m2_axis_tready , + + // Master AXIS 3 for Channel 2. + m3_axis_tdata , + m3_axis_tvalid , + m3_axis_tready , + + // Master AXIS 4 for Channel 3. + m4_axis_tdata , + m4_axis_tvalid , + m4_axis_tready , + + // Master AXIS 5 for Channel 4. + m5_axis_tdata , + m5_axis_tvalid , + m5_axis_tready , + + // Master AXIS 6 for Channel 5. + m6_axis_tdata , + m6_axis_tvalid , + m6_axis_tready , + + // Master AXIS 7 for Channel 6. + m7_axis_tdata , + m7_axis_tvalid , + m7_axis_tready , + + // Master AXIS 8 for Channel 7. + m8_axis_tdata , + m8_axis_tvalid , + m8_axis_tready + +); + +// Parameters. +parameter PMEM_N = 16; // Program Memory Depth. +parameter DMEM_N = 10; // Data Memory Depth. + +// Ports. +input s_axi_aclk; +input s_axi_aresetn; +input s0_axis_aclk; +input s0_axis_aresetn; +input m0_axis_aclk; +input m0_axis_aresetn; + +input [31:0] s_axi_awaddr; +input [2:0] s_axi_awprot; +input s_axi_awvalid; +output s_axi_awready; + +input [31:0] s_axi_wdata; +input [3:0] s_axi_wstrb; +input s_axi_wvalid; +output s_axi_wready; + +output [1:0] s_axi_bresp; +output s_axi_bvalid; +input s_axi_bready; + +input [31:0] s_axi_araddr; +input [2:0] s_axi_arprot; +input s_axi_arvalid; +output s_axi_arready; + +output [31:0] s_axi_rdata; +output [1:0] s_axi_rresp; +output s_axi_rvalid; +input s_axi_rready; + +input [31:0] s0_axis_tdata; +input s0_axis_tlast; +input s0_axis_tvalid; +output s0_axis_tready; + +output [31:0] m0_axis_tdata; +output m0_axis_tlast; +output m0_axis_tvalid; +input m0_axis_tready; + +input aclk; +input aresetn; + +input start; + +output [PMEM_N-1:0] pmem_addr; +input [63:0] pmem_do; + +input [63:0] s1_axis_tdata; +input s1_axis_tvalid; +output s1_axis_tready; + +input [63:0] s2_axis_tdata; +input s2_axis_tvalid; +output s2_axis_tready; + +input [63:0] s3_axis_tdata; +input s3_axis_tvalid; +output s3_axis_tready; + +input [63:0] s4_axis_tdata; +input s4_axis_tvalid; +output s4_axis_tready; + +output [159:0] m1_axis_tdata; +output m1_axis_tvalid; +input m1_axis_tready; + +output [159:0] m2_axis_tdata; +output m2_axis_tvalid; +input m2_axis_tready; + +output [159:0] m3_axis_tdata; +output m3_axis_tvalid; +input m3_axis_tready; + +output [159:0] m4_axis_tdata; +output m4_axis_tvalid; +input m4_axis_tready; + +output [159:0] m5_axis_tdata; +output m5_axis_tvalid; +input m5_axis_tready; + +output [159:0] m6_axis_tdata; +output m6_axis_tvalid; +input m6_axis_tready; + +output [159:0] m7_axis_tdata; +output m7_axis_tvalid; +input m7_axis_tready; + +output [159:0] m8_axis_tdata; +output m8_axis_tvalid; +input m8_axis_tready; + +// Internal connections. +// Program memory address. +wire [PMEM_N-1:0] pmem_addr_int; + +// axi_slv_custom -> data_mem +wire busy_int; +wire oper_int; +wire [DMEM_N-1:0] addr_int; +wire [31:0] dwrite_int; +wire [31:0] dread_int; +wire exec_int; +wire exec_ack_int; + +// data_mem -> dmem (port a). +wire dmem_wea; +wire [DMEM_N-1:0] dmem_addra; +wire [31:0] dmem_dia; +wire [31:0] dmem_doa; + +// tProc -> dmem (port b). +wire dmem_web; +wire [DMEM_N-1:0] dmem_addrb; +wire [31:0] dmem_dib; +wire [31:0] dmem_dob; + +// Registers. +wire START_SRC_REG; +wire START_REG; +wire MEM_MODE_REG; +wire MEM_START_REG; +wire [DMEM_N-1:0] MEM_ADDR_REG; +wire [DMEM_N-1:0] MEM_LEN_REG; + +// AXI Slave. +axi_slv_custom + axi_slv_i + ( + // Reset and clock. + .aclk_i (s_axi_aclk ), + .aresetn_i (s_axi_aresetn ), + + // Write Address Channel. + .awaddr_i (s_axi_awaddr ), + .awprot_i (s_axi_awprot ), + .awvalid_i (s_axi_awvalid ), + .awready_o (s_axi_awready ), + + // Write Data Channel. + .wdata_i (s_axi_wdata ), + .wstrb_i (s_axi_wstrb ), + .wvalid_i (s_axi_wvalid ), + .wready_o (s_axi_wready ), + + // Write Response Channel. + .bresp_o (s_axi_bresp ), + .bvalid_o (s_axi_bvalid ), + .bready_i (s_axi_bready ), + + // Read Address Channel. + .araddr_i (s_axi_araddr ), + .arprot_i (s_axi_arprot ), + .arvalid_i (s_axi_arvalid ), + .arready_o (s_axi_arready ), + + // Read Data Channel. + .rdata_o (s_axi_rdata ), + .rresp_o (s_axi_rresp ), + .rvalid_o (s_axi_rvalid ), + .rready_i (s_axi_rready ), + + // Single Access Handshake. + .busy_i (busy_int ), + .oper_o (oper_int ), + .addr_o (addr_int ), + .dwrite_o (dwrite_int ), + .dread_i (dread_int ), + .exec_o (exec_int ), + .exec_ack_i (exec_ack_int ), + + // Registers. + .START_SRC_REG (START_SRC_REG ), + .START_REG (START_REG ), + .MEM_MODE_REG (MEM_MODE_REG ), + .MEM_START_REG (MEM_START_REG ), + .MEM_ADDR_REG (MEM_ADDR_REG ), + .MEM_LEN_REG (MEM_LEN_REG ) +); + +// Data Memory arbiter. +data_mem + #( + .N (DMEM_N ), + .B (32 ) + ) + data_mem_i + ( + // Reset and clock. + .aclk_i (s_axi_aclk ), + .aresetn_i (s_axi_aresetn ), + + // Single Access Handshake. + .busy_o (busy_int ), + .oper_i (oper_int ), + .addr_i (addr_int ), + .din_i (dwrite_int ), + .dout_o (dread_int ), + .exec_i (exec_int ), + .exec_ack_o (exec_ack_int ), + + // Memory interface. + .mem_we_o (dmem_wea ), + .mem_di_o (dmem_dia ), + .mem_do_i (dmem_doa ), + .mem_addr_o (dmem_addra ), + + // AXIS Slave for receiving data. + .s_axis_tdata_i (s0_axis_tdata ), + .s_axis_tlast_i (s0_axis_tlast ), + .s_axis_tvalid_i (s0_axis_tvalid ), + .s_axis_tready_o (s0_axis_tready ), + + // AXIS Master for sending data. + .m_axis_tdata_o (m0_axis_tdata ), + .m_axis_tlast_o (m0_axis_tlast ), + .m_axis_tvalid_o (m0_axis_tvalid ), + .m_axis_tready_i (m0_axis_tready ), + + // Registers. + .MODE_REG (MEM_MODE_REG ), + .START_REG (MEM_START_REG ), + .ADDR_REG (MEM_ADDR_REG ), + .LEN_REG (MEM_LEN_REG ) +); + +// Data memory. +bram_dp + #( + // Memory address size. + .N (DMEM_N ), + // Data width. + .B (32 ) + ) + dmem_i + ( + .clka (s_axi_aclk ), + .clkb (aclk ), + .ena (1'b1 ), + .enb (1'b1 ), + .wea (dmem_wea ), + .web (dmem_web ), + .addra (dmem_addra ), + .addrb (dmem_addrb ), + .dia (dmem_dia ), + .dib (dmem_dib ), + .doa (dmem_doa ), + .dob (dmem_dob ) + ); + +// tProcessor: 64-bit, 32-bit registers, 8 channels. +tproc64x32_x8 + #( + // Program memory depth. + .N (PMEM_N ), + + // Data memory depth. + .M (DMEM_N ) + ) + tproc_i + ( + // Clock and reset. + .clk (aclk ), + .rstn (aresetn ), + + // Start/stop. + .start (start ), + + // Program Memory Interface. + .pmem_addr (pmem_addr_int ), + .pmem_do (pmem_do ), + + // Data Memory Interface. + .dmem_we (dmem_web ), + .dmem_addr (dmem_addrb ), + .dmem_di (dmem_dib ), + .dmem_do (dmem_dob ), + + // Slave AXIS 0 for Input data. + .s0_axis_tdata (s1_axis_tdata ), + .s0_axis_tvalid (s1_axis_tvalid ), + .s0_axis_tready (s1_axis_tready ), + + // Slave AXIS 1 for Input data. + .s1_axis_tdata (s2_axis_tdata ), + .s1_axis_tvalid (s2_axis_tvalid ), + .s1_axis_tready (s2_axis_tready ), + + // Slave AXIS 2 for Input data. + .s2_axis_tdata (s3_axis_tdata ), + .s2_axis_tvalid (s3_axis_tvalid ), + .s2_axis_tready (s3_axis_tready ), + + // Slave AXIS 3 for Input data. + .s3_axis_tdata (s4_axis_tdata ), + .s3_axis_tvalid (s4_axis_tvalid ), + .s3_axis_tready (s4_axis_tready ), + + // Master AXIS 0 for Output data. + .m0_axis_tdata (m1_axis_tdata ), + .m0_axis_tvalid (m1_axis_tvalid ), + .m0_axis_tready (m1_axis_tready ), + + // Master AXIS 1 for Output data. + .m1_axis_tdata (m2_axis_tdata ), + .m1_axis_tvalid (m2_axis_tvalid ), + .m1_axis_tready (m2_axis_tready ), + + // Master AXIS 2 for Output data. + .m2_axis_tdata (m3_axis_tdata ), + .m2_axis_tvalid (m3_axis_tvalid ), + .m2_axis_tready (m3_axis_tready ), + + // Master AXIS 3 for Output data. + .m3_axis_tdata (m4_axis_tdata ), + .m3_axis_tvalid (m4_axis_tvalid ), + .m3_axis_tready (m4_axis_tready ), + + // Master AXIS 4 for Output data. + .m4_axis_tdata (m5_axis_tdata ), + .m4_axis_tvalid (m5_axis_tvalid ), + .m4_axis_tready (m5_axis_tready ), + + // Master AXIS 5 for Output data. + .m5_axis_tdata (m6_axis_tdata ), + .m5_axis_tvalid (m6_axis_tvalid ), + .m5_axis_tready (m6_axis_tready ), + + // Master AXIS 6 for Output data. + .m6_axis_tdata (m7_axis_tdata ), + .m6_axis_tvalid (m7_axis_tvalid ), + .m6_axis_tready (m7_axis_tready ), + + // Master AXIS 7 for Output data. + .m7_axis_tdata (m8_axis_tdata ), + .m7_axis_tvalid (m8_axis_tvalid ), + .m7_axis_tready (m8_axis_tready ), + + // Registers. + .START_SRC_REG (START_SRC_REG ), + .START_REG (START_REG ) +); + +// Assign outputs. +assign pmem_addr = {pmem_addr_int[PMEM_N-4:0],3'b000}; // Multiply address by 8 to convert 64-bit address to 8-bit address. + +endmodule + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/bram.v b/firmware/ip/axis_tproc64x32_x8_v1/src/bram.v new file mode 100644 index 0000000..018317e --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/bram.v @@ -0,0 +1,33 @@ +module bram (clk,ena,wea,addra,dia,doa); + +// Memory address size. +parameter N = 16; +// Data width. +parameter B = 16; + +input clk; +input ena; +input wea; +input [N-1:0] addra; +input [B-1:0] dia; +output [B-1:0] doa; + +// Ram type. +reg [B-1:0] RAM [0:2**N-1]; +reg [B-1:0] doa; + +always @(posedge clk) +begin + if (ena) + begin + if (wea) begin + RAM[addra] <= dia; + end + else begin + doa <= RAM[addra]; + end + end +end + +endmodule + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/bram.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/bram.vhd new file mode 100644 index 0000000..c03c6c3 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/bram.vhd @@ -0,0 +1,51 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity bram is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in std_logic; + ena : in std_logic; + wea : in std_logic; + addra : in std_logic_vector (N-1 downto 0); + dia : in std_logic_vector (B-1 downto 0); + doa : out std_logic_vector (B-1 downto 0) + ); +end bram; + +architecture rtl of bram is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/cond.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/cond.vhd new file mode 100644 index 0000000..5804663 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/cond.vhd @@ -0,0 +1,94 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Conditional block. + +-- It operates on two inputs. +-- Operations are: +-- 0000 : din_a > din_b +-- 0001 : din_a >= din_b +-- 0010 : din_a < din_b +-- 0011 : din_a <= din_b +-- 0100 : din_a == din_b +-- 0101 : din_a != din_b + +-- Output flag is 1 when condition is true. Otherwise is 0. +-- Latency is 1 clock. + +entity cond is + Generic ( + -- Data width. + B : Integer := 16 + ); + Port ( + -- Clock and reset. + clk : in std_logic; + rstn : in std_logic; + + -- Input operands. + din_a : in std_logic_vector (B-1 downto 0); + din_b : in std_logic_vector (B-1 downto 0); + + -- Operation. + op : in std_logic_vector (3 downto 0); + + -- Flag. + flag : out std_logic + ); +end cond; + +architecture rtl of cond is + +-- Input registers. +signal din_a_r : signed (B-1 downto 0); +signal din_b_r : signed (B-1 downto 0); +signal op_r : std_logic_vector (3 downto 0); + +-- Flags for conditions. +signal cond_0_i : std_logic; -- > +signal cond_1_i : std_logic; -- >= +signal cond_2_i : std_logic; -- < +signal cond_3_i : std_logic; -- <= +signal cond_4_i : std_logic; -- == +signal cond_5_i : std_logic; -- != + +begin + +-- Registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + -- Input registers. + din_a_r <= (others => '0'); + din_b_r <= (others => '0'); + op_r <= (others => '0'); + else + -- Input registers. + din_a_r <= signed(din_a); + din_b_r <= signed(din_b); + op_r <= op; + end if; + end if; +end process; + +-- Flags for conditions. +cond_0_i <= '1' when din_a_r > din_b_r else '0' ; -- > +cond_1_i <= cond_0_i or cond_4_i ; -- >= +cond_2_i <= '1' when din_a_r < din_b_r else '0' ; -- < +cond_3_i <= cond_2_i or cond_4_i ; -- <= +cond_4_i <= '1' when din_a_r = din_b_r else '0' ; -- == +cond_5_i <= not(cond_4_i) ; -- != + +-- Mux for output. +flag <= cond_0_i when op_r = "0000" else + cond_1_i when op_r = "0001" else + cond_2_i when op_r = "0010" else + cond_3_i when op_r = "0011" else + cond_4_i when op_r = "0100" else + cond_5_i when op_r = "0101" else + '0'; + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/ctrl.sv b/firmware/ip/axis_tproc64x32_x8_v1/src/ctrl.sv new file mode 100644 index 0000000..b07dee5 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/ctrl.sv @@ -0,0 +1,1093 @@ +/* tProcessor control state machine. +This version works with 32-bit registers. To avoid modifying the whole instruction structure, +immediate value from instruction is 31 bits. It's sign-extended to get the 32-bit register +value before operating with it. It applies to I-Type instructions only. +*/ +// +// Instructions: +// +// ############## +// ### I-Type ### +// ############## +// +// I-Type: immediate type. Three registers and an immediate value. +// +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | opcode | page | channel | oper | ra | rb | rc | imm | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// +// pushi p, $ra, $rb, imm : push the content of register $ra into the stack. Load register +// $rb with imm value. Registers $ra and $rb can be the same. $p indicates the page of the +// regfile. +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 00010000 | page | xxxxxxx | xxxx | rb | ra | xx | imm | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// +// popi $p, $r : pop the content of the stack into register $r. +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 00010001 | page | xxxxxxx | xxxx | r | xx | xx | xxx | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// +// mathi $p, $ra, $rb oper imm : operation as $ra = $rb oper imm. +// oper : +// 1000 : $rb + imm +// 1001 : $rb - imm +// 1010 : $rb * imm +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 00010010 | page | xxxxxxx | oper | ra | rb | xx | imm | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// +// seti ch, p, $r, t : set value on register $r at time t for channel ch. +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 00010011 | page | channel | xxxx | xx | r | xx | t | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// +// synci t : sync master clock to t for upcoming instructions. +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 00010100 | xxxx | xxxxxxx | xxxx | xx | xx | xx | t | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// +// waiti ch, t : wait until master clock = t on channel ch. +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 00010101 | xxxx | channel | xxxx | xx | xx | xx | t | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// +// bitwi p, $ra, $rb oper imm : perform the bit-wise operation $rb oper imm and write the result +// into register $ra. +// oper : +// 0000 : $rb & imm (and) +// 0001 : $rb | imm (or) +// 0010 : $rb ^ imm (xor) +// 0011 : ~imm (not) +// 0100 : $rb << imm (left shift) +// 0101 : $rb >> imm (right shift) +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 00010110 | page | xxxxxxx | oper | ra | rb | xx | imm | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// +// NOTE: the not operation operates on a single operand. The syntax is slightly different: +// bitwi p, $ra, ~imm +// +// memri p, $r, imm : read memory at address imm and write value into register: $r = mem[imm]. +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 00010111 | page | xxxxxxx | xxxx | r | xx | xx | imm | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// +// memwi p, $r, imm : write register contents into address imm of memory: mem[imm] = $r. +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 00011000 | page | xxxxxxx | xxxx | xx | xx | r | imm | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// +// regwi p, $r, imm : write imm value into register. +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 00011001 | page | xxxxxxx | xxxx | r | xx | xx | imm | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// +// setbi ch, p, $r, t : set value on register $r at time t for channel ch (blocking). +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// | 00011010 | page | channel | xxxx | xx | r | xx | t | +// |----------|----------|----------|----------|----------|----------|----------|---------| +// +// ############## +// ### J-Type ### +// ############## +// +// J-Type: jump type. Three registers and an address for jump. +// +// |----------|----------|----------|----------|----------|----------|----------|----------|---------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 16 | 15 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|----------|---------| +// | opcode | page | xxxxxxx | oper | ra | rb | rc | xxx | addr | +// |----------|----------|----------|----------|----------|----------|----------|----------|---------| +// +// loopnz $p, $r, addr : jump to address addr if $r is not equal to zero and decrement register. +// If $r is equal to zero, continue with next instruction. +// |----------|----------|----------|----------|----------|----------|----------|----------|---------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 16 | 15 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|----------|---------| +// | 00110000 | page | xxxxxxx | 1000 | r | r | xx | xxx | addr | +// |----------|----------|----------|----------|----------|----------|----------|----------|---------| +// +// condj p, $ra oper $rb, @label : jump to address @label if condition is true. Operation is defined as: +// oper : +// 0000 : $ra > $rb +// 0001 : $ra >= $rb +// 0010 : $ra < $rb +// 0011 : $ra <= $rb +// 0100 : $ra == $rb +// 0101 : $ra != $rb +// |----------|----------|----------|----------|----------|----------|----------|----------|---------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 16 | 15 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|----------|---------| +// | 00110001 | page | xxxxxxx | oper | xx | ra | rb | xxx | addr | +// |----------|----------|----------|----------|----------|----------|----------|----------|---------| +// +// end : jump to END_ST to finish the execution of the program. +// |----------|----------|----------|----------|----------|----------|----------|----------|---------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 16 | 15 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|----------|---------| +// | 00111111 | xxxx | xxxxxxx | xxxx | xx | xx | xx | xxx | xxxx | +// |----------|----------|----------|----------|----------|----------|----------|----------|---------| +// + +// ############## +// ### R-Type ### +// ############## +// +// R-Type: register type. 8 registers: 1 for writing, 7 for reading. +// +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | opcode | page | channel | oper | ra | rb | rc | rd | re | rf | rg | rh | xxx | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// +// add $p, $ra, $rb oper $rc : apply operation on registers $rb and $rc and store the result into register $ra. Registers are on page $p. +// oper : +// 1000 : $rb + $rc +// 1001 : $rb - $rc +// 1010 : $rb * $rc +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 01010000 | page | xxxxxxx | oper | ra | rb | rc | xx | xx | xx | xx | xx | xxx | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// +// set ch, p, $ra, $rb, $rc, $rd, $re, $rt : set value on {$re,$rd,$rc,$rb,$ra} at time $rt for chhanel ch. +// $ra is the lower 32 bits and $re are the 32 most significant bits. +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 01010001 | page | channel | xxxx | xx | ra | rt | rb | rc | rd | re | xx | xxx | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// +// sync $p, $r : sync master clock to $r for upcoming instructions. +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 01010010 | page | xxxxxxx | xxxx | xx | xx | r | xx | xx | xx | xx | xx | xxx | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// +// read ch, $p, oper $r : read input data port "channel" (s?_axis) into register $r. +// oper: +// 1010 : upper 32 bits. +// else : lower 32 bits. +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 01010011 | page | channel | oper | r | xx | xx | xx | xx | xx | xx | xx | xxx | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// Example: +// read 0, 2, upper $3: read upper 32 bits of channel 0 into register 3 on page 2. +// +// wait ch, p, $r : wait until master clock reaches time specified by register $r on channel ch. +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 01010100 | page | channel | xxxx | xx | xx | r | xx | xx | xx | xx | xx | xxx | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// +// bitw p, $ra, $rb oper $rc : perform the bit-wise operation $rb oper $rc and write the result into register $ra. +// oper : +// 0000 : $rb & $rc (and) +// 0001 : $rb | $rc (or) +// 0010 : $rb ^ $rc (xor) +// 0011 : ~$rc (not) +// 0100 : $rb << $rc (left shift) +// 0101 : $rb >> $rc (right shift) +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 01010101 | page | xxxxxxx | oper | ra | rb | rc | xx | xx | xx | xx | xx | xxx | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// +// NOTE: the not operation operates on a single operand. The syntax is slightly different: +// bitw p, $ra, ~$rc +// +// memr p, $ra, $rb : read memory at address $rb and write value into register $ra: $ra = mem[$rb]. +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 01010110 | page | xxxxxxx | xxxx | ra | rb | xx | xx | xx | xx | xx | xx | xxx | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// +// memw p, $ra, $rb : write value of register $ra into memory at address $rb: $mem[$rb] = $ra. +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 01010111 | page | xxxxxxx | xxxx | xx | rb | ra | xx | xx | xx | xx | xx | xxx | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// +// setb ch, p, $ra, $rb, $rc, $rd, $re, $rt : set value on {$re,$rd,$rc,$rb,$ra} at time $rt for chhanel ch. +// $ra is the lower 32 bits and $re are the 32 most significant bits (blocking). +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 63 .. 56 | 55 .. 53 | 52 .. 50 | 49 .. 46 | 45 .. 41 | 40 .. 36 | 35 .. 31 | 30 .. 26 | 25 .. 21 | 20 .. 16 | 15 .. 11 | 10 .. 6 | 5 .. 0 | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// | 01011000 | page | channel | xxxx | xx | ra | rt | rb | rc | rd | re | xx | xxx | +// |----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|----------|---------|--------| +// + +module ctrl + ( + // Clock and reset. + clk , + rstn , + + // Start/stop. + start , + + // Opcode. + opcode , + + // IR control. + ir_en , + + // Pogram counter out (jump instructions). + pc_src , + pc_en , + pc_rst , + + // Alu control. + alu_src_b , + alu_zero , + + // Alu Time control. + alut_src_b , + + // Register write control. + reg_src , + reg_wen , + + // Conditional control. + cond_flag , + + // Stack control. + stack_en , + stack_op , + stack_full , + stack_empty , + + // Fifo time control. + fifo_wr_en , + fifo_full , + + // Data Memory control. + dmem_we , + addr_src , + + // Master clock control. + t_en , + t_sync_en , + + // Wait handshake. + waitt , + waitt_ack + ); + +// Ports. +input clk; +input rstn; + +input start; + +input [7:0] opcode; + +output ir_en; + +output pc_src; +output pc_en; +output pc_rst; + +output [1:0] alu_src_b; +input alu_zero; + +output alut_src_b; + +output [2:0] reg_src; +output reg_wen; + +input cond_flag; + +output stack_en; +output stack_op; +input stack_full; +input stack_empty; + +output fifo_wr_en; +input fifo_full; + +output dmem_we; +output addr_src; + +output t_en; +output t_sync_en; + +input waitt; +output waitt_ack; + +// States. +typedef enum { INIT_ST , + PC_RST_ST , + START_MC_ST , + FETCH_ST , + DECODE_ST , + MATHI0_ST , + MATHI1_ST , + MATHI2_ST , + MATHI3_ST , + BITWI0_ST , + BITWI1_ST , + BITWI2_ST , + BITWI3_ST , + MATH0_ST , + MATH1_ST , + MATH2_ST , + MATH3_ST , + BITW0_ST , + BITW1_ST , + BITW2_ST , + BITW3_ST , + PUSHI0_ST , + POPI0_ST , + POPI1_ST , + POPI2_ST , + LOOPNZ0_ST , + LOOPNZ1_ST , + LOOPNZ2_ST , + LOOPNZ3_ST , + SETI0_ST , + SETI1_ST , + SET0_ST , + SET1_ST , + SYNCI0_ST , + SYNCI1_ST , + SYNC0_ST , + SYNC1_ST , + CONDJ0_ST , + CONDJ1_ST , + CONDJ2_ST , + READ0_ST , + MEMRI0_ST , + MEMRI1_ST , + MEMRI2_ST , + MEMR0_ST , + MEMR1_ST , + MEMR2_ST , + MEMWI0_ST , + MEMW0_ST , + REGWI0_ST , + WAITI0_ST , + WAITI1_ST , + WAIT0_ST , + WAIT1_ST , + WAIT_ACK_ST , + ERR_INSTR_ST, + ERR_STACK_ST, + END_ST + } state_t; + +(* fsm_encoding = "one_hot" *) state_t state; + +reg state_loopnz; +reg state_condj; + +// IR control. +reg ir_en_i; + +// Pogram counter out (jump instructions). +reg pc_src_i; // 0: pc + 1, 1: jump. +reg pc_en_i; +reg pc_rst_i; + +// Alu control. +reg [1:0] alu_src_b_i; // 00: imm, 01: D1, 10: -1. + +// ALU Time control. +reg alut_src_b_i; // 0: D1, 1: imm. + +// Register write control. +reg [2:0] reg_src_i; // 000: imm, 001: Alu out, 010: Stack Out, 011: Input Port (s_axis), 100: memory. +reg reg_wen_i; + +// Stack control. +reg stack_en_i; +reg stack_op_i; // 0: pop, 1: push. + +// Fifo Time control. +reg fifo_wr_en_i; + +// Data memory control. +reg dmem_we_i; +reg addr_src_i; // 0: imm, 1: reg. + +// Master clock control. +reg t_en_i; +reg t_sync_en_i; + +// Wait handshake. +reg waitt_ack_i; + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= INIT_ST; + end + else begin + // State register. + case (state) + INIT_ST: + if (start) + state <= PC_RST_ST; + + PC_RST_ST: + state <= START_MC_ST; + + START_MC_ST: + state <= FETCH_ST; + + FETCH_ST: + state <= DECODE_ST; + + DECODE_ST: + // pushi + if ( opcode == 8'b00010000 ) + state <= PUSHI0_ST; + + // popi + else if ( opcode == 8'b00010001 ) + state <= POPI0_ST; + + // mathi + else if ( opcode == 8'b00010010 ) + state <= MATHI0_ST; + + // seti/setbi + else if ( opcode == 8'b00010011 || opcode == 8'b00011010 ) + state <= SETI0_ST; + + // synci + else if ( opcode == 8'b00010100 ) + state <= SYNCI0_ST; + + // waiti + else if ( opcode == 8'b00010101 ) + state <= WAITI0_ST; + + // bitwi + else if ( opcode == 8'b00010110 ) + state <= BITWI0_ST; + + // memri + else if ( opcode == 8'b00010111 ) + state <= MEMRI0_ST; + + // memwi + else if ( opcode == 8'b00011000 ) + state <= MEMWI0_ST; + + // regwi + else if ( opcode == 8'b00011001 ) + state <= REGWI0_ST; + + // loopnz + else if ( opcode == 8'b00110000 ) + state <= LOOPNZ0_ST; + + // condj + else if ( opcode == 8'b00110001 ) + state <= CONDJ0_ST; + + // end + else if ( opcode == 8'b00111111 ) + state <= END_ST; + + // math + else if ( opcode == 8'b01010000 ) + state <= MATH0_ST; + + // set/setb + else if ( opcode == 8'b01010001 || opcode == 8'b01011000 ) + state <= SET0_ST; + + // sync + else if ( opcode == 8'b01010010 ) + state <= SYNC0_ST; + + // read + else if ( opcode == 8'b01010011 ) + state <= READ0_ST; + + // wait + else if ( opcode == 8'b01010100 ) + state <= WAIT0_ST; + + // bitw + else if ( opcode == 8'b01010101 ) + state <= BITW0_ST; + + // memr + else if ( opcode == 8'b01010110 ) + state <= MEMR0_ST; + + // memw + else if ( opcode == 8'b01010111 ) + state <= MEMW0_ST; + + // Instruction not recognized. + else + state <= ERR_INSTR_ST; + + MATHI0_ST: + state <= MATHI1_ST; + + MATHI1_ST: + state <= MATHI2_ST; + + MATHI2_ST: + state <= MATHI3_ST; + + MATHI3_ST: + state <= DECODE_ST; + + BITWI0_ST: + state <= BITWI1_ST; + + BITWI1_ST: + state <= BITWI2_ST; + + BITWI2_ST: + state <= BITWI3_ST; + + BITWI3_ST: + state <= DECODE_ST; + + MATH0_ST: + state <= MATH1_ST; + + MATH1_ST: + state <= MATH2_ST; + + MATH2_ST: + state <= MATH3_ST; + + MATH3_ST: + state <= DECODE_ST; + + BITW0_ST: + state <= BITW1_ST; + + BITW1_ST: + state <= BITW2_ST; + + BITW2_ST: + state <= BITW3_ST; + + BITW3_ST: + state <= DECODE_ST; + + PUSHI0_ST: + if (stack_full) + state <= ERR_STACK_ST; + else + state <= DECODE_ST; + + POPI0_ST: + if (stack_empty) + state <= ERR_STACK_ST; + else + state <= POPI1_ST; + + POPI1_ST: + state <= POPI2_ST; + + POPI2_ST: + state <= DECODE_ST; + + LOOPNZ0_ST: + if (alu_zero) + // If zero, skip to next instruction. + state <= FETCH_ST; + else + // If not zero, jump to address. + state <= LOOPNZ1_ST; + + LOOPNZ1_ST: + state <= LOOPNZ2_ST; + + LOOPNZ2_ST: + state <= LOOPNZ3_ST; + + LOOPNZ3_ST: + state <= FETCH_ST; + + SETI0_ST: + state <= SETI1_ST; + + SETI1_ST: + if (~fifo_full) + state <= FETCH_ST; + + SET0_ST: + state <= SET1_ST; + + SET1_ST: + if (~fifo_full) + state <= FETCH_ST; + + SYNCI0_ST: + state <= SYNCI1_ST; + + SYNCI1_ST: + state <= DECODE_ST; + + SYNC0_ST: + state <= SYNC1_ST; + + SYNC1_ST: + state <= DECODE_ST; + + CONDJ0_ST: + state <= CONDJ1_ST; + + CONDJ1_ST: + if (cond_flag) + // Jump. + state <= CONDJ2_ST; + else + // Continue without jump. + state <= FETCH_ST; + + CONDJ2_ST: + state <= FETCH_ST; + + READ0_ST: + state <= DECODE_ST; + + MEMRI0_ST: + state <= MEMRI1_ST; + + MEMRI1_ST: + state <= MEMRI2_ST; + + MEMRI2_ST: + state <= DECODE_ST; + + MEMR0_ST: + state <= MEMR1_ST; + + MEMR1_ST: + state <= MEMR2_ST; + + MEMR2_ST: + state <= DECODE_ST; + + MEMWI0_ST: + state <= DECODE_ST; + + MEMW0_ST: + state <= DECODE_ST; + + REGWI0_ST: + state <= DECODE_ST; + + WAITI0_ST: + state <= WAITI1_ST; + + WAITI1_ST: + if (~fifo_full) + state <= WAIT_ACK_ST; + + WAIT0_ST: + state <= WAIT1_ST; + + WAIT1_ST: + if (~fifo_full) + state <= WAIT_ACK_ST; + + WAIT_ACK_ST: + if (waitt) + state <= FETCH_ST; + + ERR_INSTR_ST: + state <= END_ST; + + ERR_STACK_ST: + state <= END_ST; + + END_ST: + if (~start) + state <= INIT_ST; + endcase + end +end + +// FSM outputs. +always_comb begin + // Default. + state_loopnz = 1'b0; + state_condj = 1'b0; + ir_en_i = 1'b0; + pc_src_i = 1'b0; + pc_en_i = 1'b0; + pc_rst_i = 1'b0; + alu_src_b_i = 2'b00; + alut_src_b_i = 1'b0; + reg_src_i = 3'b000; + reg_wen_i = 1'b0; + stack_en_i = 1'b0; + stack_op_i = 1'b0; + fifo_wr_en_i = 1'b0; + dmem_we_i = 1'b0; + addr_src_i = 1'b0; + t_en_i = 1'b1; + t_sync_en_i = 1'b0; + waitt_ack_i = 1'b0; + + case (state) + //INIT_ST: + + PC_RST_ST: + pc_rst_i = 1'b1; + + START_MC_ST: + t_en_i = 1'b0; + + FETCH_ST: begin + ir_en_i = 1'b1; + pc_src_i = 1'b0; // pc + 1. + pc_en_i = 1'b1; + end + + //DECODE_ST: + + MATHI0_ST: + alu_src_b_i = 2'b00; // imm. + + MATHI1_ST: + alu_src_b_i = 2'b00; // imm. + + MATHI2_ST: + alu_src_b_i = 2'b00; // imm. + + MATHI3_ST: begin + ir_en_i = 1'b1; + pc_src_i = 1'b0; // pc + 1. + pc_en_i = 1'b1; + reg_src_i = 3'b001; // Alu out. + reg_wen_i = 1'b1; + end + + BITWI0_ST: + alu_src_b_i = 2'b00; // imm. + + BITWI1_ST: + alu_src_b_i = 2'b00; // imm. + + BITWI2_ST: + alu_src_b_i = 2'b00; // imm. + + BITWI3_ST: begin + ir_en_i = 1'b1; + pc_src_i = 1'b0; // pc + 1. + pc_en_i = 1'b1; + reg_src_i = 3'b001; // Alu out. + reg_wen_i = 1'b1; + end + + MATH0_ST: + alu_src_b_i = 2'b01; // D1. + + MATH1_ST: + alu_src_b_i = 2'b01; // D1. + + MATH2_ST: + alu_src_b_i = 2'b01; // D1. + + MATH3_ST: begin + ir_en_i = 1'b1; + pc_src_i = 1'b0; // pc + 1. + pc_en_i = 1'b1; + reg_src_i = 3'b001; // Alu out. + reg_wen_i = 1'b1; + end + + BITW0_ST: + alu_src_b_i = 2'b01; // D1. + + BITW1_ST: + alu_src_b_i = 2'b01; // D1. + + BITW2_ST: + alu_src_b_i = 2'b01; // D1. + + BITW3_ST: begin + ir_en_i = 1'b1; + pc_src_i = 1'b0; // pc + 1. + pc_en_i = 1'b1; + reg_src_i = 3'b001; // Alu out. + reg_wen_i = 1'b1; + end + + PUSHI0_ST: begin + ir_en_i = 1'b1; + pc_src_i = 1'b0; // pc + 1. + pc_en_i = 1'b1; + reg_src_i = 3'b000; // imm. + reg_wen_i = 1'b1; + stack_en_i = 1'b1; + stack_op_i = 1'b1; // push. + end + + POPI0_ST: begin + stack_en_i = 1'b1; + stack_op_i = 1'b0; // pop. + end + + POPI1_ST: begin + reg_src_i = 3'b010; // Stack Out. + end + + POPI2_ST: begin + ir_en_i = 1'b1; + pc_src_i = 1'b0; // pc + 1. + pc_en_i = 1'b1; + reg_src_i = 3'b010; // Stack Out. + reg_wen_i = 1'b1; + end + + LOOPNZ0_ST: begin + state_loopnz = 1'b1; + pc_src_i = 1'b1; // jump. + pc_en_i = 1'b1; + alu_src_b_i = 2'b10; // -1. + end + + LOOPNZ1_ST: begin + state_loopnz = 1'b1; + pc_src_i = 1'b1; // jump. + pc_en_i = 1'b1; + alu_src_b_i = 2'b10; // -1. + end + + LOOPNZ2_ST: begin + state_loopnz = 1'b1; + pc_src_i = 1'b1; // jump. + pc_en_i = 1'b1; + alu_src_b_i = 2'b10; // -1. + end + + LOOPNZ3_ST: begin + reg_src_i = 3'b001; // ALU out reg. + reg_wen_i = 1'b1; + end + + SETI0_ST: + alut_src_b_i = 1'b1; + + SETI1_ST: begin + alut_src_b_i = 1'b1; + fifo_wr_en_i = 1'b1; + end + + SET0_ST: + alut_src_b_i = 1'b0; + + SET1_ST: begin + alut_src_b_i = 1'b0; + fifo_wr_en_i = 1'b1; + end + + SYNCI0_ST: + alut_src_b_i = 1'b1; + + SYNCI1_ST: begin + ir_en_i = 1'b1; + pc_src_i = 1'b0; // pc + 1. + pc_en_i = 1'b1; + alut_src_b_i = 1'b1; + t_sync_en_i = 1'b1; + end + + SYNC0_ST: + alut_src_b_i = 1'b0; + + SYNC1_ST: begin + ir_en_i = 1'b1; + pc_src_i = 1'b0; // pc + 1. + pc_en_i = 1'b1; + alut_src_b_i = 1'b0; + t_sync_en_i = 1'b1; + end + + CONDJ0_ST: + state_condj = 1'b1; + + CONDJ1_ST: begin + state_condj = 1'b1; + pc_src_i = 1'b1; // jump. + pc_en_i = 1'b1; + end + + CONDJ2_ST: + state_condj = 1'b1; + + READ0_ST: begin + ir_en_i = 1'b1; + pc_src_i = 1'b0; // pc + 1. + pc_en_i = 1'b1; + reg_src_i = 3'b011; // Input Port (s_axis). + reg_wen_i = 1'b1; + end + + MEMRI0_ST: begin + reg_src_i = 3'b100; // Memory. + dmem_we_i = 1'b0; // Read. + addr_src_i = 1'b0; // imm. + end + + MEMRI1_ST: begin + reg_src_i = 3'b100; // Memory. + dmem_we_i = 1'b0; // Read. + addr_src_i = 1'b0; // imm. + end + + MEMRI2_ST: begin + ir_en_i = 1'b1; + pc_src_i = 1'b0; // pc + 1. + pc_en_i = 1'b1; + reg_src_i = 3'b100; // Memory. + reg_wen_i = 1'b1; + dmem_we_i = 1'b0; // Read. + addr_src_i = 1'b0; // imm. + end + + MEMR0_ST: begin + reg_src_i = 3'b100; // Memory. + dmem_we_i = 1'b0; // Read. + addr_src_i = 1'b1; // reg. + end + + MEMR1_ST: begin + reg_src_i = 3'b100; // Memory. + dmem_we_i = 1'b0; // Read. + addr_src_i = 1'b1; // reg. + end + + MEMR2_ST: begin + ir_en_i = 1'b1; + pc_src_i = 1'b0; // pc + 1. + pc_en_i = 1'b1; + reg_src_i = 3'b100; // Memory. + reg_wen_i = 1'b1; + dmem_we_i = 1'b0; // Read. + addr_src_i = 1'b1; // reg. + end + + MEMWI0_ST: begin + ir_en_i = 1'b1; + pc_src_i = 1'b0; // pc + 1. + pc_en_i = 1'b1; + dmem_we_i = 1'b1; // Write. + addr_src_i = 1'b0; // imm. + end + + MEMW0_ST: begin + ir_en_i = 1'b1; + pc_src_i = 1'b0; // pc + 1. + pc_en_i = 1'b1; + dmem_we_i = 1'b1; // Write. + addr_src_i = 1'b1; // reg. + end + + REGWI0_ST: begin + ir_en_i = 1'b1; + pc_src_i = 1'b0; // pc + 1. + pc_en_i = 1'b1; + reg_src_i = 3'b000; // imm. + reg_wen_i = 1'b1; + end + + WAITI0_ST: + alut_src_b_i = 1'b1; + + WAITI1_ST: begin + alut_src_b_i = 1'b1; + fifo_wr_en_i = 1'b1; + end + + WAIT0_ST: + alut_src_b_i = 1'b0; + + WAIT1_ST: begin + alut_src_b_i = 1'b0; + fifo_wr_en_i = 1'b1; + end + + WAIT_ACK_ST: + waitt_ack_i = 1'b1; + + //ERR_INSTR_ST: + + //ERR_STACK_ST: + + //END_ST: + + endcase +end + +// Assign outputs. +assign ir_en = ir_en_i; + +assign pc_src = (state_condj == 1'b1)? pc_src_i & cond_flag : pc_src_i; +assign pc_en = (state_loopnz == 1'b1 && state_condj == 1'b0)? pc_en_i & ~alu_zero : + (state_loopnz == 1'b0 && state_condj == 1'b1)? pc_en_i & cond_flag : + pc_en_i; + +assign pc_rst = pc_rst_i; + +assign alu_src_b = alu_src_b_i; +assign alut_src_b = alut_src_b_i; + +assign reg_src = reg_src_i; +assign reg_wen = reg_wen_i; + +assign stack_en = stack_en_i; +assign stack_op = stack_op_i; + +assign fifo_wr_en = fifo_wr_en_i; + +assign dmem_we = dmem_we_i; +assign addr_src = addr_src_i; + +assign t_en = t_en_i; +assign t_sync_en = t_sync_en_i; + +assign waitt_ack = waitt_ack_i; + +endmodule + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/axis_read.v b/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/axis_read.v new file mode 100644 index 0000000..810cfa4 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/axis_read.v @@ -0,0 +1,188 @@ +module axis_read ( + // Reset and clock. + aclk_i , + aresetn_i , + + // AXIS Master for sending data. + m_axis_tdata_o , + m_axis_tlast_o , + m_axis_tvalid_o , + m_axis_tready_i , + + // Memory interface. + mem_we_o , + mem_do_i , + mem_addr_o , + + // Handshake. + exec_i , + exec_ack_o , + + // Start address. + addr_i , + + // Length. + len_i +); + +// Parameters. +parameter N = 10; // Memory depth (2**N). +parameter B = 16; // Memory width. + +// Ports. +input aclk_i; +input aresetn_i; +output [B-1:0] m_axis_tdata_o; +output m_axis_tlast_o; +output m_axis_tvalid_o; +input m_axis_tready_i; +output mem_we_o; +input [B-1:0] mem_do_i; +output [N-1:0] mem_addr_o; +input exec_i; +output exec_ack_o; +input [N-1:0] addr_i; +input [N-1:0] len_i; + +// States. +localparam INIT_ST = 0; +localparam LOAD0_ST = 1; +localparam LOAD1_ST = 2; +localparam SEND_ST = 3; +localparam ACK_ST = 4; +localparam END_ST = 5; + +// State register. +reg [2:0] state; + +// State flags. +reg load0_state; +reg load1_state; +reg send_state; +reg ack_int; + +// Start address and length. +reg [N-1:0] addr_r; +reg [N-1:0] len_r; + +// Counter. +reg [N-1:0] cnt; + +// Selection (0: mem, 1: reg). +reg sel_r; + +// Data register. +reg [B-1:0] data_r; +wire data_en; + +// Registers. +always @(posedge aclk_i) begin + if (~aresetn_i) begin + // State register. + state <= INIT_ST; + + // Start address and length. + addr_r <= 0; + len_r <= 0; + + // Counter. + cnt <= 0; + + // Selection (0: mem, 1: reg). + sel_r <= 0; + + // Data register. + data_r <= 0; + + end + else begin + // State register. + case(state) + INIT_ST: + if (exec_i == 1'b1) + state <= LOAD0_ST; + + LOAD0_ST: + state <= LOAD1_ST; + + LOAD1_ST: + state <= SEND_ST; + + SEND_ST: + if (cnt == len_r-1 && m_axis_tready_i) + state <= ACK_ST; + + ACK_ST: + state <= END_ST; + + END_ST: + if (exec_i == 1'b0) + state <= INIT_ST; + endcase + + // Start address and length. + if (load0_state) + addr_r <= addr_i; + else if (load1_state || (send_state && m_axis_tready_i)) + addr_r <= addr_r + 1; + + if (load0_state) + len_r <= len_i; + + // Counter. + if (load0_state) + cnt <= 0; + else if (send_state && m_axis_tready_i) + cnt <= cnt + 1; + + // Selection (0: mem, 1: reg). + if (send_state && ~m_axis_tready_i) + sel_r <= 1; + else + sel_r <= 0; + + // Data register. + if (data_en) + data_r <= mem_do_i; + end +end + +// FSM outputs. +always @(state) begin + // Default. + load0_state = 0; + load1_state = 0; + send_state = 0; + ack_int = 0; + + case (state) + //INIT_ST: + + LOAD0_ST: + load0_state = 1; + + LOAD1_ST: + load1_state = 1; + + SEND_ST: + send_state = 1; + + ACK_ST: + ack_int = 1; + //END_ST: + endcase +end + +// Data enable. +assign data_en = m_axis_tready_i | ~sel_r; + +// Assign outputs. +assign m_axis_tdata_o = (sel_r == 1)? data_r : mem_do_i; +assign m_axis_tlast_o = (cnt == len_r-1) & send_state; +assign m_axis_tvalid_o = send_state; +assign mem_we_o = 1'b0; +assign mem_addr_o = addr_r; +assign exec_ack_o = ack_int; + +endmodule + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/axis_write.v b/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/axis_write.v new file mode 100644 index 0000000..fad6053 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/axis_write.v @@ -0,0 +1,151 @@ +module axis_write ( + // Reset and clock. + aclk_i , + aresetn_i , + + // AXIS Slave for receiving data. + s_axis_tdata_i , + s_axis_tlast_i , + s_axis_tvalid_i , + s_axis_tready_o , + + // Memory interface. + mem_we_o , + mem_di_o , + mem_addr_o , + + // Handshake. + exec_i , + exec_ack_o , + + // Start address. + addr_i +); + +// Parameters. +parameter N = 10; // Memory depth (2**N). +parameter B = 16; // Memory width. + +// Ports. +input aclk_i; +input aresetn_i; +input [B-1:0] s_axis_tdata_i; +input s_axis_tlast_i; +input s_axis_tvalid_i; +output s_axis_tready_o; +output mem_we_o; +output [B-1:0] mem_di_o; +output [N-1:0] mem_addr_o; +input exec_i; +output exec_ack_o; +input [N-1:0] addr_i; + +// States. +localparam INIT_ST = 0; +localparam WRITE_ST = 1; +localparam ACK_ST = 2; +localparam END_ST = 3; + +// State register. +reg [1:0] state; + +// State flags. +reg init_state; +reg write_state; +reg ack_int; + +// Address generation. +reg [N-1:0] addr_cnt; +reg [N-1:0] addr_cnt_r; + +// Data. +reg [B-1:0] data_r; + +// we generation. +wire we_int; +reg we_int_r; + +// Registers. +always @(posedge aclk_i) begin + if (~aresetn_i) begin + // State register. + state <= INIT_ST; + + // Address generation. + addr_cnt <= 0; + addr_cnt_r <= 0; + + // Data. + data_r <= 0; + + // we generation. + we_int_r <= 0; + end + else begin + // State register. + case(state) + INIT_ST: + if (exec_i == 1'b1) + state <= WRITE_ST; + + WRITE_ST: + if (s_axis_tlast_i && s_axis_tvalid_i) + state <= ACK_ST; + + ACK_ST: + state <= END_ST; + + END_ST: + if (exec_i == 1'b0) + state <= INIT_ST; + endcase + // Address generation. + if (init_state) + addr_cnt <= addr_i; + else if (s_axis_tvalid_i) + addr_cnt <= addr_cnt + 1; + + addr_cnt_r <= addr_cnt; + + // Data. + data_r <= s_axis_tdata_i; + + // we generation. + we_int_r <= we_int; + + end +end + +// FSM outputs. +always @(state) begin + // Default. + init_state = 0; + write_state = 0; + ack_int = 0; + + case (state) + INIT_ST: + init_state = 1; + + WRITE_ST: + write_state = 1; + + ACK_ST: + ack_int = 1; + + //END_ST: + endcase +end + +// we generation. +assign we_int = s_axis_tvalid_i & write_state; + +// Assign outputs. +assign s_axis_tready_o = write_state; +assign mem_we_o = we_int_r; +assign mem_di_o = data_r; +assign mem_addr_o = addr_cnt_r; +assign exec_ack_o = ack_int; + +endmodule + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/data_mem.v b/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/data_mem.v new file mode 100644 index 0000000..39beef2 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/data_mem.v @@ -0,0 +1,276 @@ +// Assembled memory access module. Three modes of accessing the memory: +// +// * Single access using the in/out ports. It's only available when busy_o = 0. +// +// * AXIS read: this mode allows to send data using m_axis_* interface, using +// ADDR_REG as the starting address and LEN_REG to indicate the number of +// samples to be transferred. The last sample will assert m_axis_tlast_o to +// indicate the external block transaction is done. Similar to AXIS write +// mode, the user needs to set START_REG = 1 to start the process. +// +// * AXIS write: this mode receives data from s_axis_* interface and writes +// into the memory using ADDR_REG as the starting address. The user must also +// provide the START_REG = 1 to allow starting receiving data. The block will +// rely on s_axis_tlast_i = 1 to finish the writing process. +// +// When not performing any AXIS transaction, the block will grant access to +// the memory using the single access interface. This is a very basic +// handshake interface to allow external blocks to easily communicate and +// perform single-access transaction. +// +// Once a AXIS transaction is done, the user must set START_REG = 0 and back +// to 1 if a new AXIS transaction needs to be executed. START_REG = 1 steady +// will not allow further AXIS transactions, and will only allow +// single-access. +// +// Registers: +// +// MODE_REG : indicates the type of the next AXIS transaction. +// * 0 : AXIS Read (from memory to m_axis). +// * 1 : AXIS Write (from s_axis to memory). +// +// START_REG : starts execution of indicated AXIS transaction. +// * 0 : Stop. +// * 1 : Execute Operation. +// +// ADDR_REG : starting memory address for either AXIS read or write. +// +// LEN_REG : number of samples to be transferred in AXIS read mode. +// +module data_mem ( + // Reset and clock. + aclk_i , + aresetn_i , + + // Single Access Handshake. + busy_o , + oper_i , + addr_i , + din_i , + dout_o , + exec_i , + exec_ack_o , + + // Memory interface. + mem_we_o , + mem_di_o , + mem_do_i , + mem_addr_o , + + // AXIS Slave for receiving data. + s_axis_tdata_i , + s_axis_tlast_i , + s_axis_tvalid_i , + s_axis_tready_o , + + // AXIS Master for sending data. + m_axis_tdata_o , + m_axis_tlast_o , + m_axis_tvalid_o , + m_axis_tready_i , + + // Registers. + MODE_REG , + START_REG , + ADDR_REG , + LEN_REG +); + +// Parameters. +parameter N = 16; +parameter B = 32; + +// Ports. +input aclk_i; +input aresetn_i; + +output busy_o; +input oper_i; +input [N-1:0] addr_i; +input [B-1:0] din_i; +output [B-1:0] dout_o; +input exec_i; +output exec_ack_o; + +output mem_we_o; +output [B-1:0] mem_di_o; +input [B-1:0] mem_do_i; +output [N-1:0] mem_addr_o; + +// AXIS Slave for receiving data. +input [B-1:0] s_axis_tdata_i; +input s_axis_tlast_i; +input s_axis_tvalid_i; +output s_axis_tready_o; + +// AXIS Master for sending data. +output [B-1:0] m_axis_tdata_o; +output m_axis_tlast_o; +output m_axis_tvalid_o; +input m_axis_tready_i; + +input MODE_REG; +input START_REG; +input [N-1:0] ADDR_REG; +input [N-1:0] LEN_REG; + +// Internals. +wire [1:0] sel; +wire ar_exec; +wire ar_exec_ack; +wire aw_exec; +wire aw_exec_ack; + +// Memory Single. +wire mem_we_single; +wire [B-1:0] mem_di_single; +wire [N-1:0] mem_addr_single; + +// Memory AXIS Read. +wire mem_we_aread; +wire [N-1:0] mem_addr_aread; + +// Memory AXIS Write. +wire mem_we_awrite; +wire [B-1:0] mem_di_awrite; +wire [N-1:0] mem_addr_awrite; + +data_mem_ctrl + #( + .N(N) + ) + data_mem_ctrl_i + ( + // Reset and clock. + .aclk_i (aclk_i ), + .aresetn_i (aresetn_i ), + + // Selector. + .sel_o (sel ), + + // axis_read handshake. + .ar_exec_o (ar_exec ), + .ar_exec_ack_i (ar_exec_ack ), + + // axis_write handshake. + .aw_exec_o (aw_exec ), + .aw_exec_ack_i (aw_exec_ack ), + + // Busy flag. + .busy_o (busy_o ), + + // Registers. + .MODE_REG (MODE_REG ), + .START_REG (START_REG ) + ); + +mem_rw + #( + .N(N), + .B(B) + ) + mem_rw_i + ( + // Reset and clock. + .aclk_i (aclk_i ), + .aresetn_i (aresetn_i ), + + // Operation. + .rw_i (oper_i ), + + // Handshake. + .exec_i (exec_i ), + .exec_ack_o (exec_ack_o ), + + // Address. + .addr_i (addr_i ), + + // Input/Output data. + .di_i (din_i ), + .do_o (dout_o ), + + // Memory interface. + .mem_we_o (mem_we_single ), + .mem_di_o (mem_di_single ), + .mem_do_i (mem_do_i ), + .mem_addr_o (mem_addr_single ) + ); + +axis_read + #( + .N(N), + .B(B) + ) + axis_read_i + ( + // Reset and clock. + .aclk_i (aclk_i ), + .aresetn_i (aresetn_i ), + + // AXIS Master for sending data. + .m_axis_tdata_o (m_axis_tdata_o ), + .m_axis_tlast_o (m_axis_tlast_o ), + .m_axis_tvalid_o (m_axis_tvalid_o ), + .m_axis_tready_i (m_axis_tready_i ), + + // Memory interface. + .mem_we_o (mem_we_aread ), + .mem_do_i (mem_do_i ), + .mem_addr_o (mem_addr_aread ), + + // Handshake. + .exec_i (ar_exec ), + .exec_ack_o (ar_exec_ack ), + + // Start address. + .addr_i (ADDR_REG ), + + // Length. + .len_i (LEN_REG ) + ); + +axis_write + #( + .N(N), + .B(B) + ) + axis_write_i + ( + // Reset and clock. + .aclk_i (aclk_i ), + .aresetn_i (aresetn_i ), + + // AXIS Slave for receiving data. + .s_axis_tdata_i (s_axis_tdata_i ), + .s_axis_tlast_i (s_axis_tlast_i ), + .s_axis_tvalid_i (s_axis_tvalid_i ), + .s_axis_tready_o (s_axis_tready_o ), + + // Memory interface. + .mem_we_o (mem_we_awrite ), + .mem_di_o (mem_di_awrite ), + .mem_addr_o (mem_addr_awrite ), + + // Start. + .exec_i (aw_exec ), + .exec_ack_o (aw_exec_ack ), + + // Start address. + .addr_i (ADDR_REG ) + ); + +// Assign outputs. +assign mem_we_o = (sel == 0)? mem_we_single : + (sel == 1)? mem_we_aread : + (sel == 2)? mem_we_awrite : + 1'b0; +assign mem_di_o = (sel == 0)? mem_di_single : + (sel == 2)? mem_di_awrite : + {B{1'b0}}; +assign mem_addr_o = (sel == 0)? mem_addr_single : + (sel == 1)? mem_addr_aread : + (sel == 2)? mem_addr_awrite : + {N{1'b0}}; + +endmodule + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/data_mem_ctrl.v b/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/data_mem_ctrl.v new file mode 100644 index 0000000..30f5804 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/data_mem_ctrl.v @@ -0,0 +1,156 @@ +// Control arbiter for memory access operations. +// +// The block arbitrates access to the memory. While executing +// either AXIS Read or Write, busy flag is asserted. If the +// busy flag is not asserted, memory can be accessed using +// single mode (external block). +// +// MODE_REG: +// * 0 : AXIS Read (from memory to m_axis). +// * 1 : AXIS Write (from s_axis to memory). +// +// START_REG: +// * 0 : Stop. +// * 1 : Execute Operation. +module data_mem_ctrl ( + // Reset and clock. + aclk_i , + aresetn_i , + + // Selector. + sel_o , + + // axis_read handshake. + ar_exec_o , + ar_exec_ack_i , + + // axis_write handshake. + aw_exec_o , + aw_exec_ack_i , + + // Busy flag. + busy_o , + + // Registers. + MODE_REG , + START_REG +); + +// Parameters. +parameter N = 16; + +// Ports. +input aclk_i; +input aresetn_i; +output [1:0] sel_o; +output ar_exec_o; +input ar_exec_ack_i; +output aw_exec_o; +input aw_exec_ack_i; +output busy_o; +input MODE_REG; +input START_REG; + +// States. +localparam INIT_ST = 0; +localparam AXIS_READ_ST = 1; +localparam AXIS_READ_ACK_ST = 2; +localparam AXIS_WRITE_ST = 3; +localparam AXIS_WRITE_ACK_ST = 4; +localparam END_ST = 6; + +// State register. +reg [2:0] state; + +// State flags. +reg busy_int; +reg ar_exec_int; +reg aw_exec_int; +reg [1:0] sel_int; // 0: single, 1: axis_read, 2: axis_write. + +// Registers. +always @(posedge aclk_i) begin + if (~aresetn_i) begin + // State register. + state <= INIT_ST; + end + else begin + // State register. + case(state) + INIT_ST: + if (START_REG == 1'b1) + if (MODE_REG == 1'b0) + // AXIS read (from memory to m_axis). + state <= AXIS_READ_ST; + else + // AXIS write (from s_axis to memory). + state <= AXIS_WRITE_ST; + + AXIS_READ_ST: + state <= AXIS_READ_ACK_ST; + + AXIS_READ_ACK_ST: + if (ar_exec_ack_i == 1'b1) + state <= END_ST; + + AXIS_WRITE_ST: + state <= AXIS_WRITE_ACK_ST; + + AXIS_WRITE_ACK_ST: + if (aw_exec_ack_i == 1'b1) + state <= END_ST; + + END_ST: + if (START_REG == 1'b0) + state <= INIT_ST; + endcase + + end +end + +// FSM outputs. +always @(state) begin + // Default. + busy_int = 0; + ar_exec_int = 0; + aw_exec_int = 0; + sel_int = 0; + + case (state) + //INIT_ST: + + AXIS_READ_ST: begin + busy_int = 1; + sel_int = 1; + end + + AXIS_READ_ACK_ST: begin + ar_exec_int = 1; + busy_int = 1; + sel_int = 1; + end + + AXIS_WRITE_ST: begin + busy_int = 1; + sel_int = 2; + end + + AXIS_WRITE_ACK_ST: begin + aw_exec_int = 1; + busy_int = 1; + sel_int = 2; + end + + //END_ST: + + endcase +end + +// Assign outputs. +assign sel_o = sel_int; +assign ar_exec_o = ar_exec_int; +assign aw_exec_o = aw_exec_int; +assign busy_o = busy_int; + +endmodule + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/mem_rw.v b/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/mem_rw.v new file mode 100644 index 0000000..a1a1c76 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/data_mem/mem_rw.v @@ -0,0 +1,148 @@ +// Block to execute single read/write operation over a memory. +module mem_rw ( + // Reset and clock. + aclk_i , + aresetn_i , + + // Operation. + rw_i , + + // Handshake. + exec_i , + exec_ack_o , + + // Address. + addr_i , + + // Input/Output data. + di_i , + do_o , + + // Memory interface. + mem_we_o , + mem_di_o , + mem_do_i , + mem_addr_o +); + +// Parameters. +parameter N = 10; // Memory depth (2**N). +parameter B = 16; // Memory width. + +// Ports. +input aclk_i; +input aresetn_i; +input rw_i; +input exec_i; +output exec_ack_o; +input [N-1:0] addr_i; +input [B-1:0] di_i; +output [B-1:0] do_o; +output mem_we_o; +output [B-1:0] mem_di_o; +input [B-1:0] mem_do_i; +output [N-1:0] mem_addr_o; + +// States. +localparam INIT_ST = 0; +localparam READ0_ST = 1; +localparam READ1_ST = 2; +localparam WRITE_ST = 3; +localparam ACK_ST = 4; + +// State register. +reg [2:0] state; + +// Flags. +reg init_state; +reg re_int; +reg we_int; +reg ack_int; + +// Address/data register. +reg [N-1:0] addr_r; +reg [B-1:0] din_r; +reg [B-1:0] dout_r; + +// Registers. +always @(posedge aclk_i) begin + if (~aresetn_i) begin + // State register. + state <= INIT_ST; + + // Address/data register. + addr_r <= 0; + din_r <= 0; + dout_r <= 0; + end + else begin + // State register. + case(state) + INIT_ST: + if (exec_i == 1'b1) + if (rw_i == 1'b0) + state <= READ0_ST; + else + state <= WRITE_ST; + + READ0_ST: + state <= READ1_ST; + + READ1_ST: + state <= ACK_ST; + + WRITE_ST: + state <= ACK_ST; + + ACK_ST: + if (exec_i == 1'b0) + state <= INIT_ST; + endcase + + // Address/data register. + if (init_state) begin + addr_r <= addr_i; + din_r <= di_i; + end + + if (re_int) + dout_r <= mem_do_i; + + end +end + +// FSM outputs. +always @(state) begin + // Default. + init_state = 0; + re_int = 0; + we_int = 0; + ack_int = 0; + + case (state) + INIT_ST: + init_state = 1; + + //READ0_ST: + + READ1_ST: + re_int = 1; + + WRITE_ST: + we_int = 1; + + ACK_ST: + ack_int = 1; + + endcase +end + +// Assign outputs. +assign exec_ack_o = ack_int; +assign do_o = dout_r; +assign mem_we_o = we_int; +assign mem_di_o = din_r; +assign mem_addr_o = addr_r; + +endmodule + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/bin2gray.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/bin2gray.vhd new file mode 100644 index 0000000..4ecc09b --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/bin2gray.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end bin2gray; + +architecture rtl of bin2gray is + +signal gray : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +gray(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + gray(I) <= din(I+1) xor din(I); +end generate; + +-- Assign output. +dout <= gray; + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/bram_dp.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/bram_dp.vhd new file mode 100644 index 0000000..d57aad1 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/bram_dp.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture rtl of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/bram_simple_dp.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/bram_simple_dp.vhd new file mode 100644 index 0000000..1494332 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/bram_simple_dp.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_simple_dp; + +architecture rtl of bram_simple_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo.vhd new file mode 100644 index 0000000..957362b --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture rtl of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Dual port, single clock BRAM. +component bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- FIFO memory. +mem_i : bram_simple_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_axi.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_dc.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/gray2bin.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/rd2axi.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/gen_sim/gen_sim.sv b/firmware/ip/axis_tproc64x32_x8_v1/src/gen_sim/gen_sim.sv new file mode 100644 index 0000000..deace3c --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/gen_sim/gen_sim.sv @@ -0,0 +1,142 @@ +// Simplified Signal Generator Simulator. +// The block reads from the queue and implements the periodic +// and non-periodic mode, using the lower 16 bits for the number +// of samples and the next bit for mode. +module gen_sim + ( + clk , + rstn , + s_axis_tdata , + s_axis_tvalid , + s_axis_tready + ); + +input clk; +input rstn; + +input [159:0] s_axis_tdata; +input s_axis_tvalid; +output s_axis_tready; + +// States. +typedef enum { READ_ST , + CNT_ST + } state_t; + +(* fsm_encoding = "one_hot" *) state_t state; + +reg fifo_rd_en; +wire [159:0] fifo_dout; +wire fifo_full; +wire fifo_empty; + +// Fifo fields. +wire [15:0] nsamp_int; +reg [15:0] nsamp_r; +wire mode_int; +reg mode_r; + +// Counter. +reg [15:0] cnt; + +// Register enable. +wire en; +reg en_r; + +// Fifo. +fifo + #( + // Data width. + .B (160 ), + + // Fifo depth. + .N (16 ) + ) + fifo_i + ( + .rstn (rstn ), + .clk (clk ), + + // Write I/F. + .wr_en (s_axis_tvalid ), + .din (s_axis_tdata ), + + // Read I/F. + .rd_en (fifo_rd_en ), + .dout (fifo_dout ), + + // Flags. + .full (fifo_full ), + .empty (fifo_empty ) + ); + +// Fifo fields. +assign nsamp_int = fifo_dout[15:0]; +assign mode_int = fifo_dout[16]; + +// Register enable. +assign en = fifo_rd_en & ~fifo_empty; + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= READ_ST; + + // Fifo fields. + nsamp_r <= 0; + mode_r <= 0; + + // Counter. + cnt <= 0; + + // Register enable. + en_r <= 0; + end + else begin + // State register. + case (state) + READ_ST: + if (mode_r == 1'b1 || fifo_empty == 1'b0) + state <= CNT_ST; + + CNT_ST: + if (cnt == nsamp_r-2) + state <= READ_ST; + endcase + + // Counter. + if (fifo_rd_en == 1'b0) + cnt <= cnt + 1; + else + cnt <= 0; + + // Fifo fields. + if (en_r == 1'b1) begin + nsamp_r <= nsamp_int; + mode_r <= mode_int; + end + + // Register enable. + en_r <= en; + end +end + +// FSM outputs. +always_comb begin + // Default. + fifo_rd_en = 1'b0; + + case (state) + READ_ST: begin + fifo_rd_en = 1'b1; + end + + //CNT_ST: + endcase +end + +assign s_axis_tready = ~fifo_full; + +endmodule + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/regfile/regfile.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/regfile/regfile.vhd new file mode 100644 index 0000000..6b6ce9c --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/regfile/regfile.vhd @@ -0,0 +1,104 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity regfile is + Generic ( + -- Data width. + B : Integer := 16; + -- Map size. + N : Integer := 4 + ); + Port ( + -- Clock. + clk : in std_logic; + + -- Read address. + addr0 : in std_logic_vector (N-1 downto 0); + addr1 : in std_logic_vector (N-1 downto 0); + addr2 : in std_logic_vector (N-1 downto 0); + addr3 : in std_logic_vector (N-1 downto 0); + addr4 : in std_logic_vector (N-1 downto 0); + addr5 : in std_logic_vector (N-1 downto 0); + addr6 : in std_logic_vector (N-1 downto 0); + + -- Write address. + addr7 : in std_logic_vector (N-1 downto 0); + + -- Write data. + din7 : in std_logic_vector (B-1 downto 0); + wen7 : in std_logic; + + -- Output registers. + dout0 : out std_logic_vector (B-1 downto 0); + dout1 : out std_logic_vector (B-1 downto 0); + dout2 : out std_logic_vector (B-1 downto 0); + dout3 : out std_logic_vector (B-1 downto 0); + dout4 : out std_logic_vector (B-1 downto 0); + dout5 : out std_logic_vector (B-1 downto 0); + dout6 : out std_logic_vector (B-1 downto 0) + ); +end regfile; + +architecture rtl of regfile is + +type mem_array_t is array ((2**N-1) downto 0) of std_logic_vector (B-1 downto 0); +signal mem_array : mem_array_t; + +begin + +process (clk) +begin + if ( rising_edge(clk) ) then + -- Write. + if ( wen7 = '1' ) then + mem_array(to_integer(unsigned(addr7))) <= din7; + end if; + + -- Read. + if ( unsigned(addr0) = 0 ) then + dout0 <= (others => '0'); + else + dout0 <= mem_array(to_integer(unsigned(addr0))); + end if; + + if ( unsigned(addr1) = 0 ) then + dout1 <= (others => '0'); + else + dout1 <= mem_array(to_integer(unsigned(addr1))); + end if; + + if ( unsigned(addr2) = 0 ) then + dout2 <= (others => '0'); + else + dout2 <= mem_array(to_integer(unsigned(addr2))); + end if; + + if ( unsigned(addr3) = 0 ) then + dout3 <= (others => '0'); + else + dout3 <= mem_array(to_integer(unsigned(addr3))); + end if; + + if ( unsigned(addr4) = 0 ) then + dout4 <= (others => '0'); + else + dout4 <= mem_array(to_integer(unsigned(addr4))); + end if; + + if ( unsigned(addr5) = 0 ) then + dout5 <= (others => '0'); + else + dout5 <= mem_array(to_integer(unsigned(addr5))); + end if; + + if ( unsigned(addr6) = 0 ) then + dout6 <= (others => '0'); + else + dout6 <= mem_array(to_integer(unsigned(addr6))); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/regfile/regfile_8p.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/regfile/regfile_8p.vhd new file mode 100644 index 0000000..6407924 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/regfile/regfile_8p.vhd @@ -0,0 +1,592 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Regfile block. +-- +-- 7 registers can be read in parallel. One clock cycle latency. +-- 1 register can be written. +-- 8 pages allow 32x8 = 256 total registers. +-- In any page, reading register 0 gives 0. + +entity regfile_8p is + Generic ( + -- Data width. + B : Integer := 16 + ); + Port ( + -- Clock and reset. + clk : in std_logic; + rstn : in std_logic; + + -- Read address. + addr0 : in std_logic_vector (4 downto 0); + addr1 : in std_logic_vector (4 downto 0); + addr2 : in std_logic_vector (4 downto 0); + addr3 : in std_logic_vector (4 downto 0); + addr4 : in std_logic_vector (4 downto 0); + addr5 : in std_logic_vector (4 downto 0); + addr6 : in std_logic_vector (4 downto 0); + + -- Write address. + addr7 : in std_logic_vector (4 downto 0); + + -- Write data. + din7 : in std_logic_vector (B-1 downto 0); + wen7 : in std_logic; + + -- Page number. + pnum : in std_logic_vector (2 downto 0); + + -- Output registers. + dout0 : out std_logic_vector (B-1 downto 0); + dout1 : out std_logic_vector (B-1 downto 0); + dout2 : out std_logic_vector (B-1 downto 0); + dout3 : out std_logic_vector (B-1 downto 0); + dout4 : out std_logic_vector (B-1 downto 0); + dout5 : out std_logic_vector (B-1 downto 0); + dout6 : out std_logic_vector (B-1 downto 0) + ); +end regfile_8p; + +architecture rtl of regfile_8p is + +constant N : Integer := 5; + +-- Register file. +component regfile is + Generic ( + -- Data width. + B : Integer := 16; + -- Map size. + N : Integer := 4 + ); + Port ( + -- Clock. + clk : in std_logic; + + -- Read address. + addr0 : in std_logic_vector (N-1 downto 0); + addr1 : in std_logic_vector (N-1 downto 0); + addr2 : in std_logic_vector (N-1 downto 0); + addr3 : in std_logic_vector (N-1 downto 0); + addr4 : in std_logic_vector (N-1 downto 0); + addr5 : in std_logic_vector (N-1 downto 0); + addr6 : in std_logic_vector (N-1 downto 0); + + -- Write address. + addr7 : in std_logic_vector (N-1 downto 0); + + -- Write data. + din7 : in std_logic_vector (B-1 downto 0); + wen7 : in std_logic; + + -- Output registers. + dout0 : out std_logic_vector (B-1 downto 0); + dout1 : out std_logic_vector (B-1 downto 0); + dout2 : out std_logic_vector (B-1 downto 0); + dout3 : out std_logic_vector (B-1 downto 0); + dout4 : out std_logic_vector (B-1 downto 0); + dout5 : out std_logic_vector (B-1 downto 0); + dout6 : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Regfile 0. +signal wen7_0 : std_logic; +signal dout0_0 : std_logic_vector (B-1 downto 0); +signal dout1_0 : std_logic_vector (B-1 downto 0); +signal dout2_0 : std_logic_vector (B-1 downto 0); +signal dout3_0 : std_logic_vector (B-1 downto 0); +signal dout4_0 : std_logic_vector (B-1 downto 0); +signal dout5_0 : std_logic_vector (B-1 downto 0); +signal dout6_0 : std_logic_vector (B-1 downto 0); + +-- Regfile 1. +signal wen7_1 : std_logic; +signal dout0_1 : std_logic_vector (B-1 downto 0); +signal dout1_1 : std_logic_vector (B-1 downto 0); +signal dout2_1 : std_logic_vector (B-1 downto 0); +signal dout3_1 : std_logic_vector (B-1 downto 0); +signal dout4_1 : std_logic_vector (B-1 downto 0); +signal dout5_1 : std_logic_vector (B-1 downto 0); +signal dout6_1 : std_logic_vector (B-1 downto 0); + +-- Regfile 2. +signal wen7_2 : std_logic; +signal dout0_2 : std_logic_vector (B-1 downto 0); +signal dout1_2 : std_logic_vector (B-1 downto 0); +signal dout2_2 : std_logic_vector (B-1 downto 0); +signal dout3_2 : std_logic_vector (B-1 downto 0); +signal dout4_2 : std_logic_vector (B-1 downto 0); +signal dout5_2 : std_logic_vector (B-1 downto 0); +signal dout6_2 : std_logic_vector (B-1 downto 0); + +-- Regfile 3. +signal wen7_3 : std_logic; +signal dout0_3 : std_logic_vector (B-1 downto 0); +signal dout1_3 : std_logic_vector (B-1 downto 0); +signal dout2_3 : std_logic_vector (B-1 downto 0); +signal dout3_3 : std_logic_vector (B-1 downto 0); +signal dout4_3 : std_logic_vector (B-1 downto 0); +signal dout5_3 : std_logic_vector (B-1 downto 0); +signal dout6_3 : std_logic_vector (B-1 downto 0); + +-- Regfile 4. +signal wen7_4 : std_logic; +signal dout0_4 : std_logic_vector (B-1 downto 0); +signal dout1_4 : std_logic_vector (B-1 downto 0); +signal dout2_4 : std_logic_vector (B-1 downto 0); +signal dout3_4 : std_logic_vector (B-1 downto 0); +signal dout4_4 : std_logic_vector (B-1 downto 0); +signal dout5_4 : std_logic_vector (B-1 downto 0); +signal dout6_4 : std_logic_vector (B-1 downto 0); + +-- Regfile 5. +signal wen7_5 : std_logic; +signal dout0_5 : std_logic_vector (B-1 downto 0); +signal dout1_5 : std_logic_vector (B-1 downto 0); +signal dout2_5 : std_logic_vector (B-1 downto 0); +signal dout3_5 : std_logic_vector (B-1 downto 0); +signal dout4_5 : std_logic_vector (B-1 downto 0); +signal dout5_5 : std_logic_vector (B-1 downto 0); +signal dout6_5 : std_logic_vector (B-1 downto 0); + +-- Regfile 6. +signal wen7_6 : std_logic; +signal dout0_6 : std_logic_vector (B-1 downto 0); +signal dout1_6 : std_logic_vector (B-1 downto 0); +signal dout2_6 : std_logic_vector (B-1 downto 0); +signal dout3_6 : std_logic_vector (B-1 downto 0); +signal dout4_6 : std_logic_vector (B-1 downto 0); +signal dout5_6 : std_logic_vector (B-1 downto 0); +signal dout6_6 : std_logic_vector (B-1 downto 0); + +-- Regfile 7. +signal wen7_7 : std_logic; +signal dout0_7 : std_logic_vector (B-1 downto 0); +signal dout1_7 : std_logic_vector (B-1 downto 0); +signal dout2_7 : std_logic_vector (B-1 downto 0); +signal dout3_7 : std_logic_vector (B-1 downto 0); +signal dout4_7 : std_logic_vector (B-1 downto 0); +signal dout5_7 : std_logic_vector (B-1 downto 0); +signal dout6_7 : std_logic_vector (B-1 downto 0); + +-- Muxed output data. +signal dout0_i : std_logic_vector (B-1 downto 0); +signal dout1_i : std_logic_vector (B-1 downto 0); +signal dout2_i : std_logic_vector (B-1 downto 0); +signal dout3_i : std_logic_vector (B-1 downto 0); +signal dout4_i : std_logic_vector (B-1 downto 0); +signal dout5_i : std_logic_vector (B-1 downto 0); +signal dout6_i : std_logic_vector (B-1 downto 0); + +-- Pipe on page selection. +signal pnum_r : std_logic_vector (2 downto 0); + +begin + +-- Register file 0. +regfile_0_i : regfile + Generic map ( + -- Data width. + B => B , + -- Map size. + N => N + ) + Port map ( + -- Clock. + clk => clk , + + -- Read address. + addr0 => addr0 , + addr1 => addr1 , + addr2 => addr2 , + addr3 => addr3 , + addr4 => addr4 , + addr5 => addr5 , + addr6 => addr6 , + + -- Write address. + addr7 => addr7 , + + -- Write data. + din7 => din7 , + wen7 => wen7_0 , + + -- Output registers. + dout0 => dout0_0 , + dout1 => dout1_0 , + dout2 => dout2_0 , + dout3 => dout3_0 , + dout4 => dout4_0 , + dout5 => dout5_0 , + dout6 => dout6_0 + ); + +-- Register file 1. +regfile_1_i : regfile + Generic map ( + -- Data width. + B => B , + -- Map size. + N => N + ) + Port map ( + -- Clock. + clk => clk , + + -- Read address. + addr0 => addr0 , + addr1 => addr1 , + addr2 => addr2 , + addr3 => addr3 , + addr4 => addr4 , + addr5 => addr5 , + addr6 => addr6 , + + -- Write address. + addr7 => addr7 , + + -- Write data. + din7 => din7 , + wen7 => wen7_1 , + + -- Output registers. + dout0 => dout0_1 , + dout1 => dout1_1 , + dout2 => dout2_1 , + dout3 => dout3_1 , + dout4 => dout4_1 , + dout5 => dout5_1 , + dout6 => dout6_1 + ); + +-- Register file 2. +regfile_2_i : regfile + Generic map ( + -- Data width. + B => B , + -- Map size. + N => N + ) + Port map ( + -- Clock. + clk => clk , + + -- Read address. + addr0 => addr0 , + addr1 => addr1 , + addr2 => addr2 , + addr3 => addr3 , + addr4 => addr4 , + addr5 => addr5 , + addr6 => addr6 , + + -- Write address. + addr7 => addr7 , + + -- Write data. + din7 => din7 , + wen7 => wen7_2 , + + -- Output registers. + dout0 => dout0_2 , + dout1 => dout1_2 , + dout2 => dout2_2 , + dout3 => dout3_2 , + dout4 => dout4_2 , + dout5 => dout5_2 , + dout6 => dout6_2 + ); + +-- Register file 3. +regfile_3_i : regfile + Generic map ( + -- Data width. + B => B , + -- Map size. + N => N + ) + Port map ( + -- Clock. + clk => clk , + + -- Read address. + addr0 => addr0 , + addr1 => addr1 , + addr2 => addr2 , + addr3 => addr3 , + addr4 => addr4 , + addr5 => addr5 , + addr6 => addr6 , + + -- Write address. + addr7 => addr7 , + + -- Write data. + din7 => din7 , + wen7 => wen7_3 , + + -- Output registers. + dout0 => dout0_3 , + dout1 => dout1_3 , + dout2 => dout2_3 , + dout3 => dout3_3 , + dout4 => dout4_3 , + dout5 => dout5_3 , + dout6 => dout6_3 + ); + +-- Register file 4. +regfile_4_i : regfile + Generic map ( + -- Data width. + B => B , + -- Map size. + N => N + ) + Port map ( + -- Clock. + clk => clk , + + -- Read address. + addr0 => addr0 , + addr1 => addr1 , + addr2 => addr2 , + addr3 => addr3 , + addr4 => addr4 , + addr5 => addr5 , + addr6 => addr6 , + + -- Write address. + addr7 => addr7 , + + -- Write data. + din7 => din7 , + wen7 => wen7_4 , + + -- Output registers. + dout0 => dout0_4 , + dout1 => dout1_4 , + dout2 => dout2_4 , + dout3 => dout3_4 , + dout4 => dout4_4 , + dout5 => dout5_4 , + dout6 => dout6_4 + ); + +-- Register file 5. +regfile_5_i : regfile + Generic map ( + -- Data width. + B => B , + -- Map size. + N => N + ) + Port map ( + -- Clock. + clk => clk , + + -- Read address. + addr0 => addr0 , + addr1 => addr1 , + addr2 => addr2 , + addr3 => addr3 , + addr4 => addr4 , + addr5 => addr5 , + addr6 => addr6 , + + -- Write address. + addr7 => addr7 , + + -- Write data. + din7 => din7 , + wen7 => wen7_5 , + + -- Output registers. + dout0 => dout0_5 , + dout1 => dout1_5 , + dout2 => dout2_5 , + dout3 => dout3_5 , + dout4 => dout4_5 , + dout5 => dout5_5 , + dout6 => dout6_5 + ); + +-- Register file 6. +regfile_6_i : regfile + Generic map ( + -- Data width. + B => B , + -- Map size. + N => N + ) + Port map ( + -- Clock. + clk => clk , + + -- Read address. + addr0 => addr0 , + addr1 => addr1 , + addr2 => addr2 , + addr3 => addr3 , + addr4 => addr4 , + addr5 => addr5 , + addr6 => addr6 , + + -- Write address. + addr7 => addr7 , + + -- Write data. + din7 => din7 , + wen7 => wen7_6 , + + -- Output registers. + dout0 => dout0_6 , + dout1 => dout1_6 , + dout2 => dout2_6 , + dout3 => dout3_6 , + dout4 => dout4_6 , + dout5 => dout5_6 , + dout6 => dout6_6 + ); + +-- Register file 7. +regfile_7_i : regfile + Generic map ( + -- Data width. + B => B , + -- Map size. + N => N + ) + Port map ( + -- Clock. + clk => clk , + + -- Read address. + addr0 => addr0 , + addr1 => addr1 , + addr2 => addr2 , + addr3 => addr3 , + addr4 => addr4 , + addr5 => addr5 , + addr6 => addr6 , + + -- Write address. + addr7 => addr7 , + + -- Write data. + din7 => din7 , + wen7 => wen7_7 , + + -- Output registers. + dout0 => dout0_7 , + dout1 => dout1_7 , + dout2 => dout2_7 , + dout3 => dout3_7 , + dout4 => dout4_7 , + dout5 => dout5_7 , + dout6 => dout6_7 + ); + + +-- Registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + -- Pipe on page selection. + pnum_r <= (others => '0'); + else + -- Pipe on page selection. + pnum_r <= pnum; + end if; + end if; +end process; + +-- Muxed write enable signals. +wen7_0 <= wen7 when pnum = "000" else '0'; +wen7_1 <= wen7 when pnum = "001" else '0'; +wen7_2 <= wen7 when pnum = "010" else '0'; +wen7_3 <= wen7 when pnum = "011" else '0'; +wen7_4 <= wen7 when pnum = "100" else '0'; +wen7_5 <= wen7 when pnum = "101" else '0'; +wen7_6 <= wen7 when pnum = "110" else '0'; +wen7_7 <= wen7 when pnum = "111" else '0'; + +-- Muxed output data. +dout0_i <= dout0_0 when pnum_r = "000" else + dout0_1 when pnum_r = "001" else + dout0_2 when pnum_r = "010" else + dout0_3 when pnum_r = "011" else + dout0_4 when pnum_r = "100" else + dout0_5 when pnum_r = "101" else + dout0_6 when pnum_r = "110" else + dout0_7; + +dout1_i <= dout1_0 when pnum_r = "000" else + dout1_1 when pnum_r = "001" else + dout1_2 when pnum_r = "010" else + dout1_3 when pnum_r = "011" else + dout1_4 when pnum_r = "100" else + dout1_5 when pnum_r = "101" else + dout1_6 when pnum_r = "110" else + dout1_7; + +dout2_i <= dout2_0 when pnum_r = "000" else + dout2_1 when pnum_r = "001" else + dout2_2 when pnum_r = "010" else + dout2_3 when pnum_r = "011" else + dout2_4 when pnum_r = "100" else + dout2_5 when pnum_r = "101" else + dout2_6 when pnum_r = "110" else + dout2_7; + +dout3_i <= dout3_0 when pnum_r = "000" else + dout3_1 when pnum_r = "001" else + dout3_2 when pnum_r = "010" else + dout3_3 when pnum_r = "011" else + dout3_4 when pnum_r = "100" else + dout3_5 when pnum_r = "101" else + dout3_6 when pnum_r = "110" else + dout3_7; + +dout4_i <= dout4_0 when pnum_r = "000" else + dout4_1 when pnum_r = "001" else + dout4_2 when pnum_r = "010" else + dout4_3 when pnum_r = "011" else + dout4_4 when pnum_r = "100" else + dout4_5 when pnum_r = "101" else + dout4_6 when pnum_r = "110" else + dout4_7; + +dout5_i <= dout5_0 when pnum_r = "000" else + dout5_1 when pnum_r = "001" else + dout5_2 when pnum_r = "010" else + dout5_3 when pnum_r = "011" else + dout5_4 when pnum_r = "100" else + dout5_5 when pnum_r = "101" else + dout5_6 when pnum_r = "110" else + dout5_7; + +dout6_i <= dout6_0 when pnum_r = "000" else + dout6_1 when pnum_r = "001" else + dout6_2 when pnum_r = "010" else + dout6_3 when pnum_r = "011" else + dout6_4 when pnum_r = "100" else + dout6_5 when pnum_r = "101" else + dout6_6 when pnum_r = "110" else + dout6_7; + +-- Assign outputs. +dout0 <= dout0_i; +dout1 <= dout1_i; +dout2 <= dout2_i; +dout3 <= dout3_i; +dout4 <= dout4_i; +dout5 <= dout5_i; +dout6 <= dout6_i; + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/s_axis_read.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/s_axis_read.vhd new file mode 100644 index 0000000..74d52b1 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/s_axis_read.vhd @@ -0,0 +1,53 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity s_axis_read is + Generic ( + -- Data width. + B : Integer := 16 + ); + Port ( + -- Clock and reset. + clk : in std_logic; + rstn : in std_logic; + + -- AXIS Slave. + s_axis_tdata : in std_logic_vector (B-1 downto 0); + s_axis_tvalid : in std_logic; + s_axis_tready : out std_logic; + + -- Output data. + dout : out std_logic_vector (B-1 downto 0) + ); +end s_axis_read; + +architecture rtl of s_axis_read is + +-- Data register. +signal data_r : std_logic_vector (B-1 downto 0); + +begin + +-- Registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + -- Data register. + data_r <= (others => '0'); + else + -- Data register. + if ( s_axis_tvalid = '1' ) then + data_r <= s_axis_tdata; + end if; + end if; + end if; +end process; + +-- Assign outputs. +s_axis_tready <= '1'; +dout <= data_r; + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/soft/compile.pl b/firmware/ip/axis_tproc64x32_x8_v1/src/soft/compile.pl new file mode 100644 index 0000000..6c417c6 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/soft/compile.pl @@ -0,0 +1,824 @@ +#!/usr/bin/perl + +# Input program file. +open(FD,"<","$ARGV[0]"); +@lines = ; + +# Output binary file. +$out_file = $ARGV[0]; +$out_file =~ s/.asm/.bin/; +open(FD_OUT,">","$out_file"); + +# Output dump file. +$out_file_dump = $out_file . "-dump"; +open(FD_OUT_DUMP,">","$out_file_dump"); + +# Hash for data structures. +my @hash = (); + +# Instruction coding. +# I-type. +$hash{instructions}{pushi}{bin} = "00010000"; +$hash{instructions}{popi}{bin} = "00010001"; +$hash{instructions}{mathi}{bin} = "00010010"; +$hash{instructions}{seti}{bin} = "00010011"; +$hash{instructions}{synci}{bin} = "00010100"; +$hash{instructions}{waiti}{bin} = "00010101"; +$hash{instructions}{bitwi}{bin} = "00010110"; +$hash{instructions}{memri}{bin} = "00010111"; +$hash{instructions}{memwi}{bin} = "00011000"; +$hash{instructions}{regwi}{bin} = "00011001"; +$hash{instructions}{setbi}{bin} = "00011010"; + +# J-type. +$hash{instructions}{loopnz}{bin} = "00110000"; +$hash{instructions}{condj}{bin} = "00110001"; +$hash{instructions}{end}{bin} = "00111111"; + +# R-type. +$hash{instructions}{math}{bin} = "01010000"; +$hash{instructions}{set}{bin} = "01010001"; +$hash{instructions}{sync}{bin} = "01010010"; +$hash{instructions}{read}{bin} = "01010011"; +$hash{instructions}{wait}{bin} = "01010100"; +$hash{instructions}{bitw}{bin} = "01010101"; +$hash{instructions}{memr}{bin} = "01010110"; +$hash{instructions}{memw}{bin} = "01010111"; +$hash{instructions}{setb}{bin} = "01011000"; + +###################################### +### First pass: parse instructions ### +###################################### +my $addr = 0; +foreach $line (@lines) +{ + chomp ($line); + + # Empty lines. + if ( $line =~ m/^\s*$/ ) + { + + } + + # Comments. + elsif ( $line =~ m/^\s*\/\// ) + { + #print "$line\n"; + } + + # Tagged instruction (for Jump). + elsif ( $line =~ m/\s*(.+)\s*:(.+);/ ) + { + my $ref = $1; + my $inst = $2; + + # Add reference entry into hash. + $hash{refs}{$ref} = $addr; + + # Parse instruction. + &parse_inst(\%hash, $inst, $addr); + + # Increment memory address. + $addr++; + } + else + { + my $inst = $line; + + # Parse instruction. + &parse_inst(\%hash, $inst, $addr); + + # Increment memory address. + $addr++; + } +} + +####################################### +### Second Pass: resolve references ### +####################################### +&resolve_refs(\%hash); + +############################### +### Convert to machine code ### +############################### +&convert(\%hash); + +############################ +### Generate output file ### +############################ +@mems = (sort {$a <=> $b} keys %{$hash{memory}}); +foreach $mem (@mems) +{ + $inst = $hash{memory}{$mem}{orig}; + $bin = $hash{memory}{$mem}{bin}; + print FD_OUT "$bin\n"; +} + +########################## +### Generate DUMP file ### +########################## +print FD_OUT_DUMP "#######################\n"; +print FD_OUT_DUMP "### Memory Contents ###\n"; +print FD_OUT_DUMP "#######################\n"; +@mems = (sort {$a <=> $b} keys %{$hash{memory}}); +foreach $mem (@mems) +{ + $inst = $hash{memory}{$mem}{orig}; + $bin = $hash{memory}{$mem}{bin}; + $hex = $hash{memory}{$mem}{hex}; + print FD_OUT_DUMP "$mem\t: $hex -> $inst\n"; +} +print FD_OUT_DUMP "\n"; + +print FD_OUT_DUMP "###############\n"; +print FD_OUT_DUMP "### Symbols ###\n"; +print FD_OUT_DUMP "###############\n"; +@refs = keys %{$hash{refs}}; +foreach $ref (@refs) +{ + $addr = $hash{refs}{$ref}; + print FD_OUT_DUMP "$ref\t: $addr\n"; +} +print FD_OUT_DUMP "\n"; + +#################### +### Sub Routines ### +#################### +sub parse_inst +{ + my ($hash_ref, $inst, $addr) = @_; + + # Remove leading spaces from instruction. + $inst =~ s/^\s+//; + + # Remove trailing comments from instruction. + $inst =~ s/\s*\/\/.+$//; + + # Remove trailing ; + $inst =~ s/;//; + + ############## + ### I-Type ### + ############## + + # pushi p, $ra, $rb, imm + if ( $inst =~ m/pushi\s+(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)\s*,\s*(\-{0,1}\d+)/ ) + { + my $page = $1; + my $ra = $2; + my $rb = $3; + my $imm = $4; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "I-type:pushi:$page:0:0:$rb:$ra:0:$imm"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # popi p, $r + if ( $inst =~ m/popi\s+(\d+)\s*,\s*\$(\d+)/ ) + { + my $page = $1; + my $r = $2; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "I-type:popi:$page:0:0:$r:0:0:0"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # mathi p, $ra, $rb oper imm. + if ( $inst =~ m/mathi\s+(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)\s*([\+\-\*])\s*(0?x?\-?[0-9a-fA-F]+)/) + { + my $page = $1; + my $ra = $2; + my $rb = $3; + my $oper = $4; + my $imm = $5; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "I-type:mathi:$page:0:$oper:$ra:$rb:0:$imm"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # seti ch, p, $r, t + if ( $inst =~ m/seti\s+(\d+)\s*,\s*(\d+)\s*,\s*\$(\d+)\s*,\s*(0?x?[0-9a-fA-F]+)/) + { + my $ch = $1; + my $page = $2; + my $ra = $3; + my $t = $4; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "I-type:seti:$page:$ch:0:0:$ra:0:$t"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # synci t + if ( $inst =~ m/synci\s+(\d+)/) + { + my $t = $1; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "I-type:synci:0:0:0:0:0:0:$t"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # waiti ch, t + if ( $inst =~ m/waiti\s+(\d+),\s*(\d+)/) + { + my $ch = $1; + my $t = $2; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "I-type:waiti:0:$ch:0:0:0:0:$t"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # bitwi p, $ra, $rb oper imm. + if ( $inst =~ m/bitwi\s+(\d+)\s*,\s*\$(\d+),\s*\$(\d+)\s*([&|<>^]+)\s*(0?x?\-?[0-9a-fA-F]+)/) + { + + my $page = $1; + my $ra = $2; + my $rb = $3; + my $oper = $4; + my $imm = $5; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "I-type:bitwi:$page:0:$oper:$ra:$rb:0:$imm"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # bitwi p, $ra, ~imm. + if ( $inst =~ m/bitwi\s+(\d+)\s*,\s*\$(\d+),\s*~\s*(0?x?\-?[0-9a-fA-F]+)/) + { + + my $page = $1; + my $ra = $2; + my $oper = "~"; + my $imm = $3; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "I-type:bitwi:$page:0:$oper:$ra:0:0:$imm"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # memri p, $r, imm. + if ( $inst =~ m/memri\s+(\d+)\s*,\s*\$(\d+),\s*(0?x?\-?[0-9a-fA-F]+)/) + { + + my $page = $1; + my $r = $2; + my $imm = $3; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "I-type:memri:$page:0:0:$r:0:0:$imm"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # memwi p, $r, imm. + if ( $inst =~ m/memwi\s+(\d+)\s*,\s*\$(\d+),\s*(0?x?\-?[0-9a-fA-F]+)/) + { + + my $page = $1; + my $r = $2; + my $imm = $3; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "I-type:memwi:$page:0:0:0:0:$r:$imm"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # regwi p, $r, imm. + if ( $inst =~ m/regwi\s+(\d+)\s*,\s*\$(\d+),\s*(0?x?\-?[0-9a-fA-F]+)/) + { + + my $page = $1; + my $r = $2; + my $imm = $3; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "I-type:regwi:$page:0:0:$r:0:0:$imm"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # setbi ch, p, $r, t + if ( $inst =~ m/setbi\s+(\d+)\s*,\s*(\d+)\s*,\s*\$(\d+)\s*,\s*(0?x?[0-9a-fA-F]+)/) + { + my $ch = $1; + my $page = $2; + my $ra = $3; + my $t = $4; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "I-type:setbi:$page:$ch:0:0:$ra:0:$t"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + ############## + ### J-Type ### + ############## + + # loopnz p, $r, @label + if ( $inst =~ m/loopnz\s+(\d+)\s*,\s*\$(\d+)\s*,\s*\@(.+)/) + { + my $page = $1; + my $oper = "+"; + my $r = $2; + my $label = $3; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "J-type:loopnz:$page:$oper:$r:$r:0:\@$label"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # condj p, $ra op $rb, @label + if ( $inst =~ m/condj\s+(\d+)\s*,\s*\$(\d+)\s*([<>=!]+)\s*\$(\d+)\s*,\s*\@(.+)/) + { + my $page = $1; + my $ra = $2; + my $op = $3; + my $rb = $4; + my $label = $5; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "J-type:condj:$page:$op:0:$ra:$rb:\@$label"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # end + if ( $inst =~ m/end/ ) + { + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "J-type:end:0:0:0:0:0:0"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + ############## + ### R-Type ### + ############## + + # math p, $ra, $rb oper $rc + if ( $inst =~ m/math\s+(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+)\s*([\+\-\*]+)\s*\$(\d+)/) + { + my $page = $1; + my $ra = $2; + my $rb = $3; + my $oper = $4; + my $rc = $5; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "R-type:math:$page:0:$oper:$ra:$rb:$rc:0:0:0:0:0"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # set ch, p, $ra, $rb, $rc, $rd, $re, $rt + if ( $inst =~ m/set\s+(\d+)\s*,\s*(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+),\s*\$(\d+),\s*\$(\d+),\s*\$(\d+),\s*\$(\d+)/) + { + my $ch = $1; + my $page = $2; + my $ra = $3; + my $rb = $4; + my $rc = $5; + my $rd = $6; + my $re = $7; + my $rt = $8; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "R-type:set:$page:$ch:0:0:$ra:$rt:$rb:$rc:$rd:$re:0"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # sync p, $r + if ( $inst =~ m/sync\s+(\d+)\s*,\s*\$(\d+)/) + { + my $page = $1; + my $r = $2; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "R-type:sync:$page:0:0:0:0:$r:0:0:0:0:0"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # read ch, p, oper $r + if ( $inst =~ m/read\s+(\d+)\s*,\s*(\d+)\s*,\s*(upper|lower)\s+\$(\d+)/) + { + my $ch = $1; + my $page = $2; + my $oper = $3; + my $ra = $4; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "R-type:read:$page:$ch:$oper:$ra:0:0:0:0:0:0:0"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # wait ch, p, $r + if ( $inst =~ m/wait\s+(\d+)\s*,\s*(\d+)\s*,\s*\$(\d+)/) + { + my $ch = $1; + my $page = $2; + my $r = $3; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "R-type:wait:$page:$ch:0:0:0:$r:0:0:0:0:0"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # bitw p, $ra, $rb oper $rc + if ( $inst =~ m/bitw\s+(\d+)\s*,\s*\$(\d+),\s*\$(\d+)\s*([&|<>^]+)\s*\$(\d+)/) + { + + my $page = $1; + my $ra = $2; + my $rb = $3; + my $oper = $4; + my $rc = $5; + + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "R-type:bitw:$page:0:$oper:$ra:$rb:$rc:0:0:0:0:0"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # bitw p, $ra, ~$rb. + if ( $inst =~ m/bitw\s+(\d+)\s*,\s*\$(\d+),\s*~\s*\$(\d+)/) + { + + my $page = $1; + my $ra = $2; + my $oper = "~"; + my $rb = $3; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "R-type:bitw:$page:0:$oper:$ra:0:$rb:0:0:0:0:0"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # memr p, $ra, $rb + if ( $inst =~ m/memr\s+(\d+)\s*,\s*\$(\d+),\s*\$(\d+)\s*/) + { + + my $page = $1; + my $ra = $2; + my $rb = $3; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "R-type:memr:$page:0:0:$ra:$rb:0:0:0:0:0:0"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # memr p, $ra, $rb + if ( $inst =~ m/memw\s+(\d+)\s*,\s*\$(\d+),\s*\$(\d+)\s*/) + { + + my $page = $1; + my $ra = $2; + my $rb = $3; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "R-type:memw:$page:0:0:0:$rb:$ra:0:0:0:0:0"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } + + # setb ch, p, $ra, $rb, $rc, $rd, $re, $rt + if ( $inst =~ m/setb\s+(\d+)\s*,\s*(\d+)\s*,\s*\$(\d+)\s*,\s*\$(\d+),\s*\$(\d+),\s*\$(\d+),\s*\$(\d+),\s*\$(\d+)/) + { + my $ch = $1; + my $page = $2; + my $ra = $3; + my $rb = $4; + my $rc = $5; + my $rd = $6; + my $re = $7; + my $rt = $8; + + # Push instruction into hash. + $$hash_ref{memory}{$addr}{inst} = "R-type:setb:$page:$ch:0:0:$ra:$rt:$rb:$rc:$rd:$re:0"; + $$hash_ref{memory}{$addr}{orig} = $inst; + } +} + +sub resolve_refs +{ + my ($hash_ref) = @_; + + my @mems = (sort {$a <=> $b} keys %{$$hash_ref{memory}}); + foreach $mem (@mems) + { + my $inst = $hash{memory}{$mem}{inst}; + + if ( $inst =~ m/\@(.+)$/ ) + { + my $ref = $1; + + # Get symbol from table. + if ( exists $$hash_ref{refs}{$ref} ) + { + # Get symbol address. + my $addr = $$hash_ref{refs}{$ref}; + + # Replace symbol with actual address. + $inst =~ s/\@(.+)$/$addr/; + + # Write value back into hash. + $$hash_ref{memory}{$mem}{inst} = $inst; + } + else + { + print "ERROR: Could not resolve $ref symbol. Aborting.\n"; + exit(0); + } + } + } +} + +sub convert +{ + my ($hash_ref) = @_; + + my @mems = (sort {$a <=> $b} keys %{$$hash_ref{memory}}); + foreach $mem (@mems) + { + # Get instructions. + my $inst = $$hash_ref{memory}{$mem}{inst}; + + # Split parameters. + my @params = split(/:/,$inst); + + # I-type instruction. + # I-type:opcode:page:channel:oper:ra:rb:imm. + if ( $params[0] eq "I-type" ) + { + # Translate instruction to machine code. + if ( exists $$hash_ref{instructions}{$params[1]} ) + { + my $i = $$hash_ref{instructions}{$params[1]}{bin}; + my $page = &unsigned2bin($params[2],3); + my $ch = &unsigned2bin($params[3],3); + my $oper = &oper2bin($params[4]); + my $ra = &unsigned2bin($params[5],5); + my $rb = &unsigned2bin($params[6],5); + my $rc = &unsigned2bin($params[7],5); + my $imm = &integer2bin($params[8],31); + + my $code = $i . $page . $ch . $oper . $ra . $rb . $rc . $imm; + my $code_h = sprintf("%x", oct("0b$code")); + + # Write binary value back into hash. + $$hash_ref{memory}{$mem}{bin} = $code; + $$hash_ref{memory}{$mem}{hex} = $code_h; + } + else + { + print "ERROR: Instruction $params[1] not found in catalog. Aborting.\n"; + exit(1); + } + } + + # J-type instruction. + # J-type:opcode:page:oper:ra:rb:rc:addr. + if ( $params[0] eq "J-type" ) + { + # Translate instruction to machine code. + if ( exists $$hash_ref{instructions}{$params[1]} ) + { + my $i = $$hash_ref{instructions}{$params[1]}{bin}; + my $page = &unsigned2bin($params[2],3); + my $z3 = &unsigned2bin(0,3); + my $oper = &oper2bin($params[3]); + my $ra = &unsigned2bin($params[4],5); + my $rb = &unsigned2bin($params[5],5); + my $rc = &unsigned2bin($params[6],5); + my $z15 = &unsigned2bin(0,15); + my $addr = &unsigned2bin($params[7],16); + + my $code = $i . $page . $z3 . $oper . $ra . $rb . $rc . $z15 . $addr; + my $code_h = sprintf("%x", oct("0b$code")); + + # Write binary value back into hash. + $$hash_ref{memory}{$mem}{bin} = $code; + $$hash_ref{memory}{$mem}{hex} = $code_h; + } + else + { + print "ERROR: Instruction $params[1] not found in catalog. Aborting.\n"; + exit(1); + } + + } + + # R-type instruction. + # R-type:opcode:page:channel:oper:ra:rb:rc:rd:re:rf:rg:rh. + if ( $params[0] eq "R-type" ) + { + # Translate instruction to machine code. + if ( exists $$hash_ref{instructions}{$params[1]} ) + { + my $i = $$hash_ref{instructions}{$params[1]}{bin}; + my $page = &unsigned2bin($params[2],3); + my $ch = &unsigned2bin($params[3],3); + my $oper = &oper2bin($params[4]); + my $ra = &unsigned2bin($params[5],5); + my $rb = &unsigned2bin($params[6],5); + my $rc = &unsigned2bin($params[7],5); + my $rd = &unsigned2bin($params[8],5); + my $re = &unsigned2bin($params[9],5); + my $rf = &unsigned2bin($params[10],5); + my $rg = &unsigned2bin($params[11],5); + my $rh = &unsigned2bin($params[12],5); + my $z6 = &unsigned2bin(0,6); + + my $code = $i . $page . $ch . $oper . $ra . $rb . $rc . $rd . $re . $rf . $rg . $rh . $z6; + my $code_h = sprintf("%x", oct("0b$code")); + + # Write binary value back into hash. + $$hash_ref{memory}{$mem}{bin} = $code; + $$hash_ref{memory}{$mem}{hex} = $code_h; + } + else + { + print "ERROR: Instruction $params[1] not found in catalog. Aborting.\n"; + exit(1); + } + } + + } +} + +sub integer2bin +{ + my $dec = shift; + my $bits = shift; + + # Number goes from -2^(bits-1) to 2^(bits-1) - 1 + $min = -2**($bits-1); + $max = 2**($bits-1) - 1; + + # Check if number is 0x form. + if ( $dec =~ m/0x/ ) + { + my $mmax = 2**$bits - 1; + + $dec = hex($dec); + + if ( $dec > $mmax ) + { + print "ERROR: number $dec bigger than $mmax\n"; + exit(1); + } + + # Perform conversion. + $f = "." . $bits . "b"; + return sprintf("%$f", $dec); + } + + # Check maximum and minimum. + if ( $dec < $min ) + { + print "ERROR: number $dec smaller than $min\n"; + exit(1); + } + + if ( $dec > $max ) + { + print "ERROR: number $dec bigger than $max\n"; + exit(1); + } + + # Check if number is negative. + if ( $dec < 0 ) + { + $dec = $dec + 2**$bits; + } + + # Perform conversion. + $f = "." . $bits . "b"; + return sprintf("%$f", $dec); +} + +sub unsigned2bin +{ + my $dec = shift; + my $bits = shift; + + # Number goes from 0 to 2^(bits-1) - 1 + $max = 2**$bits - 1; + + # Check if number is 0x form. + if ( $dec =~ m/0x/ ) + { + $dec = hex($dec); + } + + if ( $dec > $max ) + { + print "ERROR: number $dec bigger than $max\n"; + exit(1); + } + + # Perform conversion. + $f = "." . $bits . "b"; + return sprintf("%$f", $dec); +} + +sub oper2bin +{ + my $op = shift; + + if ( $op eq "0" ) + { + return "0000"; + } + + # Conditional block. + elsif ( $op eq ">" ) + { + return "0000"; + } + elsif ( $op eq ">=" ) + { + return "0001"; + } + elsif ( $op eq "<" ) + { + return "0010"; + } + elsif ( $op eq "<=" ) + { + return "0011"; + } + elsif ( $op eq "==" ) + { + return "0100"; + } + elsif ( $op eq "!=" ) + { + return "0101"; + } + + # Alu (math). + elsif ( $op eq "+" ) + { + return "1000"; + } + + elsif ( $op eq "-" ) + { + return "1001"; + } + + elsif ( $op eq "*" ) + { + return "1010"; + } + + # Alu (bitw). + elsif ( $op eq "&" ) + { + return "0000"; + } + + elsif ( $op eq "|" ) + { + return "0001"; + } + + elsif ( $op eq "^" ) + { + return "0010"; + } + + elsif ( $op eq "~" ) + { + return "0011"; + } + + elsif ( $op eq "<<" ) + { + return "0100"; + } + + elsif ( $op eq ">>" ) + { + return "0101"; + } + + # Read (upper/lower bits). + elsif ( $op eq "upper" ) + { + return "1010"; + } + + elsif ( $op eq "lower" ) + { + return "0101"; + } + + # Not recognized. + else + { + print "ERROR: operation $op not recognized. Aborting\n"; + } + +} + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.asm b/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.asm new file mode 100644 index 0000000..04e24b2 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.asm @@ -0,0 +1,15 @@ + // $1: periodic mode. + regwi 0, $1, 33; + regwi 0, $2, 1; + bitwi 0, $2, $2 << 16; + bitw 0, $1, $1 | $2; + + // $4: non-periodic mode. + regwi 0, $4, 500; + + regwi 1, $1, 100; // i +LOOP: setbi 7, 0, $4, 0; + loopnz 1, $1, @LOOP; + + end; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.asm.old b/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.asm.old new file mode 100644 index 0000000..bf00ba5 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.asm.old @@ -0,0 +1,84 @@ +// Read input ports. + read 0, 2, upper $3; + read 0, 2, lower $4; + read 1, 0, upper $3; + read 1, 0, lower $4; + read 2, 0, upper $5; + read 2, 0, lower $6; + read 3, 1, upper $1; + read 3, 1, lower $2; + +// Basic math. + regwi 0, $1, 0x1234; + regwi 0, $2, -1234; + regwi 0, $3, 7; + +LOOP: math 0, $1, $1 + $2; + loopnz 0, $3, @LOOP; + + // Some time offset to start. + synci 1000; + +// Nested loops and stack. + regwi 0, $9, 0; // memory address. + regwi 0, $1, -5000; // df + regwi 0, $3, 34; // dg + regwi 0, $5, 100; // dn + regwi 0, $8, 50; // t + + regwi 0, $2, 120000; // freq + regwi 0, $7, 5; // i = 5 + +// Loop freq. +FREQ: math 0, $2, $2 + $1; // freq = freq + df + regwi 0, $4, 120; // gain = 120 + pushi 0, $7, $7, 3; // i -> stack, j = 3 + + // Loop gain. + GAIN: math 0, $4, $4 + $3; // gain = gain + dg + regwi 0, $6, 25; // nsamples = 25 + pushi 0, $7, $7, 6; // j -> stack, k = 6 + + // Loop nsamp. + NSAMP: math 0, $6, $6 + $5; // nsamp = nsamp + dn + // Output value on port. + set 0, 0, $2, $0, $4, $0, $6, $7; + synci 150; + loopnz 0, $7, @NSAMP; // loop k + + popi 0, $7; // stack -> j + loopnz 0, $7, @GAIN; // loop j + + popi 0, $7; // stack -> i + memw 0, $2, $9; // freq -> mem[$9] + mathi 0, $9, $9 + 1; + loopnz 0, $7, @FREQ; // loop i + +// Signal end of first pass. + regwi 0, $1, 0x0ABCD; + regwi 0, $2, 0x01234; + memwi 0, $1, 100; // mem[100] = 0x0ABCD + memwi 0, $0, 101; // mem[101] = 0 +WAITF0: memri 0, $1, 101; // $1 = mem[101] + condj 0, $1 != $2, @WAITF0; + +// Wait memory upload. + regwi 0, $1, 0x0ABCD; + regwi 0, $2, 0x01234; + memwi 0, $1, 100; // mem[100] = 0x0ABCD + memwi 0, $0, 101; // mem[101] = 0 +WAITF1: memri 0, $1, 101; // $1 = mem[101] + condj 0, $1 != $2, @WAITF1; + +// Read/modify/write. + regwi 0, $1, 0; // Address. + regwi 0, $2, 54; // i. +LOOP0: memr 0, $3, $1; // $3 = mem[$1] + mathi 0, $3, $3*2; + memw 0, $3, $1; // mem[$1] = $3. + mathi 0, $1, $1 + 1; // Address = address + 1. + loopnz 0, $2, @LOOP0; + + // End of program. + end; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.bin b/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.bin new file mode 100644 index 0000000..135ef80 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.bin @@ -0,0 +1,9 @@ +0001100100000000000000100000000000000000000000000000000000100001 +0001100100000000000001000000000000000000000000000000000000000001 +0001011000000001000001000010000000000000000000000000000000010000 +0101010100000000010000100001000100000000000000000000000000000000 +0001100100000000000010000000000000000000000000000000000111110100 +0001100100100000000000100000000000000000000000000000000001100100 +0001101000011100000000000100000000000000000000000000000000000000 +0011000000100010000000100001000000000000000000000000000000000110 +0011111100000000000000000000000000000000000000000000000000000000 diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.bin-dump b/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.bin-dump new file mode 100644 index 0000000..9c46e20 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/soft/prog.bin-dump @@ -0,0 +1,18 @@ +####################### +### Memory Contents ### +####################### +0 : 1900020000000021 -> regwi 0, $1, 33 +1 : 1900040000000001 -> regwi 0, $2, 1 +2 : 1601042000000010 -> bitwi 0, $2, $2 << 16 +3 : 5500421100000000 -> bitw 0, $1, $1 | $2 +4 : 19000800000001f4 -> regwi 0, $4, 500 +5 : 1920020000000064 -> regwi 1, $1, 100 +6 : 1a1c004000000000 -> setbi 7, 0, $4, 0 +7 : 3022021000000006 -> loopnz 1, $1, @LOOP +8 : 3f00000000000000 -> end + +############### +### Symbols ### +############### +LOOP : 6 + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/stack.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/stack.vhd new file mode 100644 index 0000000..fe2f5b6 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/stack.vhd @@ -0,0 +1,131 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Stack block. +-- +-- Number of words: 256 (8 bits). +-- op: +-- * 0 : pop operation. +-- * 1 : push operation. + +entity stack is + Generic ( + -- Data width. + B : Integer := 16 + ); + Port ( + -- Clock and reset. + clk : in std_logic; + rstn : in std_logic; + + -- Enable and operation. + en : in std_logic; + op : in std_logic; + + -- Input/Output data. + din : in std_logic_vector (B-1 downto 0); + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + empty : out std_logic; + full : out std_logic + ); +end stack; + +architecture rtl of stack is + +-- Bram. +component bram is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in std_logic; + ena : in std_logic; + wea : in std_logic; + addra : in std_logic_vector (N-1 downto 0); + dia : in std_logic_vector (B-1 downto 0); + doa : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Memory signals. +signal mem_addr : std_logic_vector (7 downto 0); + +-- Stack pointer (points to the address where the next data is written). +signal sp : unsigned (7 downto 0); +signal sp_1 : unsigned (7 downto 0); + +-- Empty/full. +signal empty_i : std_logic; +signal full_i : std_logic; + +begin + +-- Bram. +bram_i : bram + Generic map ( + -- Memory address size. + N => 8 , + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => en , + wea => op , + addra => mem_addr , + dia => din , + doa => dout + ); + +-- Registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + -- Stack pointer. + sp <= (others => '1'); + else + -- Stack pointer. + if ( en = '1' ) then + if ( op = '1' ) then + -- Push. + if ( full_i = '0' ) then + -- If not full. + sp <= sp - 1; + end if; + else + -- Pop. + if ( empty_i = '0' ) then + -- If not empty. + sp <= sp + 1; + end if; + end if; + end if; + + end if; + end if; +end process; + +-- Stack pointer + 1 (read address). +sp_1 <= sp + 1; + +-- Mux for memory address. +mem_addr <= std_logic_vector (sp) when op = '1' else + std_logic_vector (sp_1); + +-- Empty/full flags. +empty_i <= '1' when sp = 255 else '0'; +full_i <= '1' when sp = 0 else '0'; + +-- Assign outputs. +empty <= empty_i; +full <= full_i; + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/synchronizer_n.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/synchronizer_n.vhd new file mode 100644 index 0000000..925425d --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/synchronizer_n.vhd @@ -0,0 +1,42 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library common_lib; +use common_lib.all; + +entity synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end synchronizer_n; + +architecture rtl of synchronizer_n is + +-- Internal register. +signal data_int_reg : std_logic_vector (N-1 downto 0); + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/tb/tb.sv b/firmware/ip/axis_tproc64x32_x8_v1/src/tb/tb.sv new file mode 100644 index 0000000..7a50b85 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/tb/tb.sv @@ -0,0 +1,708 @@ +// VIP: axi_mst_0 +// VIP: axis_mst_0 +// VIP: axis_slv_0 +// DUT: axis_tproc6664_x8 +// IF: s_axi -> axi_mst_0 +// IF: m0_axis -> axis_slv_0 +// IF: s0_axis -> axis_mst_0 + +import axi_vip_pkg::*; +import axi4stream_vip_pkg::*; +import axi_mst_0_pkg::*; +import axis_mst_0_pkg::*; +import axis_slv_0_pkg::*; + +module tb(); + +localparam PMEM_N = 16; // Program Memory Depth. +localparam DMEM_N = 10; // Data Memory Depth. +localparam DMEM_OFFSET = 256; + +/////////////////////// +// s_axi_aclk domain // +/////////////////////// +reg s_axi_aclk; +reg s_axi_aresetn; + +wire [31:0] s_axi_awaddr; +wire [2:0] s_axi_awprot; +wire s_axi_awvalid; +wire s_axi_awready; + +wire [31:0] s_axi_wdata; +wire [3:0] s_axi_wstrb; +wire s_axi_wvalid; +wire s_axi_wready; + +wire [1:0] s_axi_bresp; +wire s_axi_bvalid; +wire s_axi_bready; + +wire [31:0] s_axi_araddr; +wire [2:0] s_axi_arprot; +wire s_axi_arvalid; +wire s_axi_arready; + +wire [31:0] s_axi_rdata; +wire [1:0] s_axi_rresp; +wire s_axi_rvalid; +wire s_axi_rready; + +wire [31:0] s0_axis_tdata; +wire s0_axis_tlast; +wire s0_axis_tvalid; +wire s0_axis_tready; + +wire [31:0] m0_axis_tdata; +wire m0_axis_tlast; +wire m0_axis_tvalid; +wire m0_axis_tready; + +///////////////// +// aclk domain // +///////////////// +reg aclk; +reg aresetn; + +reg start; + +wire [PMEM_N-1:0] pmem_addr; +wire [63:0] pmem_do; + +reg [63:0] s1_axis_tdata; +reg s1_axis_tvalid; +wire s1_axis_tready; + +reg [63:0] s2_axis_tdata; +reg s2_axis_tvalid; +wire s2_axis_tready; + +reg [63:0] s3_axis_tdata; +reg s3_axis_tvalid; +wire s3_axis_tready; + +reg [63:0] s4_axis_tdata; +reg s4_axis_tvalid; +wire s4_axis_tready; + +wire [159:0] m1_axis_tdata; +wire m1_axis_tvalid; +reg m1_axis_tready; + +wire [159:0] m2_axis_tdata; +wire m2_axis_tvalid; +reg m2_axis_tready; + +wire [159:0] m3_axis_tdata; +wire m3_axis_tvalid; +reg m3_axis_tready; + +wire [159:0] m4_axis_tdata; +wire m4_axis_tvalid; +reg m4_axis_tready; + +wire [159:0] m5_axis_tdata; +wire m5_axis_tvalid; +reg m5_axis_tready; + +wire [159:0] m6_axis_tdata; +wire m6_axis_tvalid; +reg m6_axis_tready; + +wire [159:0] m7_axis_tdata; +wire m7_axis_tvalid; +reg m7_axis_tready; + +wire [159:0] m8_axis_tdata; +wire m8_axis_tvalid; +wire m8_axis_tready; + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +reg[31:0] data; +xil_axi_resp_t resp; + +// Ready generator for axis slave. +axi4stream_ready_gen ready_gen_0; +// Program memory. +bram + #( + // Memory address size. + .N (PMEM_N ), + // Data width. + .B (64 ) + ) + pmem_i ( + .clk (aclk ), + .ena (1'b1 ), + .wea (1'b0 ), + .addra ({3'b000,pmem_addr[PMEM_N-1:3]} ), + .dia ({64{1'b0}} ), + .doa (pmem_do ) + ); + +// AXIS master. +axis_mst_0 axis_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axis_tdata (s0_axis_tdata ), + .m_axis_tlast (s0_axis_tlast ), + .m_axis_tready (s0_axis_tready ), + .m_axis_tstrb ( ), + .m_axis_tvalid (s0_axis_tvalid ) + ); + +// AXIS slave. +axis_slv_0 axis_slv_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .s_axis_tdata (m0_axis_tdata ), + .s_axis_tlast (m0_axis_tlast ), + .s_axis_tready (m0_axis_tready ), + .s_axis_tstrb ( ), + .s_axis_tvalid (m0_axis_tvalid ) + ); + +// AXI master. +axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + +// DUT. +axis_tproc64x32_x8 + DUT + ( + /////////////////////// + // s_axi_aclk domain // + /////////////////////// + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + + // AXI Slave I/F for configuration. + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_awready (s_axi_awready ), + + .s_axi_wdata (s_axi_wdata ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + .s_axi_wready (s_axi_wready ), + + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_bready (s_axi_bready ), + + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_arready (s_axi_arready ), + + .s_axi_rdata (s_axi_rdata ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_rready (s_axi_rready ), + + // Slave AXIS for writing into Data Memory. + .s0_axis_tdata (s0_axis_tdata ), + .s0_axis_tlast (s0_axis_tlast ), + .s0_axis_tvalid (s0_axis_tvalid ), + .s0_axis_tready (s0_axis_tready ), + + // Master AXIS 0 to read from Data Memory. + .m0_axis_tdata (m0_axis_tdata ), + .m0_axis_tlast (m0_axis_tlast ), + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tready (m0_axis_tready ), + + ///////////////// + // aclk domain // + ///////////////// + .aclk (aclk ), + .aresetn (aresetn ), + + // Start/stop. + .start (start ), + + // Program Memory Interface. + .pmem_addr (pmem_addr ), + .pmem_do (pmem_do ), + + // Slave AXIS 0: "read" on tProcessor. + .s1_axis_tdata (s1_axis_tdata ), + .s1_axis_tvalid (s1_axis_tvalid ), + .s1_axis_tready (s1_axis_tready ), + + // Slave AXIS 1: "read" on tProcessor. + .s2_axis_tdata (s2_axis_tdata ), + .s2_axis_tvalid (s2_axis_tvalid ), + .s2_axis_tready (s2_axis_tready ), + + // Slave AXIS 2: "read" on tProcessor. + .s3_axis_tdata (s3_axis_tdata ), + .s3_axis_tvalid (s3_axis_tvalid ), + .s3_axis_tready (s3_axis_tready ), + + // Slave AXIS 3: "read" on tProcessor. + .s4_axis_tdata (s4_axis_tdata ), + .s4_axis_tvalid (s4_axis_tvalid ), + .s4_axis_tready (s4_axis_tready ), + + // Master AXIS 1 for Channel 0. + .m1_axis_tdata (m1_axis_tdata ), + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tready (m1_axis_tready ), + + // Master AXIS 2 for Channel 1. + .m2_axis_tdata (m2_axis_tdata ), + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tready (m2_axis_tready ), + + // Master AXIS 3 for Channel 2. + .m3_axis_tdata (m3_axis_tdata ), + .m3_axis_tvalid (m3_axis_tvalid ), + .m3_axis_tready (m3_axis_tready ), + + // Master AXIS 4 for Channel 3. + .m4_axis_tdata (m4_axis_tdata ), + .m4_axis_tvalid (m4_axis_tvalid ), + .m4_axis_tready (m4_axis_tready ), + + // Master AXIS 5 for Channel 4. + .m5_axis_tdata (m5_axis_tdata ), + .m5_axis_tvalid (m5_axis_tvalid ), + .m5_axis_tready (m5_axis_tready ), + + // Master AXIS 6 for Channel 5. + .m6_axis_tdata (m6_axis_tdata ), + .m6_axis_tvalid (m6_axis_tvalid ), + .m6_axis_tready (m6_axis_tready ), + + // Master AXIS 7 for Channel 6. + .m7_axis_tdata (m7_axis_tdata ), + .m7_axis_tvalid (m7_axis_tvalid ), + .m7_axis_tready (m7_axis_tready ), + + // Master AXIS 8 for Channel 7. + .m8_axis_tdata (m8_axis_tdata ), + .m8_axis_tvalid (m8_axis_tvalid ), + .m8_axis_tready (m8_axis_tready ) +); + +// Simple Signal Generator Simulator. +gen_sim + gen_sim_i + ( + .clk (aclk ), + .rstn (aresetn ), + .s_axis_tdata (m8_axis_tdata ), + .s_axis_tvalid (m8_axis_tvalid ), + .s_axis_tready (m8_axis_tready ) + ); + + +// VIP Agents +axi_mst_0_mst_t axi_mst_0_agent; +axis_mst_0_mst_t axis_mst_0_agent; +axis_slv_0_slv_t axis_slv_0_agent; + +initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + axis_mst_0_agent = new("axis_mst_0 VIP Agent",tb.axis_mst_0_i.inst.IF); + axis_slv_0_agent = new("axis_slv_0 VIP Agent",tb.axis_slv_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + axis_mst_0_agent.set_agent_tag ("axis_mst_0 VIP"); + axis_slv_0_agent.set_agent_tag ("axis_slv_0 VIP"); + + // Drive everything to 0 to avoid assertion from axi_protocol_checker. + axis_mst_0_agent.vif_proxy.set_dummy_drive_type(XIL_AXI4STREAM_VIF_DRIVE_NONE); + axis_slv_0_agent.vif_proxy.set_dummy_drive_type(XIL_AXI4STREAM_VIF_DRIVE_NONE); + + // Ready generator. + ready_gen_0 = axis_slv_0_agent.driver.create_ready("ready gen 0"); + ready_gen_0.set_ready_policy(XIL_AXI4STREAM_READY_GEN_EVENTS); + ready_gen_0.set_low_time(5); + ready_gen_0.set_event_count(6); + + // Start agents. + axi_mst_0_agent.start_master(); + axis_mst_0_agent.start_master(); + axis_slv_0_agent.start_slave(); + + // Reset sequence. + s_axi_aresetn <= 0; + aresetn <= 0; + start <= 0; + s1_axis_tdata <= 0; + s1_axis_tvalid <= 0; + s2_axis_tdata <= 0; + s2_axis_tvalid <= 0; + s3_axis_tdata <= 0; + s3_axis_tvalid <= 0; + s4_axis_tdata <= 0; + s4_axis_tvalid <= 0; + m1_axis_tready <= 1; + m2_axis_tready <= 1; + m3_axis_tready <= 1; + m4_axis_tready <= 1; + m5_axis_tready <= 1; + m6_axis_tready <= 1; + m7_axis_tready <= 1; + #1000; + s_axi_aresetn <= 1; + aresetn <= 1; + + // Load program memory. + $readmemb("../../../../../soft/prog.bin", pmem_i.RAM); + + // Change ready policy for AXIS slave. + axis_slv_0_agent.driver.send_tready(ready_gen_0); + + #300; + + // Write input ports. + @(posedge aclk) + s1_axis_tdata <= 64'h12345678_87654321; + s1_axis_tvalid <= 1; + s2_axis_tdata <= 64'h55555555_aaaaaaaa; + s2_axis_tvalid <= 1; + s3_axis_tdata <= 64'habcdef00_01234567; + s3_axis_tvalid <= 1; + s4_axis_tdata <= 64'h01012323_ababcdcd; + s4_axis_tvalid <= 1; + + @(posedge aclk) + s1_axis_tvalid <= 0; + s2_axis_tvalid <= 0; + s3_axis_tvalid <= 0; + s4_axis_tvalid <= 0; + + + // Register Map: + // + // 0 : START_SRC_REG + // 1 : START_REG + // 2 : MEM_MODE_REG + // 3 : MEM_START_REG + // 4 : MEM_ADDR_REG + // 5 : MEM_LEN_REG + + // START_SRC_REG + // * 0 : Internal Start. + // * 1 : External Start. + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*0, prot, data_wr, resp); + #10; + + // START_REG + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*1, prot, data_wr, resp); + #10; + + #50000; + + //// Read back flag to signal start of next step. + //$display("#####################"); + //$display("### Wait for flag ###"); + //$display("#####################"); + //$display("t = %0t", $time); + + //// Flag: tProcessor data memory @100. + //// Memory is accessed using the upper part of the memory map. + //// Addresses are byte-based. + //// address = DMEM_OFFSET + 4*100 + //while (1) begin + // axi_mst_0_agent.AXI4LITE_READ_BURST(DMEM_OFFSET + 4*100, prot, data, resp); + // #200; + // + // if (data == 32'h0abcd) + // break; + //end + + //// Flag: tProcessor data memory @101. + //// Memory is accessed using the upper half of the memory map. + //// address = DMEM_OFFSET + 4*101 + //data_wr = 32'h01234; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(DMEM_OFFSET + 4*101, prot, data_wr, resp); + //#200; + // + + //// Single write. + //$display("##############################"); + //$display("### Single read/write mode ###"); + //$display("##############################"); + //$display("t = %0t", $time); + // + //// Write memory (upper address map). + //for (int i=0;i<55;i++) begin + // data_wr = i; + // axi_mst_0_agent.AXI4LITE_WRITE_BURST(DMEM_OFFSET + 4*i, prot, data_wr, resp); + // #10; + //end + + //#500; + + //// Read back flag to signal start of next step. + //$display("#####################"); + //$display("### Wait for flag ###"); + //$display("#####################"); + //$display("t = %0t", $time); + + //// Flag: tProcessor data memory @100. + //// Memory is accessed using the upper part of the memory map. + //// Addresses are byte-based. + //// address = DMEM_OFFSET + 4*100 + //while (1) begin + // axi_mst_0_agent.AXI4LITE_READ_BURST(DMEM_OFFSET + 4*100, prot, data, resp); + // #200; + // + // if (data == 32'h0abcd) + // break; + //end + + //// Flag: tProcessor data memory @101. + //// Memory is accessed using the upper half of the memory map. + //// address = DMEM_OFFSET + 4*101 + //data_wr = 32'h01234; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(DMEM_OFFSET + 4*101, prot, data_wr, resp); + //#200; + + //// Read back flag to signal end of transfer. + //$display("#####################################"); + //$display("### Wait for end-of-transfer flag ###"); + //$display("#####################################"); + //$display("t = %0t", $time); + + //// Flag: tProcessor data memory @200. + //// Memory is accessed using the upper half of the memory map. + //// address = 200 + 2^DMEM_N + //while (1) begin + // axi_mst_0_agent.AXI4LITE_READ_BURST(2**DMEM_N + 4*200, prot, data, resp); + // #200; + // + // if (data == 16'h5a5a) + // break; + //end + + //// AXIS read (from memory to m0_axis). + //$display("##########################################"); + //$display("### AXIS read (from memory to m0_axis) ###"); + //$display("##########################################"); + //$display("t = %0t", $time); + + ///* + // MEM_MODE_REG = 0; + // MEM_START_REG = 1; + // MEM_ADDR_REG = 0; + // MEM_LEN_REG = 100; + //*/ + + //// MEM_MODE_REG + //data_wr = 0; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, data_wr, resp); + //#10; + + //// MEM_ADDR_REG + //data_wr = 0; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); + //#10; + + //// MEM_LEN_REG + //data_wr = 100; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*5, prot, data_wr, resp); + //#10; + + //// MEM_START_REG + //data_wr = 1; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); + //#10; + + //// Wait until transaction is done. + //while (1) begin + // @(posedge aclk); + // if (m0_axis_tlast == 1'b1 && m0_axis_tvalid == 1'b1 && m0_axis_tready == 1'b1) + // break; + //end + + //// MEM_START_REG + //data_wr = 0; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); + //#10; + + //// AXIS write (from s0_axis to memory). + //$display("###########################################"); + //$display("### AXIS write (from s0_axis to memory) ###"); + //$display("###########################################"); + //$display("t = %0t", $time); + + ///* + // MEM_MODE_REG = 1; + // MEM_START_REG = 1; + // MEM_ADDR_REG = 50; + //*/ + + //// MEM_MODE_REG + //data_wr = 1; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, data_wr, resp); + //#10; + + //// MEM_ADDR_REG + //data_wr = 50; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); + //#10; + + //// MEM_START_REG + //data_wr = 1; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); + //#10; + + //// Send data. + //fork + // gen_0(44,0); + //join + + //// MEM_START_REG + //data_wr = 0; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); + //#10; + + //// Flag to signal data has been transferred. + //data_wr = 32'h0000cdef; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(2**DMEM_N + 4*200, prot, data_wr, resp); + //#10; + + //// Read back flag to signal end of memory operation. + //$display("######################################"); + //$display("### Wait for end-of-operation flag ###"); + //$display("######################################"); + //$display("t = %0t", $time); + + //// Flag: tProcessor data memory @200. + //// Memory is accessed using the upper half of the memory map. + //// address = 200 + 2^DMEM_N + //while (1) begin + // axi_mst_0_agent.AXI4LITE_READ_BURST(2**DMEM_N + 4*200, prot, data, resp); + // #200; + // + // if (data == 16'h5a5a) + // break; + //end + + //// AXIS read (from memory to m0_axis). + //$display("##########################################"); + //$display("### AXIS read (from memory to m0_axis) ###"); + //$display("##########################################"); + //$display("t = %0t", $time); + + ///* + // MEM_MODE_REG = 0; + // MEM_START_REG = 1; + // MEM_ADDR_REG = 50; + // MEM_LEN_REG = 44; + //*/ + + //// MEM_MODE_REG + //data_wr = 0; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*2, prot, data_wr, resp); + //#10; + + //// MEM_ADDR_REG + //data_wr = 50; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*4, prot, data_wr, resp); + //#10; + + //// MEM_LEN_REG + //data_wr = 44; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*5, prot, data_wr, resp); + //#10; + + //// MEM_START_REG + //data_wr = 1; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); + //#10; + + //// Wait until transaction is done. + //while (1) begin + // @(posedge aclk); + // if (m0_axis_tlast == 1'b1 && m0_axis_tvalid == 1'b1 && m0_axis_tready == 1'b1) + // break; + //end + + //// MEM_START_REG + //data_wr = 0; + //axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*3, prot, data_wr, resp); + //#10; + + #1000; + +end + +always +begin + s_axi_aclk <= 0; + #5; + s_axi_aclk <= 1; + #5; +end + +always +begin + aclk <= 0; + #1; + aclk <= 1; + #1; +end + +task gen_0(input int cnt, input int delay); + // Create transaction. + axi4stream_transaction wr_transaction; + wr_transaction = axis_mst_0_agent.driver.create_transaction("Master 0 VIP write transaction"); + + // Set transaction parameters. + wr_transaction.set_xfer_alignment(XIL_AXI4STREAM_XFER_RANDOM); + + // Send transactions. + for (int i=0; i < cnt-1; i++) + begin + WR_TRANSACTION_FAIL: assert(wr_transaction.randomize()); + wr_transaction.set_last(0); + wr_transaction.set_delay(delay); + axis_mst_0_agent.driver.send(wr_transaction); + end + + // Last. + WR_TRANSACTION_FAIL: assert(wr_transaction.randomize()); + wr_transaction.set_last(1); + wr_transaction.set_delay(delay); + axis_mst_0_agent.driver.send(wr_transaction); + +endtask + +endmodule + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/tb/tb_alu.sv b/firmware/ip/axis_tproc64x32_x8_v1/src/tb/tb_alu.sv new file mode 100644 index 0000000..20620cc --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/tb/tb_alu.sv @@ -0,0 +1,82 @@ +module tb(); + +// Data width. +localparam B = 32; + +reg clk; +reg rstn; +reg signed [B-1:0] din_a; +reg signed [B-1:0] din_b; +reg [3:0] op; +wire zero_a; +wire zero_b; +wire signed [B-1:0] dout; + +// DUT. +alu + #( + // Data width. + .B(32) + ) + DUT + ( + // Clock and reset. + .clk (clk ), + .rstn (rstn ), + + // Input operands. + .din_a (din_a ), + .din_b (din_b ), + + // Operation. + .op (op ), + + // Zero detection. + .zero_a (zero_a ), + .zero_b (zero_b ), + + // Output. + .dout (dout ) + ); + +initial begin + // Reset sequence. + rstn <= 0; + #1000; + rstn <= 1; + + // Addition. + @(posedge clk); + op <= 4'b1000; + din_a <= 53; + din_b <= -38; + + @(posedge clk); + din_a <= 530; + din_b <= -3000; + + // Substraction. + @(posedge clk); + op <= 4'b1001; + din_a <= 5830; + din_b <= 5830; + + // Product. + @(posedge clk); + op <= 4'b1010; + din_a <= 5830; + din_b <= 8; + + #1000; +end + +always +begin + clk <= 0; + #5; + clk <= 1; + #5; +end + +endmodule + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/timed_ictrl.vhd b/firmware/ip/axis_tproc64x32_x8_v1/src/timed_ictrl.vhd new file mode 100644 index 0000000..c09ae5c --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/timed_ictrl.vhd @@ -0,0 +1,204 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Timed-instructions dispatcher control. +-- +-- 31 .. 0 : r0 +-- 63 .. 32 : r1 +-- 95 .. 64 : r2 +-- 127 .. 96 : r3 +-- 159 .. 128 : r4 +-- 207 .. 160 : t +-- 215 .. 208 : opcode +entity timed_ictrl is + Port ( + -- Clock and reset. + clk : in std_logic; + rstn : in std_logic; + + -- Master clock. + t_cnt : in unsigned (47 downto 0); + + -- Fifo Time control. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (215 downto 0); + fifo_empty : in std_logic; + + -- Wait handshake. + waitt : out std_logic; + waitt_ack : in std_logic; + + -- Output AXIS. + m_axis_tdata : out std_logic_vector (159 downto 0); + m_axis_tvalid : out std_logic; + m_axis_tready : in std_logic + ); +end timed_ictrl; + +architecture rtl of timed_ictrl is + +type fsm_type is ( READ_ST , + WAIT_ST , + WAIT_ACK_ST , + SETI_ST , + SETBI_ST , + SET_ST , + SETB_ST ); + +signal state : fsm_type; + +-- Time of actual instruction. +signal t_inst : unsigned (47 downto 0); + +-- Parameters. +signal p0_i : std_logic_vector (31 downto 0); +signal p1_i : std_logic_vector (31 downto 0); +signal p2_i : std_logic_vector (31 downto 0); +signal p3_i : std_logic_vector (31 downto 0); +signal p4_i : std_logic_vector (31 downto 0); + +-- Opcode. +signal opcode_i : std_logic_vector (7 downto 0); + +signal rd_en_i : std_logic; +signal tvalid_i : std_logic; + +-- Wait handshake. +signal waitt_i : std_logic; + +-- Output source. +signal src_i : std_logic; -- 0: 32 bits, 1: 128 bits. + +-- Zeros. +signal zeros_128: std_logic_vector (127 downto 0) := (others => '0'); + +begin + +-- Time of actual instruction. +t_inst <= unsigned (fifo_dout(207 downto 160)); + +-- Parameters. +p0_i <= fifo_dout(31 downto 0); +p1_i <= fifo_dout(63 downto 32); +p2_i <= fifo_dout(95 downto 64); +p3_i <= fifo_dout(127 downto 96); +p4_i <= fifo_dout(159 downto 128); + +-- Opcode. +opcode_i <= fifo_dout(215 downto 208); + +-- Finite State Machine. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + state <= READ_ST; + else + case (state) is + when READ_ST => + if ( fifo_empty = '0' ) then + state <= WAIT_ST; + end if; + + when WAIT_ST => + if ( t_inst <= t_cnt ) then + -- waiti/wait + if ( opcode_i = "00010101" or opcode_i = "01010100") then + state <= WAIT_ACK_ST; + + -- seti + elsif ( opcode_i = "00010011" ) then + state <= SETI_ST; + + -- setbi + elsif ( opcode_i = "00011010" ) then + state <= SETBI_ST; + + -- set + elsif ( opcode_i = "01010001" ) then + state <= SET_ST; + + -- setb + elsif ( opcode_i = "01011000" ) then + state <= SETB_ST; + + -- Read next word. + else + state <= READ_ST; + + end if; + end if; + + when WAIT_ACK_ST => + if ( waitt_ack = '1' ) then + state <= READ_ST; + end if; + + when SETI_ST => + state <= READ_ST; + + when SETBI_ST => + if ( m_axis_tready = '1' ) then + state <= READ_ST; + end if; + + when SET_ST => + state <= READ_ST; + + when SETB_ST => + if ( m_axis_tready = '1' ) then + state <= READ_ST; + end if; + + end case; + end if; + end if; +end process; + +-- Output logic. +process (state) +begin +rd_en_i <= '0'; +tvalid_i <= '0'; +waitt_i <= '0'; +src_i <= '0'; + case (state) is + when READ_ST => + rd_en_i <= '1'; + + when WAIT_ST => + + when WAIT_ACK_ST => + waitt_i <= '1'; + + when SETI_ST => + tvalid_i <= '1'; + src_i <= '0'; + + when SETBI_ST => + tvalid_i <= '1'; + src_i <= '0'; + + when SET_ST => + tvalid_i <= '1'; + src_i <= '1'; + + when SETB_ST => + tvalid_i <= '1'; + src_i <= '1'; + end case; +end process; + +-- Assign outputs. +fifo_rd_en <= rd_en_i; + +waitt <= waitt_i; + +m_axis_tdata <= zeros_128 & p0_i when src_i = '0' else + p4_i & p3_i & p2_i & p1_i & p0_i; + +m_axis_tvalid <= tvalid_i; + +end rtl; + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/src/tproc64x32_x8.v b/firmware/ip/axis_tproc64x32_x8_v1/src/tproc64x32_x8.v new file mode 100644 index 0000000..b99bc98 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/src/tproc64x32_x8.v @@ -0,0 +1,847 @@ +module tproc64x32_x8 +( + // Clock and reset. + clk , + rstn , + + // Start/stop. + start , + + // Program Memory Interface. + pmem_addr , + pmem_do , + + // Data Memory Interface. + dmem_we , + dmem_addr , + dmem_di , + dmem_do , + + // Slave AXIS 0 for Input data. + s0_axis_tdata , + s0_axis_tvalid , + s0_axis_tready , + + // Slave AXIS 1 for Input data. + s1_axis_tdata , + s1_axis_tvalid , + s1_axis_tready , + + // Slave AXIS 2 for Input data. + s2_axis_tdata , + s2_axis_tvalid , + s2_axis_tready , + + // Slave AXIS 3 for Input data. + s3_axis_tdata , + s3_axis_tvalid , + s3_axis_tready , + + // Master AXIS 0 for Output data. + m0_axis_tdata , + m0_axis_tvalid , + m0_axis_tready , + + // Master AXIS 1 for Output data. + m1_axis_tdata , + m1_axis_tvalid , + m1_axis_tready , + + // Master AXIS 2 for Output data. + m2_axis_tdata , + m2_axis_tvalid , + m2_axis_tready , + + // Master AXIS 3 for Output data. + m3_axis_tdata , + m3_axis_tvalid , + m3_axis_tready , + + // Master AXIS 4 for Output data. + m4_axis_tdata , + m4_axis_tvalid , + m4_axis_tready , + + // Master AXIS 5 for Output data. + m5_axis_tdata , + m5_axis_tvalid , + m5_axis_tready , + + // Master AXIS 6 for Output data. + m6_axis_tdata , + m6_axis_tvalid , + m6_axis_tready , + + // Master AXIS 7 for Output data. + m7_axis_tdata , + m7_axis_tvalid , + m7_axis_tready , + + // Registers. + START_SRC_REG , + START_REG +); + +// Parameters. +parameter N = 16; // Program memory depth. +parameter M = 10; // Data memory depth. + +// Ports. +input clk; +input rstn; + +input start; + +output [N-1:0] pmem_addr; +input [63:0] pmem_do; + +output dmem_we; +output [M-1:0] dmem_addr; +output [31:0] dmem_di; +input [31:0] dmem_do; + +input [63:0] s0_axis_tdata; +input s0_axis_tvalid; +output s0_axis_tready; + +input [63:0] s1_axis_tdata; +input s1_axis_tvalid; +output s1_axis_tready; + +input [63:0] s2_axis_tdata; +input s2_axis_tvalid; +output s2_axis_tready; + +input [63:0] s3_axis_tdata; +input s3_axis_tvalid; +output s3_axis_tready; + +output [159:0] m0_axis_tdata; +output m0_axis_tvalid; +input m0_axis_tready; + +output [159:0] m1_axis_tdata; +output m1_axis_tvalid; +input m1_axis_tready; + +output [159:0] m2_axis_tdata; +output m2_axis_tvalid; +input m2_axis_tready; + +output [159:0] m3_axis_tdata; +output m3_axis_tvalid; +input m3_axis_tready; + +output [159:0] m4_axis_tdata; +output m4_axis_tvalid; +input m4_axis_tready; + +output [159:0] m5_axis_tdata; +output m5_axis_tvalid; +input m5_axis_tready; + +output [159:0] m6_axis_tdata; +output m6_axis_tvalid; +input m6_axis_tready; + +output [159:0] m7_axis_tdata; +output m7_axis_tvalid; +input m7_axis_tready; + +input START_SRC_REG; +input START_REG; + +// Number of channels. +localparam NCH = 8; + +// Bit-width. +localparam B = 32; + +// Master Clock Width. +localparam TW = 48; + +// Fifo-width: 5*B (registers) + TW (Master Clock) + 8 (opcode) +localparam FW = 5*B + TW + 8; + +// Synced regs. +wire START_SRC_REG_resync; +wire START_REG_resync; +wire start_input_resync; + +// Muxed start. +wire start_i; + +// Instruction fields. +wire [7:0] opcode_i; +wire [2:0] page_i; +wire [2:0] channel_i; +wire [3:0] oper_i; +wire [31:0] imm_i; + +// IR enable. +wire ir_en_i; + +// Pogram counter out (jump instructions). +wire pc_src_i; +wire pc_en_i; +wire pc_rst_i; + +// Alu control. +wire [B-1:0] alu_a; +wire [B-1:0] alu_b; +wire [1:0] alu_src_b_i; +wire alu_zero_i; +wire [B-1:0] alu_out; + +// Alu Time control +wire alut_src_b_i; + +// Register write control. +wire [2:0] reg_src_i; +wire reg_wen_i; + +// Conditional control. +wire cond_flag_i; + +// Stack control. +wire stack_en_i; +wire stack_op_i; +wire [B-1:0] stack_din_i; +wire [B-1:0] stack_dout_i; +wire stack_full_i; +wire stack_empty_i; + +// Read address. +wire [4:0] reg_addr0_i; +wire [4:0] reg_addr1_i; +wire [4:0] reg_addr2_i; +wire [4:0] reg_addr3_i; +wire [4:0] reg_addr4_i; +wire [4:0] reg_addr5_i; +wire [4:0] reg_addr6_i; + +// Write address. +wire [4:0] reg_addr7_i; + +// Write data. +wire [B-1:0] reg_din7_i; + + +// Output registers. +wire [B-1:0] reg_dout0_i; +wire [B-1:0] reg_dout1_i; +wire [B-1:0] reg_dout2_i; +wire [B-1:0] reg_dout3_i; +wire [B-1:0] reg_dout4_i; +wire [B-1:0] reg_dout5_i; +wire [B-1:0] reg_dout6_i; + +// Program Counter. +wire [15:0] pc_i; +wire [15:0] pc_mux; +reg [15:0] pc_r; + +// Instruction register. +reg [63:0] ir_r; + +// Fifo for timed-instructions. +wire [NCH-1:0] fifo_time_wr_en; +wire [FW-1:0] fifo_time_din; +wire [NCH-1:0] fifo_time_rd_en; +wire [FW-1:0] fifo_time_dout [NCH-1:0]; +wire [NCH-1:0] fifo_time_full; +wire [NCH-1:0] fifo_time_empty; + +// Muxed fifo signals for control. +wire fifo_wr_en_mux; +wire fifo_full_mux; + +// Data memory control. +wire [M-1:0] dmem_addr_mux; +wire dmem_addr_src; + +// Alu for time computation. +wire [TW-1:0] alut_a; +wire [TW-1:0] alut_b; +wire [TW-1:0] alut_out; +reg [TW-1:0] alut_out_r; + +// Master clock. +reg [TW-1:0] t_cnt; +wire t_cnt_en; +reg [TW-1:0] t_cnt_sync; +wire t_cnt_sync_en; + +// Data memory output data register. +reg [B-1:0] dmem_do_r; + +// Stack output register. +reg [B-1:0] stack_dout_r; + +// Data input from external AXIS ports. +wire [63:0] din0_i; +wire [63:0] din1_i; +wire [63:0] din2_i; +wire [63:0] din3_i; +wire [63:0] din_mux; +wire [31:0] din_i; + +// Wait handshake. +wire [NCH-1:0] waitt_i; +wire [NCH-1:0] waitt_ack_i; +wire waitt_mux; +wire waitt_ack_mux; + +// Output AXIS. +wire [159:0] m_axis_tdata_i [NCH-1:0]; +wire [NCH-1:0] m_axis_tvalid_i; +wire [NCH-1:0] m_axis_tready_i; + +// START_SRC_REG_resync +synchronizer_n + #( + .N(2) + ) + START_SRC_REG_resync_i + ( + .rstn (rstn ), + .clk (clk ), + .data_in (START_SRC_REG ), + .data_out (START_SRC_REG_resync ) + ); + +// START_REG_resync +synchronizer_n + #( + .N(2) + ) + START_REG_resync_i + ( + .rstn (rstn ), + .clk (clk ), + .data_in (START_REG ), + .data_out (START_REG_resync ) + ); + +// start_input_resync +synchronizer_n + #( + .N(2) + ) + start_input_resync_i + ( + .rstn (rstn ), + .clk (clk ), + .data_in (start ), + .data_out (start_input_resync ) + ); + +// Control block. +ctrl + ctrl_i + ( + // Clock and reset. + .clk (clk ), + .rstn (rstn ), + + // Start/stop. + .start (start_i ), + + // Opcode. + .opcode (opcode_i ), + + // IR control. + .ir_en (ir_en_i ), + + // Pogram counter out (jump instructions). + .pc_src (pc_src_i ), + .pc_en (pc_en_i ), + .pc_rst (pc_rst_i ), + + // Alu control. + .alu_src_b (alu_src_b_i ), + .alu_zero (alu_zero_i ), + + // Alu time control. + .alut_src_b (alut_src_b_i ), + + // Register write control. + .reg_src (reg_src_i ), + .reg_wen (reg_wen_i ), + + // Conditional control. + .cond_flag (cond_flag_i ), + + // Stack control. + .stack_en (stack_en_i ), + .stack_op (stack_op_i ), + .stack_full (stack_full_i ), + .stack_empty (stack_empty_i ), + + // Fifo Time control. + .fifo_wr_en (fifo_wr_en_mux ), + .fifo_full (fifo_full_mux ), + + // Data Memory control. + .dmem_we (dmem_we ), + .addr_src (dmem_addr_src ), + + // Master clock control. + .t_en (t_cnt_en ), + .t_sync_en (t_cnt_sync_en ), + + // Wait handshake. + .waitt (waitt_mux ), + .waitt_ack (waitt_ack_mux ) + ); + +// Muxed start. +assign start_i = (START_SRC_REG_resync == 1)? start_input_resync : START_REG_resync; + +// Instruction fields. +assign opcode_i = ir_r[63:56]; +assign page_i = ir_r[55:53]; +assign channel_i = ir_r[52:50]; +assign oper_i = ir_r[49:46]; +assign imm_i = {ir_r[30],ir_r[30:0]}; // Sign-extend immediate to be 32-bit. + +// Stack block. +stack + #( + // Data width. + .B(B) + ) + stack_i + ( + // Clock and reset. + .clk (clk ), + .rstn (rstn ), + + // Enable and operation. + .en (stack_en_i ), + .op (stack_op_i ), + + // Input/Output data. + .din (stack_din_i ), + .dout (stack_dout_i ), + + // Flags. + .empty (stack_empty_i ), + .full (stack_full_i ) + ); + +// Stack input data. +assign stack_din_i = reg_dout0_i; + +// Regfile block. +regfile_8p + #( + // Data width. + .B(B) + ) + regfile_i + ( + // Clock and reset. + .clk (clk ), + .rstn (rstn ), + + // Read address. + .addr0 (reg_addr0_i ), + .addr1 (reg_addr1_i ), + .addr2 (reg_addr2_i ), + .addr3 (reg_addr3_i ), + .addr4 (reg_addr4_i ), + .addr5 (reg_addr5_i ), + .addr6 (reg_addr6_i ), + + // Write address. + .addr7 (reg_addr7_i ), + + // Write data. + .din7 (reg_din7_i ), + .wen7 (reg_wen_i ), + + // Page number. + .pnum (page_i ), + + // Output registers. + .dout0 (reg_dout0_i ), + .dout1 (reg_dout1_i ), + .dout2 (reg_dout2_i ), + .dout3 (reg_dout3_i ), + .dout4 (reg_dout4_i ), + .dout5 (reg_dout5_i ), + .dout6 (reg_dout6_i ) + ); + +// Register address. +assign reg_addr0_i = ir_r[40:36]; +assign reg_addr1_i = ir_r[35:31]; +assign reg_addr2_i = ir_r[30:26]; +assign reg_addr3_i = ir_r[25:21]; +assign reg_addr4_i = ir_r[20:16]; +assign reg_addr5_i = ir_r[15:11]; +assign reg_addr6_i = ir_r[10:6]; +assign reg_addr7_i = ir_r[45:41]; + +// Mux for register data input. +assign reg_din7_i = (reg_src_i == 3'b000)? imm_i : + (reg_src_i == 3'b001)? alu_out : + (reg_src_i == 3'b010)? stack_dout_r : + (reg_src_i == 3'b011)? din_i : + (reg_src_i == 3'b100)? dmem_do_r : + imm_i; + + +// Instantiate fifo and timed_ictrl. +generate +genvar i; + for (i = 0; i < NCH; i = i + 1 ) begin : GEN_channel + // Fifo for dispatching timed-instructions. + fifo + #( + // Data width. + .B (FW ), + + // Fifo depth. + .N (16 ) + ) + fifo_time_i + ( + .rstn (rstn ), + .clk (clk ), + + // Write I/F. + .wr_en (fifo_time_wr_en[i] ), + .din (fifo_time_din ), + + // Read I/F. + .rd_en (fifo_time_rd_en[i] ), + .dout (fifo_time_dout[i] ), + + // Flags. + .full (fifo_time_full[i] ), + .empty (fifo_time_empty[i] ) + ); + + // Write enable mux. + assign fifo_time_wr_en[i] = (channel_i == i)? fifo_wr_en_mux : 1'b0; + + // Timed-instructions dispatcher control. + timed_ictrl + timed_ictrl_i + ( + // Clock and reset. + .clk (clk ), + .rstn (rstn ), + + // Master clock. + .t_cnt (t_cnt ), + + // Fifo Time control. + .fifo_rd_en (fifo_time_rd_en[i] ), + .fifo_dout (fifo_time_dout[i] ), + .fifo_empty (fifo_time_empty[i] ), + + // Wait handshake. + .waitt (waitt_i[i] ), + .waitt_ack (waitt_ack_i[i] ), + + // Output AXIS. + .m_axis_tdata (m_axis_tdata_i[i] ), + .m_axis_tvalid (m_axis_tvalid_i[i] ), + .m_axis_tready (m_axis_tready_i[i] ) + ); + + // Wait handshake. + assign waitt_ack_i[i] = (channel_i == i)? waitt_ack_mux : 1'b0; + + end +endgenerate + +// Fifo Time input data (shared among channels). +// reg1 is reserved for time specification. reg0, reg2, reg3, reg4, reg5. +assign fifo_time_din = { opcode_i , + alut_out_r , + reg_dout5_i , + reg_dout4_i , + reg_dout3_i , + reg_dout2_i , + reg_dout0_i }; + +// Muxed fifo signals for control. +assign fifo_full_mux = fifo_time_full[channel_i[2:0]]; + +// Wait handshake. +assign waitt_mux = waitt_i[channel_i[2:0]]; + +// m_axis_tready signals. +assign m_axis_tready_i[0] = m0_axis_tready; +assign m_axis_tready_i[1] = m1_axis_tready; +assign m_axis_tready_i[2] = m2_axis_tready; +assign m_axis_tready_i[3] = m3_axis_tready; +assign m_axis_tready_i[4] = m4_axis_tready; +assign m_axis_tready_i[5] = m5_axis_tready; +assign m_axis_tready_i[6] = m6_axis_tready; +assign m_axis_tready_i[7] = m7_axis_tready; + +// Data memory address mux. +assign dmem_addr_mux = (dmem_addr_src == 1'b0)? imm_i : reg_dout0_i; + +// Conditional logic. +cond + #( + // Data width. + .B(B) + ) + cond_i + ( + // Clock and reset. + .clk (clk ), + .rstn (rstn ), + + // Input operands. + .din_a (reg_dout0_i ), + .din_b (reg_dout1_i ), + + // Operation. + .op (oper_i ), + + // Flag. + .flag (cond_flag_i ) + ); + +// Alu for math and bit-wise operations. +alu + #( + // Data width. + .B(B) + ) + alu_i + ( + // Clock and reset. + .clk (clk ), + .rstn (rstn ), + + // Input operands. + .din_a (alu_a ), + .din_b (alu_b ), + + // Operation. + .op (oper_i ), + + // Zero detection. + .zero_a (alu_zero_i ), + .zero_b ( ), + + // Output. + .dout (alu_out ) + ); + +// Alu inputs. +assign alu_a = reg_dout0_i; +assign alu_b = (alu_src_b_i == 2'b00)? imm_i : + (alu_src_b_i == 2'b01)? reg_dout1_i : + (alu_src_b_i == 2'b10)? -1 : + 0; + +// Slave AXIS 0 read block. +s_axis_read + #( + // Data width. + .B(64) + ) + s0_axis_read_i + ( + // Clock and reset. + .clk (clk ), + .rstn (rstn ), + + // AXIS Slave. + .s_axis_tdata (s0_axis_tdata ), + .s_axis_tvalid (s0_axis_tvalid ), + .s_axis_tready (s0_axis_tready ), + + // Output data. + .dout (din0_i ) + ); + +// Slave AXIS 1 read block. +s_axis_read + #( + // Data width. + .B(64) + ) + s1_axis_read_i + ( + // Clock and reset. + .clk (clk ), + .rstn (rstn ), + + // AXIS Slave. + .s_axis_tdata (s1_axis_tdata ), + .s_axis_tvalid (s1_axis_tvalid ), + .s_axis_tready (s1_axis_tready ), + + // Output data. + .dout (din1_i ) + ); + +// Slave AXIS 2 read block. +s_axis_read + #( + // Data width. + .B(64) + ) + s2_axis_read_i + ( + // Clock and reset. + .clk (clk ), + .rstn (rstn ), + + // AXIS Slave. + .s_axis_tdata (s2_axis_tdata ), + .s_axis_tvalid (s2_axis_tvalid ), + .s_axis_tready (s2_axis_tready ), + + // Output data. + .dout (din2_i ) + ); + +// Slave AXIS 3 read block. +s_axis_read + #( + // Data width. + .B(64) + ) + s3_axis_read_i + ( + // Clock and reset. + .clk (clk ), + .rstn (rstn ), + + // AXIS Slave. + .s_axis_tdata (s3_axis_tdata ), + .s_axis_tvalid (s3_axis_tvalid ), + .s_axis_tready (s3_axis_tready ), + + // Output data. + .dout (din3_i ) + ); + +// Data input mux. +assign din_mux = (channel_i == 0)? din0_i : + (channel_i == 1)? din1_i : + (channel_i == 2)? din2_i : + (channel_i == 3)? din3_i : + 0; + +// Low/high part selection. +assign din_i = (oper_i == 4'b1010)? din_mux[32 +:32] : + din_mux[0 +: 32]; + +// Alu for time inputs. +assign alut_a = t_cnt_sync; +assign alut_b = (alut_src_b_i == 0)? reg_dout1_i : imm_i; +assign alut_out = alut_a + alut_b; + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // Program counter. + pc_r <= 0; + + // Instruction counter. + ir_r <= 0; + + // ALU t output register. + alut_out_r <= 0; + + // Master clock. + t_cnt <= 0; + t_cnt_sync <= 0; + + // Data memory output data register. + dmem_do_r <= 0; + + // Stack output register. + stack_dout_r <= 0; + end + else begin + // Program counter. + if (pc_rst_i) + pc_r <= 0; + else if (pc_en_i) + pc_r <= pc_mux; + + // Instruction counter. + if (ir_en_i) + ir_r <= pmem_do; + + // ALU t output register. + alut_out_r <= alut_out; + + // Master clock. + if (pc_rst_i) + t_cnt <= 0; + else if (t_cnt_en) + t_cnt <= t_cnt + 1; + + if (pc_rst_i) + t_cnt_sync <= 0; + else if (t_cnt_sync_en) + t_cnt_sync <= alut_out_r; + + // Data memory output data register. + dmem_do_r <= dmem_do; + + // Stack output register. + stack_dout_r <= stack_dout_i; + end +end + +// Program counter. +assign pc_i = pc_r + 1; +assign pc_mux = (pc_src_i == 1)? imm_i : pc_i; + +// Assign outputs. +assign pmem_addr = pc_r; + +// Data memory interface. +assign dmem_addr = dmem_addr_mux; +assign dmem_di = reg_dout1_i; + +// Master AXIS 0 for Output data. +assign m0_axis_tdata = m_axis_tdata_i[0]; +assign m0_axis_tvalid = m_axis_tvalid_i[0]; + +// Master AXIS 1 for Output data. +assign m1_axis_tdata = m_axis_tdata_i[1]; +assign m1_axis_tvalid = m_axis_tvalid_i[1]; + +// Master AXIS 2 for Output data. +assign m2_axis_tdata = m_axis_tdata_i[2]; +assign m2_axis_tvalid = m_axis_tvalid_i[2]; + +// Master AXIS 3 for Output data. +assign m3_axis_tdata = m_axis_tdata_i[3]; +assign m3_axis_tvalid = m_axis_tvalid_i[3]; + +// Master AXIS 4 for Output data. +assign m4_axis_tdata = m_axis_tdata_i[4]; +assign m4_axis_tvalid = m_axis_tvalid_i[4]; + +// Master AXIS 5 for Output data. +assign m5_axis_tdata = m_axis_tdata_i[5]; +assign m5_axis_tvalid = m_axis_tvalid_i[5]; + +// Master AXIS 6 for Output data. +assign m6_axis_tdata = m_axis_tdata_i[6]; +assign m6_axis_tvalid = m_axis_tvalid_i[6]; + +// Master AXIS 7 for Output data. +assign m7_axis_tdata = m_axis_tdata_i[7]; +assign m7_axis_tvalid = m_axis_tvalid_i[7]; + +endmodule + diff --git a/firmware/ip/axis_tproc64x32_x8_v1/xgui/axis_tproc64x32_x8_v1_0.tcl b/firmware/ip/axis_tproc64x32_x8_v1/xgui/axis_tproc64x32_x8_v1_0.tcl new file mode 100644 index 0000000..f4042d5 --- /dev/null +++ b/firmware/ip/axis_tproc64x32_x8_v1/xgui/axis_tproc64x32_x8_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DMEM_N" -parent ${Page_0} + ipgui::add_param $IPINST -name "PMEM_N" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DMEM_N { PARAM_VALUE.DMEM_N } { + # Procedure called to update DMEM_N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMEM_N { PARAM_VALUE.DMEM_N } { + # Procedure called to validate DMEM_N + return true +} + +proc update_PARAM_VALUE.PMEM_N { PARAM_VALUE.PMEM_N } { + # Procedure called to update PMEM_N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PMEM_N { PARAM_VALUE.PMEM_N } { + # Procedure called to validate PMEM_N + return true +} + + +proc update_MODELPARAM_VALUE.PMEM_N { MODELPARAM_VALUE.PMEM_N PARAM_VALUE.PMEM_N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PMEM_N}] ${MODELPARAM_VALUE.PMEM_N} +} + +proc update_MODELPARAM_VALUE.DMEM_N { MODELPARAM_VALUE.DMEM_N PARAM_VALUE.DMEM_N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMEM_N}] ${MODELPARAM_VALUE.DMEM_N} +} + diff --git a/firmware/ip/axis_weighted_buffer/component.xml b/firmware/ip/axis_weighted_buffer/component.xml new file mode 100644 index 0000000..6fd3d10 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/component.xml @@ -0,0 +1,1533 @@ + + + user.org + user + axis_weighted_buffer + 1.2 + + + m0_axis + + + + + + + TDATA + + + m0_axis_tdata + + + + + TLAST + + + m0_axis_tlast + + + + + TVALID + + + m0_axis_tvalid + + + + + TREADY + + + m0_axis_tready + + + + + + m1_axis + + + + + + + TDATA + + + m1_axis_tdata + + + + + TLAST + + + m1_axis_tlast + + + + + TVALID + + + m1_axis_tvalid + + + + + TREADY + + + m1_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi:s1_axis_weights + + + ASSOCIATED_RESET + s_axi_aresetn + + + FREQ_HZ + + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axis_aclk + + + + + + + CLK + + + s_axis_aclk + + + + + + ASSOCIATED_BUSIF + s_axis + + + ASSOCIATED_RESET + s_axis_aresetn + + + FREQ_HZ + + + + + + s_axis_aresetn + + + + + + + RST + + + s_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m_axis_aclk + + + + + + + CLK + + + m_axis_aclk + + + + + + ASSOCIATED_RESET + m_axis_aresetn + + + ASSOCIATED_BUSIF + m0_axis:m1_axis:m2_axis + + + FREQ_HZ + + + + + + m_axis_aresetn + + + + + + + RST + + + m_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m2_axis + + + + + + + TDATA + + + m2_axis_tdata + + + + + TVALID + + + m2_axis_tvalid + + + + + TREADY + + + m2_axis_tready + + + + + + s1_axis_weights + + + + + + + TVALID + + + s1_axis_tvalid + + + + + TDATA + + + s1_axis_tdata + + + + + TREADY + + + s1_axis_tready + + + + + + + + s_axi + + reg0 + 0 + 64 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axis_weighted_buffer + + xilinx_anylanguagesynthesis_xilinx_com_ip_dsp_macro_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 73f9cfaf + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axis_weighted_buffer + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dsp_macro_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 73f9cfaf + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 62c01b7a + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + 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xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m0_axis_tdata + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m0_axis_tlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m1_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m1_axis_tlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m2_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m2_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m2_axis_tdata + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N_AVG + N Avg + 14 + + + N_BUF + N Buf + 14 + + + B + B + 16 + + + N_WGT + N Wgt + 14 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/dsp_macro_0/dsp_macro_0.xci + xci + CELL_NAME_avg_buffer_i/matchfilt_i/matched_filter_mult_ac + + + src/avg_buffer.v + verilogSource + + + src/avg_top.v + verilogSource + + + src/buffer_top.v + verilogSource + + + src/avg.sv + systemVerilogSource + + + src/buffer.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bin2gray.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/data_reader.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/fifo/fifo_dc.vhd + vhdlSource + + + src/fifo/fifo_dc_axi.vhd + vhdlSource + + + src/fifo/gray2bin.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/fifo/synchronizer_vect.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + CHECKSUM_34e13cff + + + src/matched_filter.vhd + vhdlSource + CHECKSUM_f6218d31 + + + src/axis_weighted_buffer.v + verilogSource + CHECKSUM_b6b3033f + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dsp_macro_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dsp_macro_0/dsp_macro_0.xci + xci + CELL_NAME_avg_buffer_i/matchfilt_i/matched_filter_mult_ac + + + src/avg_buffer.v + verilogSource + + + src/avg_top.v + verilogSource + + + src/buffer_top.v + verilogSource + + + src/avg.sv + systemVerilogSource + + + src/buffer.sv + systemVerilogSource + + + src/axi_slv.vhd + vhdlSource + + + src/fifo/bin2gray.vhd + vhdlSource + + + src/fifo/bram_dp.vhd + vhdlSource + + + src/fifo/bram_simple_dp.vhd + vhdlSource + + + src/data_reader.vhd + vhdlSource + + + src/fifo/fifo.vhd + vhdlSource + + + src/fifo/fifo_axi.vhd + vhdlSource + + + src/fifo/fifo_dc.vhd + vhdlSource + + + src/fifo/fifo_dc_axi.vhd + vhdlSource + + + src/fifo/gray2bin.vhd + vhdlSource + + + src/fifo/rd2axi.vhd + vhdlSource + + + src/synchronizer_n.vhd + vhdlSource + + + src/fifo/synchronizer_vect.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/matched_filter.vhd + vhdlSource + + + src/axis_weighted_buffer.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dsp_macro_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axis_weighted_buffer_v1_2.tcl + tclSource + CHECKSUM_62c01b7a + XGUI_VERSION_2 + + + + AXIS Weighted Integrator + Buffer block with external trigger and edge-counting mode. + + + N_AVG + N Avg + 14 + + + N_BUF + N Buf + 14 + + + B + B + 16 + + + Component_Name + axis_weighted_buffer_v1_0 + + + N_WGT + N Weights + 14 + + + + + + /UserIP + + AXIS Weighted Integrator + Buffer + level_2 + package_project + 12 + + user.org:user:axis_matchfilt_buffer:1.0 + user.org:user:axis_matchfilt_buffer:1.1 + user.org:user:axis_matchfilt_buffer:1.2 + + 2025-05-17T02:42:54Z + + + 2023.1 + + + + + + + + + diff --git a/firmware/ip/axis_weighted_buffer/src/avg.sv b/firmware/ip/axis_weighted_buffer/src/avg.sv new file mode 100644 index 0000000..0e71e56 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/avg.sv @@ -0,0 +1,274 @@ +// Data is I,Q. +// I: lower B bits. +// Q: upper B bits. +module avg ( + // Reset and clock. + rstn , + clk , + + // Trigger input. + trigger_i , + + // Data input. + din_valid_i , + din_i , + + // Memory interface. + mem_we_o , + mem_addr_o , + mem_di_o , + + // Registers. + START_REG , + ADDR_REG , + LEN_REG , + PHOTON_MODE_REG, + H_THRSH_REG , + L_THRSH_REG + ); + + //////////////// + // Parameters // + //////////////// + // Memory depth. + parameter N = 14; + + // Number of bits. + parameter B = 16; + + /////////// + // Ports // + /////////// + input rstn; + input clk; + + input trigger_i; + + input din_valid_i; + input [2*B-1:0] din_i; + + output mem_we_o; + output [N-1:0] mem_addr_o; + output [4*B-1:0] mem_di_o; + + + input START_REG; + input [N-1:0] ADDR_REG; + input [31:0] LEN_REG; + input PHOTON_MODE_REG; + input [B-1:0] H_THRSH_REG; + input [B-1:0] L_THRSH_REG; + + ////////////////////// + // Internal signals // + ////////////////////// + // States. + typedef enum { INIT_ST , + START_ST , + TRIGGER_ST , + AVG_ST , + QOUT_ST , + WRITE_MEM_ST , + WAIT_TRIGGER_ST + } state_t; + + // State register. + (* fsm_encoding = "one_hot" *) state_t state; + + reg start_state; + reg trigger_state; + reg avg_state; + reg qout_state; + reg write_mem_state; + + // Edge counter states. + reg high_state; + reg high_state_reg; + + // Counter. + reg [31:0] cnt; + + // Registers. + reg [N-1:0] addr_r; + reg [31:0] len_r; + reg photon_mode_r; + reg signed [B-1:0] h_thrsh_r; + reg signed [B-1:0] l_thrsh_r; + + + // Input data. + wire signed [B-1:0] din_ii, din_qq; + + // Accumulators. + reg signed [2*B-1:0] acc_i, acc_q; + reg [4*B-1:0] acc_photon; + + // Quantized outputs. + reg [4*B-1:0] out_result_r; + + + ////////////////// + // Architecture // + ////////////////// + assign din_ii = din_i[B-1:0]; + assign din_qq = din_i[2*B-1:B]; + + // Registers. + always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= INIT_ST; + + // Counter. + cnt <= 0; + + // Registers. + addr_r <= 0; + len_r <= 0; + photon_mode_r <= 1'b0; + h_thrsh_r <= 0; + l_thrsh_r <= 0; + high_state <= 1'b0; + high_state_reg <= 1'b0; + + // Accumulators. + acc_i <= 0; + acc_q <= 0; + acc_photon <= 0; + + // Quantized outputs. + out_result_r <= 0; + + end + else begin + // State register. + case (state) + INIT_ST: + state <= START_ST; + + START_ST: + if ( START_REG == 1'b1) + state <= TRIGGER_ST; + + TRIGGER_ST: + if ( START_REG == 1'b0 ) + state <= START_ST; + else if ( trigger_i == 1'b1 ) + state <= AVG_ST; + + AVG_ST: + if ( cnt == len_r-1 && din_valid_i == 1'b1 ) + state <= QOUT_ST; + + QOUT_ST: + state <= WRITE_MEM_ST; + + WRITE_MEM_ST: + state <= WAIT_TRIGGER_ST; + + WAIT_TRIGGER_ST: + if ( START_REG == 1'b0 ) + state <= START_ST; + else if ( trigger_i == 1'b0 ) begin + state <= TRIGGER_ST; + end + endcase + + // Counter. + if ( avg_state == 1'b1 ) begin + if ( din_valid_i == 1'b1) begin + cnt <= cnt + 1; + end + end + else begin + cnt <= 0; + end + + // Registers. + if ( start_state == 1'b1 ) begin + addr_r <= ADDR_REG; + len_r <= LEN_REG; + photon_mode_r <= PHOTON_MODE_REG; + h_thrsh_r <= H_THRSH_REG; + l_thrsh_r <= L_THRSH_REG; + end + else if ( write_mem_state == 1'b1 ) begin + addr_r <= addr_r + 1; + end + + // Accumulators. + if ( trigger_state == 1'b1 ) begin + acc_i <= 0; + acc_q <= 0; + acc_photon <= 0; + high_state <= 1'b0; + high_state_reg <= 1'b0; + end + else if ( avg_state == 1'b1 && din_valid_i == 1'b1 ) begin + // Accumulator counter. + if ( photon_mode_r == 1'b0 ) begin + acc_i <= acc_i + din_ii; + acc_q <= acc_q + din_qq; + end + // Rising edge counter. + else if ( high_state == 1'b1 && high_state_reg == 1'b0) + acc_photon <= acc_photon + 1; + end + + // Edge counter detect. + high_state_reg <= high_state; + if ( din_ii > h_thrsh_r ) + high_state <= 1'b1; + else if ( din_ii < l_thrsh_r ) + high_state <= 1'b0; + + // Quantized outputs. + if ( qout_state == 1'b1 ) begin + if ( photon_mode_r == 1'b0 ) + out_result_r <= {acc_q,acc_i}; + else + out_result_r <= acc_photon; + end + end + end + + // FSM outputs. + always_comb begin + // Default. + start_state = 0; + trigger_state = 0; + avg_state = 0; + qout_state = 0; + write_mem_state = 0; + + case (state) + //INIT_ST: + + START_ST: + start_state = 1'b1; + + TRIGGER_ST: + trigger_state = 1'b1; + + AVG_ST: + avg_state = 1'b1; + + QOUT_ST: + qout_state = 1'b1; + + WRITE_MEM_ST: + write_mem_state = 1'b1; + + //WAIT_TRIGGER_ST: + endcase + end + + // Assign outputs. + + // BRAM for result storage + assign mem_we_o = write_mem_state; + assign mem_addr_o = addr_r; + assign mem_di_o = out_result_r; + +endmodule + diff --git a/firmware/ip/axis_weighted_buffer/src/avg_buffer.v b/firmware/ip/axis_weighted_buffer/src/avg_buffer.v new file mode 100644 index 0000000..7cf4959 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/avg_buffer.v @@ -0,0 +1,277 @@ +// Data is I,Q. +// I: lower B bits. +// Q: upper B bits. +module avg_buffer ( + // Reset and clock for readout data path + s_axis_aclk , + s_axis_aresetn , + + // Reset and clock for writing weights + s_axi_aclk , + s_axi_aresetn , + + // Trigger input. + trigger , + + // AXIS Slave for memory programming + s1_axis_tvalid, + s1_axis_tdata, + s1_axis_tready, + + // AXIS Slave for input data. + s_axis_tvalid , + s_axis_tready , + s_axis_tdata , + + // Reset and clock for m0, m1 and m2. + m_axis_aclk , + m_axis_aresetn , + + // AXIS Master for averaged output. + m0_axis_tvalid , + m0_axis_tready , + m0_axis_tdata , + m0_axis_tlast , + + // AXIS Master for raw output. + m1_axis_tvalid , + m1_axis_tready , + m1_axis_tdata , + m1_axis_tlast , + + // AXIS Master for register output. + m2_axis_tvalid , + m2_axis_tready , + m2_axis_tdata , + + // Registers. + AVG_START_REG , + AVG_ADDR_REG , + AVG_LEN_REG , + AVG_PHOTON_MODE_REG , + AVG_H_THRSH_REG , + AVG_L_THRSH_REG , + AVG_DR_START_REG , + AVG_DR_ADDR_REG , + AVG_DR_LEN_REG , + BUF_START_REG , + BUF_ADDR_REG , + BUF_LEN_REG , + BUF_DR_START_REG , + BUF_DR_ADDR_REG , + BUF_DR_LEN_REG, + WGT_DW_ADDR_REG, + WGT_DW_START_REG + ); + + //////////////// + // Parameters // + //////////////// + // Memory depth. + parameter N_AVG = 14; + parameter N_BUF = 14; + parameter N_WGT = 14; + + // Number of bits. + parameter B = 16; + + /////////// + // Ports // + /////////// + input s_axis_aclk; + input s_axis_aresetn; + + input s_axi_aclk; + input s_axi_aresetn; + + input trigger; + + input s_axis_tvalid; + output s_axis_tready; + input [2*B-1:0] s_axis_tdata; + + input s1_axis_tvalid; + input [2*B-1:0] s1_axis_tdata; + output s1_axis_tready; + + input m_axis_aclk; + input m_axis_aresetn; + + output m0_axis_tvalid; + input m0_axis_tready; + output [4*B-1:0] m0_axis_tdata; + output m0_axis_tlast; + + output m1_axis_tvalid; + input m1_axis_tready; + output [2*B-1:0] m1_axis_tdata; + output m1_axis_tlast; + + output m2_axis_tvalid; + input m2_axis_tready; + output [4*B-1:0] m2_axis_tdata; + + input AVG_START_REG; + input [N_AVG-1:0] AVG_ADDR_REG; + input [31:0] AVG_LEN_REG; + input AVG_PHOTON_MODE_REG; + input [B-1:0] AVG_H_THRSH_REG; + input [B-1:0] AVG_L_THRSH_REG; + input AVG_DR_START_REG; + input [N_AVG-1:0] AVG_DR_ADDR_REG; + input [N_AVG-1:0] AVG_DR_LEN_REG; + input BUF_START_REG; + input [N_BUF-1:0] BUF_ADDR_REG; + input [N_BUF-1:0] BUF_LEN_REG; + input BUF_DR_START_REG; + input [N_BUF-1:0] BUF_DR_ADDR_REG; + input [N_BUF-1:0] BUF_DR_LEN_REG; + + input [N_WGT-1:0] WGT_DW_ADDR_REG; + input WGT_DW_START_REG; + + + ////////////////////// + // Internal signals // + ////////////////////// + + wire trigger_resync; + + wire [2*B-1 : 0] s_axis_filtered_tdata; + wire s_axis_filtered_tvalid; + + + ////////////////// + // Architecture // + ////////////////// + + // trigger_resync + synchronizer_n + #( + .N (2) + ) + trigger_resync_i ( + .rstn (s_axis_aresetn ), + .clk (s_axis_aclk ), + .data_in (trigger ), + .data_out (trigger_resync ) + ); + + matched_filter + #( + .N (N_WGT), + .B (B) + ) + matchfilt_i + ( + .clk (s_axis_aclk), + + .write_rstn (s_axi_aresetn), + .write_clk (s_axi_aclk), + + .trigger_i (trigger_resync), + .trigger_o (trigger_dsp_latency_compensated), + + .s_axis_tready(s1_axis_tready), + .s_axis_tvalid(s1_axis_tvalid), + .s_axis_tdata(s1_axis_tdata), + + .din_valid_i (s_axis_tvalid), + .din_i (s_axis_tdata), + + .dout_valid_o (s_axis_filtered_tvalid), + .dout_o (s_axis_filtered_tdata), + + .DW_ADDR_REG(WGT_DW_ADDR_REG), + .WE_REG(WGT_DW_START_REG), + .LEN_REG(AVG_LEN_REG) + ); + + + // Average block. + avg_top + #( + .N (N_AVG ), + .B (B ) + ) + avg_top_i + ( + // Reset and clock. + .rstn (s_axis_aresetn ), + .clk (s_axis_aclk ), + + // Trigger input. + .trigger_i (trigger_dsp_latency_compensated ), + + // Data input. + .din_valid_i (s_axis_filtered_tvalid ), + .din_i (s_axis_filtered_tdata ), + + // Reset and clock for M_AXIS_* + .m_axis_aclk (m_axis_aclk ), + .m_axis_aresetn (m_axis_aresetn ), + + // AXIS Master for output. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tready (m0_axis_tready ), + .m0_axis_tdata (m0_axis_tdata ), + .m0_axis_tlast (m0_axis_tlast ), + + // AXIS Master for register output. + .m1_axis_tvalid (m2_axis_tvalid ), + .m1_axis_tready (m2_axis_tready ), + .m1_axis_tdata (m2_axis_tdata ), + + // Registers. + .AVG_START_REG (AVG_START_REG ), + .AVG_ADDR_REG (AVG_ADDR_REG ), + .AVG_LEN_REG (AVG_LEN_REG ), + .DR_START_REG (AVG_DR_START_REG ), + .DR_ADDR_REG (AVG_DR_ADDR_REG ), + .DR_LEN_REG (AVG_DR_LEN_REG ), + .AVG_PHOTON_MODE_REG (AVG_PHOTON_MODE_REG), + .AVG_H_THRSH_REG (AVG_H_THRSH_REG ), + .AVG_L_THRSH_REG (AVG_L_THRSH_REG ) + ); + + // Buffer block. + buffer_top + #( + .N (N_BUF ), + .B (B ) + ) + buffer_top_i + ( + // Reset and clock. + .rstn (s_axis_aresetn ), + .clk (s_axis_aclk ), + + // Trigger input. + .trigger_i (trigger_dsp_latency_compensated ), + + // Data input. + .din_valid_i (s_axis_filtered_tvalid ), + .din_i (s_axis_filtered_tdata ), + + // AXIS Master for output. + .m_axis_aclk (m_axis_aclk ), + .m_axis_aresetn (m_axis_aresetn ), + .m_axis_tvalid (m1_axis_tvalid ), + .m_axis_tready (m1_axis_tready ), + .m_axis_tdata (m1_axis_tdata ), + .m_axis_tlast (m1_axis_tlast ), + + // Registers. + .BUF_START_REG (BUF_START_REG ), + .BUF_ADDR_REG (BUF_ADDR_REG ), + .BUF_LEN_REG (BUF_LEN_REG ), + .DR_START_REG (BUF_DR_START_REG ), + .DR_ADDR_REG (BUF_DR_ADDR_REG ), + .DR_LEN_REG (BUF_DR_LEN_REG ) + ); + + // Assign outputs. + assign s_axis_tready = 1'b1; + +endmodule + diff --git a/firmware/ip/axis_weighted_buffer/src/avg_top.v b/firmware/ip/axis_weighted_buffer/src/avg_top.v new file mode 100644 index 0000000..6fa3851 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/avg_top.v @@ -0,0 +1,248 @@ +module avg_top ( + // Reset and clock. + rstn , + clk , + + // Trigger input. + trigger_i , + + // Data input. + din_valid_i , + din_i , + + // Reset and clock for M_AXIS_* + m_axis_aclk , + m_axis_aresetn , + + // AXIS Master for output. + m0_axis_tvalid , + m0_axis_tready , + m0_axis_tdata , + m0_axis_tlast , + + // AXIS Master for register output. + m1_axis_tvalid , + m1_axis_tready , + m1_axis_tdata , + + // Registers. + AVG_START_REG , + AVG_ADDR_REG , + AVG_LEN_REG , + DR_START_REG , + DR_ADDR_REG , + DR_LEN_REG , + AVG_PHOTON_MODE_REG , + AVG_H_THRSH_REG , + AVG_L_THRSH_REG + ); + + //////////////// + // Parameters // + //////////////// + // Memory depth. + parameter N = 14; + + // Number of bits. + parameter B = 16; + + /////////// + // Ports // + /////////// + input rstn; + input clk; + + input trigger_i; + + input din_valid_i; + input [2*B-1:0] din_i; + + + input m_axis_aclk; + input m_axis_aresetn; + + output m0_axis_tvalid; + input m0_axis_tready; + output [4*B-1:0] m0_axis_tdata; + output m0_axis_tlast; + + output m1_axis_tvalid; + input m1_axis_tready; + output [4*B-1:0] m1_axis_tdata; + + input AVG_START_REG; + input [N-1:0] AVG_ADDR_REG; + input [31:0] AVG_LEN_REG; + input DR_START_REG; + input [N-1:0] DR_ADDR_REG; + input [N-1:0] DR_LEN_REG; + input AVG_PHOTON_MODE_REG; + input [B-1:0] AVG_H_THRSH_REG; + input [B-1:0] AVG_L_THRSH_REG; + + ////////////////////// + // Internal signals // + ////////////////////// + + wire mem_envelope_wea; + wire [N-1:0] mem_envelope_addra, mem_envelope_addrb; + wire [4*B-1:0] mem_envelope_dia, mem_envelope_dob; + + wire mem_we_int; + wire [N-1:0] mem_addra_int, mem_addrb_int; + wire [4*B-1:0] mem_di_int, mem_do_int; + + wire AVG_START_REG_resync; + wire DR_START_REG_resync; + + wire fifo_empty; + + ////////////////// + // Architecture // + ////////////////// + + // AVG_START_REG_resync + synchronizer_n + #( + .N (2) + ) + AVG_START_REG_resync_i ( + .rstn (rstn ), + .clk (clk ), + .data_in (AVG_START_REG ), + .data_out (AVG_START_REG_resync ) + ); + + // DR_START_REG_resync + synchronizer_n + #( + .N (2) + ) + DR_START_REG_resync_i ( + .rstn (m_axis_aresetn ), + .clk (m_axis_aclk ), + .data_in (DR_START_REG ), + .data_out (DR_START_REG_resync ) + ); + + // Average block. + avg + #( + .N (N), + .B (B) + ) + avg_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Trigger input. + .trigger_i (trigger_i ), + + // Data input. + .din_valid_i (din_valid_i ), + .din_i (din_i ), + + // Memory interface. + .mem_we_o (mem_we_int ), + .mem_addr_o (mem_addra_int ), + .mem_di_o (mem_di_int ), + + // Registers. + .START_REG (AVG_START_REG_resync ), + .ADDR_REG (AVG_ADDR_REG ), + .LEN_REG (AVG_LEN_REG ), + .PHOTON_MODE_REG (AVG_PHOTON_MODE_REG), + .H_THRSH_REG (AVG_H_THRSH_REG ), + .L_THRSH_REG (AVG_L_THRSH_REG ) + ); + + + // Dual port BRAM. + bram_dp + #( + .N (N ), + .B (4*B) + ) + bram_i + ( + .clka (clk ), + .clkb (m_axis_aclk ), + .ena (1'b1 ), + .enb (1'b1 ), + .wea (mem_we_int ), + .web (1'b0 ), + .addra (mem_addra_int ), + .addrb (mem_addrb_int ), + .dia (mem_di_int ), + .dib ({4*B{1'b0}} ), + .doa ( ), + .dob (mem_do_int ) + ); + + // Data reader. + data_reader + #( + .N (N ), + .B (4*B) + ) + data_reader_i + ( + // Reset and clock. + .rstn (m_axis_aresetn ), + .clk (m_axis_aclk ), + + // Memory I/F. + .mem_en ( ), + .mem_we ( ), + .mem_addr (mem_addrb_int ), + .mem_dout (mem_do_int ), + + // Data out. + .dout (m0_axis_tdata ), + .dready (m0_axis_tready ), + .dvalid (m0_axis_tvalid ), + .dlast (m0_axis_tlast ), + + // Registers. + .START_REG (DR_START_REG_resync ), + .ADDR_REG (DR_ADDR_REG ), + .LEN_REG (DR_LEN_REG ) + ); + + // Output data register (dc fifo to cross domain). + fifo_dc_axi + #( + // Data width. + .B (4*B ), + + // Fifo depth. + .N (4 ) + ) + fifo_i + ( + .wr_rstn (rstn ), + .wr_clk (clk ), + + .rd_rstn (m_axis_aresetn ), + .rd_clk (m_axis_aclk ), + + // Write I/F. + .wr_en (mem_we_int ), + .din (mem_di_int ), + + // Read I/F. + .rd_en (m1_axis_tready ), + .dout (m1_axis_tdata ), + + // Flags. + .full ( ), + .empty (fifo_empty ) + ); + + // Assign outputs. + assign m1_axis_tvalid = ~fifo_empty; + +endmodule + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0.veo b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0.veo new file mode 100644 index 0000000..5653a79 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 14 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0.vho b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0.vho new file mode 100644 index 0000000..4ca1788 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,116 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 14 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + + + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..b7ba98a --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,215 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "axi_mst_0", + "component_reference": "xilinx.com:ip:axi_vip:1.1", + "ip_revision": "14", + "gen_directory": ".", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "axi_mst_0", "resolve_type": "user", "usage": "all" } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ], + "INTERFACE_MODE": [ { "value": "MASTER", "value_src": "user", "resolve_type": "user", "usage": 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axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_14 + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_14 + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + VIP_PKG_NAME + VIP_PKG_NAME + 0 + + + + + AXI Verification IP + + xtlm + xtlm_ipc_v1_0 + protobuf + + 14 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + + + + + + + + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0_ooc.xdc b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0_ooc.xdc new file mode 100644 index 0000000..bb1ff41 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/axi_mst_0_ooc.xdc @@ -0,0 +1,57 @@ +# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of AMD and is protected under U.S. and international copyright +# and other intellectual property laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# AMD, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) AMD shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or AMD had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# AMD products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of AMD products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# DO NOT MODIFY THIS FILE. +# ######################################################### +# +# This XDC is used only in OOC mode for synthesis, implementation +# +# ######################################################### + + +create_clock -period 10 -name aclk [get_ports aclk] + + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/doc/axi_vip_v1_1_changelog.txt b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/doc/axi_vip_v1_1_changelog.txt new file mode 100644 index 0000000..967c3dc --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/doc/axi_vip_v1_1_changelog.txt @@ -0,0 +1,198 @@ +2023.1: + * Version 1.1 (Rev. 14) + * Revision change in one or more subcores + +2022.2.2: + * Version 1.1 (Rev. 13) + * No changes + +2022.2.1: + * Version 1.1 (Rev. 13) + * No changes + +2022.2: + * Version 1.1 (Rev. 13) + * Revision change in one or more subcores + +2022.1.2: + * Version 1.1 (Rev. 12) + * No changes + +2022.1.1: + * Version 1.1 (Rev. 12) + * No changes + +2022.1: + * Version 1.1 (Rev. 12) + * General: bug fix, + * Revision change in one or more subcores + +2021.2.2: + * Version 1.1 (Rev. 11) + * No changes + +2021.2.1: + * Version 1.1 (Rev. 11) + * No changes + +2021.2: + * Version 1.1 (Rev. 11) + * General: Run time enhancements, fix + * General: Fixed systemC model, unbound aresetn port - fix + * Revision change in one or more subcores + +2021.1.1: + * Version 1.1 (Rev. 10) + * No changes + +2021.1: + * Version 1.1 (Rev. 10) + * General: added external process traffic generation support using XTLM IPC for SystemC Models + * Revision change in one or more subcores + +2020.3: + * Version 1.1 (Rev. 9) + * Revision change in one or more subcores + +2020.2.2: + * Version 1.1 (Rev. 8) + * No changes + +2020.2.1: + * Version 1.1 (Rev. 8) + * No changes + +2020.2: + * Version 1.1 (Rev. 8) + * General: added new feature + * Revision change in one or more subcores + +2020.1.1: + * Version 1.1 (Rev. 7) + * No changes + +2020.1: + * Version 1.1 (Rev. 7) + * General: added new feature + * Revision change in one or more subcores + +2019.2.2: + * Version 1.1 (Rev. 6) + * No changes + +2019.2.1: + * Version 1.1 (Rev. 6) + * No changes + +2019.2: + * Version 1.1 (Rev. 6) + * General: update example design for portable + * Revision change in one or more subcores + +2019.1.3: + * Version 1.1 (Rev. 5) + * No changes + +2019.1.2: + * Version 1.1 (Rev. 5) + * No changes + +2019.1.1: + * Version 1.1 (Rev. 5) + * No changes + +2019.1: + * Version 1.1 (Rev. 5) + * General: update to have has_size + * Revision change in one or more subcores + +2018.3.1: + * Version 1.1 (Rev. 4) + * No changes + +2018.3: + * Version 1.1 (Rev. 4) + * General: update QOS in user interface tcl to match AXI meta-data in IPI + * Revision change in one or more subcores + +2018.2: + * Version 1.1 (Rev. 3) + * General: fixed typo in example design stimulus + * Revision change in one or more subcores + +2018.1: + * Version 1.1 (Rev. 2) + * General: updated coreinfo.yml,fix + * Revision change in one or more subcores + +2017.4: + * Version 1.1 (Rev. 1) + * General: updated example design + * General: added slv_rd_driver verbosity + * General: modified interface assertion + * Revision change in one or more subcores + +2017.3: + * Version 1.1 + * versionless of package, interface and PC + * Revision change in one or more subcores + +2017.2: + * Version 1.0 (Rev. 2) + * Sub core IP clk_wiz version changed to 5.4 + * Revision change in one or more subcores + +2017.1: + * Version 1.0 (Rev. 1) + * production release + * Revision change in one or more subcores + +2016.4: + * Version 1.0 + * Initial Release + +(c) Copyright 2016 - 2023 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_infrastructure_v1_1_0.vh b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_infrastructure_v1_1_0.vh new file mode 100644 index 0000000..d3d4a0e --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_infrastructure_v1_1_0.vh @@ -0,0 +1,138 @@ +// (c) Copyright 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// Generic Functions used by AXI Infrastructure Modules +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// Global Parameters: +// +// Functions: +// +// Tasks: +//-------------------------------------------------------------------------- +/////////////////////////////////////////////////////////////////////////////// +// BEGIN Global Parameters +/////////////////////////////////////////////////////////////////////////////// +localparam G_AXI_AWADDR_INDEX = 0; +localparam G_AXI_AWADDR_WIDTH = C_AXI_ADDR_WIDTH; +localparam G_AXI_AWPROT_INDEX = G_AXI_AWADDR_INDEX + G_AXI_AWADDR_WIDTH; +localparam G_AXI_AWPROT_WIDTH = 3; +localparam G_AXI_AWSIZE_INDEX = G_AXI_AWPROT_INDEX + G_AXI_AWPROT_WIDTH; +localparam G_AXI_AWSIZE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 3; +localparam G_AXI_AWBURST_INDEX = G_AXI_AWSIZE_INDEX + G_AXI_AWSIZE_WIDTH; +localparam G_AXI_AWBURST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 2; +localparam G_AXI_AWCACHE_INDEX = G_AXI_AWBURST_INDEX + G_AXI_AWBURST_WIDTH; +localparam G_AXI_AWCACHE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4; +localparam G_AXI_AWLEN_INDEX = G_AXI_AWCACHE_INDEX + G_AXI_AWCACHE_WIDTH; +localparam G_AXI_AWLEN_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8; +localparam G_AXI_AWLOCK_INDEX = G_AXI_AWLEN_INDEX + G_AXI_AWLEN_WIDTH; +localparam G_AXI_AWLOCK_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1; +localparam G_AXI_AWID_INDEX = G_AXI_AWLOCK_INDEX + G_AXI_AWLOCK_WIDTH; +localparam G_AXI_AWID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_AWQOS_INDEX = G_AXI_AWID_INDEX + G_AXI_AWID_WIDTH; +localparam G_AXI_AWQOS_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4; +localparam G_AXI_AWREGION_INDEX = G_AXI_AWQOS_INDEX + G_AXI_AWQOS_WIDTH; +localparam G_AXI_AWREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4; +localparam G_AXI_AWUSER_INDEX = G_AXI_AWREGION_INDEX + G_AXI_AWREGION_WIDTH; +localparam G_AXI_AWUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_AWUSER_WIDTH; +localparam G_AXI_AWPAYLOAD_WIDTH = G_AXI_AWUSER_INDEX + G_AXI_AWUSER_WIDTH; +localparam G_AXI_ARADDR_INDEX = 0; +localparam G_AXI_ARADDR_WIDTH = C_AXI_ADDR_WIDTH; +localparam G_AXI_ARPROT_INDEX = G_AXI_ARADDR_INDEX + G_AXI_ARADDR_WIDTH; +localparam G_AXI_ARPROT_WIDTH = 3; +localparam G_AXI_ARSIZE_INDEX = G_AXI_ARPROT_INDEX + G_AXI_ARPROT_WIDTH; +localparam G_AXI_ARSIZE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 3; +localparam G_AXI_ARBURST_INDEX = G_AXI_ARSIZE_INDEX + G_AXI_ARSIZE_WIDTH; +localparam G_AXI_ARBURST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 2; +localparam G_AXI_ARCACHE_INDEX = G_AXI_ARBURST_INDEX + G_AXI_ARBURST_WIDTH; +localparam G_AXI_ARCACHE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4; +localparam G_AXI_ARLEN_INDEX = G_AXI_ARCACHE_INDEX + G_AXI_ARCACHE_WIDTH; +localparam G_AXI_ARLEN_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8; +localparam G_AXI_ARLOCK_INDEX = G_AXI_ARLEN_INDEX + G_AXI_ARLEN_WIDTH; +localparam G_AXI_ARLOCK_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1; +localparam G_AXI_ARID_INDEX = G_AXI_ARLOCK_INDEX + G_AXI_ARLOCK_WIDTH; +localparam G_AXI_ARID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_ARQOS_INDEX = G_AXI_ARID_INDEX + G_AXI_ARID_WIDTH; +localparam G_AXI_ARQOS_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4; +localparam G_AXI_ARREGION_INDEX = G_AXI_ARQOS_INDEX + G_AXI_ARQOS_WIDTH; +localparam G_AXI_ARREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4; +localparam G_AXI_ARUSER_INDEX = G_AXI_ARREGION_INDEX + G_AXI_ARREGION_WIDTH; +localparam G_AXI_ARUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_ARUSER_WIDTH; +localparam G_AXI_ARPAYLOAD_WIDTH = G_AXI_ARUSER_INDEX + G_AXI_ARUSER_WIDTH; +// Write channel widths +localparam G_AXI_WDATA_INDEX = 0; +localparam G_AXI_WDATA_WIDTH = C_AXI_DATA_WIDTH; +localparam G_AXI_WSTRB_INDEX = G_AXI_WDATA_INDEX + G_AXI_WDATA_WIDTH; +localparam G_AXI_WSTRB_WIDTH = C_AXI_DATA_WIDTH / 8; +localparam G_AXI_WLAST_INDEX = G_AXI_WSTRB_INDEX + G_AXI_WSTRB_WIDTH; +localparam G_AXI_WLAST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 1; +localparam G_AXI_WID_INDEX = G_AXI_WLAST_INDEX + G_AXI_WLAST_WIDTH; +localparam G_AXI_WID_WIDTH = (C_AXI_PROTOCOL != 1) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_WUSER_INDEX = G_AXI_WID_INDEX + G_AXI_WID_WIDTH; +localparam G_AXI_WUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_WUSER_WIDTH; +localparam G_AXI_WPAYLOAD_WIDTH = G_AXI_WUSER_INDEX + G_AXI_WUSER_WIDTH; +// Write Response channel Widths +localparam G_AXI_BRESP_INDEX = 0; +localparam G_AXI_BRESP_WIDTH = 2; +localparam G_AXI_BID_INDEX = G_AXI_BRESP_INDEX + G_AXI_BRESP_WIDTH; +localparam G_AXI_BID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_BUSER_INDEX = G_AXI_BID_INDEX + G_AXI_BID_WIDTH; +localparam G_AXI_BUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_BUSER_WIDTH; +localparam G_AXI_BPAYLOAD_WIDTH = G_AXI_BUSER_INDEX + G_AXI_BUSER_WIDTH; +// Read channel widths +localparam G_AXI_RDATA_INDEX = 0; +localparam G_AXI_RDATA_WIDTH = C_AXI_DATA_WIDTH; +localparam G_AXI_RRESP_INDEX = G_AXI_RDATA_INDEX + G_AXI_RDATA_WIDTH; +localparam G_AXI_RRESP_WIDTH = 2; +localparam G_AXI_RLAST_INDEX = G_AXI_RRESP_INDEX + G_AXI_RRESP_WIDTH; +localparam G_AXI_RLAST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 1; +localparam G_AXI_RID_INDEX = G_AXI_RLAST_INDEX + G_AXI_RLAST_WIDTH; +localparam G_AXI_RID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH; +localparam G_AXI_RUSER_INDEX = G_AXI_RID_INDEX + G_AXI_RID_WIDTH; +localparam G_AXI_RUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_RUSER_WIDTH; +localparam G_AXI_RPAYLOAD_WIDTH = G_AXI_RUSER_INDEX + G_AXI_RUSER_WIDTH; diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_infrastructure_v1_1_vl_rfs.v b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_infrastructure_v1_1_vl_rfs.v new file mode 100644 index 0000000..d6ec7f8 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_infrastructure_v1_1_vl_rfs.v @@ -0,0 +1,670 @@ +// (c) Copyright 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// axis to vector +// A generic module to merge all axi signals into one signal called payload. +// This is strictly wires, so no clk, reset, aclken, valid/ready are required. +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// + +`timescale 1ps/1ps +`default_nettype none + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_infrastructure_v1_1_0_axi2vector # +( +/////////////////////////////////////////////////////////////////////////////// +// Parameter Definitions +/////////////////////////////////////////////////////////////////////////////// + parameter integer C_AXI_PROTOCOL = 0, + parameter integer C_AXI_ID_WIDTH = 4, + parameter integer C_AXI_ADDR_WIDTH = 32, + parameter integer C_AXI_DATA_WIDTH = 32, + parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, + parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0, + parameter integer C_AXI_AWUSER_WIDTH = 1, + parameter integer C_AXI_WUSER_WIDTH = 1, + parameter integer C_AXI_BUSER_WIDTH = 1, + parameter integer C_AXI_ARUSER_WIDTH = 1, + parameter integer C_AXI_RUSER_WIDTH = 1, + parameter integer C_AWPAYLOAD_WIDTH = 61, + parameter integer C_WPAYLOAD_WIDTH = 73, + parameter integer C_BPAYLOAD_WIDTH = 6, + parameter integer C_ARPAYLOAD_WIDTH = 61, + parameter integer C_RPAYLOAD_WIDTH = 69 +) +( +/////////////////////////////////////////////////////////////////////////////// +// Port Declarations +/////////////////////////////////////////////////////////////////////////////// + // Slave Interface Write Address Ports + input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid, + input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, + input wire [3-1:0] s_axi_awsize, + input wire [2-1:0] s_axi_awburst, + input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, + input wire [4-1:0] s_axi_awcache, + input wire [3-1:0] s_axi_awprot, + input wire [4-1:0] s_axi_awregion, + input wire [4-1:0] s_axi_awqos, + input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, + + // Slave Interface Write Data Ports + input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid, + input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata, + input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, + input wire s_axi_wlast, + input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, + + // Slave Interface Write Response Ports + output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid, + output wire [2-1:0] s_axi_bresp, + output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser, + + // Slave Interface Read Address Ports + input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid, + input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, + input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, + input wire [3-1:0] s_axi_arsize, + input wire [2-1:0] s_axi_arburst, + input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, + input wire [4-1:0] s_axi_arcache, + input wire [3-1:0] s_axi_arprot, + input wire [4-1:0] s_axi_arregion, + input wire [4-1:0] s_axi_arqos, + input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, + + // Slave Interface Read Data Ports + output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid, + output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata, + output wire [2-1:0] s_axi_rresp, + output wire s_axi_rlast, + output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, + + // payloads + output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload, + output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload, + input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload, + output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload, + input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload +); + +//////////////////////////////////////////////////////////////////////////////// +// Functions +//////////////////////////////////////////////////////////////////////////////// +`include "axi_infrastructure_v1_1_0.vh" + +//////////////////////////////////////////////////////////////////////////////// +// Local parameters +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// Wires/Reg declarations +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// BEGIN RTL +//////////////////////////////////////////////////////////////////////////////// + +// AXI4, AXI4LITE, AXI3 packing +assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr; +assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot; + +assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata; +assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb; + +assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH]; + +assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr; +assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot; + +assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH]; +assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH]; + +generate + if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing + assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize; + assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst; + assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache; + assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen; + assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock; + assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid; + assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos; + + assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast; + if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing + assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid; + end + else begin : gen_no_axi3_wid_packing + end + + assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH]; + + assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize; + assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst; + assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache; + assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen; + assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock; + assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid; + assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos; + + assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH]; + assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH]; + + if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals + assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion; + assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion; + end + else begin : gen_no_region_signals + end + if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals + assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser; + assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser; + assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH]; + assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser; + assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH]; + end + else begin : gen_no_user_signals + assign s_axi_buser = 'b0; + assign s_axi_ruser = 'b0; + end + end + else begin : gen_axi4lite_packing + assign s_axi_bid = 'b0; + assign s_axi_buser = 'b0; + + assign s_axi_rlast = 1'b1; + assign s_axi_rid = 'b0; + assign s_axi_ruser = 'b0; + end +endgenerate +endmodule + +`default_nettype wire + + +// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// Description: SRL based FIFO for AXIS/AXI Channels. +//-------------------------------------------------------------------------- + + +`timescale 1ps/1ps +`default_nettype none + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_infrastructure_v1_1_0_axic_srl_fifo #( +/////////////////////////////////////////////////////////////////////////////// +// Parameter Definitions +/////////////////////////////////////////////////////////////////////////////// + parameter C_FAMILY = "virtex7", + parameter integer C_PAYLOAD_WIDTH = 1, + parameter integer C_FIFO_DEPTH = 16 // Range: 4-16. +) +( +/////////////////////////////////////////////////////////////////////////////// +// Port Declarations +/////////////////////////////////////////////////////////////////////////////// + input wire aclk, // Clock + input wire aresetn, // Reset + input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data + input wire s_valid, // Input data valid + output reg s_ready, // Input data ready + output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data + output reg m_valid, // Output data valid + input wire m_ready // Output data ready +); +//////////////////////////////////////////////////////////////////////////////// +// Functions +//////////////////////////////////////////////////////////////////////////////// +// ceiling logb2 +function integer f_clogb2 (input integer size); + integer s; + begin + s = size; + s = s - 1; + for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1) + s = s >> 1; + end +endfunction // clogb2 + +//////////////////////////////////////////////////////////////////////////////// +// Local parameters +//////////////////////////////////////////////////////////////////////////////// +localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH); + +//////////////////////////////////////////////////////////////////////////////// +// Wires/Reg declarations +//////////////////////////////////////////////////////////////////////////////// +reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index; +wire [4-1:0] fifo_addr; +wire push; +wire pop ; +reg areset_r1; + +//////////////////////////////////////////////////////////////////////////////// +// BEGIN RTL +//////////////////////////////////////////////////////////////////////////////// + +always @(posedge aclk) begin + areset_r1 <= ~aresetn; +end + +always @(posedge aclk) begin + if (~aresetn) begin + fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}}; + end + else begin + fifo_index <= push & ~pop ? fifo_index + 1'b1 : + ~push & pop ? fifo_index - 1'b1 : + fifo_index; + end +end + +assign push = s_valid & s_ready; + +always @(posedge aclk) begin + if (~aresetn) begin + s_ready <= 1'b0; + end + else begin + s_ready <= areset_r1 ? 1'b1 : + push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 : + ~push & pop ? 1'b1 : + s_ready; + end +end + +assign pop = m_valid & m_ready; + +always @(posedge aclk) begin + if (~aresetn) begin + m_valid <= 1'b0; + end + else begin + m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 : + push & ~pop ? 1'b1 : + m_valid; + end +end + +generate + if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr + assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; + assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}}; + end + else begin : gen_fifo_addr + assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; + end +endgenerate + + +generate + genvar i; + for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit + SRL16E + u_srl_fifo( + .Q ( m_payload[i] ) , + .A0 ( fifo_addr[0] ) , + .A1 ( fifo_addr[1] ) , + .A2 ( fifo_addr[2] ) , + .A3 ( fifo_addr[3] ) , + .CE ( push ) , + .CLK ( aclk ) , + .D ( s_payload[i] ) + ); + end +endgenerate + +endmodule + +`default_nettype wire + + +// (c) Copyright 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// axi to vector +// A generic module to merge all axi signals into one signal called payload. +// This is strictly wires, so no clk, reset, aclken, valid/ready are required. +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// + +`timescale 1ps/1ps +`default_nettype none + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_infrastructure_v1_1_0_vector2axi # +( +/////////////////////////////////////////////////////////////////////////////// +// Parameter Definitions +/////////////////////////////////////////////////////////////////////////////// + parameter integer C_AXI_PROTOCOL = 0, + parameter integer C_AXI_ID_WIDTH = 4, + parameter integer C_AXI_ADDR_WIDTH = 32, + parameter integer C_AXI_DATA_WIDTH = 32, + parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, + parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0, + parameter integer C_AXI_AWUSER_WIDTH = 1, + parameter integer C_AXI_WUSER_WIDTH = 1, + parameter integer C_AXI_BUSER_WIDTH = 1, + parameter integer C_AXI_ARUSER_WIDTH = 1, + parameter integer C_AXI_RUSER_WIDTH = 1, + parameter integer C_AWPAYLOAD_WIDTH = 61, + parameter integer C_WPAYLOAD_WIDTH = 73, + parameter integer C_BPAYLOAD_WIDTH = 6, + parameter integer C_ARPAYLOAD_WIDTH = 61, + parameter integer C_RPAYLOAD_WIDTH = 69 +) +( +/////////////////////////////////////////////////////////////////////////////// +// Port Declarations +/////////////////////////////////////////////////////////////////////////////// + // Slave Interface Write Address Ports + output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid, + output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, + output wire [3-1:0] m_axi_awsize, + output wire [2-1:0] m_axi_awburst, + output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, + output wire [4-1:0] m_axi_awcache, + output wire [3-1:0] m_axi_awprot, + output wire [4-1:0] m_axi_awregion, + output wire [4-1:0] m_axi_awqos, + output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, + + // Slave Interface Write Data Ports + output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid, + output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata, + output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, + output wire m_axi_wlast, + output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, + + // Slave Interface Write Response Ports + input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid, + input wire [2-1:0] m_axi_bresp, + input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser, + + // Slave Interface Read Address Ports + output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid, + output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, + output wire [3-1:0] m_axi_arsize, + output wire [2-1:0] m_axi_arburst, + output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, + output wire [4-1:0] m_axi_arcache, + output wire [3-1:0] m_axi_arprot, + output wire [4-1:0] m_axi_arregion, + output wire [4-1:0] m_axi_arqos, + output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, + + // Slave Interface Read Data Ports + input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid, + input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, + input wire [2-1:0] m_axi_rresp, + input wire m_axi_rlast, + input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, + + // payloads + input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload, + input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload, + output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload, + input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload, + output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload +); + +//////////////////////////////////////////////////////////////////////////////// +// Functions +//////////////////////////////////////////////////////////////////////////////// +`include "axi_infrastructure_v1_1_0.vh" + +//////////////////////////////////////////////////////////////////////////////// +// Local parameters +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// Wires/Reg declarations +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// BEGIN RTL +//////////////////////////////////////////////////////////////////////////////// + +// AXI4, AXI4LITE, AXI3 packing +assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH]; +assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH]; + +assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH]; +assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH]; + +assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp; + +assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH]; +assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH]; + +assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata; +assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp; + +generate + if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing + assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ; + assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH]; + assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH]; + assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ; + assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ; + assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ; + assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ; + + assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ; + if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing + assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ; + end + else begin : gen_no_axi3_wid_packing + assign m_axi_wid = 1'b0; + end + + assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid; + + assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ; + assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH]; + assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH]; + assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ; + assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ; + assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ; + assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ; + + assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast; + assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ; + + if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals + assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH]; + assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH]; + end + else begin : gen_no_region_signals + assign m_axi_awregion = 'b0; + assign m_axi_arregion = 'b0; + end + if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals + assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH]; + assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ; + assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ; + assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH]; + assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ; + end + else begin : gen_no_user_signals + assign m_axi_awuser = 'b0; + assign m_axi_wuser = 'b0; + assign m_axi_aruser = 'b0; + end + end + else begin : gen_axi4lite_packing + assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; + assign m_axi_awburst = 'b0; + assign m_axi_awcache = 'b0; + assign m_axi_awlen = 'b0; + assign m_axi_awlock = 'b0; + assign m_axi_awid = 'b0; + assign m_axi_awqos = 'b0; + + assign m_axi_wlast = 1'b1; + assign m_axi_wid = 'b0; + + + assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; + assign m_axi_arburst = 'b0; + assign m_axi_arcache = 'b0; + assign m_axi_arlen = 'b0; + assign m_axi_arlock = 'b0; + assign m_axi_arid = 'b0; + assign m_axi_arqos = 'b0; + + assign m_axi_awregion = 'b0; + assign m_axi_arregion = 'b0; + + assign m_axi_awuser = 'b0; + assign m_axi_wuser = 'b0; + assign m_axi_aruser = 'b0; + end +endgenerate +endmodule + +`default_nettype wire + + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_vip_v1_1_vl_rfs.sv b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_vip_v1_1_vl_rfs.sv new file mode 100644 index 0000000..589cf87 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_vip_v1_1_vl_rfs.sv @@ -0,0 +1,633 @@ +// (c) Copyright 2016 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// AXI VIP wrapper +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// axi_vip +// +//-------------------------------------------------------------------------- + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_vip_v1_1_14_top # + ( + parameter C_AXI_PROTOCOL = 0, + parameter C_AXI_INTERFACE_MODE = 1, //master, slave and bypass + parameter integer C_AXI_ADDR_WIDTH = 32, + parameter integer C_AXI_WDATA_WIDTH = 32, + parameter integer C_AXI_RDATA_WIDTH = 32, + parameter integer C_AXI_WID_WIDTH = 0, + parameter integer C_AXI_RID_WIDTH = 0, + parameter integer C_AXI_AWUSER_WIDTH = 0, + parameter integer C_AXI_ARUSER_WIDTH = 0, + parameter integer C_AXI_WUSER_WIDTH = 0, + parameter integer C_AXI_RUSER_WIDTH = 0, + parameter integer C_AXI_BUSER_WIDTH = 0, + parameter integer C_AXI_SUPPORTS_NARROW = 1, + parameter integer C_AXI_HAS_BURST = 1, + parameter integer C_AXI_HAS_LOCK = 1, + parameter integer C_AXI_HAS_CACHE = 1, + parameter integer C_AXI_HAS_REGION = 1, + parameter integer C_AXI_HAS_PROT = 1, + parameter integer C_AXI_HAS_QOS = 1, + parameter integer C_AXI_HAS_WSTRB = 1, + parameter integer C_AXI_HAS_BRESP = 1, + parameter integer C_AXI_HAS_RRESP = 1, + parameter integer C_AXI_HAS_ARESETN = 1 + ) + ( + //NOTE: C_AXI_INTERFACE_MODE =0 means MASTER MODE, 1 means PASS-THROUGH MODE and 2 means SLAVE MODE + //Please refer xgui tcl and coreinfo.yml + + // System Signals + input wire aclk, + input wire aclken, + input wire aresetn, + + // Slave Interface Write Address Ports + input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_awid, + input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, + input wire [3-1:0] s_axi_awsize, + input wire [2-1:0] s_axi_awburst, + input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, + input wire [4-1:0] s_axi_awcache, + input wire [3-1:0] s_axi_awprot, + input wire [4-1:0] s_axi_awregion, + input wire [4-1:0] s_axi_awqos, + input wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, + input wire s_axi_awvalid, + output wire s_axi_awready, + + // Slave Interface Write Data Ports + input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_wid, + input wire [C_AXI_WDATA_WIDTH-1:0] s_axi_wdata, + input wire [C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0] s_axi_wstrb, + input wire s_axi_wlast, + input wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, + input wire s_axi_wvalid, + output wire s_axi_wready, + + // Slave Interface Write Response Ports + output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_bid, + output wire [2-1:0] s_axi_bresp, + output wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] s_axi_buser, + output wire s_axi_bvalid, + input wire s_axi_bready, + + // Slave Interface Read Address Ports + input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_arid, + input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, + input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, + input wire [3-1:0] s_axi_arsize, + input wire [2-1:0] s_axi_arburst, + input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, + input wire [4-1:0] s_axi_arcache, + input wire [3-1:0] s_axi_arprot, + input wire [4-1:0] s_axi_arregion, + input wire [4-1:0] s_axi_arqos, + input wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, + input wire s_axi_arvalid, + output wire s_axi_arready, + + // Slave Interface Read Data Ports + output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_rid, + output wire [C_AXI_RDATA_WIDTH-1:0] s_axi_rdata, + output wire [2-1:0] s_axi_rresp, + output wire s_axi_rlast, + output wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, + output wire s_axi_rvalid, + input wire s_axi_rready, + + // Master Interface Write Address Port + output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_awid, + output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, + output wire [3-1:0] m_axi_awsize, + output wire [2-1:0] m_axi_awburst, + output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, + output wire [4-1:0] m_axi_awcache, + output wire [3-1:0] m_axi_awprot, + output wire [4-1:0] m_axi_awregion, + output wire [4-1:0] m_axi_awqos, + output wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, + output wire m_axi_awvalid, + input wire m_axi_awready, + + // Master Interface Write Data Ports + output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_wid, + output wire [C_AXI_WDATA_WIDTH-1:0] m_axi_wdata, + output wire [C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0] m_axi_wstrb, + output wire m_axi_wlast, + output wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, + output wire m_axi_wvalid, + input wire m_axi_wready, + + // Master Interface Write Response Ports + input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_bid, + input wire [2-1:0] m_axi_bresp, + input wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] m_axi_buser, + input wire m_axi_bvalid, + output wire m_axi_bready, + + // Master Interface Read Address Port + output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_arid, + output wire [ C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, + output wire [3-1:0] m_axi_arsize, + output wire [2-1:0] m_axi_arburst, + output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, + output wire [4-1:0] m_axi_arcache, + output wire [3-1:0] m_axi_arprot, + output wire [4-1:0] m_axi_arregion, + output wire [4-1:0] m_axi_arqos, + output wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, + output wire m_axi_arvalid, + input wire m_axi_arready, + + // Master Interface Read Data Ports + input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_rid, + input wire [C_AXI_RDATA_WIDTH-1:0] m_axi_rdata, + input wire [2-1:0] m_axi_rresp, + input wire m_axi_rlast, + input wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, + input wire m_axi_rvalid, + output wire m_axi_rready + ); + + /********************************************************************************************** + * NOTE: + * C_AXI_INTERFACE_MODE =0 -- MASTER MODE, + * C_AXI_INTERFACE_MODE =1 -- PASS-THROUGH MODE + * C_AXI_INTERFACE_MODE =2 -- SLAVE MODE + * Please refer xgui tcl and coreinfo.yml + * User can change PASS_THROUGH VIP to run time master mode or run time slave mode during + * the simulation + *********************************************************************************************/ + + /********************************************************************************************** + * Master_mode means that either the dut is statically being configured to be in master mode + * or it statically being configured to be pass-through mode and switched to be in master mode + * in run time. + + * Slave mode means that either the dut is statically being configured to be in slave mode + * or it statically being configured to be pass-through mode and switched to be in slave mode + * in run time. + + * Pass-through mode means that either the dut is statically being configured to be in + * pass-through mode or it statically being configured to be pass-through mode and switched + * to be in master/slave mode and then switch back to be in pass-through mode in run time + *********************************************************************************************/ + + logic runtime_master =0; + logic runtime_slave =0; + + wire run_slave_mode; + wire run_master_mode; + wire run_passth_mode; + wire compile_master_mode; + wire compile_slave_mode; + wire master_mode; + wire slave_mode; + + assign run_master_mode = (C_AXI_INTERFACE_MODE ==1 && runtime_master ==1 &&runtime_slave ==0); + assign run_slave_mode = C_AXI_INTERFACE_MODE ==1 && runtime_slave ==1 && runtime_master ==0; + assign run_passth_mode = (runtime_slave ==0 && runtime_master ==0); + + assign compile_master_mode = (C_AXI_INTERFACE_MODE ==0 || C_AXI_INTERFACE_MODE ==1 )&& run_passth_mode ; + assign compile_slave_mode = (C_AXI_INTERFACE_MODE ==2 || C_AXI_INTERFACE_MODE ==1) && run_passth_mode ; + + assign master_mode = compile_master_mode || run_master_mode; + assign slave_mode = compile_slave_mode || run_slave_mode; + + // Slave Interface Write Address Ports Internal + assign IF.AWID = slave_mode? s_axi_awid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}}; + assign IF.AWADDR = slave_mode? s_axi_awaddr : {C_AXI_ADDR_WIDTH{1'bz}}; + assign IF.AWLEN = slave_mode? s_axi_awlen : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}}; + assign IF.AWSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_awsize): {3{1'bz}}; + assign IF.AWBURST = slave_mode? s_axi_awburst : {2{1'bz}}; + assign IF.AWLOCK = slave_mode? s_axi_awlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}}; + assign IF.AWCACHE = slave_mode? s_axi_awcache : {4{1'bz}}; + assign IF.AWPROT = slave_mode? s_axi_awprot : {3{1'bz}}; + assign IF.AWREGION = slave_mode? s_axi_awregion : {4{1'bz}}; + assign IF.AWQOS = slave_mode? s_axi_awqos : {4{1'bz}}; + assign IF.AWUSER = slave_mode? s_axi_awuser : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'bz}}; + assign IF.AWVALID = slave_mode? s_axi_awvalid : {1'bz}; + assign s_axi_awready = slave_mode? IF.AWREADY : {1'b0}; + + // Slave Interface Write Data Ports + assign IF.WID = slave_mode? s_axi_wid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}}; + assign IF.WDATA = slave_mode? s_axi_wdata : {C_AXI_WDATA_WIDTH{1'bz}}; + assign IF.WSTRB = slave_mode? s_axi_wstrb : {(C_AXI_WDATA_WIDTH/8){1'bz}}; + assign IF.WLAST = slave_mode? s_axi_wlast: {1'bz}; + assign IF.WUSER = slave_mode? s_axi_wuser : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'bz}}; + assign IF.WVALID = slave_mode? s_axi_wvalid : {1'bz}; + assign s_axi_wready = slave_mode? IF.WREADY : {1'b0}; + + // Slave Interface Write Response Ports + assign s_axi_bid = slave_mode? IF.BID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}}; + assign s_axi_bresp = slave_mode? IF.BRESP : {2{1'b0}}; + assign s_axi_buser = slave_mode? IF.BUSER : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'b0}}; + assign s_axi_bvalid = slave_mode? IF.BVALID : {1{1'b0}}; + assign IF.BREADY = slave_mode? s_axi_bready :{1{1'bz}}; + + // Slave Interface Read Address Ports + assign IF.ARID = slave_mode? s_axi_arid :{C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}}; + assign IF.ARADDR = slave_mode? s_axi_araddr : {C_AXI_ADDR_WIDTH{1'bz}} ; + assign IF.ARLEN = slave_mode? s_axi_arlen: {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}}; + assign IF.ARSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_arsize) : {3{1'bz}}; + assign IF.ARBURST = slave_mode? s_axi_arburst : {2{1'bz}}; + assign IF.ARLOCK = slave_mode? s_axi_arlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}}; + assign IF.ARCACHE = slave_mode? s_axi_arcache : {4{1'bz}}; + assign IF.ARPROT = slave_mode? s_axi_arprot : {3{1'bz}}; + assign IF.ARREGION = slave_mode? s_axi_arregion :{4{1'bz}} ; + assign IF.ARQOS = slave_mode? s_axi_arqos : {4{1'bz}}; + assign IF.ARUSER = slave_mode? s_axi_aruser :{C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'bz}}; + assign IF.ARVALID = slave_mode? s_axi_arvalid : {1'bz}; + assign s_axi_arready = slave_mode? IF.ARREADY : {1'b0}; + + //Slave Interface Read Data Ports + assign s_axi_rid = slave_mode? IF.RID: {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}}; + assign s_axi_rdata = slave_mode? IF.RDATA : {C_AXI_RDATA_WIDTH{1'b0}}; + assign s_axi_rresp = slave_mode? IF.RRESP : {2{1'b0}}; + assign s_axi_rlast = slave_mode? IF.RLAST : {{1'b0}}; + assign s_axi_ruser = slave_mode? IF.RUSER : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'b0}}; + assign s_axi_rvalid = slave_mode? IF.RVALID : {{1'b0}}; + assign IF.RREADY = slave_mode? s_axi_rready:{{1'bz}}; + + // Master Interface Write Address Port + assign m_axi_awid = master_mode? IF.AWID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}}; + assign m_axi_awaddr = master_mode? IF.AWADDR : {C_AXI_ADDR_WIDTH{1'b0}}; + assign m_axi_awlen = master_mode? IF.AWLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}}; + assign m_axi_awsize = master_mode? IF.AWSIZE : {3{1'b0}}; + assign m_axi_awburst = master_mode? IF.AWBURST : {2{1'b0}}; + assign m_axi_awlock = master_mode? IF.AWLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}}; + assign m_axi_awcache = master_mode? IF.AWCACHE : {4{1'b0}}; + assign m_axi_awprot = master_mode? IF.AWPROT : {3{1'b0}}; + assign m_axi_awregion = master_mode? IF.AWREGION : {4{1'b0}}; + assign m_axi_awqos = master_mode? IF.AWQOS : {4{1'b0}}; + assign m_axi_awuser = master_mode? IF.AWUSER : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'b0}}; + assign m_axi_awvalid = master_mode? IF.AWVALID :{1'b0}; + assign IF.AWREADY = master_mode? m_axi_awready :{1'bz}; + + // Master Interface Write Data Ports Internal + assign m_axi_wid = master_mode? IF.WID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}}; + assign m_axi_wdata = master_mode? IF.WDATA : {C_AXI_WDATA_WIDTH{1'b0}}; + assign m_axi_wstrb = master_mode? IF.WSTRB : {(C_AXI_WDATA_WIDTH/8){1'b0}}; + assign m_axi_wlast = master_mode? IF.WLAST : {1'b0}; + assign m_axi_wuser = master_mode? IF.WUSER : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'b0}}; + assign m_axi_wvalid = master_mode? IF.WVALID : {1'b0}; + assign IF.WREADY = master_mode? m_axi_wready : {1'bz}; + + // Master Interface Write Response Ports Internal + assign IF.BID = master_mode? m_axi_bid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}}; + assign IF.BRESP = master_mode? m_axi_bresp : {2{1'bz}}; + assign IF.BUSER = master_mode? m_axi_buser : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'bz}}; + assign IF.BVALID = master_mode? m_axi_bvalid : 1'bz; + assign m_axi_bready = master_mode? IF.BREADY : 1'b0; + + // Master Interface Read Address Port Internal + assign m_axi_arid = master_mode? IF.ARID : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}}; + assign m_axi_araddr = master_mode? IF.ARADDR : {C_AXI_ADDR_WIDTH{1'b0}}; + assign m_axi_arlen = master_mode? IF.ARLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}}; + assign m_axi_arsize = master_mode? IF.ARSIZE : {3{1'b0}}; + assign m_axi_arburst = master_mode? IF.ARBURST : {2{1'b0}}; + assign m_axi_arlock = master_mode? IF.ARLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}}; + assign m_axi_arcache = master_mode?IF.ARCACHE : {4{1'b0}}; + assign m_axi_arprot = master_mode? IF.ARPROT : {3{1'b0}}; + assign m_axi_arregion = master_mode? IF.ARREGION : {4{1'b0}}; + assign m_axi_arqos = master_mode? IF.ARQOS : {4{1'b0}}; + assign m_axi_aruser = master_mode? IF.ARUSER : {C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'b0}}; + assign m_axi_arvalid = master_mode? IF.ARVALID :{1'b0}; + assign IF.ARREADY = master_mode? m_axi_arready : {1{1'bz}}; + + // Master Interface Read Data Ports Internal + assign IF.RID = master_mode? m_axi_rid : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}}; + assign IF.RDATA = master_mode? m_axi_rdata : {C_AXI_RDATA_WIDTH{1'bz}}; + assign IF.RRESP = master_mode? m_axi_rresp : {2{1'bz}}; + assign IF.RLAST = master_mode? m_axi_rlast : {1{1'bz}}; + assign IF.RUSER = master_mode? m_axi_ruser : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'bz}}; + assign IF.RVALID = master_mode? m_axi_rvalid : {1{1'bz}}; + assign m_axi_rready = master_mode? IF.RREADY : {1{1'b0}}; + + axi_vip_if #( + .C_AXI_PROTOCOL(C_AXI_PROTOCOL), + .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH ), + .C_AXI_WDATA_WIDTH(C_AXI_WDATA_WIDTH ), + .C_AXI_RDATA_WIDTH(C_AXI_RDATA_WIDTH ), + .C_AXI_WID_WIDTH(C_AXI_WID_WIDTH ), + .C_AXI_RID_WIDTH(C_AXI_RID_WIDTH ), + .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH ), + .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH ), + .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH ), + .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH ), + .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH ), + .C_AXI_SUPPORTS_NARROW(C_AXI_SUPPORTS_NARROW), + .C_AXI_HAS_BURST(C_AXI_HAS_BURST), + .C_AXI_HAS_LOCK(C_AXI_HAS_LOCK), + .C_AXI_HAS_CACHE(C_AXI_HAS_CACHE), + .C_AXI_HAS_REGION(C_AXI_HAS_REGION), + .C_AXI_HAS_PROT(C_AXI_HAS_PROT), + .C_AXI_HAS_QOS(C_AXI_HAS_QOS), + .C_AXI_HAS_WSTRB(C_AXI_HAS_WSTRB), + .C_AXI_HAS_BRESP(C_AXI_HAS_BRESP), + .C_AXI_HAS_RRESP(C_AXI_HAS_RRESP), + .C_AXI_HAS_ARESETN(C_AXI_HAS_ARESETN) + ) IF ( + .ACLK(aclk), + .ARESET_N(aresetn), + .ACLKEN(aclken) + ); + + + //synthesis translate_off + initial begin + $display("XilinxAXIVIP: Found at Path: %m"); + end + + //set IF mode to be in the correct mode according to C_AXI_INTERFACE_MODE,Default is monitor mode + generate + initial begin + if(C_AXI_INTERFACE_MODE ==0) begin + IF.set_intf_master; + end else if(C_AXI_INTERFACE_MODE ==2) begin + IF.set_intf_slave; + end else if(C_AXI_INTERFACE_MODE ==1) begin + $display("This AXI VIP is in passthrough mode"); + end else begin + $fatal(0,"This AXI VIP's mode is out of range"); + end + end + endgenerate + + /* + Function: set_passthrough_mode + Sets AXI VIP passthrough into run time passthrough mode + */ + function void set_passthrough_mode(); + if (C_AXI_INTERFACE_MODE == 1) begin + runtime_master = 0; + runtime_slave = 0; + IF.set_intf_monitor(); + end else begin + $fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_passthrough_mode in the testbench. Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP"); + end + endfunction: set_passthrough_mode + + /* + Function: set_master_mode + Sets AXI VIP passthrough into run time master mode + */ + function void set_master_mode(); + if (C_AXI_INTERFACE_MODE == 1) begin + runtime_master = 1; + runtime_slave = 0; + IF.set_intf_master(); + end else begin + $fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_master_mode in the testbench .Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP "); + end + endfunction : set_master_mode + + /* + Function: set_slave_mode + Sets AXI VIP passthrough into run time slave mode + */ + function void set_slave_mode(); + if (C_AXI_INTERFACE_MODE == 1) begin + runtime_master = 0; + runtime_slave = 1; + IF.set_intf_slave(); + end else begin + $fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_slave_mode in the testbench.Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP"); + end + endfunction : set_slave_mode + + /* + Function: set_xilinx_slave_ready_check + Sets xilinx_slave_ready_check_enable of IF to be 1 + */ + function void set_xilinx_slave_ready_check(); + IF.xilinx_slave_ready_check_enable = 1; + endfunction + + /* + Function: clr_xilinx_slave_ready_check + Sets xilinx_slave_ready_check_enable of IF to be 0 + */ + function void clr_xilinx_slave_ready_check(); + IF.xilinx_slave_ready_check_enable = 0; + endfunction + + /* + Function: set_max_aw_wait_cycles (not available in VIVADO Simulator) + Sets max_aw_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_aw_wait_cycles(input integer unsigned new_num); + IF.PC.max_aw_wait_cycles = new_num; + endfunction : set_max_aw_wait_cycles + + /* + Function: set_max_ar_wait_cycles (not available in VIVADO Simulator) + Sets max_ar_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_ar_wait_cycles(input integer unsigned new_num); + IF.PC.max_ar_wait_cycles = new_num; + endfunction : set_max_ar_wait_cycles + + /* + Function: set_max_r_wait_cycles (not available in VIVADO Simulator) + Sets max_r_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_r_wait_cycles(input integer unsigned new_num); + IF.PC.max_r_wait_cycles = new_num; + endfunction : set_max_r_wait_cycles + + /* + Function: set_max_b_wait_cycles (not available in VIVADO Simulator) + Sets max_b_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_b_wait_cycles(input integer unsigned new_num); + IF.PC.max_b_wait_cycles = new_num; + endfunction : set_max_b_wait_cycles + + /* + Function: set_max_w_wait_cycles (not available in VIVADO Simulator) + Sets max_w_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_w_wait_cycles(input integer unsigned new_num); + IF.PC.max_w_wait_cycles = new_num; + endfunction : set_max_w_wait_cycles + + /* + Function: set_max_wlast_wait_cycles (not available in VIVADO Simulator) + Sets max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_wlast_wait_cycles(input integer unsigned new_num); + IF.PC.max_wlast_to_awvalid_wait_cycles = new_num; + endfunction : set_max_wlast_wait_cycles + + /* + Function: set_max_rtransfer_wait_cycles (not available in VIVADO Simulator) + Sets max_rtransfer_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_rtransfers_wait_cycles(input integer unsigned new_num); + IF.PC.max_rtransfers_wait_cycles = new_num; + endfunction : set_max_rtransfers_wait_cycles + + /* + Function: set_max_wtransfer_wait_cycles (not available in VIVADO Simulator) + Sets max_wtransfer_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_wtransfers_wait_cycles(input integer unsigned new_num); + IF.PC.max_wtransfers_wait_cycles = new_num; + endfunction : set_max_wtransfers_wait_cycles + + /* + Function: set_max_wlcmd_wait_cycles (not available in VIVADO Simulator) + Sets max_wlcmd_wait_cycles of PC(ARM Protocol Checker) + */ + function void set_max_wlcmd_wait_cycles(input integer unsigned new_num); + IF.PC.max_wlcmd_wait_cycles = new_num; + endfunction : set_max_wlcmd_wait_cycles + + /* + Function: get_max_aw_wait_cycles (not available in VIVADO Simulator) + Returns max_aw_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_aw_wait_cycles(); + return(IF.PC.max_aw_wait_cycles); + endfunction : get_max_aw_wait_cycles + + /* + Function: get_max_ar_wait_cycles (not available in VIVADO Simulator) + Returns max_ar_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_ar_wait_cycles(); + return(IF.PC.max_ar_wait_cycles); + endfunction : get_max_ar_wait_cycles + + /* + Function: get_max_r_wait_cycles (not available in VIVADO Simulator) + Returns max_r_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_r_wait_cycles(); + return(IF.PC.max_r_wait_cycles); + endfunction : get_max_r_wait_cycles + + /* + Function: get_max_b_wait_cycles (not available in VIVADO Simulator) + Returns max_b_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_b_wait_cycles(); + return(IF.PC.max_b_wait_cycles); + endfunction : get_max_b_wait_cycles + + /* + Function: get_max_w_wait_cycles (not available in VIVADO Simulator) + Returns max_w_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_w_wait_cycles(); + return(IF.PC.max_w_wait_cycles); + endfunction :get_max_w_wait_cycles + + /* + Function: get_max_wlast_wait_cycles (not available in VIVADO Simulator) + Returns max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_wlast_wait_cycles(); + return(IF.PC.max_wlast_to_awvalid_wait_cycles); + endfunction :get_max_wlast_wait_cycles + + /* + Function: get_max_rtransfer_wait_cycles (not available in VIVADO Simulator) + Returns max_rtransfer_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_rtransfers_wait_cycles(); + return(IF.PC.max_rtransfers_wait_cycles); + endfunction :get_max_rtransfers_wait_cycles + + /* + Function: get_max_wtransfer_wait_cycles (not available in VIVADO Simulator) + Returns max_wtransfer_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_wtransfers_wait_cycles(); + return(IF.PC.max_wtransfers_wait_cycles); + endfunction :get_max_wtransfers_wait_cycles + + /* + Function: get_max_wlcmd_wait_cycles (not available in VIVADO Simulator) + Returns max_wlcmd_wait_cycles of PC(ARM Protocol Checker) + */ + function integer unsigned get_max_wlcmd_wait_cycles(); + return(IF.PC.max_wlcmd_wait_cycles); + endfunction :get_max_wlcmd_wait_cycles + + /* + Function: set_fatal_to_warnings (not available in VIVADO Simulator) + Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 1 + */ + function void set_fatal_to_warnings(); + IF.PC.fatal_to_warnings = 1; + endfunction : set_fatal_to_warnings + + /* + Function: clr_fatal_to_warnings (not available in VIVADO Simulator) + Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 0 + */ + function void clr_fatal_to_warnings(); + IF.PC.fatal_to_warnings = 0; + endfunction : clr_fatal_to_warnings + //synthesis translate_on + +endmodule // axi_vip_v1_1_14_top + + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_vip_v1_1_vlsyn_rfs.sv b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_vip_v1_1_vlsyn_rfs.sv new file mode 100644 index 0000000..3aebc6b --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/hdl/axi_vip_v1_1_vlsyn_rfs.sv @@ -0,0 +1,257 @@ +// (c) Copyright 2016 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// AXI VIP wrapper +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// axi_vip +// +//-------------------------------------------------------------------------- + +`timescale 1ps/1ps + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_vip_v1_1_14_top # + ( + parameter C_AXI_PROTOCOL = 0, + parameter C_AXI_INTERFACE_MODE = 1, //master, slave and bypass + parameter integer C_AXI_ADDR_WIDTH = 32, + parameter integer C_AXI_WDATA_WIDTH = 32, + parameter integer C_AXI_RDATA_WIDTH = 32, + parameter integer C_AXI_WID_WIDTH = 0, + parameter integer C_AXI_RID_WIDTH = 0, + parameter integer C_AXI_AWUSER_WIDTH = 0, + parameter integer C_AXI_ARUSER_WIDTH = 0, + parameter integer C_AXI_WUSER_WIDTH = 0, + parameter integer C_AXI_RUSER_WIDTH = 0, + parameter integer C_AXI_BUSER_WIDTH = 0, + parameter integer C_AXI_SUPPORTS_NARROW = 1, + parameter integer C_AXI_HAS_BURST = 1, + parameter integer C_AXI_HAS_LOCK = 1, + parameter integer C_AXI_HAS_CACHE = 1, + parameter integer C_AXI_HAS_REGION = 1, + parameter integer C_AXI_HAS_PROT = 1, + parameter integer C_AXI_HAS_QOS = 1, + parameter integer C_AXI_HAS_WSTRB = 1, + parameter integer C_AXI_HAS_BRESP = 1, + parameter integer C_AXI_HAS_RRESP = 1, + parameter integer C_AXI_HAS_ARESETN = 1 + ) + ( + //NOTE: C_AXI_INTERFACE_MODE =0 means MASTER MODE, 1 means PASS-THROUGH MODE and 2 means SLAVE MODE + //Please refer xgui tcl and coreinfo.yml + + // System Signals + input wire aclk, + input wire aclken, + input wire aresetn, + + // Slave Interface Write Address Ports + input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_awid, + input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, + input wire [3-1:0] s_axi_awsize, + input wire [2-1:0] s_axi_awburst, + input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, + input wire [4-1:0] s_axi_awcache, + input wire [3-1:0] s_axi_awprot, + input wire [4-1:0] s_axi_awregion, + input wire [4-1:0] s_axi_awqos, + input wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, + input wire s_axi_awvalid, + output wire s_axi_awready, + + // Slave Interface Write Data Ports + input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_wid, + input wire [C_AXI_WDATA_WIDTH-1:0] s_axi_wdata, + input wire [C_AXI_WDATA_WIDTH/8-1:0] s_axi_wstrb, + input wire s_axi_wlast, + input wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, + input wire s_axi_wvalid, + output wire s_axi_wready, + + // Slave Interface Write Response Ports + output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_bid, + output wire [2-1:0] s_axi_bresp, + output wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] s_axi_buser, + output wire s_axi_bvalid, + input wire s_axi_bready, + + // Slave Interface Read Address Ports + input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_arid, + input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, + input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, + input wire [3-1:0] s_axi_arsize, + input wire [2-1:0] s_axi_arburst, + input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, + input wire [4-1:0] s_axi_arcache, + input wire [3-1:0] s_axi_arprot, + input wire [4-1:0] s_axi_arregion, + input wire [4-1:0] s_axi_arqos, + input wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, + input wire s_axi_arvalid, + output wire s_axi_arready, + + // Slave Interface Read Data Ports + output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_rid, + output wire [C_AXI_RDATA_WIDTH-1:0] s_axi_rdata, + output wire [2-1:0] s_axi_rresp, + output wire s_axi_rlast, + output wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, + output wire s_axi_rvalid, + input wire s_axi_rready, + + // Master Interface Write Address Port + output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_awid, + output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, + output wire [3-1:0] m_axi_awsize, + output wire [2-1:0] m_axi_awburst, + output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, + output wire [4-1:0] m_axi_awcache, + output wire [3-1:0] m_axi_awprot, + output wire [4-1:0] m_axi_awregion, + output wire [4-1:0] m_axi_awqos, + output wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, + output wire m_axi_awvalid, + input wire m_axi_awready, + + // Master Interface Write Data Ports + output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_wid, + output wire [C_AXI_WDATA_WIDTH-1:0] m_axi_wdata, + output wire [C_AXI_WDATA_WIDTH/8-1:0] m_axi_wstrb, + output wire m_axi_wlast, + output wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, + output wire m_axi_wvalid, + input wire m_axi_wready, + + // Master Interface Write Response Ports + input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_bid, + input wire [2-1:0] m_axi_bresp, + input wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] m_axi_buser, + input wire m_axi_bvalid, + output wire m_axi_bready, + + // Master Interface Read Address Port + output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_arid, + output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, + output wire [3-1:0] m_axi_arsize, + output wire [2-1:0] m_axi_arburst, + output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, + output wire [4-1:0] m_axi_arcache, + output wire [3-1:0] m_axi_arprot, + output wire [4-1:0] m_axi_arregion, + output wire [4-1:0] m_axi_arqos, + output wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, + output wire m_axi_arvalid, + input wire m_axi_arready, + + // Master Interface Read Data Ports + input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_rid, + input wire [C_AXI_RDATA_WIDTH-1:0] m_axi_rdata, + input wire [2-1:0] m_axi_rresp, + input wire m_axi_rlast, + input wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, + input wire m_axi_rvalid, + output wire m_axi_rready + ); + + assign s_axi_awready = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :m_axi_awready ; + assign s_axi_wready = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :m_axi_wready; + assign s_axi_bid = (C_AXI_INTERFACE_MODE != 1) ?{C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH {1'b0}}:m_axi_bid; + assign s_axi_bresp = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :m_axi_bresp; + assign s_axi_buser = (C_AXI_INTERFACE_MODE != 1) ?{C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH {1'b0}} :m_axi_buser; + assign s_axi_bvalid = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :m_axi_bvalid; + assign s_axi_arready = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :m_axi_arready; + assign s_axi_rid = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH {1'b0}}:m_axi_rid; + assign s_axi_rdata = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_RDATA_WIDTH==0?1:C_AXI_RDATA_WIDTH {1'b0}} :m_axi_rdata; + assign s_axi_rresp = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :m_axi_rresp; + assign s_axi_rlast = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :m_axi_rlast ; + assign s_axi_ruser = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH {1'b0}} :m_axi_ruser; + assign s_axi_rvalid = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :m_axi_rvalid ; + + assign m_axi_awid = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH {1'b0}} :s_axi_awid; + assign m_axi_awaddr = (C_AXI_INTERFACE_MODE != 1) ?{C_AXI_ADDR_WIDTH==0?1:C_AXI_ADDR_WIDTH {1'b0}} :s_axi_awaddr ; + assign m_axi_awlen = (C_AXI_INTERFACE_MODE != 1) ? {((C_AXI_PROTOCOL == 1) ? 4 : 8) {1'b0}} :s_axi_awlen; + assign m_axi_awsize = (C_AXI_INTERFACE_MODE != 1) ? 3'b0 :s_axi_awsize; + assign m_axi_awburst = (C_AXI_INTERFACE_MODE != 1) ? 2'b0 :s_axi_awburst; + assign m_axi_awlock = (C_AXI_INTERFACE_MODE != 1) ? {((C_AXI_PROTOCOL == 1) ? 2 : 1) {1'b0}} :s_axi_awlock; + assign m_axi_awcache = (C_AXI_INTERFACE_MODE != 1) ? 4'b0 :s_axi_awcache; + assign m_axi_awprot = (C_AXI_INTERFACE_MODE != 1) ? 3'b0 :s_axi_awprot; + assign m_axi_awregion = (C_AXI_INTERFACE_MODE != 1) ? 4'b0 :s_axi_awregion; + assign m_axi_awqos = (C_AXI_INTERFACE_MODE != 1) ? 4'b0 :s_axi_awqos ; + assign m_axi_awuser = (C_AXI_INTERFACE_MODE != 1) ?{C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH {1'b0}} :s_axi_awuser; + assign m_axi_awvalid = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :s_axi_awvalid; + assign m_axi_wid = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH {1'b0}} :s_axi_wid ; + assign m_axi_wdata = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_WDATA_WIDTH==0?1:C_AXI_WDATA_WIDTH {1'b0}} :s_axi_wdata; + assign m_axi_wstrb = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_WDATA_WIDTH==0?1:C_AXI_WDATA_WIDTH/8 {1'b0}} :s_axi_wstrb; + assign m_axi_wlast = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :s_axi_wlast; + assign m_axi_wuser = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH {1'b0}} :s_axi_wuser; + assign m_axi_wvalid = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :s_axi_wvalid; + assign m_axi_bready = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :s_axi_bready ; + assign m_axi_arid = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH {1'b0}} :s_axi_arid; + assign m_axi_araddr = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_ADDR_WIDTH==0?1:C_AXI_ADDR_WIDTH {1'b0}} :s_axi_araddr; + assign m_axi_arlen = (C_AXI_INTERFACE_MODE != 1) ? {((C_AXI_PROTOCOL == 1) ? 4 : 8) {1'b0}} :s_axi_arlen; + assign m_axi_arsize = (C_AXI_INTERFACE_MODE != 1) ? 3'b0 :s_axi_arsize; + assign m_axi_arburst = (C_AXI_INTERFACE_MODE != 1) ? 2'b0 :s_axi_arburst; + assign m_axi_arlock = (C_AXI_INTERFACE_MODE != 1) ? {((C_AXI_PROTOCOL == 1) ? 1 : 1) {1'b0}} :s_axi_arlock; + assign m_axi_arcache = (C_AXI_INTERFACE_MODE != 1) ? 4'b0 :s_axi_arcache; + assign m_axi_arprot = (C_AXI_INTERFACE_MODE != 1) ? 3'b0 :s_axi_arprot; + assign m_axi_arregion = (C_AXI_INTERFACE_MODE != 1) ? 4'b0 :s_axi_arregion; + assign m_axi_arqos = (C_AXI_INTERFACE_MODE != 1) ? 4'b0 :s_axi_arqos; + assign m_axi_aruser = (C_AXI_INTERFACE_MODE != 1) ? {C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH {1'b0}} : s_axi_aruser; + assign m_axi_arvalid = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :s_axi_arvalid ; + assign m_axi_rready = (C_AXI_INTERFACE_MODE != 1) ? 1'b0 :s_axi_rready; + + +endmodule // axi_vip_v1_1_14_top + + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0.cpp b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0.cpp new file mode 100644 index 0000000..411b875 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0.cpp @@ -0,0 +1,582 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#include "axi_mst_0_sc.h" + +#include "axi_mst_0.h" + +#include "axi_vip.h" + +#include +#include + + + + + +#ifdef XILINX_SIMULATOR +axi_mst_0::axi_mst_0(const sc_core::sc_module_name& nm) : axi_mst_0_sc(nm), aclk("aclk"), aresetn("aresetn"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready") +{ + + // initialize pins + mp_impl->aclk(aclk); + mp_impl->aresetn(aresetn); + + // initialize transactors + mp_M_AXI_transactor = NULL; + + // initialize socket stubs + +} + +void axi_mst_0::before_end_of_elaboration() +{ + // configure 'M_AXI' transactor + + if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("axi_mst_0", "M_AXI_TLM_MODE") != 1) + { + // Instantiate Socket Stubs + + // 'M_AXI' transactor parameters + xsc::common_cpp::properties M_AXI_transactor_param_props; + M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("FREQ_HZ", "100000000"); + M_AXI_transactor_param_props.addLong("ID_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("HAS_BURST", "0"); + M_AXI_transactor_param_props.addLong("HAS_LOCK", "0"); + M_AXI_transactor_param_props.addLong("HAS_PROT", "1"); + M_AXI_transactor_param_props.addLong("HAS_CACHE", "0"); + M_AXI_transactor_param_props.addLong("HAS_QOS", "0"); + M_AXI_transactor_param_props.addLong("HAS_REGION", "0"); + M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1"); + M_AXI_transactor_param_props.addLong("HAS_BRESP", "1"); + M_AXI_transactor_param_props.addLong("HAS_RRESP", "1"); + M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); + M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1"); + M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); + M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("HAS_SIZE", "0"); + M_AXI_transactor_param_props.addLong("HAS_RESET", "1"); + M_AXI_transactor_param_props.addFloat("PHASE", "0.0"); + M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE"); + M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE"); + M_AXI_transactor_param_props.addString("CLK_DOMAIN", ""); + + mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props); + + // M_AXI' transactor ports + + mp_M_AXI_transactor->ARADDR(m_axi_araddr); + mp_M_AXI_transactor->ARPROT(m_axi_arprot); + mp_M_AXI_transactor->ARREADY(m_axi_arready); + mp_M_AXI_transactor->ARVALID(m_axi_arvalid); + mp_M_AXI_transactor->AWADDR(m_axi_awaddr); + mp_M_AXI_transactor->AWPROT(m_axi_awprot); + mp_M_AXI_transactor->AWREADY(m_axi_awready); + mp_M_AXI_transactor->AWVALID(m_axi_awvalid); + mp_M_AXI_transactor->BREADY(m_axi_bready); + mp_M_AXI_transactor->BRESP(m_axi_bresp); + mp_M_AXI_transactor->BVALID(m_axi_bvalid); + mp_M_AXI_transactor->RDATA(m_axi_rdata); + mp_M_AXI_transactor->RREADY(m_axi_rready); + mp_M_AXI_transactor->RRESP(m_axi_rresp); + mp_M_AXI_transactor->RVALID(m_axi_rvalid); + mp_M_AXI_transactor->WDATA(m_axi_wdata); + mp_M_AXI_transactor->WREADY(m_axi_wready); + mp_M_AXI_transactor->WSTRB(m_axi_wstrb); + mp_M_AXI_transactor->WVALID(m_axi_wvalid); + mp_M_AXI_transactor->CLK(aclk); + mp_M_AXI_transactor->RST(aresetn); + + // M_AXI' transactor sockets + + mp_impl->M_INITIATOR_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket)); + mp_impl->M_INITIATOR_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket)); + } + else + { + } + +} + +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +axi_mst_0::axi_mst_0(const sc_core::sc_module_name& nm) : axi_mst_0_sc(nm), aclk("aclk"), aresetn("aresetn"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready") +{ + + // initialize pins + mp_impl->aclk(aclk); + mp_impl->aresetn(aresetn); + + // initialize transactors + mp_M_AXI_transactor = NULL; + + // initialize socket stubs + +} + +void axi_mst_0::before_end_of_elaboration() +{ + // configure 'M_AXI' transactor + + if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("axi_mst_0", "M_AXI_TLM_MODE") != 1) + { + // Instantiate Socket Stubs + + // 'M_AXI' transactor parameters + xsc::common_cpp::properties M_AXI_transactor_param_props; + M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("FREQ_HZ", "100000000"); + M_AXI_transactor_param_props.addLong("ID_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("HAS_BURST", "0"); + M_AXI_transactor_param_props.addLong("HAS_LOCK", "0"); + M_AXI_transactor_param_props.addLong("HAS_PROT", "1"); + M_AXI_transactor_param_props.addLong("HAS_CACHE", "0"); + M_AXI_transactor_param_props.addLong("HAS_QOS", "0"); + M_AXI_transactor_param_props.addLong("HAS_REGION", "0"); + M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1"); + M_AXI_transactor_param_props.addLong("HAS_BRESP", "1"); + M_AXI_transactor_param_props.addLong("HAS_RRESP", "1"); + M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); + M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1"); + M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); + M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("HAS_SIZE", "0"); + M_AXI_transactor_param_props.addLong("HAS_RESET", "1"); + M_AXI_transactor_param_props.addFloat("PHASE", "0.0"); + M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE"); + M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE"); + M_AXI_transactor_param_props.addString("CLK_DOMAIN", ""); + + mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props); + + // M_AXI' transactor ports + + mp_M_AXI_transactor->ARADDR(m_axi_araddr); + mp_M_AXI_transactor->ARPROT(m_axi_arprot); + mp_M_AXI_transactor->ARREADY(m_axi_arready); + mp_M_AXI_transactor->ARVALID(m_axi_arvalid); + mp_M_AXI_transactor->AWADDR(m_axi_awaddr); + mp_M_AXI_transactor->AWPROT(m_axi_awprot); + mp_M_AXI_transactor->AWREADY(m_axi_awready); + mp_M_AXI_transactor->AWVALID(m_axi_awvalid); + mp_M_AXI_transactor->BREADY(m_axi_bready); + mp_M_AXI_transactor->BRESP(m_axi_bresp); + mp_M_AXI_transactor->BVALID(m_axi_bvalid); + mp_M_AXI_transactor->RDATA(m_axi_rdata); + mp_M_AXI_transactor->RREADY(m_axi_rready); + mp_M_AXI_transactor->RRESP(m_axi_rresp); + mp_M_AXI_transactor->RVALID(m_axi_rvalid); + mp_M_AXI_transactor->WDATA(m_axi_wdata); + mp_M_AXI_transactor->WREADY(m_axi_wready); + mp_M_AXI_transactor->WSTRB(m_axi_wstrb); + mp_M_AXI_transactor->WVALID(m_axi_wvalid); + mp_M_AXI_transactor->CLK(aclk); + mp_M_AXI_transactor->RST(aresetn); + + // M_AXI' transactor sockets + + mp_impl->M_INITIATOR_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket)); + mp_impl->M_INITIATOR_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket)); + } + else + { + } + +} + +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +axi_mst_0::axi_mst_0(const sc_core::sc_module_name& nm) : axi_mst_0_sc(nm), aclk("aclk"), aresetn("aresetn"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready") +{ + + // initialize pins + mp_impl->aclk(aclk); + mp_impl->aresetn(aresetn); + + // initialize transactors + mp_M_AXI_transactor = NULL; + + // initialize socket stubs + +} + +void axi_mst_0::before_end_of_elaboration() +{ + // configure 'M_AXI' transactor + + if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("axi_mst_0", "M_AXI_TLM_MODE") != 1) + { + // Instantiate Socket Stubs + + // 'M_AXI' transactor parameters + xsc::common_cpp::properties M_AXI_transactor_param_props; + M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("FREQ_HZ", "100000000"); + M_AXI_transactor_param_props.addLong("ID_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("HAS_BURST", "0"); + M_AXI_transactor_param_props.addLong("HAS_LOCK", "0"); + M_AXI_transactor_param_props.addLong("HAS_PROT", "1"); + M_AXI_transactor_param_props.addLong("HAS_CACHE", "0"); + M_AXI_transactor_param_props.addLong("HAS_QOS", "0"); + M_AXI_transactor_param_props.addLong("HAS_REGION", "0"); + M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1"); + M_AXI_transactor_param_props.addLong("HAS_BRESP", "1"); + M_AXI_transactor_param_props.addLong("HAS_RRESP", "1"); + M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); + M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1"); + M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); + M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("HAS_SIZE", "0"); + M_AXI_transactor_param_props.addLong("HAS_RESET", "1"); + M_AXI_transactor_param_props.addFloat("PHASE", "0.0"); + M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE"); + M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE"); + M_AXI_transactor_param_props.addString("CLK_DOMAIN", ""); + + mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props); + + // M_AXI' transactor ports + + mp_M_AXI_transactor->ARADDR(m_axi_araddr); + mp_M_AXI_transactor->ARPROT(m_axi_arprot); + mp_M_AXI_transactor->ARREADY(m_axi_arready); + mp_M_AXI_transactor->ARVALID(m_axi_arvalid); + mp_M_AXI_transactor->AWADDR(m_axi_awaddr); + mp_M_AXI_transactor->AWPROT(m_axi_awprot); + mp_M_AXI_transactor->AWREADY(m_axi_awready); + mp_M_AXI_transactor->AWVALID(m_axi_awvalid); + mp_M_AXI_transactor->BREADY(m_axi_bready); + mp_M_AXI_transactor->BRESP(m_axi_bresp); + mp_M_AXI_transactor->BVALID(m_axi_bvalid); + mp_M_AXI_transactor->RDATA(m_axi_rdata); + mp_M_AXI_transactor->RREADY(m_axi_rready); + mp_M_AXI_transactor->RRESP(m_axi_rresp); + mp_M_AXI_transactor->RVALID(m_axi_rvalid); + mp_M_AXI_transactor->WDATA(m_axi_wdata); + mp_M_AXI_transactor->WREADY(m_axi_wready); + mp_M_AXI_transactor->WSTRB(m_axi_wstrb); + mp_M_AXI_transactor->WVALID(m_axi_wvalid); + mp_M_AXI_transactor->CLK(aclk); + mp_M_AXI_transactor->RST(aresetn); + + // M_AXI' transactor sockets + + mp_impl->M_INITIATOR_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket)); + mp_impl->M_INITIATOR_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket)); + } + else + { + } + +} + +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +axi_mst_0::axi_mst_0(const sc_core::sc_module_name& nm) : axi_mst_0_sc(nm), aclk("aclk"), aresetn("aresetn"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready") +{ + // initialize pins + mp_impl->aclk(aclk); + mp_impl->aresetn(aresetn); + + // initialize transactors + mp_M_AXI_transactor = NULL; + + // Instantiate Socket Stubs + + // configure M_AXI_transactor + xsc::common_cpp::properties M_AXI_transactor_param_props; + M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("FREQ_HZ", "100000000"); + M_AXI_transactor_param_props.addLong("ID_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("HAS_BURST", "0"); + M_AXI_transactor_param_props.addLong("HAS_LOCK", "0"); + M_AXI_transactor_param_props.addLong("HAS_PROT", "1"); + M_AXI_transactor_param_props.addLong("HAS_CACHE", "0"); + M_AXI_transactor_param_props.addLong("HAS_QOS", "0"); + M_AXI_transactor_param_props.addLong("HAS_REGION", "0"); + M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1"); + M_AXI_transactor_param_props.addLong("HAS_BRESP", "1"); + M_AXI_transactor_param_props.addLong("HAS_RRESP", "1"); + M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); + M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1"); + M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); + M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("HAS_SIZE", "0"); + M_AXI_transactor_param_props.addLong("HAS_RESET", "1"); + M_AXI_transactor_param_props.addFloat("PHASE", "0.0"); + M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE"); + M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE"); + M_AXI_transactor_param_props.addString("CLK_DOMAIN", ""); + + mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props); + mp_M_AXI_transactor->ARADDR(m_axi_araddr); + mp_M_AXI_transactor->ARPROT(m_axi_arprot); + mp_M_AXI_transactor->ARREADY(m_axi_arready); + mp_M_AXI_transactor->ARVALID(m_axi_arvalid); + mp_M_AXI_transactor->AWADDR(m_axi_awaddr); + mp_M_AXI_transactor->AWPROT(m_axi_awprot); + mp_M_AXI_transactor->AWREADY(m_axi_awready); + mp_M_AXI_transactor->AWVALID(m_axi_awvalid); + mp_M_AXI_transactor->BREADY(m_axi_bready); + mp_M_AXI_transactor->BRESP(m_axi_bresp); + mp_M_AXI_transactor->BVALID(m_axi_bvalid); + mp_M_AXI_transactor->RDATA(m_axi_rdata); + mp_M_AXI_transactor->RREADY(m_axi_rready); + mp_M_AXI_transactor->RRESP(m_axi_rresp); + mp_M_AXI_transactor->RVALID(m_axi_rvalid); + mp_M_AXI_transactor->WDATA(m_axi_wdata); + mp_M_AXI_transactor->WREADY(m_axi_wready); + mp_M_AXI_transactor->WSTRB(m_axi_wstrb); + mp_M_AXI_transactor->WVALID(m_axi_wvalid); + mp_M_AXI_transactor->CLK(aclk); + mp_M_AXI_transactor->RST(aresetn); + + // initialize transactors stubs + M_AXI_transactor_initiator_wr_socket_stub = nullptr; + M_AXI_transactor_initiator_rd_socket_stub = nullptr; + +} + +void axi_mst_0::before_end_of_elaboration() +{ + // configure 'M_AXI' transactor + if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("axi_mst_0", "M_AXI_TLM_MODE") != 1) + { + mp_impl->M_INITIATOR_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket)); + mp_impl->M_INITIATOR_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket)); + + } + else + { + M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0); + M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket)); + M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0); + M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket)); + mp_M_AXI_transactor->disable_transactor(); + } + +} + +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +axi_mst_0::axi_mst_0(const sc_core::sc_module_name& nm) : axi_mst_0_sc(nm), aclk("aclk"), aresetn("aresetn"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready") +{ + // initialize pins + mp_impl->aclk(aclk); + mp_impl->aresetn(aresetn); + + // initialize transactors + mp_M_AXI_transactor = NULL; + + // Instantiate Socket Stubs + + // configure M_AXI_transactor + xsc::common_cpp::properties M_AXI_transactor_param_props; + M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("FREQ_HZ", "100000000"); + M_AXI_transactor_param_props.addLong("ID_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32"); + M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0"); + M_AXI_transactor_param_props.addLong("HAS_BURST", "0"); + M_AXI_transactor_param_props.addLong("HAS_LOCK", "0"); + M_AXI_transactor_param_props.addLong("HAS_PROT", "1"); + M_AXI_transactor_param_props.addLong("HAS_CACHE", "0"); + M_AXI_transactor_param_props.addLong("HAS_QOS", "0"); + M_AXI_transactor_param_props.addLong("HAS_REGION", "0"); + M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1"); + M_AXI_transactor_param_props.addLong("HAS_BRESP", "1"); + M_AXI_transactor_param_props.addLong("HAS_RRESP", "1"); + M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); + M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1"); + M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); + M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); + M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0"); + M_AXI_transactor_param_props.addLong("HAS_SIZE", "0"); + M_AXI_transactor_param_props.addLong("HAS_RESET", "1"); + M_AXI_transactor_param_props.addFloat("PHASE", "0.0"); + M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE"); + M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE"); + M_AXI_transactor_param_props.addString("CLK_DOMAIN", ""); + + mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props); + mp_M_AXI_transactor->ARADDR(m_axi_araddr); + mp_M_AXI_transactor->ARPROT(m_axi_arprot); + mp_M_AXI_transactor->ARREADY(m_axi_arready); + mp_M_AXI_transactor->ARVALID(m_axi_arvalid); + mp_M_AXI_transactor->AWADDR(m_axi_awaddr); + mp_M_AXI_transactor->AWPROT(m_axi_awprot); + mp_M_AXI_transactor->AWREADY(m_axi_awready); + mp_M_AXI_transactor->AWVALID(m_axi_awvalid); + mp_M_AXI_transactor->BREADY(m_axi_bready); + mp_M_AXI_transactor->BRESP(m_axi_bresp); + mp_M_AXI_transactor->BVALID(m_axi_bvalid); + mp_M_AXI_transactor->RDATA(m_axi_rdata); + mp_M_AXI_transactor->RREADY(m_axi_rready); + mp_M_AXI_transactor->RRESP(m_axi_rresp); + mp_M_AXI_transactor->RVALID(m_axi_rvalid); + mp_M_AXI_transactor->WDATA(m_axi_wdata); + mp_M_AXI_transactor->WREADY(m_axi_wready); + mp_M_AXI_transactor->WSTRB(m_axi_wstrb); + mp_M_AXI_transactor->WVALID(m_axi_wvalid); + mp_M_AXI_transactor->CLK(aclk); + mp_M_AXI_transactor->RST(aresetn); + + // initialize transactors stubs + M_AXI_transactor_initiator_wr_socket_stub = nullptr; + M_AXI_transactor_initiator_rd_socket_stub = nullptr; + +} + +void axi_mst_0::before_end_of_elaboration() +{ + // configure 'M_AXI' transactor + if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("axi_mst_0", "M_AXI_TLM_MODE") != 1) + { + mp_impl->M_INITIATOR_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket)); + mp_impl->M_INITIATOR_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket)); + + } + else + { + M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0); + M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket)); + M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0); + M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket)); + mp_M_AXI_transactor->disable_transactor(); + } + +} + +#endif // MTI_SYSTEMC + + + + +axi_mst_0::~axi_mst_0() +{ + delete mp_M_AXI_transactor; + +} + +#ifdef MTI_SYSTEMC +SC_MODULE_EXPORT(axi_mst_0); +#endif + +#ifdef XM_SYSTEMC +XMSC_MODULE_EXPORT(axi_mst_0); +#endif + +#ifdef RIVIERA +SC_MODULE_EXPORT(axi_mst_0); +#endif + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0.h b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0.h new file mode 100644 index 0000000..f3001bf --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0.h @@ -0,0 +1,330 @@ +#ifndef IP_AXI_MST_0_H_ +#define IP_AXI_MST_0_H_ + +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +#include "axi_mst_0_sc.h" + + + + +#ifdef XILINX_SIMULATOR +class DllExport axi_mst_0 : public axi_mst_0_sc +{ +public: + + axi_mst_0(const sc_core::sc_module_name& nm); + virtual ~axi_mst_0(); + + // module pin-to-pin RTL interface + + sc_core::sc_in< bool > aclk; + sc_core::sc_in< bool > aresetn; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot; + sc_core::sc_out< bool > m_axi_awvalid; + sc_core::sc_in< bool > m_axi_awready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata; + sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb; + sc_core::sc_out< bool > m_axi_wvalid; + sc_core::sc_in< bool > m_axi_wready; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp; + sc_core::sc_in< bool > m_axi_bvalid; + sc_core::sc_out< bool > m_axi_bready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot; + sc_core::sc_out< bool > m_axi_arvalid; + sc_core::sc_in< bool > m_axi_arready; + sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp; + sc_core::sc_in< bool > m_axi_rvalid; + sc_core::sc_out< bool > m_axi_rready; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor; + +}; +#endif // XILINX_SIMULATOR + + + + +#ifdef XM_SYSTEMC +class DllExport axi_mst_0 : public axi_mst_0_sc +{ +public: + + axi_mst_0(const sc_core::sc_module_name& nm); + virtual ~axi_mst_0(); + + // module pin-to-pin RTL interface + + sc_core::sc_in< bool > aclk; + sc_core::sc_in< bool > aresetn; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot; + sc_core::sc_out< bool > m_axi_awvalid; + sc_core::sc_in< bool > m_axi_awready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata; + sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb; + sc_core::sc_out< bool > m_axi_wvalid; + sc_core::sc_in< bool > m_axi_wready; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp; + sc_core::sc_in< bool > m_axi_bvalid; + sc_core::sc_out< bool > m_axi_bready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot; + sc_core::sc_out< bool > m_axi_arvalid; + sc_core::sc_in< bool > m_axi_arready; + sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp; + sc_core::sc_in< bool > m_axi_rvalid; + sc_core::sc_out< bool > m_axi_rready; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor; + +}; +#endif // XM_SYSTEMC + + + + +#ifdef RIVIERA +class DllExport axi_mst_0 : public axi_mst_0_sc +{ +public: + + axi_mst_0(const sc_core::sc_module_name& nm); + virtual ~axi_mst_0(); + + // module pin-to-pin RTL interface + + sc_core::sc_in< bool > aclk; + sc_core::sc_in< bool > aresetn; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot; + sc_core::sc_out< bool > m_axi_awvalid; + sc_core::sc_in< bool > m_axi_awready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata; + sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb; + sc_core::sc_out< bool > m_axi_wvalid; + sc_core::sc_in< bool > m_axi_wready; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp; + sc_core::sc_in< bool > m_axi_bvalid; + sc_core::sc_out< bool > m_axi_bready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot; + sc_core::sc_out< bool > m_axi_arvalid; + sc_core::sc_in< bool > m_axi_arready; + sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp; + sc_core::sc_in< bool > m_axi_rvalid; + sc_core::sc_out< bool > m_axi_rready; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor; + +}; +#endif // RIVIERA + + + + +#ifdef VCSSYSTEMC +#include "utils/xtlm_aximm_initiator_stub.h" + +class DllExport axi_mst_0 : public axi_mst_0_sc +{ +public: + + axi_mst_0(const sc_core::sc_module_name& nm); + virtual ~axi_mst_0(); + + // module pin-to-pin RTL interface + + sc_core::sc_in< bool > aclk; + sc_core::sc_in< bool > aresetn; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot; + sc_core::sc_out< bool > m_axi_awvalid; + sc_core::sc_in< bool > m_axi_awready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata; + sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb; + sc_core::sc_out< bool > m_axi_wvalid; + sc_core::sc_in< bool > m_axi_wready; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp; + sc_core::sc_in< bool > m_axi_bvalid; + sc_core::sc_out< bool > m_axi_bready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot; + sc_core::sc_out< bool > m_axi_arvalid; + sc_core::sc_in< bool > m_axi_arready; + sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp; + sc_core::sc_in< bool > m_axi_rvalid; + sc_core::sc_out< bool > m_axi_rready; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor; + + // Transactor stubs + xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub; + xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub; + + // Socket stubs + +}; +#endif // VCSSYSTEMC + + + + +#ifdef MTI_SYSTEMC +#include "utils/xtlm_aximm_initiator_stub.h" + +class DllExport axi_mst_0 : public axi_mst_0_sc +{ +public: + + axi_mst_0(const sc_core::sc_module_name& nm); + virtual ~axi_mst_0(); + + // module pin-to-pin RTL interface + + sc_core::sc_in< bool > aclk; + sc_core::sc_in< bool > aresetn; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot; + sc_core::sc_out< bool > m_axi_awvalid; + sc_core::sc_in< bool > m_axi_awready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata; + sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb; + sc_core::sc_out< bool > m_axi_wvalid; + sc_core::sc_in< bool > m_axi_wready; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp; + sc_core::sc_in< bool > m_axi_bvalid; + sc_core::sc_out< bool > m_axi_bready; + sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr; + sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot; + sc_core::sc_out< bool > m_axi_arvalid; + sc_core::sc_in< bool > m_axi_arready; + sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata; + sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp; + sc_core::sc_in< bool > m_axi_rvalid; + sc_core::sc_out< bool > m_axi_rready; + + // Dummy Signals for IP Ports + + +protected: + + virtual void before_end_of_elaboration(); + +private: + + xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor; + + // Transactor stubs + xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub; + xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub; + + // Socket stubs + +}; +#endif // MTI_SYSTEMC +#endif // IP_AXI_MST_0_H_ diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0.sv b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0.sv new file mode 100644 index 0000000..7a6cbf0 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0.sv @@ -0,0 +1,246 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 14 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module axi_mst_0 ( + aclk, + aresetn, + m_axi_awaddr, + m_axi_awprot, + m_axi_awvalid, + m_axi_awready, + m_axi_wdata, + m_axi_wstrb, + m_axi_wvalid, + m_axi_wready, + m_axi_bresp, + m_axi_bvalid, + m_axi_bready, + m_axi_araddr, + m_axi_arprot, + m_axi_arvalid, + m_axi_arready, + m_axi_rdata, + m_axi_rresp, + m_axi_rvalid, + m_axi_rready +); + +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLOCK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLOCK CLK" *) +input wire aclk; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RESET, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RESET RST" *) +input wire aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) +output wire [31 : 0] m_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) +output wire [2 : 0] m_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) +output wire m_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) +input wire m_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) +output wire [31 : 0] m_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) +output wire [3 : 0] m_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) +output wire m_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) +input wire m_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) +input wire [1 : 0] m_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) +input wire m_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) +output wire m_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) +output wire [31 : 0] m_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) +output wire [2 : 0] m_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) +output wire m_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) +input wire m_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) +input wire [31 : 0] m_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) +input wire [1 : 0] m_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) +input wire m_axi_rvalid; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_B\ +ITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) +output wire m_axi_rready; + + axi_vip_v1_1_14_top #( + .C_AXI_PROTOCOL(2), + .C_AXI_INTERFACE_MODE(0), + .C_AXI_ADDR_WIDTH(32), + .C_AXI_WDATA_WIDTH(32), + .C_AXI_RDATA_WIDTH(32), + .C_AXI_WID_WIDTH(0), + .C_AXI_RID_WIDTH(0), + .C_AXI_AWUSER_WIDTH(0), + .C_AXI_ARUSER_WIDTH(0), + .C_AXI_WUSER_WIDTH(0), + .C_AXI_RUSER_WIDTH(0), + .C_AXI_BUSER_WIDTH(0), + .C_AXI_SUPPORTS_NARROW(0), + .C_AXI_HAS_BURST(0), + .C_AXI_HAS_LOCK(0), + .C_AXI_HAS_CACHE(0), + .C_AXI_HAS_REGION(0), + .C_AXI_HAS_PROT(1), + .C_AXI_HAS_QOS(0), + .C_AXI_HAS_WSTRB(1), + .C_AXI_HAS_BRESP(1), + .C_AXI_HAS_RRESP(1), + .C_AXI_HAS_ARESETN(1) + ) inst ( + .aclk(aclk), + .aclken(1'B1), + .aresetn(aresetn), + .s_axi_awid(1'B0), + .s_axi_awaddr(32'B0), + .s_axi_awlen(8'B0), + .s_axi_awsize(3'B0), + .s_axi_awburst(2'B1), + .s_axi_awlock(1'B0), + .s_axi_awcache(4'B0), + .s_axi_awprot(3'B0), + .s_axi_awregion(4'B0), + .s_axi_awqos(4'B0), + .s_axi_awuser(1'B0), + .s_axi_awvalid(1'B0), + .s_axi_awready(), + .s_axi_wid(1'B0), + .s_axi_wdata(32'B0), + .s_axi_wstrb(4'HF), + .s_axi_wlast(1'B0), + .s_axi_wuser(1'B0), + .s_axi_wvalid(1'B0), + .s_axi_wready(), + .s_axi_bid(), + .s_axi_bresp(), + .s_axi_buser(), + .s_axi_bvalid(), + .s_axi_bready(1'B0), + .s_axi_arid(1'B0), + .s_axi_araddr(32'B0), + .s_axi_arlen(8'B0), + .s_axi_arsize(3'B0), + .s_axi_arburst(2'B1), + .s_axi_arlock(1'B0), + .s_axi_arcache(4'B0), + .s_axi_arprot(3'B0), + .s_axi_arregion(4'B0), + .s_axi_arqos(4'B0), + .s_axi_aruser(1'B0), + .s_axi_arvalid(1'B0), + .s_axi_arready(), + .s_axi_rid(), + .s_axi_rdata(), + .s_axi_rresp(), + .s_axi_rlast(), + .s_axi_ruser(), + .s_axi_rvalid(), + .s_axi_rready(1'B0), + .m_axi_awid(), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awlen(), + .m_axi_awsize(), + .m_axi_awburst(), + .m_axi_awlock(), + .m_axi_awcache(), + .m_axi_awprot(m_axi_awprot), + .m_axi_awregion(), + .m_axi_awqos(), + .m_axi_awuser(), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_awready(m_axi_awready), + .m_axi_wid(), + .m_axi_wdata(m_axi_wdata), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wlast(), + .m_axi_wuser(), + .m_axi_wvalid(m_axi_wvalid), + .m_axi_wready(m_axi_wready), + .m_axi_bid(1'B0), + .m_axi_bresp(m_axi_bresp), + .m_axi_buser(1'B0), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_bready(m_axi_bready), + .m_axi_arid(), + .m_axi_araddr(m_axi_araddr), + .m_axi_arlen(), + .m_axi_arsize(), + .m_axi_arburst(), + .m_axi_arlock(), + .m_axi_arcache(), + .m_axi_arprot(m_axi_arprot), + .m_axi_arregion(), + .m_axi_arqos(), + .m_axi_aruser(), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_arready(m_axi_arready), + .m_axi_rid(1'B0), + .m_axi_rdata(m_axi_rdata), + .m_axi_rresp(m_axi_rresp), + .m_axi_rlast(1'B0), + .m_axi_ruser(1'B0), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_rready(m_axi_rready) + ); +endmodule diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_pkg.sv b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_pkg.sv new file mode 100644 index 0000000..33345d8 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_pkg.sv @@ -0,0 +1,69 @@ +/////////////////////////////////////////////////////////////////////////// +//NOTE: This file has been automatically generated by Vivado. +/////////////////////////////////////////////////////////////////////////// +`timescale 1ps/1ps +package axi_mst_0_pkg; +import axi_vip_pkg::*; +/////////////////////////////////////////////////////////////////////////// +// These parameters are named after the component for use in your verification +// environment. +/////////////////////////////////////////////////////////////////////////// + parameter axi_mst_0_VIP_PROTOCOL = 2; + parameter axi_mst_0_VIP_READ_WRITE_MODE = "READ_WRITE"; + parameter axi_mst_0_VIP_INTERFACE_MODE = 0; + parameter axi_mst_0_VIP_ADDR_WIDTH = 32; + parameter axi_mst_0_VIP_DATA_WIDTH = 32; + parameter axi_mst_0_VIP_ID_WIDTH = 0; + parameter axi_mst_0_VIP_AWUSER_WIDTH = 0; + parameter axi_mst_0_VIP_ARUSER_WIDTH = 0; + parameter axi_mst_0_VIP_RUSER_WIDTH = 0; + parameter axi_mst_0_VIP_WUSER_WIDTH = 0; + parameter axi_mst_0_VIP_BUSER_WIDTH = 0; + parameter axi_mst_0_VIP_SUPPORTS_NARROW = 0; + parameter axi_mst_0_VIP_HAS_BURST = 0; + parameter axi_mst_0_VIP_HAS_LOCK = 0; + parameter axi_mst_0_VIP_HAS_CACHE = 0; + parameter axi_mst_0_VIP_HAS_REGION = 0; + parameter axi_mst_0_VIP_HAS_QOS = 0; + parameter axi_mst_0_VIP_HAS_PROT = 1; + parameter axi_mst_0_VIP_HAS_WSTRB = 1; + parameter axi_mst_0_VIP_HAS_BRESP = 1; + parameter axi_mst_0_VIP_HAS_RRESP = 1; + parameter axi_mst_0_VIP_HAS_ACLKEN = 0; + parameter axi_mst_0_VIP_HAS_ARESETN = 1; +/////////////////////////////////////////////////////////////////////////// +typedef axi_mst_agent #(axi_mst_0_VIP_PROTOCOL, + axi_mst_0_VIP_ADDR_WIDTH, + axi_mst_0_VIP_DATA_WIDTH, + axi_mst_0_VIP_DATA_WIDTH, + axi_mst_0_VIP_ID_WIDTH, + axi_mst_0_VIP_ID_WIDTH, + axi_mst_0_VIP_AWUSER_WIDTH, + axi_mst_0_VIP_WUSER_WIDTH, + axi_mst_0_VIP_BUSER_WIDTH, + axi_mst_0_VIP_ARUSER_WIDTH, + axi_mst_0_VIP_RUSER_WIDTH, + axi_mst_0_VIP_SUPPORTS_NARROW, + axi_mst_0_VIP_HAS_BURST, + axi_mst_0_VIP_HAS_LOCK, + axi_mst_0_VIP_HAS_CACHE, + axi_mst_0_VIP_HAS_REGION, + axi_mst_0_VIP_HAS_PROT, + axi_mst_0_VIP_HAS_QOS, + axi_mst_0_VIP_HAS_WSTRB, + axi_mst_0_VIP_HAS_BRESP, + axi_mst_0_VIP_HAS_RRESP, + axi_mst_0_VIP_HAS_ARESETN) axi_mst_0_mst_t; + +/////////////////////////////////////////////////////////////////////////// +// How to start the verification component +/////////////////////////////////////////////////////////////////////////// +// axi_mst_0_mst_t axi_mst_0_mst; +// initial begin : START_axi_mst_0_MASTER +// axi_mst_0_mst = new("axi_mst_0_mst", `axi_mst_0_PATH_TO_INTERFACE); +// axi_mst_0_mst.start_master(); +// end + + + +endpackage : axi_mst_0_pkg diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_sc.cpp b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_sc.cpp new file mode 100644 index 0000000..7c931c6 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_sc.cpp @@ -0,0 +1,102 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#include "axi_mst_0_sc.h" + +#include "axi_vip.h" + +#include +#include + +axi_mst_0_sc::axi_mst_0_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL) +{ + // configure connectivity manager + xsc::utils::xsc_sim_manager::addInstance("axi_mst_0", this); + + // initialize module + xsc::common_cpp::properties model_param_props; + model_param_props.addLong("C_AXI_PROTOCOL", "2"); + model_param_props.addLong("C_AXI_INTERFACE_MODE", "0"); + model_param_props.addLong("C_AXI_ADDR_WIDTH", "32"); + model_param_props.addLong("C_AXI_WDATA_WIDTH", "32"); + model_param_props.addLong("C_AXI_RDATA_WIDTH", "32"); + model_param_props.addLong("C_AXI_WID_WIDTH", "0"); + model_param_props.addLong("C_AXI_RID_WIDTH", "0"); + model_param_props.addLong("C_AXI_AWUSER_WIDTH", "0"); + model_param_props.addLong("C_AXI_ARUSER_WIDTH", "0"); + model_param_props.addLong("C_AXI_WUSER_WIDTH", "0"); + model_param_props.addLong("C_AXI_RUSER_WIDTH", "0"); + model_param_props.addLong("C_AXI_BUSER_WIDTH", "0"); + model_param_props.addLong("C_AXI_SUPPORTS_NARROW", "0"); + model_param_props.addLong("C_AXI_HAS_BURST", "0"); + model_param_props.addLong("C_AXI_HAS_LOCK", "0"); + model_param_props.addLong("C_AXI_HAS_CACHE", "0"); + model_param_props.addLong("C_AXI_HAS_REGION", "0"); + model_param_props.addLong("C_AXI_HAS_PROT", "1"); + model_param_props.addLong("C_AXI_HAS_QOS", "0"); + model_param_props.addLong("C_AXI_HAS_WSTRB", "1"); + model_param_props.addLong("C_AXI_HAS_BRESP", "1"); + model_param_props.addLong("C_AXI_HAS_RRESP", "1"); + model_param_props.addLong("C_AXI_HAS_ARESETN", "1"); + model_param_props.addString("COMPONENT_NAME", "axi_mst_0"); + + mp_impl = new axi_vip("inst", model_param_props); + + // initialize AXI sockets + M_INITIATOR_rd_socket = mp_impl->M_INITIATOR_rd_socket; + M_INITIATOR_wr_socket = mp_impl->M_INITIATOR_wr_socket; +} + +axi_mst_0_sc::~axi_mst_0_sc() +{ + xsc::utils::xsc_sim_manager::clean(); + + delete mp_impl; +} + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_sc.h b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_sc.h new file mode 100644 index 0000000..5820d4b --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_sc.h @@ -0,0 +1,96 @@ +#ifndef IP_AXI_MST_0_SC_H_ +#define IP_AXI_MST_0_SC_H_ + +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +#ifndef XTLM +#include "xtlm.h" +#endif +#ifndef SYSTEMC_INCLUDED +#include +#endif + +#if defined(_MSC_VER) +#define DllExport __declspec(dllexport) +#elif defined(__GNUC__) +#define DllExport __attribute__ ((visibility("default"))) +#else +#define DllExport +#endif + +class axi_vip; + +class DllExport axi_mst_0_sc : public sc_core::sc_module +{ +public: + + axi_mst_0_sc(const sc_core::sc_module_name& nm); + virtual ~axi_mst_0_sc(); + + // module socket-to-socket AXI TLM interfaces + + xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_rd_socket; + xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_wr_socket; + + // module socket-to-socket TLM interfaces + + +protected: + + axi_vip* mp_impl; + +private: + + axi_mst_0_sc(const axi_mst_0_sc&); + const axi_mst_0_sc& operator=(const axi_mst_0_sc&); + +}; + +#endif // IP_AXI_MST_0_SC_H_ diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_stub.sv b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_stub.sv new file mode 100644 index 0000000..ba8eb44 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sim/axi_mst_0_stub.sv @@ -0,0 +1,121 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +//------------------------------------------------------------------------------------ +// Filename: axi_mst_0_stub.sv +// Description: This HDL file is intended to be used with following simulators only: +// +// Vivado Simulator (XSim) +// Cadence Xcelium Simulator +// +//------------------------------------------------------------------------------------ +`timescale 1ps/1ps + +`ifdef XILINX_SIMULATOR + +`ifndef XILINX_SIMULATOR_BITASBOOL +`define XILINX_SIMULATOR_BITASBOOL +typedef bit bit_as_bool; +`endif + +(* SC_MODULE_EXPORT *) +module axi_mst_0 ( + input bit_as_bool aclk, + input bit_as_bool aresetn, + output bit [31 : 0] m_axi_awaddr, + output bit [2 : 0] m_axi_awprot, + output bit_as_bool m_axi_awvalid, + input bit_as_bool m_axi_awready, + output bit [31 : 0] m_axi_wdata, + output bit [3 : 0] m_axi_wstrb, + output bit_as_bool m_axi_wvalid, + input bit_as_bool m_axi_wready, + input bit [1 : 0] m_axi_bresp, + input bit_as_bool m_axi_bvalid, + output bit_as_bool m_axi_bready, + output bit [31 : 0] m_axi_araddr, + output bit [2 : 0] m_axi_arprot, + output bit_as_bool m_axi_arvalid, + input bit_as_bool m_axi_arready, + input bit [31 : 0] m_axi_rdata, + input bit [1 : 0] m_axi_rresp, + input bit_as_bool m_axi_rvalid, + output bit_as_bool m_axi_rready +); +endmodule +`endif + +`ifdef XCELIUM +(* XMSC_MODULE_EXPORT *) +module axi_mst_0 (aclk,aresetn,m_axi_awaddr,m_axi_awprot,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arprot,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rvalid,m_axi_rready) +(* integer foreign = "SystemC"; +*); + input bit aclk; + input bit aresetn; + output wire [31 : 0] m_axi_awaddr; + output wire [2 : 0] m_axi_awprot; + output wire m_axi_awvalid; + input bit m_axi_awready; + output wire [31 : 0] m_axi_wdata; + output wire [3 : 0] m_axi_wstrb; + output wire m_axi_wvalid; + input bit m_axi_wready; + input bit [1 : 0] m_axi_bresp; + input bit m_axi_bvalid; + output wire m_axi_bready; + output wire [31 : 0] m_axi_araddr; + output wire [2 : 0] m_axi_arprot; + output wire m_axi_arvalid; + input bit m_axi_arready; + input bit [31 : 0] m_axi_rdata; + input bit [1 : 0] m_axi_rresp; + input bit m_axi_rvalid; + output wire m_axi_rready; +endmodule +`endif diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/synth/axi_mst_0.sv b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/synth/axi_mst_0.sv new file mode 100644 index 0000000..e238f2d --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/synth/axi_mst_0.sv @@ -0,0 +1,248 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 14 + +(* X_CORE_INFO = "axi_vip_v1_1_14_top,Vivado 2023.1" *) +(* CHECK_LICENSE_TYPE = "axi_mst_0,axi_vip_v1_1_14_top,{}" *) +(* CORE_GENERATION_INFO = "axi_mst_0,axi_vip_v1_1_14_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_vip,x_ipVersion=1.1,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_AXI_PROTOCOL=2,C_AXI_INTERFACE_MODE=0,C_AXI_ADDR_WIDTH=32,C_AXI_WDATA_WIDTH=32,C_AXI_RDATA_WIDTH=32,C_AXI_WID_WIDTH=0,C_AXI_RID_WIDTH=0,C_AXI_AWUSER_WIDTH=0,C_AXI_ARUSER_WIDTH=0,C_AXI_WUSER_WIDTH=0,C_AXI_RUSER_WIDTH=0,C_AXI_BUSER_WIDTH=0,C_AXI_SUPPORTS_NARROW=0,C_AXI_HAS_BURST=0,C_AXI_HAS_LOCK=0,C_AXI_HAS_C\ +ACHE=0,C_AXI_HAS_REGION=0,C_AXI_HAS_PROT=1,C_AXI_HAS_QOS=0,C_AXI_HAS_WSTRB=1,C_AXI_HAS_BRESP=1,C_AXI_HAS_RRESP=1,C_AXI_HAS_ARESETN=1}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module axi_mst_0 ( + aclk, + aresetn, + m_axi_awaddr, + m_axi_awprot, + m_axi_awvalid, + m_axi_awready, + m_axi_wdata, + m_axi_wstrb, + m_axi_wvalid, + m_axi_wready, + m_axi_bresp, + m_axi_bvalid, + m_axi_bready, + m_axi_araddr, + m_axi_arprot, + m_axi_arvalid, + m_axi_arready, + m_axi_rdata, + m_axi_rresp, + m_axi_rvalid, + m_axi_rready +); + +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLOCK, ASSOCIATED_BUSIF M_AXI:S_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLOCK CLK" *) +input wire aclk; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RESET, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RESET RST" *) +input wire aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) +output wire [31 : 0] m_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) +output wire [2 : 0] m_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) +output wire m_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) +input wire m_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) +output wire [31 : 0] m_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) +output wire [3 : 0] m_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) +output wire m_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) +input wire m_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) +input wire [1 : 0] m_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) +input wire m_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) +output wire m_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) +output wire [31 : 0] m_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) +output wire [2 : 0] m_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) +output wire m_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) +input wire m_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) +input wire [31 : 0] m_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) +input wire [1 : 0] m_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) +input wire m_axi_rvalid; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_B\ +ITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) +output wire m_axi_rready; + + axi_vip_v1_1_14_top #( + .C_AXI_PROTOCOL(2), + .C_AXI_INTERFACE_MODE(0), + .C_AXI_ADDR_WIDTH(32), + .C_AXI_WDATA_WIDTH(32), + .C_AXI_RDATA_WIDTH(32), + .C_AXI_WID_WIDTH(0), + .C_AXI_RID_WIDTH(0), + .C_AXI_AWUSER_WIDTH(0), + .C_AXI_ARUSER_WIDTH(0), + .C_AXI_WUSER_WIDTH(0), + .C_AXI_RUSER_WIDTH(0), + .C_AXI_BUSER_WIDTH(0), + .C_AXI_SUPPORTS_NARROW(0), + .C_AXI_HAS_BURST(0), + .C_AXI_HAS_LOCK(0), + .C_AXI_HAS_CACHE(0), + .C_AXI_HAS_REGION(0), + .C_AXI_HAS_PROT(1), + .C_AXI_HAS_QOS(0), + .C_AXI_HAS_WSTRB(1), + .C_AXI_HAS_BRESP(1), + .C_AXI_HAS_RRESP(1), + .C_AXI_HAS_ARESETN(1) + ) inst ( + .aclk(aclk), + .aclken(1'B1), + .aresetn(aresetn), + .s_axi_awid(1'B0), + .s_axi_awaddr(32'B0), + .s_axi_awlen(8'B0), + .s_axi_awsize(3'B0), + .s_axi_awburst(2'B1), + .s_axi_awlock(1'B0), + .s_axi_awcache(4'B0), + .s_axi_awprot(3'B0), + .s_axi_awregion(4'B0), + .s_axi_awqos(4'B0), + .s_axi_awuser(1'B0), + .s_axi_awvalid(1'B0), + .s_axi_awready(), + .s_axi_wid(1'B0), + .s_axi_wdata(32'B0), + .s_axi_wstrb(4'HF), + .s_axi_wlast(1'B0), + .s_axi_wuser(1'B0), + .s_axi_wvalid(1'B0), + .s_axi_wready(), + .s_axi_bid(), + .s_axi_bresp(), + .s_axi_buser(), + .s_axi_bvalid(), + .s_axi_bready(1'B0), + .s_axi_arid(1'B0), + .s_axi_araddr(32'B0), + .s_axi_arlen(8'B0), + .s_axi_arsize(3'B0), + .s_axi_arburst(2'B1), + .s_axi_arlock(1'B0), + .s_axi_arcache(4'B0), + .s_axi_arprot(3'B0), + .s_axi_arregion(4'B0), + .s_axi_arqos(4'B0), + .s_axi_aruser(1'B0), + .s_axi_arvalid(1'B0), + .s_axi_arready(), + .s_axi_rid(), + .s_axi_rdata(), + .s_axi_rresp(), + .s_axi_rlast(), + .s_axi_ruser(), + .s_axi_rvalid(), + .s_axi_rready(1'B0), + .m_axi_awid(), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awlen(), + .m_axi_awsize(), + .m_axi_awburst(), + .m_axi_awlock(), + .m_axi_awcache(), + .m_axi_awprot(m_axi_awprot), + .m_axi_awregion(), + .m_axi_awqos(), + .m_axi_awuser(), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_awready(m_axi_awready), + .m_axi_wid(), + .m_axi_wdata(m_axi_wdata), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wlast(), + .m_axi_wuser(), + .m_axi_wvalid(m_axi_wvalid), + .m_axi_wready(m_axi_wready), + .m_axi_bid(1'B0), + .m_axi_bresp(m_axi_bresp), + .m_axi_buser(1'B0), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_bready(m_axi_bready), + .m_axi_arid(), + .m_axi_araddr(m_axi_araddr), + .m_axi_arlen(), + .m_axi_arsize(), + .m_axi_arburst(), + .m_axi_arlock(), + .m_axi_arcache(), + .m_axi_arprot(m_axi_arprot), + .m_axi_arregion(), + .m_axi_arqos(), + .m_axi_aruser(), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_arready(m_axi_arready), + .m_axi_rid(1'B0), + .m_axi_rdata(m_axi_rdata), + .m_axi_rresp(m_axi_rresp), + .m_axi_rlast(1'B0), + .m_axi_ruser(1'B0), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_rready(m_axi_rready) + ); +endmodule diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/axi_vip.cpp b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/axi_vip.cpp new file mode 100644 index 0000000..dfa25ea --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/axi_vip.cpp @@ -0,0 +1,140 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +#include "axi_vip.h" +#include + +axi_vip::axi_vip(sc_core::sc_module_name module_name, + xsc::common_cpp::properties model_param_props) : + sc_module(module_name), S_TARGET_rd_socket(nullptr), S_TARGET_wr_socket( + nullptr), M_INITIATOR_rd_socket(nullptr), M_INITIATOR_wr_socket( + nullptr), P1(nullptr), P2(nullptr), m_ipc_master(nullptr), m_ipc_slave( + nullptr) +{ + int int_type = model_param_props.getLongLong("C_AXI_INTERFACE_MODE"); + if (int_type == 1) + { + M_INITIATOR_rd_socket = new xtlm::xtlm_aximm_initiator_socket( + "initiator_rd_socket", 32); + M_INITIATOR_wr_socket = new xtlm::xtlm_aximm_initiator_socket( + "initiator_wr_socket", 32); + S_TARGET_rd_socket = new xtlm::xtlm_aximm_target_socket( + "target_rd_socket", 32); + S_TARGET_wr_socket = new xtlm::xtlm_aximm_target_socket( + "target_wr_socket", 32); + P1 = new xtlm::xtlm_aximm_passthru_module("P1"); + P2 = new xtlm::xtlm_aximm_passthru_module("P2"); + P1->initiator_socket->bind(*M_INITIATOR_rd_socket); + P2->initiator_socket->bind(*M_INITIATOR_wr_socket); + S_TARGET_rd_socket->bind(*(P1->target_socket)); + S_TARGET_wr_socket->bind(*(P2->target_socket)); + } + if (int_type == 0) + { + if (std::getenv("ENABLE_XTLM_IPC_IN_VIP") == nullptr) + { + M_INITIATOR_rd_socket = new xtlm::xtlm_aximm_initiator_socket( + "initiator_rd_socket", 32); + M_INITIATOR_wr_socket = new xtlm::xtlm_aximm_initiator_socket( + "initiator_wr_socket", 32); + auto *stubWr = new xtlm::xtlm_aximm_initiator_stub("ifWrStubskt0", + 32); + stubWr->initiator_socket->bind(*M_INITIATOR_wr_socket); + auto *stubRd = new xtlm::xtlm_aximm_initiator_stub("ifRdStubskt0", + 32); + stubRd->initiator_socket->bind(*M_INITIATOR_rd_socket); + stubInitSkt.push_back(stubWr); + stubInitSkt.push_back(stubRd); + } + else + { + m_ipc_master = new sim_ipc_aximm_master(this->name(), + model_param_props); + M_INITIATOR_rd_socket = m_ipc_master->rd_socket; + M_INITIATOR_wr_socket = m_ipc_master->wr_socket; + m_ipc_master->m_aximm_aclk(aclk); + m_ipc_master->m_aximm_aresetn(aresetn); + } + } + if (int_type == 2) + { + if (std::getenv("ENABLE_XTLM_IPC_IN_VIP") == nullptr) + { + S_TARGET_rd_socket = new xtlm::xtlm_aximm_target_socket( + "target_rd_socket", 32); + S_TARGET_wr_socket = new xtlm::xtlm_aximm_target_socket( + "target_wr_socket", 32); + auto *stubWr = new xtlm::xtlm_aximm_target_stub("ifWrStubskt0", 32); + S_TARGET_wr_socket->bind(stubWr->target_socket); + auto *stubRd = new xtlm::xtlm_aximm_target_stub("ifRdStubskt0", 32); + S_TARGET_rd_socket->bind(stubRd->target_socket); + stubTargetSkt.push_back(stubWr); + stubTargetSkt.push_back(stubRd); + } + else + { + m_ipc_slave = new sim_ipc_aximm_slave(this->name(), + model_param_props); + S_TARGET_rd_socket = m_ipc_slave->rd_socket; + S_TARGET_wr_socket = m_ipc_slave->wr_socket; + m_ipc_slave->s_aximm_aclk(aclk); + m_ipc_slave->s_aximm_aresetn(aresetn); + } + } +} +axi_vip::~axi_vip() +{ + delete M_INITIATOR_wr_socket; + delete M_INITIATOR_rd_socket; + delete S_TARGET_wr_socket; + delete S_TARGET_rd_socket; + delete P1; + delete P2; + delete m_ipc_master; + delete m_ipc_slave; +} diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/axi_vip.h b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/axi_vip.h new file mode 100644 index 0000000..b11098e --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/axi_vip.h @@ -0,0 +1,81 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +#pragma once + +#include +#include "utils/xtlm_aximm_target_stub.h" +#include "utils/xtlm_aximm_initiator_stub.h" +#include +#include +#include "sim_ipc_aximm_master.h" +#include "sim_ipc_aximm_slave.h" + +class axi_vip: public sc_core::sc_module +{ +public: + axi_vip(sc_core::sc_module_name module_name, + xsc::common_cpp::properties model_param_props); + virtual ~axi_vip(); + SC_HAS_PROCESS (axi_vip); + xtlm::xtlm_aximm_target_socket *S_TARGET_rd_socket; + xtlm::xtlm_aximm_target_socket *S_TARGET_wr_socket; + xtlm::xtlm_aximm_initiator_socket *M_INITIATOR_rd_socket; + xtlm::xtlm_aximm_initiator_socket *M_INITIATOR_wr_socket; + std::vector stubTargetSkt; + std::vector stubInitSkt; + sc_core::sc_in aclk; + sc_core::sc_in aresetn; +private: + xtlm::xtlm_aximm_passthru_module *P1; + xtlm::xtlm_aximm_passthru_module *P2; + sim_ipc_aximm_master* m_ipc_master; + sim_ipc_aximm_slave* m_ipc_slave; + +}; + diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_master.cpp b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_master.cpp new file mode 100644 index 0000000..59bf57a --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_master.cpp @@ -0,0 +1,144 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +#include "sim_ipc_aximm_master.h" +using namespace xtlm; + +sim_ipc_aximm_master::sim_ipc_aximm_master(sc_core::sc_module_name name, + xsc::common_cpp::properties &ppts):sc_module(name), + rd_util(sc_gen_unique_name("rd_util"),xtlm::aximm::TRANSACTION,0), + wr_util(sc_gen_unique_name("wr_util"),xtlm::aximm::TRANSACTION,0), + m_logger((std::string) name) +{ + rd_socket = new xtlm::xtlm_aximm_initiator_socket( + sc_gen_unique_name("rd_socket"), 0); + wr_socket = new xtlm::xtlm_aximm_initiator_socket( + sc_gen_unique_name("wr_socket"), 0); + + //TODO Supporting outstanding transactions + rd_util.rd_socket.bind(*rd_socket); + wr_util.wr_socket.bind(*wr_socket); + + m_ipc2aximm_socket = new xsc::ipc2aximm_socket( + sc_gen_unique_name("ipc2aximm_socket"), get_ipi_name(this->name())); + + SC_METHOD(ipc2aximm_receive); + sensitive << m_ipc2aximm_socket->event(); + sensitive << wr_util.resp_available; + sensitive << rd_util.data_available; + //As of now only 1 outstanding transaction is supported. + //If we support more, this may need to be updated. + dont_initialize(); + + SC_METHOD(send_response); + sensitive << wr_util.resp_available; + sensitive << rd_util.data_available; + dont_initialize(); +} + +sim_ipc_aximm_master::~sim_ipc_aximm_master() +{ + delete m_ipc2aximm_socket; + delete rd_socket; + delete wr_socket; +} + +void sim_ipc_aximm_master::ipc2aximm_receive() +{ + if(!m_ipc2aximm_socket->peek_payload()) + return; + + if (wr_util.is_slave_ready() && + (m_ipc2aximm_socket->peek_payload()->get_command() + == xtlm::XTLM_WRITE_COMMAND)) + { + auto delay = sc_core::sc_time(SC_ZERO_TIME); + XSC_REPORT_INFO_VERB(m_logger, "IPC_AXIMM_MASTER", + "Sending Write Request", DEBUG); + //We Can do transaction on Write Channel + wr_util.send_transaction(*m_ipc2aximm_socket->get_payload(), delay); + + } + + //Don't proceed further if there's no transaction + if (!m_ipc2aximm_socket->peek_payload()) + return; + + if (rd_util.is_slave_ready() + && (m_ipc2aximm_socket->peek_payload()->get_command() + == xtlm::XTLM_READ_COMMAND)) + { + auto delay = sc_core::sc_time(SC_ZERO_TIME); + XSC_REPORT_INFO_VERB(m_logger, "IPC_AXIMM_MASTER", + "Sending Read Request", DEBUG); + rd_util.send_transaction(*m_ipc2aximm_socket->get_payload(), delay); + } +} + +void sim_ipc_aximm_master::send_response() +{ + if(wr_util.is_resp_available()) + { + XSC_REPORT_INFO_VERB(m_logger, "IPC_AXIMM_MASTER", + "Sending Write Response", DEBUG); + m_ipc2aximm_socket->send_response(wr_util.get_resp()); + } + if(rd_util.is_data_available()) + { + XSC_REPORT_INFO_VERB(m_logger, "IPC_AXIMM_MASTER", + "Sending Read Response", DEBUG); + m_ipc2aximm_socket->send_response(rd_util.get_data()); + } +} + +std::string sim_ipc_aximm_master::get_ipi_name(std::string s) +{ + s = s.substr(0, s.find_last_of("./")); // Adding "/" to support QUESTA + s = s.substr(s.find_last_of("./") + 1); + return s; +} diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_master.h b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_master.h new file mode 100644 index 0000000..6691a81 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_master.h @@ -0,0 +1,82 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +#pragma once + +#include "xtlm.h" +#include "ipc2aximm_socket.h" +#include + +class sim_ipc_aximm_master : public sc_core::sc_module +{ +public: + SC_HAS_PROCESS(sim_ipc_aximm_master); + + sim_ipc_aximm_master(sc_core::sc_module_name name, + xsc::common_cpp::properties &ppts); + + ~sim_ipc_aximm_master(); + + sc_core::sc_in m_aximm_aresetn; + sc_core::sc_in m_aximm_aclk; + + //Read & Write Sockets + xtlm::xtlm_aximm_initiator_socket* rd_socket; + xtlm::xtlm_aximm_initiator_socket* wr_socket; + + xtlm::xtlm_aximm_initiator_rd_socket_util rd_util; + xtlm::xtlm_aximm_initiator_wr_socket_util wr_util; +private: + //! SystemC Method to Read incoming data from ipc... + void ipc2aximm_receive(); + void send_response(); + std::string get_ipi_name(std::string s); + + xsc::ipc2aximm_socket* m_ipc2aximm_socket; + xsc::common_cpp::report_handler m_logger; +}; diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_slave.cpp b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_slave.cpp new file mode 100644 index 0000000..1a9dad1 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_slave.cpp @@ -0,0 +1,134 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +#include "sim_ipc_aximm_slave.h" + +sim_ipc_aximm_slave::sim_ipc_aximm_slave(sc_core::sc_module_name name, + xsc::common_cpp::properties &ppts) : + sc_module(name), + rd_util(sc_gen_unique_name("rd_util"),xtlm::aximm::TRANSACTION,0), + wr_util(sc_gen_unique_name("wr_util"),xtlm::aximm::TRANSACTION,0), + m_logger(static_cast(name)) +{ + rd_socket = new xtlm::xtlm_aximm_target_socket( + sc_gen_unique_name("rd_socket"), 0); + wr_socket = new xtlm::xtlm_aximm_target_socket( + sc_gen_unique_name("wr_socket"), 0); + wr_socket->bind(wr_util.wr_socket); + rd_socket->bind(rd_util.rd_socket); + + m_aximm2ipc_socket = new xsc::aximm2ipc_socket("aximm2ipc_socket", + get_ipi_name(this->name())); + + SC_METHOD(aximm2ipc_send); + sensitive << wr_util.transaction_available; + sensitive << rd_util.transaction_available; + m_aximm2ipc_socket->event(); + dont_initialize(); + + SC_METHOD(aximm_resp_handler); + sensitive << m_aximm2ipc_socket->event(); + sensitive << wr_util.transaction_available; + sensitive << rd_util.transaction_available; + dont_initialize(); +} + +sim_ipc_aximm_slave::~sim_ipc_aximm_slave() +{ + delete m_aximm2ipc_socket; +} + +void sim_ipc_aximm_slave::aximm2ipc_send() +{ + if(wr_util.is_trans_available() && m_aximm2ipc_socket->is_ready()) + { + XSC_REPORT_INFO_VERB(m_logger, "IPC_AXIMM_SLAVE", + "Sending Write Request", DEBUG); + m_aximm2ipc_socket->transport(wr_util.get_transaction()); + } + if(rd_util.is_trans_available() && m_aximm2ipc_socket->is_ready()) + { + XSC_REPORT_INFO_VERB(m_logger, "IPC_AXIMM_SLAVE", + "Sending Read Request", DEBUG); + m_aximm2ipc_socket->transport(rd_util.get_transaction()); + } +} + +void sim_ipc_aximm_slave::aximm_resp_handler() +{ + //if there's no payload response. Return + if(!m_aximm2ipc_socket->peek_resp()) + return; + if (wr_util.is_master_ready() + && m_aximm2ipc_socket->peek_resp()->get_command() + == xtlm::XTLM_WRITE_COMMAND) + { + auto delay = sc_core::sc_time(SC_ZERO_TIME); + XSC_REPORT_INFO_VERB(m_logger, "IPC_AXIMM_SLAVE", + "Sending Write Response", DEBUG); + wr_util.send_resp(*m_aximm2ipc_socket->get_resp(),delay); + } + //if there's no payload response. Return + if(!m_aximm2ipc_socket->peek_resp()) + return; + + if(rd_util.is_master_ready() && m_aximm2ipc_socket->peek_resp()->get_command() == xtlm::XTLM_READ_COMMAND) + { + auto delay = sc_core::sc_time(SC_ZERO_TIME); + XSC_REPORT_INFO_VERB(m_logger, "IPC_AXIMM_SLAVE", + "Sending Read Data", DEBUG); + rd_util.send_data(*m_aximm2ipc_socket->get_resp(), delay); + } +} + +std::string sim_ipc_aximm_slave::get_ipi_name(std::string s) +{ + s = s.substr(0, s.find_last_of("./")); // Adding "/" to support QUESTA + s = s.substr(s.find_last_of("./") + 1); + return s; +} diff --git a/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_slave.h b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_slave.h new file mode 100644 index 0000000..74bd633 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_mst_0/sysc/sim_ipc_aximm_slave.h @@ -0,0 +1,82 @@ +// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +#pragma once + +#include "xtlm.h" +#include "aximm2ipc_socket.h" + +class sim_ipc_aximm_slave : public sc_core::sc_module +{ +public: + SC_HAS_PROCESS(sim_ipc_aximm_slave); + sim_ipc_aximm_slave(sc_core::sc_module_name name, + xsc::common_cpp::properties& ppts); + ~sim_ipc_aximm_slave(); + + sc_core::sc_in s_aximm_aclk; + sc_core::sc_in s_aximm_aresetn; + + xtlm::xtlm_aximm_target_socket* rd_socket; + xtlm::xtlm_aximm_target_socket* wr_socket; + + xtlm::xtlm_aximm_target_rd_socket_util rd_util; + xtlm::xtlm_aximm_target_wr_socket_util wr_util; + +private: + //! SystemC method to send the AXIMM data to external process + void aximm2ipc_send(); + + //! SystemC Method to handle AXIMM Response + void aximm_resp_handler(); + + std::string get_ipi_name(std::string s); + + xsc::aximm2ipc_socket* m_aximm2ipc_socket; + xsc::common_cpp::report_handler m_logger; +}; diff --git a/firmware/ip/axis_weighted_buffer/src/axi_slv.vhd b/firmware/ip/axis_weighted_buffer/src/axi_slv.vhd new file mode 100644 index 0000000..8621d43 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axi_slv.vhd @@ -0,0 +1,544 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + AVG_START_REG : out std_logic; + AVG_ADDR_REG : out std_logic_vector (31 downto 0); + AVG_LEN_REG : out std_logic_vector (31 downto 0); + AVG_PHOTON_MODE_REG : out std_logic; + AVG_H_THRSH_REG : out std_logic_vector (31 downto 0); + AVG_L_THRSH_REG : out std_logic_vector (31 downto 0); + AVG_DR_START_REG: out std_logic; + AVG_DR_ADDR_REG : out std_logic_vector (31 downto 0); + AVG_DR_LEN_REG : out std_logic_vector (31 downto 0); + BUF_START_REG : out std_logic; + BUF_ADDR_REG : out std_logic_vector (31 downto 0); + BUF_LEN_REG : out std_logic_vector (31 downto 0); + BUF_DR_START_REG: out std_logic; + BUF_DR_ADDR_REG : out std_logic_vector (31 downto 0); + BUF_DR_LEN_REG : out std_logic_vector (31 downto 0); + WGT_DW_ADDR_REG : out std_logic_vector (31 downto 0); + WGT_DW_START_REG: out std_logic + ); +end axi_slv; + +architecture rtl of axi_slv is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + -- Register Map. + + -- Output Registers. + AVG_START_REG <= slv_reg0(0); + AVG_ADDR_REG <= slv_reg1; + AVG_LEN_REG <= slv_reg2; + AVG_DR_START_REG <= slv_reg3(0); + AVG_DR_ADDR_REG <= slv_reg4; + AVG_DR_LEN_REG <= slv_reg5; + BUF_START_REG <= slv_reg0(1); + BUF_ADDR_REG <= slv_reg6; + BUF_LEN_REG <= slv_reg7; + BUF_DR_START_REG <= slv_reg3(1); + BUF_DR_ADDR_REG <= slv_reg8; + BUF_DR_LEN_REG <= slv_reg9; + AVG_PHOTON_MODE_REG <= slv_reg10(0); + AVG_H_THRSH_REG <= slv_reg11; + AVG_L_THRSH_REG <= slv_reg12; + WGT_DW_ADDR_REG <= slv_reg13; + WGT_DW_START_REG <= slv_reg3(2); + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/axis_weighted_buffer.v b/firmware/ip/axis_weighted_buffer/src/axis_weighted_buffer.v new file mode 100644 index 0000000..7967dde --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/axis_weighted_buffer.v @@ -0,0 +1,299 @@ +// AXIS AVG BUFFER. +// s_axi_aclk : clock for s_axi_* +// s_axis_aclk : clock for s_axis_* +// m_axis_aclk : clock for m0_axis_* and m1_axis_* +// +module axis_weighted_buffer + ( + // AXI Slave I/F for configuration. + s_axi_aclk , + s_axi_aresetn , + + s_axi_awaddr , + s_axi_awprot , + s_axi_awvalid , + s_axi_awready , + + s_axi_wdata , + s_axi_wstrb , + s_axi_wvalid , + s_axi_wready , + + s_axi_bresp , + s_axi_bvalid , + s_axi_bready , + + s_axi_araddr , + s_axi_arprot , + s_axi_arvalid , + s_axi_arready , + + s_axi_rdata , + s_axi_rresp , + s_axi_rvalid , + s_axi_rready , + + // Trigger input. + trigger , + + // AXIS Slave for memory programming + s1_axis_tvalid, + s1_axis_tdata, + s1_axis_tready, + + // AXIS Slave for input data. + s_axis_aclk , + s_axis_aresetn , + s_axis_tvalid , + s_axis_tready , + s_axis_tdata , + + // Reset and clock for m0 and m1. + m_axis_aclk , + m_axis_aresetn , + + // AXIS Master for averaged output. + m0_axis_tvalid , + m0_axis_tready , + m0_axis_tdata , + m0_axis_tlast , + + // AXIS Master for raw output. + m1_axis_tvalid , + m1_axis_tready , + m1_axis_tdata , + m1_axis_tlast , + + // AXIS Master for register output. + m2_axis_tvalid , + m2_axis_tready , + m2_axis_tdata + ); + + /**************/ + /* Parameters */ + /**************/ + // Memory depth. + parameter N_AVG = 14; + parameter N_BUF = 14; + parameter N_WGT = 14; + + // Number of bits. + parameter B = 16; + + /*********/ + /* Ports */ + /*********/ + input s_axi_aclk; + input s_axi_aresetn; + + input [5:0] s_axi_awaddr; + input [2:0] s_axi_awprot; + input s_axi_awvalid; + output s_axi_awready; + + input [31:0] s_axi_wdata; + input [3:0] s_axi_wstrb; + input s_axi_wvalid; + output s_axi_wready; + + output [1:0] s_axi_bresp; + output s_axi_bvalid; + input s_axi_bready; + + input [5:0] s_axi_araddr; + input [2:0] s_axi_arprot; + input s_axi_arvalid; + output s_axi_arready; + + output [31:0] s_axi_rdata; + output [1:0] s_axi_rresp; + output s_axi_rvalid; + input s_axi_rready; + + input trigger; + + input s_axis_aclk; + input s_axis_aresetn; + input s_axis_tvalid; + output s_axis_tready; + input [2*B-1:0] s_axis_tdata; + + input s1_axis_tvalid; + output s1_axis_tready; + input [2*B-1:0] s1_axis_tdata; + + input m_axis_aclk; + input m_axis_aresetn; + + output m0_axis_tvalid; + input m0_axis_tready; + output [4*B-1:0] m0_axis_tdata; + output m0_axis_tlast; + + output m1_axis_tvalid; + input m1_axis_tready; + output [2*B-1:0] m1_axis_tdata; + output m1_axis_tlast; + + output m2_axis_tvalid; + input m2_axis_tready; + output [4*B-1:0] m2_axis_tdata; + + + /********************/ + /* Internal signals */ + /********************/ + // Registers. + wire AVG_START_REG; + wire [N_AVG-1:0] AVG_ADDR_REG; + wire [31:0] AVG_LEN_REG; + wire AVG_PHOTON_MODE_REG; + wire [B-1:0] AVG_H_THRSH_REG; + wire [B-1:0] AVG_L_THRSH_REG; + wire AVG_DR_START_REG; + wire [N_AVG-1:0] AVG_DR_ADDR_REG; + wire [N_AVG-1:0] AVG_DR_LEN_REG; + wire BUF_START_REG; + wire [N_BUF-1:0] BUF_ADDR_REG; + wire [N_BUF-1:0] BUF_LEN_REG; + wire BUF_DR_START_REG; + wire [N_BUF-1:0] BUF_DR_ADDR_REG; + wire [N_BUF-1:0] BUF_DR_LEN_REG; + wire [N_WGT-1:0] WGT_DW_ADDR_REG; + wire WGT_DW_START_REG; + + + + /**********************/ + /* Begin Architecture */ + /**********************/ + // AXI Slave. + axi_slv axi_slv_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + + // Write Address Channel. + .awaddr (s_axi_awaddr ), + .awprot (s_axi_awprot ), + .awvalid (s_axi_awvalid ), + .awready (s_axi_awready ), + + // Write Data Channel. + .wdata (s_axi_wdata ), + .wstrb (s_axi_wstrb ), + .wvalid (s_axi_wvalid ), + .wready (s_axi_wready ), + + // Write Response Channel. + .bresp (s_axi_bresp ), + .bvalid (s_axi_bvalid ), + .bready (s_axi_bready ), + + // Read Address Channel. + .araddr (s_axi_araddr ), + .arprot (s_axi_arprot ), + .arvalid (s_axi_arvalid ), + .arready (s_axi_arready ), + + // Read Data Channel. + .rdata (s_axi_rdata ), + .rresp (s_axi_rresp ), + .rvalid (s_axi_rvalid ), + .rready (s_axi_rready ), + + // Registers. + .AVG_START_REG (AVG_START_REG ), + .AVG_ADDR_REG (AVG_ADDR_REG ), + .AVG_LEN_REG (AVG_LEN_REG ), + .AVG_PHOTON_MODE_REG (AVG_PHOTON_MODE_REG), + .AVG_H_THRSH_REG (AVG_H_THRSH_REG ), + .AVG_L_THRSH_REG (AVG_L_THRSH_REG ), + .AVG_DR_START_REG (AVG_DR_START_REG ), + .AVG_DR_ADDR_REG (AVG_DR_ADDR_REG ), + .AVG_DR_LEN_REG (AVG_DR_LEN_REG ), + .BUF_START_REG (BUF_START_REG ), + .BUF_ADDR_REG (BUF_ADDR_REG ), + .BUF_LEN_REG (BUF_LEN_REG ), + .BUF_DR_START_REG (BUF_DR_START_REG ), + .BUF_DR_ADDR_REG (BUF_DR_ADDR_REG ), + .BUF_DR_LEN_REG (BUF_DR_LEN_REG ), + .WGT_DW_ADDR_REG (WGT_DW_ADDR_REG ), + .WGT_DW_START_REG (WGT_DW_START_REG) + ); + + // Averager + Buffer Top. + avg_buffer + #( + .N_AVG (N_AVG ), + .N_BUF (N_BUF ), + .N_WGT (N_WGT ), + .B (B ) + ) + avg_buffer_i + ( + // Reset and clock for readout data path + .s_axis_aclk (s_axis_aclk ), + .s_axis_aresetn (s_axis_aresetn ), + + // Reset and clock for writing weights + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + + // Trigger input. + .trigger (trigger ), + + // AXIS Slave for memory programming + .s1_axis_tvalid(s1_axis_tvalid), + .s1_axis_tdata(s1_axis_tdata), + .s1_axis_tready(s1_axis_tready), + + // AXIS Slave for input data. + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tready (s_axis_tready ), + .s_axis_tdata (s_axis_tdata ), + + // Reset and clock for m0 and m1. + .m_axis_aclk (m_axis_aclk ), + .m_axis_aresetn (m_axis_aresetn ), + + // AXIS Master for averaged output. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tready (m0_axis_tready ), + .m0_axis_tdata (m0_axis_tdata ), + .m0_axis_tlast (m0_axis_tlast ), + + // AXIS Master for raw output. + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tready (m1_axis_tready ), + .m1_axis_tdata (m1_axis_tdata ), + .m1_axis_tlast (m1_axis_tlast ), + + // AXIS Master for register output. + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tready (m2_axis_tready ), + .m2_axis_tdata (m2_axis_tdata ), + + // Registers. + .AVG_START_REG (AVG_START_REG ), + .AVG_ADDR_REG (AVG_ADDR_REG[N_AVG-1:0] ), + .AVG_LEN_REG (AVG_LEN_REG[2*B-1:0] ), + .AVG_PHOTON_MODE_REG (AVG_PHOTON_MODE_REG), + .AVG_H_THRSH_REG (AVG_H_THRSH_REG[N_BUF-1:0] ), + .AVG_L_THRSH_REG (AVG_L_THRSH_REG[B-1:0] ), + .AVG_DR_START_REG (AVG_DR_START_REG ), + .AVG_DR_ADDR_REG (AVG_DR_ADDR_REG[N_AVG-1:0] ), + .AVG_DR_LEN_REG (AVG_DR_LEN_REG[N_AVG-1:0] ), + .BUF_START_REG (BUF_START_REG ), + .BUF_ADDR_REG (BUF_ADDR_REG[N_BUF-1:0] ), + .BUF_LEN_REG (BUF_LEN_REG[N_BUF-1:0] ), + .BUF_DR_START_REG (BUF_DR_START_REG ), + .BUF_DR_ADDR_REG (BUF_DR_ADDR_REG[N_BUF-1:0] ), + .BUF_DR_LEN_REG (BUF_DR_LEN_REG[N_BUF-1:0] ), + .WGT_DW_ADDR_REG (WGT_DW_ADDR_REG[N_WGT-1:0] ), + .WGT_DW_START_REG (WGT_DW_START_REG) + ); + +endmodule + diff --git a/firmware/ip/axis_weighted_buffer/src/buffer.sv b/firmware/ip/axis_weighted_buffer/src/buffer.sv new file mode 100644 index 0000000..ef168f6 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/buffer.sv @@ -0,0 +1,174 @@ +// Data is I,Q. +// I: lower B bits. +// Q: upper B bits. +module buffer ( + // Reset and clock. + rstn , + clk , + + // Trigger input. + trigger_i , + + // Data input. + din_valid_i , + din_i , + + // Memory interface. + mem_we_o , + mem_addr_o , + mem_di_o , + + // Registers. + START_REG , + ADDR_REG , + LEN_REG + ); + +//////////////// +// Parameters // +//////////////// +// Memory depth. +parameter N = 10; + +// Number of bits. +parameter B = 16; + +/////////// +// Ports // +/////////// +input rstn; +input clk; + +input trigger_i; + +input din_valid_i; +input [2*B-1:0] din_i; + +output mem_we_o; +output [N-1:0] mem_addr_o; +output [2*B-1:0] mem_di_o; + +input START_REG; +input [N-1:0] ADDR_REG; +input [N-1:0] LEN_REG; + +////////////////////// +// Internal signals // +////////////////////// +// States. +typedef enum { INIT_ST , + START_ST , + TRIGGER_ST , + MEMW_ST , + WAIT_TRIGGER_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +reg start_state; +reg trigger_state; +reg memw_state; + +// Counter. +reg [N-1:0] cnt; + +// Registers. +reg [N-1:0] addr_r; +reg [N-1:0] len_r; + +////////////////// +// Architecture // +////////////////// + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= INIT_ST; + + // Counter. + cnt <= 0; + + // Registers. + addr_r <= 0; + len_r <= 0; + end + else begin + // State register. + case (state) + INIT_ST: + state <= START_ST; + + START_ST: + if ( START_REG == 1'b1) + state <= TRIGGER_ST; + + TRIGGER_ST: + if ( START_REG == 1'b0 ) + state <= START_ST; + else if ( trigger_i == 1'b1 ) + state <= MEMW_ST; + + MEMW_ST: + if ( cnt == len_r-1 && din_valid_i == 1'b1 ) + state <= WAIT_TRIGGER_ST; + + WAIT_TRIGGER_ST: + if ( START_REG == 1'b0 ) + state <= START_ST; + else if ( trigger_i == 1'b0 ) begin + state <= TRIGGER_ST; + end + endcase + + // Counter. + if ( memw_state == 1'b1 ) begin + if (din_valid_i == 1'b1) + cnt <= cnt + 1; + end + else begin + cnt <= 0; + end + + // Registers. + if ( start_state == 1'b1 ) begin + addr_r <= ADDR_REG; + len_r <= LEN_REG; + end + else if ( memw_state == 1'b1 && din_valid_i == 1'b1) begin + addr_r <= addr_r + 1; + end + end +end + +// FSM outputs. +always_comb begin + // Default. + start_state = 0; + trigger_state = 0; + memw_state = 0; + + case (state) + //INIT_ST: + + START_ST: + start_state = 1'b1; + + TRIGGER_ST: + trigger_state = 1'b1; + + MEMW_ST: + memw_state = 1'b1; + + //WAIT_TRIGGER_ST: + endcase +end + +// Assign outputs. +assign mem_we_o = memw_state & din_valid_i; +assign mem_addr_o = addr_r; +assign mem_di_o = din_i; + +endmodule + diff --git a/firmware/ip/axis_weighted_buffer/src/buffer_top.v b/firmware/ip/axis_weighted_buffer/src/buffer_top.v new file mode 100644 index 0000000..3a5259a --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/buffer_top.v @@ -0,0 +1,185 @@ +module buffer_top ( + // Reset and clock. + rstn , + clk , + + // Trigger input. + trigger_i , + + // Data input. + din_valid_i , + din_i , + + // AXIS Master for output. + m_axis_aclk , + m_axis_aresetn , + m_axis_tvalid , + m_axis_tready , + m_axis_tdata , + m_axis_tlast , + + // Registers. + BUF_START_REG , + BUF_ADDR_REG , + BUF_LEN_REG , + DR_START_REG , + DR_ADDR_REG , + DR_LEN_REG + ); + + //////////////// + // Parameters // + //////////////// + // Memory depth. + parameter N = 10; + + // Number of bits. + parameter B = 16; + + /////////// + // Ports // + /////////// + input rstn; + input clk; + + input trigger_i; + + input din_valid_i; + input [2*B-1:0] din_i; + + input m_axis_aclk; + input m_axis_aresetn; + output m_axis_tvalid; + input m_axis_tready; + output [2*B-1:0] m_axis_tdata; + output m_axis_tlast; + + input BUF_START_REG; + input [N-1:0] BUF_ADDR_REG; + input [N-1:0] BUF_LEN_REG; + input DR_START_REG; + input [N-1:0] DR_ADDR_REG; + input [N-1:0] DR_LEN_REG; + + ////////////////////// + // Internal signals // + ////////////////////// + wire mem_we_int; + wire [N-1:0] mem_addra_int, mem_addrb_int; + wire [2*B-1:0] mem_di_int, mem_do_int; + + wire BUF_START_REG_resync; + wire DR_START_REG_resync; + + ////////////////// + // Architecture // + ////////////////// + + // BUF_START_REG_resync + synchronizer_n + #( + .N (2) + ) + BUF_START_REG_resync_i ( + .rstn (rstn ), + .clk (clk ), + .data_in (BUF_START_REG ), + .data_out (BUF_START_REG_resync ) + ); + + //DR_START_REG_resync + synchronizer_n + #( + .N (2) + ) + DR_START_REG_resync_i ( + .rstn (m_axis_aresetn ), + .clk (m_axis_aclk ), + .data_in (DR_START_REG ), + .data_out (DR_START_REG_resync ) + ); + + // Buffer block. + buffer + #( + .N (N), + .B (B) + ) + buffer_i + ( + // Reset and clock. + .rstn (rstn ), + .clk (clk ), + + // Trigger input. + .trigger_i (trigger_i ), + + // Data input. + .din_valid_i (din_valid_i ), + .din_i (din_i ), + + // Memory interface. + .mem_we_o (mem_we_int ), + .mem_addr_o (mem_addra_int ), + .mem_di_o (mem_di_int ), + + // Registers. + .START_REG (BUF_START_REG_resync ), + .ADDR_REG (BUF_ADDR_REG ), + .LEN_REG (BUF_LEN_REG ) + ); + + // Dual port BRAM. + bram_dp + #( + .N (N ), + .B (2*B) + ) + bram_i + ( + .clka (clk ), + .clkb (m_axis_aclk ), + .ena (1'b1 ), + .enb (1'b1 ), + .wea (mem_we_int ), + .web (1'b0 ), + .addra (mem_addra_int ), + .addrb (mem_addrb_int ), + .dia (mem_di_int ), + .dib ({4*B{1'b0}} ), + .doa ( ), + .dob (mem_do_int ) + ); + + // Data reader. + data_reader + #( + .N (N ), + .B (2*B) + ) + data_reader_i + ( + // Reset and clock. + .rstn (m_axis_aresetn ), + .clk (m_axis_aclk ), + + // Memory I/F. + .mem_en ( ), + .mem_we ( ), + .mem_addr (mem_addrb_int ), + .mem_dout (mem_do_int ), + + // Data out. + .dout (m_axis_tdata ), + .dready (m_axis_tready ), + .dvalid (m_axis_tvalid ), + .dlast (m_axis_tlast ), + + // Registers. + .START_REG (DR_START_REG_resync ), + .ADDR_REG (DR_ADDR_REG ), + .LEN_REG (DR_LEN_REG ) + ); + +endmodule + diff --git a/firmware/ip/axis_weighted_buffer/src/data_reader.vhd b/firmware/ip/axis_weighted_buffer/src/data_reader.vhd new file mode 100644 index 0000000..a566ef5 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/data_reader.vhd @@ -0,0 +1,300 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity data_reader is + Generic + ( + -- Address map of memory. + N : Integer := 8; + -- Data width. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Memory I/F. + mem_en : out std_logic; + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_dout : in std_logic_vector (B-1 downto 0); + + -- Data out. + dout : out std_logic_vector (B-1 downto 0); + dready : in std_logic; + dvalid : out std_logic; + dlast : out std_logic; + + -- Registers. + START_REG : in std_logic; + ADDR_REG : in std_logic_vector (N-1 downto 0); + LEN_REG : in std_logic_vector (N-1 downto 0) + ); +end entity; + +architecture rtl of data_reader is + +constant NPOW : Integer := 2**N; + +-- Fifo to drive AXI Stream Master I/F. +component fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +type fsm_state is ( INIT_ST, + REGS_ST, + READ_ST, + WRITE_ST, + READ_LAST_ST, + WRITE_LAST_ST, + FIFO_ST, + END_ST); +signal current_state, next_state : fsm_state; + +signal init_state : std_logic; +signal regs_state : std_logic; +signal read_state : std_logic; +signal write_state : std_logic; +signal fifo_state : std_logic; +signal read_en : std_logic; + +-- Counter for memory address and samples. +signal cnt : unsigned(N-1 downto 0); +signal addr_cnt : unsigned(N-1 downto 0); + +-- Length register. +signal len_r : unsigned(N-1 downto 0); + +-- Fifo signals. +signal fifo_wr_en : std_logic; +signal fifo_rd_en : std_logic; +signal fifo_din : std_logic_vector (B-1 downto 0); +signal fifo_dout : std_logic_vector (B-1 downto 0); +signal fifo_full : std_logic; +signal fifo_empty : std_logic; + +-- Fifof pipeline. +signal fifo_dout_r : std_logic_vector (B-1 downto 0); +signal fifo_empty_r : std_logic; + +signal mem_dout_r : std_logic_vector (B-1 downto 0); + +signal dlast_i : std_logic; + +begin + +-- Fifo to drive AXI Stream Master I/F. +fifo_i : fifo_axi + Generic map + ( + -- Data width. + B => B , + + -- Fifo depth. + N => 4 + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => fifo_wr_en , + din => fifo_din , + + -- Read I/F. + rd_en => fifo_rd_en , + dout => fifo_dout , + + -- Flags. + full => fifo_full , + empty => fifo_empty + ); + +-- Fifo connections. +fifo_wr_en <= write_state; +fifo_din <= mem_dout_r; +fifo_rd_en <= dready when read_en = '1' else + '0'; + +-- dlast generation. +dlast_i <= fifo_state and fifo_empty; + +process(clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + -- State register. + current_state <= INIT_ST; + + -- Counter for memory address and samples. + cnt <= (others => '0'); + addr_cnt <= (others => '0'); + mem_dout_r <= (others => '0'); + + -- Length register. + len_r <= (others => '0'); + + -- Fifo pipeline. + fifo_dout_r <= (others => '0'); + fifo_empty_r <= '1'; + else + -- State register. + current_state <= next_state; + + -- Memory address and data. + if ( init_state = '1' ) then + mem_dout_r <= (others => '0'); + cnt <= (others => '0'); + addr_cnt <= (others => '0'); + len_r <= (others => '0'); + elsif ( regs_state = '1' ) then + cnt <= (others => '0'); + addr_cnt <= unsigned(ADDR_REG); + len_r <= unsigned(LEN_REG); + elsif ( read_state = '1' ) then + mem_dout_r <= mem_dout; + cnt <= cnt + 1; + addr_cnt <= addr_cnt + 1; + end if; + + -- Fifo pipeline. + if ( dready = '1' ) then + fifo_dout_r <= fifo_dout; + fifo_empty_r <= fifo_empty; + end if; + end if; + end if; +end process; + +-- Next state logic. +process (current_state, START_REG, len_r, cnt, addr_cnt, fifo_full, fifo_empty, dready) +begin + case current_state is + when INIT_ST => + if (START_REG = '0') then + next_state <= INIT_ST; + else + next_state <= REGS_ST; + end if; + + when REGS_ST => + next_state <= READ_ST; + + when READ_ST => + next_state <= WRITE_ST; + + when WRITE_ST => + if ( fifo_full = '1' ) then + next_state <= WRITE_ST; + elsif ( cnt < len_r-1 ) then + next_state <= READ_ST; + else + next_state <= READ_LAST_ST; + end if; + + when READ_LAST_ST => + next_state <= WRITE_LAST_ST; + + when WRITE_LAST_ST => + if ( fifo_full = '1' ) then + next_state <= WRITE_LAST_ST; + else + next_state <= FIFO_ST; + end if; + + when FIFO_ST => + if ( fifo_empty = '1' and dready = '1' ) then + next_state <= END_ST; + else + next_state <= FIFO_ST; + end if; + + when END_ST => + if ( START_REG = '1' ) then + next_state <= END_ST; + else + next_state <= INIT_ST; + end if; + end case; +end process; + +-- Output logic. +process (current_state) +begin +init_state <= '0'; +regs_state <= '0'; +read_state <= '0'; +write_state <= '0'; +fifo_state <= '0'; +read_en <= '0'; + case current_state is + when INIT_ST => + init_state <= '1'; + + when REGS_ST => + regs_state <= '1'; + + when READ_ST => + read_state <= '1'; + read_en <= '1'; + + when WRITE_ST => + write_state <= '1'; + read_en <= '1'; + + when READ_LAST_ST => + read_state <= '1'; + read_en <= '1'; + + when WRITE_LAST_ST => + write_state <= '1'; + read_en <= '1'; + + when FIFO_ST => + fifo_state <= '1'; + read_en <= '1'; + + when END_ST => + + end case; +end process; + +-- Assign outputs. +mem_en <= '1'; +mem_we <= '0'; +mem_addr <= std_logic_vector(addr_cnt); + +dout <= fifo_dout_r; +dvalid <= not(fifo_empty_r); +dlast <= dlast_i; + +end rtl; diff --git a/firmware/ip/axis_weighted_buffer/src/data_writer.vhd b/firmware/ip/axis_weighted_buffer/src/data_writer.vhd new file mode 100644 index 0000000..d7d8046 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/data_writer.vhd @@ -0,0 +1,225 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.MATH_REAL.all; +use IEEE.NUMERIC_STD.all; + +entity data_writer is + generic + ( + -- Number of tables. + NT : integer := 16; + -- Address map of each table. + N : integer := 16; + -- Data width. + B : integer := 16 + ); + port + ( + rstn : in std_logic; + clk : in std_logic; + + -- AXI Stream I/F. + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- Memory I/F. + mem_en : out std_logic_vector (NT-1 downto 0); + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_di : out std_logic_vector (B-1 downto 0); + + -- Registers. + START_ADDR_REG : in std_logic_vector (31 downto 0); + WE_REG : in std_logic + ); +end data_writer; + +architecture rtl of data_writer is + +-- Log2 of number of tables. + constant NT_LOG2 : integer := integer(ceil(log2(real(NT)))); + +-- Synchronizer. + component synchronizer_n is + generic ( + N : integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); + end component; + +-- State machine. + type fsm_state is (INIT_ST, + READ_START_ADDR_ST, + WAIT_TVALID_ST, + RW_TDATA_ST); + signal state : fsm_state; + + signal read_start_addr_state : std_logic; + signal rw_tdata_state : std_logic; + +-- WE_REG_resync. + signal WE_REG_resync : std_logic; + +-- Axis registers. + signal tready_i : std_logic; + signal tready_r : std_logic; + signal tdata_r : std_logic_vector(B-1 downto 0); + signal tdata_rr : std_logic_vector(B-1 downto 0); + signal tdata_rrr : std_logic_vector(B-1 downto 0); + signal tvalid_r : std_logic; + signal tvalid_rr : std_logic; + signal tvalid_rrr : std_logic; + +-- Memory Enable. + signal mem_en_i : std_logic_vector (NT-1 downto 0); + signal mem_en_r : std_logic_vector (NT-1 downto 0); + +-- Memory address space. + signal mem_addr_full : unsigned (NT_LOG2+N-1 downto 0); + signal mem_addr_low : unsigned (NT_LOG2-1 downto 0); + signal mem_addr_high : unsigned (N-1 downto 0); + signal mem_addr_high_r : unsigned (N-1 downto 0); + +begin + +-- WE_REG_resync + WE_REG_resync_i : synchronizer_n + generic map ( + N => 2 + ) + port map ( + rstn => rstn, + clk => clk, + data_in => WE_REG, + data_out => WE_REG_resync + ); + +-- Enable logic generation. + GEN : for I in 0 to NT-1 generate + + mem_en_i(I) <= '1' when mem_addr_low = to_unsigned(I, mem_addr_low'length) else + '0'; + + end generate GEN; + + process (clk) + begin + if (rising_edge(clk)) then + if (rstn = '0') then + -- Axis registers. + tready_r <= '0'; + tdata_r <= (others => '0'); + tdata_rr <= (others => '0'); + tdata_rrr <= (others => '0'); + tvalid_r <= '0'; + tvalid_rr <= '0'; + tvalid_rrr <= '0'; + + -- Memory address. + mem_addr_full <= (others => '0'); + mem_addr_high_r <= (others => '0'); + mem_en_r <= (others => '0'); + + else + -- Axis registers. + tready_r <= tready_i; + tdata_r <= s_axis_tdata; + tvalid_r <= s_axis_tvalid; + + -- Extra registers to account pipe of state machine. + tdata_rr <= tdata_r; + tdata_rrr <= tdata_rr; + tvalid_rr <= tvalid_r; + tvalid_rrr <= tvalid_rr; + + -- Memory address. + if (read_start_addr_state = '1') then + mem_addr_full <= to_unsigned(to_integer(unsigned(START_ADDR_REG)), mem_addr_full'length); + elsif (rw_tdata_state = '1') then + mem_addr_full <= mem_addr_full + 1; + end if; + mem_addr_high_r <= mem_addr_high; + mem_en_r <= mem_en_i; + + end if; + end if; + end process; + +-- Address computation. + mem_addr_low <= mem_addr_full(NT_LOG2-1 downto 0); + mem_addr_high <= mem_addr_full(NT_LOG2+N-1 downto NT_LOG2); + +-- Finite state machine. + process (clk) + begin + if (rising_edge(clk)) then + if (rstn = '0') then + state <= INIT_ST; + else + case state is + when INIT_ST => + if (WE_REG_resync = '1') then + state <= READ_START_ADDR_ST; + end if; + + when READ_START_ADDR_ST => + state <= WAIT_TVALID_ST; + + when WAIT_TVALID_ST => + if (WE_REG_resync = '1') then + if (tvalid_r = '0') then + state <= WAIT_TVALID_ST; + else + state <= RW_TDATA_ST; + end if; + else + state <= INIT_ST; + end if; + + when RW_TDATA_ST => + if (tvalid_r = '0') then + state <= WAIT_TVALID_ST; + end if; + + end case; + end if; + end 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"xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cesel2_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cesel3_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cesel4_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "cesel5_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "sclrd_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclra_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrb_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrconcat_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrc_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrm_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrp_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrsel_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/bin2gray.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/bin2gray.vhd new file mode 100644 index 0000000..4ecc09b --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/bin2gray.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end bin2gray; + +architecture rtl of bin2gray is + +signal gray : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +gray(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + gray(I) <= din(I+1) xor din(I); +end generate; + +-- Assign output. +dout <= gray; + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/bram_dp.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/bram_dp.vhd new file mode 100644 index 0000000..d57aad1 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/bram_dp.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture rtl of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/bram_simple_dp.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/bram_simple_dp.vhd new file mode 100644 index 0000000..1494332 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/bram_simple_dp.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_simple_dp; + +architecture rtl of bram_simple_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (ena = '1') then + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + end if; + end if; +end process; + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/fifo.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/fifo.vhd new file mode 100644 index 0000000..957362b --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/fifo.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture rtl of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Dual port, single clock BRAM. +component bram_simple_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clk : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- FIFO memory. +mem_i : bram_simple_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clk => clk , + ena => '1' , + enb => rd_en , + wea => mem_wea , + addra => std_logic_vector(wptr) , + addrb => std_logic_vector(rptr) , + dia => din , + dob => mem_dob + ); + +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; + +-- Full/empty signals. +full_i <= '1' when wptr = rptr - 1 else + '0'; +empty_i <= '1' when wptr = rptr else + '0'; + +-- wr_clk registers. +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wptr <= (others => '0'); + rptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/fifo_axi.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/fifo_axi.vhd new file mode 100644 index 0000000..e1f76f7 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/fifo_axi.vhd @@ -0,0 +1,147 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_axi; + +architecture rtl of fifo_axi is + +-- FIFO. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- FIFO. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rstn , + clk => clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/fifo_dc.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/fifo_dc.vhd new file mode 100644 index 0000000..c214fae --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/fifo_dc.vhd @@ -0,0 +1,291 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc; + +architecture rtl of fifo_dc is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Binary to gray converter. +component bin2gray is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Gray to binary converter. +component gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Vector synchronizer (only for gray coded). +component synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end component; + +-- Dual port BRAM. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Pointers. +signal wptr : unsigned (N_LOG2-1 downto 0); +signal wptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal wptr_c : std_logic_vector (N_LOG2-1 downto 0); +signal rptr : unsigned (N_LOG2-1 downto 0); +signal rptr_g : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_gc : std_logic_vector (N_LOG2-1 downto 0); +signal rptr_c : std_logic_vector (N_LOG2-1 downto 0); + +-- Memory signals. +signal mem_wea : std_logic; +signal mem_dib : std_logic_vector (B-1 downto 0); +signal mem_doa : std_logic_vector (B-1 downto 0); +signal mem_dob : std_logic_vector (B-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- wptr_i: binary to gray. +wptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(wptr), + dout => wptr_g + ); + +-- wptr_g: write to read domain. +wptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => rd_rstn, + clk => rd_clk, + data_in => wptr_g, + data_out => wptr_gc + ); + +-- wptr_gc_i +wptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => wptr_gc, + dout => wptr_c + ); + +-- rptr_i: binary to gray. +rptr_i : bin2gray + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => std_logic_vector(rptr), + dout => rptr_g + ); + +-- rptr_g: read to write domain. +rptr_g_i : synchronizer_vect + generic map ( + -- Sync stages. + N => 2, + + -- Data width. + B => N_LOG2 + ) + port map ( + rstn => wr_rstn, + clk => wr_clk, + data_in => rptr_g, + data_out => rptr_gc + ); + +-- rptr_gc_i +rptr_gc_i : gray2bin + Generic map + ( + -- Data width. + B => N_LOG2 + ) + Port map + ( + din => rptr_gc, + dout => rptr_c + ); + +-- FIFO memory. +mem_i : bram_dp + Generic map ( + -- Memory address size. + N => N_LOG2, + -- Data width. + B => B + ) + Port map ( + clka => wr_clk, + clkb => rd_clk, + ena => '1', + enb => rd_en, + wea => mem_wea, + web => '0', + addra => std_logic_vector(wptr), + addrb => std_logic_vector(rptr), + dia => din, + dib => mem_dib, + doa => mem_doa, + dob => mem_dob + ); +-- Memory connections. +mem_wea <= wr_en when full_i = '0' else + '0'; +mem_dib <= (others => '0'); + +-- Full/empty signals. +full_i <= '1' when wptr = unsigned(rptr_c) - 1 else + '0'; +empty_i <= '1' when unsigned(wptr_c) = rptr else + '0'; + +-- wr_clk registers. +process (wr_clk) +begin + if ( rising_edge(wr_clk) ) then + if ( wr_rstn = '0' ) then + wptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + + -- Increment pointer. + wptr <= wptr + 1; + end if; + end if; + end if; +end process; + +-- rd_clk registers. +process (rd_clk) +begin + if ( rising_edge(rd_clk) ) then + if ( rd_rstn = '0' ) then + rptr <= (others => '0'); + else + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Read data. + + -- Increment pointer. + rptr <= rptr + 1; + end if; + end if; + end if; +end process; + +-- Assign outputs. +dout <= mem_dob; +full <= full_i; +empty <= empty_i; + +end rtl; diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/fifo_dc_axi.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/fifo_dc_axi.vhd new file mode 100644 index 0000000..eb83d1a --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/fifo_dc_axi.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity fifo_dc_axi is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo_dc_axi; + +architecture rtl of fifo_dc_axi is + +-- Dual-clock FIFO. +component fifo_dc is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + wr_rstn : in std_logic; + wr_clk : in std_logic; + + rd_rstn : in std_logic; + rd_clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- FIFO read to AXI adapter. +component rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end component; + +signal rd_en_i : std_logic; +signal dout_i : std_logic_vector (B-1 downto 0); +signal empty_i : std_logic; + +begin + +-- Dual-clock FIFO. +fifo_i : fifo_dc + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => N + ) + Port map + ( + wr_rstn => wr_rstn , + wr_clk => wr_clk , + + rd_rstn => rd_rstn , + rd_clk => rd_clk , + + -- Write I/F. + wr_en => wr_en , + din => din , + + -- Read I/F. + rd_en => rd_en_i , + dout => dout_i , + + -- Flags. + full => full , + empty => empty_i + ); + +-- FIFO read to AXI adapter. +rd2axi_i : rd2axi + Generic map + ( + -- Data width. + B => B + ) + Port map + ( + rstn => rd_rstn , + clk => rd_clk , + + -- FIFO Read I/F. + fifo_rd_en => rd_en_i , + fifo_dout => dout_i , + fifo_empty => empty_i , + + -- Read I/F. + rd_en => rd_en , + dout => dout , + empty => empty + ); + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/gray2bin.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/gray2bin.vhd new file mode 100644 index 0000000..e23f8af --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/gray2bin.vhd @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gray2bin is + Generic + ( + -- Data width. + B : Integer := 8 + ); + Port + ( + din : in std_logic_vector (B-1 downto 0); + dout: out std_logic_vector (B-1 downto 0) + ); +end gray2bin; + +architecture rtl of gray2bin is + +signal bin : std_logic_vector (B-1 downto 0); + +begin + +-- MSB always match. +bin(B-1) <= din(B-1); + +GEN: for I in 0 to B-2 generate +begin + bin(I) <= bin(I+1) xor din(I); +end generate GEN; + +-- Assign output. +dout <= bin; + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/rd2axi.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/rd2axi.vhd new file mode 100644 index 0000000..babadc6 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/rd2axi.vhd @@ -0,0 +1,138 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity rd2axi is + Generic + ( + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- FIFO Read I/F. + fifo_rd_en : out std_logic; + fifo_dout : in std_logic_vector (B-1 downto 0); + fifo_empty : in std_logic; + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + empty : out std_logic + ); +end rd2axi; + +architecture rtl of rd2axi is + +type fsm_state is ( WAIT_EMPTY_ST, + READ_FIRST_ST, + READ_ST, + READ_LAST_ST); +signal current_state, next_state : fsm_state; + +signal wait_empty_state : std_logic; +signal read_first_state : std_logic; +signal read_state : std_logic; + +signal fifo_rd_en_i : std_logic; +signal empty_i : std_logic; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + current_state <= WAIT_EMPTY_ST; + else + current_state <= next_state; + end if; + end if; +end process; + +-- Next state logic. +process(current_state, fifo_empty, rd_en) +begin + case current_state is + when WAIT_EMPTY_ST => + if (fifo_empty = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_FIRST_ST; + end if; + + when READ_FIRST_ST => + next_state <= READ_ST; + + when READ_ST => + if (fifo_empty = '0') then + next_state <= READ_ST; + else + if (rd_en = '1') then + next_state <= WAIT_EMPTY_ST; + else + next_state <= READ_LAST_ST; + end if; + end if; + + when READ_LAST_ST => + if (rd_en = '0') then + next_state <= READ_LAST_ST; + else + next_state <= WAIT_EMPTY_ST; + end if; + + end case; +end process; + +-- Output logic. +process(current_state) +begin +wait_empty_state <= '0'; +read_first_state <= '0'; +read_state <= '0'; +empty_i <= '0'; + case current_state is + when WAIT_EMPTY_ST => + wait_empty_state <= '1'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '1'; + + when READ_FIRST_ST => + wait_empty_state <= '0'; + read_first_state <= '1'; + read_state <= '0'; + empty_i <= '1'; + + when READ_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '1'; + empty_i <= '0'; + + when READ_LAST_ST => + wait_empty_state <= '0'; + read_first_state <= '0'; + read_state <= '0'; + empty_i <= '0'; + + end case; +end process; + +-- FIFO Read enable signal. +fifo_rd_en_i <= read_first_state or (read_state and rd_en); + +-- Assign outputs. +fifo_rd_en <= fifo_rd_en_i; +-- TODO: add register to freeze last value. +dout <= fifo_dout when empty_i = '0' else + (others => '0'); +empty <= empty_i; + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/fifo/synchronizer_vect.vhd b/firmware/ip/axis_weighted_buffer/src/fifo/synchronizer_vect.vhd new file mode 100644 index 0000000..2fbb696 --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/fifo/synchronizer_vect.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This block is intended to use to sync gray coded vectors. + +-- NOTE: Do not use with generic vector data, as it may result +-- in corrupted re-sync data. + +entity synchronizer_vect is + generic ( + -- Sync stages. + N : Integer := 2; + + -- Data width. + B : Integer := 8 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic_vector (B-1 downto 0); + data_out : out std_logic_vector (B-1 downto 0) + ); +end synchronizer_vect; + +architecture rtl of synchronizer_vect is + +-- Internal register. +type reg_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal data_int_reg : reg_t; + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => (others => '0')); -- 1 FF. + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/matched_filter.vhd b/firmware/ip/axis_weighted_buffer/src/matched_filter.vhd new file mode 100644 index 0000000..e937f5e --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/matched_filter.vhd @@ -0,0 +1,277 @@ +------------------------------------------------------------------------------- +-- Title : Matched Filter Time-Domain Multiplier +-- Project : +------------------------------------------------------------------------------- +-- File : matched_filter.vhd +-- Author : +-- Company : +-- Created : 2025-02-27 +-- Last update: 2025-03-03 +-- Platform : +-- Standard : VHDL'08 +------------------------------------------------------------------------------- +-- Description: Stores filter envelope and processes DSP +-- Inputs are single precision (B), outputs double (2*B) +------------------------------------------------------------------------------- +-- Copyright (c) 2025 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2025-02-27 1.0 javierc Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity matched_filter is + generic ( + B : natural := 16; + N : natural := 10 + ); + port ( + -- clock+reset for readout data path + clk : in std_logic; + + -- clock+reset for writing weights + write_rstn : in std_logic; + write_clk : in std_logic; + + trigger_i : in std_logic; + trigger_o : out std_logic; + + -- AXIS programming interface from DMA + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(2*B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- Input and output readout streams + din_valid_i : in std_logic; + din_i : in std_logic_vector(2*B-1 downto 0); + dout_o : out std_logic_vector(2*B-1 downto 0); + dout_valid_o : out std_logic; + + -- Configuration registers + -- active length of the weights buffer (how many samples of incoming data will be weighted) + LEN_REG : in std_logic_vector (31 downto 0); + -- data writer start address and write-enable + DW_ADDR_REG : in std_logic_vector(31 downto 0); + WE_REG : in std_logic + ); +end matched_filter; + +architecture rtl of matched_filter is + signal mem_envelope_wea, mem_envelope_ena : std_logic := '0'; + signal mem_envelope_addra : std_logic_vector(N-1 downto 0); + signal mem_envelope_addrb : std_logic_vector(31 downto 0); + signal mem_envelope_dia : std_logic_vector(2*B-1 downto 0); + signal envelope_iq : std_logic_vector(2*B-1 downto 0); + signal envelope_ii, envelope_qq : std_logic_vector (B-1 downto 0); + + signal ac, bd, ad, bc : std_logic_vector(47 downto 0); + signal ac_signed, bd_signed, ad_signed, bc_signed : signed(2*B-1 downto 0); + + signal din_ii, din_qq : std_logic_vector(B-1 downto 0); + signal filt_ii, filt_qq : std_logic_vector(2*B-1 downto 0); + signal filt_ii_quant, filt_qq_quant : std_logic_vector(B-1 downto 0); + signal filt_ii_quant_r, filt_qq_quant_r : std_logic_vector(B-1 downto 0); + + -- Higher precision + signal dfiltered_ii, dfiltered_qq : std_logic_vector (2*N-1 downto 0); + + -- Compensate memory latency for data + constant WGT_LATENCY : natural := 3; + -- Compensate DSP latency for trigger & valid + constant DSP_LATENCY : natural := 3; + + type reg_t is array (WGT_LATENCY-1 downto 0) of std_logic_vector (2*B-1 downto 0); + signal din_reg : reg_t; + + signal trigger_reg : std_logic_vector(0 to WGT_LATENCY+DSP_LATENCY-1); + signal dout_valid_reg : std_logic_vector(0 to WGT_LATENCY+DSP_LATENCY-1); + + -- Read address + signal cnt : unsigned (31 downto 0) := to_unsigned(0, 32); + signal length : unsigned (31 downto 0) := to_unsigned(0, 32); + + type fsm_state is (INIT_ST, + WAIT_ST, + READ_ST); + signal state : fsm_state; + + component dsp_macro_0 + port ( + CLK : in std_logic; + CE : in std_logic; + A : in std_logic_vector(B-1 downto 0); + B : in std_logic_vector(B-1 downto 0); + C : in std_logic_vector(47 downto 0); + P : out std_logic_vector(47 downto 0) + ); + end component; +begin + + data_writer_i : entity work.data_writer + generic map ( + NT => 1, + N => N, + B => 2*B) + port map ( + rstn => write_rstn, + clk => write_clk, + s_axis_tready => s_axis_tready, + s_axis_tdata => s_axis_tdata, + s_axis_tvalid => s_axis_tvalid, + mem_en(0) => mem_envelope_ena, + mem_we => mem_envelope_wea, + mem_addr => mem_envelope_addra, + mem_di => mem_envelope_dia, + START_ADDR_REG => DW_ADDR_REG, + WE_REG => WE_REG); + + bram_envelope_iq : entity work.bram_dp + generic map ( + N => N, + B => 2*B) + port map ( + clka => write_clk, + clkb => clk, + ena => '1', + enb => '1', + wea => mem_envelope_wea, + web => '0', + addra => mem_envelope_addra, + addrb => mem_envelope_addrb(N-1 downto 0), + dia => mem_envelope_dia, + dib => (others => '0'), + doa => open, + dob => envelope_iq); + + + matched_filter_mult_ac : dsp_macro_0 + port map ( + CLK => clk, + CE => '1', + A => din_ii, + B => envelope_ii, + C => (others => '0'), + P => ac + ); + + matched_filter_mult_bd : dsp_macro_0 + port map ( + CLK => clk, + CE => '1', + A => din_qq, + B => envelope_qq, + C => (others => '0'), + P => bd + ); + + matched_filter_mult_ad : dsp_macro_0 + port map ( + CLK => clk, + CE => '1', + A => din_ii, + B => envelope_qq, + C => (others => '0'), + P => ad + ); + + matched_filter_mult_bc : dsp_macro_0 + port map ( + CLK => clk, + CE => '1', + A => din_qq, + B => envelope_ii, + C => (others => '0'), + P => bc + ); + + latency_compensation : process (clk) is + variable i : integer; + begin + if (rising_edge(clk)) then + din_reg(0) <= din_i; + trigger_reg(0) <= trigger_i; + dout_valid_reg(0) <= din_valid_i; + for i in 1 to WGT_LATENCY-1 loop + din_reg(i) <= din_reg(i-1); + end loop; + for i in 1 to WGT_LATENCY+DSP_LATENCY-1 loop + trigger_reg(i) <= trigger_reg(i-1); + dout_valid_reg(i) <= dout_valid_reg(i-1); + end loop; + end if; + end process; + + proc_read_addr : process(clk) is + begin + if (rising_edge(clk)) then + if (state = READ_ST) then + if (din_valid_i = '1') then + cnt <= cnt + 1; + end if; + else + cnt <= to_unsigned(0, 32); + end if; + end if; + end process; + + proc_state : process (clk) is + begin + if (rising_edge(clk)) then + case state is + when INIT_ST => + state <= WAIT_ST; + when WAIT_ST => + if (trigger_i = '1') then + state <= READ_ST; + end if; + + when READ_ST => + if (cnt > length) then + state <= INIT_ST; + end if; + end case; + end if; + end process; + + reg_output : process(clk) is + begin + if (rising_edge(clk)) then + filt_ii_quant_r <= filt_ii_quant; + filt_qq_quant_r <= filt_qq_quant; + end if; + end process; + + din_ii <= din_reg(WGT_LATENCY-1)(2*B-1 downto B); + din_qq <= din_reg(WGT_LATENCY-1)(B-1 downto 0); + + trigger_o <= trigger_reg(WGT_LATENCY+DSP_LATENCY - 1); + dout_valid_o <= dout_valid_reg(WGT_LATENCY+DSP_LATENCY - 1); + + mem_envelope_addrb <= std_logic_vector(cnt); + envelope_ii <= envelope_iq(2*B-1 downto B); + envelope_qq <= envelope_iq(B-1 downto 0); + + + ac_signed <= signed(ac(2*B-1 downto 0)); + bd_signed <= signed(bd(2*B-1 downto 0)); + ad_signed <= signed(ad(2*B-1 downto 0)); + bc_signed <= signed(bc(2*B-1 downto 0)); + + filt_ii <= std_logic_vector(ac_signed - bd_signed); + filt_qq <= std_logic_vector(ad_signed + bc_signed); + + -- Keep only MSBs + filt_ii_quant <= filt_ii(2*B-1 downto B); + filt_qq_quant <= filt_qq(2*B-1 downto B); + + dout_o(2*B-1 downto B) <= filt_ii_quant_r; + dout_o(B-1 downto 0) <= filt_qq_quant_r; + + length <= unsigned(LEN_REG); + + +end rtl; diff --git a/firmware/ip/axis_weighted_buffer/src/outreg.sv b/firmware/ip/axis_weighted_buffer/src/outreg.sv new file mode 100644 index 0000000..d35357a --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/outreg.sv @@ -0,0 +1,113 @@ +// Data is I,Q. +// I: lower B bits. +// Q: upper B bits. +module outreg ( + // Reset and clock. + rstn , + clk , + + // Data input. + wen , + din , + + // M_AXIS. + m_axis_tdata , + m_axis_tready , + m_axis_tvalid + ); + +//////////////// +// Parameters // +//////////////// +// Number of bits. +parameter B = 16; + +/////////// +// Ports // +/////////// +input rstn; +input clk; + +input wen; +input [B-1:0] din; + +output [B-1:0] m_axis_tdata; +input m_axis_tready; +output m_axis_tvalid; + +////////////////////// +// Internal signals // +////////////////////// +// States. +typedef enum { WAIT_IN_ST , + READ_IN_ST , + WRITE_OUT_ST + } state_t; + +// State register. +(* fsm_encoding = "one_hot" *) state_t state; + +// Data register. +reg [B-1:0] din_r; + +reg din_en_i; +reg valid_i; + +////////////////// +// Architecture // +////////////////// + +// Registers. +always @(posedge clk) begin + if (~rstn) begin + // State register. + state <= WAIT_IN_ST; + + // Data register. + din_r <= 0; + end + else begin + // State register. + case (state) + WAIT_IN_ST: + if ( wen == 1'b1) + state <= READ_IN_ST; + + READ_IN_ST: + if ( wen == 1'b0 ) + state <= WRITE_OUT_ST; + + WRITE_OUT_ST: + if ( m_axis_tready == 1'b1 ) + state <= WAIT_IN_ST; + endcase + + // Data register. + if (din_en_i == 1'b1) + din_r <= din; + end +end + +// FSM outputs. +always_comb begin + // Default. + din_en_i = 0; + valid_i = 0; + + case (state) + //WAIT_IN_ST: + + READ_IN_ST: + din_en_i = 1'b1; + + WRITE_OUT_ST: + valid_i = 1'b1; + endcase +end + +// Assign outputs. +assign m_axis_tdata = din_r; +assign m_axis_tvalid = valid_i; + +endmodule + diff --git a/firmware/ip/axis_weighted_buffer/src/synchronizer_n.vhd b/firmware/ip/axis_weighted_buffer/src/synchronizer_n.vhd new file mode 100644 index 0000000..925425d --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/synchronizer_n.vhd @@ -0,0 +1,42 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library common_lib; +use common_lib.all; + +entity synchronizer_n is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end synchronizer_n; + +architecture rtl of synchronizer_n is + +-- Internal register. +signal data_int_reg : std_logic_vector (N-1 downto 0); + +begin + +process(clk) +begin + if (rising_edge(clk)) then + if (rstn = '0') then + data_int_reg <= (others => '0'); + else + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/axis_weighted_buffer/src/tb/data_iq.txt b/firmware/ip/axis_weighted_buffer/src/tb/data_iq.txt new file mode 100644 index 0000000..301691a --- /dev/null +++ b/firmware/ip/axis_weighted_buffer/src/tb/data_iq.txt @@ -0,0 +1,10000 @@ +16392,0 +3219,0 +-15142,0 +-9091,0 +11604,0 +13648,0 +-6276,0 +-16068,0 +11,0 +16054,0 +6273,0 +-13649,0 +-11616,0 +9106,0 +15132,0 +-3192,0 +-16399,0 +-3234,0 +15152,0 +9107,0 +-11593,0 +-13656,0 +6261,0 +16068,0 +-33,0 +-16070,0 +-6267,0 +13617,0 +11569,0 +-9125,0 +-15134,0 +3218,0 +16370,0 +3175,0 +-15157,0 +-9123,0 +11589,0 +13654,0 +-6280,0 +-16043,0 +-18,0 +16062,0 +6261,0 +-13626,0 +-11596,0 +9094,0 +15131,0 +-3187,0 +-16385,0 +-3199,0 +15154,0 +9090,0 +-11588,0 +-13611,0 +6289,0 +16084,0 +14,0 +-16091,0 +-6292,0 +13607,0 +11584,0 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axi_mst_0_pkg::*; + +module tb(); + + localparam N_AVG = 16; + localparam N_BUF = 16; + localparam B = 16; + + // s_axi interfase. + reg s_axi_aclk; + reg s_axi_aresetn; + wire [5:0] s_axi_araddr; + wire [2:0] s_axi_arprot; + wire s_axi_arready; + wire s_axi_arvalid; + wire [5:0] s_axi_awaddr; + wire [2:0] s_axi_awprot; + wire s_axi_awready; + wire s_axi_awvalid; + wire s_axi_bready; + wire [1:0] s_axi_bresp; + wire s_axi_bvalid; + wire [31:0] s_axi_rdata; + wire s_axi_rready; + wire [1:0] s_axi_rresp; + wire s_axi_rvalid; + wire [31:0] s_axi_wdata; + wire s_axi_wready; + wire [3:0] s_axi_wstrb; + wire s_axi_wvalid; + + reg trigger; + + + reg s_axis_aclk; + reg s_axis_aresetn; + reg s_axis_tvalid; + wire s_axis_tready; + reg [2*B-1:0] s_axis_tdata; + + // From DMA + reg s1_axis_tvalid; + wire s1_axis_tready; + reg [2*B-1:0] s1_axis_tdata; + + reg m_axis_aclk; + reg m_axis_aresetn; + + wire m0_axis_tvalid; + reg m0_axis_tready; + wire [4*B-1:0] m0_axis_tdata; + wire m0_axis_tlast; + + wire m1_axis_tvalid; + reg m1_axis_tready; + wire [2*B-1:0] m1_axis_tdata; + wire m1_axis_tlast; + + wire m2_axis_tvalid; + reg m2_axis_tready; + wire [4*B-1:0] m2_axis_tdata; + + // AXI VIP master address. + xil_axi_ulong avg_start_reg = 0; + xil_axi_ulong avg_addr_reg = 1; + xil_axi_ulong avg_len_reg = 2; + xil_axi_ulong avg_dr_start_reg = 3; + xil_axi_ulong avg_dr_addr_reg = 4; + xil_axi_ulong avg_dr_len_reg = 5; + xil_axi_ulong buf_start_reg = 6; + xil_axi_ulong buf_addr_reg = 7; + xil_axi_ulong buf_len_reg = 8; + xil_axi_ulong buf_dr_start_reg = 9; + xil_axi_ulong buf_dr_addr_reg = 10; + xil_axi_ulong buf_dr_len_reg = 11; + xil_axi_ulong filter_start_addr_reg = 15; + + xil_axi_prot_t prot = 0; + reg[31:0] data_wr = 32'h12345678; + reg[31:0] data; + xil_axi_resp_t resp; + + // Test bench control. + reg tb_load_mem = 0; + reg tb_load_mem_done = 0; + reg tb_input = 0; + reg tb_input_done = 0; + + // axi_mst_0. + axi_mst_0 axi_mst_0_i + ( + .aclk (s_axi_aclk ), + .aresetn (s_axi_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + + axis_weighted_buffer + # + ( + .N_AVG (N_AVG ), + .N_BUF (N_BUF ), + .B (B ) + ) + DUT + ( + // AXI Slave I/F for configuration. + .s_axi_aclk (s_axi_aclk ), + .s_axi_aresetn (s_axi_aresetn ), + .s_axi_araddr (s_axi_araddr ), + .s_axi_arprot (s_axi_arprot ), + .s_axi_arready (s_axi_arready ), + .s_axi_arvalid (s_axi_arvalid ), + .s_axi_awaddr (s_axi_awaddr ), + .s_axi_awprot (s_axi_awprot ), + .s_axi_awready (s_axi_awready ), + .s_axi_awvalid (s_axi_awvalid ), + .s_axi_bready (s_axi_bready ), + .s_axi_bresp (s_axi_bresp ), + .s_axi_bvalid (s_axi_bvalid ), + .s_axi_rdata (s_axi_rdata ), + .s_axi_rready (s_axi_rready ), + .s_axi_rresp (s_axi_rresp ), + .s_axi_rvalid (s_axi_rvalid ), + .s_axi_wdata (s_axi_wdata ), + .s_axi_wready (s_axi_wready ), + .s_axi_wstrb (s_axi_wstrb ), + .s_axi_wvalid (s_axi_wvalid ), + + // Trigger input. + .trigger (trigger ), + + // AXIS Slave for input data. + .s_axis_aclk (s_axis_aclk ), + .s_axis_aresetn (s_axis_aresetn ), + .s_axis_tvalid (s_axis_tvalid ), + .s_axis_tready (s_axis_tready ), + .s_axis_tdata (s_axis_tdata ), + + // AXIS Slave for memory programming + .s1_axis_tvalid(s1_axis_tvalid), + .s1_axis_tdata(s1_axis_tdata), + .s1_axis_tready(s1_axis_tready), + + + // Reset and clock for m0 and m1. + .m_axis_aclk (m_axis_aclk ), + .m_axis_aresetn (m_axis_aresetn ), + + // AXIS Master for averaged output. + .m0_axis_tvalid (m0_axis_tvalid ), + .m0_axis_tready (m0_axis_tready ), + .m0_axis_tdata (m0_axis_tdata ), + .m0_axis_tlast (m0_axis_tlast ), + + // AXIS Master for raw output. + .m1_axis_tvalid (m1_axis_tvalid ), + .m1_axis_tready (m1_axis_tready ), + .m1_axis_tdata (m1_axis_tdata ), + .m1_axis_tlast (m1_axis_tlast ), + + // AXIS Master for register output. + .m2_axis_tvalid (m2_axis_tvalid ), + .m2_axis_tready (m2_axis_tready ), + .m2_axis_tdata (m2_axis_tdata ) + ); + + // VIP Agents + axi_mst_0_mst_t axi_mst_0_agent; + + // Main TB Control. + initial begin + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb.axi_mst_0_i.inst.IF); + + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + + // Start agents. + axi_mst_0_agent.start_master(); + + // Reset sequence. + s_axi_aresetn <= 0; + s_axis_aresetn <= 0; + m_axis_aresetn <= 0; + m0_axis_tready <= 1; + m1_axis_tready <= 1; + m2_axis_tready <= 1; + trigger <= 0; + #500; + s_axi_aresetn <= 1; + s_axis_aresetn <= 1; + m_axis_aresetn <= 1; + + #1000; + + $display("##############"); + $display("### Test 0 ###"); + $display("##############"); + $display("t = %0t", $time); + // Average/buffer: + // * addr = 0. + // * len = 1280. + + // avg_addr_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_addr_reg, prot, data_wr, resp); + #10; + + // avg_len_reg + data_wr = 1800; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_len_reg, prot, data_wr, resp); + #10; + + // buf_addr_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_addr_reg, prot, data_wr, resp); + #10; + + // buf_len_reg + data_wr = 1280; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_len_reg, prot, data_wr, resp); + #10; + + // {filter_we_reg, avg_start_reg} + data_wr = 3; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_start_reg, prot, data_wr, resp); + #10; + + // buf_start_reg + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_start_reg, prot, data_wr, resp); + #10; + + // filter_start_addr_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*filter_start_addr_reg, prot, data_wr, resp); + #10; + + tb_load_mem <= 1; + + wait (tb_load_mem_done); + + + // Start sending input data. + tb_input <= 1; + + trigger_gen(5,4*1280); + + wait (tb_input_done); + + tb_input <= 0; + + // avg_start_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_start_reg, prot, data_wr, resp); + #10; + + // buf_start_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_start_reg, prot, data_wr, resp); + #10; + + // Average DR. + // * addr = 0. + // * len = 10; + + // avg_dr_addr_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_dr_addr_reg, prot, data_wr, resp); + #10; + + // avg_dr_len_reg + data_wr = 10; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_dr_len_reg, prot, data_wr, resp); + #10; + + // avg_dr_start_reg + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_dr_start_reg, prot, data_wr, resp); + #10; + + // avg_dr_start_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*avg_dr_start_reg, prot, data_wr, resp); + #10; + + #100; + + // Buffer DR. + // * addr = 0. + // * len = 1280*5 = 6400, I use 7000; + + // buf_dr_addr_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_dr_addr_reg, prot, data_wr, resp); + #10; + + // buf_dr_len_reg + data_wr = 7000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_dr_len_reg, prot, data_wr, resp); + #10; + + // buf_dr_start_reg + data_wr = 1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_dr_start_reg, prot, data_wr, resp); + #10; + + // buf_dr_start_reg + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(4*buf_dr_start_reg, prot, data_wr, resp); + #10; + + #20000; + end + + + // Load data into memroy. + initial begin + int fd,vali,valq; + bit signed [15:0] ii,qq; + + s1_axis_tvalid <= 0; + s1_axis_tdata <= 0; + + wait (tb_load_mem); + + fd = $fopen("../../../../../src/tb/gauss.txt","r"); + + wait (s1_axis_tready); + + while($fscanf(fd,"%d,%d", valq,vali) == 2) begin + $display("I,Q: %d, %d", vali,valq); + ii = vali; + qq = valq; + @(posedge s_axis_aclk); + s1_axis_tvalid <= 1; + s1_axis_tdata <= {qq,ii}; + end + + @(posedge s_axis_aclk); + s1_axis_tvalid <= 0; + + $fclose(fd); + tb_load_mem_done <= 1; + + end + + // Input data. + initial begin + int fd; + int vali, valq; + + s_axis_tvalid <= 0; + s_axis_tdata <= 0; + tb_input_done <= 0; + + wait (tb_input); + + fd = $fopen("../../../../../src/tb/data_iq.txt","r"); + + while ($fscanf(fd,"%d,%d", vali, valq) == 2) begin + $display("Time %t: I = %d, Q = %d", $time, vali, valq); + @(posedge s_axis_aclk); + s_axis_tvalid <= 1; + s_axis_tdata[0 +: 16] <= vali; + s_axis_tdata[16 +: 16] <= valq; + @(posedge s_axis_aclk); + s_axis_tvalid <= 0; + @(posedge s_axis_aclk); + @(posedge s_axis_aclk); + end + + @(posedge s_axis_aclk); + s_axis_tvalid <= 0; + tb_input_done <= 1; + + end + + // s_axi_aclk. + always begin + s_axi_aclk <= 0; + #10; + s_axi_aclk <= 1; + #10; + end + + // s_axis_aclk. + always begin + s_axis_aclk <= 0; + #7; + s_axis_aclk <= 1; + #7; + end + + // m_axis_aclk. + always begin + m_axis_aclk <= 0; + #3; + m_axis_aclk <= 1; + #3; + end + + task trigger_gen (input int cnt, input int waitc); + for (int i=0; i + + user.org + user + mr_buffer_et + 1.1 + + + m00_axis + + + + + + + TDATA + + + m00_axis_tdata + + + + + TSTRB + + + m00_axis_tstrb + + + + + TLAST + + + m00_axis_tlast + + + + + TVALID + + + m00_axis_tvalid + + + + + TREADY + + + m00_axis_tready + + + + + + s00_axis + + + + + + + TDATA + + + s00_axis_tdata + + + + + TSTRB + + + s00_axis_tstrb + + + + + TLAST + + + s00_axis_tlast + + + + + TVALID + + + s00_axis_tvalid + + + + + TREADY + + + s00_axis_tready + + + + + + s00_axi + + + + + + + + + AWADDR + + + s00_axi_awaddr + + + + + AWPROT + + + s00_axi_awprot + + + + + AWVALID + + + s00_axi_awvalid + + + + + AWREADY + + + s00_axi_awready + + + + + WDATA + + + s00_axi_wdata + + + + + WSTRB + + + s00_axi_wstrb + + + + + WVALID + + + s00_axi_wvalid + + + + + WREADY + + + s00_axi_wready + + + + + BRESP + + + s00_axi_bresp + + + + + BVALID + + + s00_axi_bvalid + + + + + BREADY + + + s00_axi_bready + + + + + ARADDR + + + s00_axi_araddr + + + + + ARPROT + + + s00_axi_arprot + + + + + ARVALID + + + s00_axi_arvalid + + + + + ARREADY + + + s00_axi_arready + + + + + RDATA + + + s00_axi_rdata + + + + + RRESP + + + s00_axi_rresp + + + + + RVALID + + + s00_axi_rvalid + + + + + RREADY + + + s00_axi_rready + + + + + + m00_axis_aresetn + + + + + + + RST + + + m00_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s00_axi_aresetn + + + + + + + RST + + + s00_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s00_axis_aresetn + + + + + + + RST + + + s00_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m00_axis_aclk + + + + + + + CLK + + + m00_axis_aclk + + + + + + ASSOCIATED_BUSIF + m00_axis + + + ASSOCIATED_RESET + m00_axis_aresetn + + + + + s00_axi_aclk + + + + + + + CLK + + + s00_axi_aclk + + + + + + ASSOCIATED_BUSIF + s00_axi + + + ASSOCIATED_RESET + s00_axi_aresetn + + + + + s00_axis_aclk + + + + + + + CLK + + + s00_axis_aclk + + + + + + ASSOCIATED_BUSIF + s00_axis + + + ASSOCIATED_RESET + s00_axis_aresetn + + + + + + + s00_axi + + reg0 + 0 + 4096 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + mr_buffer_v1_0 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + f1b39ed6 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + mr_buffer_v1_0 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + f1b39ed6 + + + + + xilinx_testbench + Test Bench + :vivado.xilinx.com:simulation.testbench + tb + + xilinx_testbench_view_fileset + + + + viewChecksum + bd3e64f2 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 5c442cfe + + + + + + + trigger + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s00_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axis_tdata + + in + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axis_tstrb + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s00_axis_tlast + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s00_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tdata + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tstrb + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_dbg_probe + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + m_dbg_probe + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + + + NM + Nm + 8 + + + N + N + 8 + + + B + B + 16 + + + C_S00_AXI_DATA_WIDTH + C S00 Axi Data Width + 32 + + + C_S00_AXI_ADDR_WIDTH + C S00 Axi Addr Width + 6 + + + DEBUG + Debug + 0 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/bram_dp.vhd + vhdlSource + + + src/data_reader.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/fifo.vhd + vhdlSource + + + src/mr_buffer.vhd + vhdlSource + + + src/mr_buffer_v1_0_S00_AXI.vhd + vhdlSource + + + src/synchronizer.vhd + vhdlSource + + + src/mr_buffer_v1_0.vhd + vhdlSource + CHECKSUM_0a79e04f + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/bram_dp.vhd + vhdlSource + + + src/data_reader.vhd + vhdlSource + + + src/data_writer.vhd + vhdlSource + + + src/fifo.vhd + vhdlSource + + + src/mr_buffer.vhd + vhdlSource + + + src/mr_buffer_v1_0_S00_AXI.vhd + vhdlSource + + + src/synchronizer.vhd + vhdlSource + + + src/mr_buffer_v1_0.vhd + vhdlSource + + + + xilinx_testbench_view_fileset + + src/tb/tb.sv + systemVerilogSource + USED_IN_simulation + USED_IN_testbench + + + src/tb/tb_behav_waves.wcfg + unknown + USED_IN_simulation + USED_IN_testbench + + + src/tb/axi4stream_vip_0/axi4stream_vip_0.xci + xci + + + src/tb/axi_vip_0/axi_vip_0.xci + xci + + + src/tb/axi4stream_vip_1/axi4stream_vip_1.xci + xci + + + + xilinx_xpgui_view_fileset + + xgui/mr_buffer_et_v1_1.tcl + tclSource + CHECKSUM_5c442cfe + XGUI_VERSION_2 + + + + Multi-Rate Buffer with External Trigger. + + + NM + Nm + 8 + + + N + N + 8 + + + B + B + 16 + + + C_S00_AXI_DATA_WIDTH + C S00 Axi Data Width + 32 + + + C_S00_AXI_ADDR_WIDTH + C S00 Axi Addr Width + 6 + + + Component_Name + mr_buffer_v1_0_v1_0 + + + DEBUG + Debug + 0 + + + + + + zynquplus + + + /UserIP + + Multi-Rate Buffer ET + package_project + 1 + + user.org:user:mr_buffer_et:1.0 + + 2025-05-30T20:00:48Z + + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + /home/lstefana/v18.3/ip-git/mr_buffer_et + + + + 2023.1 + + + + + + + + + diff --git a/firmware/ip/mr_buffer_et/src/bram_dp.vhd b/firmware/ip/mr_buffer_et/src/bram_dp.vhd new file mode 100644 index 0000000..86df6ac --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/bram_dp.vhd @@ -0,0 +1,88 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04/02/2019 09:12:29 AM +-- Design Name: +-- Module Name: bram_dp - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end bram_dp; + +architecture Behavioral of bram_dp is + +-- Ram type. +type ram_type is array (2**N-1 downto 0) of std_logic_vector (B-1 downto 0); +shared variable RAM : ram_type; + +begin + +-- CLKA port. +process (clka) +begin + if (clka'event and clka = '1') then + if (ena = '1') then + doa <= RAM(conv_integer(addra)); + if (wea = '1') then + RAM(conv_integer(addra)) := dia; + end if; + end if; + end if; +end process; + +-- CLKB port. +process (clkb) +begin + if (clkb'event and clkb = '1') then + if (enb = '1') then + dob <= RAM(conv_integer(addrb)); + if (web = '1') then + RAM(conv_integer(addrb)) := dib; + end if; + end if; + end if; +end process; + +end Behavioral; diff --git a/firmware/ip/mr_buffer_et/src/data_reader.vhd b/firmware/ip/mr_buffer_et/src/data_reader.vhd new file mode 100644 index 0000000..154da8e --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/data_reader.vhd @@ -0,0 +1,338 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/26/2019 12:08:45 PM +-- Design Name: +-- Module Name: data_reader - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity data_reader is + Generic + ( + -- Number of memories. + NM : Integer := 8; + -- Address map of each memory. + N : Integer := 8; + -- Data width. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Memory I/F. + mem_en : out std_logic; + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_dout : in std_logic_vector (NM*B-1 downto 0); + + -- Data out. + dout : out std_logic_vector (B-1 downto 0); + dready : in std_logic; + dvalid : out std_logic; + dlast : out std_logic; + + -- Registers. + START_REG : in std_logic + ); +end entity; + +architecture Behavioral of data_reader is + +constant NM_LOG2 : Integer := Integer(ceil(log2(real(NM)))); +constant NPOW : Integer := 2**N; + +-- Fifo to drive AXI Stream Master I/F. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +type fsm_state is ( INIT_ST, + READ_ST, + WRITE_ST, + READ_LAST_ST, + WRITE_LAST_ST, + FIFO_ST, + END_ST); +signal current_state, next_state : fsm_state; + +signal init_state : std_logic; +signal read_state : std_logic; +signal write_state : std_logic; +signal fifo_state : std_logic; +signal read_en : std_logic; + +-- Counter for memory address. +signal addr_cnt : unsigned(N-1 downto 0); + +-- Counter for memory selection. +signal sel_cnt : unsigned(NM_LOG2-1 downto 0); + +-- Counter for read data. +signal read_cnt : unsigned(NM_LOG2-1 downto 0); + +-- Fifo signals. +signal fifo_wr_en : std_logic; +signal fifo_rd_en : std_logic; +signal fifo_din : std_logic_vector (B-1 downto 0); +signal fifo_dout : std_logic_vector (B-1 downto 0); +signal fifo_full : std_logic; +signal fifo_empty : std_logic; + +signal mem_dout_r : std_logic_vector (NM*B-1 downto 0); + +signal dlast_i : std_logic; + +begin + +-- Fifo to drive AXI Stream Master I/F. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => 4 + ) + Port map + ( + rstn => rstn, + clk => clk, + + -- Write I/F. + wr_en => fifo_wr_en, + din => fifo_din, + + -- Read I/F. + rd_en => fifo_rd_en, + dout => fifo_dout, + + -- Flags. + full => fifo_full, + empty => fifo_empty + ); + +-- Fifo connections. +fifo_wr_en <= write_state; + +fifo_rd_en <= dready when read_en = '1' else + '0'; + +-- Mux for fifo_din. +process(sel_cnt,mem_dout_r) +begin + fifo_din <= (others => '0'); + for I in 0 to NM-1 loop + if ( sel_cnt = to_unsigned(I,sel_cnt'length) ) then + fifo_din <= mem_dout_r((I+1)*B-1 downto I*B); + end if; + end loop; +end process; + +-- dlast generation. +dlast_i <= '1' when (read_cnt = to_unsigned(NM-1,read_cnt'length)) and (fifo_state = '1') else + '0'; + +process(clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + current_state <= INIT_ST; + + addr_cnt <= (others => '0'); + sel_cnt <= (others => '0'); + read_cnt <= (others => '0'); + + mem_dout_r <= (others => '0'); + else + current_state <= next_state; + + if ( init_state = '1' ) then + mem_dout_r <= (others => '0'); + addr_cnt <= (others => '0'); + sel_cnt <= (others => '0'); + elsif ( read_state = '1' ) then + mem_dout_r <= mem_dout; + addr_cnt <= addr_cnt + 1; + elsif ( write_state = '1' ) then + if ( fifo_full = '0' ) then + sel_cnt <= sel_cnt + 1; + end if; + end if; + + if ( init_state = '1' ) then + read_cnt <= (others => '0'); + else + if ( dready = '1' and fifo_empty = '0' ) then + read_cnt <= read_cnt + 1; + end if; + end if; + end if; + end if; +end process; + +-- Next state logic. +process (current_state, START_REG, addr_cnt, sel_cnt, fifo_full, fifo_empty) +begin + case current_state is + when INIT_ST => + if (START_REG = '0') then + next_state <= INIT_ST; + else + next_state <= READ_ST; + end if; + + when READ_ST => + next_state <= WRITE_ST; + + when WRITE_ST => + if ( (sel_cnt < to_unsigned(NM-1,sel_cnt'length)) or (fifo_full = '1') ) then + next_state <= WRITE_ST; + elsif ( addr_cnt < to_unsigned(NPOW-1,addr_cnt'length) ) then + next_state <= READ_ST; + else + next_state <= READ_LAST_ST; + end if; + + when READ_LAST_ST => + next_state <= WRITE_LAST_ST; + + when WRITE_LAST_ST => + if ( (sel_cnt < to_unsigned(NM-1,sel_cnt'length)) or (fifo_full = '1') ) then + next_state <= WRITE_LAST_ST; + else + next_state <= FIFO_ST; + end if; + + when FIFO_ST => + if ( fifo_empty = '0' ) then + next_state <= FIFO_ST; + else + next_state <= END_ST; + end if; + + when END_ST => + if ( START_REG = '1' ) then + next_state <= END_ST; + else + next_state <= INIT_ST; + end if; + end case; +end process; + +-- Output logic. +process (current_state) +begin + init_state <= '0'; + read_state <= '0'; + write_state <= '0'; + fifo_state <= '0'; + read_en <= '0'; + case current_state is + when INIT_ST => + init_state <= '1'; + read_state <= '0'; + write_state <= '0'; + fifo_state <= '0'; + read_en <= '0'; + + when READ_ST => + init_state <= '0'; + read_state <= '1'; + write_state <= '0'; + fifo_state <= '0'; + read_en <= '1'; + + when WRITE_ST => + init_state <= '0'; + read_state <= '0'; + write_state <= '1'; + fifo_state <= '0'; + read_en <= '1'; + + when READ_LAST_ST => + init_state <= '0'; + read_state <= '1'; + write_state <= '0'; + fifo_state <= '0'; + read_en <= '1'; + + when WRITE_LAST_ST => + init_state <= '0'; + read_state <= '0'; + write_state <= '1'; + fifo_state <= '0'; + read_en <= '1'; + + when FIFO_ST => + init_state <= '0'; + read_state <= '0'; + write_state <= '0'; + fifo_state <= '1'; + read_en <= '1'; + + when END_ST => + init_state <= '0'; + read_state <= '0'; + write_state <= '0'; + fifo_state <= '0'; + read_en <= '0'; + + end case; +end process; + +-- Assign outputs. +mem_en <= '1'; +mem_we <= '0'; +mem_addr <= std_logic_vector(addr_cnt); + +dout <= fifo_dout; +dvalid <= not(fifo_empty); +dlast <= dlast_i; + +end Behavioral; diff --git a/firmware/ip/mr_buffer_et/src/data_writer.vhd b/firmware/ip/mr_buffer_et/src/data_writer.vhd new file mode 100644 index 0000000..32a7d17 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/data_writer.vhd @@ -0,0 +1,212 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity data_writer is + Generic + ( + -- Number of memories. + NM : Integer := 8; + -- Address map of each memory. + N : Integer := 8; + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Trigger. + trigger : in std_logic; + + -- AXI Stream I/F. + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- Memory I/F. + mem_en : out std_logic; + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_di : out std_logic_vector (B-1 downto 0); + + -- Registers. + CAPTURE_REG : in std_logic + ); +end entity; + +architecture Behavioral of data_writer is + +constant NPOW : Integer := 2**N; + +-- Fifo to interfase with AXI Stream. +component fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end component; + +-- State machine. +type fsm_state is ( INIT_ST, + TRIGGER_ST, + CAPTURE_ST, + END_ST); +signal current_state, next_state : fsm_state; + +signal init_state : std_logic; + +signal write_en : std_logic; + +signal fifo_wr_en : std_logic; +signal fifo_rd_en : std_logic; +signal fifo_dout : std_logic_vector (B-1 downto 0); +signal fifo_full : std_logic; +signal fifo_empty : std_logic; + +signal addr_cnt : unsigned (N-1 downto 0); + +begin + +-- Fifo to interface with AXI stream. +fifo_i : fifo + Generic map + ( + -- Data width. + B => B, + + -- Fifo depth. + N => 4 + ) + Port map + ( + rstn => rstn, + clk => clk, + + -- Write I/F. + wr_en => fifo_wr_en, + din => s_axis_tdata, + + -- Read I/F. + rd_en => fifo_rd_en, + dout => fifo_dout, + + -- Flags. + full => fifo_full, + empty => fifo_empty + ); + +-- Mux for fifo_wr_en. +fifo_wr_en <= s_axis_tvalid when write_en = '1' else + '0'; + +-- fifo_rd_en. +fifo_rd_en <= not fifo_empty; + +-- Registers. +process (clk) +begin + if (rising_edge(clk)) then + if ( rstn = '0' ) then + current_state <= INIT_ST; + else + current_state <= next_state; + + -- Address counter + if ( write_en = '1' ) then + if ( fifo_rd_en = '1' and fifo_empty = '0' ) then + addr_cnt <= addr_cnt + 1; + end if; + else + addr_cnt <= (others => '0'); + end if; + end if; + end if; +end process; + +-- Next state logic. +process (current_state, CAPTURE_REG, trigger, addr_cnt, fifo_rd_en, fifo_empty) +begin + case current_state is + when INIT_ST => + if (CAPTURE_REG = '0') then + next_state <= INIT_ST; + else + next_state <= TRIGGER_ST; + end if; + + when TRIGGER_ST => + if (trigger = '0') then + next_state <= TRIGGER_ST; + else + next_state <= CAPTURE_ST; + end if; + + when CAPTURE_ST => + if ( addr_cnt = to_unsigned(NPOW-1,addr_cnt'length) and fifo_rd_en = '1' and fifo_empty = '0' ) then + next_state <= END_ST; + else + next_state <= CAPTURE_ST; + end if; + + when END_ST => + if ( CAPTURE_REG = '0' and fifo_empty = '1') then + -- Wait until input FIFO is flushed out + next_state <= INIT_ST; + else + next_state <= END_ST; + end if; + end case; +end process; + +-- Output logic. +process (current_state) +begin + init_state <= '0'; + write_en <= '0'; + case current_state is + when INIT_ST => + init_state <= '1'; + + when TRIGGER_ST => + + when CAPTURE_ST => + write_en <= '1'; + + when END_ST => + + end case; +end process; + +-- Assign outputs. +s_axis_tready <= not(fifo_full) when write_en = '1' else + '0'; + +mem_en <= '1'; +mem_we <= write_en; +mem_addr <= std_logic_vector(addr_cnt); +mem_di <= fifo_dout; + +end Behavioral; diff --git a/firmware/ip/mr_buffer_et/src/fifo.vhd b/firmware/ip/mr_buffer_et/src/fifo.vhd new file mode 100644 index 0000000..2795bb6 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/fifo.vhd @@ -0,0 +1,115 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07/18/2019 08:35:37 AM +-- Design Name: +-- Module Name: fifo - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +use IEEE.NUMERIC_STD.ALL; + + +entity fifo is + Generic + ( + -- Data width. + B : Integer := 16; + + -- Fifo depth. + N : Integer := 4; + + -- Almost full. + AF : Integer := 3 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Write I/F. + wr_en : in std_logic; + din : in std_logic_vector (B-1 downto 0); + + -- Read I/F. + rd_en : in std_logic; + dout : out std_logic_vector (B-1 downto 0); + + -- Flags. + full : out std_logic; + empty : out std_logic + ); +end fifo; + +architecture Behavioral of fifo is + +-- Number of bits of depth. +constant N_LOG2 : Integer := Integer(ceil(log2(real(N)))); + +-- Registers. +type array_t is array (N-1 downto 0) of std_logic_vector (B-1 downto 0); +signal regs : array_t; + +-- Pointers. +signal wr_ptr : unsigned (N_LOG2-1 downto 0); +signal rd_ptr : unsigned (N_LOG2-1 downto 0); + +-- Flags. +signal full_i : std_logic; +signal empty_i : std_logic; + +begin + +-- Full/empty signals. +full_i <= '1' when wr_ptr = rd_ptr - 1 else + '0'; +empty_i <= '1' when wr_ptr = rd_ptr else + '0'; + +process (clk) +begin + if ( rising_edge(clk) ) then + if ( rstn = '0' ) then + wr_ptr <= (others => '0'); + rd_ptr <= (others => '0'); + else + -- Write. + if ( wr_en = '1' and full_i = '0' ) then + -- Write data. + regs(to_integer(wr_ptr)) <= din; + + -- Increment pointer. + wr_ptr <= wr_ptr + 1; + end if; + + -- Read. + if ( rd_en = '1' and empty_i = '0' ) then + -- Increment pointer. + rd_ptr <= rd_ptr + 1; + end if; + + end if; + end if; +end process; + +-- Assign outputs. +dout <= regs(to_integer(rd_ptr)); +full <= full_i; +empty <= empty_i; + +end Behavioral; diff --git a/firmware/ip/mr_buffer_et/src/mr_buffer.vhd b/firmware/ip/mr_buffer_et/src/mr_buffer.vhd new file mode 100644 index 0000000..4c669d9 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/mr_buffer.vhd @@ -0,0 +1,370 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity mr_buffer is + Generic + ( + -- Number of memories. + NM : Integer := 8; + -- Address map of each memory. + N : Integer := 8; + -- Data width. + B : Integer := 16 + ); + Port + ( + -- Trigger. + trigger : in std_logic; + + -- AXI Stream Slave I/F. + s_axis_aclk : in std_logic; + s_axis_aresetn : in std_logic; + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(NM*B-1 downto 0); + s_axis_tstrb : in std_logic_vector((NM*B/8)-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXI Stream Master I/F. + m_axis_aclk : in std_logic; + m_axis_aresetn : in std_logic; + m_axis_tvalid : out std_logic; + m_axis_tdata : out std_logic_vector(B-1 downto 0); + m_axis_tstrobe : out std_logic_vector((B/8)-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tready : in std_logic; + + -- Registers. + DW_CAPTURE_REG : in std_logic; + DR_START_REG : in std_logic; + DEBUG_REG : in std_logic_vector(31 downto 0); + + -- Debug Output Probes + s_dbg_probe : out std_logic_vector(31 downto 0); + m_dbg_probe : out std_logic_vector(31 downto 0) + + ); +end mr_buffer; + +architecture Behavioral of mr_buffer is + +-- Synchronizer. +component synchronizer is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end component; + +-- Memory. +component bram_dp is + Generic ( + -- Memory address size. + N : Integer := 16; + -- Data width. + B : Integer := 16 + ); + Port ( + clka : in STD_LOGIC; + clkb : in STD_LOGIC; + ena : in STD_LOGIC; + enb : in STD_LOGIC; + wea : in STD_LOGIC; + web : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR (N-1 downto 0); + addrb : in STD_LOGIC_VECTOR (N-1 downto 0); + dia : in STD_LOGIC_VECTOR (B-1 downto 0); + dib : in STD_LOGIC_VECTOR (B-1 downto 0); + doa : out STD_LOGIC_VECTOR (B-1 downto 0); + dob : out STD_LOGIC_VECTOR (B-1 downto 0) + ); +end component; + +-- Data writer. +component data_writer is + Generic + ( + -- Number of memories. + NM : Integer := 8; + -- Address map of each memory. + N : Integer := 8; + -- Data width. + B : Integer := 16 + ); + Port + ( + rstn : in std_logic; + clk : in std_logic; + + -- Trigger. + trigger : in std_logic; + + -- AXI Stream I/F. + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(B-1 downto 0); + s_axis_tvalid : in std_logic; + + -- Memory I/F. + mem_en : out std_logic; + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_di : out std_logic_vector (B-1 downto 0); + + -- Registers. + CAPTURE_REG : in std_logic + ); +end component; + +-- Data reader. +component data_reader is + Generic + ( + -- Number of memories. + NM : Integer := 8; + -- Address map of each memory. + N : Integer := 8; + -- Data width. + B : Integer := 16 + ); + Port + ( + -- Reset and clock. + rstn : in std_logic; + clk : in std_logic; + + -- Memory I/F. + mem_en : out std_logic; + mem_we : out std_logic; + mem_addr : out std_logic_vector (N-1 downto 0); + mem_dout : in std_logic_vector (NM*B-1 downto 0); + + -- Data out. + dout : out std_logic_vector (B-1 downto 0); + dready : in std_logic; + dvalid : out std_logic; + dlast : out std_logic; + + -- Registers. + START_REG : in std_logic + ); +end component; + +-- Re-sync trigger and registers. +signal DW_CAPTURE_REG_resync: std_logic; +signal DR_START_REG_resync : std_logic; +signal trigger_or_dbg : std_logic; +signal trigger_resync : std_logic; + +-- ena/enb/wea/web. +signal ena : std_logic_vector (NM-1 downto 0); +signal enb : std_logic; +signal wea : std_logic_vector (NM-1 downto 0); +signal web : std_logic; + +-- addra/addrb. +type addr_array_t is array (NM-1 downto 0) of std_logic_vector (N-1 downto 0); +signal addra : addr_array_t; +signal addrb : std_logic_vector (N-1 downto 0); + +-- dia/dib/doa/dob/dout. +type di_do_array_t is array (NM-1 downto 0) of std_logic_vector (B-1 downto 0); +signal dia : di_do_array_t; +signal dib : std_logic_vector (B-1 downto 0); +signal doa : di_do_array_t; +signal dob : di_do_array_t; +signal dout : std_logic_vector (B-1 downto 0); + +-- Concatenated data for reader. +signal dob_c: std_logic_vector (NM*B-1 downto 0); + +-- s_axis_tdata. +type tdata_array_t is array (NM-1 downto 0) of std_logic_vector (B-1 downto 0); +signal s_axis_tdata_i : tdata_array_t; + +-- s_axis_tvalid/tready. +signal s_axis_tvalid_i : std_logic_vector (NM-1 downto 0); +signal s_axis_tready_i : std_logic_vector (NM-1 downto 0); + +signal dtvalid : std_logic; +signal dtlast : std_logic; +signal dtdata : std_logic_vector(B-1 downto 0); + +-- Debug signals +signal trigger_dbg : std_logic; +signal s_axis_tready_force : std_logic; + +begin + + trigger_dbg <= DEBUG_REG(0); + s_axis_tready_force <= DEBUG_REG(1); + +-- DW_CAPTURE_REG_resync. +DW_CAPTURE_REG_resync_i : synchronizer + generic map ( + N => 2 + ) + port map ( + rstn => s_axis_aresetn, + clk => s_axis_aclk, + data_in => DW_CAPTURE_REG, + data_out => DW_CAPTURE_REG_resync + ); + +-- DR_START_REG_resync. +DR_START_REG_resync_i : synchronizer + generic map ( + N => 2 + ) + port map ( + rstn => m_axis_aresetn, + clk => m_axis_aclk, + data_in => DR_START_REG, + data_out => DR_START_REG_resync + ); + + trigger_or_dbg <= trigger or trigger_dbg; + +-- trigger_resync. +trigger_resync_i : synchronizer + generic map ( + N => 2 + ) + port map ( + rstn => s_axis_aresetn, + clk => s_axis_aclk, + data_in => trigger_or_dbg, + data_out => trigger_resync + ); + +GEN: for I in 0 to NM-1 generate + + -- Memory instantiation. + bram_dp_i : bram_dp + Generic map + ( + -- Memory address size. + N => N, + -- Data width. + B => B + ) + Port map + ( + clka => s_axis_aclk, + clkb => m_axis_aclk, + ena => ena(I), + enb => enb, + wea => wea(I), + web => web, + addra => addra(I), + addrb => addrb, + dia => dia(I), + dib => dib, + doa => doa(I), + dob => dob(I) + ); + + -- Data writer. + data_writer_i : data_writer + Generic map + ( + -- Number of memories. + NM => NM, + -- Address map of each memory. + N => N, + -- Data width. + B => B + ) + Port map + ( + rstn => s_axis_aresetn , + clk => s_axis_aclk , + + -- Trigger. + trigger => trigger_resync , + + -- AXI Stream I/F. + s_axis_tready => s_axis_tready_i(I) , + s_axis_tdata => s_axis_tdata_i(I) , + s_axis_tvalid => s_axis_tvalid_i(I) , + + -- Memory I/F. + mem_en => ena(I) , + mem_we => wea(I) , + mem_addr => addra(I) , + mem_di => dia(I) , + + -- Registers. + CAPTURE_REG => DW_CAPTURE_REG_resync + ); + + -- Input tdata. + s_axis_tdata_i(I) <= s_axis_tdata((I+1)*B-1 downto I*B); + s_axis_tvalid_i(I) <= s_axis_tvalid; + + -- Concatenate output data for port b. + dob_c((I+1)*B-1 downto I*B) <= dob(I); + +end generate GEN; + +-- Data reader instantiation. +data_reader_i : data_reader +Generic map +( + -- Number of memories. + NM => NM, + -- Memory address size. + N => N, + -- Data width. + B => B +) +Port map +( + -- Reset and clock. + rstn => m_axis_aresetn, + clk => m_axis_aclk, + + -- Memory I/F. + mem_en => enb, + mem_we => web, + mem_addr => addrb, + mem_dout => dob_c, + + -- Data out. + dready => m_axis_tready, + dout => dtdata, + dvalid => dtvalid, + dlast => dtlast, + + -- Registers. + START_REG => DR_START_REG_resync +); + +-- Output assignment. +s_axis_tready <= s_axis_tready_i(0) or s_axis_tready_force; +m_axis_tstrobe <= (others => '1'); + +m_axis_tvalid <= dtvalid; +m_axis_tlast <= dtlast; +m_axis_tdata <= dtdata; + + +-- Debug ILA probe +s_dbg_probe(7 downto 0) <= "000" & DW_CAPTURE_REG_resync & trigger_resync & wea(0) & s_axis_tvalid_i(0) & s_axis_tready_i(0); +s_dbg_probe(15 downto 8) <= s_axis_tdata_i(0)(7 downto 0); +s_dbg_probe(23 downto 16) <= std_logic_vector(resize(unsigned(addra(0)),8)); +s_dbg_probe(31 downto 24) <= dia(0)(7 downto 0); + + +m_dbg_probe(7 downto 0) <= "000" & DR_START_REG_resync & web & dtlast & dtvalid & m_axis_tready; +m_dbg_probe(15 downto 8) <= dtdata(7 downto 0); +m_dbg_probe(23 downto 16) <= std_logic_vector(resize(unsigned(addrb),8)); +m_dbg_probe(31 downto 24) <= dob_c(7 downto 0); + +end Behavioral; + diff --git a/firmware/ip/mr_buffer_et/src/mr_buffer_v1_0.vhd b/firmware/ip/mr_buffer_et/src/mr_buffer_v1_0.vhd new file mode 100644 index 0000000..fe2d212 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/mr_buffer_v1_0.vhd @@ -0,0 +1,214 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mr_buffer_v1_0 is + generic ( + -- Number of memories. + NM : Integer := 8; + -- Address map of each memory. + N : Integer := 8; + -- Data width. + B : Integer := 16; + + -- Parameters of Axi Slave Bus Interface S00_AXI + C_S00_AXI_DATA_WIDTH : integer := 32; + C_S00_AXI_ADDR_WIDTH : integer := 6; + + -- Enable Debug + DEBUG : Integer := 0 + ); + port ( + -- Trigger. + trigger : in std_logic; + + -- Ports of Axi Slave Bus Interface S00_AXI + s00_axi_aclk : in std_logic; + s00_axi_aresetn : in std_logic; + s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); + s00_axi_awprot : in std_logic_vector(2 downto 0); + s00_axi_awvalid : in std_logic; + s00_axi_awready : out std_logic; + s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0); + s00_axi_wvalid : in std_logic; + s00_axi_wready : out std_logic; + s00_axi_bresp : out std_logic_vector(1 downto 0); + s00_axi_bvalid : out std_logic; + s00_axi_bready : in std_logic; + s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); + s00_axi_arprot : in std_logic_vector(2 downto 0); + s00_axi_arvalid : in std_logic; + s00_axi_arready : out std_logic; + s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + s00_axi_rresp : out std_logic_vector(1 downto 0); + s00_axi_rvalid : out std_logic; + s00_axi_rready : in std_logic; + + -- Ports of Axi Slave Bus Interface S00_AXIS + s00_axis_aclk : in std_logic; + s00_axis_aresetn: in std_logic; + s00_axis_tready : out std_logic; + s00_axis_tdata : in std_logic_vector(NM*B-1 downto 0); + s00_axis_tstrb : in std_logic_vector((NM*B/8)-1 downto 0); + s00_axis_tlast : in std_logic; + s00_axis_tvalid : in std_logic; + + -- Ports of Axi Master Bus Interface M00_AXIS + m00_axis_aclk : in std_logic; + m00_axis_aresetn : in std_logic; + m00_axis_tvalid : out std_logic; + m00_axis_tdata : out std_logic_vector(B-1 downto 0); + m00_axis_tstrb : out std_logic_vector((B/8)-1 downto 0); + m00_axis_tlast : out std_logic; + m00_axis_tready : in std_logic; + + -- Debug Output Probes + s_dbg_probe : out std_logic_vector(31 downto 0); + m_dbg_probe : out std_logic_vector(31 downto 0) + + ); +end mr_buffer_v1_0; + +architecture arch_imp of mr_buffer_v1_0 is + + -- component declaration + component mr_buffer_v1_0_S00_AXI is + generic ( + -- Number of memories. + NM : Integer := 8; + -- Address map of each memory. + N : Integer := 8; + -- Data width. + B : Integer := 16; + + -- Parameters of Axi Slave Bus Interface S00_AXI + C_S_AXI_DATA_WIDTH : integer := 32; + C_S_AXI_ADDR_WIDTH : integer := 6 + ); + port ( + -- Trigger. + trigger : in std_logic; + + -- Ports of Axi Slave Bus Interface S00_AXI + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic; + + -- Ports of Axi Slave Bus Interface S00_AXIS + S_AXIS_ACLK : in std_logic; + S_AXIS_ARESETN : in std_logic; + S_AXIS_TREADY : out std_logic; + S_AXIS_TDATA : in std_logic_vector(NM*B-1 downto 0); + S_AXIS_TSTRB : in std_logic_vector((NM*B/8)-1 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TVALID : in std_logic; + + -- Ports of Axi Master Bus Interface M00_AXIS + M_AXIS_ACLK : in std_logic; + M_AXIS_ARESETN : in std_logic; + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(B-1 downto 0); + M_AXIS_TSTRB : out std_logic_vector((B/8)-1 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TREADY : in std_logic; + + -- Debug Output Probes + s_dbg_probe : out std_logic_vector(31 downto 0); + m_dbg_probe : out std_logic_vector(31 downto 0) + ); + end component mr_buffer_v1_0_S00_AXI; + + signal s_dbg_probe_int : std_logic_vector(31 downto 0); + signal m_dbg_probe_int : std_logic_vector(31 downto 0); + +begin + +-- Instantiation of Axi Bus Interface S00_AXI +mr_buffer_v1_0_S00_AXI_inst : mr_buffer_v1_0_S00_AXI + generic map ( + NM => NM, + N => N, + B => B, + C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH + ) + port map ( + -- Trigger. + trigger => trigger, + + -- Ports of Axi Slave Bus Interface S00_AXI + S_AXI_ACLK => s00_axi_aclk, + S_AXI_ARESETN => s00_axi_aresetn, + S_AXI_AWADDR => s00_axi_awaddr, + S_AXI_AWPROT => s00_axi_awprot, + S_AXI_AWVALID => s00_axi_awvalid, + S_AXI_AWREADY => s00_axi_awready, + S_AXI_WDATA => s00_axi_wdata, + S_AXI_WSTRB => s00_axi_wstrb, + S_AXI_WVALID => s00_axi_wvalid, + S_AXI_WREADY => s00_axi_wready, + S_AXI_BRESP => s00_axi_bresp, + S_AXI_BVALID => s00_axi_bvalid, + S_AXI_BREADY => s00_axi_bready, + S_AXI_ARADDR => s00_axi_araddr, + S_AXI_ARPROT => s00_axi_arprot, + S_AXI_ARVALID => s00_axi_arvalid, + S_AXI_ARREADY => s00_axi_arready, + S_AXI_RDATA => s00_axi_rdata, + S_AXI_RRESP => s00_axi_rresp, + S_AXI_RVALID => s00_axi_rvalid, + S_AXI_RREADY => s00_axi_rready, + + -- Ports of Axi Slave Bus Interface S00_AXIS + S_AXIS_ACLK => s00_axis_aclk, + S_AXIS_ARESETN => s00_axis_aresetn, + S_AXIS_TREADY => s00_axis_tready, + S_AXIS_TDATA => s00_axis_tdata, + S_AXIS_TSTRB => s00_axis_tstrb, + S_AXIS_TLAST => s00_axis_tlast, + S_AXIS_TVALID => s00_axis_tvalid, + + -- Ports of Axi Master Bus Interface M00_AXIS + M_AXIS_ACLK => m00_axis_aclk, + M_AXIS_ARESETN => m00_axis_aresetn, + M_AXIS_TVALID => m00_axis_tvalid, + M_AXIS_TDATA => m00_axis_tdata, + M_AXIS_TSTRB => m00_axis_tstrb, + M_AXIS_TLAST => m00_axis_tlast, + M_AXIS_TREADY => m00_axis_tready, + + s_dbg_probe => s_dbg_probe_int, + m_dbg_probe => m_dbg_probe_int + ); + + DEBUG_GEN: if DEBUG = 1 generate + -- Debug ILA probe + s_dbg_probe <= s_dbg_probe_int; + m_dbg_probe <= m_dbg_probe_int; + end generate; + DEBUG_NOGEN: if DEBUG /= 1 generate + s_dbg_probe <= (others => '0'); + m_dbg_probe <= (others => '0'); + end generate; + +end arch_imp; + diff --git a/firmware/ip/mr_buffer_et/src/mr_buffer_v1_0_S00_AXI.vhd b/firmware/ip/mr_buffer_et/src/mr_buffer_v1_0_S00_AXI.vhd new file mode 100644 index 0000000..0f2b6f7 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/mr_buffer_v1_0_S00_AXI.vhd @@ -0,0 +1,613 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mr_buffer_v1_0_S00_AXI is + generic ( + -- Number of memories. + NM : Integer := 8; + -- Address map of each memory. + N : Integer := 8; + -- Data width. + B : Integer := 16; + + -- Width of S_AXI data bus + C_S_AXI_DATA_WIDTH : integer := 32; + -- Width of S_AXI address bus + C_S_AXI_ADDR_WIDTH : integer := 6 + ); + port ( + -- Trigger. + trigger : in std_logic; + + -- Ports of Axi Slave Bus Interface S00_AXI + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic; + + -- Ports of Axi Slave Bus Interface S00_AXIS + S_AXIS_ACLK : in std_logic; + S_AXIS_ARESETN : in std_logic; + S_AXIS_TREADY : out std_logic; + S_AXIS_TDATA : in std_logic_vector(NM*B-1 downto 0); + S_AXIS_TSTRB : in std_logic_vector((NM*B/8)-1 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TVALID : in std_logic; + + -- Ports of Axi Master Bus Interface M00_AXIS + M_AXIS_ACLK : in std_logic; + M_AXIS_ARESETN : in std_logic; + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(B-1 downto 0); + M_AXIS_TSTRB : out std_logic_vector((B/8)-1 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TREADY : in std_logic; + + -- Debug Output Probes + s_dbg_probe : out std_logic_vector(31 downto 0); + m_dbg_probe : out std_logic_vector(31 downto 0) + ); +end mr_buffer_v1_0_S00_AXI; + +architecture arch_imp of mr_buffer_v1_0_S00_AXI is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + + component mr_buffer is + Generic + ( + -- Number of memories. + NM : Integer := 8; + -- Address map of each memory. + N : Integer := 8; + -- Data width. + B : Integer := 16 + ); + Port + ( + -- Trigger. + trigger : in std_logic; + + -- AXI Stream Slave I/F. + s_axis_aclk : in std_logic; + s_axis_aresetn : in std_logic; + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(NM*B-1 downto 0); + s_axis_tstrb : in std_logic_vector((NM*B/8)-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXI Stream Master I/F. + m_axis_aclk : in std_logic; + m_axis_aresetn : in std_logic; + m_axis_tvalid : out std_logic; + m_axis_tdata : out std_logic_vector(B-1 downto 0); + m_axis_tstrobe : out std_logic_vector((B/8)-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tready : in std_logic; + + -- Registers. + DW_CAPTURE_REG : in std_logic; + DR_START_REG : in std_logic; + DEBUG_REG : in std_logic_vector(31 downto 0); + + -- Debug Output Probes + s_dbg_probe : out std_logic_vector(31 downto 0); + m_dbg_probe : out std_logic_vector(31 downto 0) + ); + end component; + +begin + -- I/O Connections assignments + + S_AXI_AWREADY <= axi_awready; + S_AXI_WREADY <= axi_wready; + S_AXI_BRESP <= axi_bresp; + S_AXI_BVALID <= axi_bvalid; + S_AXI_ARREADY <= axi_arready; + S_AXI_RDATA <= axi_rdata; + S_AXI_RRESP <= axi_rresp; + S_AXI_RVALID <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= S_AXI_AWADDR; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ; + + process (S_AXI_ACLK) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and S_AXI_ARVALID = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= S_AXI_ARADDR; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, S_AXI_ARESETN, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= slv_reg9; + when b"1010" => + reg_data_out <= slv_reg10; + when b"1011" => + reg_data_out <= slv_reg11; + when b"1100" => + reg_data_out <= slv_reg12; + when b"1101" => + reg_data_out <= slv_reg13; + when b"1110" => + reg_data_out <= slv_reg14; + when b"1111" => + reg_data_out <= slv_reg15; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + mr_buffer_i : mr_buffer + Generic map + ( + -- Number of memories. + NM => NM, + -- Address map of each memory. + N => N, + -- Data width. + B => B + ) + Port map + ( + -- Trigger. + trigger => trigger, + + -- AXI Stream Slave I/F. + s_axis_aclk => S_AXIS_ACLK, + s_axis_aresetn => S_AXIS_ARESETN, + s_axis_tready => S_AXIS_TREADY, + s_axis_tdata => S_AXIS_TDATA, + s_axis_tstrb => S_AXIS_TSTRB, + s_axis_tlast => S_AXIS_TLAST, + s_axis_tvalid => S_AXIS_TVALID, + + -- AXI Stream Master I/F. + m_axis_aclk => M_AXIS_ACLK, + m_axis_aresetn => M_AXIS_ARESETN, + m_axis_tvalid => M_AXIS_TVALID, + m_axis_tdata => M_AXIS_TDATA, + m_axis_tstrobe => M_AXIS_TSTRB, + m_axis_tlast => M_AXIS_TLAST, + m_axis_tready => M_AXIS_TREADY, + + -- Registers. + DW_CAPTURE_REG => slv_reg0(0), + DR_START_REG => slv_reg1(0), + DEBUG_REG => slv_reg15, + + s_dbg_probe => s_dbg_probe, + m_dbg_probe => m_dbg_probe + ); + +end arch_imp; + diff --git a/firmware/ip/mr_buffer_et/src/synchronizer.vhd b/firmware/ip/mr_buffer_et/src/synchronizer.vhd new file mode 100644 index 0000000..d982c68 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/synchronizer.vhd @@ -0,0 +1,40 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library common_lib; +use common_lib.all; + +entity synchronizer is + generic ( + N : Integer := 2 + ); + port ( + rstn : in std_logic; + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); +end synchronizer; + +architecture rtl of synchronizer is + +-- Internal register. +signal data_int_reg : std_logic_vector (N-1 downto 0); + +begin + +process(clk,rstn) +begin + if (rstn = '0') then + data_int_reg <= (others => '0'); -- 1 FF. + elsif (clk'event and clk='1') then + data_int_reg <= data_int_reg(N-2 downto 0) & data_in; + end if; +end process; + +-- Assign output. +data_out <= data_int_reg(N-1); + +end rtl; + diff --git a/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_0/axi4stream_vip_0.vho b/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_0/axi4stream_vip_0.vho new file mode 100644 index 0000000..2fcd3f2 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_0/axi4stream_vip_0.vho @@ -0,0 +1,84 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. +-- IP VLNV: xilinx.com:ip:axi4stream_vip:1.1 +-- IP Revision: 14 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi4stream_vip_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + s_axis_tvalid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_tready : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi4stream_vip_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + s_axis_tvalid => s_axis_tvalid, + s_axis_tready => s_axis_tready, + s_axis_tdata => s_axis_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi4stream_vip_0.vhd when simulating +-- the core, axi4stream_vip_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + + + diff --git a/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_0/axi4stream_vip_0.xci b/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_0/axi4stream_vip_0.xci new file mode 100644 index 0000000..7c9b893 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_0/axi4stream_vip_0.xci @@ -0,0 +1,128 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "axi4stream_vip_0", + "component_reference": "xilinx.com:ip:axi4stream_vip:1.1", + "ip_revision": "14", + "gen_directory": ".", + "parameters": { + "component_parameters": { + "INTERFACE_MODE": [ { "value": "SLAVE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "TDATA_NUM_BYTES": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "USER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": 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"value": "." } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "aclk": [ { "direction": "in", "driver_value": "0" } ], + "aresetn": [ { "direction": "in", "driver_value": "1" } ], + "s_axis_tvalid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "s_axis_tready": [ { "direction": "out", "size_left": "0", "size_right": "0" } ], + "s_axis_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ] + }, + "interfaces": { + "S_AXIS": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "slave", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": 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"physical_name": "s_axis_tvalid" } ] + } + }, + "RESET": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "aresetn" } ] + } + }, + "CLOCK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "aclk" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_0/axi4stream_vip_0.xml b/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_0/axi4stream_vip_0.xml new file mode 100644 index 0000000..5bebb98 --- /dev/null +++ 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+ + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + Component_Name + axi4stream_vip_0 + + + + + AXI4-Stream Verification IP + + XPM_CDC + + + xtlm + protobuf + xtlm_ipc_v1_0 + sim_ipc_multi_intf_v1_0 + + 14 + true + + + + + + + + + + + 2023.1 + + + + + + + + diff --git a/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_1/axi4stream_vip_1.vho b/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_1/axi4stream_vip_1.vho new file mode 100644 index 0000000..2d3e7f0 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_1/axi4stream_vip_1.vho @@ -0,0 +1,84 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. +-- IP VLNV: xilinx.com:ip:axi4stream_vip:1.1 +-- IP Revision: 14 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi4stream_vip_1 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axis_tvalid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + m_axis_tready : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi4stream_vip_1 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axis_tvalid => m_axis_tvalid, + m_axis_tready => m_axis_tready, + m_axis_tdata => m_axis_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi4stream_vip_1.vhd when simulating +-- the core, axi4stream_vip_1. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + + + diff --git a/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_1/axi4stream_vip_1.xci b/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_1/axi4stream_vip_1.xci new file mode 100644 index 0000000..b872481 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/tb/axi4stream_vip_1/axi4stream_vip_1.xci @@ -0,0 +1,128 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "axi4stream_vip_1", + "component_reference": "xilinx.com:ip:axi4stream_vip:1.1", + "ip_revision": "14", + "gen_directory": ".", + "parameters": { + "component_parameters": { + "INTERFACE_MODE": [ { "value": "MASTER", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "USER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "HAS_TUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "TID_WIDTH": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "HAS_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Component_Name": [ { "value": "axi4stream_vip_1", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "C_AXI4STREAM_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_AXI4STREAM_INTERFACE_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI4STREAM_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI4STREAM_USER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI4STREAM_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI4STREAM_DEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI4STREAM_USER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI4STREAM_HAS_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ], + "BASE_BOARD_PART": [ { "value": "xilinx.com:zcu111:part0:1.4" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xczu28dr" } ], + "PACKAGE": [ { "value": "ffvg1517" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], + "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], + "USE_RDI_GENERATION": [ { "value": "TRUE" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Flow" } ], + "IPREVISION": [ { "value": "14" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "." } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "." } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "aclk": [ { "direction": "in", "driver_value": "0" } ], + "aresetn": [ { "direction": "in", "driver_value": "1" } ], + "m_axis_tvalid": [ { "direction": "out", "size_left": "0", "size_right": "0" } ], + "m_axis_tready": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "m_axis_tdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ] + }, + "interfaces": { + "M_AXIS": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "master", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": 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"physical_name": "m_axis_tvalid" } ] + } + }, + "RESET": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "aresetn" } ] + } + }, + "CLOCK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", 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sysc/axi_stream_vip.cpp + systemCSource + axi4stream_vip_v1_1_14 + + + sysc/axi_stream_vip.h + systemCSource + true + axi4stream_vip_v1_1_14 + + + sysc/sim_ipc_axis_multi_intf.h + systemCSource + true + axi4stream_vip_v1_1_14 + + + sysc/sim_ipc_axis_multi_intf.cpp + systemCSource + axi4stream_vip_v1_1_14 + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi4stream_vip_1_sc.h + systemCSource + true + + + sim/axi4stream_vip_1_sc.cpp + systemCSource + + + sim/axi4stream_vip_1.h + systemCSource + true + + + sim/axi4stream_vip_1.cpp + systemCSource + + + sim/axi4stream_vip_1_stub.sv + systemVerilogSource + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset + + hdl/axis_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axis_infrastructure_v1_1_0 + + + hdl/axis_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axis_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi4stream_vip_1_pkg.sv + systemVerilogSource + + + hdl/axi4stream_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi4stream_vip_v1_1_14 + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi4stream_vip_1.vho + vhdlTemplate + + + axi4stream_vip_1.veo + verilogTemplate + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi4stream_vip_1.sv + systemVerilogSource + xil_defaultlib + + + + The AXI4-Stream Verification IP. + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + TDATA_NUM_BYTES + TDATA WIDTH(BYTES) + 4 + + + USER_BITS_PER_BYTE + TUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_TUSER_BITS_PER_BYTE + HAS TUSER_BITS_PER_BYTE + 0 + + + TID_WIDTH + TID WIDTH(BITS) + 0 + + + TDEST_WIDTH + TDEST WIDTH(BITS) + 0 + + + TUSER_WIDTH + TUSER WIDTH(BITS) + 0 + + + HAS_TREADY + ENABLE TREADY + 1 + + + HAS_TSTRB + ENABLE TSTRB + 0 + + + HAS_TKEEP + ENABLE TKEEP + 0 + + + HAS_TLAST + ENABLE TLAST + 0 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + Component_Name + axi4stream_vip_1 + + + + + AXI4-Stream Verification IP + + XPM_CDC + + + xtlm + protobuf + xtlm_ipc_v1_0 + sim_ipc_multi_intf_v1_0 + + 14 + true + + + + + + + + + + + + 2023.1 + + + + + + + + diff --git a/firmware/ip/mr_buffer_et/src/tb/axi_vip_0/axi_vip_0.vho b/firmware/ip/mr_buffer_et/src/tb/axi_vip_0/axi_vip_0.vho new file mode 100644 index 0000000..8f42c20 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/tb/axi_vip_0/axi_vip_0.vho @@ -0,0 +1,116 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 14 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_vip_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_vip_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_vip_0.vhd when simulating +-- the core, axi_vip_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + + + diff --git a/firmware/ip/mr_buffer_et/src/tb/axi_vip_0/axi_vip_0.xci b/firmware/ip/mr_buffer_et/src/tb/axi_vip_0/axi_vip_0.xci new file mode 100644 index 0000000..ce43588 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/tb/axi_vip_0/axi_vip_0.xci @@ -0,0 +1,215 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "axi_vip_0", + "component_reference": "xilinx.com:ip:axi_vip:1.1", + "ip_revision": "14", + "gen_directory": ".", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "axi_vip_0", "resolve_type": "user", "usage": "all" } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ], + "INTERFACE_MODE": [ { "value": "MASTER", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "AWUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "ARUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "RUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "WUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "BUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } 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xtlm.h + + + requires + + + tlm + + + name + wr_socket + + + width + 32 + + + + + + + 1 + + + + + M_INITIATOR_rd_socket + AXIMM Read Socket + AXIMM Socket for Read + + + xtlm::xtlm_aximm_initiator_socket + xtlm.h + + + requires + + + tlm + + + name + rd_socket + + + width + 32 + + + + + + + 1 + + + + + S_TARGET_wr_socket + AXIMM Write Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + wr_socket + + + + + + + 1 + + + + + S_TARGET_rd_socket + AXIMM Read Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + + + + + 1 + + + + + + + C_AXI_PROTOCOL + 2 + + + C_AXI_INTERFACE_MODE + 0 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_WDATA_WIDTH + 32 + + + C_AXI_RDATA_WIDTH + 32 + + + C_AXI_WID_WIDTH + 0 + + + C_AXI_RID_WIDTH + 0 + + + C_AXI_AWUSER_WIDTH + 0 + + + C_AXI_ARUSER_WIDTH + 0 + + + C_AXI_WUSER_WIDTH + 0 + + + C_AXI_RUSER_WIDTH + 0 + + + C_AXI_BUSER_WIDTH + 0 + + + C_AXI_SUPPORTS_NARROW + 0 + + + C_AXI_HAS_BURST + 0 + + + C_AXI_HAS_LOCK + 0 + + + C_AXI_HAS_CACHE + 0 + + + C_AXI_HAS_REGION + 0 + + + C_AXI_HAS_PROT + 1 + + + C_AXI_HAS_QOS + 0 + + + C_AXI_HAS_WSTRB + 1 + + + C_AXI_HAS_BRESP + 1 + + + C_AXI_HAS_RRESP + 1 + + + C_AXI_HAS_ARESETN + 1 + + + + + + choice_list_04fafd91 + AXI3 + AXI4 + AXI4LITE + + + choice_list_6240decd + READ_ONLY + READ_WRITE + WRITE_ONLY + + + choice_list_642e7122 + MASTER + PASS_THROUGH + SLAVE + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_0fc128e8 + 0 + 0 + + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.h + systemCSource + true + + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_14 + + + sysc/sim_ipc_aximm_master.cpp + systemCSource + axi_vip_v1_1_14 + + + sysc/sim_ipc_aximm_slave.cpp + systemCSource + axi_vip_v1_1_14 + + + sysc/sim_ipc_aximm_master.h + systemCSource + true + axi_vip_v1_1_14 + + + sysc/sim_ipc_aximm_slave.h + systemCSource + true + axi_vip_v1_1_14 + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_vip_0_sc.h + systemCSource + true + + + sim/axi_vip_0_sc.cpp + systemCSource + + + sim/axi_vip_0.h + systemCSource + true + + + sim/axi_vip_0.cpp + systemCSource + + + sim/axi_vip_0_stub.sv + systemVerilogSource + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_vip_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_14 + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi_vip_0.vho + vhdlTemplate + + + axi_vip_0.veo + verilogTemplate + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_vip_0.sv + systemVerilogSource + xil_defaultlib + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_vip_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + VIP_PKG_NAME + VIP_PKG_NAME + 0 + + + + + AXI Verification IP + + xtlm + xtlm_ipc_v1_0 + protobuf + + 14 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + + + + + + + + diff --git a/firmware/ip/mr_buffer_et/src/tb/tb.sv b/firmware/ip/mr_buffer_et/src/tb/tb.sv new file mode 100644 index 0000000..57dc623 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/tb/tb.sv @@ -0,0 +1,361 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 02/19/2019 01:38:28 PM +// Design Name: +// Module Name: tb +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +import axi_vip_pkg::*; +import axi_vip_0_pkg::*; +import axi4stream_vip_pkg::*; +import axi4stream_vip_0_pkg::*; +import axi4stream_vip_1_pkg::*; + +module tb( + ); + +// AXI signals. +reg aclk = 0; +reg aresetn; +reg trigger; +wire [31:0] m_axi_awaddr; +wire [2:0] m_axi_awprot; +wire m_axi_awvalid; +wire m_axi_awready; +wire [31:0] m_axi_wdata; +wire [3:0] m_axi_wstrb; +wire m_axi_wvalid; +wire m_axi_wready; +wire [1:0] m_axi_bresp; +wire m_axi_bvalid; +wire m_axi_bready; +wire [31:0] m_axi_araddr; +wire [2:0] m_axi_arprot; +wire m_axi_arvalid; +wire m_axi_arready; +wire [31:0] m_axi_rdata; +wire [1:0] m_axi_rresp; +wire m_axi_rvalid; +wire m_axi_rready; + +// AXIS Master signals. +reg m_axis_aclk = 0; +reg m_axis_aresetn; +wire m_axis_tvalid; +wire m_axis_tready; +wire [7:0] m_axis_tdata; + +// AXIS Slave signals. +reg s_axis_aclk = 0; +reg s_axis_aresetn; +wire s_axis_tready; +wire [31:0] s_axis_tdata; +wire s_axis_tvalid; + +axi4stream_transaction wr_transaction; +axi4stream_ready_gen ready_gen; + +xil_axi_ulong addr_DW_CAPTURE_REG = 32'h44A00000; // 0 +xil_axi_ulong addr_DR_START_REG = 32'h44A00004; // 1 + +xil_axi_prot_t prot = 0; +reg[31:0] data_wr=32'h01234567; +reg[31:0] data_rd=32'h01234567; +xil_axi_resp_t resp; + +// AXI Master VIP. +axi_vip_0 axi_vip_i ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); + +// AXIS Master VIP. +axi4stream_vip_1 axis_mst_vip_i ( + .aclk(s_axis_aclk), // input wire aclk + .aresetn(s_axis_aresetn), // input wire aresetn + .m_axis_tvalid(s_axis_tvalid), // output wire [0 : 0] m_axis_tvalid + .m_axis_tready(s_axis_tready), // input wire [0 : 0] m_axis_tready + .m_axis_tdata(s_axis_tdata) // output wire [7 : 0] m_axis_tdata +); + +// AXIS Slave VIP. +axi4stream_vip_0 axis_slv_vip_i ( + .aclk(m_axis_aclk), // input wire aclk + .aresetn(m_axis_aresetn), // input wire aresetn + .s_axis_tvalid(m_axis_tvalid), // input wire [0 : 0] s_axis_tvalid + .s_axis_tready(m_axis_tready), // output wire [0 : 0] s_axis_tready + .s_axis_tdata(m_axis_tdata) // input wire [31 : 0] s_axis_tdata +); + +// Instantiate DUT. +mr_buffer_v1_0 + #(.NM(4), .N(4), .B(8)) + DUT ( + .trigger(trigger), + .s00_axi_aclk(aclk), + .s00_axi_aresetn(aresetn), + .s00_axi_awaddr(m_axi_awaddr), + .s00_axi_awprot(m_axi_awprot), + .s00_axi_awvalid(m_axi_awvalid), + .s00_axi_awready(m_axi_awready), + .s00_axi_wdata(m_axi_wdata), + .s00_axi_wstrb(m_axi_wstrb), + .s00_axi_wvalid(m_axi_wvalid), + .s00_axi_wready(m_axi_wready), + .s00_axi_bresp(m_axi_bresp), + .s00_axi_bvalid(m_axi_bvalid), + .s00_axi_bready(m_axi_bready), + .s00_axi_araddr(m_axi_araddr), + .s00_axi_arprot(m_axi_arprot), + .s00_axi_arvalid(m_axi_arvalid), + .s00_axi_arready(m_axi_arready), + .s00_axi_rdata(m_axi_rdata), + .s00_axi_rresp(m_axi_rresp), + .s00_axi_rvalid(m_axi_rvalid), + .s00_axi_rready(m_axi_rready), + .s00_axis_aclk(s_axis_aclk), + .s00_axis_aresetn(s_axis_aresetn), + .s00_axis_tready(s_axis_tready), + .s00_axis_tdata({s_axis_tdata^s_axis_tdata,s_axis_tdata}), + .s00_axis_tstrb(), + .s00_axis_tlast(), + .s00_axis_tvalid(s_axis_tvalid), + .m00_axis_aclk(m_axis_aclk), + .m00_axis_aresetn(m_axis_aresetn), + .m00_axis_tvalid(m_axis_tvalid), + .m00_axis_tdata(m_axis_tdata), + .m00_axis_tstrb(), + .m00_axis_tlast(), + .m00_axis_tready(m_axis_tready)); + +// Declare AXI master VIP agent. +axi_vip_0_mst_t mst_agent; + +// Declare AXIS master VIP agent. +axi4stream_vip_1_mst_t axis_mst_agent; + +// Declare AXIS slave VIP agent. +axi4stream_vip_0_slv_t axis_slv_agent; + +initial begin + // Create agentt. + mst_agent = new("axi master vip agent", axi_vip_i.inst.IF); + axis_mst_agent = new("axis master vip agent", axis_mst_vip_i.inst.IF); + axis_slv_agent = new("axis slave vip agent", axis_slv_vip_i.inst.IF); + + // Set tag for agent to ease debug. + mst_agent.set_agent_tag("AXI Master VIP"); + axis_mst_agent.set_agent_tag("AXIS Master VIP"); + axis_slv_agent.set_agent_tag("AXIS Slave VIP"); + + // Set print verbosity level. + mst_agent.set_verbosity(400); + axis_mst_agent.set_verbosity(400); + axis_slv_agent.set_verbosity(400); + + /*************************************************************************************************** + * When bus is in idle, it must drive everything to 0.otherwise it will + * trigger false assertion failure from axi_protocol_chekcer + ***************************************************************************************************/ + + axis_mst_agent.vif_proxy.set_dummy_drive_type(XIL_AXI4STREAM_VIF_DRIVE_NONE); + axis_slv_agent.vif_proxy.set_dummy_drive_type(XIL_AXI4STREAM_VIF_DRIVE_NONE); + + /* + DW_CAPTURE_REG : 1 bit. + -> 0 : disable capture. + -> 1 : enable capture. + + DR_START_REG : 1 bit. + -> 0 : stop. + -> 1 : start. + + trigger : 1 bit. + -> 0 : wait. + -> 1 : start capture. + */ + + // Start the agent. + mst_agent.start_master(); + axis_mst_agent.start_master(); + axis_slv_agent.start_slave(); + + // dready generator. + ready_gen = axis_slv_agent.driver.create_ready("ready_gen"); + ready_gen.set_ready_policy(XIL_AXI4STREAM_READY_GEN_EVENTS); + ready_gen.set_low_time(4); + ready_gen.set_event_count(25); + + trigger <= 0; + + // Reset sequence. + aresetn = 0; + m_axis_aresetn = 0; + s_axis_aresetn = 0; + #200ns; + + repeat(16) @(negedge aclk); + + aresetn = 1; + m_axis_aresetn = 1; + s_axis_aresetn = 1; + #200ns; + + repeat(2) begin + + // Write DW_CAPTURE_REG. + data_wr = 1; + mst_agent.AXI4LITE_WRITE_BURST(addr_DW_CAPTURE_REG,prot,data_wr,resp); + #200ns; + + // // Send data. + // fork + // gen_0(8,10); + // join_none + + // #1us; + + // Trigger. + trigger <= 1; + #1us; + + // Send data. + fork + gen_0(8,0); + join + + #1us; + trigger <= 0; + + // Write DW_CAPTURE_REG. + data_wr = 0; + mst_agent.AXI4LITE_WRITE_BURST(addr_DW_CAPTURE_REG,prot,data_wr,resp); + #200ns; + + #1us; + + // Write DW_CAPTURE_REG. + data_wr = 1; + mst_agent.AXI4LITE_WRITE_BURST(addr_DW_CAPTURE_REG,prot,data_wr,resp); + #200ns; + + #200ns; + + // Write DW_CAPTURE_REG. + data_wr = 0; + mst_agent.AXI4LITE_WRITE_BURST(addr_DW_CAPTURE_REG,prot,data_wr,resp); + #200ns; + + // Send data. + fork + gen_0(16,10); + join_none + + #100ns; + trigger <= 1; + + #1us; + + // Write DR_START_REG. + data_wr = 1; + mst_agent.AXI4LITE_WRITE_BURST(addr_DR_START_REG,prot,data_wr,resp); + #200ns; + + // Write DR_START_REG. + data_wr = 0; + mst_agent.AXI4LITE_WRITE_BURST(addr_DR_START_REG,prot,data_wr,resp); + #200ns; + + #2us; + + axis_slv_agent.driver.send_tready(ready_gen); + + // Write DR_START_REG. + data_wr = 1; + mst_agent.AXI4LITE_WRITE_BURST(addr_DR_START_REG,prot,data_wr,resp); + #200ns; + + // Write DR_START_REG. + data_wr = 0; + mst_agent.AXI4LITE_WRITE_BURST(addr_DR_START_REG,prot,data_wr,resp); + #200ns; + + trigger <= 0; + + #1us; + + end + + $finish(); +end + +// aclk. +always begin + #10; aclk = ~aclk; +end + +//m_axis_aclk +always begin + #4; m_axis_aclk = ~m_axis_aclk; +end + +//s_axis_aclk +always begin + #3; s_axis_aclk = ~s_axis_aclk; +end + +task gen_0(input bit [31:0] cnt, input bit [31:0] delay); + static int data_val_cnt = 0; + // Create transaction. + axi4stream_transaction wr_transaction; + wr_transaction = axis_mst_agent.driver.create_transaction("Master 0 VIP write transaction"); + + // Set transaction parameters. +// wr_transaction.set_xfer_alignment(XIL_AXI4STREAM_XFER_RANDOM); + wr_transaction.set_xfer_alignment(XIL_AXI4STREAM_XFER_ALL_SET); + wr_transaction.set_delay(0); + + // Send transactions. + for (int i=0; i < cnt; i++) + begin + // WR_TRANSACTION_FAIL: assert(wr_transaction.randomize()); + wr_transaction.set_data('{data_val_cnt+1,data_val_cnt+2,data_val_cnt+3,data_val_cnt+4}); + axis_mst_agent.driver.send(wr_transaction); + data_val_cnt += 4; + end +endtask + +endmodule diff --git a/firmware/ip/mr_buffer_et/src/tb/tb_behav_waves.wcfg b/firmware/ip/mr_buffer_et/src/tb/tb_behav_waves.wcfg new file mode 100644 index 0000000..3e0a9a0 --- /dev/null +++ b/firmware/ip/mr_buffer_et/src/tb/tb_behav_waves.wcfg @@ -0,0 +1,306 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + NM + NM + + + N + N + + + B + B + + + s_axis_aclk + s_axis_aclk + + + s_axis_aresetn + s_axis_aresetn + + + s_axis_tready + s_axis_tready + + + s_axis_tvalid + s_axis_tvalid + + + s_axis_tdata[31:0] + s_axis_tdata[31:0] + + + DW_CAPTURE_REG + DW_CAPTURE_REG + + + DR_START_REG + DR_START_REG + + + trigger + trigger + + + DATA_WR_FSM_0 + label + + + addr_cnt[3:0] + addr_cnt[3:0] + UNSIGNEDDECRADIX + + + current_state + current_state + + + init_state + init_state + + + write_en + write_en + + + + WR_FIFO_0 + label + + + rstn + rstn + + + clk + clk + + + wr_en + wr_en + + + din[7:0] + din[7:0] + UNSIGNEDDECRADIX + + + full + full + + + rd_en + rd_en + + + dout[7:0] + dout[7:0] + UNSIGNEDDECRADIX + + + empty + empty + + + + WR_MEM_0 + label + + + clka + clka + + + ena + ena + + + wea + wea + + + dia[7:0] + dia[7:0] + UNSIGNEDDECRADIX + + + addra[3:0] + addra[3:0] + UNSIGNEDDECRADIX + + + doa[7:0] + doa[7:0] + + + clkb + clkb + + + enb + enb + + + web + web + + + dib[7:0] + dib[7:0] + + + addrb[3:0] + addrb[3:0] + UNSIGNEDDECRADIX + + + dob[7:0] + dob[7:0] + UNSIGNEDDECRADIX + + + + DATA_READER_FSM + label + + + mem_dout[31:0] + mem_dout[31:0] + + + mem_dout_r[31:0] + mem_dout_r[31:0] + + + NPOW + NPOW + + + current_state + current_state + + + addr_cnt[3:0] + addr_cnt[3:0] + UNSIGNEDDECRADIX + + + read_cnt[1:0] + read_cnt[1:0] + + + sel_cnt[1:0] + sel_cnt[1:0] + + + mem_addr[3:0] + mem_addr[3:0] + UNSIGNEDDECRADIX + + + + mem_dout_r[31:0] + mem_dout_r[31:0] + + + DATA_READER_FIFO + label + + rstn + rstn + + + clk + clk + + + wr_en + wr_en + + + din[7:0] + din[7:0] + + + full + full + + + rd_en + rd_en + + + dout[7:0] + dout[7:0] + + + empty + empty + + + + M_AXIS + label + + + m_axis_aresetn + m_axis_aresetn + + + m_axis_aclk + m_axis_aclk + + + m_axis_tready + m_axis_tready + + + m_axis_tvalid + m_axis_tvalid + + + m_axis_tdata[7:0] + m_axis_tdata[7:0] + UNSIGNEDDECRADIX + + + m_axis_tstrobe[0:0] + m_axis_tstrobe[0:0] + + + m_axis_tlast + m_axis_tlast + + + + NPOW + NPOW + + diff --git a/firmware/ip/mr_buffer_et/xgui/mr_buffer_et_v1_0.tcl b/firmware/ip/mr_buffer_et/xgui/mr_buffer_et_v1_0.tcl new file mode 100644 index 0000000..2f38e18 --- /dev/null +++ b/firmware/ip/mr_buffer_et/xgui/mr_buffer_et_v1_0.tcl @@ -0,0 +1,99 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "B" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "N" -parent ${Page_0} + ipgui::add_param $IPINST -name "NM" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to update B when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to validate B + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to validate C_S00_AXI_ADDR_WIDTH + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to validate C_S00_AXI_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + +proc update_PARAM_VALUE.NM { PARAM_VALUE.NM } { + # Procedure called to update NM when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NM { PARAM_VALUE.NM } { + # Procedure called to validate NM + return true +} + + +proc update_MODELPARAM_VALUE.NM { MODELPARAM_VALUE.NM PARAM_VALUE.NM } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NM}] ${MODELPARAM_VALUE.NM} +} + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + +proc update_MODELPARAM_VALUE.B { MODELPARAM_VALUE.B PARAM_VALUE.B } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.B}] ${MODELPARAM_VALUE.B} +} + +proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH} +} + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + diff --git a/firmware/ip/mr_buffer_et/xgui/mr_buffer_et_v1_1.tcl b/firmware/ip/mr_buffer_et/xgui/mr_buffer_et_v1_1.tcl new file mode 100644 index 0000000..2f38e18 --- /dev/null +++ b/firmware/ip/mr_buffer_et/xgui/mr_buffer_et_v1_1.tcl @@ -0,0 +1,99 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "B" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "N" -parent ${Page_0} + ipgui::add_param $IPINST -name "NM" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to update B when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.B { PARAM_VALUE.B } { + # Procedure called to validate B + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to validate C_S00_AXI_ADDR_WIDTH + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to validate C_S00_AXI_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + +proc update_PARAM_VALUE.NM { PARAM_VALUE.NM } { + # Procedure called to update NM when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NM { PARAM_VALUE.NM } { + # Procedure called to validate NM + return true +} + + +proc update_MODELPARAM_VALUE.NM { MODELPARAM_VALUE.NM PARAM_VALUE.NM } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NM}] ${MODELPARAM_VALUE.NM} +} + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + +proc update_MODELPARAM_VALUE.B { MODELPARAM_VALUE.B PARAM_VALUE.B } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.B}] ${MODELPARAM_VALUE.B} +} + +proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH} +} + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + diff --git a/firmware/ip/qick_com/component.xml b/firmware/ip/qick_com/component.xml new file mode 100644 index 0000000..b5120b9 --- /dev/null +++ b/firmware/ip/qick_com/component.xml @@ -0,0 +1,1284 @@ + + + Fermi + user + qick_com + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + c_aresetn + + + + + + + RST + + + c_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + ps_aresetn + + + + + + + RST + + + ps_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + c_clk + + + + + + + CLK + + + c_clk + + + + + + ASSOCIATED_RESET + c_aresetn + + + ASSOCIATED_BUSIF + QCOM + + + + + ps_clk + + + + + + + CLK + + + ps_clk + + + + + + ASSOCIATED_RESET + ps_aresetn + + + ASSOCIATED_BUSIF + s_axi + + + + + QCOM + + + + + + + a_dt + + + qcom_dt1_i + + + + + flag + + + qcom_flag_o + + + + + rdy + + + qcom_rdy_o + + + + + Enable + + + qcom_en_i + + + + + dt_in_2 + + + qcom_dt2_o + + + + + Operation + + + qcom_op_i + + + + + dt_in_1 + + + qcom_dt1_o + + + + + dt_valid + + + qcom_vld_o + + + + + + t_aresetn + + + + + + + RST + + + t_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + t_clk + + + + + + + CLK + + + t_clk + + + + + + ASSOCIATED_RESET + t_aresetn:qproc_start_o + + + ASSOCIATED_BUSIF + QPROC_CTRL + + + + + QPROC_CTRL + Processor Control + + + + + + + start + + + qproc_start_o + + + + + + + false + + + + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axi_qick_com + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 6f4768b4 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axi_qick_com + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 6f4768b4 + + + + + xilinx_testbench + Test Bench + :vivado.xilinx.com:simulation.testbench + tb_qcom + + xilinx_testbench_view_fileset + + + + viewChecksum + a040b0f3 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 12885887 + + + + + + + c_clk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + c_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + t_clk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + t_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ps_clk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ps_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qcom_en_i + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qcom_op_i + + in + + 4 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qcom_dt1_i + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qcom_rdy_o + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qcom_dt1_o + + out + + 31 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qcom_dt2_o + + out + + 31 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qcom_vld_o + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qcom_flag_o + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync_i + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + qproc_start_o + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + pmod_i + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + pmod_o + + out + + 3 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + qcom_do + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + + + DEBUG + Debug + 0 + + + SYNC + Sync + 0 + + + + + + choice_list_98b8ce5c + 0 + 1 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_8098f617 + 0 + 1 + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/_qcom_ips.sv + systemVerilogSource + + + src/qcom_link.sv + systemVerilogSource + + + src/qick_cmd.sv + systemVerilogSource + + + src/qick_com.sv + systemVerilogSource + + + src/axi_slv_qcom.vhd + vhdlSource + + + src/axi_qick_com.sv + systemVerilogSource + CHECKSUM_4b928db9 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/_qcom_ips.sv + systemVerilogSource + + + src/qcom_link.sv + systemVerilogSource + + + src/qick_cmd.sv + systemVerilogSource + + + src/qick_com.sv + systemVerilogSource + + + src/axi_slv_qcom.vhd + vhdlSource + + + src/axi_qick_com.sv + systemVerilogSource + + + + xilinx_testbench_view_fileset + + src/TB/tb_qcom.sv + systemVerilogSource + USED_IN_implementation + USED_IN_simulation + USED_IN_synthesis + + + src/TB/tb_behav.wcfg + unknown + USED_IN_simulation + + + + xilinx_xpgui_view_fileset + + xgui/qick_com_v1_0.tcl + tclSource + CHECKSUM_12885887 + XGUI_VERSION_2 + + + + qick_com + + + DEBUG + Debug + 0 + + + Component_Name + axis_qick_com_v1_0 + + + SYNC + Processor Syncronization + 0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /UserIP + + qick_com + package_project + 7 + 2024-06-20T14:01:58Z + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/qick_com/src/TB/tb_behav.wcfg b/firmware/ip/qick_com/src/TB/tb_behav.wcfg new file mode 100644 index 0000000..adc8c9f --- /dev/null +++ b/firmware/ip/qick_com/src/TB/tb_behav.wcfg @@ -0,0 +1,408 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + ps_clk + ps_clk + + + c_clk + c_clk + + + rst_ni + rst_ni + + + cmd_ack_i + cmd_ack_i + + + p_op_r[3:0] + p_op_r[3:0] + + + cmd_op[3:0] + cmd_op[3:0] + + + cmd_req_o + cmd_req_o + + + cmd_op_o[3:0] + cmd_op_o[3:0] + + + QCOM_CFG[3:0] + QCOM_CFG[3:0] + + + QCOM_CTRL[7:0] + QCOM_CTRL[7:0] + + + RAXI_DT1[31:0] + RAXI_DT1[31:0] + SIGNEDDECRADIX + + + c_en_i + c_en_i + + + c_op_i[4:0] + c_op_i[4:0] + UNSIGNEDDECRADIX + + + cmd_op[3:0] + cmd_op[3:0] + + + cmd_cnt[7:0] + cmd_cnt[7:0] + HEXRADIX + + + cmd_req + cmd_req + + + ready + ready + + + qcom_header[3:0] + qcom_header[3:0] + + + tx_vld_i + tx_vld_i + #E0FFFF + true + + + tx_header_i[3:0] + tx_header_i[3:0] + #E0FFFF + true + + + tx_data_i[31:0] + tx_data_i[31:0] + #E0FFFF + true + + + c_cmd_i + c_cmd_i + #00FFFF + true + + + c_cmd_i + c_cmd_i + #00FFFF + true + + + c_dt1_i[31:0] + c_dt1_i[31:0] + #00FFFF + true + UNSIGNEDDECRADIX + + + c_op_i[4:0] + c_op_i[4:0] + #00FFFF + true + UNSIGNEDDECRADIX + + + qcom_dt1_o + qcom_dt1_o + #0000FF + true + + + qcom_dt2_o + qcom_dt2_o + #0000FF + true + + + qcom_vld_o + qcom_vld_o + #0000FF + true + + + qcom_flag_o + qcom_flag_o + #0000FF + true + + + qproc_start_o + qproc_start_o + #0000FF + true + + + pmod_o[3:0] + pmod_o[3:0] + #0000FF + true + + + + QCOM_CFG[3:0] + QCOM_CFG[3:0] + UNSIGNEDDECRADIX + + + qcom_dt1_o[31:0] + qcom_dt1_o[31:0] + SIGNEDDECRADIX + + + qcom_dt2_o[31:0] + qcom_dt2_o[31:0] + UNSIGNEDDECRADIX + + + qcom_flag_o + qcom_flag_o + + + qcom_tx_st[31:0] + qcom_tx_st[31:0] + #FF00FF + true + + + qcom_rx_st[31:0] + qcom_rx_st[31:0] + #FF00FF + true + + + qctrl_st[31:0] + qctrl_st[31:0] + #FF00FF + true + + + tx_vld + tx_vld + + + qcom_sync + qcom_sync + + + qctrl_sync + qctrl_sync + + + start_req + start_req + + + t_start_req + t_start_req + + + t_start_ack + t_start_ack + + + start_ack + start_ack + + + tx_vld_i + tx_vld_i + #808000 + true + + + tx_header_i[3:0] + tx_header_i[3:0] + #808000 + true + + + tx_data_i[31:0] + tx_data_i[31:0] + #808000 + true + + + qcom_rx_st[31:0] + qcom_rx_st[31:0] + #FF00FF + true + + + qctrl_st[31:0] + qctrl_st[31:0] + + + rx_vld_o + rx_vld_o + #808000 + true + + + rx_header_o[2:0] + rx_header_o[2:0] + #808000 + true + + + rx_data_o[32:0] + rx_data_o[32:0] + #808000 + true + SIGNEDDECRADIX + + + qcom_vld_o + qcom_vld_o + + + cmd_req_i + cmd_req_i + + + cmd_op_i[3:0] + cmd_op_i[3:0] + + + qcom_flag_o + qcom_flag_o + + + qcom_dt1_o[31:0] + qcom_dt1_o[31:0] + + + qcom_dt2_o[31:0] + qcom_dt2_o[31:0] + + + c_clk + c_clk + + + t_clk + t_clk + + + ps_clk + ps_clk + + + sync_i + sync_i + #00FFFF + true + + + label + qproc_start_o + qproc_start_o + #0000FF + true + qproc_start_1 + + + label + qproc_start_o + qproc_start_o + #0000A0 + true + qproc_start_2 + + + qctrl_st[31:0] + qctrl_st[31:0] + + + tx_sync + tx_sync + + + rx_sync + rx_sync + + + t_start_req + t_start_req + + + t_start_ack + t_start_ack + + + start_ack + start_ack + + + qctrl_st[31:0] + qctrl_st[31:0] + + + tx_sync + tx_sync + #808000 + true + + + rx_sync + rx_sync + #808000 + true + + + t_start_req + t_start_req + + + t_start_ack + t_start_ack + #808000 + true + + + start_ack + start_ack + #808000 + true + + diff --git a/firmware/ip/qick_com/src/TB/tb_qcom.sv b/firmware/ip/qick_com/src/TB/tb_qcom.sv new file mode 100644 index 0000000..a3ea223 --- /dev/null +++ b/firmware/ip/qick_com/src/TB/tb_qcom.sv @@ -0,0 +1,409 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : mdife +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/10ps + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +`define T_T_CLK 1 // 1.66 // Half Clock Period for Simulation +`define T_C_CLK 2 +`define T_PS_CLK 5 // Half Clock Period for Simulation + +localparam DEBUG = 0; // Debugging + +module tb_qcom(); + +/////////////////////////////////////////////////////////////////////////////// + +// VIP Agent +axi_mst_0_mst_t axi_mst_0_agent; +xil_axi_prot_t prot = 0; +xil_axi_resp_t resp; + +// Signals +reg c_clk, t_clk, ps_clk; +reg rst_ni; +reg[31:0] data_wr = 32'h12345678; + +//AXI-LITE +wire [7:0] s_axi_awaddr ; +wire [2:0] s_axi_awprot ; +wire s_axi_awvalid ; +wire s_axi_awready ; +wire [31:0] s_axi_wdata ; +wire [3:0] s_axi_wstrb ; +wire s_axi_wvalid ; +wire s_axi_wready ; +wire [1:0] s_axi_bresp ; +wire s_axi_bvalid ; +wire s_axi_bready ; +wire [7:0] s_axi_araddr ; +wire [2:0] s_axi_arprot ; +wire s_axi_arvalid ; +wire s_axi_arready ; +wire [31:0] s_axi_rdata ; +wire [1:0] s_axi_rresp ; +wire s_axi_rvalid ; +wire s_axi_rready ; + +reg sync_i; +////////////////////////////////////////////////////////////////////////// +// CLK Generation +initial begin + c_clk = 1'b0; + forever # (`T_C_CLK) c_clk = ~c_clk; +end +initial begin + t_clk = 1'b0; + forever # (`T_T_CLK) t_clk = ~t_clk; +end +initial begin + ps_clk = 1'b0; + forever # (`T_PS_CLK) ps_clk = ~ps_clk; +end +initial begin + sync_i = 1'b0; + forever # (1000) sync_i = ~sync_i; +end + + + + +reg c_cmd_i ; +reg [4 :0] c_op_i; + +// Register ADDRESS +parameter QCOM_CTRL = 0 * 4 ; +parameter QCOM_CFG = 1 * 4 ; +parameter RAXI_DT1 = 2 * 4 ; +parameter QCOM_FLAG = 7 * 4 ; +parameter QCOM_DT1 = 8 * 4 ; +parameter QCOM_DT2 = 9 * 4 ; +parameter QCOM_STATUS = 10 * 4 ; + + +////////////////////////////////////////////////////////////////////////// +// AXI AGENT +axi_mst_0 axi_mst_0_i ( + .aclk (ps_clk ), + .aresetn (rst_ni ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) +); + +reg [ 3:0] pmod_si ; +wire[ 3:0] pmod_o1, pmod_o2, pmod_i ; +reg [31:0] c_dt1_i, c_dt2_i, c_dt3_i ; + +////////////////////////////////////////////////////////////////////////// +// QCOM1 +axi_qick_com # ( + .DEBUG ( DEBUG ) +) QICK_COM_1 ( + .c_clk ( c_clk ) , + .c_aresetn ( rst_ni ) , + .t_clk ( t_clk ) , + .t_aresetn ( rst_ni ) , + .ps_clk ( ps_clk ) , + .ps_aresetn ( rst_ni ) , + .sync_i ( sync_i ) , + .qcom_en_i ( c_cmd_i ) , + .qcom_op_i ( c_op_i ) , + .qcom_dt1_i ( c_dt1_i ) , + .qcom_rdy_o ( ready ) , + .qcom_dt1_o ( qcom_dt1_o ) , + .qcom_dt2_o ( qcom_dt2_o ) , + .qcom_vld_o ( qcom_vld_o ) , + .qcom_flag_o ( qcom_flag_o ) , + .qproc_start_o ( qproc_start_o1 ) , + .pmod_i ( pmod_i ) , + .pmod_o ( pmod_o1 ) , + .s_axi_awaddr ( s_axi_awaddr ) , + .s_axi_awprot ( s_axi_awprot ) , + .s_axi_awvalid ( s_axi_awvalid ) , + .s_axi_awready ( s_axi_awready ) , + .s_axi_wdata ( s_axi_wdata ) , + .s_axi_wstrb ( s_axi_wstrb ) , + .s_axi_wvalid ( s_axi_wvalid ) , + .s_axi_wready ( s_axi_wready ) , + .s_axi_bresp ( s_axi_bresp ) , + .s_axi_bvalid ( s_axi_bvalid ) , + .s_axi_bready ( s_axi_bready ) , + .s_axi_araddr ( s_axi_araddr ) , + .s_axi_arprot ( s_axi_arprot ) , + .s_axi_arvalid ( s_axi_arvalid ) , + .s_axi_arready ( s_axi_arready ) , + .s_axi_rdata ( s_axi_rdata ) , + .s_axi_rresp ( s_axi_rresp ) , + .s_axi_rvalid ( s_axi_rvalid ) , + .s_axi_rready ( s_axi_rready ) , + .qcom_do ( qcom_do ) +); +////////////////////////////////////////////////////////////////////////// +// QCOM +axi_qick_com # ( + .DEBUG ( DEBUG ) +) QICK_COM_2 ( + .c_clk ( c_clk ) , + .c_aresetn ( rst_ni ) , + .t_clk ( t_clk ) , + .t_aresetn ( rst_ni ) , + .ps_clk ( ps_clk ) , + .ps_aresetn ( rst_ni ) , + .sync_i ( sync_i ) , + .qcom_en_i ( 0 ) , + .qcom_op_i ( 0 ) , + .qcom_dt1_i ( 0 ) , + .qcom_rdy_o ( ) , + .qcom_dt1_o ( ) , + .qcom_dt2_o ( ) , + .qcom_vld_o ( ) , + .qcom_flag_o ( ) , + .qproc_start_o ( qproc_start_o2 ) , + .pmod_i ( pmod_o1 ) , + .pmod_o ( pmod_o2 ) , + .s_axi_awaddr ( 0 ) , + .s_axi_awprot ( 0 ) , + .s_axi_awvalid ( 0 ) , + .s_axi_awready ( ) , + .s_axi_wdata ( 0 ) , + .s_axi_wstrb ( 0 ) , + .s_axi_wvalid ( 0 ) , + .s_axi_wready ( ) , + .s_axi_bresp ( ) , + .s_axi_bvalid ( ) , + .s_axi_bready ( ) , + .s_axi_araddr ( 0 ) , + .s_axi_arprot ( 0 ) , + .s_axi_arvalid ( 0 ) , + .s_axi_arready ( ) , + .s_axi_rdata ( ) , + .s_axi_rresp ( ) , + .s_axi_rvalid ( ) , + .s_axi_rready ( ) , + .qcom_do ( ) +); + + + +reg tx_loop; + +initial begin + START_SIMULATION(); + SIM_BUG(); + //SIM_CMD_TPROC(); + //SIM_CMD_PYTHON(); + //TEST_AXI () ; + //#2000; + // SIM_RX(); + // SIM_TX(); + +end + +task START_SIMULATION (); begin + $display("START SIMULATION"); + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb_qcom.axi_mst_0_i.inst.IF); + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + // Start agents. + axi_mst_0_agent.start_master(); + rst_ni = 1'b0; + c_cmd_i = 1'b0 ; + c_op_i = 5'd0; + c_dt1_i = 0; + c_dt2_i = 0; + c_dt3_i = 0; + pmod_si = 0; + tx_loop = 1'b0 ; + #25; + @ (posedge ps_clk); #0.1; + rst_ni = 1'b1; + +end +endtask + +assign pmod_i = tx_loop ? pmod_o1 : pmod_si; + +integer conf; + +task SIM_BUG(); begin + $display("SIM BUG"); + + for (conf = 1 ; conf <= 15; conf=conf+1) begin + WRITE_AXI( QCOM_CFG , conf); // DATA + WRITE_AXI( RAXI_DT1 , 1001001*conf); // DATA + CMD_SEND_32B_DT1 (); + #1000; + WRITE_AXI( RAXI_DT1 , 2002001*conf); // DATA + CMD_SEND_32B_DT2 (); + #1000; + end +end +endtask + + +task SIM_CMD_PYTHON(); begin + $display("SIM Command from PYTHON"); + @ (posedge c_clk); #0.1; + WRITE_AXI( RAXI_DT1 , -1); // DATA + CMD_SET_FLG (); + CMD_CLR_FLG (); + WRITE_AXI( QCOM_CFG , 7); // DATA + WRITE_AXI( RAXI_DT1 , 700000007); // DATA + + CMD_SEND_8B_DT1 (); + CMD_SEND_8B_DT2 (); + CMD_SEND_16B_DT1 (); + #250; + CMD_SEND_16B_DT2 (); + #250; + CMD_SEND_32B_DT1 (); + #500; + CMD_SEND_32B_DT2 (); + #500; + CMD_SYNC_START (); + #4000; + WRITE_AXI( RAXI_DT1 , 0 ); // DATA + CMD_SEND_32B_DT1 (); + #500; + CMD_SEND_32B_DT2 (); + #500; +end +endtask + +task CMD_RUN(); begin + c_cmd_i = 1'b1 ; + @ (posedge c_clk); #0.1; + c_cmd_i = 1'b0 ; + @ (posedge c_clk); #0.1; + wait (ready == 1'b1); +end +endtask + +task SIM_CMD_TPROC(); begin + $display("SIM Command from TPROC"); + c_dt1_i = -1; + + @ (posedge c_clk); #0.1; + c_op_i = 5'd8; //SET FLAG + CMD_RUN(); + + @ (posedge c_clk); #0.1; + c_op_i = 5'd0; //CLR FLAG + CMD_RUN(); + + @ (posedge c_clk); #0.1; + c_op_i = 5'd2; //SEND 8_BIT + CMD_RUN(); + @ (posedge c_clk); #0.1; + c_op_i = 5'd3; //SEND 8_BIT + CMD_RUN(); + + @ (posedge c_clk); #0.1; + c_op_i = 5'd4; //SEND 16_BIT + CMD_RUN(); + @ (posedge c_clk); #0.1; + c_op_i = 5'd5; //SEND 16_BIT + CMD_RUN(); + + @ (posedge c_clk); #0.1; + c_op_i = 5'd6; //SEND 32_BIT + CMD_RUN(); + @ (posedge c_clk); #0.1; + c_op_i = 5'd7; //SEND 32_BIT + CMD_RUN(); + + @ (posedge c_clk); #0.1; + c_op_i = 5'd10; //SYNC + CMD_RUN(); + end + #4000; +endtask + +task CMD_CLR_FLG (); + WRITE_AXI( QCOM_CTRL , 1 + 2 * 0); +endtask +task CMD_SEND_8B_DT1 (); + WRITE_AXI( QCOM_CTRL , 1 + 2 * 2); +endtask +task CMD_SEND_8B_DT2 (); + WRITE_AXI( QCOM_CTRL , 1 + 2 * 3); +endtask +task CMD_SEND_16B_DT1 (); + WRITE_AXI( QCOM_CTRL , 1 + 2 * 4); +endtask +task CMD_SEND_16B_DT2 (); + WRITE_AXI( QCOM_CTRL , 1 + 2 * 5); +endtask +task CMD_SEND_32B_DT1 (); + WRITE_AXI( QCOM_CTRL , 1 + 2 * 6); +endtask +task CMD_SEND_32B_DT2 (); + WRITE_AXI( QCOM_CTRL , 1 + 2 * 7); +endtask +task CMD_SET_FLG (); + WRITE_AXI( QCOM_CTRL , 1 + 2 * 8); +endtask +task CMD_SYNC_START (); + WRITE_AXI( QCOM_CTRL , 1 + 2 * 10); +endtask + + + +task WRITE_AXI(integer PORT_AXI, DATA_AXI); begin + @ (posedge ps_clk); #0.1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(PORT_AXI, prot, DATA_AXI, resp); + end +endtask + +task TEST_AXI (); begin + $display("-----Writting AXI "); + WRITE_AXI( QCOM_CTRL , 1 *2+1); // Set Flag + WRITE_AXI( QCOM_CTRL , 0 *2+1); // Clear Flag + WRITE_AXI( QCOM_CTRL , 1 *2+1); // Set Flag + WRITE_AXI( QCOM_CTRL , 0 *2+1); // Clear Flag + WRITE_AXI( RAXI_DT1 , -1); // DATA + WRITE_AXI( QCOM_CTRL , 2 *2+1); // Send 8bit (1) + WRITE_AXI( RAXI_DT1 , 8); // DATA + WRITE_AXI( QCOM_CTRL , 10 *2+1); // Send 8bit (2) + WRITE_AXI( QCOM_CTRL , 3 *2+1); // SYNC_START + WRITE_AXI( RAXI_DT1 , -1); // DATA + WRITE_AXI( QCOM_CTRL , 4 *2+1); // Send 16bit (1) + WRITE_AXI( RAXI_DT1 , 16); // DATA + WRITE_AXI( QCOM_CTRL , 12 *2+1); // Send 16bit (2) + WRITE_AXI( RAXI_DT1 , -1); // DATA + WRITE_AXI( QCOM_CTRL , 6 *2+1); // Send 32bit (1) + WRITE_AXI( RAXI_DT1 , 32); // DATA + WRITE_AXI( QCOM_CTRL , 14 *2+1); // Send 32bit (2) +end +endtask + + + +endmodule + + + + diff --git a/firmware/ip/qick_com/src/_qcom_ips.sv b/firmware/ip/qick_com/src/_qcom_ips.sv new file mode 100644 index 0000000..e22486d --- /dev/null +++ b/firmware/ip/qick_com/src/_qcom_ips.sv @@ -0,0 +1,29 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_5 +// Version : 1 +/////////////////////////////////////////////////////////////////////////////// + +/// Clock Domain Register Change +module sync_reg # ( + parameter DW = 32 +)( + input wire [DW-1:0] dt_i , + input wire clk_i , + input wire rst_ni , + output wire [DW-1:0] dt_o ); + +(* ASYNC_REG = "TRUE" *) reg [DW-1:0] data_cdc, data_r ; +always_ff @(posedge clk_i) + if(!rst_ni) begin + data_cdc <= 0; + data_r <= 0; + end else begin + data_cdc <= dt_i; + data_r <= data_cdc; + end +assign dt_o = data_r ; + +endmodule diff --git a/firmware/ip/qick_com/src/axi_qick_com.sv b/firmware/ip/qick_com/src/axi_qick_com.sv new file mode 100644 index 0000000..38bd411 --- /dev/null +++ b/firmware/ip/qick_com/src/axi_qick_com.sv @@ -0,0 +1,196 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_6_20 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : Board Communication Peripheral +////////////////////////////////////////////////////////////////////////////// + +module axi_qick_com # ( + parameter SYNC = 0 , + parameter DEBUG = 0 +)( +// Core and AXI CLK & RST + input wire c_clk , + input wire c_aresetn , + input wire t_clk , + input wire t_aresetn , + input wire ps_clk , + input wire ps_aresetn , +// QCOM INTERFACE (c_clk) + input wire qcom_en_i , + input wire [4:0] qcom_op_i , + input wire [31:0] qcom_dt1_i , + output reg qcom_rdy_o , + output reg [31:0] qcom_dt1_o , + output reg [31:0] qcom_dt2_o , + output reg qcom_vld_o , + output reg qcom_flag_o , +// TPROC CONTROL (t_clk) + input wire sync_i , + output reg qproc_start_o , +// PMOD COM (c_clk) + input wire [ 3:0] pmod_i , + output reg [ 3:0] pmod_o , +// AXI-Lite DATA Slave I/F (ps_clk) + input wire [5:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + input wire [31:0] s_axi_wdata , + input wire [ 3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + output wire [ 1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + input wire [ 5:0] s_axi_araddr , + input wire [ 2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + output wire [31:0] s_axi_rdata , + output wire [ 1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , +///// DEBUG + output wire [31:0] qcom_do +); + +// Signal Declaration +/////////////////////////////////////////////////////////////////////////////// + +wire [31:0] qcom_flag, qcom_dt_1, qcom_dt_2 ; // QCOM Outputs +wire [31:0] qcom_tx_dt_ds, qcom_rx_dt_ds, qcom_status_ds, qcom_ds; +wire [15:0] qcom_debug_ds ; + +wire [31:0] xreg_tx_dt, xreg_rx_dt ; +wire [23:0] xreg_debug ; + +// QCOM Control (From Python and tProc) +wire [ 3:0] cmd_op ; +wire [31:0] cmd_dt ; +wire [ 7:0] cmd_cnt ; + +wire [ 7:0] QCOM_CTRL ; +wire [ 3:0] QCOM_CFG ; +wire [31:0] RAXI_DT1 ; + +wire sync_s ; +reg qproc_start_s ; + + +qick_cmd #( + .OP_DW ( 4 ), + .DT_QTY ( 1 ) +) CMD ( + .clk_i ( c_clk ), + .rst_ni ( c_aresetn ), + .ps_clk_i ( ps_clk ), + .ps_rst_ni ( ps_aresetn ), + .c_en_i ( qcom_en_i ), + .c_op_i ( qcom_op_i ), + .c_dt_i ( '{qcom_dt1_i} ), + .p_ctrl_i ( QCOM_CTRL[4:0] ), + .p_dt_i ( '{RAXI_DT1} ), + .cmd_req_o ( cmd_req ), + .cmd_ack_i ( cmd_ack ), + .cmd_op_o ( cmd_op ), + .cmd_dt_o ( '{cmd_dt} ), + .cmd_cnt_do ( cmd_cnt )); + +qick_com QCOM ( + .c_clk_i ( c_clk ), + .c_rst_ni ( c_aresetn ), + .t_clk_i ( t_clk ), + .t_rst_ni ( t_aresetn ), + .qcom_cfg_i ( QCOM_CFG[3:0] ), + .pulse_i ( sync_s ), + .cmd_req_i ( cmd_req ), + .cmd_ack_o ( cmd_ack ), + .cmd_op_i ( cmd_op ), + .cmd_dt_i ( cmd_dt ), + .qcom_rdy_o ( qcom_rdy_o ), + .qcom_dt1_o ( qcom_dt1_o ), + .qcom_dt2_o ( qcom_dt2_o ), + .qcom_vld_o ( qcom_vld_o ), + .qcom_flag_o ( qcom_flag_o ), + .qproc_start_o ( qproc_start_s ), + .pmod_i ( pmod_i ), + .pmod_o ( pmod_o ), + .qcom_tx_dt_do ( qcom_tx_dt_ds ), + .qcom_rx_dt_do ( qcom_rx_dt_ds ), + .qcom_status_do ( qcom_status_ds ), + .qcom_debug_do ( qcom_debug_ds ), + .qcom_do ( qcom_ds )); + + + +/////////////////////////////////////////////////////////////////////////////// +// AXI Registers +/////////////////////////////////////////////////////////////////////////////// +axi_slv_qcom QCOM_xREG ( + .aclk ( ps_clk ) , + .aresetn ( ps_aresetn ) , + .awaddr ( s_axi_awaddr [5:0] ) , + .awprot ( s_axi_awprot ) , + .awvalid ( s_axi_awvalid ) , + .awready ( s_axi_awready ) , + .wdata ( s_axi_wdata ) , + .wstrb ( s_axi_wstrb ) , + .wvalid ( s_axi_wvalid ) , + .wready ( s_axi_wready ) , + .bresp ( s_axi_bresp ) , + .bvalid ( s_axi_bvalid ) , + .bready ( s_axi_bready ) , + .araddr ( s_axi_araddr ) , + .arprot ( s_axi_arprot ) , + .arvalid ( s_axi_arvalid ) , + .arready ( s_axi_arready ) , + .rdata ( s_axi_rdata ) , + .rresp ( s_axi_rresp ) , + .rvalid ( s_axi_rvalid ) , + .rready ( s_axi_rready ) , + .QCOM_CTRL ( QCOM_CTRL ) , + .QCOM_CFG ( QCOM_CFG ) , + .RAXI_DT1 ( RAXI_DT1 ) , + .QCOM_FLAG ( qcom_flag_o ) , + .QCOM_DT_1 ( qcom_dt1_o ) , + .QCOM_DT_2 ( qcom_dt2_o ) , + .QCOM_STATUS ( qcom_status_ds ) , + .QCOM_TX_DT ( xreg_tx_dt ) , + .QCOM_RX_DT ( xreg_rx_dt ) , + .QCOM_DEBUG ( xreg_debug ) ); + + + +/////////////////////////////////////////////////////////////////////////////// +// SYNC OPTION +/////////////////////////////////////////////////////////////////////////////// +generate + if (SYNC == 0) begin : SYNC_NO + assign sync_s = 0 ; + assign qproc_start_o = 0 ; + end else if (SYNC == 1) begin : SYNC_YES + assign sync_s = sync_i ; + assign qproc_start_o = qproc_start_s ; + end +endgenerate +/////////////////////////////////////////////////////////////////////////////// +// DEBUG +/////////////////////////////////////////////////////////////////////////////// + +generate + if (DEBUG == 0) begin : DEBUG_NO + assign xreg_tx_dt = '{default:'0} ; + assign xreg_rx_dt = '{default:'0} ; + assign xreg_debug = '{default:'0} ; + end else if (DEBUG == 1) begin : DEBUG_YES + assign xreg_tx_dt = qcom_tx_dt_ds; + assign xreg_rx_dt = qcom_rx_dt_ds; + assign xreg_debug = {qcom_debug_ds, cmd_cnt}; + end +endgenerate + +endmodule diff --git a/firmware/ip/qick_com/src/axi_slv_qcom.vhd b/firmware/ip/qick_com/src/axi_slv_qcom.vhd new file mode 100644 index 0000000..2eb3774 --- /dev/null +++ b/firmware/ip/qick_com/src/axi_slv_qcom.vhd @@ -0,0 +1,521 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv_qcom is Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); Port ( + aclk : in std_logic; + aresetn : in std_logic; + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + -- Registers. + QCOM_CTRL : out std_logic_vector ( 7 downto 0) ; + QCOM_CFG : out std_logic_vector ( 3 downto 0) ; + RAXI_DT1 : out std_logic_vector (31 downto 0) ; + QCOM_FLAG : in std_logic ; + QCOM_DT_1 : in std_logic_vector (31 downto 0) ; + QCOM_DT_2 : in std_logic_vector (31 downto 0) ; + QCOM_STATUS : in std_logic_vector ( 7 downto 0) ; + QCOM_TX_DT : in std_logic_vector (31 downto 0) ; + QCOM_RX_DT : in std_logic_vector (31 downto 0) ; + QCOM_DEBUG : in std_logic_vector (23 downto 0) ); +end axi_slv_qcom; + +architecture rtl of axi_slv_qcom is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + + signal slv_reg0_rst : std_logic; +begin + -- I/O Connections assignments + + awready <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= "00000000000000000000000000000011"; + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + -- Reset + if (unsigned(slv_reg0) /= 0) then slv_reg0_rst <= ('1'); else slv_reg0_rst <= ('0'); end if; + if (slv_reg0_rst = '1') then slv_reg0 <= (others => '0'); end if; + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + -- 4 : TAVG_LOW_REG (r). + -- 5 : TAVG_HIGH_REG(r). + + process (slv_reg0, slv_reg1, slv_reg2, QCOM_FLAG, QCOM_DT_1, QCOM_DT_2, QCOM_STATUS, QCOM_TX_DT, QCOM_RX_DT, QCOM_DEBUG, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= "00000000000000000000000000000000"; + when b"0100" => + reg_data_out <= "00000000000000000000000000000000"; + when b"0101" => + reg_data_out <= "00000000000000000000000000000000"; + when b"0110" => + reg_data_out <= "00000000000000000000000000000000"; + when b"0111" => + reg_data_out <= "0000000000000000000000000000000" & QCOM_FLAG; + when b"1000" => + reg_data_out <= QCOM_DT_1; + when b"1001" => + reg_data_out <= QCOM_DT_2; + when b"1010" => + reg_data_out <= "000000000000000000000000" & QCOM_STATUS; + when b"1011" => + reg_data_out <= "00000000000000000000000000000000"; + when b"1100" => + reg_data_out <= "00000000000000000000000000000000"; + when b"1101" => + reg_data_out <= QCOM_TX_DT; + when b"1110" => + reg_data_out <= QCOM_RX_DT; + when b"1111" => + reg_data_out <= "00000000" & QCOM_DEBUG; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + +-- Output Registers. + +QCOM_CTRL <= slv_reg0( 7 downto 0); +QCOM_CFG <= slv_reg1( 3 downto 0); +RAXI_DT1 <= slv_reg2(31 downto 0); + +end rtl; + + + + diff --git a/firmware/ip/qick_com/src/qcom_link.sv b/firmware/ip/qick_com/src/qcom_link.sv new file mode 100644 index 0000000..2035e0a --- /dev/null +++ b/firmware/ip/qick_com/src/qcom_link.sv @@ -0,0 +1,372 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_5 +// Version : 1 +/////////////////////////////////////////////////////////////////////////////// + +module qcom_link ( +// Core and AXI CLK & RST + input wire c_clk_i , + input wire c_rst_ni , +// Config + input wire [ 3:0] tick_cfg , // Pulse Duration of PMOD measured in c_clk +// Transmittion + input wire tx_vld_i , + output reg tx_ready_o , + input wire [ 3:0] tx_header_i , + input wire [31:0] tx_data_i , +// Command Processing + output reg rx_vld_o , + output reg [ 2:0] rx_header_o , + output reg [32:0] rx_data_o , +// PMOD COM + input wire [ 3:0] pmod_i , + output reg [ 3:0] pmod_o , +///// DEBUG + output wire [31:0] qcom_link_do + ); + +/////////////////////////////////////////////////////////////////////////////// +// ###### # # +// # # # # +// # # # # +// ###### # +// # # # # +// # # # # +// # # # # +/////////////////////////////////////////////////////////////////////////////// +reg rx_idle_s, rx_header_s, rx_end_s, rx_fault_s ; + + +/////////////////////////////////////////////////////////////////////////////// +// Sync Input and PMOD[3] edge detection +reg [3:0] pmod_r, pmod_r2; +(* ASYNC_REG = "TRUE" *) reg [3:0] pmod_cdc ; +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) begin + pmod_cdc <= 4'd0; + pmod_r <= 4'd0; + pmod_r2 <= 4'd0; + end else begin + pmod_cdc <= pmod_i; + pmod_r <= pmod_cdc; + pmod_r2 <= pmod_r; + end +end +assign rx_new_dt = pmod_r2[3] ^ pmod_r[3]; + +/////////////////////////////////////////////////////////////////////////////// +// RX Store Data +reg [32:0] rx_dt; +reg [2:0] rx_header_r ; +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) begin + rx_dt <= '{default:'0} ; + rx_header_r <= '{default:'0} ; + end else begin + if (rx_new_dt) begin + if ( rx_idle_s ) rx_header_r <= { pmod_r[2], pmod_r[1], pmod_r[0] } ; + else rx_dt <= { rx_dt[29:0], pmod_r[2], pmod_r[1], pmod_r[0] } ; + end else if (rx_end_s | rx_fault_s) begin + rx_dt <= '{default:'0} ; + end + end +end + +/////////////////////////////////////////////////////////////////////////////// +// RX Decoding +reg [3:0] rx_pack_size; +always_comb begin + case ( rx_header_r ) + 3'b000 : rx_pack_size = 4'd1 ; // CLEAR FLAG (1) + 3'b001 : rx_pack_size = 4'd1 ; // SET FLAG (1) + 3'b010 : rx_pack_size = 4'd4 ; // Receive 8 Bits (4) + 3'b011 : rx_pack_size = 4'd4 ; // Receive SYNC Command + 3'b100 : rx_pack_size = 4'd7 ; // Receive 16 Bits (7) + 3'b110 : rx_pack_size = 4'd12; // Receive 32 Bits (12) + default : rx_pack_size = 4'd0; + endcase +end + +/////////////////////////////////////////////////////////////////////////////// +// RX Measurment +reg [4:0] rx_time_out_cnt, rx_tick_cnt ; +reg [3:0] rx_pack_cnt ; + +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) begin + rx_tick_cnt <= 5'd1; + rx_time_out_cnt <= 5'd0; + rx_pack_cnt <= 8'd1; + end else begin + if (rx_new_dt) begin + rx_pack_cnt <= rx_pack_cnt + 1'b1 ; + rx_time_out_cnt <= 4'd0; + end else begin + if (rx_header_s) rx_tick_cnt <= rx_tick_cnt + 1'b1; + else if ( rx_idle_s ) rx_tick_cnt <= 5'd1; + if (rx_idle_s) begin + rx_pack_cnt <= 8'd1; + rx_time_out_cnt <= 4'd0; + end else + rx_time_out_cnt <= rx_time_out_cnt + 1'b1 ; + end + end +end + +wire rx_time_out, rx_last_dt, rx_single_dt; +assign rx_last_dt = rx_new_dt & (rx_pack_size == rx_pack_cnt) ; // Last Data Received +assign rx_single_dt = rx_new_dt & (rx_pack_size == 4'd1) ; // Package has only Header +assign rx_time_out = rx_time_out_cnt > rx_tick_cnt ; // New Data was not received in time + +/////////////////////////////////////////////////////////////////////////////// +///// RX STATE +typedef enum { RX_IDLE, RX_HEADER, RX_DATA, RX_END, RX_FAULT, RX_CHECK, RX_RTZ } TYPE_RX_ST ; +(* fsm_encoding = "one_hot" *) TYPE_RX_ST rx_st; +TYPE_RX_ST rx_st_nxt; + + +always_ff @ (posedge c_clk_i) begin + if ( !c_rst_ni ) rx_st <= RX_IDLE; + else rx_st <= rx_st_nxt; +end +always_comb begin + rx_st_nxt = rx_st; // Default Current + rx_idle_s = 1'b0; + rx_header_s = 1'b0; + rx_end_s = 1'b0; + rx_fault_s = 1'b0; + case (rx_st) + RX_IDLE : begin + rx_idle_s = 1'b1; + if ( rx_new_dt ) begin + if (pmod_r[3]) rx_st_nxt = RX_HEADER; // First Transition 0 to 1 + else rx_st_nxt = RX_RTZ; // Tx is returning to Zero + end + end + RX_HEADER : begin + rx_header_s = 1'b1; + if ( rx_single_dt ) rx_st_nxt = RX_END; // Package has only Header + else if ( rx_new_dt ) rx_st_nxt = RX_DATA; // New Data Received + else if ( rx_time_out ) rx_st_nxt = RX_FAULT; + end + RX_DATA : begin + if ( rx_last_dt ) rx_st_nxt = RX_END; // Last Data Received + else if ( rx_time_out ) rx_st_nxt = RX_FAULT; // No Data Received + end + RX_END : begin + rx_end_s = 1'b1; + rx_st_nxt = RX_CHECK; + end + RX_CHECK : begin + if ( rx_new_dt ) begin + if ( pmod_r[3] ) rx_st_nxt = RX_FAULT; // Extra Data Received + else rx_st_nxt = RX_RTZ; // Tx is returning to Zero + end else if (rx_time_out) rx_st_nxt = RX_IDLE; // No more Data is received + end + RX_FAULT : begin + rx_fault_s = 1'b1; + rx_st_nxt = RX_IDLE; + end + RX_RTZ : begin + rx_st_nxt = RX_IDLE; + end + endcase +end + + + +/////////////////////////////////////////////////////////////////////////////// +// ####### # # +// # # # +// # # # +// # # +// # # # +// # # # +// # # # +/////////////////////////////////////////////////////////////////////////////// +reg tx_idle_s, tx_header_s, tx_data_s, tx_end_s; +reg tick_clk ; //Clock (PMOD[3})should be updated +reg tick_dt ; //Data (PMOD[2:0})should be updated +reg tick_en ; // Enable tick Generation + + +/////////////////////////////////////////////////////////////////////////////// +// TX Encode Header and Check Command +reg [ 3:0] tx_pack_size, tx_pack_size_r; +reg [35:0] tx_dt ; +reg tx_ok; + +always_comb begin + tx_pack_size = 4'd0; + tx_dt = 33'd0 ; + tx_ok = 1'b0; + case ( tx_header_i[3:1] ) + 3'b000 : begin // CLEAR FLAG (1) + tx_pack_size = 4'd1; + tx_dt = {tx_header_i, 32'd0}; + tx_ok = 1'b1; + end + 3'b001 : begin // SET FLAG (1) + tx_pack_size = 4'd1; + tx_dt = {tx_header_i, 32'd0}; + tx_ok = 1'b1; + end + 3'b010 : begin // Send 8 Bits (4) + tx_pack_size = 4'd4; + tx_dt = {tx_header_i, tx_data_i[7:0], 24'd0}; + tx_ok = 1'b1; + end + 3'b011 : begin // Send SYNC COMMAND + tx_pack_size = 4'd4; + tx_dt = {tx_header_i, 32'd0}; + tx_ok = 1'b1; + end + 3'b100 : begin // Send 16 Bits (7) + tx_pack_size = 4'd7; + tx_dt = {tx_header_i, 1'b0, tx_data_i[15:0], 15'd0}; + tx_ok = 1'b1; + end + 3'b110 : begin // Send 32 Bits (12) + tx_pack_size = 4'd12; + tx_dt = {tx_header_i, tx_data_i[31:0]}; + tx_ok = 1'b1; + end + default : begin + tx_pack_size = 4'd0; + tx_dt = 33'd0 ; + tx_ok = 1'b0; + end + endcase +end + +/////////////////////////////////////////////////////////////////////////////// +// TX Registers + +reg [ 3:0] tx_pmod ; // PMOD values for OUTPUT [3]Clk [2:0]Data +reg [35:0] tx_buff ; //Shift Register For Par 2 Ser. (Data encoded on tx_dt) +reg [ 3:0] tx_pack_cnt; //Number of Packages transmited (Total Defined in tx_pack_size) + +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) begin + tx_pmod <= '{default:'0} ; + tx_buff <= '{default:'0} ; + tx_pack_cnt <= 4'd0; + tx_pack_size_r <= 4'd0; + end else begin + if (tx_vld_i) begin + tx_buff <= tx_dt; + tx_pack_cnt <= 8'd0; + tx_pack_size_r <= tx_pack_size; + end else if ( tx_idle_s ) begin + tx_pmod[3] <= 1'b0; + end else if ( tick_clk ) + tx_pmod[3] <= ~tx_pmod[3]; + if (tick_dt) begin + tx_pack_cnt <= tx_pack_cnt + 1'b1 ; + tx_buff <= tx_buff << 3; + tx_pmod[2] <= tx_buff[35] ; + tx_pmod[1] <= tx_buff[34] ; + tx_pmod[0] <= tx_buff[33] ; + end + end +end + +assign tx_last_dt = (tx_pack_cnt == tx_pack_size_r) ; + + +/////////////////////////////////////////////////////////////////////////////// +// TICK GENERATOR + +reg [ 3:0] tx_tick_cnt ; // NUmber of c_clk in current PMOD Pulse + +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) begin + tx_tick_cnt <= 1'b0; + tick_clk <= 1'b0; + tick_dt <= 1'b0; + end else begin + if (tick_en) begin + if (tx_tick_cnt == tick_cfg) begin + tick_clk <= 1'b1; + tx_tick_cnt <= 4'd1; + end else begin + tick_clk <= 1'b0; + tx_tick_cnt <= tx_tick_cnt + 1'b1 ; + end + if (tx_tick_cnt == tick_cfg>>1) tick_dt <= 1'b1; + else tick_dt <= 1'b0; + end else begin + tx_tick_cnt <= tick_cfg>>1 ; + tick_dt <= 1'b0; + tick_clk <= 1'b0; + end + end +end + +/////////////////////////////////////////////////////////////////////////////// +///// TX STATE +typedef enum { TX_IDLE, TX_DT, TX_CLK, TX_END, TX_RTZ, TX_WAIT } TYPE_TX_ST ; +(* fsm_encoding = "one_hot" *) TYPE_TX_ST tx_st; +TYPE_TX_ST tx_st_nxt; + + +always_ff @ (posedge c_clk_i) begin + if ( !c_rst_ni ) tx_st <= TX_IDLE; + else tx_st <= tx_st_nxt; +end +always_comb begin + tx_st_nxt = tx_st; // Default Current + tick_en = 1'b0; + tx_idle_s = 1'b0; + case (tx_st) + TX_IDLE : begin + tx_idle_s = 1'b1; + if ( tx_vld_i & tx_ok ) tx_st_nxt = TX_DT; + end + TX_DT : begin + tick_en = 1'b1; + tx_data_s = 1'b1; + if ( tick_clk ) tx_st_nxt = TX_CLK; + end + TX_CLK : begin + tick_en = 1'b1; + tx_header_s = 1'b1; + if ( tick_dt ) begin + if ( tx_last_dt ) tx_st_nxt = TX_END; + else tx_st_nxt = TX_DT; + end + end + TX_END : begin + tick_en = 1'b1; + tx_end_s = 1'b1; + if (tx_pmod[3]) tx_st_nxt = TX_RTZ; + else tx_st_nxt = TX_WAIT; + end + TX_RTZ : begin + tick_en = 1'b1; + if ( tick_clk ) tx_st_nxt = TX_WAIT; + end + TX_WAIT : begin + tick_en = 1'b1; + if ( tick_dt ) tx_st_nxt = TX_IDLE; + end + + endcase +end + +/////////////////////////////////////////////////////////////////////////////// +// OUTPUTS +/////////////////////////////////////////////////////////////////////////////// + +assign tx_ready_o = tx_idle_s; +assign rx_vld_o = rx_end_s; +assign rx_header_o = rx_header_r; +assign rx_data_o = rx_dt; +assign pmod_o = tx_pmod; +assign qcom_link_do = 0; + +endmodule + diff --git a/firmware/ip/qick_com/src/qick_cmd.sv b/firmware/ip/qick_com/src/qick_cmd.sv new file mode 100644 index 0000000..852d1fa --- /dev/null +++ b/firmware/ip/qick_com/src/qick_cmd.sv @@ -0,0 +1,119 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_5 +// Version : 1 +/////////////////////////////////////////////////////////////////////////////// +// This module receives commands from the Processor and from Python and generates the Request signal +/* +qick_cmd #( + .OP_DW ( 5 ), + .DT_QTY ( 4 ) +) CMD_SYNC ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .c_en_i ( c_en_i ), + .c_op_i ( c_op_i ), + .c_dt_i ( c_dt_i ), + .p_ctrl_i ( p_ctrl_i ), + .p_dt_i ( p_dt_i ), + .cmd_req_o ( cmd_req_o ), + .cmd_ack_i ( cmd_ack_i ), + .cmd_op_o ( cmd_op_o ), + .cmd_dt_o ( cmd_dt_o ), + .cmd_cnt_do ( cmd_cnt_do )); +*/ + +module qick_cmd #( + parameter OP_DW = 5 , + parameter DT_QTY = 4 +)( + input wire clk_i , + input wire rst_ni , + input wire ps_clk_i , + input wire ps_rst_ni , + // Command from tProcessor + input wire c_en_i , + input wire [4:0] c_op_i , + input wire [31:0] c_dt_i [DT_QTY] , + // Command from Python + input wire [OP_DW:0] p_ctrl_i , + input wire [31:0] p_dt_i [DT_QTY] , + // Command Execution + output wire cmd_req_o , + input wire cmd_ack_i , + output wire [OP_DW-1:0] cmd_op_o , + output wire [31:0] cmd_dt_o [DT_QTY], + output wire [7 :0] cmd_cnt_do ); + +// PS to Core Sincronization +/////////////////////////////////////////////////////////////////////////////// +// Register the Operation and generates one clock later the Enable. +reg [OP_DW-1:0] p_op_r; +reg p_ctrl_en, p_ctrl_en_r; +always_ff @(posedge ps_clk_i) + if (!ps_rst_ni) begin + p_op_r <= 0; + p_ctrl_en <= 1'b0; + p_ctrl_en_r <= 1'b0; + end else begin + if (p_ctrl_i[0]) + p_op_r <= p_ctrl_i[OP_DW:1]; + p_ctrl_en <= p_ctrl_i[0]; + p_ctrl_en_r <= p_ctrl_en; + end +wire p_en_r, p_en_r_t01; +sync_reg # ( + .DW ( 1 ) +) sync_tx_i ( + .dt_i ( p_ctrl_en_r ) , + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .dt_o ( p_en_r ) ); + +reg p_en_2r; +always_ff @(posedge clk_i) if (!rst_ni) p_en_2r <= 1'b0; else p_en_2r <= p_en_r; + +assign p_en_r_t01 = !p_en_2r & p_en_r; + +// COMMAND OPERATON +reg cmd_req; +reg [OP_DW-1:0] cmd_op; +reg [31:0] cmd_dt [DT_QTY]; +// Command Debug +reg [ 3:0] p_cmd_cnt, c_cmd_cnt; + +always_ff @(posedge clk_i) + if (!rst_ni) begin + cmd_req <= 1'b0; + cmd_op <= '{default:'0}; + cmd_dt <= '{default:'0}; + p_cmd_cnt <= 3'd0; + c_cmd_cnt <= 3'd0; + end else begin + if (p_en_r_t01 & !cmd_ack_i) begin + cmd_req <= 1'b1; + cmd_op <= p_op_r ; + cmd_dt <= p_dt_i ; + p_cmd_cnt <= p_cmd_cnt + 1'b1; + end else if (c_en_i & !cmd_ack_i) begin + cmd_req <= 1'b1; + cmd_op <= c_op_i ; + cmd_dt <= c_dt_i ; + c_cmd_cnt <= c_cmd_cnt + 1'b1; + end else + if ( cmd_ack_i ) cmd_req <= 1'b0; + end + +// OUTPUTS +/////////////////////////////////////////////////////////////////////////////// +assign cmd_req_o = cmd_req; +assign cmd_op_o = cmd_op; +assign cmd_dt_o = cmd_dt; + +// DEBUG +/////////////////////////////////////////////////////////////////////////////// +assign cmd_cnt_do ={ c_cmd_cnt, p_cmd_cnt }; + +endmodule \ No newline at end of file diff --git a/firmware/ip/qick_com/src/qick_com.sv b/firmware/ip/qick_com/src/qick_com.sv new file mode 100644 index 0000000..0fbb700 --- /dev/null +++ b/firmware/ip/qick_com/src/qick_com.sv @@ -0,0 +1,407 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_5 +// Version : 1 +/////////////////////////////////////////////////////////////////////////////// + +module qick_com ( +// Core and AXI CLK & RST + input wire c_clk_i , + input wire c_rst_ni , + input wire t_clk_i , + input wire t_rst_ni , +// QCOM INTERFACE + input wire pulse_i , + input wire [3:0] qcom_cfg_i , +// QCOM INTERFACE + input wire cmd_req_i , + output wire cmd_ack_o , + input wire [3:0] cmd_op_i , + input wire [31:0] cmd_dt_i , + output reg qcom_rdy_o , + output reg [31:0] qcom_dt1_o , + output reg [31:0] qcom_dt2_o , + output reg qcom_vld_o , + output reg qcom_flag_o , +// TPROC CONTROL + output reg qproc_start_o , +// PMOD COM + input wire [ 3:0] pmod_i , + output wire [ 3:0] pmod_o , +// DEBUG + output wire [31:0] qcom_tx_dt_do , + output wire [31:0] qcom_rx_dt_do , + output wire [31:0] qcom_status_do , + output wire [15:0] qcom_debug_do , + output wire [31:0] qcom_do ); + +// Signal Declaration +/////////////////////////////////////////////////////////////////////////////// +reg t_start_ack; +reg cmd_end, start_req; + +// Register Inputs +/////////////////////////////////////////////////////////////////////////////// +wire [31:0] qcom_dt ; +wire [ 3:0] qcom_header ; +wire [ 1:0] qcom_dt_size ; + +assign qcom_type = cmd_op_i[3]; +assign qcom_dt_size = cmd_op_i[2:1] ; +assign qcom_dt_dst = cmd_op_i[0]; + +assign qcom_header = { qcom_dt_size, qcom_type, qcom_dt_dst}; +assign qcom_dt = cmd_dt_i; +assign qcom_sync = ( cmd_op_i[3:0] == 4'b1010 ); + + + +/////////////////////////////////////////////////////////////////////////////// +// C CLOCK SYNC +reg c_sync_r2 ; +sync_reg # ( + .DW ( 1 ) +) c_sync_pulse ( + .dt_i ( pulse_i ) , + .clk_i ( c_clk_i ) , + .rst_ni ( c_rst_ni ) , + .dt_o ( c_sync_r ) ); +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) c_sync_r2 <= 1'b0; + else c_sync_r2 <= c_sync_r; +end +assign c_sync_t01 = !c_sync_r2 & c_sync_r ; + + +/////////////////////////////////////////////////////////////////////////////// +// ####### # # +// # # # +// # # # +// # # +// # # # +// # # # +// # # # +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// TX Control state +typedef enum { TX_IDLE, TX_SEND, TX_WSYNC, TX_WRDY, TX_WCMD } TYPE_TX_ST ; +(* fsm_encoding = "sequential" *) TYPE_TX_ST qcom_tx_st; +TYPE_TX_ST qcom_tx_st_nxt; + +reg tx_sync ; + +always_ff @ (posedge c_clk_i) begin + if ( !c_rst_ni ) qcom_tx_st <= TX_IDLE; + else qcom_tx_st <= qcom_tx_st_nxt; +end +reg tx_vld, qready; + +always_comb begin + qcom_tx_st_nxt = qcom_tx_st; // Default Current + tx_vld = 1'b0; + qready = 1'b0; + tx_sync = 1'b0; + case (qcom_tx_st) + TX_IDLE : begin + qready = 1'b1; + if ( cmd_req_i ) + if ( qcom_sync ) + qcom_tx_st_nxt = TX_WSYNC; + else begin + qcom_tx_st_nxt = TX_SEND; + tx_vld = 1'b1; + end + end + TX_WSYNC : begin + if ( c_sync_t01 ) begin + tx_vld = 1'b1; + qcom_tx_st_nxt = TX_SEND; + end + end + TX_SEND : begin + if ( qcom_sync ) qcom_tx_st_nxt = TX_WCMD; + else qcom_tx_st_nxt = TX_WRDY; + end + TX_WRDY : begin + if ( tx_ready ) qcom_tx_st_nxt = TX_IDLE; + end + TX_WCMD : begin + tx_sync = 1'b1; + if ( cmd_end ) qcom_tx_st_nxt = TX_IDLE; + end + endcase +end + + +/////////////////////////////////////////////////////////////////////////////// +// ###### # # +// # # # # +// # # # # +// ###### # +// # # # # +// # # # # +// # # # # +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// RX Decoding +wire [32:0] rx_data; // Data Received +wire [ 2:0] rx_header; // Header Received +reg reg_sel ; // Write Register Selection +reg [31:0] new_dt ; // New Data to Register reg_sel +wire [ 1:0] reg_wr_size; // Write Size 1, 8, 16, or 32 Bits +reg rx_wreg, rx_wflg, rx_sync; + +assign reg_wr_size = rx_header[2:1]; + +always_comb begin + reg_sel = rx_data[32]; + new_dt = rx_data[31:0]; + rx_sync = 1'b0; + rx_wreg = 1'b0; + rx_wflg = 1'b0; + case ( reg_wr_size ) + 2'b00 : begin // 1 BIT + rx_wflg = 1'b1; + end + 2'b01 : begin // 8 BITS | SYNC + if ( rx_header[0] ) + rx_sync = 1'b1 ; + else begin + rx_wreg = 1'b1; + reg_sel = rx_data[8]; + new_dt = {24'd0, rx_data[7:0]}; + end + end + 2'b10 : begin // 16 BITS + rx_wreg = 1'b1; + reg_sel = rx_data[17]; + new_dt = {16'd0, rx_data[15:0]}; + end + 2'b11 : begin // 32 BIT + rx_wreg = 1'b1; + reg_sel = rx_data[32]; + new_dt = rx_data[31:0]; + end + default : begin // :P + rx_wreg = 1'b1; + reg_sel = rx_data[32]; + new_dt = rx_data[31:0]; + end + endcase +end + +assign rx_wreg_en = rx_vld & rx_wreg; +assign rx_wflg_en = rx_vld & rx_wflg; + +/////////////////////////////////////////////////////////////////////////////// +// Register Update +reg qflag_dt, rx_wreg_r ; +reg [31:0] qreg1_dt, qreg2_dt; +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) begin + qflag_dt <= 1'b0; + qreg1_dt <= '{default:'0} ; + qreg2_dt <= '{default:'0} ; + rx_wreg_r <= 1'b0; + end else begin + rx_wreg_r <= rx_wreg_en ; + if ( rx_wreg_en ) + case ( reg_sel ) + 1'b0 : qreg1_dt <= new_dt; // Reg_dt1 + 1'b1 : qreg2_dt <= new_dt; // Reg_dt2 + endcase + else if ( rx_wflg_en ) + qflag_dt <= rx_header[0]; // FLAG + + + end + +end + + +/////////////////////////////////////////////////////////////////////////////// +// RX +typedef enum { RX_IDLE, RX_CMD } TYPE_RX_ST ; + (* fsm_encoding = "sequential" *) TYPE_RX_ST qcom_rx_st; + TYPE_RX_ST qcom_rx_st_nxt; + +always_ff @ (posedge c_clk_i) begin + if ( !c_rst_ni ) qcom_rx_st <= RX_IDLE; + else qcom_rx_st <= qcom_rx_st_nxt; +end + +always_comb begin + qcom_rx_st_nxt = qcom_rx_st; // Default Current + case (qcom_rx_st) + RX_IDLE : + if ( rx_vld ) qcom_rx_st_nxt = RX_CMD; + RX_CMD : begin + qcom_rx_st_nxt = RX_IDLE; + end + endcase +end + + + + + +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR RESTART +assign qctrl_sync = tx_sync | rx_sync; + +// PULSE SYNC +/////////////////////////////////////////////////////////////////////////////// +// T CLOCK SYNC +reg t_sync_r2 ; +sync_reg # ( + .DW ( 1 ) +) t_sync_pulse ( + .dt_i ( pulse_i ) , + .clk_i ( t_clk_i ) , + .rst_ni ( t_rst_ni ) , + .dt_o ( t_sync_r ) ); + +always_ff @ (posedge t_clk_i, negedge t_rst_ni) begin + if (!t_rst_ni) t_sync_r2 <= 1'b0; + else t_sync_r2 <= t_sync_r; +end +assign t_sync_t01 = !t_sync_r2 & t_sync_r ; + + + + +/////////////////////////////////////////////////////////////////////////////// +typedef enum { QRST_IDLE, QRST_REQ, QRST_WSYNC, QRST_CMD } TYPE_QCTRL_ST ; + (* fsm_encoding = "sequential" *) TYPE_QCTRL_ST qctrl_st; + TYPE_QCTRL_ST qctrl_st_nxt; + +always_ff @ (posedge c_clk_i) begin + if ( !c_rst_ni ) qctrl_st <= QRST_IDLE; + else qctrl_st <= qctrl_st_nxt; +end + +always_comb begin + qctrl_st_nxt = qctrl_st; // Default Current + cmd_end = 1'b0; + start_req = 1'b0; + case (qctrl_st) + QRST_IDLE : + if ( qctrl_sync ) qctrl_st_nxt = QRST_REQ; + QRST_REQ : begin + start_req = 1'b1; + if ( start_ack ) qctrl_st_nxt = QRST_WSYNC; + end + QRST_WSYNC : begin + if ( c_sync_t01 ) qctrl_st_nxt = QRST_CMD; + end + QRST_CMD : begin + cmd_end = 1'b1; + if ( !start_ack ) qctrl_st_nxt = QRST_IDLE; + end + endcase +end + +/////////////////////////////////////////////////////////////////////////////// +// REQ - ACK SYNC +sync_reg # (.DW(1)) t_sync_start_req ( + .dt_i ( start_req ) , + .clk_i ( t_clk_i ) , + .rst_ni ( t_rst_ni ) , + .dt_o ( t_start_req ) ); + +sync_reg # (.DW(1)) c_sync_start_ack ( + .dt_i ( t_start_ack ) , + .clk_i ( c_clk_i ) , + .rst_ni ( c_rst_ni ) , + .dt_o ( start_ack ) ); + +reg [2:0] t_start_cnt; +reg t_start_r; + +always_ff @ (posedge t_clk_i, negedge t_rst_ni) begin + if (!t_rst_ni) begin + t_start_cnt <= 0; + t_start_ack <= 1'b0; + t_start_r <= 1'b0; + end else begin + if ( t_start_req ) t_start_ack <= 1'b1; + else if ( qproc_hit ) t_start_ack <= 1'b0; + + if ( qproc_hit ) t_start_r <= 1'b1; + else if ( t_start_cnt==3'd7 ) t_start_r <= 1'b0; + + if ( t_start_r ) t_start_cnt <= t_start_cnt+1'b1; + else t_start_cnt <= 0; + end +end + +assign qproc_hit = t_start_ack & t_sync_t01; + + +/////////////////////////////////////////////////////////////////////////////// +// INSTANCES +/////////////////////////////////////////////////////////////////////////////// + + +/////////////////////////////////////////////////////////////////////////////// +wire [3:0] tick_cfg ; +assign tick_cfg = qcom_cfg_i[3:0]; + +qcom_link QCOM_LINK ( + .c_clk_i ( c_clk_i ) , + .c_rst_ni ( c_rst_ni ) , + .tick_cfg ( tick_cfg ) , + .tx_vld_i ( tx_vld ) , + .tx_ready_o ( tx_ready ) , + .tx_header_i ( qcom_header ) , + .tx_data_i ( qcom_dt ) , + .rx_vld_o ( rx_vld ) , + .rx_header_o ( rx_header ) , + .rx_data_o ( rx_data ) , + .pmod_i ( pmod_i ) , + .pmod_o ( pmod_o ) , + .qcom_link_do ( ) +); + +/////////////////////////////////////////////////////////////////////////////// +// DEBUG +reg [3:0] sync_cnt; +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) begin + sync_cnt <= 0; + end else begin + if ( c_sync_t01 ) sync_cnt <= sync_cnt + 1'b1; + end +end + +assign qcom_tx_dt_do = qcom_dt; +assign qcom_rx_dt_do = rx_data; +assign qcom_status_do = {tx_ready, qctrl_st[1:0], qcom_tx_st[2:0], qcom_rx_st[1:0] }; +assign qcom_debug_do = {pulse_i, tx_ready, reg_wr_size[1:0], reg_sel, qcom_header[2:0], rx_header[2:0], sync_cnt[3:0] }; +assign qcom_do = 0; + +/////////////////////////////////////////////////////////////////////////////// +// OUTPUTS +/////////////////////////////////////////////////////////////////////////////// + +// OUT SIGNALS +assign qcom_rdy_o = qready; +assign qcom_dt1_o = qreg1_dt; +assign qcom_dt2_o = qreg2_dt; +assign qcom_vld_o = rx_wreg_r; +assign qcom_flag_o = qflag_dt; +assign qcom_do = 0; +assign qproc_start_o = t_start_r; +assign cmd_ack_o = ~qready; + + + + + +endmodule + + diff --git a/firmware/ip/qick_com/xgui/axis_qick_com_v1_0.tcl b/firmware/ip/qick_com/xgui/axis_qick_com_v1_0.tcl new file mode 100644 index 0000000..95980b7 --- /dev/null +++ b/firmware/ip/qick_com/xgui/axis_qick_com_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DEBUG" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + diff --git a/firmware/ip/qick_com/xgui/qick_com_v1_0.tcl b/firmware/ip/qick_com/xgui/qick_com_v1_0.tcl new file mode 100644 index 0000000..63a7910 --- /dev/null +++ b/firmware/ip/qick_com/xgui/qick_com_v1_0.tcl @@ -0,0 +1,46 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + #Adding Group + set Communication_Options [ipgui::add_group $IPINST -name "Communication Options" -parent ${Page_0}] + ipgui::add_param $IPINST -name "SYNC" -parent ${Communication_Options} -widget checkBox + + #Adding Group + set Debug [ipgui::add_group $IPINST -name "Debug" -parent ${Page_0}] + ipgui::add_param $IPINST -name "DEBUG" -parent ${Debug} -widget comboBox + + + +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + +proc update_PARAM_VALUE.SYNC { PARAM_VALUE.SYNC } { + # Procedure called to update SYNC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SYNC { PARAM_VALUE.SYNC } { + # Procedure called to validate SYNC + return true +} + + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + +proc update_MODELPARAM_VALUE.SYNC { MODELPARAM_VALUE.SYNC PARAM_VALUE.SYNC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SYNC}] ${MODELPARAM_VALUE.SYNC} +} + diff --git a/firmware/ip/qick_interfaces/Debug_Core.xml b/firmware/ip/qick_interfaces/Debug_Core.xml new file mode 100644 index 0000000..3d5fb8b --- /dev/null +++ b/firmware/ip/qick_interfaces/Debug_Core.xml @@ -0,0 +1,11 @@ + + + Fermi + user + Debug_Core + 1.0 + false + false + 1 + 1 + diff --git a/firmware/ip/qick_interfaces/Debug_Core_rtl.xml b/firmware/ip/qick_interfaces/Debug_Core_rtl.xml new file mode 100644 index 0000000..13b0581 --- /dev/null +++ b/firmware/ip/qick_interfaces/Debug_Core_rtl.xml @@ -0,0 +1,114 @@ + + + Fermi + user + Debug_Core_rtl + 1.0 + + + + Data_32_0 + 32 BIt Data + + + true + + + required + 32 + + + 32 + in + + 0 + + + + Data_32_1 + 32 BIt Data + + + true + + + 32 + + + 32 + in + + 0 + + + + Data_32_2 + 32 BIt Data + + + true + + + 32 + + + 32 + in + + 0 + + + + Data_32_3 + 32 BIt Data + + + true + + + 32 + + + required + 32 + in + + 0 + + + + Data_32_4 + 32 BIt Data + + + true + + + 32 + + + 32 + in + + 0 + + + + Data_32_5 + 32 BIt Data + + + true + + + 32 + + + 32 + in + + 0 + + + + diff --git a/firmware/ip/qick_interfaces/qick_peripheral.xml b/firmware/ip/qick_interfaces/qick_peripheral.xml new file mode 100644 index 0000000..f43f7eb --- /dev/null +++ b/firmware/ip/qick_interfaces/qick_peripheral.xml @@ -0,0 +1,11 @@ + + + Fermi + user + qick_peripheral + 1.0 + false + false + 1 + 1 + diff --git a/firmware/ip/qick_interfaces/qick_peripheral_rtl.xml b/firmware/ip/qick_interfaces/qick_peripheral_rtl.xml new file mode 100644 index 0000000..b96abf8 --- /dev/null +++ b/firmware/ip/qick_interfaces/qick_peripheral_rtl.xml @@ -0,0 +1,202 @@ + + + Fermi + user + qick_peripheral_rtl + 1.0 + + + + Enable + Peripheral Enable + + + true + + + required + 1 + + + required + 1 + in + + 0 + + + + Operation + Peripheral Operation + + + true + + + required + 5 + + + required + 5 + in + + 0 + + + + a_dt + Peripheral Data A + + + true + + + required + 32 + + + required + 32 + in + + 0 + + + + b_dt + Peripheral Data + + + true + + + 32 + + + 32 + in + + 0 + + + + c_dt + Peripheral Data + + + true + + + 32 + + + 32 + in + + 0 + + + + d_dt + Peripheral Data + + + true + + + 32 + + + 32 + in + + 0 + + + + rdy + Peripheral Ready + + + required + 1 + in + + + required + 1 + + 1 + + + + dt_in_1 + Peripheral Data Out + + + true + + + 32 + in + + + 32 + + 0 + + + + dt_in_2 + Peripheral Data Out + + + true + + + 32 + in + + + 32 + + 0 + + + + flag + Flag + + + true + + + 1 + in + + + 1 + + 0 + + + + dt_valid + Data Valid + + + true + + + 1 + in + + + 1 + + 0 + + + + diff --git a/firmware/ip/qick_interfaces/qick_qproc_ctrl.xml b/firmware/ip/qick_interfaces/qick_qproc_ctrl.xml new file mode 100644 index 0000000..a13a4cd --- /dev/null +++ b/firmware/ip/qick_interfaces/qick_qproc_ctrl.xml @@ -0,0 +1,11 @@ + + + Fermi + user + qick_qproc_control + 1.0 + false + false + 1 + 1 + diff --git a/firmware/ip/qick_interfaces/qick_qproc_ctrl_rtl.xml b/firmware/ip/qick_interfaces/qick_qproc_ctrl_rtl.xml new file mode 100644 index 0000000..d459ad4 --- /dev/null +++ b/firmware/ip/qick_interfaces/qick_qproc_ctrl_rtl.xml @@ -0,0 +1,36 @@ + + + Fermi + user + qick_qproc_control_rtl + 1.0 + + + + start + + + 1 + + + 1 + in + + 0 + + + + stop + + + 1 + + + 1 + in + + 0 + + + + diff --git a/firmware/ip/qick_interfaces/qproc_time_ctrl.xml b/firmware/ip/qick_interfaces/qproc_time_ctrl.xml new file mode 100644 index 0000000..76f7ea3 --- /dev/null +++ b/firmware/ip/qick_interfaces/qproc_time_ctrl.xml @@ -0,0 +1,11 @@ + + + Fermi + user + qick_time_control + 1.0 + false + false + 1 + 1 + diff --git a/firmware/ip/qick_interfaces/qproc_time_ctrl_rtl.xml b/firmware/ip/qick_interfaces/qproc_time_ctrl_rtl.xml new file mode 100644 index 0000000..0310cc9 --- /dev/null +++ b/firmware/ip/qick_interfaces/qproc_time_ctrl_rtl.xml @@ -0,0 +1,65 @@ + + + Fermi + user + qick_time_control_rtl + 1.0 + + + + time_rst + + + 1 + + + 1 + in + + 0 + + + + time_updt + + + 1 + + + 1 + in + + 0 + + + + time_init + + + 1 + + + 1 + in + + 0 + + + + time_dt + + + true + + + 32 + + + 32 + in + + 0 + + + + diff --git a/firmware/ip/qick_peripheral_template/component.xml b/firmware/ip/qick_peripheral_template/component.xml new file mode 100644 index 0000000..eb75c43 --- /dev/null +++ b/firmware/ip/qick_peripheral_template/component.xml @@ -0,0 +1,1203 @@ + + + Fermi + user + qick_peripheral + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + c_aresetn + + + + + + + RST + + + c_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + ps_aresetn + + + + + + + RST + + + ps_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + c_clk + + + + + + + CLK + + + c_clk + + + + + + ASSOCIATED_RESET + c_aresetn + + + ASSOCIATED_BUSIF + QP + + + + + ps_clk + + + + + + + CLK + + + ps_clk + + + + + + ASSOCIATED_RESET + ps_aresetn + + + ASSOCIATED_BUSIF + s_axi + + + + + QP + + + + + + + b_dt + + + qp_dt2_i + + + + + c_dt + + + qp_dt3_i + + + + + a_dt + + + qp_dt1_i + + + + + flag + + + qp_flag_o + + + + + d_dt + + + qp_dt4_i + + + + + rdy + + + qp_rdy_o + + + + + Enable + + + qp_en_i + + + + + dt_in_2 + + + qp_dt2_o + + + + + Operation + + + qp_op_i + + + + + dt_in_1 + + + qp_dt1_o + + + + + dt_valid + + + qp_vld_o + + + + + + + + s_axi + s_axi + + reg0 + reg0 + 0x0 + 0x1000 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axi_qick_peripheral + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + c1aa1824 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axi_qick_peripheral + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + c1aa1824 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 8269e14c + + + + + + + c_clk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + c_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ps_clk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ps_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_en_i + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_op_i + + in + + 4 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_dt1_i + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_dt2_i + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_dt3_i + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_dt4_i + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_rdy_o + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_dt1_o + + out + + 31 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_dt2_o + + out + + 31 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_vld_o + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_flag_o + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_signal_i + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + qp_vector_i + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + qp_signal_o + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qp_vector_o + + out + + 31 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 5 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + qp_do + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + DEBUG + Debug + 1 + + + INPUTS + Inputs + 0 + + + + + + choice_list_98b8ce5c + 0 + 1 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/_qp_ips.sv + systemVerilogSource + + + src/qick_periph.sv + systemVerilogSource + + + src/axi_slv_qp.vhd + vhdlSource + + + src/axi_qick_peripheral.sv + systemVerilogSource + CHECKSUM_25be0871 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/_qp_ips.sv + systemVerilogSource + + + src/qick_periph.sv + systemVerilogSource + + + src/axi_slv_qp.vhd + vhdlSource + + + src/axi_qick_peripheral.sv + systemVerilogSource + + + + xilinx_xpgui_view_fileset + + xgui/qick_peripheral_v1_0.tcl + tclSource + CHECKSUM_8269e14c + XGUI_VERSION_2 + + + + qick_peripheral + + + Component_Name + axis_qick_com_v1_0 + + + DEBUG + Debug + 1 + + + INPUTS + Inputs + 0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /UserIP + + qick_peripheral + package_project + 8 + 2024-01-04T12:49:10Z + + + 2022.1 + + + + + + + + + diff --git a/firmware/ip/qick_peripheral_template/src/TB/tb_enc.sv b/firmware/ip/qick_peripheral_template/src/TB/tb_enc.sv new file mode 100644 index 0000000..25070eb --- /dev/null +++ b/firmware/ip/qick_peripheral_template/src/TB/tb_enc.sv @@ -0,0 +1,203 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : mdife +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/10ps + +`define HP_PS_CLK 50 // Half Clock Period for Simulation +`define HP_C_CLK 5 // Half Clock Period for Simulation +`define HP_T_CLK 2 // Half Clock Period for Simulation + +localparam DEBUG = 1; // Debugging + +module tb_enc(); + +// Signals +/////////////////////////////////////////////////////////////////////////////// +reg c_clk, t_clk, ps_clk; +reg rst_n; +reg sync; +// CLK Generation +////////////////////////////////////////////////////////////////////////// +initial begin + ps_clk = 1'b0; + forever # (`HP_PS_CLK) ps_clk = ~ps_clk; +end +initial begin + c_clk = 1'b0; + forever # (`HP_C_CLK) c_clk = ~c_clk; +end +initial begin + t_clk = 1'b0; + forever # (`HP_T_CLK) t_clk = ~t_clk; +end +// Other Periodical Signals +////////////////////////////////////////////////////////////////////////// +initial begin + sync = 1'b0; + forever # (1000) sync = ~sync; +end + + + +reg [SMP_DW:0] data ; +wire [SMP_DW*SMP_CK-1:0] data_v ; + +reg [SMP_DW-1:0] data_0,data_1, data_2, data_3, data_4,data_5, data_6, data_7 ; + +assign data_7 = data[SMP_DW-1:0] ; +assign data_6 = data[SMP_DW-1:0] +1; +assign data_5 = data[SMP_DW-1:0] +2; +assign data_4 = data[SMP_DW-1:0] +3; +assign data_3 = data[SMP_DW-1:0] +4; +assign data_2 = data[SMP_DW-1:0] +8; +assign data_1 = data[SMP_DW-1:0] +10; +assign data_0 = data[SMP_DW-1:0] +13; + +assign data_v = {data_7, data_6, data_5, data_4,data_3, data_2, data_1, data_0}; + +parameter EFF_DW = 14 ; //Effective DAta Width +parameter SMP_DW = 16 ; +parameter SMP_CK = 8 ; +parameter DW = $clog2(SMP_CK) ; + + + +/////////////////////////////////////////////// +// DESIGN +////////////////////////////////////////// +assign clk_i = c_clk; +assign rst_ni = rst_n; + +/// Time Counter +////////////////////////////////////////////////////////////////////////// + // Clk is 300Mhz, Deat ime 100ns > 32 + +reg [28:0] time_cnt; +always_ff @(posedge clk_i) + if(!rst_ni) begin + time_cnt <= 0; + end else begin + if (cmp_event & !inhibit) + inhibit <= 1'b1; + else if (inhibit & !dead_time_hit) + time_cnt <= dead_time_cnt+1'b1; + else if (dead_time_hit) begin + inhibit <= 1'b0; + time_cnt <= 1'b1; + end + end + +assign trig = cmp_event & !inhibit ; + + + +wire [SMP_CK-1:0] cmp_unary_dt; + +threshold_comparator # ( + .EFF_DW ( EFF_DW ) , + .SMP_DW ( SMP_DW ) , + .SMP_CK ( SMP_CK ) + ) DUT_thc ( + .clk_i ( c_clk ) , + .rst_ni ( rst_n ) , + .en_i ( en_i ) , + .concat_dt_i ( data_v ) , + .th_i ( th_i ) , + .cmp_o ( cmp_unary_dt ) , + .vld_o ( cmp_event ) ); + +/// Priority Encoder +////////////////////////////////////////////////////////////////////////// +reg [DW-1:0] cmp_bin_dt ; + +priority_encoder # ( + .DW (DW) +) DUT ( + .clk_i ( c_clk ) , + .rst_ni ( rst_n ) , + .one_hot_dt_i ( cmp_unary_dt ) , + .bin_dt_o ( cmp_bin_dt ) , + .vld_o ( vld_o ) ); + +/// Dead Time +////////////////////////////////////////////////////////////////////////// + // Clk is 300Mhz, Deat ime 100ns > 32 +assign clk_i = c_clk; +assign rst_ni = rst_n; +reg [9:0] dead_time_cnt, dead_time_lenght; +reg inhibit; +assign dead_time_hit = dead_time_cnt == dead_time_lenght; +always_ff @(posedge clk_i) + if(!rst_ni) begin + dead_time_cnt <= 0; + inhibit <= 0; + end else begin + if (cmp_event & !inhibit) + inhibit <= 1'b1; + else if (inhibit & !dead_time_hit) + dead_time_cnt <= dead_time_cnt+1'b1; + else if (dead_time_hit) begin + inhibit <= 1'b0; + dead_time_cnt <= 1'b1; + end + end + +assign trig = cmp_event & !inhibit ; + + + + + + +initial begin + START_SIMULATION(); + SIM_ENC(); + +end +reg [EFF_DW-1:0]th_i; +reg en_i; + +integer i; + +task SIM_ENC(); begin + $display("SIM TX"); + # (5 * `HP_C_CLK); + + @ (posedge c_clk); #0.1; + + for (i=0;i<=2**EFF_DW;i=i+1) begin + @ (posedge tt ); + @ (posedge c_clk); #0.1; + data = i; + end +end +endtask + +assign tt = trig | ps_clk; + +task START_SIMULATION (); begin + $display("START SIMULATION"); +// Reset + rst_n = 1'b0; + en_i = 1'b0; + th_i = 15; + dead_time_lenght = 5; + data = 0; + #100; + @ (posedge ps_clk); #0.1; + rst_n = 1'b1; + + en_i = 1'b1; + + end +endtask + + +endmodule + + + + diff --git a/firmware/ip/qick_peripheral_template/src/TB/tb_periph.sv b/firmware/ip/qick_peripheral_template/src/TB/tb_periph.sv new file mode 100644 index 0000000..cc6b7da --- /dev/null +++ b/firmware/ip/qick_peripheral_template/src/TB/tb_periph.sv @@ -0,0 +1,417 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : mdife +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/10ps + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +`define T_C_CLK 3 // 1.66 // Half Clock Period for Simulation +`define T_PS_CLK 25 // Half Clock Period for Simulation + +localparam DEBUG = 1; // Debugging + +module tb_qperiph(); + +/////////////////////////////////////////////////////////////////////////////// + +// VIP Agent +axi_mst_0_mst_t axi_mst_0_agent; +xil_axi_prot_t prot = 0; +xil_axi_resp_t resp; + +// Signals +reg c_clk, ps_clk; +reg rst_ni; +reg[31:0] data_wr = 32'h12345678; + +//AXI-LITE +wire [7:0] s_axi_awaddr ; +wire [2:0] s_axi_awprot ; +wire s_axi_awvalid ; +wire s_axi_awready ; +wire [31:0] s_axi_wdata ; +wire [3:0] s_axi_wstrb ; +wire s_axi_wvalid ; +wire s_axi_wready ; +wire [1:0] s_axi_bresp ; +wire s_axi_bvalid ; +wire s_axi_bready ; +wire [7:0] s_axi_araddr ; +wire [2:0] s_axi_arprot ; +wire s_axi_arvalid ; +wire s_axi_arready ; +wire [31:0] s_axi_rdata ; +wire [1:0] s_axi_rresp ; +wire s_axi_rvalid ; +wire s_axi_rready ; + +reg sync_i; +////////////////////////////////////////////////////////////////////////// +// CLK Generation +initial begin + c_clk = 1'b0; + forever # (`T_C_CLK) c_clk = ~c_clk; +end +initial begin + ps_clk = 1'b0; + forever # (`T_PS_CLK) ps_clk = ~ps_clk; +end +initial begin + sync_i = 1'b0; + forever # (1000) sync_i = ~sync_i; +end + + + + +reg c_cmd_i ; +reg [4 :0] c_op_i; + +// Register ADDRESS +parameter QCOM_CTRL = 0 * 4 ; +parameter QCOM_CFG = 1 * 4 ; +parameter RAXI_DT1 = 2 * 4 ; +parameter QCOM_FLAG = 7 * 4 ; +parameter QCOM_DT1 = 8 * 4 ; +parameter QCOM_DT2 = 9 * 4 ; +parameter QCOM_STATUS = 10 * 4 ; + + +////////////////////////////////////////////////////////////////////////// +// AXI AGENT +axi_mst_0 axi_mst_0_i ( + .aclk (ps_clk ), + .aresetn (rst_ni ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) +); + +reg [ 3:0] pmod_si ; +wire[ 3:0] pmod_o1, pmod_o2, pmod_i ; +reg [31:0] c_dt1_i, c_dt2_i, c_dt3_i ; + +////////////////////////////////////////////////////////////////////////// +// QCOM1 +axis_qick_com # ( + .DEBUG ( DEBUG ) +) QICK_COM_1 ( + .c_clk ( c_clk ) , + .c_aresetn ( rst_ni ) , + .ps_clk ( ps_clk ) , + .ps_aresetn ( rst_ni ) , + .sync_i ( sync_i ) , + .qcom_en_i ( c_cmd_i ) , + .qcom_op_i ( c_op_i ) , + .qcom_dt1_i ( c_dt1_i ) , + .qcom_rdy_o ( ready ) , + .qcom_dt1_o ( qcom_dt1_o ) , + .qcom_dt2_o ( qcom_dt2_o ) , + .qcom_vld_o ( qcom_vld_o ) , + .qcom_flag_o ( qcom_flag_o ) , + .qproc_start_o ( qproc_start_o1 ) , + .pmod_i ( pmod_i ) , + .pmod_o ( pmod_o1 ) , + .s_axi_awaddr ( s_axi_awaddr ) , + .s_axi_awprot ( s_axi_awprot ) , + .s_axi_awvalid ( s_axi_awvalid ) , + .s_axi_awready ( s_axi_awready ) , + .s_axi_wdata ( s_axi_wdata ) , + .s_axi_wstrb ( s_axi_wstrb ) , + .s_axi_wvalid ( s_axi_wvalid ) , + .s_axi_wready ( s_axi_wready ) , + .s_axi_bresp ( s_axi_bresp ) , + .s_axi_bvalid ( s_axi_bvalid ) , + .s_axi_bready ( s_axi_bready ) , + .s_axi_araddr ( s_axi_araddr ) , + .s_axi_arprot ( s_axi_arprot ) , + .s_axi_arvalid ( s_axi_arvalid ) , + .s_axi_arready ( s_axi_arready ) , + .s_axi_rdata ( s_axi_rdata ) , + .s_axi_rresp ( s_axi_rresp ) , + .s_axi_rvalid ( s_axi_rvalid ) , + .s_axi_rready ( s_axi_rready ) , + .qcom_do ( qcom_do ) +); +////////////////////////////////////////////////////////////////////////// +// QCOM +axis_qick_com # ( + .DEBUG ( DEBUG ) +) QICK_COM_2 ( + .c_clk ( c_clk ) , + .c_aresetn ( rst_ni ) , + .ps_clk ( ps_clk ) , + .ps_aresetn ( rst_ni ) , + .sync_i ( sync_i ) , + .qcom_en_i ( 0 ) , + .qcom_op_i ( 0 ) , + .qcom_dt1_i ( 0 ) , + .qcom_rdy_o ( ) , + .qcom_dt1_o ( ) , + .qcom_dt2_o ( ) , + .qcom_vld_o ( ) , + .qcom_flag_o ( ) , + .qproc_start_o ( qproc_start_o2 ) , + .pmod_i ( pmod_o1 ) , + .pmod_o ( pmod_o2 ) , + .s_axi_awaddr ( 0 ) , + .s_axi_awprot ( 0 ) , + .s_axi_awvalid ( 0 ) , + .s_axi_awready ( ) , + .s_axi_wdata ( 0 ) , + .s_axi_wstrb ( 0 ) , + .s_axi_wvalid ( 0 ) , + .s_axi_wready ( ) , + .s_axi_bresp ( ) , + .s_axi_bvalid ( ) , + .s_axi_bready ( ) , + .s_axi_araddr ( 0 ) , + .s_axi_arprot ( 0 ) , + .s_axi_arvalid ( 0 ) , + .s_axi_arready ( ) , + .s_axi_rdata ( ) , + .s_axi_rresp ( ) , + .s_axi_rvalid ( ) , + .s_axi_rready ( ) , + .qcom_do ( ) +); + + + +reg tx_loop; + +initial begin + START_SIMULATION(); + TEST_AXI () ; + // SIM_RX(); + SIM_TX(); + +end + +assign pmod_i = tx_loop ? pmod_o1 : pmod_si; + +task SIM_TX(); begin + $display("SIM TX"); + + tx_loop = 1'b0 ; + c_cmd_i = 1'b0 ; + c_op_i = 4'd0; + c_dt1_i = 0; + c_dt2_i = 0; + c_dt3_i = 0; + + + wait (ready == 1'b1) + @ (posedge c_clk); #0.1; + c_op_i = 5'b0001_0; //SET FLAG + c_cmd_i = 1'b1 ; + @ (posedge c_clk); #0.1; + c_cmd_i = 1'b0 ; + @ (posedge c_clk); #0.1; + + wait (ready == 1'b1) + # (5 * `T_C_CLK); + + @ (posedge c_clk); #0.1; + c_op_i = 5'b0000_0; //CLR FLAG + c_cmd_i = 1'b1 ; + @ (posedge c_clk); #0.1; + c_cmd_i = 1'b0 ; + @ (posedge c_clk); #0.1; + + wait (ready == 1'b1) + # (5 * `T_C_CLK); + + @ (posedge c_clk); #0.1; + c_op_i = 5'b0010_0; //SEND 8_BIT + c_dt1_i = 8'b10101010 ; + c_cmd_i = 1'b1 ; + @ (posedge c_clk); #0.1; + c_cmd_i = 1'b0 ; + @ (posedge c_clk); #0.1; + + wait (ready == 1'b1) + # (5 * `T_C_CLK); + + @ (posedge c_clk); #0.1; + c_op_i = 5'b0100_0; //SEND 16_BIT + c_dt1_i = 16'b0100_0011_0010_0001 ; + c_cmd_i = 1'b1 ; + @ (posedge c_clk); #0.1; + c_cmd_i = 1'b0 ; + @ (posedge c_clk); #0.1; + + wait (ready == 1'b1) + # (5 * `T_C_CLK); + + @ (posedge c_clk); #0.1; + c_op_i = 5'b0110_0; //SEND 32_BIT + c_dt1_i = 4660; + c_cmd_i = 1'b1 ; + @ (posedge c_clk); #0.1; + c_cmd_i = 1'b0 ; + @ (posedge c_clk); #0.1; + + wait (ready == 1'b1) + # (5 * `T_C_CLK); + + @ (posedge c_clk); #0.1; + c_op_i = 5'b0110_1; //SEND 32_BIT + c_dt1_i =53758; + c_cmd_i = 1'b1 ; + @ (posedge c_clk); #0.1; + c_cmd_i = 1'b0 ; + @ (posedge c_clk); #0.1; + + wait (ready == 1'b1) + # (5 * `T_C_CLK); + + @ (posedge c_clk); #0.1; + c_op_i = 5'b0011_0; //SYNC + c_dt1_i =53758; + c_cmd_i = 1'b1 ; + @ (posedge c_clk); #0.1; + c_cmd_i = 1'b0 ; + @ (posedge c_clk); #0.1; + + end +endtask + +task SIM_RX(); begin + tx_loop = 1'b0 ; + # (5 * `T_C_CLK); + @ (posedge c_clk); #0.1; + pmod_si = 4'b0001; // DATA + @ (posedge c_clk); #0.1; + pmod_si = 4'b1001; // Same DATA CLK + # (5 * `T_C_CLK); + @ (posedge c_clk); #0.1; + pmod_si = 4'b1001; // DATA + @ (posedge c_clk); #0.1; + pmod_si = 4'b0001; // Same DATA CLK + # (5 * `T_C_CLK); + @ (posedge c_clk); #0.1; + pmod_si = 4'b0000; // DATA + @ (posedge c_clk); #0.1; + pmod_si = 4'b1000; // Same DATA CLK + # (5 * `T_C_CLK); + @ (posedge c_clk); #0.1; + pmod_si = 4'b1110; // DATA + @ (posedge c_clk); #0.1; + pmod_si = 4'b0110; // Same DATA CLK + # (5 * `T_C_CLK); + @ (posedge c_clk); #0.1; + pmod_si = 4'b0100; // DATA + @ (posedge c_clk); #0.1; + pmod_si = 4'b1100; // Same DATA CLK + + # (33 * `T_C_CLK); + pmod_si = 4'b011; // Same DATA CLK + + # (18 * `T_C_CLK); + @ (posedge c_clk); #0.1; + pmod_si = 4'b0111; // DATA + @ (posedge c_clk); #0.1; + pmod_si = 4'b1111; // Same DATA CLK + # (5 * `T_C_CLK); + @ (posedge c_clk); #0.1; + pmod_si = 4'b1110; // DATA + @ (posedge c_clk); #0.1; + pmod_si = 4'b0110; // Same DATA CLK + # (5 * `T_C_CLK); + @ (posedge c_clk); #0.1; + pmod_si = 4'b0101; // DATA + @ (posedge c_clk); #0.1; + pmod_si = 4'b1101; // Same DATA CLK + # (5 * `T_C_CLK); + @ (posedge c_clk); #0.1; + pmod_si = 4'b1100; // DATA + @ (posedge c_clk); #0.1; + pmod_si = 4'b0100; // Same DATA CLK + end +endtask + +task WRITE_AXI(integer PORT_AXI, DATA_AXI); begin + @ (posedge ps_clk); #0.1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(PORT_AXI, prot, DATA_AXI, resp); + end +endtask + +task TEST_AXI (); begin + $display("-----Writting AXI "); + WRITE_AXI( QCOM_CTRL , 5); // Set Flag + WRITE_AXI( QCOM_CTRL , 1); // Clear Flag + WRITE_AXI( QCOM_CTRL , 5); // Set Flag + WRITE_AXI( QCOM_CTRL , 1); // Clear Flag + + WRITE_AXI( RAXI_DT1 , 1); // DATA + WRITE_AXI( QCOM_CTRL , 9); // Send 8bit (1) + WRITE_AXI( RAXI_DT1 , 2); // DATA + WRITE_AXI( QCOM_CTRL , 11); // Send 8bit (2) + + WRITE_AXI( QCOM_CTRL , 13); // SYNC_START + + WRITE_AXI( RAXI_DT1 , 16); // DATA + WRITE_AXI( QCOM_CTRL , 17); // Send 16bit (1) + WRITE_AXI( RAXI_DT1 , 32); // DATA + WRITE_AXI( QCOM_CTRL , 19); // Send 16bit (2) + + WRITE_AXI( RAXI_DT1 , 256); // DATA + WRITE_AXI( QCOM_CTRL , 25); // Send 32bit (1) + WRITE_AXI( RAXI_DT1 , 512); // DATA + WRITE_AXI( QCOM_CTRL , 27); // Send 32bit (2) + + +end +endtask + + +task START_SIMULATION (); begin + $display("START SIMULATION"); + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb_qcom.axi_mst_0_i.inst.IF); + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + // Start agents. + axi_mst_0_agent.start_master(); + rst_ni = 1'b0; + c_cmd_i = 1'b0 ; + c_op_i = 4'd0; + c_dt1_i = 0; + c_dt2_i = 0; + c_dt3_i = 0; + pmod_si = 0; + tx_loop = 1'b0 ; + + @ (posedge ps_clk); #0.1; + rst_ni = 1'b1; + + end +endtask + + +endmodule + + + + diff --git a/firmware/ip/qick_peripheral_template/src/_qp_ips.sv b/firmware/ip/qick_peripheral_template/src/_qp_ips.sv new file mode 100644 index 0000000..377b2d3 --- /dev/null +++ b/firmware/ip/qick_peripheral_template/src/_qp_ips.sv @@ -0,0 +1,95 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 1-2024 +// Version : 1 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : Custom Peripheral Template +/* Description: + File to add all the custom IPs needed for the peripheral +*/ +////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +/// Clock Domain Register Change +/////////////////////////////////////////////////////////////////////////////// +module sync_reg # ( + parameter DW = 32 +)( + input wire [DW-1:0] dt_i , + input wire clk_i , + input wire rst_ni , + output wire [DW-1:0] dt_o ); + +(* ASYNC_REG = "TRUE" *) reg [DW-1:0] data_rcd, data_r ; +always_ff @(posedge clk_i) + if(!rst_ni) begin + data_rcd <= 0; + data_r <= 0; + end else begin + data_rcd <= dt_i; + data_r <= data_rcd; + end +assign dt_o = data_r ; + +endmodule + +/////////////////////////////////////////////////////////////////////////////// +// DUAL PORT RAM +/////////////////////////////////////////////////////////////////////////////// +module bram_dual_port_dc # ( + parameter MEM_AW = 16 , + parameter MEM_DW = 16 , + parameter RAM_OUT = "NO_REGISTERED" // Select "NO_REGISTERED" or "REGISTERED" +) ( + input wire clk_a_i , + input wire en_a_i , + input wire we_a_i , + input wire [MEM_AW-1:0] addr_a_i , + input wire [MEM_DW-1:0] dt_a_i , + output wire [MEM_DW-1:0] dt_a_o , + input wire clk_b_i , + input wire en_b_i , + input wire we_b_i , + input wire [MEM_AW-1:0] addr_b_i , + input wire [MEM_DW-1:0] dt_b_i , + output wire [MEM_DW-1:0] dt_b_o ); + +localparam RAM_SIZE = 2**MEM_AW ; + +reg [MEM_DW-1:0] RAM [RAM_SIZE]; +reg [MEM_DW-1:0] ram_dt_a = {MEM_DW{1'b0}}; +reg [MEM_DW-1:0] ram_dt_b = {MEM_DW{1'b0}}; + +always @(posedge clk_a_i) + if (en_a_i) begin + ram_dt_a <= RAM[addr_a_i] ; + if (we_a_i) + RAM[addr_a_i] <= dt_a_i; + //else + // ram_dt_a <= RAM[addr_a_i] ; + end +always @(posedge clk_b_i) + if (en_b_i) + if (we_b_i) + RAM[addr_b_i] <= dt_b_i; + else + ram_dt_b <= RAM[addr_b_i] ; + +generate + if (RAM_OUT == "NO_REGISTERED") begin: no_output_register // 1 clock cycle read + assign dt_a_o = ram_dt_a ; + assign dt_b_o = ram_dt_b ; + end else begin: output_register // 2 clock cycle read + reg [MEM_DW-1:0] ram_dt_a_r = {MEM_DW{1'b0}}; + reg [MEM_DW-1:0] ram_dt_b_r = {MEM_DW{1'b0}}; + always @(posedge clk_a_i) ram_dt_a_r <= ram_dt_a; + always @(posedge clk_b_i) ram_dt_b_r <= ram_dt_b; + assign dt_a_o = ram_dt_a_r ; + assign dt_b_o = ram_dt_b_r ; + end +endgenerate + +endmodule + diff --git a/firmware/ip/qick_peripheral_template/src/axi_qick_peripheral.sv b/firmware/ip/qick_peripheral_template/src/axi_qick_peripheral.sv new file mode 100644 index 0000000..04713b1 --- /dev/null +++ b/firmware/ip/qick_peripheral_template/src/axi_qick_peripheral.sv @@ -0,0 +1,171 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 1-2024 +// Version : 1 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : Custom Peripheral Template +/* Description: + Top Level of the Peripheral Template. It includes two modules + 1) The axi_qick_peripheral core processing unit + 2) The Axi Register, used to read and write from Python. +*/ +////////////////////////////////////////////////////////////////////////////// + +module axi_qick_peripheral # ( + parameter DEBUG = 1 , + parameter INPUTS = 1 +) ( +// Core and AXI CLK & RST + input wire c_clk , + input wire c_aresetn , + input wire ps_clk , + input wire ps_aresetn , +// QPERIPH INTERFACE + input wire qp_en_i , // + input wire [ 4:0] qp_op_i , // + input wire [31:0] qp_dt1_i , // + input wire [31:0] qp_dt2_i , // + input wire [31:0] qp_dt3_i , // + input wire [31:0] qp_dt4_i , // + output reg qp_rdy_o , // + output reg [31:0] qp_dt1_o , // + output reg [31:0] qp_dt2_o , // + output reg qp_vld_o , // + output reg qp_flag_o , // +// INPUTS + input wire qp_signal_i , + input wire [31:0] qp_vector_i , +// OUTPUTS + output reg qp_signal_o , + output reg [31:0] qp_vector_o , +// AXI-Lite DATA Slave I/F. + input wire [5:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + input wire [31:0] s_axi_wdata , + input wire [ 3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + output wire [ 1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + input wire [ 5:0] s_axi_araddr , + input wire [ 2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + output wire [31:0] s_axi_rdata , + output wire [ 1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , +///// DEBUG + output wire [31:0] qp_do + ); + + +/////////////////////////////////////////////////////////////////////////////// +// AXI Register. +wire [ 7:0] r_qp_ctrl; +wire [ 7:0] r_qp_cfg; +wire [31:0] r_axi_dt1, r_axi_dt2, r_axi_dt3, r_axi_dt4; +wire [31:0] r_qp_dt1, r_qp_dt2, r_qp_dt3, r_qp_dt4; +reg [31:0] r_qp_status, r_qp_debug; + +axi_slv_qp AXI_REG ( + .aclk ( ps_aclk ) , + .aresetn ( ps_aresetn ) , + .awaddr ( s_axi_awaddr[5:0] ) , + .awprot ( s_axi_awprot ) , + .awvalid ( s_axi_awvalid ) , + .awready ( s_axi_awready ) , + .wdata ( s_axi_wdata ) , + .wstrb ( s_axi_wstrb ) , + .wvalid ( s_axi_wvalid ) , + .wready ( s_axi_wready ) , + .bresp ( s_axi_bresp ) , + .bvalid ( s_axi_bvalid ) , + .bready ( s_axi_bready ) , + .araddr ( s_axi_araddr ) , + .arprot ( s_axi_arprot ) , + .arvalid ( s_axi_arvalid ) , + .arready ( s_axi_arready ) , + .rdata ( s_axi_rdata ) , + .rresp ( s_axi_rresp ) , + .rvalid ( s_axi_rvalid ) , + .rready ( s_axi_rready ) , +// Registers + .QP_CTRL ( r_qp_ctrl ) , + .QP_CFG ( r_qp_cfg ) , + .AXI_DT1 ( r_axi_dt1 ) , + .AXI_DT2 ( r_axi_dt2 ) , + .AXI_DT3 ( r_axi_dt3 ) , + .AXI_DT4 ( r_axi_dt4 ) , + .QP_DT1 ( r_qp_dt1 ) , + .QP_DT2 ( r_qp_dt2 ) , + .QP_DT3 ( r_qp_dt3 ) , + .QP_DT4 ( r_qp_dt4 ) , + .QP_STATUS ( r_qp_status ) , + .QP_DEBUG ( r_qp_debug ) ); + +wire [31:0] qp_do_s; +qick_periph # ( + .PARAM ( 1 ) +) QP ( + .clk_i ( c_clk ) , + .rst_ni ( c_aresetn ) , + .qp_en_i ( qp_en_i ) , + .qp_op_i ( qp_op_i ) , + .qp_dt1_i ( qp_dt1_i ) , + .qp_dt2_i ( qp_dt2_i ) , + .qp_dt3_i ( qp_dt3_i ) , + .qp_dt4_i ( qp_dt4_i ) , + .qp_rdy_o ( qp_rdy_o ) , + .qp_dt1_o ( qp_dt1_o ) , + .qp_dt2_o ( qp_dt2_o ) , + .qp_vld_o ( qp_vld_o ) , + .qp_flag_o ( qp_flag_o ) , + .QP_CTRL ( r_qp_ctrl ) , + .QP_CFG ( r_qp_cfg ) , + .AXI_DT1 ( r_axi_dt1 ) , + .AXI_DT2 ( r_axi_dt2 ) , + .AXI_DT3 ( r_axi_dt3 ) , + .AXI_DT4 ( r_axi_dt4 ) , + .QP_DT1 ( r_qp_dt1 ) , + .QP_DT2 ( r_qp_dt2 ) , + .QP_DT3 ( r_qp_dt3 ) , + .QP_DT4 ( r_qp_dt4 ) , + .QP_STATUS ( r_qp_status ) , + .QP_DEBUG ( r_qp_debug ) , + .qp_signal_i ( qp_signal_i ) , + .qp_vector_i ( qp_vector_i ) , + .qp_signal_o ( qp_signal_o ) , + .qp_vector_o ( qp_vector_o ) , + .qp_do ( qp_do_s ) ); + + + + +/////////////////////////////////////////////////////////////////////////////// +// DEBUG +/////////////////////////////////////////////////////////////////////////////// +wire [31:0] qp_debug_s ; +// Assign AXI Debug Signbals +assign qp_debug_s[31:16] = r_axi_dt3[15:0] ; +assign qp_debug_s[15: 0] = r_axi_dt4[15:0] ; + +generate + if (DEBUG == 0 ) begin: DEBUG_NO + assign qp_debug = 0; + assign qp_do = 0; + end else if (DEBUG == 1) begin: DEBUG_REG + assign r_qp_debug = qp_debug_s; + assign qp_do = 0; + end else begin: DEBUG_OUT + assign r_qp_debug = qp_debug_s; + assign qp_do = qp_do_s; + end +endgenerate + +endmodule diff --git a/firmware/ip/qick_peripheral_template/src/axi_slv_qp.vhd b/firmware/ip/qick_peripheral_template/src/axi_slv_qp.vhd new file mode 100644 index 0000000..33a7832 --- /dev/null +++ b/firmware/ip/qick_peripheral_template/src/axi_slv_qp.vhd @@ -0,0 +1,522 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv_qp is + Generic ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6); + Port ( + aclk : in std_logic; + aresetn : in std_logic; + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + -- Registers. + QP_CTRL : out std_logic_vector ( 7 downto 0) ; + QP_CFG : out std_logic_vector ( 7 downto 0) ; + AXI_DT1 : out std_logic_vector (31 downto 0) ; + AXI_DT2 : out std_logic_vector (31 downto 0) ; + AXI_DT3 : out std_logic_vector (31 downto 0) ; + AXI_DT4 : out std_logic_vector (31 downto 0) ; + QP_DT1 : in std_logic_vector (31 downto 0) ; + QP_DT2 : in std_logic_vector (31 downto 0) ; + QP_DT3 : in std_logic_vector (31 downto 0) ; + QP_DT4 : in std_logic_vector (31 downto 0) ; + QP_STATUS : in std_logic_vector (31 downto 0) ; + QP_DEBUG : in std_logic_vector (31 downto 0) ); +end axi_slv_qp; + +architecture rtl of axi_slv_qp is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + + signal slv_reg0_rst : std_logic; +begin + -- I/O Connections assignments + + awready <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + -- Reset + if (unsigned(slv_reg0) /= 0) then slv_reg0_rst <= ('1'); else slv_reg0_rst <= ('0'); end if; + if (slv_reg0_rst = '1') then slv_reg0 <= (others => '0'); end if; + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + -- 4 : TAVG_LOW_REG (r). + -- 5 : TAVG_HIGH_REG(r). + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, QP_DT1, QP_DT2, QP_DT3, QP_DT4, QP_STATUS, QP_DEBUG, axi_araddr) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= "00000000000000000000000000000000"; + when b"0111" => + reg_data_out <= QP_DT1; + when b"1000" => + reg_data_out <= QP_DT2; + when b"1001" => + reg_data_out <= QP_DT3; + when b"1010" => + reg_data_out <= QP_DT4; + when b"1011" => + reg_data_out <= "00000000000000000000000000000000"; + when b"1100" => + reg_data_out <= "00000000000000000000000000000000"; + when b"1101" => + reg_data_out <= "00000000000000000000000000000000"; + when b"1110" => + reg_data_out <= QP_STATUS; + when b"1111" => + reg_data_out <= QP_DEBUG; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + +-- Output Registers. + +QP_CTRL <= slv_reg0( 7 downto 0); +QP_CFG <= slv_reg1( 7 downto 0); +AXI_DT1 <= slv_reg2(31 downto 0); +AXI_DT2 <= slv_reg3(31 downto 0); +AXI_DT3 <= slv_reg4(31 downto 0); +AXI_DT4 <= slv_reg5(31 downto 0); + +end rtl; diff --git a/firmware/ip/qick_peripheral_template/src/qick_periph.sv b/firmware/ip/qick_peripheral_template/src/qick_periph.sv new file mode 100644 index 0000000..db42e0b --- /dev/null +++ b/firmware/ip/qick_peripheral_template/src/qick_periph.sv @@ -0,0 +1,164 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 1-2024 +// Version : 1 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : Custom Peripheral Template +/* Description: + Core processing unit: implement here the peripheral. +*/ +////////////////////////////////////////////////////////////////////////////// +module qick_periph # ( + parameter PARAM = 1 +)( +// Core CLK & RST + input wire clk_i , + input wire rst_ni , +// QPERIPH INTERFACE + input wire qp_en_i , // + input wire [ 4:0] qp_op_i , // + input wire [31:0] qp_dt1_i , // + input wire [31:0] qp_dt2_i , // + input wire [31:0] qp_dt3_i , // + input wire [31:0] qp_dt4_i , // + output reg qp_rdy_o , // + output reg [31:0] qp_dt1_o , // + output reg [31:0] qp_dt2_o , // + output reg qp_vld_o , // + output reg qp_flag_o , // +// AXI REG + input wire [ 7:0] QP_CTRL , + input wire [ 7:0] QP_CFG , + input wire [31:0] AXI_DT1 , + input wire [31:0] AXI_DT2 , + input wire [31:0] AXI_DT3 , + input wire [31:0] AXI_DT4 , + output reg [31:0] QP_DT1 , + output reg [31:0] QP_DT2 , + output reg [31:0] QP_DT3 , + output reg [31:0] QP_DT4 , + output reg [31:0] QP_STATUS , + output reg [31:0] QP_DEBUG , +// INPUTS + input wire qp_signal_i , + input wire [31:0] qp_vector_i , +// OUTPUTS + output reg qp_signal_o , + output reg [31:0] qp_vector_o , +// DEBUG + output wire [31:0] qp_do ); + + +/////////////////////////////////////////////////////////////////////////////// +// Python Command SYNCRONIZATION +/////////////////////////////////////////////////////////////////////////////// +// Control Signal SYNC +wire [ 5:0] axi_ctrl ; +sync_reg # ( + .DW ( 6 ) +)cmd_sync ( + .dt_i ( QP_CTRL[5:0] ) , + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .dt_o ( axi_ctrl ) ); + +assign p_cmd_in = axi_ctrl[0] ; + +reg [ 7:0] p_cmd_in_r ; + +always_ff @ (posedge clk_i, negedge rst_ni) begin + if (!rst_ni) p_cmd_in_r <= 1'b0; + else p_cmd_in_r <= p_cmd_in; +end +//Single Pulse Control Signal +assign p_cmd_in_t01 = !p_cmd_in_r & p_cmd_in; + + +/////////////////////////////////////////////////////////////////////////////// +// Input Command and Data +/////////////////////////////////////////////////////////////////////////////// +reg [ 4:0] c_op_r ; +reg [31:0] c_dt1_r, c_dt2_r ; + +// REGISTERES INs +always_ff @ (posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + c_op_r <= 1'b0; + c_dt1_r <= '{default:'0} ; + c_dt2_r <= '{default:'0} ; + end else if (p_cmd_in_t01) begin + // Command from Python Interface + c_op_r <= axi_ctrl[5:1]; + c_dt1_r <= AXI_DT1; + c_dt2_r <= AXI_DT2; + end else if (qp_en_i) begin + // Command from QPROC Interface + c_op_r <= qp_op_i[4:0]; + c_dt1_r <= qp_dt1_i; + c_dt2_r <= qp_dt1_i; + end +end + + +/////////////////////////////////////////////////////////////////////////////// +// ASYNCHONOUS INPUT SYNCRONIZATION +/////////////////////////////////////////////////////////////////////////////// +wire qp_signal_r; +sync_reg # ( + .DW ( 1 ) +) sg_sync ( + .dt_i ( qp_signal_i ) , + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .dt_o ( qp_signal_r ) ); + +wire [31:0] qp_vector_r; +sync_reg # ( + .DW ( 32 ) +) vec_sync ( + .dt_i ( qp_vector_i ) , + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .dt_o ( qp_vector_r ) ); + +/////////////////////////////////////////////////////////////////////////////// +// PERIPHERAL PROCESSING +/////////////////////////////////////////////////////////////////////////////// +assign xreg_QP_DT1 = AXI_DT1 ; +assign xreg_QP_DT2 = AXI_DT2 ; +assign xreg_QP_DT3 = AXI_DT3 ; +assign xreg_QP_DT4 = AXI_DT4 ; + + + +/////////////////////////////////////////////////////////////////////////////// +// INSTANCES +/////////////////////////////////////////////////////////////////////////////// + + + +/////////////////////////////////////////////////////////////////////////////// +// OUTPUTS +/////////////////////////////////////////////////////////////////////////////// + +// AXI REGISTERS +assign QP_DT1 = xreg_QP_DT1 ; +assign QP_DT2 = xreg_QP_DT2 ; +assign QP_DT3 = xreg_QP_DT3 ; +assign QP_DT4 = xreg_QP_DT4 ; +assign QP_STATUS = 0 ; + +// REGISTERES OUTs +always_ff @ (posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + qp_signal_o <= 1'b0; + qp_vector_o <= '{default:'0} ; + end else begin + qp_signal_o <= qp_signal_r; + qp_vector_o <= qp_vector_r; + end +end + +endmodule diff --git a/firmware/ip/qick_peripheral_template/xgui/axis_qick_com_v1_0.tcl b/firmware/ip/qick_peripheral_template/xgui/axis_qick_com_v1_0.tcl new file mode 100644 index 0000000..95980b7 --- /dev/null +++ b/firmware/ip/qick_peripheral_template/xgui/axis_qick_com_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DEBUG" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + diff --git a/firmware/ip/qick_peripheral_template/xgui/qick_com_v1_0.tcl b/firmware/ip/qick_peripheral_template/xgui/qick_com_v1_0.tcl new file mode 100644 index 0000000..95980b7 --- /dev/null +++ b/firmware/ip/qick_peripheral_template/xgui/qick_com_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DEBUG" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + diff --git a/firmware/ip/qick_peripheral_template/xgui/qick_peripheral_v1_0.tcl b/firmware/ip/qick_peripheral_template/xgui/qick_peripheral_v1_0.tcl new file mode 100644 index 0000000..f2d9383 --- /dev/null +++ b/firmware/ip/qick_peripheral_template/xgui/qick_peripheral_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DEBUG" -parent ${Page_0} + ipgui::add_param $IPINST -name "INPUTS" -parent ${Page_0} -widget checkBox + + +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + +proc update_PARAM_VALUE.INPUTS { PARAM_VALUE.INPUTS } { + # Procedure called to update INPUTS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.INPUTS { PARAM_VALUE.INPUTS } { + # Procedure called to validate INPUTS + return true +} + + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + +proc update_MODELPARAM_VALUE.INPUTS { MODELPARAM_VALUE.INPUTS PARAM_VALUE.INPUTS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.INPUTS}] ${MODELPARAM_VALUE.INPUTS} +} + diff --git a/firmware/ip/qick_processor/component.xml b/firmware/ip/qick_processor/component.xml new file mode 100644 index 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src/qcore_mem.v + verilogSource + xil_defaultlib + + + src/qproc_mem_ctrl.v + verilogSource + xil_defaultlib + + + src/_qproc_defines.svh + systemVerilogSource + true + xil_defaultlib + + + src/_qproc_ips.sv + systemVerilogSource + xil_defaultlib + + + src/qcore_cpu.sv + systemVerilogSource + xil_defaultlib + + + src/qcore_ctrl_hazard.sv + systemVerilogSource + xil_defaultlib + + + src/qcore_reg_bank.sv + systemVerilogSource + xil_defaultlib + + + src/qick_processor.sv + systemVerilogSource + xil_defaultlib + + + src/qproc_axi_reg.sv + systemVerilogSource + xil_defaultlib + + + src/qproc_core.sv + systemVerilogSource + xil_defaultlib + + + src/qproc_dispatcher.sv + systemVerilogSource + xil_defaultlib + + + src/qproc_inport_reg.sv + systemVerilogSource + xil_defaultlib + + + src/qproc_time_ctrl.sv + systemVerilogSource + xil_defaultlib + + + src/axi_slv_qproc.vhd + vhdlSource + xil_defaultlib + + + src/qproc_ctrl.sv + systemVerilogSource + xil_defaultlib + + + src/axis_qick_processor.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dsp_macro_1_0__ref_view_fileset + + + + + + + + + + xilinx_testbench_view_fileset + + src/tb/axi_mst_0/axi_mst_0.xci + xci + + + src/tb/tb_qproc_issue35.wcfg + unknown + USED_IN_simulation + USED_IN_testbench + + + src/tb/wave_issue35.mem + mem + USED_IN_simulation + USED_IN_testbench + + + src/tb/dmem_issue35.mem + mem + USED_IN_simulation + USED_IN_testbench + + + src/tb/prog_issue35.mem + mem + USED_IN_simulation + USED_IN_testbench + + + src/tb/tb_qick_processor_issue35.sv + systemVerilogSource + USED_IN_simulation + USED_IN_testbench + xil_defaultlib + + + + xilinx_xpgui_view_fileset + + xgui/qick_processor_v2_0.tcl + tclSource + CHECKSUM_4ab07b4f + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + src/logoQICK_128x128.png + image + LOGO + + + + qick_processor + + + PMEM_AW + Program Mem Address Width + 8 + + + DMEM_AW + Data Mem Address Width + 8 + + + WMEM_AW + WaveParam Mem Address Width + 8 + + + REG_AW + General Purpose Register Address Width + 4 + + + IN_PORT_QTY + Data IN Port Quantity + 1 + + + OUT_DPORT_QTY + DPORT - Data Port Quantity + 1 + + + OUT_WPORT_QTY + WPORT - Wave Port Quantity + 1 + + + Component_Name + axis_tproc_B_v1_0 + + + LFSR + Random Number Generator + 1 + + + DIVIDER + Integer Divider + 0 + + + ARITH + Arithmetic Co-Processor + 0 + + + TIME_READ + Time User Read (Python and qProc) + 1 + + + CUSTOM_PERIPH + Custom Peripheral Interface + 0 + + + DEBUG + Debug + 1 + + + IO_CTRL + IO Control + 0 + + + DUAL_CORE + Number of Cores (Not Available YET) + 0 + + + OUT_DPORT_DW + DPORT - Data Port Width + 4 + + + OUT_TRIG_QTY + TRIG - Trigger Port Quantity + 2 + + + FIFO_DEPTH + FIFO Depth + 9 + + + EXT_FLAG + External Flag + 0 + + + QCOM + QCOM > QICK Communication Interface + 0 + + + CALL_DEPTH + Call Depth + 255 + + + OUT_TIME + Out Time + 0 + + + QNET + QNET > QICK Network Communication + 0 + + + TIME_CTRL + Time Ctrl + 0 + + + CORE_CTRL + Core Ctrl + 0 + + + GEN_SYNC + Gen Sync + 0 + + + + + + /UserIP + + qick_processor + level_2 + package_project + + XPM_FIFO + + 26 + + user.org:user:axis_tproc_B:1.0 + + 2025-07-08T15:39:03Z + + + 2023.1 + + + + + + + + + diff --git a/firmware/ip/qick_processor/src/_qproc_defines.svh b/firmware/ip/qick_processor/src/_qproc_defines.svh new file mode 100644 index 0000000..ec9d4fc --- /dev/null +++ b/firmware/ip/qick_processor/src/_qproc_defines.svh @@ -0,0 +1,106 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// GENERAL +`ifndef DEFINES + `define DEFINES + // Data Comming from the AXI Stream + `define AXIS_IN_DW 32 // 14 - 30 + `define AXI_WDATA_WIDTH 32 + `define AXI_RDATA_WIDTH 32 + `define AXI_WSTRB_WIDTH 4 + + parameter CFG = 3'b000; + parameter BRANCH = 3'b001; + parameter INT_CTRL = 3'b010; + parameter EXT_CTRL = 3'b011; + parameter REG_WR = 3'b100; + parameter MEM_WR = 3'b101; + parameter PORT_WR = 3'b110; + + typedef struct packed { + bit we ; + bit r_wave_we ; + bit [6:0] addr ; + bit [1:0] src ; + bit port_re ; + } CTRL_REG; + + typedef struct packed { + reg cfg_addr_imm ; + reg cfg_dt_imm ; + reg cfg_port_src ; + reg cfg_port_type ; + reg cfg_port_time ; + reg [3:0] cfg_cond ; + reg cfg_alu_src ; + reg [3:0] cfg_alu_op ; + reg [8:0] usr_ctrl ; + reg flag_we ; + reg dmem_we ; + reg wmem_we ; + reg port_we ; + } CTRL_FLOW; + + typedef struct packed { + logic [31:0] p_time ; + logic p_type ; // 00-WAVE 01-DATA 10- + logic [5:0] p_addr ; + logic [167:0] p_data ; + } PORT_DT; + + typedef struct packed { + logic [47:0] qtp_time ; + logic [7 :0] qtp_version ; + logic [7 :0] qtp_cfg ; + logic [7 :0] qtp_ctrl ; + logic [7 :0] qtp_dst ; + logic [15:0] qtp_len ; + } QTP_CTRL; + +// AXI-Lite DATA Slave I/F. +interface TYPE_IF_AXI_REG #( ); + logic [5:0] axi_awaddr ; + logic [2:0] axi_awprot ; + logic axi_awvalid ; + logic axi_awready ; + logic [31:0] axi_wdata ; + logic [3:0] axi_wstrb ; + logic axi_wvalid ; + logic axi_wready ; + logic [1:0] axi_bresp ; + logic axi_bvalid ; + logic axi_bready ; + logic [5:0] axi_araddr ; + logic [2:0] axi_arprot ; + logic axi_arvalid ; + logic axi_arready ; + logic [31:0] axi_rdata ; + logic [1:0] axi_rresp ; + logic axi_rvalid ; + logic axi_rready ; + + modport master ( output axi_awaddr,axi_awprot, axi_awvalid,axi_wdata,axi_wstrb,axi_wvalid,axi_bready,axi_araddr,axi_arprot,axi_arvalid,axi_rready, + input axi_awready,axi_wready,axi_bresp,axi_bvalid,axi_arready,axi_rdata,axi_rresp,axi_rvalid ); + modport slave ( input axi_awaddr,axi_awprot, axi_awvalid,axi_wdata,axi_wstrb,axi_wvalid,axi_bready,axi_araddr,axi_arprot,axi_arvalid,axi_rready, + output axi_awready,axi_wready,axi_bresp,axi_bvalid,axi_arready,axi_rdata,axi_rresp,axi_rvalid ); + +endinterface + +interface TYPE_IF_MEM #( + parameter DW = 32, + parameter AW = 8 +); + logic dmem_en ; + logic dmem_we ; + logic [ AW-1 : 0 ] dmem_addr; + logic [ DW-1 : 0 ] dmem_w_dt; + logic [ DW-1 : 0 ] dmem_r_dt; +// modport slave ( input dmem_en, dmem_we, dmem_addr, dmem_w_dt, output dmem_r_dt); +// modport master ( input dmem_en, dmem_we, dmem_addr, dmem_w_dt, output dmem_r_dt); +endinterface + +`endif + diff --git a/firmware/ip/qick_processor/src/_qproc_ips.sv b/firmware/ip/qick_processor/src/_qproc_ips.sv new file mode 100644 index 0000000..8e09bc6 --- /dev/null +++ b/firmware/ip/qick_processor/src/_qproc_ips.sv @@ -0,0 +1,1298 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 3-2024 +// Version : 3 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : qick_processor tProc_v2 +/* Description: +IPs used in the design of the qick_processor + +* SYNCHRONIZATION REGISTER +* DUAL PORT RAM +* LIFO +* GRAY CODE COUNTER +* FIFO DUAL CLOCK +* TWO inputs ALU +* DSP ARITH BLOCK +* DIVIDER REGISTERED +* INTERLEAVING DUACL CLOCK EN +- DIVISION Pipelined 32 BIT integer +- gray_2_bin +- bin_2_gray + +*/ +////////////////////////////////////////////////////////////////////////////// + +`define USE_XPM_MACROS + +/////////////////////////////////////////////////////////////////////////////// +/// SYNC - Clock Domain Data Syncronization +/////////////////////////////////////////////////////////////////////////////// +module sync_reg # ( + parameter DW = 32 +)( + input wire [DW-1:0] dt_i , + input wire clk_i , + input wire rst_ni , + output wire [DW-1:0] dt_o ); + +// FAST REGISTER GRAY TRANSFORM OF INPUT +(* ASYNC_REG = "TRUE" *) reg [DW-1:0] data_cdc, data_r ; +always_ff @(posedge clk_i) + if(!rst_ni) begin + data_cdc <= 0; + data_r <= 0; + end else begin + data_cdc <= dt_i; + data_r <= data_cdc; + end +assign dt_o = data_r ; + +endmodule + + +/////////////////////////////////////////////////////////////////////////////// +// DUAL PORT RAM +/////////////////////////////////////////////////////////////////////////////// +module bram_dual_port_dc # ( + parameter MEM_AW = 16 , + parameter MEM_DW = 16 , + parameter RAM_OUT = "NO_REGISTERED" // Select "NO_REGISTERED" or "REGISTERED" +) ( + input wire clk_a_i , + input wire en_a_i , + input wire we_a_i , + input wire [MEM_AW-1:0] addr_a_i , + input wire [MEM_DW-1:0] dt_a_i , + output wire [MEM_DW-1:0] dt_a_o , + input wire clk_b_i , + input wire en_b_i , + input wire we_b_i , + input wire [MEM_AW-1:0] addr_b_i , + input wire [MEM_DW-1:0] dt_b_i , + output wire [MEM_DW-1:0] dt_b_o ); + +localparam RAM_SIZE = 2**MEM_AW ; + +reg [MEM_DW-1:0] RAM [RAM_SIZE]; +reg [MEM_DW-1:0] ram_dt_a = {MEM_DW{1'b0}}; +reg [MEM_DW-1:0] ram_dt_b = {MEM_DW{1'b0}}; + +initial begin + for (int i=0; i < RAM_SIZE; i=i+1) begin + RAM[i] = 'd0; + end +end + +always @(posedge clk_a_i) + if (en_a_i) begin + ram_dt_a <= RAM[addr_a_i] ; + if (we_a_i) + RAM[addr_a_i] <= dt_a_i; + end +always @(posedge clk_b_i) + if (en_b_i) + if (we_b_i) + RAM[addr_b_i] <= dt_b_i; + else + ram_dt_b <= RAM[addr_b_i] ; + +generate + if (RAM_OUT == "NO_REGISTERED") begin: no_output_register // 1 clock cycle read + assign dt_a_o = ram_dt_a ; + assign dt_b_o = ram_dt_b ; + end else begin: output_register // 2 clock cycle read + reg [MEM_DW-1:0] ram_dt_a_r = {MEM_DW{1'b0}}; + reg [MEM_DW-1:0] ram_dt_b_r = {MEM_DW{1'b0}}; + always @(posedge clk_a_i) ram_dt_a_r <= ram_dt_a; + always @(posedge clk_b_i) ram_dt_b_r <= ram_dt_b; + assign dt_a_o = ram_dt_a_r ; + assign dt_b_o = ram_dt_b_r ; + end +endgenerate + +endmodule + + +/////////////////////////////////////////////////////////////////////////////// +// LIFO +/////////////////////////////////////////////////////////////////////////////// +module LIFO # ( + parameter WIDTH = 16 , + parameter DEPTH = 8 // MAX 8 +) ( + input wire clk_i , + input wire rst_ni , + input wire [WIDTH - 1:0] data_i , + input wire push , + input wire pop , + output wire [WIDTH - 1:0] data_o , + output wire full_o ); + +wire [2:0] ptr_p1, ptr_m1 ; +reg [2:0] ptr ; +reg [WIDTH-1:0] stack [DEPTH] ; + +assign ptr_p1 = ptr + 1'b1; +assign ptr_m1 = ptr - 1'b1; + +// Pointer +always_ff @(posedge clk_i) begin + if (!rst_ni) ptr <= 0; + else if (push & !full_o) ptr <= ptr_p1; + else if (pop & !empty_o) ptr <= ptr_m1; +end + +// Data +always_ff @(posedge clk_i) begin + if (!rst_ni) stack <= '{default:'0} ; + if(push & !full_o) stack[ptr] <= data_i ; +end + +assign empty_o = !(|ptr) ; +assign full_o = !(|(ptr ^ DEPTH)); +assign data_o = stack[ptr_m1]; + +endmodule + +`ifndef USE_XPM_MACROS +/////////////////////////////////////////////////////////////////////////////// +//GRAY CODE COUNTER +/////////////////////////////////////////////////////////////////////////////// +module gcc # ( + parameter DW = 32 +)( + input wire clk_i , + input wire rst_ni , + input wire async_clear_i , + output wire clear_o , + input wire cnt_en_i , + output wire [DW-1:0] count_bin_o , + output wire [DW-1:0] count_gray_o , + output wire [DW-1:0] count_bin_p1_o , + output wire [DW-1:0] count_gray_p1_o); + +reg [DW-1:0] count_bin ; // count turned into binary number +wire [DW-1:0] count_bin_p1; // count_bin+1 + +reg [DW-1:0] count_bin_r, count_gray_r; + +integer ind; +always_comb begin + count_bin[DW-1] = count_gray_r[DW-1]; + for (ind=DW-2 ; ind>=0; ind=ind-1) begin + count_bin[ind] = count_bin[ind+1]^count_gray_r[ind]; + end +end + +(* ASYNC_REG = "TRUE" *) reg clear_cdc, clear_r; +always_ff @(posedge clk_i, negedge rst_ni) + if(!rst_ni) begin + clear_cdc <= 0; + clear_r <= 0; + end else begin + clear_cdc <= async_clear_i; + clear_r <= clear_cdc; + end + +assign count_bin_p1 = count_bin + 1 ; + +reg [DW-1:0] count_bin_2r, count_gray_2r; +always_ff @(posedge clk_i, negedge rst_ni) + if(!rst_ni) begin + count_gray_r <= 1; + count_bin_r <= 1; + count_gray_2r <= 0; + count_bin_2r <= 0; + end else begin + if (clear_r) begin + count_gray_r <= 1; + count_bin_r <= 1; + count_gray_2r <= 0; + count_bin_2r <= 0; + end else if (cnt_en_i) begin + count_gray_r <= count_bin_p1 ^ {1'b0,count_bin_p1[DW-1:1]}; + count_bin_r <= count_bin_p1; + count_gray_2r <= count_gray_r; + count_bin_2r <= count_bin_r; + + end + end + +assign clear_o = clear_r ; +assign count_bin_o = count_bin_2r ; +assign count_gray_o = count_gray_2r ; +assign count_bin_p1_o = count_bin_r ; +assign count_gray_p1_o = count_gray_r ; + +endmodule +`endif + + +`ifdef USE_XPM_MACROS + +module BRAM_FIFO_DC_2 # ( + parameter FIFO_DW = 16 , + parameter FIFO_AW = 8 +) ( + input wire wr_clk_i , + input wire wr_rst_ni , + input wire wr_en_i , + input wire push_i , + input wire [FIFO_DW - 1:0] data_i , + input wire rd_clk_i , + input wire rd_rst_ni , + input wire rd_en_i , + input wire pop_i , + input wire flush_i , + output logic [FIFO_DW - 1:0] data_o , + output logic async_empty_o , + output logic async_full_o +); + + // XPM_FIFO instantiation template for Asynchronous FIFO configurations + // Refer to the targeted device family architecture libraries guide for XPM_FIFO documentation + // ======================================================================================================================= + + // Parameter usage table, organized as follows: + // +---------------------------------------------------------------------------------------------------------------------+ + // | Parameter name | Data type | Restrictions, if applicable | + // |---------------------------------------------------------------------------------------------------------------------| + // | Description | + // +---------------------------------------------------------------------------------------------------------------------+ + // +---------------------------------------------------------------------------------------------------------------------+ + // | CASCADE_HEIGHT | Integer | Range: 0 - 64. Default value = 0. | + // |---------------------------------------------------------------------------------------------------------------------| + // | 0- No Cascade Height, Allow Vivado Synthesis to choose. | + // | 1 or more - Vivado Synthesis sets the specified value as Cascade Height. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | CDC_SYNC_STAGES | Integer | Range: 2 - 8. Default value = 2. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Specifies the number of synchronization stages on the CDC path | + // | | + // | Must be < 5 if FIFO_WRITE_DEPTH = 16 | + // +---------------------------------------------------------------------------------------------------------------------+ + // | DOUT_RESET_VALUE | String | Default value = 0. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Reset value of read data path. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | ECC_MODE | String | Allowed values: no_ecc, en_ecc. Default value = no_ecc. | + // |---------------------------------------------------------------------------------------------------------------------| + // | | + // | "no_ecc" - Disables ECC | + // | "en_ecc" - Enables both ECC Encoder and Decoder | + // | | + // | NOTE: ECC_MODE should be "no_ecc" if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior.| + // +---------------------------------------------------------------------------------------------------------------------+ + // | FIFO_MEMORY_TYPE | String | Allowed values: auto, block, distributed. Default value = auto. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Designate the fifo memory primitive (resource type) to use. | + // | | + // | "auto"- Allow Vivado Synthesis to choose | + // | "block"- Block RAM FIFO | + // | "distributed"- Distributed RAM FIFO | + // | | + // | NOTE: There may be a behavior mismatch if Block RAM or Ultra RAM specific features, like ECC or Asymmetry, are selected with FIFO_MEMORY_TYPE set to "auto".| + // +---------------------------------------------------------------------------------------------------------------------+ + // | FIFO_READ_LATENCY | Integer | Range: 0 - 10. Default value = 1. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Number of output register stages in the read data path. | + // | | + // | If READ_MODE = "fwft", then the only applicable value is 0. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | FIFO_WRITE_DEPTH | Integer | Range: 16 - 4194304. Default value = 2048. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Defines the FIFO Write Depth, must be power of two. | + // | | + // | In standard READ_MODE, the effective depth = FIFO_WRITE_DEPTH-1 | + // | In First-Word-Fall-Through READ_MODE, the effective depth = FIFO_WRITE_DEPTH+1 | + // | | + // | NOTE: The maximum FIFO size (width x depth) is limited to 150-Megabits. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | FULL_RESET_VALUE | Integer | Range: 0 - 1. Default value = 0. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Sets full, almost_full and prog_full to FULL_RESET_VALUE during reset | + // +---------------------------------------------------------------------------------------------------------------------+ + // | PROG_EMPTY_THRESH | Integer | Range: 3 - 4194301. Default value = 10. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Specifies the minimum number of read words in the FIFO at or below which prog_empty is asserted. | + // | | + // | Min_Value = 3 + (READ_MODE_VAL*2) | + // | Max_Value = (FIFO_WRITE_DEPTH-3) - (READ_MODE_VAL*2) | + // | | + // | If READ_MODE = "std", then READ_MODE_VAL = 0; Otherwise READ_MODE_VAL = 1. | + // | NOTE: The default threshold value is dependent on default FIFO_WRITE_DEPTH value. If FIFO_WRITE_DEPTH value is | + // | changed, ensure the threshold value is within the valid range though the programmable flags are not used. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | PROG_FULL_THRESH | Integer | Range: 5 - 4194301. Default value = 10. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Specifies the maximum number of write words in the FIFO at or above which prog_full is asserted. | + // | | + // | Min_Value = 3 + (READ_MODE_VAL*2*(FIFO_WRITE_DEPTH/FIFO_READ_DEPTH))+CDC_SYNC_STAGES | + // | Max_Value = (FIFO_WRITE_DEPTH-3) - (READ_MODE_VAL*2*(FIFO_WRITE_DEPTH/FIFO_READ_DEPTH)) | + // | | + // | If READ_MODE = "std", then READ_MODE_VAL = 0; Otherwise READ_MODE_VAL = 1. | + // | NOTE: The default threshold value is dependent on default FIFO_WRITE_DEPTH value. If FIFO_WRITE_DEPTH value is | + // | changed, ensure the threshold value is within the valid range though the programmable flags are not used. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | RD_DATA_COUNT_WIDTH | Integer | Range: 1 - 23. Default value = 1. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Specifies the width of rd_data_count. To reflect the correct value, the width should be log2(FIFO_READ_DEPTH)+1. | + // | | + // | FIFO_READ_DEPTH = FIFO_WRITE_DEPTH*WRITE_DATA_WIDTH/READ_DATA_WIDTH | + // +---------------------------------------------------------------------------------------------------------------------+ + // | READ_DATA_WIDTH | Integer | Range: 1 - 4096. Default value = 32. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Defines the width of the read data port, dout | + // | | + // | Write and read width aspect ratio must be 1:1, 1:2, 1:4, 1:8, 8:1, 4:1 and 2:1 | + // | For example, if WRITE_DATA_WIDTH is 32, then the READ_DATA_WIDTH must be 32, 64,128, 256, 16, 8, 4. | + // | | + // | NOTE: | + // | | + // | READ_DATA_WIDTH should be equal to WRITE_DATA_WIDTH if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior. | + // | The maximum FIFO size (width x depth) is limited to 150-Megabits. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | READ_MODE | String | Allowed values: std, fwft. Default value = std. | + // |---------------------------------------------------------------------------------------------------------------------| + // | | + // | "std"- standard read mode | + // | "fwft"- First-Word-Fall-Through read mode | + // +---------------------------------------------------------------------------------------------------------------------+ + // | RELATED_CLOCKS | Integer | Range: 0 - 1. Default value = 0. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Specifies if the wr_clk and rd_clk are related having the same source but different clock ratios | + // +---------------------------------------------------------------------------------------------------------------------+ + // | SIM_ASSERT_CHK | Integer | Range: 0 - 1. Default value = 0. | + // |---------------------------------------------------------------------------------------------------------------------| + // | 0- Disable simulation message reporting. Messages related to potential misuse will not be reported. | + // | 1- Enable simulation message reporting. Messages related to potential misuse will be reported. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | USE_ADV_FEATURES | String | Default value = 0707. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Enables data_valid, almost_empty, rd_data_count, prog_empty, underflow, wr_ack, almost_full, wr_data_count, | + // | prog_full, overflow features. | + // | | + // | Setting USE_ADV_FEATURES[0] to 1 enables overflow flag; Default value of this bit is 1 | + // | Setting USE_ADV_FEATURES[1] to 1 enables prog_full flag; Default value of this bit is 1 | + // | Setting USE_ADV_FEATURES[2] to 1 enables wr_data_count; Default value of this bit is 1 | + // | Setting USE_ADV_FEATURES[3] to 1 enables almost_full flag; Default value of this bit is 0 | + // | Setting USE_ADV_FEATURES[4] to 1 enables wr_ack flag; Default value of this bit is 0 | + // | Setting USE_ADV_FEATURES[8] to 1 enables underflow flag; Default value of this bit is 1 | + // | Setting USE_ADV_FEATURES[9] to 1 enables prog_empty flag; Default value of this bit is 1 | + // | Setting USE_ADV_FEATURES[10] to 1 enables rd_data_count; Default value of this bit is 1 | + // | Setting USE_ADV_FEATURES[11] to 1 enables almost_empty flag; Default value of this bit is 0 | + // | Setting USE_ADV_FEATURES[12] to 1 enables data_valid flag; Default value of this bit is 0 | + // +---------------------------------------------------------------------------------------------------------------------+ + // | WAKEUP_TIME | Integer | Range: 0 - 2. Default value = 0. | + // |---------------------------------------------------------------------------------------------------------------------| + // | | + // | 0 - Disable sleep | + // | 2 - Use Sleep Pin | + // | | + // | NOTE: WAKEUP_TIME should be 0 if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | WRITE_DATA_WIDTH | Integer | Range: 1 - 4096. Default value = 32. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Defines the width of the write data port, din | + // | | + // | Write and read width aspect ratio must be 1:1, 1:2, 1:4, 1:8, 8:1, 4:1 and 2:1 | + // | For example, if WRITE_DATA_WIDTH is 32, then the READ_DATA_WIDTH must be 32, 64,128, 256, 16, 8, 4. | + // | | + // | NOTE: | + // | | + // | WRITE_DATA_WIDTH should be equal to READ_DATA_WIDTH if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior. | + // | The maximum FIFO size (width x depth) is limited to 150-Megabits. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | WR_DATA_COUNT_WIDTH | Integer | Range: 1 - 23. Default value = 1. | + // |---------------------------------------------------------------------------------------------------------------------| + // | Specifies the width of wr_data_count. To reflect the correct value, the width should be log2(FIFO_WRITE_DEPTH)+1. | + // +---------------------------------------------------------------------------------------------------------------------+ + + // Port usage table, organized as follows: + // +---------------------------------------------------------------------------------------------------------------------+ + // | Port name | Direction | Size, in bits | Domain | Sense | Handling if unused | + // |---------------------------------------------------------------------------------------------------------------------| + // | Description | + // +---------------------------------------------------------------------------------------------------------------------+ + // +---------------------------------------------------------------------------------------------------------------------+ + // | almost_empty | Output | 1 | rd_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Almost Empty : When asserted, this signal indicates that only one more read can be performed before the FIFO goes to| + // | empty. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | almost_full | Output | 1 | wr_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Almost Full: When asserted, this signal indicates that only one more write can be performed before the FIFO is full.| + // +---------------------------------------------------------------------------------------------------------------------+ + // | data_valid | Output | 1 | rd_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Read Data Valid: When asserted, this signal indicates that valid data is available on the output bus (dout). | + // +---------------------------------------------------------------------------------------------------------------------+ + // | dbiterr | Output | 1 | rd_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Double Bit Error: Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted.| + // +---------------------------------------------------------------------------------------------------------------------+ + // | din | Input | WRITE_DATA_WIDTH | wr_clk | NA | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Write Data: The input data bus used when writing the FIFO. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | dout | Output | READ_DATA_WIDTH | rd_clk | NA | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Read Data: The output data bus is driven when reading the FIFO. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | empty | Output | 1 | rd_clk | Active-high | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Empty Flag: When asserted, this signal indicates that the FIFO is empty. | + // | Read requests are ignored when the FIFO is empty, initiating a read while empty is not destructive to the FIFO. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | full | Output | 1 | wr_clk | Active-high | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Full Flag: When asserted, this signal indicates that the FIFO is full. | + // | Write requests are ignored when the FIFO is full, initiating a write when the FIFO is full is not destructive | + // | to the contents of the FIFO. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | injectdbiterr | Input | 1 | wr_clk | Active-high | Tie to 1'b0 | + // |---------------------------------------------------------------------------------------------------------------------| + // | Double Bit Error Injection: Injects a double bit error if the ECC feature is used on block RAMs or | + // | UltraRAM macros. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | injectsbiterr | Input | 1 | wr_clk | Active-high | Tie to 1'b0 | + // |---------------------------------------------------------------------------------------------------------------------| + // | Single Bit Error Injection: Injects a single bit error if the ECC feature is used on block RAMs or | + // | UltraRAM macros. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | overflow | Output | 1 | wr_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Overflow: This signal indicates that a write request (wren) during the prior clock cycle was rejected, | + // | because the FIFO is full. Overflowing the FIFO is not destructive to the contents of the FIFO. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | prog_empty | Output | 1 | rd_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Programmable Empty: This signal is asserted when the number of words in the FIFO is less than or equal | + // | to the programmable empty threshold value. | + // | It is de-asserted when the number of words in the FIFO exceeds the programmable empty threshold value. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | prog_full | Output | 1 | wr_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal | + // | to the programmable full threshold value. | + // | It is de-asserted when the number of words in the FIFO is less than the programmable full threshold value. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | rd_clk | Input | 1 | NA | Rising edge | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Read clock: Used for read operation. rd_clk must be a free running clock. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | rd_data_count | Output | RD_DATA_COUNT_WIDTH | rd_clk | NA | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Read Data Count: This bus indicates the number of words read from the FIFO. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | rd_en | Input | 1 | rd_clk | Active-high | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Read Enable: If the FIFO is not empty, asserting this signal causes data (on dout) to be read from the FIFO. | + // | | + // | Must be held active-low when rd_rst_busy is active high. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | rd_rst_busy | Output | 1 | rd_clk | Active-high | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Read Reset Busy: Active-High indicator that the FIFO read domain is currently in a reset state. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | rst | Input | 1 | wr_clk | Active-high | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Reset: Must be synchronous to wr_clk. The clock(s) can be unstable at the time of applying reset, but reset must be released only after the clock(s) is/are stable.| + // +---------------------------------------------------------------------------------------------------------------------+ + // | sbiterr | Output | 1 | rd_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Single Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | sleep | Input | 1 | NA | Active-high | Tie to 1'b0 | + // |---------------------------------------------------------------------------------------------------------------------| + // | Dynamic power saving: If sleep is High, the memory/fifo block is in power saving mode. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | underflow | Output | 1 | rd_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Underflow: Indicates that the read request (rd_en) during the previous clock cycle was rejected | + // | because the FIFO is empty. Under flowing the FIFO is not destructive to the FIFO. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | wr_ack | Output | 1 | wr_clk | Active-high | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Write Acknowledge: This signal indicates that a write request (wr_en) during the prior clock cycle is succeeded. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | wr_clk | Input | 1 | NA | Rising edge | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Write clock: Used for write operation. wr_clk must be a free running clock. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | wr_data_count | Output | WR_DATA_COUNT_WIDTH | wr_clk | NA | DoNotCare | + // |---------------------------------------------------------------------------------------------------------------------| + // | Write Data Count: This bus indicates the number of words written into the FIFO. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | wr_en | Input | 1 | wr_clk | Active-high | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Write Enable: If the FIFO is not full, asserting this signal causes data (on din) to be written to the FIFO. | + // | | + // | Must be held active-low when rst or wr_rst_busy is active high. | + // +---------------------------------------------------------------------------------------------------------------------+ + // | wr_rst_busy | Output | 1 | wr_clk | Active-high | Required | + // |---------------------------------------------------------------------------------------------------------------------| + // | Write Reset Busy: Active-High indicator that the FIFO write domain is currently in a reset state. | + // +---------------------------------------------------------------------------------------------------------------------+ + + logic rd_rst_busy, wr_rst_busy; + logic wr_full, rd_empty, rd_empty_d1, rd_empty_d2; + logic [FIFO_DW - 1:0] dout; + + // Hold full high during Flush or Reset + assign async_full_o = wr_full | flush_i | wr_rst_busy; + + // Delay empty 2 clocks + always_ff @(posedge rd_clk_i) begin + rd_empty_d1 <= rd_empty; + rd_empty_d2 <= rd_empty_d1; + end + assign async_empty_o = rd_empty_d2; + + // Clear data output when empty + always_ff @(posedge rd_clk_i) begin + data_o <= rd_empty ? 'd0 : dout; + end + // assign data_o = rd_empty ? 'd0 : dout; + + + // xpm_fifo_async: Asynchronous FIFO + // Xilinx Parameterized Macro, version 2023.1 + xpm_fifo_async #( + .CASCADE_HEIGHT (0), // DECIMAL + .CDC_SYNC_STAGES (2), // DECIMAL + .DOUT_RESET_VALUE ("0"), // String + .ECC_MODE ("no_ecc"), // String + .FIFO_MEMORY_TYPE ("auto"), // String + .FIFO_READ_LATENCY (1), // DECIMAL + .FIFO_WRITE_DEPTH (2**FIFO_AW), // DECIMAL + .FULL_RESET_VALUE (1), // DECIMAL + .PROG_EMPTY_THRESH (10), // DECIMAL + .PROG_FULL_THRESH (10), // DECIMAL + .RD_DATA_COUNT_WIDTH (1), // DECIMAL + .READ_DATA_WIDTH (FIFO_DW), // DECIMAL + // .READ_MODE ("std"), // String + .READ_MODE ("fwft"), // String + .RELATED_CLOCKS (0), // DECIMAL + .SIM_ASSERT_CHK (0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages + .USE_ADV_FEATURES ("0000"), // String + .WAKEUP_TIME (0), // DECIMAL + .WRITE_DATA_WIDTH (FIFO_DW), // DECIMAL + .WR_DATA_COUNT_WIDTH (1) // DECIMAL + ) + xpm_fifo_async_inst ( + .almost_empty (), // 1-bit output: Almost Empty : When asserted, this signal indicates that + // only one more read can be performed before the FIFO goes to empty. + + .almost_full (), // 1-bit output: Almost Full: When asserted, this signal indicates that + // only one more write can be performed before the FIFO is full. + + .data_valid (), // 1-bit output: Read Data Valid: When asserted, this signal indicates + // that valid data is available on the output bus (dout). + + .dbiterr (), // 1-bit output: Double Bit Error: Indicates that the ECC decoder detected + // a double-bit error and data in the FIFO core is corrupted. + + .dout (dout), // READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven + // when reading the FIFO. + + .empty (rd_empty), // 1-bit output: Empty Flag: When asserted, this signal indicates that the + // FIFO is empty. Read requests are ignored when the FIFO is empty, + // initiating a read while empty is not destructive to the FIFO. + + .full (wr_full), // 1-bit output: Full Flag: When asserted, this signal indicates that the + // FIFO is full. Write requests are ignored when the FIFO is full, + // initiating a write when the FIFO is full is not destructive to the + // contents of the FIFO. + + .overflow (), // 1-bit output: Overflow: This signal indicates that a write request + // (wren) during the prior clock cycle was rejected, because the FIFO is + // full. Overflowing the FIFO is not destructive to the contents of the + // FIFO. + + .prog_empty (), // 1-bit output: Programmable Empty: This signal is asserted when the + // number of words in the FIFO is less than or equal to the programmable + // empty threshold value. It is de-asserted when the number of words in + // the FIFO exceeds the programmable empty threshold value. + + .prog_full (), // 1-bit output: Programmable Full: This signal is asserted when the + // number of words in the FIFO is greater than or equal to the + // programmable full threshold value. It is de-asserted when the number of + // words in the FIFO is less than the programmable full threshold value. + + .rd_data_count (), // RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates the + // number of words read from the FIFO. + + .rd_rst_busy (rd_rst_busy), // 1-bit output: Read Reset Busy: Active-High indicator that the FIFO read + // domain is currently in a reset state. + + .sbiterr (), // 1-bit output: Single Bit Error: Indicates that the ECC decoder detected + // and fixed a single-bit error. + + .underflow (), // 1-bit output: Underflow: Indicates that the read request (rd_en) during + // the previous clock cycle was rejected because the FIFO is empty. Under + // flowing the FIFO is not destructive to the FIFO. + + .wr_ack (), // 1-bit output: Write Acknowledge: This signal indicates that a write + // request (wr_en) during the prior clock cycle is succeeded. + + .wr_data_count (), // WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates + // the number of words written into the FIFO. + + .wr_rst_busy (wr_rst_busy), // 1-bit output: Write Reset Busy: Active-High indicator that the FIFO + // write domain is currently in a reset state. + + .din (data_i), // WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when + // writing the FIFO. + + .injectdbiterr (1'b0), // 1-bit input: Double Bit Error Injection: Injects a double bit error if + // the ECC feature is used on block RAMs or UltraRAM macros. + + .injectsbiterr (1'b0), // 1-bit input: Single Bit Error Injection: Injects a single bit error if + // the ECC feature is used on block RAMs or UltraRAM macros. + + .rd_clk (rd_clk_i), // 1-bit input: Read clock: Used for read operation. rd_clk must be a free + // running clock. + + .rd_en (~rd_rst_busy & rd_en_i & (pop_i | flush_i)), // 1-bit input: Read Enable: If the FIFO is not empty, asserting this + // signal causes data (on dout) to be read from the FIFO. Must be held + // active-low when rd_rst_busy is active high. + + .rst (~wr_rst_ni | flush_i), // 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be + // unstable at the time of applying reset, but reset must be released only + // after the clock(s) is/are stable. + + .sleep (1'b0), // 1-bit input: Dynamic power saving: If sleep is High, the memory/fifo + // block is in power saving mode. + + .wr_clk (wr_clk_i), // 1-bit input: Write clock: Used for write operation. wr_clk must be a + // free running clock. + + .wr_en (~wr_rst_busy & wr_rst_ni & wr_en_i & push_i) // 1-bit input: Write Enable: If the FIFO is not full, asserting this + // signal causes data (on din) to be written to the FIFO. Must be held + // active-low when rst or wr_rst_busy is active high. + ); + + // End of xpm_fifo_async_inst instantiation + +endmodule + +`else + +/////////////////////////////////////////////////////////////////////////////// +// FIFO DUAL CLOCK +/////////////////////////////////////////////////////////////////////////////// +module BRAM_FIFO_DC_2 # ( + parameter FIFO_DW = 16 , + parameter FIFO_AW = 8 +) ( + input wire wr_clk_i , + input wire wr_rst_ni , + input wire wr_en_i , + input wire push_i , + input wire [FIFO_DW - 1:0] data_i , + input wire rd_clk_i , + input wire rd_rst_ni , + input wire rd_en_i , + input wire pop_i , + output wire [FIFO_DW - 1:0] data_o , + input wire flush_i , + output wire async_empty_o , + output wire async_full_o ); + +// The WRITE_POINTER is on the Last Empty Value +// The READ_POINTER is on the Last Value +wire [FIFO_AW-1:0] rd_gptr_p1 ; +wire [FIFO_AW-1:0] wr_gptr_p1 ; +wire [FIFO_AW-1:0] rd_gptr, wr_gptr ; +wire clr_wr, clr_rd; +reg async_empty_r; +wire busy; +wire [FIFO_DW - 1:0] mem_dt; +wire async_empty, async_full; + +// Sample Pointers +(* ASYNC_REG = "TRUE" *) reg [FIFO_AW-1:0] wr_gptr_cdc, wr_gptr_r; +always_ff @(posedge rd_clk_i) begin + wr_gptr_cdc <= wr_gptr; + wr_gptr_r <= wr_gptr_cdc; + async_empty_r <= async_empty; +end + +(* ASYNC_REG = "TRUE" *) reg [FIFO_AW-1:0] rd_gptr_cdc, rd_gptr_r; +always_ff @(posedge wr_clk_i) begin + rd_gptr_cdc <= rd_gptr; + rd_gptr_r <= rd_gptr_cdc; +end + +reg clr_fifo_req, clr_fifo_ack; +always_ff @(posedge wr_clk_i, negedge wr_rst_ni) begin + if (!wr_rst_ni) begin + clr_fifo_req <= 0 ; + clr_fifo_ack <= 0 ; + end else begin + if (flush_i) + clr_fifo_req <= 1 ; + else if (clr_fifo_ack ) + clr_fifo_req <= 0 ; + + if (clr_rd & clr_wr) + clr_fifo_ack <= 1 ; + else if (clr_fifo_ack & !clr_rd & !clr_wr) + clr_fifo_ack <= 0 ; + end +end + +assign busy = clr_fifo_ack | clr_fifo_req ; + +//SYNC with POP (RD_CLK) +assign async_empty = (rd_gptr == wr_gptr_r) ; + +//SYNC with PUSH (WR_CLK) +assign async_full = (rd_gptr_r == wr_gptr_p1) ; + +wire do_pop, do_push; +assign do_pop = pop_i & !async_empty; +assign do_push = wr_en_i & push_i & !async_full; + +//assign async_empty_o = async_empty | busy; // While RESETTING, Shows EMPTY +assign async_empty_o = async_empty_r | busy; // While RESETTING, Shows EMPTY + +assign async_full_o = async_full | busy; +assign data_o = mem_dt; + +gcc #( + .DW ( FIFO_AW ) +) gcc_wr_ptr ( + .clk_i ( wr_clk_i ) , + .rst_ni ( wr_rst_ni ) , + .async_clear_i ( clr_fifo_req ) , + .clear_o ( clr_wr ) , + .cnt_en_i ( do_push ) , + .count_bin_o ( ) , + .count_gray_o ( wr_gptr ) , + .count_bin_p1_o ( ) , + .count_gray_p1_o ( wr_gptr_p1 ) ); + +gcc #( + .DW ( FIFO_AW ) +) gcc_rd_ptr ( + .clk_i ( rd_clk_i ) , + .rst_ni ( rd_rst_ni ) , + .async_clear_i ( clr_fifo_req ) , + .clear_o ( clr_rd ) , + .cnt_en_i ( do_pop ) , + .count_bin_o ( ) , + .count_gray_o ( rd_gptr ) , + .count_bin_p1_o ( ) , + .count_gray_p1_o ( rd_gptr_p1 ) ); + +// Data +bram_dual_port_dc # ( + .MEM_AW ( FIFO_AW ) , + .MEM_DW ( FIFO_DW ) , + //.RAM_OUT ( "NO_REGISTERED" ) // Select "NO_REGISTERED" or "REGISTERED" + .RAM_OUT ( "REGISTERED" ) // Select "NO_REGISTERED" or "REGISTERED" +) fifo_mem ( + .clk_a_i ( wr_clk_i ) , + .en_a_i ( wr_en_i ) , + .we_a_i ( do_push ) , + .addr_a_i ( wr_gptr ) , + .dt_a_i ( data_i ) , + .dt_a_o ( ) , + .clk_b_i ( rd_clk_i ) , + .en_b_i ( rd_en_i ) , + .we_b_i ( 1'b0 ) , + .addr_b_i ( rd_gptr ) , + .dt_b_i ( ) , + .dt_b_o ( mem_dt ) ); + +endmodule + +`endif + + +/////////////////////////////////////////////////////////////////////////////// +// TWO inputs ALU +////////////////////////////////////////////////////////////////////////////// +module AB_alu ( + input wire clk_i , + input wire signed [31:0] A_i , + input wire signed [31:0] B_i , + input wire [3:0] alu_op_i , + output wire Z_o , + output wire C_o , + output wire S_o , + output wire signed [31:0] alu_result_o ); + +reg [32:0] result; +wire zero_flag, carry_flag, sign_flag; + +wire[3:0] shift ; +assign shift = B_i[3:0]; + +wire [31:0] neg_B, a_plus_b, a_minus_b, abs_b; +wire [31:0] msh_a, lsh_a, swap_a; +wire [31:0] a_cat_b, a_sl_b, a_lsr_b, a_asr_b ; + +assign neg_B = -B_i ; +assign a_plus_b = A_i + B_i; +assign a_minus_b = A_i + neg_B; +assign abs_b = B_i[31] ? neg_B : B_i; +assign msh_a = {16'b00000000_00000000, A_i[31:16]} ; +assign lsh_a = {16'b00000000_00000000, A_i[15: 0]} ; +assign swap_a = {A_i[15:0], A_i[31:16]} ; +assign a_cat_b = {A_i[15:0], B_i[15:0]}; +assign a_sl_b = A_i << shift ; +assign a_lsr_b = A_i >> shift ; +assign a_asr_b = A_i >>> shift ; + +always_comb begin + if (~alu_op_i[0]) + // ARITHMETIC + case ( alu_op_i[3:1] ) + 3'b000: result = a_plus_b ; + 3'b001: result = a_minus_b ; + 3'b010: result = A_i & B_i ; + 3'b011: result = a_asr_b ; + 3'b100: result = abs_b ; + 3'b101: result = msh_a ; + 3'b110: result = lsh_a ; + 3'b111: result = swap_a ; + endcase + else + // LOGIC + case ( alu_op_i[3:1] ) + 3'b000: result = ~A_i ; + 3'b001: result = A_i | B_i ; + 3'b010: result = A_i ^ B_i ; + 3'b011: result = a_cat_b ; + 3'b100: result = 0 ; + 3'b101: result = {31'b0, ^A_i} ; + 3'b110: result = a_sl_b ; + 3'b111: result = a_lsr_b ; + endcase +end + +assign zero_flag = (result == 0) ; +assign carry_flag = result[32]; +assign sign_flag = result[31]; + +assign alu_result_o = result[31:0] ; +assign Z_o = zero_flag ; +assign C_o = carry_flag ; +assign S_o = sign_flag ; + +endmodule + + +/////////////////////////////////////////////////////////////////////////////// +// DSP ARITH BLOCK +/////////////////////////////////////////////////////////////////////////////// +module arith ( + input wire clk_i , + input wire rst_ni , + input wire start_i , + input wire signed [31:0] A_i , + input wire signed [31:0] B_i , + input wire signed [31:0] C_i , + input wire signed [31:0] D_i , + input wire [4:0] alu_op_i , + output wire ready_o , + output wire signed [63:0] arith_result_o ); + +// DSP OUTPUTS +wire [45:0] arith_result ; +// DSP INPUTS +reg [3:0] ALU_OP ; + +reg signed [26:0] A_dt ; +reg signed [17:0] B_dt ; +reg signed [31:0] C_dt ; +reg signed [26:0] D_dt ; +reg working, working_r, working_r2, working_r3 ; + +always_ff @ (posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + A_dt <= 0; + B_dt <= 0; + C_dt <= 0; + D_dt <= 0; + ALU_OP <= 0; + working <= 1'b0 ; + working_r <= 1'b0 ; + working_r2 <= 1'b0 ; + working_r3 <= 1'b0 ; + end else begin + working_r <= working ; + working_r2 <= working_r ; + working_r3 <= working_r2 ; + if (start_i) begin + A_dt <= A_i[26:0] ; + B_dt <= B_i[17:0] ; + C_dt <= C_i[31:0] ; + D_dt <= D_i[26:0] ; + ALU_OP <= { alu_op_i[3:0]} ; + working <= 1'b1 ; + end else if (working_r3) begin + working <= 1'b0; + working_r <= 1'b0; + working_r2 <= 1'b0; + working_r3 <= 1'b0; + + end + end +end + + +dsp_macro_0 ARITH_DSP ( + .CLK ( clk_i ), // input wire CLK + .SEL ( ALU_OP ), // input wire [3 : 0] SEL + .A ( A_dt[26:0] ), // input wire [26 : 0] A + .B ( B_dt[17:0] ), // input wire [17 : 0] B + .C ( C_dt[31:0] ), // input wire [31 : 0] C + .D ( D_dt[26:0] ), // input wire [26 : 0] D + .P ( arith_result ) // output wire [45 : 0] P +); + +//signed extension of +assign arith_result_o = { {18{arith_result[45]}}, arith_result }; +// assign ready_o = ~ ( working | working_r ); +assign ready_o = ~ ( working ); + +endmodule + + +/////////////////////////////////////////////////////////////////////////////// +// DIVIDER REGISTERED +/////////////////////////////////////////////////////////////////////////////// +module div_r #( + parameter DW = 32 +) ( + input wire clk_i , + input wire rst_ni , + input wire start_i , + input wire [DW-1:0] A_i , + input wire [DW-1:0] B_i , + output wire ready_o , + output reg [DW-1:0] div_quotient_o , + output reg [DW-1:0] div_remainder_o ); + +// Registers +reg [DW-1:0] inB ; +reg [DW-1:0] r_temp, q_temp; +reg [4:0] ind_bit; + +reg working; + +reg qtb; +reg [2*DW-1 :0] sub_temp ; +reg [DW-1 :0] r_temp_nxt ; + +wire [31:0] ind_bit_m1; + + +assign ind_bit_m1 = ind_bit - 1'b1; +assign div_start = start_i; +assign div_end = (ind_bit==0) ; + +// State Machine +/////////////////////////////////////////////////////////////////////////// +enum {IDLE, WORKING} div_st, div_st_nxt; + +always_ff @(posedge clk_i) + if (!rst_ni) div_st <= IDLE; + else div_st <= div_st_nxt; + + +always_comb begin + div_st_nxt = div_st; + working = 1'b0; + case (div_st) + IDLE: begin + if ( div_start ) div_st_nxt = WORKING; + end + WORKING: begin + working = 1'b1; + if ( div_end ) div_st_nxt = IDLE; + end + endcase +end + +always_ff @ (posedge clk_i) begin + if (!rst_ni) begin + ind_bit <= 31; + q_temp <= 0 ; + r_temp <= 0 ; + end else if (div_start) begin + ind_bit <= 31; + q_temp <= 0 ; + r_temp <= A_i ; + inB <= B_i ; + end else if (div_end) begin + ind_bit <= 31; + q_temp <= 0 ; + r_temp <= A_i ; + inB <= B_i ; + end else if (working) begin + ind_bit <= ind_bit_m1; + r_temp <= r_temp_nxt ; + q_temp[ind_bit_m1] <= qtb ; + end +end // Always + +/////////////////////////////////////////////////////////////////////////// +// COMBINATORIAL PART +always_comb begin + qtb = 1'b0; + r_temp_nxt = r_temp ; + sub_temp = inB << ind_bit_m1 ; + if (r_temp_nxt >= sub_temp ) begin + qtb = 1'b1 ; + r_temp_nxt = r_temp_nxt - sub_temp ; + end +end + +/////////////////////////////////////////////////////////////////////////// +// OUT REG +always_ff @ (posedge clk_i) begin + if (!rst_ni) begin + div_quotient_o <= 0; + div_remainder_o <= 0 ; + end else if (div_end) begin + div_quotient_o <= q_temp; + div_remainder_o <= r_temp_nxt ; + end +end // Always + +assign ready_o = ~working; + +endmodule + + +/////////////////////////////////////////////////////////////////////////////// +// LFSR +/////////////////////////////////////////////////////////////////////////////// +module LFSR ( + input wire clk_i , + input wire rst_ni , + input wire en_i , + input wire load_we_i , + input wire [31:0] load_dt_i , + output wire [31:0] lfsr_dt_o ); + +// LFSR +/////////////////////////////////////////////////////////////////////////////// + +reg [31:0] reg_lfsr ; + +always_ff @(posedge clk_i, negedge rst_ni) + if (!rst_ni) + reg_lfsr <= 0;//32'h00000000; + else begin + if (load_we_i) + reg_lfsr <= load_dt_i ; + else if (en_i) begin + //reg_lfsr[0] <= ~^{reg_lfsr[31], reg_lfsr[21], reg_lfsr[1:0]}; + reg_lfsr[31:1] <= reg_lfsr[30:0]; + reg_lfsr[0] <= ~^{reg_lfsr[31], reg_lfsr[21], reg_lfsr[1:0]}; + end + end +assign lfsr_dt_o = reg_lfsr ; + +endmodule + +/////////////////////////////////////////////////////////////////////////////// +// INTERLEAVING DUACL CLOCK EN +/////////////////////////////////////////////////////////////////////////////// +/* +sync_ab_en sync_pulse_inst ( + .clk_a_i ( ) , + .rst_a_ni ( ) , + .clk_b_i ( ) , + .rst_b_ni ( ) , + .a_en_o ( ) , + .b_en_o ( ) ); + */ +module sync_ab_en ( + input wire clk_a_i , + input wire rst_a_ni , + input wire clk_b_i , + input wire rst_b_ni , + output wire a_en_o , + output wire b_en_o +); +/// REQ Time from C to T +/////////////////////////////////////////////////////////////////////////////// +reg a_pulse_req; +always_ff @ (posedge clk_a_i, negedge rst_a_ni) begin + if ( !rst_a_ni ) begin + a_pulse_req <= 1'b0; + end else + if ( a_pulse_ack ) a_pulse_req <= 1'b0; + else if ( !a_pulse_ack ) a_pulse_req <= 1'b1; +end + +/// Generate B PULSE +/////////////////////////////////////////////////////////////////////////////// +(* ASYNC_REG = "TRUE" *) reg pulse_req_cdc, b_pulse_req ; +reg pulse_b_req_r; +always_ff @(posedge clk_b_i) + if(!rst_b_ni) begin + pulse_req_cdc <= 0; + b_pulse_req <= 0; + end else begin + pulse_req_cdc <= a_pulse_req; + b_pulse_req <= pulse_req_cdc; + pulse_b_req_r <= b_pulse_req; + end + +assign pulse_b = b_pulse_req ^ pulse_b_req_r; + +/// ACK +/////////////////////////////////////////////////////////////////////////////// +reg b_pulse_ack; +always_ff @ (posedge clk_a_i, negedge rst_a_ni) begin + if ( !rst_a_ni ) begin + b_pulse_ack <= 1'b0; + end else + if ( b_pulse_req ) b_pulse_ack <= 1'b1; + else if ( !b_pulse_req ) b_pulse_ack <= 1'b0; +end + +(* ASYNC_REG = "TRUE" *) reg pulse_ack_cdc, a_pulse_ack ; +always_ff @(posedge clk_a_i) + if(!rst_a_ni) begin + pulse_ack_cdc <= 0; + a_pulse_ack <= 0; + end else begin + pulse_ack_cdc <= b_pulse_ack; + a_pulse_ack <= pulse_ack_cdc; + end + +assign pulse_a = a_pulse_req ~^ a_pulse_ack ; + +assign a_en_o = pulse_a; +assign b_en_o = pulse_b; + +endmodule + +/* +//////////////////////////////////////////////////////////////////////////////// +// DIVISION Pipelined 32 BIT integer +/////////////////////////////////////////////////////////////////////////////// +module div_p #( + parameter DW = 32 , + parameter N_PIPE = 32 +) ( + input wire clk_i , + input wire rst_ni , + input wire start_i , + input wire [DW-1:0] A_i , + input wire [DW-1:0] B_i , + output wire ready_o , + output wire [DW-1:0] div_quotient_o , + output wire [DW-1:0] div_remainder_o ); + +localparam comb_per_reg = DW / N_PIPE; + +reg [DW-1 : 0 ] inB ; +reg [DW-1 : 0 ] q_temp ; +reg [DW-1 : 0 ] r_temp [N_PIPE] ; +reg [DW-1 : 0 ] r_temp_nxt [N_PIPE] ; +reg [2*DW-1 : 0 ] sub_temp [N_PIPE] ; + +integer ind_comb_stage [N_PIPE]; +integer ind_bit[N_PIPE]; + +wire working; +reg [N_PIPE-1:0] en_r ; + +assign working = |en_r; + + +always_ff @ (posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + en_r <= 0 ; + r_temp[0] <= 0 ; + inB <= 0 ; + end else + if (start_i) begin + en_r <= {en_r[N_PIPE-2:0], 1'b1} ; + r_temp [0] <= A_i ; + inB <= B_i ; + end else if (working) + en_r <= {en_r[N_PIPE-2:0], 1'b0} ; +end // Always + + +/////////////////////////////////////////////////////////////////////////// +// FIRST STAGE +always @ (r_temp[0], r_temp_nxt[0], inB) begin + r_temp_nxt[0] = r_temp[0]; + for (ind_comb_stage[0]=0; ind_comb_stage[0] < comb_per_reg ; ind_comb_stage[0]=ind_comb_stage[0]+1) begin + ind_bit[0] = (DW-1) - ( ind_comb_stage[0] ) ; + sub_temp[0] = inB << ind_bit[0] ; + if (r_temp_nxt[0] >= sub_temp[0]) begin + q_temp [ind_bit[0]] = 1'b1 ; + r_temp_nxt[0] = r_temp_nxt[0] - sub_temp[0]; + end else + q_temp [ind_bit[0]] = 1'b0; + end +end + +genvar ind_reg_stage; +for (ind_reg_stage=1; ind_reg_stage < N_PIPE ; ind_reg_stage=ind_reg_stage+1) begin + // SEQUENCIAL PART + always_ff @ (posedge clk_i) begin + r_temp [ind_reg_stage] = r_temp_nxt [ind_reg_stage-1] ; + end + // COMBINATORIAL PART + always_comb begin + r_temp_nxt[ind_reg_stage] = r_temp[ind_reg_stage]; + for (ind_comb_stage[ind_reg_stage]=0; ind_comb_stage[ind_reg_stage] < comb_per_reg ; ind_comb_stage[ind_reg_stage]=ind_comb_stage[ind_reg_stage]+1) begin + ind_bit[ind_reg_stage] = (DW-1) - (ind_comb_stage[ind_reg_stage] + (ind_reg_stage * comb_per_reg)) ; + sub_temp[ind_reg_stage] = inB << ind_bit[ind_reg_stage] ; + if (r_temp_nxt[ind_reg_stage] >= sub_temp[ind_reg_stage]) begin + q_temp [ind_bit[ind_reg_stage]] = 1'b1 ; + r_temp_nxt[ind_reg_stage] = r_temp_nxt[ind_reg_stage] - sub_temp[ind_reg_stage]; + end else + q_temp [ind_bit[ind_reg_stage]] = 1'b0; + end + end +end + +assign ready_o = ~working; +assign div_quotient_o = q_temp; +assign div_remainder_o = r_temp_nxt[N_PIPE-1]; + +endmodule +module bin_2_gray # ( + parameter DW = 32 +)( + input wire [DW-1:0] count_bin_i , + output wire [DW-1:0] count_gray_o ); +assign count_gray_o = count_bin_i ^ {1'b0,count_bin_i[DW-1:1]}; +endmodule + +module gray_2_bin # ( + parameter DW = 32 +)( + input wire [DW-1:0] count_gray_i , + output reg [DW-1:0] count_bin_o ); +integer ind; +always_comb begin + count_bin_o[DW-1] = count_gray_i[DW-1]; + for (ind=DW-2 ; ind>=0; ind=ind-1) begin + count_bin_o[ind] = count_bin_o[ind+1]^count_gray_i[ind]; + end +end + +endmodule +*/ + + diff --git a/firmware/ip/qick_processor/src/axi_slv_qproc.vhd b/firmware/ip/qick_processor/src/axi_slv_qproc.vhd new file mode 100644 index 0000000..c2df595 --- /dev/null +++ b/firmware/ip/qick_processor/src/axi_slv_qproc.vhd @@ -0,0 +1,536 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv_qproc is + Generic + ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6 + ); + Port + ( + aclk : in std_logic; + aresetn : in std_logic; + + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + + -- Registers. + TPROC_CTRL : out std_logic_vector (15 downto 0) ; -- Register AUTORESET + TPROC_CFG : out std_logic_vector (15 downto 0) ; + MEM_ADDR : out std_logic_vector (15 downto 0) ; + MEM_LEN : out std_logic_vector (15 downto 0) ; + MEM_DT_I : out std_logic_vector (31 downto 0) ; + TPROC_W_DT1 : out std_logic_vector (31 downto 0) ; + TPROC_W_DT2 : out std_logic_vector (31 downto 0) ; + CORE_CFG : out std_logic_vector (7 downto 0) ; + READ_SEL : out std_logic_vector (7 downto 0) ; + MEM_DT_O : in std_logic_vector (31 downto 0) ; + TPROC_R_DT1 : in std_logic_vector (31 downto 0) ; + TPROC_R_DT2 : in std_logic_vector (31 downto 0) ; + TIME_USR : in std_logic_vector (31 downto 0) ; + TPROC_STATUS : in std_logic_vector (31 downto 0) ; + TPROC_DEBUG : in std_logic_vector (31 downto 0) ); + end axi_slv_qproc; + +architecture rtl of axi_slv_qproc is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + awreadY <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + -- Reset + if (unsigned(slv_reg0) /= 0) then slv_reg0 <= (others => '0'); end if; + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + + -- 4 : TAVG_LOW_REG (r). + -- 5 : TAVG_HIGH_REG(r). + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, MEM_DT_O, TPROC_R_DT1, TPROC_R_DT2, TIME_USR, TPROC_STATUS, TPROC_DEBUG, axi_araddr, aresetn, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= slv_reg5; + when b"0110" => + reg_data_out <= slv_reg6; + when b"0111" => + reg_data_out <= slv_reg7; + when b"1000" => + reg_data_out <= slv_reg8; + when b"1001" => + reg_data_out <= "00000000000000000000000000001001"; + when b"1010" => + reg_data_out <= MEM_DT_O; + when b"1011" => + reg_data_out <= TPROC_R_DT1; + when b"1100" => + reg_data_out <= TPROC_R_DT2; + when b"1101" => + reg_data_out <= TIME_USR; + when b"1110" => + reg_data_out <= TPROC_STATUS; + when b"1111" => + reg_data_out <= TPROC_DEBUG; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + +-- Output Registers. +TPROC_CTRL <= slv_reg0(15 downto 0); +TPROC_CFG <= slv_reg1(15 downto 0); +MEM_ADDR <= slv_reg2(15 downto 0); +MEM_LEN <= slv_reg3(15 downto 0); +MEM_DT_I <= slv_reg4(31 downto 0); +TPROC_W_DT1 <= slv_reg5(31 downto 0); +TPROC_W_DT2 <= slv_reg6(31 downto 0); +CORE_CFG <= slv_reg7(7 downto 0); +READ_SEL <= slv_reg8(7 downto 0); + + +end rtl; diff --git a/firmware/ip/qick_processor/src/axis_qick_processor.sv b/firmware/ip/qick_processor/src/axis_qick_processor.sv new file mode 100644 index 0000000..a1c8ca5 --- /dev/null +++ b/firmware/ip/qick_processor/src/axis_qick_processor.sv @@ -0,0 +1,662 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024-10-2 +// Version : 4 +// Revision : 22 (Use Assembler Version 3 Rev-23) +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: +qick_processor top level file +*/ +////////////////////////////////////////////////////////////////////////////// + +`include "_qproc_defines.svh" + +module axis_qick_processor # ( + parameter DUAL_CORE = 0 , // 0-Single Core 1-Dual core + parameter GEN_SYNC = 0 , // Generate Sync Signal + parameter IO_CTRL = 0 , // 0-No IO control 1-Add proc_strat and Proc Stop IN + parameter TIME_CTRL = 0 , // 0-No NET control 1-Add proc_strat and Proc Stop IN + parameter CORE_CTRL = 0 , // 0-No NET control 1-Add proc_strat and Proc Stop IN + parameter OUT_TIME = 0 , // + parameter DEBUG = 1 , // 0-No Debug 1-AXI control 2-Only Registers 3-Registers and OUT Signals + parameter QNET = 0 , // QNET Interfrace 0-No 1-Yes + parameter QCOM = 0 , // QCOM Interfrace 0-No 1-Yes + parameter CUSTOM_PERIPH = 0 , // PERIPH Interfrace 0-No 1-ONE 2-Two + parameter LFSR = 1 , // LFSR 0-No 1-Yes + parameter DIVIDER = 0 , // DIVIDER 0-No 1-Yes + parameter ARITH = 0 , // Arith 0-No 1-Yes + parameter EXT_FLAG = 0 , // External Flag Input 0-No 1-Yes + parameter TIME_READ = 1 , // Time in sreg and AXI-Reg 0-No 1-Yes + parameter FIFO_DEPTH = 9 , // 9 Bits in Dispatcher FIFOs address + parameter PMEM_AW = 8 , // Bits in Program Memory address + parameter DMEM_AW = 8 , // Bits in Data Memory address + parameter WMEM_AW = 8 , // Bits in WaveParam Memory address + parameter REG_AW = 4 , // Bits to address DREG + parameter IN_PORT_QTY = 1 , // Number of Input Ports + parameter OUT_TRIG_QTY = 2 , // Number of Output Trigger Ports + parameter OUT_DPORT_QTY = 1 , // Number of Output Data Ports + parameter OUT_DPORT_DW = 4 , // BitSize of Output Data Ports + parameter OUT_WPORT_QTY = 1 , // Number of Output Wave Ports + parameter CALL_DEPTH = 255 // Nested Functions + +)( +// Core, Time and AXI CLK & RST. + input wire t_clk_i , + input wire t_resetn , + input wire c_clk_i , + input wire c_resetn , + input wire ps_clk_i , + input wire ps_resetn , +// External Control + input wire ext_flag_i , + input wire proc_start_i , + input wire proc_stop_i , + input wire core_start_i , + input wire core_stop_i , + input wire time_rst_i , + input wire time_init_i , + input wire time_updt_i , + input wire [31:0] time_dt_i , + output wire [47:0] t_time_abs_o , + output wire pulse_sync_o , +//QNET + output wire qnet_en_o , + output wire [4 :0] qnet_op_o , + output wire [31:0] qnet_a_dt_o , + output wire [31:0] qnet_b_dt_o , + output wire [31:0] qnet_c_dt_o , + input wire qnet_rdy_i , + input wire [31 :0] qnet_dt1_i , + input wire [31 :0] qnet_dt2_i , + input wire qnet_vld_i , + input wire qnet_flag_i , +//QCOM + output wire qcom_en_o , + output wire [4 :0] qcom_op_o , + output wire [31:0] qcom_dt_o , + input wire qcom_rdy_i , + input wire [31 :0] qcom_dt1_i , + input wire [31 :0] qcom_dt2_i , + input wire qcom_vld_i , + input wire qcom_flag_i , +// QP1 + output wire qp1_en_o , + output wire [4 :0] qp1_op_o , + output wire [31:0] qp1_a_dt_o , + output wire [31:0] qp1_b_dt_o , + output wire [31:0] qp1_c_dt_o , + output wire [31:0] qp1_d_dt_o , + input wire qp1_rdy_i , + input wire [31 :0] qp1_dt1_i , + input wire [31 :0] qp1_dt2_i , + input wire qp1_vld_i , + input wire qp1_flag_i , +// QP2 + output wire qp2_en_o , + output wire [4 :0] qp2_op_o , + output wire [31:0] qp2_a_dt_o , + output wire [31:0] qp2_b_dt_o , + output wire [31:0] qp2_c_dt_o , + output wire [31:0] qp2_d_dt_o , + input wire qp2_rdy_i , + input wire [31 :0] qp2_dt1_i , + input wire [31 :0] qp2_dt2_i , + input wire qp2_vld_i , +// DMA AXIS FOR READ AND WRITE MEMORY + input wire [255 :0] s_dma_axis_tdata_i , + input wire s_dma_axis_tlast_i , + input wire s_dma_axis_tvalid_i , + output wire s_dma_axis_tready_o , + output wire [255 :0] m_dma_axis_tdata_o , + output wire m_dma_axis_tlast_o , + output wire m_dma_axis_tvalid_o , + input wire m_dma_axis_tready_i , +// AXI-Lite DATA Slave I/F. + input wire [7:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + input wire [31:0] s_axi_wdata , + input wire [3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + output wire [1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + input wire [7:0] s_axi_araddr , + input wire [2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + output wire [31:0] s_axi_rdata , + output wire [1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , + +/// DATA PORT INPUT + input wire [63:0] s0_axis_tdata , + input wire s0_axis_tvalid , + output wire s0_axis_tready , + input wire [63:0] s1_axis_tdata , + input wire s1_axis_tvalid , + output wire s1_axis_tready , + input wire [63:0] s2_axis_tdata , + input wire s2_axis_tvalid , + output wire s2_axis_tready , + input wire [63:0] s3_axis_tdata , + input wire s3_axis_tvalid , + output wire s3_axis_tready , + input wire [63:0] s4_axis_tdata , + input wire s4_axis_tvalid , + output wire s4_axis_tready , + input wire [63:0] s5_axis_tdata , + input wire s5_axis_tvalid , + output wire s5_axis_tready , + input wire [63:0] s6_axis_tdata , + input wire s6_axis_tvalid , + output wire s6_axis_tready , + input wire [63:0] s7_axis_tdata , + input wire s7_axis_tvalid , + output wire s7_axis_tready , + input wire [63:0] s8_axis_tdata , + input wire s8_axis_tvalid , + output wire s8_axis_tready , + input wire [63:0] s9_axis_tdata , + input wire s9_axis_tvalid , + output wire s9_axis_tready , + input wire [63:0] s10_axis_tdata , + input wire s10_axis_tvalid , + output wire s10_axis_tready , + input wire [63:0] s11_axis_tdata , + input wire s11_axis_tvalid , + output wire s11_axis_tready , + input wire [63:0] s12_axis_tdata , + input wire s12_axis_tvalid , + output wire s12_axis_tready , + input wire [63:0] s13_axis_tdata , + input wire s13_axis_tvalid , + output wire s13_axis_tready , + input wire [63:0] s14_axis_tdata , + input wire s14_axis_tvalid , + output wire s14_axis_tready , + input wire [63:0] s15_axis_tdata , + input wire s15_axis_tvalid , + output wire s15_axis_tready , +// OUT WAVE PORTS + // AXI Stream Master 0 /// + output wire [167:0] m0_axis_tdata , + output wire m0_axis_tvalid , + input wire m0_axis_tready , + output wire [167:0] m1_axis_tdata , + output wire m1_axis_tvalid , + input wire m1_axis_tready , + output wire [167:0] m2_axis_tdata , + output wire m2_axis_tvalid , + input wire m2_axis_tready , + output wire [167:0] m3_axis_tdata , + output wire m3_axis_tvalid , + input wire m3_axis_tready , + output wire [167:0] m4_axis_tdata , + output wire m4_axis_tvalid , + input wire m4_axis_tready , + output wire [167:0] m5_axis_tdata , + output wire m5_axis_tvalid , + input wire m5_axis_tready , + output wire [167:0] m6_axis_tdata , + output wire m6_axis_tvalid , + input wire m6_axis_tready , + output wire [167:0] m7_axis_tdata , + output wire m7_axis_tvalid , + input wire m7_axis_tready , + output wire [167:0] m8_axis_tdata , + output wire m8_axis_tvalid , + input wire m8_axis_tready , + output wire [167:0] m9_axis_tdata , + output wire m9_axis_tvalid , + input wire m9_axis_tready , + output wire [167:0] m10_axis_tdata , + output wire m10_axis_tvalid , + input wire m10_axis_tready , + output wire [167:0] m11_axis_tdata , + output wire m11_axis_tvalid , + input wire m11_axis_tready , + output wire [167:0] m12_axis_tdata , + output wire m12_axis_tvalid , + input wire m12_axis_tready , + output wire [167:0] m13_axis_tdata , + output wire m13_axis_tvalid , + input wire m13_axis_tready , + output wire [167:0] m14_axis_tdata , + output wire m14_axis_tvalid , + input wire m14_axis_tready , + output wire [167:0] m15_axis_tdata , + output wire m15_axis_tvalid , + input wire m15_axis_tready , + ///// TRIGGERS + output reg trig_0_o , + output reg trig_1_o , + output reg trig_2_o , + output reg trig_3_o , + output reg trig_4_o , + output reg trig_5_o , + output reg trig_6_o , + output reg trig_7_o , + output reg trig_8_o , + output reg trig_9_o , + output reg trig_10_o , + output reg trig_11_o , + output reg trig_12_o , + output reg trig_13_o , + output reg trig_14_o , + output reg trig_15_o , + output reg trig_16_o , + output reg trig_17_o , + output reg trig_18_o , + output reg trig_19_o , + output reg trig_20_o , + output reg trig_21_o , + output reg trig_22_o , + output reg trig_23_o , + output reg trig_24_o , + output reg trig_25_o , + output reg trig_26_o , + output reg trig_27_o , + output reg trig_28_o , + output reg trig_29_o , + output reg trig_30_o , + output reg trig_31_o , +// OUT DATA PORTS + output reg [OUT_DPORT_DW-1:0] port_0_dt_o , + output reg [OUT_DPORT_DW-1:0] port_1_dt_o , + output reg [OUT_DPORT_DW-1:0] port_2_dt_o , + output reg [OUT_DPORT_DW-1:0] port_3_dt_o , +// Debug Signals + output wire [31:0] ps_debug_do , + output wire [31:0] t_debug_do , + output wire [31:0] t_fifo_do , + output wire [31:0] c_time_usr_do , + output wire [31:0] c_debug_do , + output wire [31:0] c_time_ref_do , + output wire [31:0] c_proc_do , + output wire [31:0] c_port_do , + output wire [31:0] c_core_do + ); + +// DATA IN INTERFACE +reg port_tvalid_si [16]; +reg [63:0] port_tdata_si [16]; + +// TRIGGER INTERFACE +wire port_trig_so [32] ; + +// DATA OUT INTERFACE +wire [OUT_DPORT_DW-1:0] port_tdata_so [4] ; +wire port_tvalid_so [4] ; + +wire [167:0] m_axis_tdata_s [16] ; +wire m_axis_tvalid_s[16] ; +wire m_axis_tready_s[16] ; + +wire [31:0] periph_a_dt, periph_b_dt, periph_c_dt, periph_d_dt ; +wire [ 4:0] periph_op, periph_addr ; + +///// AXI LITE PORT ///// +/////////////////////////////////////////////////////////////////////////////// +TYPE_IF_AXI_REG IF_s_axireg() ; +assign IF_s_axireg.axi_awaddr = s_axi_awaddr ; +assign IF_s_axireg.axi_awprot = s_axi_awprot ; +assign IF_s_axireg.axi_awvalid = s_axi_awvalid; +assign IF_s_axireg.axi_wdata = s_axi_wdata ; +assign IF_s_axireg.axi_wstrb = s_axi_wstrb ; +assign IF_s_axireg.axi_wvalid = s_axi_wvalid ; +assign IF_s_axireg.axi_bready = s_axi_bready ; +assign IF_s_axireg.axi_araddr = s_axi_araddr ; +assign IF_s_axireg.axi_arprot = s_axi_arprot ; +assign IF_s_axireg.axi_arvalid = s_axi_arvalid; +assign IF_s_axireg.axi_rready = s_axi_rready ; +assign s_axi_awready = IF_s_axireg.axi_awready; +assign s_axi_wready = IF_s_axireg.axi_wready ; +assign s_axi_bresp = IF_s_axireg.axi_bresp ; +assign s_axi_bvalid = IF_s_axireg.axi_bvalid ; +assign s_axi_arready = IF_s_axireg.axi_arready; +assign s_axi_rdata = IF_s_axireg.axi_rdata ; +assign s_axi_rresp = IF_s_axireg.axi_rresp ; +assign s_axi_rvalid = IF_s_axireg.axi_rvalid ; + + +///// DATA IN PORTS ///// +/////////////////////////////////////////////////////////////////////////////// +always_comb begin + port_tdata_si[0] <= s0_axis_tdata ; + port_tdata_si[1] <= s1_axis_tdata ; + port_tdata_si[2] <= s2_axis_tdata ; + port_tdata_si[3] <= s3_axis_tdata ; + port_tdata_si[4] <= s4_axis_tdata ; + port_tdata_si[5] <= s5_axis_tdata ; + port_tdata_si[6] <= s6_axis_tdata ; + port_tdata_si[7] <= s7_axis_tdata ; + port_tdata_si[8] <= s8_axis_tdata ; + port_tdata_si[9] <= s9_axis_tdata ; + port_tdata_si[10] <= s10_axis_tdata ; + port_tdata_si[11] <= s11_axis_tdata ; + port_tdata_si[12] <= s12_axis_tdata ; + port_tdata_si[13] <= s13_axis_tdata ; + port_tdata_si[14] <= s14_axis_tdata ; + port_tdata_si[15] <= s15_axis_tdata ; + port_tvalid_si[0] <= s0_axis_tvalid ; + port_tvalid_si[1] <= s1_axis_tvalid ; + port_tvalid_si[2] <= s2_axis_tvalid ; + port_tvalid_si[3] <= s3_axis_tvalid ; + port_tvalid_si[4] <= s4_axis_tvalid ; + port_tvalid_si[5] <= s5_axis_tvalid ; + port_tvalid_si[6] <= s6_axis_tvalid ; + port_tvalid_si[7] <= s7_axis_tvalid ; + port_tvalid_si[8] <= s8_axis_tvalid ; + port_tvalid_si[9] <= s9_axis_tvalid ; + port_tvalid_si[10] <= s10_axis_tvalid ; + port_tvalid_si[11] <= s11_axis_tvalid ; + port_tvalid_si[12] <= s12_axis_tvalid ; + port_tvalid_si[13] <= s13_axis_tvalid ; + port_tvalid_si[14] <= s14_axis_tvalid ; + port_tvalid_si[15] <= s15_axis_tvalid ; +end + + +reg proc_start_cdc, proc_start_r, proc_start_r2; +reg proc_stop_cdc , proc_stop_r , proc_stop_r2; + + +// Syncronice to C_CLK +always_ff @(posedge c_clk_i) + if (!c_resetn) begin + proc_start_cdc <= 0 ; + proc_start_r <= 0 ; + proc_start_r2 <= 0 ; + proc_stop_cdc <= 0 ; + proc_stop_r <= 0 ; + proc_stop_r2 <= 0 ; + end else begin + proc_start_cdc <= proc_start_i ; + proc_start_r <= proc_start_cdc ; + proc_start_r2 <= proc_start_r ; + proc_stop_cdc <= proc_stop_i ; + proc_stop_r <= proc_stop_cdc ; + proc_stop_r2 <= proc_stop_r ; + end + +// The C_TPROC_CTRL is only ONE clock. +assign proc_start_t01 = proc_start_r & ~proc_start_r2 ; +assign proc_stop_t01 = proc_stop_r & ~proc_stop_r2 ; + + +qick_processor# ( + .DEBUG ( DEBUG ), + .DUAL_CORE ( DUAL_CORE ), + .LFSR ( LFSR ), + .DIVIDER ( DIVIDER ), + .ARITH ( ARITH ), + .TIME_READ ( TIME_READ ), + .FIFO_DEPTH ( FIFO_DEPTH ), + .PMEM_AW ( PMEM_AW ), + .DMEM_AW ( DMEM_AW ), + .WMEM_AW ( WMEM_AW ), + .REG_AW ( REG_AW ), + .IN_PORT_QTY ( IN_PORT_QTY ), + .OUT_TRIG_QTY ( OUT_TRIG_QTY ), + .OUT_DPORT_QTY ( OUT_DPORT_QTY ), + .OUT_DPORT_DW ( OUT_DPORT_DW ), + .OUT_WPORT_QTY ( OUT_WPORT_QTY ) +) QPROC ( + .t_clk_i ( t_clk_i ) , + .t_rst_ni ( t_resetn ) , + .c_clk_i ( c_clk_i ) , + .c_rst_ni ( c_resetn ) , + .ps_clk_i ( ps_clk_i ) , + .ps_rst_ni ( ps_resetn ) , +// CTRL + .ext_flag_i ( ext_flag_i ) , + .proc_start_i ( proc_start_t01 ) , + .proc_stop_i ( proc_stop_t01 ) , + .core_start_i ( core_start_i ) , + .core_stop_i ( core_stop_i ) , + .time_rst_i ( time_rst_i ) , + .time_init_i ( time_init_i ) , + .time_updt_i ( time_updt_i ) , + .time_updt_dt_i ( time_dt_i ) , + .time_abs_o ( t_time_abs_o ) , +// PERIPHERALS + .periph_a_dt_o ( periph_a_dt ) , + .periph_b_dt_o ( periph_b_dt ) , + .periph_c_dt_o ( periph_c_dt ) , + .periph_d_dt_o ( periph_d_dt ) , + .periph_op_o ( periph_op ) , + .qnet_en_o ( qnet_en_o ) , + .qnet_rdy_i ( qnet_rdy_i ) , + .qnet_dt_i ( {qnet_dt1_i, qnet_dt2_i} ) , + .qnet_vld_i ( qnet_vld_i ) , + .qnet_flag_i ( qnet_flag_i ) , + .qcom_en_o ( qcom_en_o ) , + .qcom_rdy_i ( qcom_rdy_i ) , + .qcom_dt_i ( {qcom_dt1_i, qcom_dt2_i} ) , + .qcom_vld_i ( qcom_vld_i ) , + .qcom_flag_i ( qcom_flag_i ) , + .qp1_en_o ( qp1_en_o ) , + .qp1_rdy_i ( qp1_rdy_i ) , + .qp1_dt_i ( {qp1_dt1_i, qp1_dt2_i}) , + .qp1_vld_i ( qp1_vld_i ) , + .qp1_flag_i ( qp1_flag_i ) , + .qp2_en_o ( qp2_en_o ) , + .qp2_rdy_i ( qp2_rdy_i ) , + .qp2_dt_i ( {qp2_dt1_i, qp2_dt2_i}) , + .qp2_vld_i ( qp2_vld_i ) , +// PS + .IF_s_axireg ( IF_s_axireg ) , + .s_dma_axis_tdata_i ( s_dma_axis_tdata_i ) , + .s_dma_axis_tlast_i ( s_dma_axis_tlast_i ) , + .s_dma_axis_tvalid_i ( s_dma_axis_tvalid_i ) , + .s_dma_axis_tready_o ( s_dma_axis_tready_o ) , + .m_dma_axis_tdata_o ( m_dma_axis_tdata_o ) , + .m_dma_axis_tlast_o ( m_dma_axis_tlast_o ) , + .m_dma_axis_tvalid_o ( m_dma_axis_tvalid_o ) , + .m_dma_axis_tready_i ( m_dma_axis_tready_i ) , +// PORTS + .port_tvalid_i ( port_tvalid_si [0:IN_PORT_QTY-1] ) , + .port_tdata_i ( port_tdata_si [0:IN_PORT_QTY-1] ) , + .port_trig_o ( port_trig_so [0:OUT_TRIG_QTY-1] ) , + .port_tvalid_o ( port_tvalid_so [0:OUT_DPORT_QTY-1] ) , + .port_tdata_o ( port_tdata_so [0:OUT_DPORT_QTY-1] ) , + .m_axis_tdata ( m_axis_tdata_s [0:OUT_WPORT_QTY-1] ) , + .m_axis_tvalid ( m_axis_tvalid_s [0:OUT_WPORT_QTY-1] ) , + .m_axis_tready ( m_axis_tready_s [0:OUT_WPORT_QTY-1] ) , +//DEBUG + .dport_di ( port_tdata_so[0][3:0] ) , + .ps_debug_do ( ps_debug_do ) , + .c_time_usr_do ( c_time_usr_do ) , + .t_debug_do ( t_debug_do ) , + .t_fifo_do ( t_fifo_do ) , + .c_debug_do ( c_debug_do ) , + .c_time_ref_do ( c_time_ref_do ) , + .c_proc_do ( c_proc_do ) , + .c_port_do ( c_port_do ) , + .c_core_do ( c_core_do ) +); + + + +// OUTPUT ASSIGNMENT +/////////////////////////////////////////////////////////////////////////////// + +///// QNET_DT +assign qnet_op_o = periph_op ; +assign qnet_a_dt_o = periph_a_dt ; +assign qnet_b_dt_o = periph_b_dt ; +assign qnet_c_dt_o = periph_c_dt ; + +///// QCOM_DT +assign qcom_op_o = periph_op ; +assign qcom_dt_o = periph_b_dt ; + +///// P1 +assign qp1_op_o = periph_op ; +assign qp1_a_dt_o = periph_a_dt ; +assign qp1_b_dt_o = periph_b_dt ; +assign qp1_c_dt_o = periph_c_dt ; +assign qp1_d_dt_o = periph_d_dt ; + +///// P2 +assign qp2_op_o = periph_op ; +assign qp2_a_dt_o = periph_a_dt ; +assign qp2_b_dt_o = periph_b_dt ; +assign qp2_c_dt_o = periph_c_dt ; +assign qp2_d_dt_o = periph_d_dt ; + +///// TRIGGER PORTS +genvar ind_t; +generate + if (OUT_TRIG_QTY < 31) + for (ind_t=31; ind_t >= OUT_TRIG_QTY; ind_t=ind_t-1) begin: TRIGGER_PORT_NOT_PRESENT + assign port_trig_so [ind_t] = 0; + end +endgenerate + +///// TRIGGERS +assign trig_0_o = port_trig_so[0] ; +assign trig_1_o = port_trig_so[1] ; +assign trig_2_o = port_trig_so[2] ; +assign trig_3_o = port_trig_so[3] ; +assign trig_4_o = port_trig_so[4] ; +assign trig_5_o = port_trig_so[5] ; +assign trig_6_o = port_trig_so[6] ; +assign trig_7_o = port_trig_so[7] ; +assign trig_8_o = port_trig_so[8] ; +assign trig_9_o = port_trig_so[9] ; +assign trig_10_o = port_trig_so[10] ; +assign trig_11_o = port_trig_so[11] ; +assign trig_12_o = port_trig_so[12] ; +assign trig_13_o = port_trig_so[13] ; +assign trig_14_o = port_trig_so[14] ; +assign trig_15_o = port_trig_so[15] ; +assign trig_16_o = port_trig_so[16] ; +assign trig_17_o = port_trig_so[17] ; +assign trig_18_o = port_trig_so[18] ; +assign trig_19_o = port_trig_so[19] ; +assign trig_20_o = port_trig_so[20] ; +assign trig_21_o = port_trig_so[21] ; +assign trig_22_o = port_trig_so[22] ; +assign trig_23_o = port_trig_so[23] ; +assign trig_24_o = port_trig_so[24] ; +assign trig_25_o = port_trig_so[25] ; +assign trig_26_o = port_trig_so[26] ; +assign trig_27_o = port_trig_so[27] ; +assign trig_28_o = port_trig_so[28] ; +assign trig_29_o = port_trig_so[29] ; +assign trig_30_o = port_trig_so[30] ; +assign trig_31_o = port_trig_so[31] ; + +///// DATA OUT PORTS +genvar ind; +generate + if (OUT_DPORT_QTY < 3) + for (ind=3; ind >= OUT_DPORT_QTY; ind=ind-1) begin: DATA_PORT_NOT_PRESENT + assign port_tdata_so [ind] = '{default:'0} ; + assign port_tvalid_so[ind] = 0; + end +endgenerate + +assign port_0_dt_o = port_tdata_so[0] ; +assign port_1_dt_o = port_tdata_so[1] ; +assign port_2_dt_o = port_tdata_so[2] ; +assign port_3_dt_o = port_tdata_so[3] ; + +///// WAVE OUT PORTS +generate + if (OUT_WPORT_QTY < 16) + for (ind=15; ind >= OUT_WPORT_QTY; ind=ind-1) begin: WAVE_PORT_NOT_PRESENT + assign m_axis_tdata_s[ind] = '{default:'0} ; + assign m_axis_tvalid_s[ind] = 0 ; + end +endgenerate + +assign s0_axis_tready = 1'b1; +assign s1_axis_tready = 1'b1; +assign s2_axis_tready = 1'b1; +assign s3_axis_tready = 1'b1; +assign s4_axis_tready = 1'b1; +assign s5_axis_tready = 1'b1; +assign s6_axis_tready = 1'b1; +assign s7_axis_tready = 1'b1; +assign s8_axis_tready = 1'b1; +assign s9_axis_tready = 1'b1; +assign s10_axis_tready = 1'b1; +assign s11_axis_tready = 1'b1; +assign s12_axis_tready = 1'b1; +assign s13_axis_tready = 1'b1; +assign s14_axis_tready = 1'b1; +assign s15_axis_tready = 1'b1; + +assign m_axis_tready_s[0] = m0_axis_tready ; +assign m_axis_tready_s[1] = m1_axis_tready ; +assign m_axis_tready_s[2] = m2_axis_tready ; +assign m_axis_tready_s[3] = m3_axis_tready ; +assign m_axis_tready_s[4] = m4_axis_tready ; +assign m_axis_tready_s[5] = m5_axis_tready ; +assign m_axis_tready_s[6] = m6_axis_tready ; +assign m_axis_tready_s[7] = m7_axis_tready ; +assign m_axis_tready_s[8] = m8_axis_tready ; +assign m_axis_tready_s[9] = m9_axis_tready ; +assign m_axis_tready_s[10] = m10_axis_tready ; +assign m_axis_tready_s[11] = m11_axis_tready ; +assign m_axis_tready_s[12] = m12_axis_tready ; +assign m_axis_tready_s[13] = m13_axis_tready ; +assign m_axis_tready_s[14] = m14_axis_tready ; +assign m_axis_tready_s[15] = m15_axis_tready ; + +assign m0_axis_tdata = m_axis_tdata_s [0] ; +assign m0_axis_tvalid = m_axis_tvalid_s[0] ; +assign m1_axis_tdata = m_axis_tdata_s [1] ; +assign m1_axis_tvalid = m_axis_tvalid_s[1] ; +assign m2_axis_tdata = m_axis_tdata_s [2] ; +assign m2_axis_tvalid = m_axis_tvalid_s[2] ; +assign m3_axis_tdata = m_axis_tdata_s [3] ; +assign m3_axis_tvalid = m_axis_tvalid_s[3] ; +assign m4_axis_tdata = m_axis_tdata_s [4] ; +assign m4_axis_tvalid = m_axis_tvalid_s[4] ; +assign m5_axis_tdata = m_axis_tdata_s [5] ; +assign m5_axis_tvalid = m_axis_tvalid_s[5] ; +assign m6_axis_tdata = m_axis_tdata_s [6] ; +assign m6_axis_tvalid = m_axis_tvalid_s[6] ; +assign m7_axis_tdata = m_axis_tdata_s [7] ; +assign m7_axis_tvalid = m_axis_tvalid_s[7] ; +assign m8_axis_tdata = m_axis_tdata_s [8] ; +assign m8_axis_tvalid = m_axis_tvalid_s[8] ; +assign m9_axis_tdata = m_axis_tdata_s [9] ; +assign m9_axis_tvalid = m_axis_tvalid_s[9] ; +assign m10_axis_tdata = m_axis_tdata_s [10] ; +assign m10_axis_tvalid = m_axis_tvalid_s[10] ; +assign m11_axis_tdata = m_axis_tdata_s [11] ; +assign m11_axis_tvalid = m_axis_tvalid_s[11] ; +assign m12_axis_tdata = m_axis_tdata_s [12] ; +assign m12_axis_tvalid = m_axis_tvalid_s[12] ; +assign m13_axis_tdata = m_axis_tdata_s [13] ; +assign m13_axis_tvalid = m_axis_tvalid_s[13] ; +assign m14_axis_tdata = m_axis_tdata_s [14] ; +assign m14_axis_tvalid = m_axis_tvalid_s[14] ; +assign m15_axis_tdata = m_axis_tdata_s [15] ; +assign m15_axis_tvalid = m_axis_tvalid_s[15] ; + + +generate + reg net_sync; + if (GEN_SYNC == 1) begin : SYNC_OUT + always_ff @ (posedge t_clk_i, negedge t_resetn) begin + if (!t_resetn) net_sync <= 1'b0; + else net_sync <= t_time_abs_o[29]; + end + assign pulse_sync_o = net_sync; + end else + assign pulse_sync_o = 0; +endgenerate + +endmodule diff --git a/firmware/ip/qick_processor/src/axis_read.v b/firmware/ip/qick_processor/src/axis_read.v new file mode 100644 index 0000000..c974e21 --- /dev/null +++ b/firmware/ip/qick_processor/src/axis_read.v @@ -0,0 +1,137 @@ +module axis_read # ( + parameter N = 10 , // Memory depth (2**N). + parameter B = 16 // Memory width. +)( + input aclk_i , + input aresetn_i , + input [N-1:0] addr_i , + input [N-1:0] len_i , + input exec_i , + output exec_ack_o , + output mem_we_o , + output [N-1:0] mem_addr_o , + input [B-1:0] mem_do_i , + input m_axis_tready_i , + output [B-1:0] m_axis_tdata_o , + output m_axis_tlast_o , + output m_axis_tvalid_o ); + +// States. +localparam INIT_ST = 0; +localparam LOAD0_ST = 1; +localparam LOAD1_ST = 2; +localparam SEND_ST = 3; +localparam ACK_ST = 4; +localparam END_ST = 5; + +// State register. +reg [2:0] state; +// State flags. +reg load0_state; +reg load1_state; +reg send_state; +reg ack_int; +// Start address and length. +reg [N-1:0] addr_r; +reg [N-1:0] len_r; +// Counter. +reg [N-1:0] cnt; +// Selection (0: mem, 1: reg). +reg sel_r; + +// Data register. +reg [B-1:0] data_r; +wire data_en; + +// Registers. +always @(posedge aclk_i) begin + if (~aresetn_i) begin + // State register. + state <= INIT_ST; + // Start address and length. + addr_r <= 0; + len_r <= 0; + // Counter. + cnt <= 0; + // Selection (0: mem, 1: reg). + sel_r <= 0; + // Data register. + data_r <= 0; + end + else begin + // State register. + case(state) + INIT_ST: + if (exec_i == 1'b1) + state <= LOAD0_ST; + LOAD0_ST: + state <= LOAD1_ST; + + LOAD1_ST: + state <= SEND_ST; + + SEND_ST: + if (cnt == len_r-1 && m_axis_tready_i) + state <= ACK_ST; + + ACK_ST: + state <= END_ST; + + END_ST: + if (exec_i == 1'b0) + state <= INIT_ST; + endcase + // Start address and length. + if (load0_state) + addr_r <= addr_i; + else if (load1_state || (send_state && m_axis_tready_i)) + addr_r <= addr_r + 1; + if (load0_state) + len_r <= len_i; + // Counter. + if (load0_state) + cnt <= 0; + else if (send_state && m_axis_tready_i) + cnt <= cnt + 1; + + // Selection (0: mem, 1: reg). + if (send_state && ~m_axis_tready_i) + sel_r <= 1; + else + sel_r <= 0; + + // Data register. + if (data_en) + data_r <= mem_do_i; + end +end + +// FSM outputs. +always @(state) begin + // Default. + load0_state = 0; + load1_state = 0; + send_state = 0; + ack_int = 0; + case (state) + //INIT_ST: + LOAD0_ST: load0_state = 1; + LOAD1_ST: load1_state = 1; + SEND_ST: send_state = 1; + ACK_ST: ack_int = 1; + //END_ST: + endcase +end + +// Data enable. +assign data_en = m_axis_tready_i | ~sel_r; + +// Assign outputs. +assign m_axis_tdata_o = (sel_r == 1)? data_r : mem_do_i; +assign m_axis_tlast_o = (cnt == len_r-1) & send_state; +assign m_axis_tvalid_o = send_state; +assign mem_we_o = 1'b0; +assign mem_addr_o = addr_r; +assign exec_ack_o = ack_int; + +endmodule diff --git a/firmware/ip/qick_processor/src/axis_write.v b/firmware/ip/qick_processor/src/axis_write.v new file mode 100644 index 0000000..4313143 --- /dev/null +++ b/firmware/ip/qick_processor/src/axis_write.v @@ -0,0 +1,151 @@ +module axis_write ( + // Reset and clock. + aclk_i , + aresetn_i , + + // AXIS Slave for receiving data. + s_axis_tdata_i , + s_axis_tlast_i , + s_axis_tvalid_i , + s_axis_tready_o , + + // Memory interface. + mem_we_o , + mem_di_o , + mem_addr_o , + + // Handshake. + exec_i , + exec_ack_o , + + // Start address. + addr_i +); + +// Parameters. +parameter N = 10; // Memory depth (2**N). +parameter B = 16; // Memory width. + +// Ports. +input aclk_i; +input aresetn_i; +input [B-1:0] s_axis_tdata_i; +input s_axis_tlast_i; +input s_axis_tvalid_i; +output s_axis_tready_o; +output mem_we_o; +output [B-1:0] mem_di_o; +output [N-1:0] mem_addr_o; +input exec_i; +output exec_ack_o; +input [N-1:0] addr_i; + +// States. +localparam INIT_ST = 0; +localparam WRITE_ST = 1; +localparam ACK_ST = 2; +localparam END_ST = 3; + +// State register. +reg [1:0] state; + +// State flags. +reg init_state; +reg write_state; +reg ack_int; + +// Address generation. +reg [N-1:0] addr_cnt; +reg [N-1:0] addr_cnt_r; + +// Data. +reg [B-1:0] data_r; + +// we generation. +wire we_int; +reg we_int_r; + +// Registers. +always @(posedge aclk_i) begin + if (~aresetn_i) begin + // State register. + state <= INIT_ST; + + // Address generation. + addr_cnt <= 0; + addr_cnt_r <= 0; + + // Data. + data_r <= 0; + + // we generation. + we_int_r <= 0; + end + else begin + // State register. + case(state) + INIT_ST: + if (exec_i == 1'b1) + state <= WRITE_ST; + + WRITE_ST: + if (s_axis_tlast_i && s_axis_tvalid_i) + state <= ACK_ST; + + ACK_ST: + state <= END_ST; + + END_ST: + if (exec_i == 1'b0) + state <= INIT_ST; + endcase + // Address generation. + if (init_state) + addr_cnt <= addr_i; + else if (s_axis_tvalid_i) + addr_cnt <= addr_cnt + 1; + + addr_cnt_r <= addr_cnt; + + // Data. + data_r <= s_axis_tdata_i; + + // we generation. + we_int_r <= we_int; + + end +end + +// FSM outputs. +always @(state) begin + // Default. + init_state = 0; + write_state = 0; + ack_int = 0; + + case (state) + INIT_ST: + init_state = 1; + + WRITE_ST: + write_state = 1; + + ACK_ST: + ack_int = 1; + + //END_ST: + endcase +end + +// we generation. +assign we_int = s_axis_tvalid_i & write_state; + +// Assign outputs. +assign s_axis_tready_o = write_state; +assign mem_we_o = we_int_r; +assign mem_di_o = data_r; +assign mem_addr_o = addr_cnt_r; +assign exec_ack_o = ack_int; + +endmodule + diff --git a/firmware/ip/qick_processor/src/data_mem_ctrl.v b/firmware/ip/qick_processor/src/data_mem_ctrl.v new file mode 100644 index 0000000..252f153 --- /dev/null +++ b/firmware/ip/qick_processor/src/data_mem_ctrl.v @@ -0,0 +1,121 @@ +// Control arbiter for memory access operations. +// +// The block arbitrates access to the memory. While executing +// either AXIS Read or Write, busy flag is asserted. If the +// busy flag is not asserted, memory can be accessed using +// single mode (external block). +// +// mem_op_i: +// * 0 : AXIS Read (from memory to m_axis). +// * 1 : AXIS Write (from s_axis to memory). +// +// mem_start_i: +// * 0 : Stop. +// * 1 : Execute Operation. +module data_mem_ctrl #( + parameter N = 16 +)( + input wire aclk_i , + input wire aresetn_i , + output wire [1:0] sel_o , + output wire ar_exec_o , + input wire ar_exec_ack_i , + output wire aw_exec_o , + input wire aw_exec_ack_i , + output wire busy_o , + input wire mem_op_i , + input wire mem_start_i ); + +// States. +localparam INIT_ST = 0; +localparam AXIS_READ_ST = 1; +localparam AXIS_READ_ACK_ST = 2; +localparam AXIS_WRITE_ST = 3; +localparam AXIS_WRITE_ACK_ST = 4; +localparam END_ST = 6; + +// State register. +reg [2:0] state; +// State flags. +reg busy_int ; +reg ar_exec_int ; +reg aw_exec_int ; +reg [1:0] sel_int ; // 0: single, 1: axis_read, 2: axis_write. + +// Registers. +always @(posedge aclk_i) begin + if (~aresetn_i) begin + // State register. + state <= INIT_ST; + end + else begin + // State register. + case(state) + INIT_ST: + if (mem_start_i == 1'b1) + if (mem_op_i == 1'b0) + // AXIS read (from memory to m_axis). + state <= AXIS_READ_ST; + else + // AXIS write (from s_axis to memory). + state <= AXIS_WRITE_ST; + AXIS_READ_ST: + state <= AXIS_READ_ACK_ST; + AXIS_READ_ACK_ST: + if (ar_exec_ack_i == 1'b1) + state <= END_ST; + AXIS_WRITE_ST: + state <= AXIS_WRITE_ACK_ST; + AXIS_WRITE_ACK_ST: + if (aw_exec_ack_i == 1'b1) + state <= END_ST; + END_ST: + if (mem_start_i == 1'b0) + state <= INIT_ST; + endcase + + end +end + +// FSM outputs. +always @(state) begin + // Default. + busy_int = 0; + ar_exec_int = 0; + aw_exec_int = 0; + sel_int = 0; + + case (state) + //INIT_ST: + + AXIS_READ_ST: begin + busy_int = 1; + sel_int = 1; + end + AXIS_READ_ACK_ST: begin + ar_exec_int = 1; + busy_int = 1; + sel_int = 1; + end + AXIS_WRITE_ST: begin + busy_int = 1; + sel_int = 2; + end + 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"value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrm_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrp_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "sclrsel_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/firmware/ip/qick_processor/src/logoQICK_128x128.png b/firmware/ip/qick_processor/src/logoQICK_128x128.png new file mode 100644 index 0000000..209264b Binary files /dev/null and b/firmware/ip/qick_processor/src/logoQICK_128x128.png differ diff --git a/firmware/ip/qick_processor/src/mem_rw.v b/firmware/ip/qick_processor/src/mem_rw.v new file mode 100644 index 0000000..897f2e9 --- /dev/null +++ b/firmware/ip/qick_processor/src/mem_rw.v @@ -0,0 +1,103 @@ +// Block to execute single read/write operation over a memory. +module mem_rw # ( + parameter N = 10 , // Memory depth (2**N). + parameter B = 16 // Memory width. +)( + input wire aclk_i , + input wire aresetn_i , + input wire rw_i , //0-READ , 1-Write + input wire exec_i , + output wire exec_ack_o , + input wire [N-1:0] addr_i , + input wire [B-1:0] di_i , + output wire [B-1:0] do_o , + output wire mem_we_o , + output wire [B-1:0] mem_di_o , + input wire [B-1:0] mem_do_i , + output wire [N-1:0] mem_addr_o ); + +// States. +localparam INIT_ST = 0; +localparam READ0_ST = 1; +localparam READ1_ST = 2; +localparam WRITE_ST = 3; +localparam ACK_ST = 4; + +// State register. +reg [2:0] state; + +// Flags. +reg init_state; +reg re_int; +reg we_int; +reg ack_int; + +// Address/data register. +reg [N-1:0] addr_r; +reg [B-1:0] din_r; +reg [B-1:0] dout_r; + +// Registers. +always @(posedge aclk_i) begin + if (~aresetn_i) begin + state <= INIT_ST; + addr_r <= 0; + din_r <= 0; + dout_r <= 0; + end else begin + // State register. + case(state) + INIT_ST: + if (exec_i == 1'b1) + if (rw_i == 1'b0) + state <= READ0_ST; + else + state <= WRITE_ST; + READ0_ST: + state <= READ1_ST; + READ1_ST: + state <= ACK_ST; + WRITE_ST: + state <= ACK_ST; + ACK_ST: + if (exec_i == 1'b0) + state <= INIT_ST; + endcase + // Address/data register. + if (init_state) begin + addr_r <= addr_i; + din_r <= di_i; + end + if (re_int) + dout_r <= mem_do_i; + end +end + +// FSM outputs. +always @(state) begin + // Default. + init_state = 0; + re_int = 0; + we_int = 0; + ack_int = 0; + case (state) + INIT_ST: + init_state = 1; + //READ0_ST: + READ1_ST: + re_int = 1; + WRITE_ST: + we_int = 1; + ACK_ST: + ack_int = 1; + endcase +end + +// Assign outputs. +assign exec_ack_o = ack_int; +assign do_o = dout_r ; +assign mem_we_o = we_int ; +assign mem_di_o = din_r ; +assign mem_addr_o = addr_r ; + +endmodule diff --git a/firmware/ip/qick_processor/src/qcore_cpu.sv b/firmware/ip/qick_processor/src/qcore_cpu.sv new file mode 100644 index 0000000..cb19ed2 --- /dev/null +++ b/firmware/ip/qick_processor/src/qcore_cpu.sv @@ -0,0 +1,726 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: + +*/ +////////////////////////////////////////////////////////////////////////////// + +`include "_qproc_defines.svh" + +module qcore_cpu # ( + parameter LFSR = 1 , + parameter PMEM_AW = 8 , + parameter DMEM_AW = 8 , + parameter WMEM_AW = 8 , + parameter REG_AW = 4 +)( + input wire clk_i , + input wire rst_ni , + input wire restart_i , + input wire en_i , + input wire [1:0] lfsr_cfg_i , // CONFIGURATION (LFSR) + output wire [31:0] lfsr_o , +// DEBUG + output wire [31:0] core_do , // Core Signal Debug +// CONDITIONS + input wire flag_i , // External Condition +// DATA INPUT + output wire [7:0] sreg_cfg_o , + output wire [7:0] sreg_ctrl_o , + input wire [31:0] sreg_arith_i , + input wire [31:0] sreg_div_i [2] , + input wire [31:0] sreg_status_i , + input wire [31:0] sreg_core_r_dt_i[2] , + input wire [31:0] sreg_port_dt_i [2] , + input wire [31:0] sreg_time_dt_i , + output wire [31:0] sreg_core_w_dt_o[2] , + output wire usr_en_o , // CONTROL Enable + output wire [7:0] usr_ctrl_o , // CONTROL from Current Instruction + output wire [31:0] usr_dt_a_o , // Data A from Current Instruction (rsD0) + output wire [31:0] usr_dt_b_o , // Data B from Current Instruction (rsD1) + output wire [31:0] usr_dt_c_o , // Data C from Current Instruction (rsA0) + output wire [31:0] usr_dt_d_o , // Data D from Current Instruction (rsA1m) +// PROGRAM MEMORY + output wire [PMEM_AW-1:0] pmem_addr_o , + output wire pmem_en_o , + input wire [71:0] pmem_dt_i , +// DATA MEMORY + output wire dmem_we_o , + output wire [DMEM_AW-1:0] dmem_addr_o , + output wire [31:0] dmem_w_dt_o , + input wire [31:0] dmem_r_dt_i , +// WAVE MEMORY + output wire wmem_we_o , + output wire [WMEM_AW-1:0] wmem_addr_o , + output wire [167:0] wmem_w_dt_o , + input wire [167:0] wmem_r_dt_i , +//OUTPUT PORTS + output wire port_we_o , + output wire port_re_o , + output PORT_DT port_o + ); + +/////////////////////////////////////////////////////////////////////////////// +// Signal Declaration + +// Address Signals +reg [10:0] r_id_imm_addr, r_rd_imm_addr ; +reg [5:0] r_rd_rsA1_addr ; +wire [PMEM_AW-1:0] reg_addr; +//Data Signals +reg [31 :0] r_id_imm_dt, r_rd_imm_dt, r_x1_imm_dt; +reg [31 :0] r_x1_alu_dt ; +// Data Signals +wire [31:0] x1_alu_dt ; +wire x1_alu_fZ, x1_alu_fC, x1_alu_fS ; +wire [WMEM_AW-1:0] x1_wave_addr ; +// Pipeline registers. +reg [PMEM_AW-1 : 0] PC_curr, PC_nxt, PC_prev ; +reg [2:0] cfg_pc_nxt; + +wire id_pc_change; +reg r_id_pc_change ; +reg [5:0] r_id_rs_A_addr [2] ; // Address in the RegBank +reg [6:0] r_id_rs_D_addr [2] ; // Address in the RegBank +wire [31:0] reg_D_fwd_dt [2] ; +wire [31:0] reg_A_fwd_dt [2] ; +wire [31:0] reg_time ; + +// PROCESSOR STATUS +/////////////////////////////////////////////////////////////////////////////// +wire halt, flush, stall, bubble_id, bubble_rd; + +assign halt = ~en_i ; +assign flush = id_pc_change | r_id_pc_change ; +assign stall = bubble_id | bubble_rd; +assign fetch_en = ~stall & ~halt; + + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// IF - 1 FIRST Stage IF_ ( Instruction FECTH ) +/////////////////////////////////////////////////////////////////////////////////////////////////// + +wire [ 15 : 0 ] if_op_code ; +wire [ 55 : 0 ] if_op_data ; +reg [ 15 : 0 ] r_if_op_code ; +reg [ 55 : 0 ] r_if_op_data ; +reg r_mem_rst; +assign if_op_code = pmem_dt_i [ 71 : 56 ] ; +assign if_op_data = pmem_dt_i [ 55 : 0 ] ; + +// empty memory Pipeline +always_ff @ (posedge clk_i) begin + if (!rst_ni) begin + r_mem_rst <= 1; + r_if_op_code <= 0; + r_if_op_data <= 0; + end else if (restart_i) begin + r_mem_rst <= 1; + r_if_op_code <= 0; + r_if_op_data <= 0; + end else begin + r_mem_rst <= 0; + if (pmem_en_o) begin + if (flush) begin + r_if_op_code <= 0; + r_if_op_data <= 0; + end else begin + r_if_op_code <= if_op_code; + r_if_op_data <= if_op_data; + end + end + end + +end + + +/////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////// +// ID - 2 SECOND STAGE ID_ INSTRUCTION DECODER +/////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////// + +// CONTROL +/////////////////////////////////////////////////////////// +wire [2:0] id_HEADER ; +wire id_AI ; +wire [1:0] id_DF ; +wire [2:0] id_COND; +wire id_SO, id_TO; + +assign id_HEADER = r_if_op_code [ 15 : 13 ] ; +assign id_AI = r_if_op_code [ 12 ] ; +assign id_DF = r_if_op_code [ 11 : 10] ; +assign id_COND = r_if_op_code [ 9 : 7 ] ; +assign id_SO = r_if_op_code [ 6 ] ; +assign id_TO = r_if_op_code [ 5 ] ; + + +reg id_type_cfg, id_type_br, id_type_int_ctrl, id_type_ext_ctrl; +reg id_type_wr, id_type_wrd, id_type_wrw, id_type_wra ; +reg id_type_wp, id_type_wpd, id_type_wpw ; +reg id_type_wm, id_type_wmd, id_type_wmw; + +reg id_cfg_port_src, id_cfg_alu_src, id_cfg_dt_imm ; +reg [3:0] id_cfg_alu_op ; +reg [1:0] id_cfg_reg_src ; +reg cfg_dual_regs_en, cfg_flag_en, cfg_dual_port_en, cfg_dual_wmem_en ; +reg cfg_dual_regs_we, cfg_dual_port_we, cfg_dual_wmem_we ; +reg id_flag_we; +reg id_dmem_we , id_wmem_we ; +reg id_dreg_we , id_r_wave_we ; +reg id_dport_re, id_dport_we, id_wport_we ; + +reg id_call, id_ret ; + +reg [8:0] id_usr_ctrl; // MSB indicate Internal or External +reg id_cond_ok, id_exec_ok, id_branch_cond_ok; +reg alu_fZ_r, alu_fS_r; + +reg id_wpd_imm, id_periph_imm; + +always_comb begin : DECODER + id_type_cfg = ( id_HEADER == CFG ) ; + id_type_br = ( id_HEADER == BRANCH ) ; + id_type_wr = ( id_HEADER == REG_WR ) ; + id_type_wm = ( id_HEADER == MEM_WR ) ; + id_type_wp = ( id_HEADER == PORT_WR ) ; + id_type_int_ctrl = ( id_HEADER == INT_CTRL ) ; + id_type_ext_ctrl = ( id_HEADER == EXT_CTRL ) ; + id_type_wra = id_type_wr & (~id_SO & ~id_TO) ; // Write Data Register from ALU + id_type_wrd = id_type_wr & ~(id_SO & ~id_TO) ; // Write Data Register (ALU, MEM, or IMM) + id_type_wrw = id_type_wr & (id_SO & ~id_TO) ; // Write Wave Data Register + id_type_wmd = id_type_wm & ~id_SO ; // Write Data Memory + id_type_wmw = id_type_wm & id_SO ; // Write Wave Memory + id_type_wpd = id_type_wp & ~id_SO ; // Write Data Port + id_type_wpw = id_type_wp & id_SO ; // Write Wave Port + + id_cfg_port_src = r_if_op_code[8] ; + //id_wpd_imm = id_type_wpd & id_cfg_port_src ; + //id_periph_imm = id_type_int_ctrl & id_AI; + //id_cfg_dt_imm = &id_DF | ( (id_type_wm | id_type_cfg) & id_TO ) | id_wpd_imm | id_periph_imm ; // Immediate input Data + id_cfg_dt_imm = &id_DF | ( (id_type_wm | id_type_cfg) & id_TO ) | (id_type_wpd & id_cfg_port_src) ; // Immediate input Data + id_cfg_alu_src = ( id_DF == 2'b10) ; //With DI=10 Source =1 + id_cfg_alu_op = id_type_wra ? r_if_op_code[3:0] : {1'b0, r_if_op_code[1:0], 1'b0 } ; + id_cfg_reg_src = id_type_wrd ? r_if_op_code[6:5] : {2{r_if_op_code [2]}} ; // When Writing WAVE Second OPTION + cfg_dual_regs_en = ( id_type_wrw | id_type_wm | id_type_wp | id_type_br | id_type_cfg ) ; // Is Possible to + cfg_flag_en = cfg_dual_regs_en | id_type_wr ; // Is Possible to Update Flag + cfg_dual_port_en = id_type_wrw | id_type_wmw ; // Is Possible to Dual PORT WRITE + cfg_dual_wmem_en = id_type_wrw | id_type_wpw ; // Is Possible to Dual WaveForm MEM WRITE + cfg_dual_regs_we = cfg_dual_regs_en & r_if_op_code[3] ; // Dual REGISTER WRITE ENABLE + cfg_dual_port_we = cfg_dual_port_en & r_if_op_code[7] ; // Dual PORT WRITE ENABLE + cfg_dual_wmem_we = cfg_dual_wmem_en & r_if_op_code[9] ; // Dual WMEM WRITE ENABLE + id_flag_we = id_exec_ok & cfg_flag_en & r_if_op_code[4] ; // Flag WRITE ENABLE + id_dreg_we = id_exec_ok & ( id_type_wrd | cfg_dual_regs_we ) ; // DREG WRITE ENABLE + id_r_wave_we = id_type_wrw ; // WREG WRITE ENABLE (The 167 Bits) + id_dmem_we = id_exec_ok & ( id_type_wmd ) ; // DMEM WRITE ENABLE + id_wmem_we = id_type_wmw | cfg_dual_wmem_we & r_if_op_code[9] ; // WMEM WRITE ENABLE + id_dport_we = id_type_wpd & r_if_op_code[7] ; // DPORT WRITE ENABLE + id_dport_re = id_type_wpd & ~r_if_op_code[7] ; // DPORT READ ENABLE + id_wport_we = id_type_wpw | cfg_dual_port_we ; // WPORT WRITE ENABLE + id_call = id_branch_cond_ok & id_SO & ~id_TO ; // Execute CALL Instruction (Push) + id_ret = id_type_br & id_SO & id_TO ; // Execute RET Instruction (Pull) + id_usr_ctrl = id_type_int_ctrl ? {id_exec_ok, 1'b0, r_if_op_code[6:0]} : id_type_ext_ctrl ? {id_exec_ok,1'b1,r_if_op_code[6:0]} : 9'b000000000 ; +end + + + +reg [ 31 : 0 ] id_imm_dt ; +reg [15:0] id_imm_addr ; +reg [5 :0] id_rs_A_addr [2]; +reg [6 :0] id_rs_D_addr [2]; +reg [6 :0] id_rd_addr ; +wire [PMEM_AW-1:0] pc_stack; + +/////////////////////////////////////////////////////////////////////////////// +// DATA +always_comb + unique case (id_DF) + 2'b00 : id_imm_dt = id_imm_addr ; // Data Immediate is 16 Bits Address Space + 2'b01 : id_imm_dt = { {16{r_if_op_data[22]}} , r_if_op_data [22:7]} ; // Data Immediate is 16 Bits SIGNED + 2'b10 : id_imm_dt = { { 8{r_if_op_data[30]}} , r_if_op_data [30:7]} ; // Data Immediate is 24 Bits SIGNED + 2'b11 : id_imm_dt = r_if_op_data [38:7] ; // Data Immediate is 32 Bits + endcase + +/////////////////////////////////////////////////////////////////////////////// +// ADDRESS +// Immediate DATA is not Register ADDRESS +//assign id_use_RA0 = id_AI; +//assign id_use_RA1 = id_type_wmd | (id_type_wr & (~id_SO & id_TO)); +assign id_use_RD0 = id_DF != 2'b11; +assign id_use_RD1 = id_DF == 2'b01; + +assign id_type_wr_dmem = id_type_wr & (~id_SO & id_TO); // Write Data Register from DMEM + +always_comb begin + id_imm_addr = r_if_op_data [ 55 : 45 ] ; + id_rs_A_addr[0] = r_if_op_data [ 50 : 45 ] ; + id_rs_A_addr[1] = r_if_op_data [ 44 : 39 ] ; + id_rs_D_addr[0] = id_use_RD0 ? r_if_op_data [ 37 : 31 ] : 0 ; + id_rs_D_addr[1] = id_use_RD1 ? r_if_op_data [ 29 : 23 ] : 0 ; + id_rd_addr = r_if_op_data [ 6 : 0 ] ; +end + +assign id_reg.we = id_dreg_we ; +assign id_reg.r_wave_we = id_r_wave_we ; +assign id_reg.addr = id_rd_addr ; +assign id_reg.src = id_cfg_reg_src ; +assign id_reg.port_re = id_dport_re ; + +assign id_ctrl.cfg_addr_imm = id_AI ; +assign id_ctrl.cfg_dt_imm = id_cfg_dt_imm ; +assign id_ctrl.cfg_port_src = id_cfg_port_src ; +assign id_ctrl.cfg_port_type = id_type_wpd ; +assign id_ctrl.cfg_port_time = id_type_wp & id_TO ; +assign id_ctrl.cfg_cond = id_COND ; +assign id_ctrl.cfg_alu_src = id_cfg_alu_src ; +assign id_ctrl.cfg_alu_op = id_cfg_alu_op ; +assign id_ctrl.usr_ctrl = id_usr_ctrl ; +assign id_ctrl.flag_we = id_flag_we ; +assign id_ctrl.dmem_we = id_dmem_we ; +assign id_ctrl.wmem_we = id_wmem_we ; +assign id_ctrl.port_we = id_wport_we | id_dport_we ; + + +// CONDITION +///////////////////////////////////////////////// + +reg id_cond_used, id_flag_used ; +always_comb begin + unique case ( id_COND ) + 3'b000: id_cond_ok = 1 ; // ALWAYS + 3'b001: id_cond_ok = alu_fZ_r ; //EQ - Z + 3'b010: id_cond_ok = alu_fS_r ; //LT - S + 3'b011: id_cond_ok = ~alu_fZ_r ; //NZ -not(Z) + 3'b100: id_cond_ok = ~alu_fS_r ; //NS -not(S) + 3'b101: id_cond_ok = flag_i ; // External Flag + 3'b110: id_cond_ok = ~flag_i ; // NOT External Flag + 3'b111: id_cond_ok = 0 ; // RFU + endcase + id_cond_used = id_type_cfg | id_type_wra | id_type_wrd | id_type_wmd | id_type_br | id_type_int_ctrl | id_type_ext_ctrl ; // Conditional Instruction + id_flag_used = id_cond_used & |id_COND ; // Condition should be checked + id_exec_ok = id_cond_ok | ~id_cond_used ; // Execute Instruction + id_branch_cond_ok = id_type_br & id_exec_ok ; // Execute BRANCH +end + + +// PC_ADDR CALCULATION +///////////////////////////////////////////////// +always_comb begin + cfg_pc_nxt = 2'b00; // Move to Next Address + if ( id_ret ) cfg_pc_nxt = 2'b11; // Return from CALL RET is NOT conditional + else if (id_branch_cond_ok) + if (id_AI) cfg_pc_nxt = 2'b01 ; // Jump to IMM Address + else cfg_pc_nxt = 2'b10; // Jump to REG Address +end + +wire id_jmp_reg_used; +assign id_jmp_reg_used = (cfg_pc_nxt == 2'b10) ; + +assign id_pc_change = |cfg_pc_nxt; + +always_comb + unique case (cfg_pc_nxt ) + 2'b00: PC_nxt = PC_curr + 1 ; + 2'b01: PC_nxt = id_imm_addr ; + 2'b10: PC_nxt = reg_addr ; + 2'b11: PC_nxt = pc_stack ; + endcase + +always @(posedge clk_i) begin + if (!rst_ni) begin + PC_curr <= 0; + PC_prev <= 0; + end else begin + if (restart_i) begin + PC_curr <= 0; + PC_prev <= 0; + end else if (fetch_en) begin + PC_curr <= PC_nxt; + PC_prev <= PC_curr; + end + end +end + + + +// X1 - 4 FOURTH STAGE - ADDRESS CALCULATION - EXECUTE_1 +/////////////////////////////////////////////////////////////////////////////////////////////////// + +wire [31:0] x1_rsD0_dt, x1_rsD1_dt ; +wire [31:0] x1_rsA1_dt, x1_rsA0_dt ; +wire [31:0] rs_A_dt [2] ; +wire [31:0] rs_D_dt [2] ; + + +assign x1_rsA0_dt = x1_ctrl.cfg_addr_imm ? r_rd_imm_addr : reg_A_fwd_dt[0] ; +assign x1_rsA1_dt = reg_A_fwd_dt[1] ; +assign x1_rsD0_dt = reg_D_fwd_dt[0] ; +assign x1_rsD1_dt = reg_D_fwd_dt[1] ; + +// ARITHMETIC UNIT +///////////////////////////////////////////////// +reg [31:0] x1_alu_in_A, x1_alu_in_B ; +assign x1_alu_in_A = x1_rsD0_dt; +assign x1_alu_in_B = x1_ctrl.cfg_alu_src ? r_rd_imm_dt : x1_rsD1_dt ; + +// DATA MEMORY +///////////////////////////////////////////////// +wire [DMEM_AW-1:0] x1_mem_addr ; +wire [31:0] x1_mem_w_dt ; +assign x1_mem_addr = x1_rsA0_dt + x1_rsA1_dt ; +assign x1_mem_w_dt = x1_ctrl.cfg_dt_imm ? r_rd_imm_dt : x1_alu_dt ; + +// WAVE MEMORY +/////////////////////////////////////////////////////////////////////////////// +assign x1_wave_addr = x1_rsA0_dt[WMEM_AW-1:0] ; + +// PORT +/////////////////////////////////////////////////////////////////////////////// +wire [5:0] x1_port_w_addr; +assign x1_port_w_addr = r_rd_rsA1_addr[5:0] ; + + +/////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////// +// X2 - 5 FIFTH STAGE X2_ - EXECUTE_2 +/////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////// + +reg [167:0] reg_wave_dt ; + +// Input to Register Bank +reg [31:0] x2_reg_w_dt ; + +always_comb begin +// Data Input + case (x2_reg.src) + 2'b00: x2_reg_w_dt = r_x1_alu_dt ; + 2'b01: x2_reg_w_dt = dmem_r_dt_i ; + 2'b10: x2_reg_w_dt = r_x1_alu_dt ; + 2'b11: x2_reg_w_dt = r_x1_imm_dt ; + + endcase +end + + +// WAVE +///////////////////////////////////////////////// +wire [167:0] x2_wave_w_dt; +assign x2_wave_w_dt = x2_ctrl.cfg_port_src ? reg_wave_dt : wmem_r_dt_i ; + +// PORT +///////////////////////////////////////////////// +wire [167:0] x2_port_w_dt ; +reg [5:0] r_x1_port_w_addr; + + +reg [31:0] r_x1_port_dt; + +assign x2_port_w_dt = x2_ctrl.cfg_port_type ? r_x1_port_dt : x2_wave_w_dt ; + + +/////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////// +// INSTANCES +/////////////////////////////////////////////////////////////////////////////// + +CTRL_REG id_reg, rd_reg, x1_reg, x2_reg, wr_reg ; +CTRL_FLOW id_ctrl, rd_ctrl, x1_ctrl, x2_ctrl ; + +qcore_ctrl_hazard ctrl_hzrd ( + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .halt_i ( halt ) , + .rs_A_addr_i ( r_id_rs_A_addr ) , + .rs_A_dt_i ( rs_A_dt ) , + .rs_D_addr_i ( r_id_rs_D_addr ) , + .rs_D_dt_i ( rs_D_dt ) , + // Register Write Enable + .id_reg_i ( id_reg ) , + .rd_reg_i ( rd_reg ) , + .x1_reg_i ( x1_reg ) , + .x2_reg_i ( x2_reg ) , + .wr_reg_i ( wr_reg ) , + // Peripheral + .rd_periph_use ( rd_ctrl.usr_ctrl[8] ) , + .x1_periph_use ( x1_ctrl.usr_ctrl[8] ) , + .x2_periph_use ( x2_ctrl.usr_ctrl[8] ) , + // Port Write + .id_type_wp ( id_type_wp ), + .port_we ( rd_ctrl.port_we | x1_ctrl.port_we /*| x2_ctrl.port_we*/ ), + // Wave Register + .id_wmem_we ( id_wmem_we ) , //r_wave will be READ + // FLAG + .id_flag_used ( id_flag_used ) , // SELECCIONAR CORRECTAMENTE WR/MEM_WR and JUMPD + .flag_we ( rd_ctrl.flag_we | x1_ctrl.flag_we ) , + // PC JUMP + .id_jmp_i ( id_jmp_reg_used ) , + // ALU (00) Data in each Pipeline Stage + .x1_alu_dt_i ( x1_alu_dt ) , + .x2_alu_dt_i ( r_x1_alu_dt ) , + // DMEM (01) in each Pipeline Stage + .x2_dmem_dt_i (dmem_r_dt_i) , + // Imm Data in each Pipeline Stage + .rd_imm_dt_i ( r_id_imm_dt ) , + .x1_imm_dt_i ( r_rd_imm_dt ) , + .x2_imm_dt_i ( r_x1_imm_dt ) , + // Data Memory Write Enable + .reg_A_dt_o ( reg_A_fwd_dt ) , + .reg_D_dt_o ( reg_D_fwd_dt ) , + .bubble_id_o ( bubble_id ) , + .bubble_rd_o ( bubble_rd ) ); + +// REG BANK +///////////////////////////////////////////////// +qcore_reg_bank # ( + .LFSR (LFSR) , + .PMEM_AW (PMEM_AW) , + .REG_AW (REG_AW) +) reg_bank ( + .clk_i ( clk_i ) , + .halt_i ( halt ) , + .rst_ni ( rst_ni ) , + .clear_i ( restart_i ) , + .lfsr_cfg_i ( lfsr_cfg_i ) , + .reg_arith_i ( sreg_arith_i ) , + .reg_div_i ( sreg_div_i ) , + .reg_port_i ( sreg_port_dt_i ) , + .tproc_ext_i ( sreg_core_r_dt_i ) , + .status_i ( sreg_status_i ) , + .reg_cfg_o ( sreg_cfg_o ) , + .reg_ctrl_o ( sreg_ctrl_o ) , + .time_dt_i ( sreg_time_dt_i ) , + .wave_we_i ( x2_reg.r_wave_we ) , + .we_i ( x2_reg.we ) , + .w_addr_i ( x2_reg.addr ) , + .w_dt_i ( x2_reg_w_dt ) , + .wave_dt_i ( x2_wave_w_dt ) , + .rs_A_addr_i ( r_id_rs_A_addr ) , + .rs_D_addr_i ( r_id_rs_D_addr ) , + .rs_A_dt_o ( rs_A_dt ) , + .rs_D_dt_o ( rs_D_dt ) , + .sreg_dt_o ( sreg_core_w_dt_o ) , + .out_addr_o ( reg_addr ) , + .out_time_o ( reg_time ) , + .out_wreg_o ( reg_wave_dt ) , + .lfsr_o ( lfsr_o ) );// + +// ALU - 2 Inputs +///////////////////////////////////////////////// +AB_alu alu ( + .clk_i ( clk_i ) , + .A_i ( x1_alu_in_A ) , + .B_i ( x1_alu_in_B ) , + .alu_op_i ( x1_ctrl.cfg_alu_op ) , + .Z_o ( x1_alu_fZ ) , + .C_o ( x1_alu_fC ) , + .S_o ( x1_alu_fS ) , + .alu_result_o ( x1_alu_dt ) ); + + +wire pc_stack_full; +// PC STACK +///////////////////////////////////////////////// +///////////////////////////////////////////////// +LIFO # ( + .WIDTH ( PMEM_AW ) , + .DEPTH ( 8 ) +) pc_stack_inst ( + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .data_i ( PC_prev ) , + .push ( id_call & fetch_en ) , + .pop ( id_ret & fetch_en ) , + .data_o ( pc_stack ) , + .full_o ( pc_stack_full ) ); + + + +assign halt = ~en_i ; +assign flush = id_pc_change | r_id_pc_change ; +assign stall = bubble_id | bubble_rd; +assign fetch_en = ~stall & ~halt; + +/////////////////////////////////////////////////////////////////////////////// +// PIPELINE +/////////////////////////////////////////////////////////////////////////////// + +assign id_stage_keep = !fetch_en ; +assign rd_stage_keep = bubble_rd ; +assign rd_stage_zero = bubble_id & !bubble_rd ; +assign x1_stage_zero = bubble_rd ; + + +// DATA & ADDRESS PIPELINE +always_ff @ (posedge clk_i) begin + if (!rst_ni) begin + // CONTROL SIGNALS + r_id_pc_change <= 0 ; + rd_ctrl <= '{default:'0}; + x1_ctrl <= '{default:'0}; + x2_ctrl <= '{default:'0}; + rd_reg <= '{default:'0}; + x1_reg <= '{default:'0}; + x2_reg <= '{default:'0}; + wr_reg <= '{default:'0}; + //Address Signals + r_id_imm_addr <= 0 ; + r_rd_imm_addr <= 0 ; +// r_rd_rsA0_addr <= 0 ; + r_rd_rsA1_addr <= 0 ; + r_id_rs_A_addr <= '{default:'0}; + r_id_rs_D_addr <= '{default:'0}; + //Data Signals + r_id_imm_dt <= 0 ; + r_rd_imm_dt <= 0 ; + r_x1_imm_dt <= 0 ; + r_x1_alu_dt <= 0 ; + r_x1_port_dt <= 0 ; + alu_fZ_r <= 0 ; + alu_fS_r <= 0 ; + end else if (restart_i ) begin + r_id_pc_change <= 0 ; + rd_ctrl <= '{default:'0}; + x1_ctrl <= '{default:'0}; + x2_ctrl <= '{default:'0}; + rd_reg <= '{default:'0}; + x1_reg <= '{default:'0}; + x2_reg <= '{default:'0}; + wr_reg <= '{default:'0}; + r_id_imm_addr <= 0 ; + r_rd_imm_addr <= 0 ; +// r_rd_rsA0_addr <= 0 ; + r_rd_rsA1_addr <= 0 ; + r_id_rs_A_addr <= '{default:'0}; + r_id_rs_D_addr <= '{default:'0}; + r_id_imm_dt <= 0 ; + r_rd_imm_dt <= 0 ; + r_x1_imm_dt <= 0 ; + r_x1_alu_dt <= 0 ; + r_x1_port_dt <= 0 ; + alu_fZ_r <= 0 ; + alu_fS_r <= 0 ; + r_x1_port_w_addr <= 0 ; + end else begin + if (~halt) begin + + ///////////////////////////////////////////////////////// + // STAGE > READ + if ( rd_stage_zero ) begin + rd_ctrl <= '{default:'0}; + rd_reg <= '{default:'0}; + r_id_pc_change <= 1'b0; + r_id_imm_dt <= '{default:'0}; + r_id_imm_addr <= '{default:'0}; + r_id_rs_D_addr <= '{default:'0}; + r_id_rs_A_addr <= '{default:'0}; + end else if ( rd_stage_keep ) begin + rd_ctrl <= rd_ctrl; + rd_reg <= rd_reg; + r_id_pc_change <= r_id_pc_change; + r_id_imm_dt <= r_id_imm_dt; + r_id_imm_addr <= r_id_imm_addr; + r_id_rs_D_addr <= r_id_rs_D_addr; + r_id_rs_A_addr <= r_id_rs_A_addr; + end else begin + //Control Signals + rd_ctrl <= id_ctrl ; + rd_reg <= id_reg ; + r_id_pc_change <= id_pc_change ; + //Data Signals + r_id_imm_dt <= id_imm_dt ; + r_id_imm_addr <= id_imm_addr ; + r_id_rs_D_addr <= id_rs_D_addr ; + r_id_rs_A_addr <= id_rs_A_addr; + end + + ///////////////////////////////////////////////////////// + // STAGE > EXECUTE 1 + if ( x1_stage_zero ) begin + x1_ctrl <= '{default:'0}; + x1_reg <= '{default:'0}; + r_rd_imm_dt <= '{default:'0}; + r_rd_imm_addr <= '{default:'0}; + r_rd_rsA1_addr <= '{default:'0}; + end else begin + x1_ctrl <= rd_ctrl ; + x1_reg <= rd_reg ; + r_rd_imm_dt <= r_id_imm_dt ; + r_rd_imm_addr <= r_id_imm_addr ; + r_rd_rsA1_addr <= r_id_rs_A_addr[1] ; + end + + ///////////////////////////////////////////////////////// + // STAGE > EXECUTE 2 + //Control Signals + x2_ctrl <= x1_ctrl ; + x2_reg <= x1_reg ; + //Data Signals + r_x1_imm_dt <= r_rd_imm_dt ; + r_x1_alu_dt <= x1_alu_dt ; + r_x1_port_dt <= x1_rsA0_dt ; + r_x1_port_w_addr <= x1_port_w_addr ; + if (x1_ctrl.flag_we) begin + alu_fZ_r <= x1_alu_fZ ; + alu_fS_r <= x1_alu_fS ; + end + + ///////////////////////////////////////////////////////// + // STAGE > WRITE + //Control Signals + wr_reg <= x2_reg ; + + end //(~HALT) + end //NotRST +end //ALWAYS + +///////////////////////////////////////////////////////////////////////////////////////// +// OUTPUTS +///////////////////////////////////////////////////////////////////////////////////////// + +// PROGRAM MEMORY +assign pmem_en_o = fetch_en | r_mem_rst; +assign pmem_addr_o = PC_curr ; // Disable next instruction with pc_jump + +// DATA MEMORY +assign dmem_we_o = halt ? 0 : x1_ctrl.dmem_we; +assign dmem_addr_o = x1_mem_addr ; +assign dmem_w_dt_o = x1_mem_w_dt ; + +// WAVE MEMORY +assign wmem_we_o = halt ? 0 : x1_ctrl.wmem_we; +assign wmem_addr_o = x1_wave_addr ; +assign wmem_w_dt_o = reg_wave_dt ; + +// PERIPH OUT +// assign = <1-bit_select> ? : ; +assign usr_en_o = halt ? 0 : x1_ctrl.usr_ctrl[8] ; +assign usr_ctrl_o = halt ? 0 : x1_ctrl.usr_ctrl[7:0] ; +assign usr_dt_a_o = x1_rsD0_dt ; +assign usr_dt_b_o = x1_ctrl.cfg_dt_imm ? r_rd_imm_dt : x1_rsD1_dt ; +assign usr_dt_c_o = x1_rsA0_dt ; +assign usr_dt_d_o = x1_rsA1_dt; + +// PORT OUTPUT +assign port_we_o = halt ? 0 : x2_ctrl.port_we ; +assign port_re_o = halt ? 0 : x2_reg.port_re ; + +assign port_o.p_time = x2_ctrl.cfg_port_time ? r_x1_imm_dt : reg_time; +assign port_o.p_type = x2_ctrl.cfg_port_type ; +assign port_o.p_addr = r_x1_port_w_addr ; +assign port_o.p_data = x2_port_w_dt ; + +// DEBUG +assign core_do [31:24] = {restart_i, stall, flush, id_flag_we, alu_fZ_r, alu_fS_r, x2_ctrl.port_we, x2_reg.port_re}; +assign core_do [23:16] = {id_type_ext_ctrl, id_type_int_ctrl, id_type_cfg, id_type_br, id_type_wr, id_type_wm, id_type_wp, pc_stack_full } ; +assign core_do [15:8] = r_x1_alu_dt[7:0] ; +assign core_do [7:0] = port_o.p_time[7:0] ; + +endmodule \ No newline at end of file diff --git a/firmware/ip/qick_processor/src/qcore_ctrl_hazard.sv b/firmware/ip/qick_processor/src/qcore_ctrl_hazard.sv new file mode 100644 index 0000000..97c851f --- /dev/null +++ b/firmware/ip/qick_processor/src/qcore_ctrl_hazard.sv @@ -0,0 +1,322 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: + +DATA HAZARD +Data hazards are caused when the execution of one instruction depends on the results of a previous instruction +that is still being processed in the pipeline. + +-DATA FORWARDING +The Data Forwaring occurs when Data from different pipeline stages should be used in the read stage (RD) of the Pipeline. + +This block compares the Source of the instruction in RD Stage with the Destination address of all the instruction in the pipeline +to see if the Data used in the current instruction is going to be written and is in the Pipeline + +-STALLING +The Stalling occurs when Data still not processed should be used in the read stage (RD) of the Pipeline. +This block compares the Source of the instruction in RD Stage with all the possible incomes of data +to see if the Data used in the current instruction is being processed. + +Possible Sources are > +-A) DSW_REG +-B) DMEM +-C) R_WAVE +-D) CORE_R_DT +-E) IN_PORT_DT +-F) STATUS +-G) time_usr +-H) s_addr +-I) Flags ( -if() ) +-J) Random Number + +*/ +////////////////////////////////////////////////////////////////////////////// + +`include "_qproc_defines.svh" + + +module qcore_ctrl_hazard ( + input wire clk_i , + input wire rst_ni , + input wire halt_i , + input wire [5:0] rs_A_addr_i [2] , + input wire [31:0] rs_A_dt_i [2] , + input wire [6:0] rs_D_addr_i [2] , + input wire [31:0] rs_D_dt_i [2] , + // Register + input CTRL_REG id_reg_i , + input CTRL_REG rd_reg_i , + input CTRL_REG x1_reg_i , + input CTRL_REG x2_reg_i , + input CTRL_REG wr_reg_i , + // Peripheral + input wire rd_periph_use , + input wire x1_periph_use , + input wire x2_periph_use , + // Wave Register + input wire id_wmem_we , + // Port Write + input wire id_type_wp , + input wire port_we , + // Flag + input wire id_flag_used , + input wire flag_we , + // JUMP + input wire id_jmp_i , + // ALU (00) Data in each Pipeline Stage + input wire [31:0] x1_alu_dt_i , + input wire [31:0] x2_alu_dt_i , + // DMEM (01) in each Pipeline Stage + input wire [31:0] x2_dmem_dt_i , + // IMM Data (11) in each Pipeline Stage + input wire [31:0] rd_imm_dt_i , + input wire [31:0] x1_imm_dt_i , + input wire [31:0] x2_imm_dt_i , + // New Data to avoid Hazard + output wire [31:0] reg_A_dt_o [2] , + output wire [31:0] reg_D_dt_o [2] , + // Bubble in RD and Wait for DATA + output wire bubble_id_o , + output wire bubble_rd_o ); + + +// DATA HAZARD + +// STALLING +reg stall_id_w ; // Give time to update R_WAVE +reg stall_id_wp ; // Give time to process PORT_WR +reg stall_id_f ; // Give time to update FLAG +reg stall_id_j ; // Give time to update S_ADDR when JUMP +reg stall_id_rand ; // Gives time to update rand number + +reg stall_rd_core_rdt ; // Gives time to update core_r_dt after Peripheral or S_CTRL +reg stall_rd_port ; // Gives time to update PORT_L & PORT_H after DPORT_RD +reg stall_rd_status ; // Gives time to update STATUS after Peripheral or S_CTRL +reg stall_rd_stime ; // Gives time to update s_out_time after TIME instruction +reg [ 1:0] w_stall_D_rd ; // Gives time to update R_WAVE when REG_WR r_wave +reg [ 1:0] d_stall_D_rd ; // Gives time to READ MEMORY +reg [ 1:0] stall_A_rd ; // Gives time to READ MEMORY + +// DATA FORWARDING +reg [ 1:0] fwd_D_X1, fwd_D_X2 ; +reg [31:0] reg_D_nxt [2] ; + +// ADDRESS FORWARDING +reg [ 1:0] fwd_A_X1, fwd_A_X2 ; +reg [31:0] reg_A_nxt [2] ; + +reg [1:0] rfrom_rand_r, rfrom_core_r, rfrom_port_r, rfrom_status_r, rfrom_stime_r; + + +assign rfrom_rand = |rfrom_rand_r ; // READ FROM CORE_R_DT(s6, s7) +assign rfrom_core_rdt = |rfrom_core_r ; // READ FROM CORE_R_DT(s6, s7) +assign rfrom_port = |rfrom_port_r ; // READ FROM IN_PORT (s8, s9)) +assign rfrom_status = |rfrom_status_r ; // READ FROM STATUS (s10) +assign rfrom_stime = |rfrom_stime_r ; // READ FROM TIME_USR (s11) +assign port_re = rd_reg_i.port_re | x1_reg_i.port_re | x2_reg_i.port_re ; //PORT READ COMMAND + +// WREG IS BEING UPDATED +assign wto_r_wave = rd_reg_i.r_wave_we | x1_reg_i.r_wave_we | x2_reg_i.r_wave_we ; +assign wto_wreg = rd_reg_i.addr[6:5] == 2'b10 | x1_reg_i.addr[6:5] == 2'b10 | x2_reg_i.addr[6:5] == 2'b10; +// PERIPHERAL IS BEING UPDATED +assign wto_qp = rd_periph_use | x1_periph_use | x2_periph_use; +// SFR CFG OR CTRL IS BEING UPDATED +assign wto_s_cfg = (rd_reg_i.addr == 7'b0000010) | (x1_reg_i.addr == 7'b0000010) | (x2_reg_i.addr == 7'b0000010) | (wr_reg_i.addr == 7'b0000010) ; +// SFR S_ADDR IS BEING UPDATED +assign wto_s_addr = (rd_reg_i.addr == 7'b00_01111) | (x1_reg_i.addr == 7'b00_01111) | (x2_reg_i.addr == 7'b00_01111) ; +// SFR S_RAND RAND IS BEING UPDATED +assign wto_s_rand = (rd_reg_i.addr == 7'b00_00001) | (x1_reg_i.addr == 7'b00_00001) | (x2_reg_i.addr == 7'b00_00001) ; + + +// (A and B) READ dreg, sreg, wreg or DMEM +/////////////////////////////////////////////////////////////////////////////// +// REG_WR after REG_WR +genvar ind_D; +generate + for (ind_D=0; ind_D <2 ; ind_D=ind_D+1) begin + // Check for read + always_comb begin + rfrom_rand_r[ind_D] = (rs_D_addr_i[ind_D][6:0] == 7'b00_00001) ; //sfr(s1) _00_000001 + rfrom_status_r[ind_D] = (rs_D_addr_i[ind_D][6:0] == 7'b00_01010) ; //sfr(s10) _00_001010 + rfrom_stime_r[ind_D] = (rs_D_addr_i[ind_D][6:0] == 7'b00_01011) ; //sfr(s11) _00_001011 + rfrom_core_r[ind_D] = (rs_D_addr_i[ind_D][6:1] == 6'b00_0011) ; //sfr _00_ Address 6 or 7 + rfrom_port_r[ind_D] = (rs_D_addr_i[ind_D][6:1] == 6'b00_0100) ; //sfr _00_ Address 8 or 9 + end + // 1- Use DataRegister after REG_WR to Register + always_comb begin + reg_D_nxt[ind_D] = rs_D_dt_i[ind_D]; + d_stall_D_rd[ind_D] = 1'b0; + fwd_D_X1[ind_D] = ( (rs_D_addr_i[ind_D] == x1_reg_i.addr ) & x1_reg_i.we ); //Data is in X1 STage + fwd_D_X2[ind_D] = ( (rs_D_addr_i[ind_D] == x2_reg_i.addr ) & x2_reg_i.we ); //Data is in X2 STage + if ( fwd_D_X1[ind_D] ) //Data is in X1 STage + unique case (x1_reg_i.src) + 2'b00 : reg_D_nxt[ind_D] = x1_alu_dt_i ; // Data Comes from ALU + 2'b01 : d_stall_D_rd[ind_D] = 1'b1 ; // Data Comes from DATA MEMORY + 2'b11 : reg_D_nxt[ind_D] = x1_imm_dt_i ; // Data Comes from Imm + endcase + else if ( fwd_D_X2[ind_D] ) //Data is in X2 STage + unique case (x2_reg_i.src) + 2'b00 : reg_D_nxt[ind_D] = x2_alu_dt_i ; // Data Comes from ALU + 2'b01 : reg_D_nxt[ind_D] = x2_dmem_dt_i ; // Data Comes from DATA MEMORY + 2'b11 : reg_D_nxt[ind_D] = x2_imm_dt_i ; // Data Comes from Imm + endcase + end // always_comb + // 2) Use WREG after REG_WR r_wave + always_comb begin + w_stall_D_rd[ind_D] = rs_D_addr_i[ind_D][6:5] == 2'b10 & (wto_r_wave) ; //WREG Read and modified + end + end //for +endgenerate + +genvar ind_A; +generate + for (ind_A=0; ind_A <2 ; ind_A=ind_A+1) begin + // 1-ADDRESS) REG_WR from AddresRegister after REG_WR to Register + always_comb begin + reg_A_nxt[ind_A] = rs_A_dt_i[ind_A]; + stall_A_rd[ind_A] = 1'b0; + fwd_A_X1[ind_A] = ( ( {1'b0,rs_A_addr_i[ind_A]} == x1_reg_i.addr ) & x1_reg_i.we ); //Address is in X1 STage + fwd_A_X2[ind_A] = ( ( {1'b0,rs_A_addr_i[ind_A]} == x2_reg_i.addr ) & x2_reg_i.we ); //Address is in X2 STage + if ( fwd_A_X1[ind_A] ) //Address is in X1 STage + unique case (x1_reg_i.src) + 2'b00 : reg_A_nxt[ind_A] = x1_alu_dt_i ; // Address Comes from ALU + 2'b01 : stall_A_rd[ind_A] = 1'b1 ; // Address Comes from DATA MEMORY + 2'b11 : reg_A_nxt[ind_A] = x1_imm_dt_i ; // Address Comes from Imm + endcase + else if ( fwd_A_X2[ind_A] ) //Address is in X2 STage + unique case (x2_reg_i.src) + 2'b00 : reg_A_nxt[ind_A] = x2_alu_dt_i ; // Address Comes from ALU + 2'b01 : reg_A_nxt[ind_A] = x2_dmem_dt_i ; // Address Comes from DATA MEMORY + 2'b11 : reg_A_nxt[ind_A] = x2_imm_dt_i ; // Address Comes from Imm + endcase + end // always_comb + end //for +endgenerate + +// (C) READ r_wave +/////////////////////////////////////////////////////////////////////////////// +// 3) WMEM_WR after REG_WR r_wave or wreg wr +always_comb begin + stall_id_w = 1'b0 ; + if ( id_wmem_we ) + if ( wto_r_wave | wto_wreg ) + stall_id_w = 1'b1 ; +end + +always_comb begin + stall_id_wp = 1'b0 ; + if ( id_type_wp ) + if ( port_we ) + stall_id_wp = 1'b1 ; +end + + + +// (D) CORE_R_DT +/////////////////////////////////////////////////////////////////////////////// +// 4) CORE_R_DT read after S_CONF Write +always_comb begin + stall_rd_core_rdt = 1'b0 ; + if (rfrom_core_rdt) + if ( wto_qp | wto_s_cfg) + stall_rd_core_rdt = 1'b1 ; +end + +// (E) IN_PORT +/////////////////////////////////////////////////////////////////////////////// +// 5) IN_PORT read after DPORT_RD +always_comb begin + stall_rd_port = 1'b0 ; + if ( rfrom_port ) + if ( port_re ) + stall_rd_port = 1'b1 ; +end + +// (F) STATUS +/////////////////////////////////////////////////////////////////////////////// +// 6) STATUS read after S_CTRL Write or Write to Peripheral +always_comb begin + stall_rd_status = 1'b0 ; + if (rfrom_status ) + if ( wto_qp | wto_s_cfg) + stall_rd_status = 1'b1 ; +end + +// (G) TIME_USR +/////////////////////////////////////////////////////////////////////////////// +// 7) TIME_USR read after Peripheral (TIME inc_ref is Peripheral) +always_comb begin + stall_rd_stime = 1'b0 ; + if ( rfrom_stime ) + if ( wto_qp ) + stall_rd_stime = 1'b1 ; +end + +// (H) S_ADDR +/////////////////////////////////////////////////////////////////////////////// +// 8) JUMP after WRITE_REG s_addr >>> STALL +always_comb begin + stall_id_j = 1'b0 ; + if (wto_s_addr ) + if (id_jmp_i ) + stall_id_j = 1'b1 ; +end + +// (I) Flag Used +/////////////////////////////////////////////////////////////////////////////// +// 9) -if() after -uf >>> STALL +// 10) -if() after s_cfg >>> STALL +// 11) -if() after FLAG set or clr + +always_comb begin + stall_id_f = 1'b0 ; + if (id_flag_used) begin // FLAG IS USED + if ( flag_we ) // a) ALU Flag is being UPDATED + stall_id_f = 1'b1 ; + else if ( wto_s_cfg ) // b) SRC Flag could be Updated or clear + stall_id_f = 1'b1 ; + else if ( wto_qp ) // c) Peripheral was used + stall_id_f = 1'b1 ; + end +end + +// (J) RAND Used +/////////////////////////////////////////////////////////////////////////////// +// 12) RAND Read after READ >>> STALL +// 13) RAND Read after WRITE >>> STALL +always_comb begin + stall_id_rand = 1'b0 ; + if (wto_s_rand | rfrom_rand ) + stall_id_rand = 1'b1 ; +end + +// OUTPUTS +/////////////////////////////////////////////////////////////////////////////// +// Data Forwarding REGISTER +reg [31:0] reg_A [2] ; +reg [31:0] reg_D [2] ; + +//Register DATA & ADDRESS OUT +always_ff @ (posedge clk_i, negedge rst_ni) + if (!rst_ni) begin + reg_A <= '{default:'0}; + reg_D <= '{default:'0}; + end else begin + if (~halt_i) begin + reg_A <= reg_A_nxt ; + reg_D <= reg_D_nxt ; + end + end + +assign reg_A_dt_o = reg_A; +assign reg_D_dt_o = reg_D; +assign bubble_id_o = stall_id_j | stall_id_f | stall_id_w | stall_id_wp | stall_id_rand; +assign bubble_rd_o = |stall_A_rd | |d_stall_D_rd | |w_stall_D_rd | stall_rd_stime | stall_rd_status | stall_rd_port | stall_rd_core_rdt ; + +endmodule \ No newline at end of file diff --git a/firmware/ip/qick_processor/src/qcore_mem.v b/firmware/ip/qick_processor/src/qcore_mem.v new file mode 100644 index 0000000..b390248 --- /dev/null +++ b/firmware/ip/qick_processor/src/qcore_mem.v @@ -0,0 +1,126 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: + +*/ +////////////////////////////////////////////////////////////////////////////// + + +module qcore_mem # ( + parameter PMEM_AW = 16 , + parameter DMEM_AW = 16 , + parameter WMEM_AW = 16 +)( + // CLK & RST. + input wire c_clk_i , + input wire c_rst_ni , + input wire ps_clk_i , + input wire ps_rst_ni , + input wire [1: 0] ps_sel_i , + input wire ps_we_i , + input wire [15: 0] ps_addr_i , + input wire [167:0] ps_w_dt_i , + output wire [167:0] ps_r_dt_o , +// PROGRAM MEMORY + input wire c_pmem_en_i , + input wire [PMEM_AW-1:0] c_pmem_addr_i , + output wire [71:0] c_pmem_r_dt_o , +// DATA MEMORY + input wire c_dmem_we_i , + input wire [DMEM_AW-1:0] c_dmem_addr_i , + input wire [31:0] c_dmem_w_dt_i , + output wire [31:0] c_dmem_r_dt_o , +// WAVE MEMORY + input wire c_wmem_we_i , + input wire [WMEM_AW-1:0] c_wmem_addr_i , + input wire [167:0] c_wmem_w_dt_i , + output wire [167:0] c_wmem_r_dt_o ); + + +wire [71 :0] ps_P_r_dt; +wire [31 :0] ps_D_r_dt; +wire [167:0] ps_W_r_dt; + +// Memory Control +wire ext_P_mem_en, ext_D_mem_en, ext_W_mem_en; +wire ext_P_mem_we, ext_D_mem_we, ext_W_mem_we; + +assign ext_P_mem_en = (ps_sel_i== 2'b01) ; +assign ext_D_mem_en = (ps_sel_i== 2'b10) ; +assign ext_W_mem_en = (ps_sel_i== 2'b11) ; + +assign ext_P_mem_we = ext_P_mem_en & ps_we_i ; +assign ext_D_mem_we = ext_D_mem_en & ps_we_i ; +assign ext_W_mem_we = ext_W_mem_en & ps_we_i ; + +assign ps_r_dt_o = (ps_sel_i == 2'b01)? { 96'd0, ps_P_r_dt } : + (ps_sel_i == 2'b10)? { 136'd0, ps_D_r_dt }: + (ps_sel_i == 2'b11)? ps_W_r_dt : + 0; + +// PROGRAM MEMORY +/////////////////////////////////////////////////////////////////////////////// +bram_dual_port_dc # ( + .MEM_AW ( PMEM_AW ), + .MEM_DW ( 72 ), + .RAM_OUT ("NO_REGISTERED" ) +) P_MEM ( + .clk_a_i ( c_clk_i ) , + .en_a_i ( c_pmem_en_i ) , + .we_a_i ( 1'b0 ) , + .addr_a_i ( c_pmem_addr_i ) , + .dt_a_i ( 72'd0 ) , + .dt_a_o ( c_pmem_r_dt_o ) , + .clk_b_i ( ps_clk_i ) , + .en_b_i ( ext_P_mem_en ) , + .we_b_i ( ext_P_mem_we ) , + .addr_b_i ( ps_addr_i[PMEM_AW-1:0] ) , + .dt_b_i ( ps_w_dt_i[71:0] ) , + .dt_b_o ( ps_P_r_dt ) ); +// DATA MEMORY +/////////////////////////////////////////////////////////////////////////////// +bram_dual_port_dc # ( + .MEM_AW ( DMEM_AW ), + .MEM_DW ( 32 ), + .RAM_OUT ("NO_REGISTERED" ) +) D_MEM ( + .clk_a_i ( c_clk_i ) , + .en_a_i ( 1'b1 ) , + .we_a_i ( c_dmem_we_i ) , + .addr_a_i ( c_dmem_addr_i ) , + .dt_a_i ( c_dmem_w_dt_i ) , + .dt_a_o ( c_dmem_r_dt_o ) , + .clk_b_i ( ps_clk_i ) , + .en_b_i ( ext_D_mem_en ) , + .we_b_i ( ext_D_mem_we ) , + .addr_b_i ( ps_addr_i[DMEM_AW-1:0] ) , + .dt_b_i ( ps_w_dt_i[31:0] ) , + .dt_b_o ( ps_D_r_dt ) ); +// WAVE MEMORY +///////////////////////////////////////////////// +bram_dual_port_dc # ( + .MEM_AW ( WMEM_AW ), + .MEM_DW ( 168 ), + .RAM_OUT ("NO_REGISTERED" ) +) W_MEM ( + .clk_a_i ( c_clk_i ) , + .en_a_i ( 1'b1 ) , + .we_a_i ( c_wmem_we_i ) , + .addr_a_i ( c_wmem_addr_i ) , + .dt_a_i ( c_wmem_w_dt_i ) , + .dt_a_o ( c_wmem_r_dt_o ) , + .clk_b_i ( ps_clk_i ) , + .en_b_i ( ext_W_mem_en ) , + .we_b_i ( ext_W_mem_we ) , + .addr_b_i ( ps_addr_i[WMEM_AW-1:0] ) , + .dt_b_i ( ps_w_dt_i ) , + .dt_b_o ( ps_W_r_dt ) ); + + +endmodule diff --git a/firmware/ip/qick_processor/src/qcore_reg_bank.sv b/firmware/ip/qick_processor/src/qcore_reg_bank.sv new file mode 100644 index 0000000..d62f15f --- /dev/null +++ b/firmware/ip/qick_processor/src/qcore_reg_bank.sv @@ -0,0 +1,251 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: + +*/ +////////////////////////////////////////////////////////////////////////////// + +`include "_qproc_defines.svh" + +module qcore_reg_bank # ( + parameter LFSR = 1 , + parameter PMEM_AW = 8 , + parameter REG_AW = 4 +)( + input wire clk_i , + input wire halt_i , + input wire rst_ni , + input wire clear_i , + input wire [1:0] lfsr_cfg_i , + input wire [31:0] reg_arith_i , + input wire [31:0] reg_div_i [2] , + input wire [31:0] reg_port_i [2] , + input wire [31:0] tproc_ext_i[2] , + input wire [31:0] time_dt_i , + input wire [167:0] wave_dt_i , + input wire [31:0] status_i , + output wire [7:0] reg_cfg_o , + output wire [7:0] reg_ctrl_o , + input wire wave_we_i , + input wire we_i , + input wire [ 6 : 0 ] w_addr_i , + input wire [31:0] w_dt_i , + input wire [ 5 : 0 ] rs_A_addr_i[2] , + input wire [ 6 : 0 ] rs_D_addr_i[2] , + output wire [31:0] rs_D_dt_o [2] , + output wire [31:0] rs_A_dt_o [2] , + output wire [31:0] sreg_dt_o [2] , + output wire [PMEM_AW-1:0] out_addr_o , + output wire [31:0] out_time_o , + output wire [167:0] out_wreg_o , + output wire [31:0] lfsr_o ); + +/* +The memory is a group of REGs (ZERO, RAND, DIV, MULT, REGBANK), and connected with a generate +Input has 8 Bits> +XX-000000 2 Page and 64 Address +00-Special Registers (32 Bits) +01-User Register (32 Bits) +10-Wave Parameter Register (32 Bits) +11-RFU +*/ + +/////////////////////////////////////////////////////////////////////////////// +// PARAMETERS +localparam REG_QTY = (2 ** (REG_AW) ) ; + + +/////////////////////////////////////////////////////////////////////////////// +// SIGNALS +//LFSR +wire [31:0] lfsr_reg; +reg lfsr_en; +wire lfsr_sel, lfsr_we, lfsr_step; + +/////////////////////////////////////////////////////////////////////////////// +// SPECIAL REGISTER BANK 00_00000 to 00_11111 +reg [31:0] sreg_dt [4]; // Four SFR +wire sreg_en, sreg_we; + +reg [7:0] sreg_cfg_dt ; // Configuration Register(Lower 16Bit of s2) +reg [7:0] sreg_ctrl_dt ; // Control Register (Upper 16Bit of s2) +wire sreg_cfg_en, sreg_cfg_we; + +assign sreg_en = w_addr_i[6:2] == 5'b00_011 ; //Register 12 to 15 selected +assign sreg_we = we_i & sreg_en ; +assign sreg_cfg_en = w_addr_i == 7'b00_00010 ; //Register 2 Selected +assign sreg_cfg_we = we_i & sreg_cfg_en; + +/////////////////////////////////////////////////////////////////////////////// +// General Data Registers 01_00000 to 01_11111 +reg [31:0] dreg_32_dt [REG_QTY]; +wire [REG_AW-1:0] dreg_32_addr ; +wire dreg_32_en, dreg_32_we; + +assign dreg_32_addr = w_addr_i[REG_AW-1:0] ; +assign dreg_32_en = w_addr_i[6:5] == 2'b01; //~w_addr_i[6] & ~w_addr_i[5] ; +assign dreg_32_we = we_i & dreg_32_en ; + +/////////////////////////////////////////////////////////////////////////////// +// Wave Registers 10_00000 to 10_0110 +reg [31:0] wreg_32_dt [6] ; +wire [ 2:0] wreg_32_addr ; +wire wreg_32_en, wreg_32_we; +assign wreg_32_addr = w_addr_i[2:0] ; +assign wreg_32_en = w_addr_i[6:5] == 2'b10; //~w_addr_i[6] & w_addr_i[5] ; +assign wreg_32_we = we_i & wreg_32_en; + + + + +/////////////////////////////////////////////////////////////////////////////// +// DATA, WAVE and SFR REGISTER BANK +always_ff @ (posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + dreg_32_dt = '{default:'0}; + wreg_32_dt = '{default:'0}; + sreg_dt = '{default:'0}; + sreg_cfg_dt = 0; + sreg_ctrl_dt = 0; + end else if (clear_i) begin + dreg_32_dt = '{default:'0}; + wreg_32_dt = '{default:'0}; + sreg_dt = '{default:'0}; + sreg_cfg_dt = 0; + sreg_ctrl_dt = 0; + end else begin + if (~halt_i) begin + if (dreg_32_we) + dreg_32_dt [dreg_32_addr] = w_dt_i; + if (wreg_32_we) + wreg_32_dt [wreg_32_addr] = w_dt_i; + else if (wave_we_i) begin + wreg_32_dt [5] = wave_dt_i[167:152]; + wreg_32_dt [4] = wave_dt_i[151:120]; + wreg_32_dt [3] = wave_dt_i[119: 88]; + wreg_32_dt [2] = wave_dt_i[ 87: 64]; + wreg_32_dt [1] = wave_dt_i[ 63: 32]; + wreg_32_dt [0] = wave_dt_i[ 31: 0]; + end + if (sreg_we) + sreg_dt [w_addr_i[1:0]] = w_dt_i; + if (sreg_cfg_we) begin + sreg_cfg_dt = w_dt_i[7:0]; + sreg_ctrl_dt = w_dt_i[23:16]; + end else if (|sreg_ctrl_dt) + sreg_ctrl_dt = 8'd0; + + // Not Used Register to GND + sreg_dt [3][31:16] = '{default:'0}; + end + end +end + +/////////////////////////////////////////////////////////////////////////////// +// LFSR +// cfg_i 00_FreeRunning 10_Change WHen Read 11_Change when writes to 0 +generate + if (LFSR == 1) begin : LFSR_YES + always_comb + unique case (lfsr_cfg_i) + 2'b00 : lfsr_en = 1'b0 ; + 2'b01 : lfsr_en = 1'b1 ; + 2'b10 : lfsr_en = lfsr_sel ; + 2'b11 : lfsr_en = lfsr_step ; + endcase + assign lfsr_sel = (rs_D_addr_i[0] == 7'b0000001) ; + assign lfsr_we = we_i & (w_addr_i == 7'b0000001) ; + assign lfsr_step = we_i & (w_addr_i == 7'b0000000) ; + LFSR lfsr ( + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .en_i ( lfsr_en ) , + .load_we_i ( lfsr_we ) , + .load_dt_i ( w_dt_i ) , + .lfsr_dt_o ( lfsr_reg ) ); + end else begin : LFSR_NO + assign lfsr_sel = 0; + assign lfsr_we = 0; + assign lfsr_step = 0; + assign lfsr_reg = 0; + end +endgenerate + +/////////////////////////////////////////////////////////////////////////////// +// SFR ASSEMBLY +wire [31:0] sreg_32_dt [16] ; + +assign sreg_32_dt[0] = 0 ; +assign sreg_32_dt[1] = lfsr_reg ; +assign sreg_32_dt[2] = sreg_cfg_dt ; +assign sreg_32_dt[3] = reg_arith_i ; +assign sreg_32_dt[4] = reg_div_i[0] ; +assign sreg_32_dt[5] = reg_div_i[1] ; +assign sreg_32_dt[6] = tproc_ext_i [0] ; +assign sreg_32_dt[7] = tproc_ext_i [1] ; +assign sreg_32_dt[8] = reg_port_i [0] ; +assign sreg_32_dt[9] = reg_port_i [1] ; +assign sreg_32_dt[10] = status_i ; +assign sreg_32_dt[11] = time_dt_i ; +assign sreg_32_dt[12] = sreg_dt [0] ; // CORE_W_DT1 +assign sreg_32_dt[13] = sreg_dt [1] ; // CORE_W_DT2 +assign sreg_32_dt[14] = sreg_dt [2] ; // OUT TIME +assign sreg_32_dt[15] = sreg_dt [3] ; // PC_NXT_ADDR_REG + + +/////////////////////////////////////////////////////////////////////////////// +// out MUX for rsA[0] and rsA[1] +wire [31:0] data_A [2]; + +genvar ind_A; +generate + for (ind_A=0; ind_A <2 ; ind_A=ind_A+1) begin + assign data_A[ind_A] = rs_A_addr_i[ind_A][5] ? dreg_32_dt[rs_A_addr_i[ind_A][REG_AW-1:0]] : sreg_32_dt[rs_A_addr_i[ind_A][3:0]] ; + end +endgenerate + +reg [31:0] data_D [2] ; + +/////////////////////////////////////////////////////////////////////////////// +// out MUX for rsD[0] and rsD[1] +genvar ind_D; +generate + for (ind_D=0; ind_D <2 ; ind_D=ind_D+1) begin + always_comb begin + case (rs_D_addr_i[ind_D][6:5]) + 2'b00 : data_D[ind_D] = sreg_32_dt[ rs_D_addr_i[ind_D][3:0] ]; // 16 Registers + 2'b01 : data_D[ind_D] = dreg_32_dt[ rs_D_addr_i[ind_D][REG_AW-1:0] ]; + 2'b10 : data_D[ind_D] = wreg_32_dt[ rs_D_addr_i[ind_D][2:0] ]; // 6 Registers + 2'b11 : data_D[ind_D] = 0 ; + endcase + end + end +endgenerate + +/////////////////////////////////////////////////////////////////////////////// +// OUTPUT ASSIGNMENT +assign rs_A_dt_o = data_A ; +assign rs_D_dt_o = data_D ; + +assign lfsr_o = lfsr_reg ; +assign reg_cfg_o = sreg_cfg_dt ; +assign reg_ctrl_o = sreg_ctrl_dt ; +assign sreg_dt_o[0] = sreg_32_dt[12] ; +assign sreg_dt_o[1] = sreg_32_dt[13] ; +assign out_time_o = sreg_32_dt[14] ; +assign out_addr_o = sreg_32_dt[15] [PMEM_AW-1:0]; + +assign out_wreg_o[167:152] = wreg_32_dt[5][15:0]; +assign out_wreg_o[151:120] = wreg_32_dt[4] ; +assign out_wreg_o[119: 88] = wreg_32_dt[3] ; +assign out_wreg_o[ 87: 64] = wreg_32_dt[2][23:0] ; +assign out_wreg_o[ 63: 32] = wreg_32_dt[1] ; +assign out_wreg_o[ 31: 0] = wreg_32_dt[0] ; + +endmodule \ No newline at end of file diff --git a/firmware/ip/qick_processor/src/qick_processor.sv b/firmware/ip/qick_processor/src/qick_processor.sv new file mode 100644 index 0000000..8886f58 --- /dev/null +++ b/firmware/ip/qick_processor/src/qick_processor.sv @@ -0,0 +1,916 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2024 +// Version : 4 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: + +*/ +////////////////////////////////////////////////////////////////////////////// + +`include "_qproc_defines.svh" + +module qick_processor # ( + parameter DEBUG = 0 , + parameter DUAL_CORE = 0 , + parameter LFSR = 0 , + parameter DIVIDER = 1 , + parameter ARITH = 1 , + parameter TIME_READ = 1 , + parameter FIFO_DEPTH = 8 , + parameter PMEM_AW = 8 , + parameter DMEM_AW = 8 , + parameter WMEM_AW = 8 , + parameter REG_AW = 4 , + parameter IN_PORT_QTY = 1 , + parameter OUT_TRIG_QTY = 1 , + parameter OUT_DPORT_QTY = 1 , + parameter OUT_DPORT_DW = 4 , + parameter OUT_WPORT_QTY = 1 +)( +// Time, Core and AXI CLK & RST. + input wire t_clk_i , + input wire t_rst_ni , + input wire c_clk_i , + input wire c_rst_ni , + input wire ps_clk_i , + input wire ps_rst_ni , +// External Control + input wire ext_flag_i , + input wire proc_start_i , + input wire proc_stop_i , + input wire core_start_i , + input wire core_stop_i , + input wire time_rst_i , + input wire time_init_i , + input wire time_updt_i , + input wire [31:0] time_updt_dt_i , + output wire [47:0] time_abs_o , +// External PERIPHERALS + output wire [31:0] periph_a_dt_o , + output wire [31:0] periph_b_dt_o , + output wire [31:0] periph_c_dt_o , + output wire [31:0] periph_d_dt_o , + output wire [4 :0] periph_op_o , +//QNET_DT + output wire qnet_en_o , + input wire qnet_rdy_i , + input wire [31:0] qnet_dt_i [2] , + input wire qnet_vld_i , + input wire qnet_flag_i , +//QCOM_DT + output wire qcom_en_o , + input wire qcom_rdy_i , + input wire [31:0] qcom_dt_i [2] , + input wire qcom_vld_i , + input wire qcom_flag_i , +// QP1 + output wire qp1_en_o , + input wire qp1_rdy_i , + input wire [31:0] qp1_dt_i [2] , + input wire qp1_vld_i , + input wire qp1_flag_i , +// QP2 + output wire qp2_en_o , + input wire qp2_rdy_i , + input wire [31:0] qp2_dt_i [2] , + input wire qp2_vld_i , + +// DMA AXIS FOR READ AND WRITE MEMORY + input wire [255:0] s_dma_axis_tdata_i , + input wire s_dma_axis_tlast_i , + input wire s_dma_axis_tvalid_i , + output wire s_dma_axis_tready_o , + output wire [255:0] m_dma_axis_tdata_o , + output wire m_dma_axis_tlast_o , + output wire m_dma_axis_tvalid_o , + input wire m_dma_axis_tready_i , +// AXI-Lite DATA Slave I/F. + TYPE_IF_AXI_REG.slave IF_s_axireg , +// DATA INPUT INTERFACE + input wire port_tvalid_i[IN_PORT_QTY ] , + input wire [63:0] port_tdata_i [IN_PORT_QTY ] , +// TRIGGERS + output wire port_trig_o [OUT_TRIG_QTY] , +// DATA OUTPUT INTERFACE + output wire port_tvalid_o[OUT_DPORT_QTY] , + output wire [OUT_DPORT_DW-1:0] port_tdata_o [OUT_DPORT_QTY] , +// AXI Stream Master I/F. + output wire [167:0] m_axis_tdata [OUT_WPORT_QTY] , + output wire m_axis_tvalid [OUT_WPORT_QTY] , + input wire m_axis_tready [OUT_WPORT_QTY] , + +// DEBUG INTERFACE + input wire [ 3:0] dport_di , + output wire [31:0] ps_debug_do , + output wire [31:0] t_debug_do , + output wire [31:0] t_fifo_do , + output wire [31:0] c_time_usr_do , + output wire [31:0] c_debug_do , + output wire [31:0] c_time_ref_do , + output wire [31:0] c_proc_do , + output wire [31:0] c_port_do , + output wire [31:0] c_core_do ); + +// SIGNALS +/////////////////////////////////////////////////////////////////////////////// +// When signal start with t_ is in t_clk Domain +// When signal start with c_ is in c_clk Domain + +// TIME +wire [47:0] time_abs ; // Absolute Time Counter Value "out_abs_time" +reg [47:0] c_time_ref_dt ; // Reference time "ref_time" +wire [31:0] c_time_usr ; // User time "current_user_time" + +// AXI REGISTERS +wire [15:0] xreg_TPROC_CTRL , xreg_TPROC_CFG ; +wire [15:0] xreg_MEM_ADDR , xreg_MEM_LEN ; +wire [31:0] xreg_MEM_DT_I , xreg_MEM_DT_O ; +reg [31:0] xreg_TPROC_STATUS, xreg_TPROC_DEBUG ; +reg [31:0] xreg_TPROC_W_DT [2]; +wire [ 7:0] xreg_CORE_CFG; +wire [ 7:0] xreg_READ_SEL ; +reg [31:0] xreg_TPROC_R_DT [2]; + +// AXIS-INPUT +reg [63:0] in_port_dt_r [ IN_PORT_QTY ] ; // Data registerd from Input Port, Register with t_valid = 1 +wire [15:0] port_dt_new ; + +// CTRL Instruction ( TIME, FLAG, ARITH, DIV, NET, CUSTOM ) +wire [31:0] core_usr_a_dt, core_usr_b_dt, core_usr_c_dt, core_usr_d_dt ; +wire [ 4:0] core_usr_operation ; // 4 bits for internal 5 bits for external + +// Control +reg t_core_rst_prev_net; // NET Request to RESET the Processor and go to previous state + +///// DUAL CORE +reg [31:0] core1_w_dt [2]; + +// Memory Operations +wire [1:0] ext_core_sel; +wire [1:0] ext_mem_sel; +wire ext_mem_we; +wire [15:0] ext_mem_addr; +wire [167:0] ext_mem_w_dt; +wire [167:0] ext_mem_r_dt, ext_mem_r_0_dt, ext_mem_r_1_dt; + +// PERIPHERALS +wire div_rdy, arith_rdy; +wire [63:0] arith_result; +wire [31:0] div_remainder, div_quotient; +wire [31:0] core0_lfsr; +wire [31:0] core1_lfsr; + +// DEBUG SIGNALS +wire [31:0] axi_mem_ds ; +wire [31:0] core_r_d0 [2], core_r_d1 [2], core_r_d2[2], core_r_d3[2] ; +wire [31:0] core_ds ; + + +/////////////////////////////////////////////////////////////////////////////// +// CONTROL Signals +/////////////////////////////////////////////////////////////////////////////// + +wire [2:0] time_st_ds, core_st_ds; +wire [6:0] ctrl_t_ds, ctrl_c_ds; +qproc_ctrl # ( + .TIME_READ ( TIME_READ ) +) QPROC_CTRL ( + .t_clk_i ( t_clk_i ), + .t_rst_ni ( t_rst_ni ), + .c_clk_i ( c_clk_i ), + .c_rst_ni ( c_rst_ni ), + .proc_start_i ( proc_start_i ), + .proc_stop_i ( proc_stop_i ), + .core_start_i ( core_start_i ), + .core_stop_i ( core_stop_i ), + .time_rst_i ( time_rst_i ), + .time_updt_i ( time_updt_i ), + .time_updt_dt_i ( time_updt_dt_i ), + .int_time_en ( int_time_pen ), + .int_time_cmd ( core_usr_operation[3:0] ), + .int_time_dt ( core_usr_b_dt ), + .PS_TPROC_CTRL ( xreg_TPROC_CTRL ), + .PS_TPROC_CFG ( xreg_TPROC_CFG[10:9]), + // .xreg_TPROC_CTRL ( xreg_TPROC_CTRL ), + // .xreg_TPROC_CFG ( xreg_TPROC_CFG ), + .xreg_TPROC_W_DT ( xreg_TPROC_W_DT[0] ), + .all_fifo_full_i ( all_fifo_full ), + .core_rst_o ( core_rst ), + .core_en_o ( core_en_s ), + .time_rst_o ( time_rst ), + .time_en_o ( time_en ), + .time_abs_o ( time_abs ), + .c_time_ref_o ( c_time_ref_dt ), + .c_time_usr_o ( c_time_usr ), + .time_st_do ( time_st_ds), + .core_st_do ( core_st_ds), + .t_debug_do ( ctrl_t_ds), + .c_debug_do ( ctrl_c_ds) +); + +assign fifo_ok = ~(some_fifo_full) | xreg_TPROC_CFG[11] ; // With 1 in TPROC_CFG[11] Continue +assign core_en = core_en_s & fifo_ok; + +/////////////////////////////////////////////////////////////////////////////// +// Processor STATUS +/////////////////////////////////////////////////////////////////////////////// +wire [ 3:0] core0_src_dt, core1_src_dt; +wire arith_clr, div_clr, qnet_clr, qcom_clr, qp1_clr, qp2_clr, port_clr ; +reg arith_rdy_r , div_rdy_r , qnet_rdy_r , qcom_rdy_r , qp1_rdy_r , qp2_rdy_r; +reg arith_dt_new, div_dt_new, qnet_dt_new, qcom_dt_new, qp1_dt_new, qp2_dt_new ; +reg [31:0] qnet_dt_r [2], qcom_dt_r [2], qp1_dt_r[2], qp2_dt_r[2] ; + +wire [7:0] core0_cfg, core1_cfg; +wire [7:0] core0_ctrl, core1_ctrl; + +assign core0_src_dt = core0_cfg[3:0]; +assign core1_src_dt = core1_cfg[3:0]; + +assign arith_clr = core0_ctrl[0] | core1_ctrl[0] ; +assign div_clr = core0_ctrl[1] | core1_ctrl[1] ; +assign qnet_clr = core0_ctrl[2] | core1_ctrl[2] ; +assign qcom_clr = core0_ctrl[3] | core1_ctrl[3] ; +assign qp1_clr = core0_ctrl[4] | core1_ctrl[4] ; +assign qp2_clr = core0_ctrl[5] | core1_ctrl[5] ; +assign port_clr = core0_ctrl[6] | core1_ctrl[6] ; + +wire [31:0] sreg_status; +assign sreg_status[0] = arith_rdy ; +assign sreg_status[1] = arith_dt_new ; +assign sreg_status[2] = div_rdy ; +assign sreg_status[3] = div_dt_new ; +assign sreg_status[4] = qnet_rdy_r ; +assign sreg_status[5] = qnet_dt_new ; +assign sreg_status[6] = qcom_rdy_r ; +assign sreg_status[7] = qcom_dt_new ; +assign sreg_status[8] = qp1_rdy_r ; +assign sreg_status[9] = qp1_dt_new ; +assign sreg_status[10] = qp2_rdy_r ; +assign sreg_status[11] = qp2_dt_new ; +assign sreg_status[12] = 1'b0 ; +assign sreg_status[13] = 1'b0 ; +assign sreg_status[14] = some_fifo_full ; +assign sreg_status[15] = |port_dt_new; +assign sreg_status[31:16] = port_dt_new ; + + + +// With rising edge of RDY detect new values +always_ff @(posedge c_clk_i) begin + if (core_rst) begin + arith_rdy_r <= 1'b1 ; + div_rdy_r <= 1'b1 ; + qnet_rdy_r <= 1'b1 ; + qcom_rdy_r <= 1'b1 ; + qp1_rdy_r <= 1'b1 ; + qp2_rdy_r <= 1'b1 ; + arith_dt_new <= 1'b0 ; + div_dt_new <= 1'b0 ; + qnet_dt_new <= 1'b0 ; + qcom_dt_new <= 1'b0 ; + qp1_dt_new <= 1'b0 ; + qp2_dt_new <= 1'b0 ; + qnet_dt_r <= '{default:'0} ; + qcom_dt_r <= '{default:'0} ; + qp1_dt_r <= '{default:'0} ; + qp2_dt_r <= '{default:'0} ; + end else begin + arith_rdy_r <= arith_rdy ; + div_rdy_r <= div_rdy ; + qnet_rdy_r <= qnet_rdy_i ; + qcom_rdy_r <= qcom_rdy_i ; + qp1_rdy_r <= qp1_rdy_i; + qp2_rdy_r <= qp2_rdy_i; + // Arith Control + if ( arith_rdy & ~arith_rdy_r ) arith_dt_new <= 1 ; + else if (~arith_rdy & arith_rdy_r ) arith_dt_new <= 0 ; + else if ( arith_clr ) arith_dt_new <= 0 ; + // DIV Control + if ( div_rdy & ~div_rdy_r ) div_dt_new <= 1 ; + else if (~div_rdy & div_rdy_r ) div_dt_new <= 0 ; + else if ( div_clr ) div_dt_new <= 0 ; + // QNET Control + if ( qnet_vld_i ) begin + qnet_dt_new <= 1 ; + qnet_dt_r <= qnet_dt_i ; + end else if ( qnet_clr ) qnet_dt_new <= 0 ; + // QCOM Control + if ( qcom_vld_i ) begin + qcom_dt_new <= 1 ; + qcom_dt_r <= qcom_dt_i ; + end else if ( qcom_clr ) qcom_dt_new <= 0 ; + // Q-PERIPHERAL 1 Control + if ( qp1_vld_i ) begin + qp1_dt_new <= 1 ; + qp1_dt_r <= qp1_dt_i ; + end else if ( qp1_clr ) qp1_dt_new <= 0 ; + // Q-PERIPHERAL 2 Control + if ( qp2_vld_i ) begin + qp2_dt_new <= 1 ; + qp2_dt_r <= qp2_dt_i ; + end else if ( qp1_clr ) qp2_dt_new <= 0 ; + + end +end + + +/////////////////////////////////////////////////////////////////////////////// +// FLAG +/////////////////////////////////////////////////////////////////////////////// + +// EXTERNAL Flag +/////////////////////////////////////////////////////////////////////////////// +sync_reg # (.DW ( 1 ) ) sync_flag_ext_c ( + .dt_i ( ext_flag_i ) , + .clk_i ( c_clk_i ) , + .rst_ni ( c_rst_ni ) , + .dt_o ( ext_flag_r ) ); + + +// INTERNAL Flag +/////////////////////////////////////////////////////////////////////////////// + +assign axi_flag_set = xreg_TPROC_CTRL[13] ; +assign axi_flag_clr = xreg_TPROC_CTRL[14] ; +assign int_flag_set = (int_flag_pen & core_usr_operation[0]); +assign int_flag_clr = (int_flag_pen & core_usr_operation[1]); +assign int_flag_inv = (int_flag_pen & core_usr_operation[2]); + +reg axi_flag_r, int_flag_r ; +always_ff @(posedge c_clk_i) begin + if (core_rst) begin + axi_flag_r <= 0; + int_flag_r <= 0; + end else begin + if ( axi_flag_set ) axi_flag_r <= 1 ; // SET EXTERNAL FLAG + else if ( axi_flag_clr ) axi_flag_r <= 0 ; // CLEAR EXTERNAL FLAG + if ( int_flag_set ) int_flag_r <= 1 ; // SET INTERNAL FLAG + else if ( int_flag_clr ) int_flag_r <= 0 ; // CLEAR INTERNAL FLAG + else if ( int_flag_inv ) int_flag_r <= ~int_flag_r ; // Flip INTERNAL FLAG + end +end + + +/////////////////////////////////////////////////////////////////////////////// +// INSTANCES +/////////////////////////////////////////////////////////////////////////////// + +// IN PORT DATA REGISTER +/////////////////////////////////////////////////////////////////////////////// +qproc_inport_reg # ( + .PORT_QTY (IN_PORT_QTY) +) IN_PORT_REG ( + .c_clk_i ( c_clk_i ) , + .c_rst_ni ( c_rst_ni ) , + .c_clear ( port_clr ) , + .port_tvalid_i ( port_tvalid_i ) , + .port_tdata_i ( port_tdata_i ) , + .port_tnew_o ( port_dt_new ) , + .port_tdata_o ( in_port_dt_r ) ); + +// MEM CONTROL +/////////////////////////////////////////////////////////////////////////////// +assign ext_mem_r_dt = ext_mem_r_0_dt ; // From Core0 + +qproc_mem_ctrl # ( + .PMEM_AW ( PMEM_AW ), + .DMEM_AW ( DMEM_AW ), + .WMEM_AW ( WMEM_AW ) +) QMEM_CTRL ( + .ps_clk_i ( ps_clk_i ) , + .ps_rst_ni ( ps_rst_ni ) , + .ext_core_sel_o ( ext_core_sel ) , + .ext_mem_sel_o ( ext_mem_sel ) , + .ext_mem_we_o ( ext_mem_we ) , + .ext_mem_addr_o ( ext_mem_addr ) , + .ext_mem_w_dt_o ( ext_mem_w_dt ) , + .ext_mem_r_dt_i ( ext_mem_r_dt ) , + .s_axis_tdata_i ( s_dma_axis_tdata_i ) , + .s_axis_tlast_i ( s_dma_axis_tlast_i ) , + .s_axis_tvalid_i ( s_dma_axis_tvalid_i ) , + .s_axis_tready_o ( s_dma_axis_tready_o ) , + .m_axis_tdata_o ( m_dma_axis_tdata_o ) , + .m_axis_tlast_o ( m_dma_axis_tlast_o ) , + .m_axis_tvalid_o ( m_dma_axis_tvalid_o ) , + .m_axis_tready_i ( m_dma_axis_tready_i ) , + .MEM_CTRL ( xreg_TPROC_CFG[6:0] ) , + .MEM_ADDR ( xreg_MEM_ADDR ) , + .MEM_LEN ( xreg_MEM_LEN ) , + .MEM_DT_I ( xreg_MEM_DT_I ) , + .MEM_DT_O ( xreg_MEM_DT_O ) , + .DEBUG_O ( axi_mem_ds) ); + + +// AXI REGISTERS +/////////////////////////////////////////////////////////////////////////////// +qproc_axi_reg QPROC_xREG ( + .ps_aclk ( ps_clk_i ) , + .ps_aresetn ( ps_rst_ni ) , + .IF_s_axireg ( IF_s_axireg ) , + .TPROC_CTRL ( xreg_TPROC_CTRL ) , + .TPROC_CFG ( xreg_TPROC_CFG ) , + .MEM_ADDR ( xreg_MEM_ADDR ) , + .MEM_LEN ( xreg_MEM_LEN ) , + .MEM_DT_I ( xreg_MEM_DT_I ) , + .TPROC_W_DT1 ( xreg_TPROC_W_DT [0] ) , + .TPROC_W_DT2 ( xreg_TPROC_W_DT [1] ) , + .CORE_CFG ( xreg_CORE_CFG ) , + .READ_SEL ( xreg_READ_SEL ) , + .MEM_DT_O ( xreg_MEM_DT_O ) , + .TPROC_R_DT1 ( xreg_TPROC_R_DT[0] ) , + .TPROC_R_DT2 ( xreg_TPROC_R_DT[1] ) , + .TIME_USR ( c_time_usr ) , + .TPROC_STATUS ( xreg_TPROC_STATUS ) , + .TPROC_DEBUG ( xreg_TPROC_DEBUG ) ); + +// AXI_REG TPROC_R_DT source selection +/////////////////////////////////////////////////////////////////////////////// +wire [ 3:0] tproc_src_dt; +assign tproc_src_dt = xreg_READ_SEL[3:0]; + +always_ff @ (posedge ps_clk_i, negedge ps_rst_ni) begin + if (!ps_rst_ni) begin + xreg_TPROC_R_DT <= '{default:'0} ; + end else begin + case (tproc_src_dt) + 4'd0 : xreg_TPROC_R_DT = xreg_TPROC_W_DT ; + 4'd1 : xreg_TPROC_R_DT = core0_w_dt ; + 4'd2 : xreg_TPROC_R_DT = core1_w_dt ; + 4'd3 : xreg_TPROC_R_DT = {div_quotient ,div_remainder }; + 4'd4 : xreg_TPROC_R_DT = '{arith_result[31:0], arith_result[63:32]}; + 4'd5 : xreg_TPROC_R_DT = qnet_dt_r ; + 4'd6 : xreg_TPROC_R_DT = qcom_dt_r; + 4'd7 : xreg_TPROC_R_DT = qp1_dt_r; + 4'd8 : xreg_TPROC_R_DT = qp2_dt_r; + 4'd9 : xreg_TPROC_R_DT = '{in_port_dt_r[0][31:0], in_port_dt_r[0][63:32]}; + 4'd10: xreg_TPROC_R_DT = '{core0_lfsr, core1_lfsr}; + default: xreg_TPROC_R_DT = '{default:'0} ; + endcase + end +end + + + +/////////////////////////////////////////////////////////////////////////////// +// PERIPHERALS +/////////////////////////////////////////////////////////////////////////////// + +wire [7:0] usr_ctrl_s; +// Internal Peripherals Enable (MSB=0 - 8 possible Peripherals) +assign int_time_pen = usr_en & (usr_ctrl_s[7:4] == 4'b0000 ); +assign int_flag_pen = usr_en & (usr_ctrl_s[7:4] == 4'b0001 ); +assign int_arith_pen = usr_en & (usr_ctrl_s[7:4] == 4'b0010 ); +assign int_div_pen = usr_en & (usr_ctrl_s[7:4] == 4'b0011 ); +//assign int_A_pen = usr_en & (usr_ctrl_s[7:4] == 4'b0100 ); +//assign int_B_pen = usr_en & (usr_ctrl_s[7:4] == 4'b0101 ); +//assign int_C_pen = usr_en & (usr_ctrl_s[7:4] == 4'b0110 ); +//assign int_D_pen = usr_en & (usr_ctrl_s[7:4] == 4'b0111 ); + +// External Peripherals Enable (MSB=1 - 4 possible Peripherals) +assign ext_net_pen = usr_en & (usr_ctrl_s[7:5] == 3'b100 ); +assign ext_com_pen = usr_en & (usr_ctrl_s[7:5] == 3'b101 ); +assign ext_p1_pen = usr_en & (usr_ctrl_s[7:5] == 3'b110 ); +assign ext_p2_pen = usr_en & (usr_ctrl_s[7:5] == 3'b111 ); + +assign core_usr_operation = usr_ctrl_s[4:0]; + +// DIVIDER +/////////////////////////////////////////////////////////////////////////////// +generate + if (DIVIDER == 1) begin : QPER_DIV + wire [31:0] div_remainder_s, div_quotient_s; + reg [31:0] div_remainder_r, div_quotient_r; + div_r #( + .DW ( 32 ) + ) DIV ( + .clk_i ( c_clk_i ) , + .rst_ni ( c_rst_ni ) , + .start_i ( int_div_pen ) , + .A_i ( core_usr_d_dt ) , + .B_i ( core_usr_b_dt ) , + .ready_o ( div_rdy ) , + .div_remainder_o ( div_remainder_s ) , + .div_quotient_o ( div_quotient_s ) ); + + always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) begin + div_remainder_r <= 0 ; + div_quotient_r <= 0 ; + end else begin + div_remainder_r <= div_remainder_s ; + div_quotient_r <= div_quotient_s ; + end + end + assign div_remainder = div_remainder_r; + assign div_quotient = div_quotient_r; + end else begin : DIVIDER_NO + assign div_rdy = 0; + assign div_remainder = 0; + assign div_quotient = 0; + end +endgenerate + +// ARITH +/////////////////////////////////////////////////////////////////////////////// +generate + if (ARITH == 1) begin : QPER_ARITH + arith ARITH ( + .clk_i ( c_clk_i ) , + .rst_ni ( c_rst_ni ) , + .start_i ( int_arith_pen ) , + .A_i ( core_usr_a_dt ) , + .B_i ( core_usr_b_dt ) , + .C_i ( core_usr_c_dt ) , + .D_i ( core_usr_d_dt ) , + .alu_op_i ( core_usr_operation[3:0] ) , + .ready_o ( arith_rdy ) , + .arith_result_o ( arith_result ) ); + end else begin : ARITH_NO + assign arith_rdy = 0; + assign arith_result = 0; + end +endgenerate + + + + +/////////////////////////////////////////////////////////////////////////////// +// T PROCESSOR CORE +wire [1:0] core0_lfsr_cfg; +assign core0_lfsr_cfg = xreg_CORE_CFG[1:0]; + +// Core0 FLAG source selection +/////////////////////////////////////////////////////////////////////////////// +wire [3:0] core0_src_flg; +assign core0_src_flg = core0_cfg[7:4]; +reg flag_c0; +always_comb begin + case (core0_src_flg) + 4'b000 : flag_c0 = int_flag_r ; + 4'b001 : flag_c0 = axi_flag_r ; + 4'b010 : flag_c0 = ext_flag_r ; + 4'b011 : flag_c0 = div_dt_new | arith_dt_new ; + 4'b100 : flag_c0 = |port_dt_new ; + 4'b101 : flag_c0 = qnet_flag_i; + 4'b110 : flag_c0 = qcom_flag_i ; + 4'b111 : flag_c0 = qp1_flag_i ; + default: flag_c0 = 0 ; + endcase +end + +// Core0 CORE_R_DT sreg(s7) source selection +/////////////////////////////////////////////////////////////////////////////// +reg [31:0] core0_r_dt [2], core0_w_dt [2]; +always_comb begin + case (core0_src_dt) + 4'b0000 : core0_r_dt = xreg_TPROC_W_DT ; + 4'b0001 : core0_r_dt = '{arith_result[31:0], arith_result[63:32]} ; + 4'b0010 : core0_r_dt = qnet_dt_r ; + 4'b0011 : core0_r_dt = qcom_dt_r; + 4'b0100 : core0_r_dt = qp1_dt_r; + 4'b0101 : core0_r_dt = qp2_dt_r; + 4'b0110 : core0_r_dt = core1_w_dt; + 4'b0111 : core0_r_dt = '{in_port_dt_r[0][31:0], in_port_dt_r[0][63:32]}; + //DEBUG + 4'b1000: core0_r_dt = core_r_d0; + 4'b1001: core0_r_dt = core_r_d1; + 4'b1010: core0_r_dt = core_r_d2; + 4'b1011: core0_r_dt = core_r_d3; + default: core0_r_dt = xreg_TPROC_W_DT ; + endcase +end + +PORT_DT out_port_data ; // Port Data from the CORE + +qproc_core # ( + .LFSR ( LFSR ), + .IN_PORT_QTY ( IN_PORT_QTY ), + .PMEM_AW ( PMEM_AW ), + .DMEM_AW ( DMEM_AW ), + .WMEM_AW ( WMEM_AW ), + .REG_AW ( REG_AW ) +) CORE_0 ( + .c_clk_i ( c_clk_i ) , + .c_rst_ni ( c_rst_ni ) , + .ps_clk_i ( ps_clk_i ) , + .ps_rst_ni ( ps_rst_ni ) , + .en_i ( core_en ) , + .restart_i ( core_rst ) , +// CORE CTRL + .lfsr_cfg_i ( core0_lfsr_cfg ) , + .core_status_o ( ) , + .core_debug_o ( ) , + .lfsr_o ( core0_lfsr ) , + .port_dt_i ( in_port_dt_r ) , //ALL The port Values + .flag_i ( flag_c0 ) , + .sreg_cfg_o ( core0_cfg ) , + .sreg_ctrl_o ( core0_ctrl ) , + .sreg_arith_i ( arith_result[31:0] ) , + .sreg_div_i ( {div_quotient ,div_remainder } ) , + .sreg_status_i ( sreg_status ) , + .sreg_core_r_dt_i ( core0_r_dt ) , + .sreg_time_dt_i ( c_time_usr ) , + .sreg_core_w_dt_o ( core0_w_dt ) , + .usr_en_o ( usr_en ) , + .usr_ctrl_o ( usr_ctrl_s ) , + .usr_dt_a_o ( core_usr_a_dt ) , + .usr_dt_b_o ( core_usr_b_dt ) , + .usr_dt_c_o ( core_usr_c_dt ) , + .usr_dt_d_o ( core_usr_d_dt ) , + .ps_mem_sel_i ( ext_mem_sel ) , + .ps_mem_we_i ( ext_mem_we ) , + .ps_mem_addr_i ( ext_mem_addr ) , + .ps_mem_w_dt_i ( ext_mem_w_dt ) , + .ps_mem_r_dt_o ( ext_mem_r_0_dt ) , + .port_we_o ( port_we ) , + .port_o ( out_port_data ) , + .core_do ( core_ds ) ); + + + +/////////////////////////////////////////////////////////////////////////////// +///// DUAL CORE +wire [1 :0] core1_lfsr_cfg; +assign core1_lfsr_cfg = xreg_CORE_CFG[3:2]; + +generate + if ( DUAL_CORE == 1) begin : DUAL_CORE_YES + reg [31:0] core1_r_dt [2]; + always_comb begin + case (core1_src_dt) + 4'b0000 : core1_r_dt = xreg_TPROC_W_DT ; + 4'b0001 : core1_r_dt = '{arith_result[31:0], arith_result[63:32]} ; + 4'b0010 : core1_r_dt = qnet_dt_r ; + 4'b0011 : core1_r_dt = qcom_dt_r; + 4'b0100 : core1_r_dt = qp1_dt_r; + 4'b0101 : core1_r_dt = qp2_dt_r; + 4'b0110 : core1_r_dt = core1_w_dt; + 4'b0111 : core1_r_dt = '{in_port_dt_r[0][31:0], in_port_dt_r[0][63:32]}; + default : core1_r_dt = '{default:'0} ; + endcase + end + qproc_core # ( + .LFSR ( LFSR ), + .IN_PORT_QTY ( IN_PORT_QTY ), + .PMEM_AW ( PMEM_AW ), + .DMEM_AW ( DMEM_AW ), + .WMEM_AW ( WMEM_AW ), + .REG_AW ( REG_AW ) + ) CORE_1 ( + .c_clk_i ( c_clk_i ) , + .c_rst_ni ( c_rst_ni ) , + .ps_clk_i ( ps_clk_i ) , + .ps_rst_ni ( ps_rst_ni ) , + .en_i ( core_en ) , + .restart_i ( core_rst ) , + .port_dt_i ( in_port_dt_r ) , + .sreg_arith_i ( {arith_result[31:0],arith_result[63:32]} ) , + .sreg_div_i ( {div_quotient ,div_remainder } ) , + .sreg_status_i ( sreg_status ) , + .sreg_core_r_dt_i ( core1_r_dt ) , + .sreg_core_w_dt_o ( core1_w_dt ) , + .sreg_time_dt_i ( c_time_usr ) , + .sreg_cfg_o ( core1_cfg ) , + .usr_dt_a_o ( ) , + .usr_dt_b_o ( ) , + .usr_dt_c_o ( ) , + .usr_dt_d_o ( ) , + .usr_ctrl_o ( ) , + .ps_mem_sel_i ( ) , + .ps_mem_we_i ( ) , + .ps_mem_addr_i ( ) , + .ps_mem_w_dt_i ( ) , + .ps_mem_r_dt_o ( ) , + .port_we_o ( ) , + .port_o ( ) , + .core_do ( ) ); + end else begin : DUAL_CORE_NO + assign core1_lfsr = '{default:'0} ; + assign core1_w_dt = '{default:'0} ; + assign core1_cfg = '{default:'0} ; + assign core1_ctrl = '{default:'0} ; + assign ext_mem_r_1_dt = '{default:'0} ; + end +endgenerate + + + + + +wire [31:0] fifo_dt_ds, axi_fifo_ds; +wire [15:0] c_fifo_ds, t_fifo_ds ; + +qproc_dispatcher # ( + .FIFO_DEPTH ( FIFO_DEPTH ), + .IN_PORT_QTY ( IN_PORT_QTY ), + .OUT_TRIG_QTY ( OUT_TRIG_QTY ), + .OUT_DPORT_QTY ( OUT_DPORT_QTY ), + .OUT_DPORT_DW ( OUT_DPORT_DW ), + .OUT_WPORT_QTY ( OUT_WPORT_QTY ) +) DISPATCHER ( + .c_clk_i ( c_clk_i ) , + .c_rst_ni ( c_rst_ni ) , + .t_clk_i ( t_clk_i ) , + .t_rst_ni ( t_rst_ni ) , + //Port + .core_en ( core_en ) , + .core_rst ( core_rst ) , + .time_en ( time_en ) , + .time_rst ( time_rst ) , + .c_time_ref_dt ( c_time_ref_dt ) , + .time_abs_i ( time_abs ) , + .all_fifo_full ( all_fifo_full ) , + .some_fifo_full ( some_fifo_full ), + .port_we ( port_we ) , + .out_port_data ( out_port_data ) , + // TRIGGERS + .port_trig_o ( port_trig_o ) , + // DATA OUTPUT INTERFACE + .port_tvalid_o ( port_tvalid_o ) , + .port_tdata_o ( port_tdata_o ) , + // WAVE OUTPUT INTERFACE + .m_axis_tdata ( m_axis_tdata ) , + .m_axis_tvalid ( m_axis_tvalid ) , + .m_axis_tready ( m_axis_tready ) , + // DEBUG outputs + .fifo_dt_do ( fifo_dt_ds ) , + .axi_fifo_do ( axi_fifo_ds ) , + .c_fifo_do ( c_fifo_ds ) , + .t_fifo_do ( t_fifo_ds ) +); + + +/////////////////////////////////////////////////////////////////////////////// +// OUTPUTS +/////////////////////////////////////////////////////////////////////////////// + + + + + + + + +/////////////////////////////////////////////////////////////////////////////// +// NO REGISTERED OUTPUT + + +/////////////////////////////////////////////////////////////////////////////// +// OUT PERIPHERLAS (QNET, QCOM, P1 and P2) +assign qnet_en_o = ext_net_pen ; +assign qcom_en_o = ext_com_pen ; +assign qp1_en_o = ext_p1_pen ; +assign qp2_en_o = ext_p2_pen ; + +assign periph_a_dt_o = core_usr_a_dt; +assign periph_b_dt_o = core_usr_b_dt; +assign periph_c_dt_o = core_usr_c_dt; +assign periph_d_dt_o = core_usr_d_dt; +assign periph_op_o = core_usr_operation; + + +/////////////////////////////////////////////////////////////////////////////// +///// External Control +assign time_abs_o = time_abs ; + + + + +/////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////// +// DEBUG +/////////////////////////////////////////////////////////////////////////////// + + + +//wire [ 3:0] c_fifo_data_dt; +//wire [31:0] c_fifo_data_time; + + +localparam DEBUG_AXI = (DEBUG > 0) ? 1 : 0; +localparam DEBUG_REG = (DEBUG > 1) ? 1 : 0; +localparam DEBUG_OUT = (DEBUG > 2) ? 1 : 0; + + +generate + +///// DEBUG AXI_REG +/////////////////////////////////////////////////////////////////////////////// + if (DEBUG_AXI == 1) begin : AXI_DB + wire [31:0] axi_status_ds, axi_port_ds; + + assign axi_status_ds[31:26] = { qp2_rdy_r , qp1_rdy_r , qcom_rdy_r , qnet_rdy_r, arith_rdy_r, div_rdy_r }; + assign axi_status_ds[25:20] = { qp2_dt_new, qp1_dt_new, qcom_dt_new, qnet_dt_new, div_dt_new, |port_dt_new }; + assign axi_status_ds[19:16] = { flag_c0, qp1_flag_i, qcom_flag_i, qnet_flag_i }; + assign axi_status_ds[15:13] = { ext_flag_r, axi_flag_r, int_flag_r }; + assign axi_status_ds[12: 8] = { core0_src_flg[2:0], core0_src_dt[1:0]}; + assign axi_status_ds[ 7: 4] = { time_en , time_st_ds[2:0] }; + assign axi_status_ds[ 3: 0] = { core_en , core_st_ds[2:0]}; + + assign axi_port_ds[31:28] = dport_di; + assign axi_port_ds[27] = port_trig_o[0] ; + assign axi_port_ds[26:24] = port_dt_new[2:0] ; + assign axi_port_ds[23: 0] = in_port_dt_r[0][23:0] ; + + always_ff @ (posedge ps_clk_i, negedge ps_rst_ni) begin + if (!ps_rst_ni) begin + xreg_TPROC_STATUS <= '{default:'0} ; + xreg_TPROC_DEBUG <= '{default:'0} ; + end else begin + xreg_TPROC_STATUS <= axi_status_ds; + case (tproc_src_dt[1:0]) + 4'd0 : xreg_TPROC_DEBUG <= axi_fifo_ds ; + 4'd1 : xreg_TPROC_DEBUG <= axi_mem_ds ; + 4'd2 : xreg_TPROC_DEBUG <= c_time_ref_dt ; + 4'd3 : xreg_TPROC_DEBUG <= axi_port_ds ; + endcase + end + end + end else begin + // NO DEBUG AXI_REG + assign xreg_TPROC_STATUS = 0 ; + assign xreg_TPROC_DEBUG = 0 ; + end + +///// DEBUG CORE_R_DT +/////////////////////////////////////////////////////////////////////////////// + if (DEBUG_REG == 1) begin : REG_DB + assign core_r_d0 = core0_w_dt ; + assign core_r_d1 = '{ in_port_dt_r[0], {15'd0, port_trig_o[0], 12'd0,dport_di} } ; + assign core_r_d2 = '{c_time_ref_dt[31:0], 32'd0} ; + end else begin + // NO DEBUG CORE_R_DT + assign core_r_d0 = '{default:'0} ; + assign core_r_d1 = '{default:'0} ; + assign core_r_d2 = '{default:'0} ; + assign core_r_d3 = '{default:'0} ; + end + + +///// DEBUG OUT SIGNALS +/////////////////////////////////////////////////////////////////////////////// + if (DEBUG_OUT == 1) begin : OUT_DB + ///// PS_CLOCK Debug Signals + assign ps_debug_do[31:28] = {IF_s_axireg.axi_arready, IF_s_axireg.axi_rready, IF_s_axireg.axi_awready, IF_s_axireg.axi_wready}; + assign ps_debug_do[27:24] = {IF_s_axireg.axi_arvalid, IF_s_axireg.axi_rvalid, IF_s_axireg.axi_awvalid, IF_s_axireg.axi_wvalid}; + assign ps_debug_do[23:12] = {IF_s_axireg.axi_araddr[5:0], IF_s_axireg.axi_awaddr[5:0]}; + assign ps_debug_do[11 :0] = {IF_s_axireg.axi_rdata[5:0], IF_s_axireg.axi_wdata[5:0]}; + + ///// T_CLOCK Debug Signals + assign t_debug_do[31:16] = t_fifo_ds; + assign t_debug_do[15:12] = 4'd0; + assign t_debug_do[11:10] = { time_rst, time_en }; + assign t_debug_do[ 9: 3] = ctrl_t_ds; + assign t_debug_do[ 2: 0] = { time_st_ds[2:0] }; + + assign t_fifo_do = fifo_dt_ds ; + + ///// C_CLOCK Debug Signals + assign c_time_usr_do = c_time_usr ; + + assign c_debug_do[31:16] = c_fifo_ds; + assign c_debug_do[15:14] = { some_fifo_full, all_fifo_full } ; + assign c_debug_do[13:12] = { 2'd0 } ; + assign c_debug_do[11:10] = { core_rst, core_en } ; + assign c_debug_do[ 9: 3] = ctrl_c_ds; + assign c_debug_do[ 2: 0] = { core_st_ds[2:0] }; + + assign c_time_ref_do = c_time_ref_dt ; + + assign c_port_do[31:28] = out_port_data.p_addr[3:0] ; + assign c_port_do[27:16] = out_port_data.p_data[11:0]; + assign c_port_do[15: 0] = out_port_data.p_time[15:0]; + + assign c_proc_do[31:30] = { flag_c0, |port_dt_new } ; + assign c_proc_do[29:18] = sreg_status[11:0]; + assign c_proc_do[17:11] = core0_ctrl[6:0] ; + assign c_proc_do[10: 8] = core0_src_dt[2:0] ; + assign c_proc_do[ 7: 2] = { int_flag_r, axi_flag_r, int_flag_clr, int_flag_set, axi_flag_clr, axi_flag_set } ; + assign c_proc_do[ 1: 0] = { time_ref_inc, time_ref_set } ; + + assign c_core_do = core_ds ; + + assign time_ref_set = ( int_time_pen & core_usr_operation[2]) ; + assign time_ref_inc = ( int_time_pen & core_usr_operation[3]) ; + + end else begin + // DEBUG OUT + assign ps_debug_do = 0 ; + assign t_debug_do = 0 ; + assign t_fifo_do = 0 ; + assign c_time_usr_do = 0 ; + assign c_debug_do = 0 ; + assign c_time_ref_do = 0 ; + assign c_port_do = 0 ; + assign c_proc_do = 0 ; + assign c_core_do = 0 ; + end +endgenerate + + +endmodule + diff --git a/firmware/ip/qick_processor/src/qick_processor_ooc.xdc b/firmware/ip/qick_processor/src/qick_processor_ooc.xdc new file mode 100644 index 0000000..e9b099b --- /dev/null +++ b/firmware/ip/qick_processor/src/qick_processor_ooc.xdc @@ -0,0 +1,5 @@ +create_clock -period 10.000 -name ps_clk_i -waveform {0.000 5.000} [get_ports ps_clk_i] +create_clock -period 1.620 -name t_clk_i -waveform {0.000 0.810} [get_ports t_clk_i] +create_clock -period 5.000 -name c_clk_i -waveform {0.000 2.500} [get_ports c_clk_i] +set_clock_groups -asynchronous -group [get_clocks c_clk_i] -group [get_clocks t_clk_i] -group [get_clocks ps_clk_i] + diff --git a/firmware/ip/qick_processor/src/qproc_axi_reg.sv b/firmware/ip/qick_processor/src/qproc_axi_reg.sv new file mode 100644 index 0000000..e6136a1 --- /dev/null +++ b/firmware/ip/qick_processor/src/qproc_axi_reg.sv @@ -0,0 +1,93 @@ +`include "_qproc_defines.svh" + +// TPROC REG +///////////////////////////////////////////////// +module qproc_axi_reg( + input wire ps_aclk , + input wire ps_aresetn , + TYPE_IF_AXI_REG.slave IF_s_axireg , + output logic [15:0] TPROC_CTRL , + output logic [15:0] TPROC_CFG , + output logic [15:0] MEM_ADDR , + output logic [15:0] MEM_LEN , + output logic [31:0] MEM_DT_I , + output logic [31:0] TPROC_W_DT1 , + output logic [31:0] TPROC_W_DT2 , + output logic [7:0] CORE_CFG , + output logic [7:0] READ_SEL , + input wire [31:0] MEM_DT_O , + input wire [31:0] TPROC_R_DT1 , + input wire [31:0] TPROC_R_DT2 , + input wire [31:0] TIME_USR , + input wire [31:0] TPROC_STATUS , + input wire [31:0] TPROC_DEBUG +); + + +// wire [15:0] PS_TPROC_CTRL, PS_TPROC_CFG; + +// AXI Slave. +axi_slv_qproc QPROC_xREG ( + .aclk ( ps_aclk ) , + .aresetn ( ps_aresetn ) , + .awaddr ( IF_s_axireg.axi_awaddr [5:0] ) , + .awprot ( IF_s_axireg.axi_awprot ) , + .awvalid ( IF_s_axireg.axi_awvalid ) , + .awready ( IF_s_axireg.axi_awready ) , + .wdata ( IF_s_axireg.axi_wdata ) , + .wstrb ( IF_s_axireg.axi_wstrb ) , + .wvalid ( IF_s_axireg.axi_wvalid ) , + .wready ( IF_s_axireg.axi_wready ) , + .bresp ( IF_s_axireg.axi_bresp ) , + .bvalid ( IF_s_axireg.axi_bvalid ) , + .bready ( IF_s_axireg.axi_bready ) , + .araddr ( IF_s_axireg.axi_araddr ) , + .arprot ( IF_s_axireg.axi_arprot ) , + .arvalid ( IF_s_axireg.axi_arvalid ) , + .arready ( IF_s_axireg.axi_arready ) , + .rdata ( IF_s_axireg.axi_rdata ) , + .rresp ( IF_s_axireg.axi_rresp ) , + .rvalid ( IF_s_axireg.axi_rvalid ) , + .rready ( IF_s_axireg.axi_rready ) , + .TPROC_CTRL ( TPROC_CTRL ) , + .TPROC_CFG ( TPROC_CFG ) , + .MEM_ADDR ( MEM_ADDR ) , + .MEM_LEN ( MEM_LEN ) , + .MEM_DT_I ( MEM_DT_I ) , + .TPROC_W_DT1 ( TPROC_W_DT1 ) , + .TPROC_W_DT2 ( TPROC_W_DT2 ) , + .CORE_CFG ( CORE_CFG ) , + .READ_SEL ( READ_SEL ) , + .MEM_DT_O ( MEM_DT_O ) , + .TPROC_R_DT1 ( TPROC_R_DT1 ) , + .TPROC_R_DT2 ( TPROC_R_DT2 ) , + .TIME_USR ( TIME_USR ) , + .TPROC_STATUS ( TPROC_STATUS ) , + .TPROC_DEBUG ( TPROC_DEBUG ) ); + +//------------------------------------------------------- +// Moved to qproc_ctrl due to issue #33 + +// reg [15:0] tproc_ctrl_rcd, tproc_ctrl_r, tproc_ctrl_2r; +// reg [15:0] tproc_cfg_rcd; + +// // From PS_CLK to C_CLK +// always_ff @(posedge c_clk_i) +// if (!c_rst_ni) begin +// tproc_ctrl_rcd <= 0 ; +// tproc_ctrl_r <= 0 ; +// tproc_ctrl_2r <= 0 ; +// tproc_cfg_rcd <= 0 ; +// end else begin +// tproc_ctrl_rcd <= PS_TPROC_CTRL ; +// tproc_ctrl_r <= tproc_ctrl_rcd ; +// tproc_ctrl_2r <= tproc_ctrl_r ; +// tproc_cfg_rcd <= PS_TPROC_CFG ; +// TPROC_CFG <= tproc_cfg_rcd ; +// end + +// // The C_TPROC_CTRL is only ONE clock. +// assign TPROC_CTRL = tproc_ctrl_r & ~tproc_ctrl_2r ; +//------------------------------------------------------- + +endmodule diff --git a/firmware/ip/qick_processor/src/qproc_core.sv b/firmware/ip/qick_processor/src/qproc_core.sv new file mode 100644 index 0000000..8a19cf2 --- /dev/null +++ b/firmware/ip/qick_processor/src/qproc_core.sv @@ -0,0 +1,169 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: + +*/ +////////////////////////////////////////////////////////////////////////////// + +`include "_qproc_defines.svh" + +module qproc_core # ( + parameter LFSR = 1, + parameter IN_PORT_QTY = 1, + parameter PMEM_AW = 8, + parameter DMEM_AW = 8, + parameter WMEM_AW = 8, + parameter REG_AW = 4 +)( + input wire c_clk_i , + input wire c_rst_ni , + input wire ps_clk_i , + input wire ps_rst_ni , + input wire en_i , + input wire restart_i , +// CORE CTRL + input wire [1:0] lfsr_cfg_i , + output wire [31:0] core_status_o , + output wire [31:0] core_debug_o , + output wire [31:0] lfsr_o , +// AXI Registers + input wire [63:0] port_dt_i [ IN_PORT_QTY ] , + input wire flag_i , +// Special Function Registers + output wire [7 :0] sreg_cfg_o , + output wire [7 :0] sreg_ctrl_o , + input wire [31:0] sreg_arith_i , + input wire [31:0] sreg_div_i[2] , + input wire [31:0] sreg_status_i , + input wire [31:0] sreg_core_r_dt_i[2] , + input wire [31:0] sreg_time_dt_i , + output wire [31:0] sreg_core_w_dt_o[2] , +// Peripherals + output wire usr_en_o , + output wire [7:0] usr_ctrl_o , + output wire [31:0] usr_dt_a_o , + output wire [31:0] usr_dt_b_o , + output wire [31:0] usr_dt_c_o , + output wire [31:0] usr_dt_d_o , + +// Memory + input wire [ 1:0] ps_mem_sel_i , + input wire ps_mem_we_i , + input wire [ 15:0] ps_mem_addr_i , + input wire [167:0] ps_mem_w_dt_i , + output wire [167:0] ps_mem_r_dt_o , +//Port + output wire port_we_o , + output PORT_DT port_o , +//Debug + output wire [31:0] core_do ); + + +wire [PMEM_AW-1:0] pmem_addr ; +wire pmem_en ; +wire [71:0] pmem_dt ; +wire dmem_we ; +wire [DMEM_AW-1:0] dmem_addr ; +wire [31:0] dmem_w_dt ; +wire [31:0] dmem_r_dt ; +wire wmem_we ; +wire [WMEM_AW-1:0] wmem_addr ; +wire [167:0] wmem_w_dt ; +wire [167:0] wmem_r_dt ; + +wire port_re; + + + + +qcore_cpu # ( + .LFSR ( LFSR ) , + .PMEM_AW ( PMEM_AW ) , + .DMEM_AW ( DMEM_AW ) , + .WMEM_AW ( WMEM_AW ) , + .REG_AW ( REG_AW ) +) CORE_CPU ( + .clk_i ( c_clk_i ) , + .rst_ni ( c_rst_ni ) , + .restart_i ( restart_i ) , + .en_i ( en_i ) , + .lfsr_cfg_i ( lfsr_cfg_i ) , + .lfsr_o ( lfsr_o ) , + .flag_i ( flag_i ) , // External Condition + .sreg_cfg_o ( sreg_cfg_o ) , + .sreg_ctrl_o ( sreg_ctrl_o ) , + .sreg_arith_i ( sreg_arith_i ) , // Arith Input + .sreg_div_i ( sreg_div_i ) , // Div Input + .sreg_status_i ( sreg_status_i ) , + .sreg_core_r_dt_i ( sreg_core_r_dt_i ) , + .sreg_port_dt_i ( {in_port_dt_r[31:0], in_port_dt_r[63:32] } ) , + .sreg_time_dt_i ( sreg_time_dt_i ) , + .sreg_core_w_dt_o ( sreg_core_w_dt_o ) , + .usr_ctrl_o ( usr_ctrl_o ) , + .usr_en_o ( usr_en_o ) , + .usr_dt_a_o ( usr_dt_a_o ) , + .usr_dt_b_o ( usr_dt_b_o ) , + .usr_dt_c_o ( usr_dt_c_o ) , + .usr_dt_d_o ( usr_dt_d_o ) , + .pmem_addr_o ( pmem_addr ) , + .pmem_en_o ( pmem_en ) , + .pmem_dt_i ( pmem_dt ) , + .dmem_we_o ( dmem_we ) , + .dmem_addr_o ( dmem_addr ) , + .dmem_w_dt_o ( dmem_w_dt ) , + .dmem_r_dt_i ( dmem_r_dt ) , + .wmem_we_o ( wmem_we ) , + .wmem_addr_o ( wmem_addr ) , + .wmem_w_dt_o ( wmem_w_dt ) , + .wmem_r_dt_i ( wmem_r_dt ) , + .port_we_o ( port_we_o ) , + .port_re_o ( port_re ) , + .port_o ( port_o ) , + .core_do ( core_do ) ); + + +reg [63:0 ] in_port_dt_r; +// PORT READ +/////////////////////////////////////////////////////////////////////////////// +always_ff @(posedge c_clk_i) begin + if ( restart_i ) in_port_dt_r <= 0 ; + else if ( port_re ) in_port_dt_r <= port_dt_i[port_o.p_addr[3:0]]; +end + + +qcore_mem # ( + .PMEM_AW ( PMEM_AW ) , + .DMEM_AW ( DMEM_AW ) , + .WMEM_AW ( WMEM_AW ) +) CORE_MEM ( + .c_clk_i ( c_clk_i ) , + .c_rst_ni ( c_rst_ni ) , + .ps_clk_i ( ps_clk_i ) , + .ps_rst_ni ( ps_rst_ni ) , + .ps_sel_i ( ps_mem_sel_i ) , + .ps_we_i ( ps_mem_we_i ) , + .ps_addr_i ( ps_mem_addr_i ) , + .ps_w_dt_i ( ps_mem_w_dt_i ) , + .ps_r_dt_o ( ps_mem_r_dt_o ) , + .c_pmem_en_i ( pmem_en ) , + .c_pmem_addr_i ( pmem_addr ) , + .c_pmem_r_dt_o ( pmem_dt ) , + .c_dmem_we_i ( dmem_we ) , + .c_dmem_addr_i ( dmem_addr ) , + .c_dmem_w_dt_i ( dmem_w_dt ) , + .c_dmem_r_dt_o ( dmem_r_dt ) , + .c_wmem_we_i ( wmem_we ) , + .c_wmem_addr_i ( wmem_addr ) , + .c_wmem_w_dt_i ( wmem_w_dt ) , + .c_wmem_r_dt_o ( wmem_r_dt ) ); + +assign core_status_o = 0; +assign core_debug_o =0; + +endmodule \ No newline at end of file diff --git a/firmware/ip/qick_processor/src/qproc_ctrl.sv b/firmware/ip/qick_processor/src/qproc_ctrl.sv new file mode 100644 index 0000000..6daa7a9 --- /dev/null +++ b/firmware/ip/qick_processor/src/qproc_ctrl.sv @@ -0,0 +1,341 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2024 +// Version : 4 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: + +*/ +////////////////////////////////////////////////////////////////////////////// +module qproc_ctrl # ( + parameter TIME_READ = 1 +)( +// Time, Core and AXI CLK & RST. + input wire t_clk_i , + input wire t_rst_ni , + input wire c_clk_i , + input wire c_rst_ni , +// External Control + input wire proc_start_i , + input wire proc_stop_i , + input wire core_start_i , + input wire core_stop_i , + input wire time_rst_i , + input wire time_updt_i , + input wire [31:0] time_updt_dt_i , +// Core Control + input wire int_time_en , //int_time_pen + input wire [3:0] int_time_cmd , //core_usr_operation + input wire [31:0] int_time_dt , //core_usr_operation +// AXI Control + input wire [15:0] PS_TPROC_CTRL, + input wire [10:9] PS_TPROC_CFG, + // input wire [15:0] xreg_TPROC_CTRL , + // input wire [15:0] xreg_TPROC_CFG , + input wire [31:0] xreg_TPROC_W_DT , +// QPROC_STATE + input wire all_fifo_full_i , +// CORE ST + output reg core_rst_o , + output reg core_en_o , +// TIME ST + output reg time_rst_o , + output reg time_en_o , + output wire [47:0] time_abs_o , + output reg [47:0] c_time_ref_o , + output wire [31:0] c_time_usr_o , // User time "current_user_time" +// DEBUG + output reg [ 2:0] time_st_do , + output reg [ 2:0] core_st_do , + output reg [ 6:0] t_debug_do , + output reg [ 6:0] c_debug_do +); + +//------------------------------------------------------- +// Code moved from qproc_axi_reg due to issue #33 +logic [15:0] xreg_TPROC_CTRL; +logic [10:9] xreg_TPROC_CFG, TPROC_CFG; + +logic [15:0] tproc_ctrl_rcd, tproc_ctrl_r, tproc_ctrl_2r; +logic [10:9] tproc_cfg_rcd; + +// From PS_CLK to C_CLK +always_ff @(posedge c_clk_i) + if (!c_rst_ni) begin + tproc_ctrl_rcd <= 0 ; + tproc_ctrl_r <= 0 ; + tproc_ctrl_2r <= 0 ; + tproc_cfg_rcd <= 0 ; + end else begin + tproc_ctrl_rcd <= PS_TPROC_CTRL ; + tproc_ctrl_r <= tproc_ctrl_rcd ; + tproc_ctrl_2r <= tproc_ctrl_r ; + tproc_cfg_rcd <= PS_TPROC_CFG ; + TPROC_CFG <= tproc_cfg_rcd ; + end + +// The C_TPROC_CTRL is only ONE clock. +assign xreg_TPROC_CTRL = tproc_ctrl_r & ~tproc_ctrl_2r ; +assign xreg_TPROC_CFG = TPROC_CFG; +//------------------------------------------------------- + + +// Control +reg t_core_rst_prev_net; // NET Request to RESET the Processor and go to previous state +reg [31:0] time_updt_dt ; // New incremental time value + +/////////////////////////////////////////////////////////////////////////////// +// CONTROL Signals +/////////////////////////////////////////////////////////////////////////////// + +/// IO CTRL +assign proc_start_io = proc_start_i & xreg_TPROC_CFG[10] ; +assign proc_stop_io = proc_stop_i & xreg_TPROC_CFG[10] ; + +/// PYTHON +assign time_stop_p = xreg_TPROC_CTRL[3] | xreg_TPROC_CTRL[9] | proc_stop_io ; // STOP | P_FREEZE +assign time_run_p = xreg_TPROC_CTRL[7] | xreg_TPROC_CTRL[8] ; // RUN | P_PAUSE +assign time_rst_stop_p = xreg_TPROC_CTRL[6] ; //T_RST | START | P_RST +assign time_rst_run_p = xreg_TPROC_CTRL[0] | xreg_TPROC_CTRL[2] | proc_start_io ; // START | T_RST +assign time_update_p = xreg_TPROC_CTRL[1] ; +assign time_step_p = xreg_TPROC_CTRL[10] | xreg_TPROC_CTRL[12] ; + +assign core_stop_p = xreg_TPROC_CTRL[3] | xreg_TPROC_CTRL[5] | xreg_TPROC_CTRL[8] | proc_stop_io; // STOP | C_STOP | P_PAUSE +assign core_run_p = xreg_TPROC_CTRL[7] | xreg_TPROC_CTRL[9] ; // RUN | P_FREEZE +assign core_rst_stop_p = xreg_TPROC_CTRL[6] ; // P_RST +assign core_rst_run_p = xreg_TPROC_CTRL[2] | xreg_TPROC_CTRL[4] | proc_start_io ; // START | C_START +assign core_rst_prev_p = xreg_TPROC_CTRL[0] ; // T_RST +assign core_step_p = xreg_TPROC_CTRL[10] | xreg_TPROC_CTRL[11] ; + +/// QPROC-CORE +assign time_rst_core = ( int_time_en & int_time_cmd[0]) ; +assign time_updt_core = ( int_time_en & int_time_cmd[1]) ; +assign time_ref_set = ( int_time_en & int_time_cmd[2]) ; +assign time_ref_inc = ( int_time_en & int_time_cmd[3]) ; + +/// NET CTRL +assign time_rst_net = time_rst_i & ~xreg_TPROC_CFG[9] ; +assign time_updt_net = time_updt_i & ~xreg_TPROC_CFG[9] ; +assign core_start_net = core_start_i & ~xreg_TPROC_CFG[9] ; +assign core_stop_net = core_stop_i & ~xreg_TPROC_CFG[9] ; + +assign c_time_rst_run = time_rst_run_p | time_rst_core ; +assign c_time_updt = time_update_p | time_updt_core ; + + + +/////////////////////////////////////////////////////////////////////////////// +// CORE CONTROL +/////////////////////////////////////////////////////////////////////////////// + +// Store Time_Update_Data from PROCESSOR or PYTHON in offset_dt_r +reg [31:0] offset_dt_r; +always_ff @(posedge c_clk_i) + if (!c_rst_ni) begin + offset_dt_r <= 0; + end else begin + if ( time_updt_core ) offset_dt_r <= int_time_dt ; // Update from CORE + else if ( time_update_p ) offset_dt_r <= xreg_TPROC_W_DT ; // Update from PYTHON + end + +assign ctrl_c_rst_stop = core_rst_stop_p ; +assign ctrl_c_rst_run = core_start_net | core_rst_run_p ; +assign ctrl_c_stop = core_stop_net | core_stop_p ; +assign ctrl_c_run = core_run_p; +assign ctrl_c_step = core_step_p ; + + +// Core Control State Machine +/////////////////////////////////////////////////////////////////////////////// +enum {C_RST_STOP=0, C_RST_STOP_WAIT=1, C_RST_RUN=2, C_RST_RUN_WAIT=3, C_STOP=4, C_RUN=5, C_STEP=6, C_END_STEP=7} core_st_nxt, core_st; + +// Sequential Stante Machine +always_ff @(posedge c_clk_i) + if (!c_rst_ni) core_st <= C_RST_STOP; + else core_st <= core_st_nxt; + +// State change and Out +always_comb begin + core_en_o = 0; + core_rst_o = 0; + core_st_nxt = core_st; + //COMMON TRANSITIONS + if ( ctrl_c_stop ) core_st_nxt = C_STOP; + else if ( ctrl_c_run ) core_st_nxt = C_RUN; + else if ( ctrl_c_rst_run ) core_st_nxt = C_RST_RUN; + else if ( ctrl_c_rst_stop) core_st_nxt = C_RST_STOP; + else if ( ctrl_c_step ) core_st_nxt = C_STEP; + //State Transitions and Out + case (core_st) + C_RST_RUN : begin + core_rst_o = 1; + if (all_fifo_full_i) core_st_nxt = C_RST_RUN_WAIT; + end + C_RST_RUN_WAIT : + if (!all_fifo_full_i) core_st_nxt = C_RUN; + C_RST_STOP : begin + core_rst_o = 1; + if (all_fifo_full_i) core_st_nxt = C_RST_STOP_WAIT; + end + C_RST_STOP_WAIT : + if (!all_fifo_full_i) core_st_nxt = C_STOP; + C_RUN: begin + core_en_o = 1; + end + C_STOP: begin + end + C_STEP: begin + core_en_o = 1; + core_st_nxt = C_END_STEP; + end + C_END_STEP: begin + if (!ctrl_c_step) core_st_nxt = C_STOP; + end + endcase +end + +/////////////////////////////////////////////////////////////////////////////// +// TIME CONTROL +/////////////////////////////////////////////////////////////////////////////// + +// T_CLK DOMAIN Synchronization +/////////////////////////////////////////////////////////////////////////////// +sync_reg # (.DW ( 7 ) ) sync_ctrl_ps_t ( + .dt_i ( {core_rst_o, time_rst_stop_p, c_time_rst_run, c_time_updt, time_stop_p, time_run_p, time_step_p} ) , + .clk_i ( t_clk_i ) , + .rst_ni ( t_rst_ni ) , + .dt_o ( {core_rst_ack, t_time_rst_stop, t_time_rst_run, t_time_update, t_time_stop, t_time_run, t_time_step } ) ); + + +always_ff @(posedge t_clk_i) + if (!t_rst_ni) begin + t_core_rst_prev_net <= 1'b0 ; // NET Request to RESET the Processor + time_updt_dt <= 32'd0; // Store Time_Update_Data from offset_dt_r(CORE, PYTHON) OR time_updt_dt_i (NET) + end else begin + if ( t_time_update ) + time_updt_dt <= offset_dt_r; + else + time_updt_dt <= time_updt_dt_i; + if ( time_rst_net ) t_core_rst_prev_net <= 1'b1; + else if ( core_rst_ack ) t_core_rst_prev_net <= 1'b0; + end + +assign ctrl_t_rst_stop = t_time_rst_stop ; +assign ctrl_t_rst_run = time_rst_net | t_time_rst_run ; +assign ctrl_t_updt = time_updt_net | t_time_update ; +assign ctrl_t_run = t_time_run ; +assign ctrl_t_stop = t_time_stop; +assign ctrl_t_step = t_time_step ; + +// Time Control State Machine +/////////////////////////////////////////////////////////////////////////////// +enum {T_RST_STOP=0, T_RST_RUN=1, T_UPDT=2, T_RUN=3, T_STOP=4, T_STEP=5} time_st_nxt, time_st; +// Sequential Stante Machine +always_ff @(posedge t_clk_i) + if (!t_rst_ni) time_st <= T_RST_STOP; + else time_st <= time_st_nxt; +// State change and Out +reg time_updt ; +always_comb begin + time_en_o = 0; + time_rst_o = 0; + time_updt = 0; + time_st_nxt = time_st; + //COMMON TRANSITIONS + if ( ctrl_t_rst_stop ) time_st_nxt = T_RST_STOP ; + if ( ctrl_t_rst_run ) time_st_nxt = T_RST_RUN ; + else if ( ctrl_t_updt ) time_st_nxt = T_UPDT ; + else if ( ctrl_t_run ) time_st_nxt = T_RUN ; + else if ( ctrl_t_stop ) time_st_nxt = T_STOP ; + else if ( ctrl_t_step ) time_st_nxt = T_STEP ; + case (time_st) + T_RST_STOP : begin + time_en_o = 1; + time_rst_o = 1; + time_st_nxt = T_STOP ; + end + T_RST_RUN : begin + time_en_o = 1; + time_rst_o = 1; + time_st_nxt = T_RUN ; + end + T_UPDT : begin + time_en_o = 1; + time_updt = 1; + time_st_nxt = T_RUN ; + end + T_RUN: begin + time_en_o = 1; + end + T_STEP: begin + time_en_o = 1; + time_st_nxt = T_STOP ; + end + endcase +end + + +// Time REF +/////////////////////////////////////////////////////////////////////////////// +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) c_time_ref_o <= '{default:'0} ; + else if (core_rst_o) c_time_ref_o <= '{default:'0} ; + else if (time_ref_set ) c_time_ref_o <= {16'd0, int_time_dt} ; + else if (time_ref_inc ) c_time_ref_o <= c_time_ref_o + {16'd0, int_time_dt} ; +end + +// Time ABS +/////////////////////////////////////////////////////////////////////////////// +qproc_time_ctrl QTIME_CTRL ( + .t_clk_i ( t_clk_i ) , + .t_rst_ni ( t_rst_ni ) , + .time_en_i ( time_en_o ) , + .time_rst_i ( time_rst_o ) , + .time_init_i ( 1'b0 ) , + .time_updt_i ( time_updt ) , + .updt_dt_i ( time_updt_dt ) , + .time_abs_o ( time_abs_o ) ); + +assign c_debug_do = { 2'b00, ctrl_c_step, ctrl_c_stop, ctrl_c_run, ctrl_c_rst_run, ctrl_c_rst_stop } ; +assign t_debug_do = { ctrl_t_updt, 1'b0, ctrl_t_step, ctrl_t_stop, ctrl_t_run, ctrl_t_rst_run, ctrl_t_rst_stop } ; + +/////////////////////////////////////////////////////////////////////////////// +// TIME READ +reg [47:0] t_time_abs_cdc, c_time_abs_r ; // Absolute Time Counter Value "Registered" + +generate + if ( TIME_READ == 1) begin : QPER_TIME_READ + sync_ab_en sync_ab_en_inst ( + .clk_a_i ( c_clk_i ) , + .rst_a_ni ( c_rst_ni ) , + .clk_b_i ( t_clk_i ) , + .rst_b_ni ( t_rst_ni ) , + .a_en_o ( c_time_en ) , + .b_en_o ( t_time_en ) ); + + // Register TIME_ABS + /////////////////////////////////////////////////////////////////////////////// + always_ff @(posedge t_clk_i) begin + if ( !t_rst_ni ) t_time_abs_cdc <= 0; + else if ( t_time_en ) t_time_abs_cdc <= time_abs_o; + end + + always_ff @(posedge c_clk_i) begin + if ( !c_rst_ni ) c_time_abs_r <= 0; + else if ( c_time_en ) c_time_abs_r <= t_time_abs_cdc; + end + + assign c_time_usr_o = (c_time_abs_r - c_time_ref_o); + + end else begin : TIME_READ_NO + assign c_time_usr_o = 0; + end +endgenerate + +assign time_st_do = { time_st[2:0] }; +assign core_st_do = { core_st[2:0] }; + +endmodule diff --git a/firmware/ip/qick_processor/src/qproc_dispatcher.sv b/firmware/ip/qick_processor/src/qproc_dispatcher.sv new file mode 100644 index 0000000..92c467b --- /dev/null +++ b/firmware/ip/qick_processor/src/qproc_dispatcher.sv @@ -0,0 +1,434 @@ +`include "_qproc_defines.svh" + +module qproc_dispatcher # ( + parameter FIFO_DEPTH = 8 , + parameter IN_PORT_QTY = 1 , + parameter OUT_TRIG_QTY = 1 , + parameter OUT_DPORT_QTY = 1 , + parameter OUT_DPORT_DW = 4 , + parameter OUT_WPORT_QTY = 1 +)( + input wire c_clk_i , + input wire c_rst_ni , + input wire t_clk_i , + input wire t_rst_ni , + //Port + input wire core_en , + input wire core_rst , + input wire time_en , + input wire time_rst , + input wire [47:0] c_time_ref_dt , + input wire [47:0] time_abs_i , + input wire port_we , + input PORT_DT out_port_data , + output wire all_fifo_full , + output wire some_fifo_full , + // TRIGGERS + output wire port_trig_o [OUT_TRIG_QTY] , + // DATA OUTPUT INTERFACE + output wire port_tvalid_o[OUT_DPORT_QTY] , + output wire [OUT_DPORT_DW-1:0] port_tdata_o [OUT_DPORT_QTY] , + // WAVE OUTPUT INTERFACE + output wire [167:0] m_axis_tdata [OUT_WPORT_QTY] , + output wire m_axis_tvalid [OUT_WPORT_QTY] , + input wire m_axis_tready [OUT_WPORT_QTY] , + // DEBUG outputs + output wire [31:0] fifo_dt_do , + output wire [31:0] axi_fifo_do , + output wire [15:0] c_fifo_do , + output wire [15:0] t_fifo_do +); + + +// FIFOS & DISPATCHER + +// .p_type > Select between WAVE or DATA (TRIG is DATA with high address) +// .p_addr > Select Port Addr (Bit 3 select between DATA and TRIGGER (Addr 0 to 7 are Data, Addr 8 to 15 are Trigger) +// .p_time > c_fifo_time_in_r +// .p_data > c_fifo_data_in_r +reg [ 47:0] time_abs_r ; + +reg [ 47:0] c_fifo_time_in_r ; // TIME from the CORE > To the FIFOs +reg [167:0] c_fifo_data_in_r ; // DATA from the CORE > To the FIFOs + +wire [47:0] t_fifo_wave_time [OUT_WPORT_QTY-1:0]; // TIME from the FIFO > To the Comparator +wire [167:0] t_fifo_wave_dt [OUT_WPORT_QTY-1:0]; // DATA from the FIFO > TO the WPORT +// wire [47:0] W_RESULT [OUT_WPORT_QTY-1:0]; // Comparison between t_fifo_wave_time and time_abs_i +wire W_CARRYOUT [OUT_WPORT_QTY-1:0]; // Carry of Comparison between t_fifo_wave_time and time_abs_i +reg [OUT_WPORT_QTY-1:0] wave_t_gr; // Sign bit of W_RESULT +reg [OUT_WPORT_QTY-1:0] c_fifo_wave_push, c_fifo_wave_push_r, c_fifo_wave_push_s; +reg [OUT_WPORT_QTY-1:0] wave_pop, wave_pop_prev; +reg [OUT_WPORT_QTY-1:0] wave_pop_r, wave_pop_r2; + +wire [47:0] t_fifo_data_time [OUT_DPORT_QTY-1:0]; // TIME from the FIFO > To the Comparator +wire [OUT_DPORT_DW-1 :0] t_fifo_data_dt [OUT_DPORT_QTY-1:0]; // DATA from the FIFO > TO the DPORT +// wire [47:0] D_RESULT [OUT_DPORT_QTY-1:0]; // Comparison between t_fifo_data_time and time_abs_i +wire D_CARRYOUT [OUT_DPORT_QTY-1:0]; // Carry of Comparison between t_fifo_data_time and time_abs_i +reg [OUT_DPORT_QTY-1:0] data_t_gr; // Sign bit of D_RESULT +reg [OUT_DPORT_QTY-1:0] c_fifo_data_push, c_fifo_data_push_r, c_fifo_data_push_s ; +reg data_pop[OUT_DPORT_QTY], data_pop_prev[OUT_DPORT_QTY]; +reg data_pop_r[OUT_DPORT_QTY], data_pop_r2[OUT_DPORT_QTY]; + +wire [47:0] t_fifo_trig_time [OUT_TRIG_QTY]; // TIME from the FIFO > To the Comparator +wire t_fifo_trig_dt [OUT_TRIG_QTY]; // DATA from the FIFO > TO the WPORT +// wire [47:0] T_RESULT [OUT_TRIG_QTY]; // Comparison between t_fifo_trig_time and time_abs_i +wire T_CARRYOUT [OUT_TRIG_QTY]; // Carry of Comparison between t_fifo_trig_time and time_abs_i +reg [OUT_TRIG_QTY-1:0] trig_t_gr; // Sign bit of T_RESULT +reg [OUT_TRIG_QTY-1:0] c_fifo_trig_push, c_fifo_trig_push_r, c_fifo_trig_push_s ; +reg trig_pop[OUT_TRIG_QTY], trig_pop_prev[OUT_TRIG_QTY]; +reg trig_pop_r[OUT_TRIG_QTY], trig_pop_r2[OUT_TRIG_QTY]; + +reg [OUT_TRIG_QTY-1:0] c_fifo_trig_empty ; +wire [OUT_TRIG_QTY-1:0] t_fifo_trig_empty, c_fifo_trig_full ; +reg [OUT_DPORT_QTY-1:0] c_fifo_data_empty ; +wire [OUT_DPORT_QTY-1:0] t_fifo_data_empty, c_fifo_data_full ; +reg [OUT_WPORT_QTY-1:0] c_fifo_wave_empty; +wire [OUT_WPORT_QTY-1:0] t_fifo_wave_empty , c_fifo_wave_full ; +wire dfifo_full, wfifo_full; + +/////////////////////////////////////////////////////////////////////////////// +/// FIFO & DISPATCHER +/////////////////////////////////////////////////////////////////////////////// +assign all_tfifo_empty = &c_fifo_trig_empty ; +assign all_dfifo_empty = &c_fifo_data_empty ; +assign all_wfifo_empty = &c_fifo_wave_empty ; +assign all_fifo_empty = all_tfifo_empty & all_dfifo_empty & all_wfifo_empty ; + +assign all_tfifo_full = &c_fifo_trig_full ; +assign all_dfifo_full = &c_fifo_data_full ; +assign all_wfifo_full = &c_fifo_wave_full ; +assign all_fifo_full = all_dfifo_full & all_wfifo_full & all_tfifo_full; + +assign tfifo_full = |c_fifo_trig_full ; +assign dfifo_full = |c_fifo_data_full ; +assign wfifo_full = |c_fifo_wave_full ; +assign some_fifo_full = tfifo_full | dfifo_full | wfifo_full ; + +// CLOCK DOMAIN CHANGE +(* ASYNC_REG = "TRUE" *) reg [OUT_TRIG_QTY-1:0] fifo_trig_empty_cdc; +(* ASYNC_REG = "TRUE" *) reg [OUT_DPORT_QTY-1:0] fifo_data_empty_cdc; +(* ASYNC_REG = "TRUE" *) reg [OUT_WPORT_QTY-1:0] fifo_wave_empty_cdc; +always_ff @(posedge c_clk_i) begin + fifo_trig_empty_cdc <= t_fifo_trig_empty; + fifo_data_empty_cdc <= t_fifo_data_empty; + fifo_wave_empty_cdc <= t_fifo_wave_empty; + c_fifo_trig_empty <= fifo_trig_empty_cdc; + c_fifo_data_empty <= fifo_data_empty_cdc; + c_fifo_wave_empty <= fifo_wave_empty_cdc; +end + +/////////////////////////////////////////////////////////////////////////////// +/// FIFO CTRL-REG +always_comb begin + c_fifo_wave_push = 0; + c_fifo_data_push = 0; + c_fifo_trig_push = 0; + if (port_we) + if (out_port_data.p_type) + if ( out_port_data.p_addr[5] == 1'b1 ) //TRIGGER Selection Bit + c_fifo_trig_push [out_port_data.p_addr[4:0] ] = 1'b1 ; //32 Possible Port Address + else // DATA + c_fifo_data_push [out_port_data.p_addr[4:0] ] = 1'b1 ; //32 Possible Port Address + else + c_fifo_wave_push [out_port_data.p_addr] = 1'b1 ; + if (core_en) begin + c_fifo_trig_push_s = c_fifo_trig_push_r; + c_fifo_data_push_s = c_fifo_data_push_r; + c_fifo_wave_push_s = c_fifo_wave_push_r; + end else begin + c_fifo_trig_push_s = '{default:'0} ; + c_fifo_data_push_s = '{default:'0} ; + c_fifo_wave_push_s = '{default:'0} ; + end +end + +always_ff @ (posedge c_clk_i, negedge c_rst_ni) begin + if (!c_rst_ni) begin + c_fifo_data_in_r <= '{default:'0} ; + c_fifo_time_in_r <= '{default:'0} ; + c_fifo_trig_push_r <= '{default:'0} ; + c_fifo_data_push_r <= '{default:'0} ; + c_fifo_wave_push_r <= '{default:'0} ; + end else if (core_en) begin + c_fifo_trig_push_r <= c_fifo_trig_push ; + c_fifo_data_push_r <= c_fifo_data_push ; + c_fifo_wave_push_r <= c_fifo_wave_push ; + if (c_fifo_trig_push | c_fifo_data_push | c_fifo_wave_push) begin + c_fifo_data_in_r <= out_port_data.p_data ; + //c_fifo_time_in_r <= {16'd0, out_port_data.p_time} + c_time_ref_dt; + c_fifo_time_in_r <= { {16{out_port_data.p_time[31]}} , out_port_data.p_time} + c_time_ref_dt; + end + end +end + + +always_ff @ (posedge t_clk_i, negedge t_rst_ni) begin + if (!t_rst_ni) begin + time_abs_r <= '{default:'0} ; + trig_pop_r <= '{default:'0} ; + trig_pop_r2 <= '{default:'0} ; + data_pop_r <= '{default:'0} ; + data_pop_r2 <= '{default:'0} ; + wave_pop_r <= '{default:'0} ; + wave_pop_r2 <= '{default:'0} ; + end else begin + time_abs_r <= time_abs_i; + trig_pop_r <= trig_pop; + trig_pop_r2 <= trig_pop_r; + data_pop_r <= data_pop; + data_pop_r2 <= data_pop_r; + wave_pop_r <= wave_pop; + wave_pop_r2 <= wave_pop_r; + end +end + + +/////////////////////////////////////////////////////////////////////////////// +/// TRIGGER PORT +/////////////////////////////////////////////////////////////////////////////// +genvar ind_tfifo; +generate + for (ind_tfifo=0; ind_tfifo < OUT_TRIG_QTY; ind_tfifo=ind_tfifo+1) begin: TRIG_PORT + // TRIGGER FIFO + BRAM_FIFO_DC_2 # ( + .FIFO_DW (1+48) , + .FIFO_AW (FIFO_DEPTH) + ) trig_fifo_inst ( + .wr_clk_i ( c_clk_i ) , + .wr_rst_ni ( c_rst_ni ) , + .wr_en_i ( 1'b1 ) , + .push_i ( c_fifo_trig_push_s[ind_tfifo] ) , + .data_i ( {c_fifo_data_in_r[0],c_fifo_time_in_r} ) , + .rd_clk_i ( t_clk_i ) , + .rd_rst_ni ( t_rst_ni ) , + .rd_en_i ( time_en ) , + .pop_i ( trig_pop [ind_tfifo] ) , + .data_o ( {t_fifo_trig_dt[ind_tfifo], t_fifo_trig_time[ind_tfifo]} ) , + .flush_i ( core_rst ), + .async_empty_o ( t_fifo_trig_empty [ind_tfifo] ) , // SYNC with RD_CLK + .async_full_o ( c_fifo_trig_full [ind_tfifo] ) ); // SYNC with WR_CLK + + // Time Comparator + ADDSUB_MACRO #( + .DEVICE ("7SERIES"), // Target Device: "7SERIES" + .LATENCY ( 1 ), // Desired clock cycle latency, 0-2 + .WIDTH ( 48 ) // Input / output bus width, 1-48 + ) ADDSUB_MACRO_T_inst ( + .CARRYOUT ( T_CARRYOUT[ind_tfifo] ), // 1-bit carry-out output signal + .RESULT ( /*T_RESULT[ind_tfifo]*/ ), // Add/sub result output, width defined by WIDTH parameter + .A ( t_fifo_trig_time[ind_tfifo] ), // Input A bus, width defined by WIDTH parameter + .B ( time_abs_r[47:0] ), // Input B bus, width defined by WIDTH parameter + .ADD_SUB ( 1'b0 ), // 1-bit add/sub input, high selects add, low selects subtract + .CARRYIN ( 1'b0 ), // 1-bit carry-in input + .CE ( 1'b1 ), // 1-bit clock enable input + .CLK ( t_clk_i ), // 1-bit clock input + .RST ( ~t_rst_ni ) // 1-bit active high synchronous reset + ); + // POP Generator + always_comb begin : TRIG_DISPATCHER + // trig_t_gr[ind_tfifo] = T_RESULT[ind_tfifo][47]; + trig_t_gr[ind_tfifo] = ~T_CARRYOUT[ind_tfifo]; + trig_pop[ind_tfifo] = 0; + trig_pop_prev[ind_tfifo] = |({trig_pop_r[ind_tfifo], trig_pop_r2[ind_tfifo]}); + if (time_en & ~t_fifo_trig_empty[ind_tfifo] ) + if ( trig_t_gr[ind_tfifo] & ~trig_pop_prev[ind_tfifo] ) + trig_pop [ind_tfifo] = 1'b1 ; + end //ALWAYS + end //FOR +endgenerate + + +/////////////////////////////////////////////////////////////////////////////// +/// WAVE PORT +/////////////////////////////////////////////////////////////////////////////// +genvar ind_wfifo; +generate + for (ind_wfifo=0; ind_wfifo < OUT_WPORT_QTY; ind_wfifo=ind_wfifo+1) begin: WAVE_PORT + // WaveForm FIFO + BRAM_FIFO_DC_2 # ( + .FIFO_DW (168+48) , + .FIFO_AW (FIFO_DEPTH) + ) wave_fifo_inst ( + .wr_clk_i ( c_clk_i ) , + .wr_rst_ni ( c_rst_ni ) , + .wr_en_i ( 1'b1 ) , + .push_i ( c_fifo_wave_push_s [ind_wfifo] ) , + .data_i ( {c_fifo_data_in_r,c_fifo_time_in_r} ) , + .rd_clk_i ( t_clk_i ) , + .rd_rst_ni ( t_rst_ni ) , + .rd_en_i ( time_en ) , + .pop_i ( wave_pop [ind_wfifo] ) , + .data_o ( {t_fifo_wave_dt[ind_wfifo],t_fifo_wave_time[ind_wfifo]} ) , + .flush_i ( core_rst ), + .async_empty_o ( t_fifo_wave_empty [ind_wfifo] ) , // SYNC with RD_CLK + .async_full_o ( c_fifo_wave_full [ind_wfifo] ) ); // SYNC with WR_CLK + // Time Comparator + ADDSUB_MACRO #( + .DEVICE ( "7SERIES" ), // Target Device: "7SERIES" + .LATENCY ( 1 ), // Desired clock cycle latency, 0-2 + .WIDTH ( 48 ) // Input / output bus width, 1-48 + ) ADDSUB_MACRO_W_inst ( + .CARRYOUT ( W_CARRYOUT[ind_wfifo] ), // 1-bit carry-out output signal + .RESULT ( /*W_RESULT[ind_wfifo]*/ ), // Add/sub result output, width defined by WIDTH parameter + .B ( time_abs_r[47:0] ), // Input A bus, width defined by WIDTH parameter + .A ( t_fifo_wave_time[ind_wfifo] ), // Input B bus, width defined by WIDTH parameter + .ADD_SUB ( 1'b0 ), // 1-bit add/sub input, high selects add, low selects subtract + .CARRYIN ( 1'b0 ), // 1-bit carry-in input + .CE ( 1'b1 ), // 1-bit clock enable input + .CLK ( t_clk_i ), // 1-bit clock input + .RST ( ~t_rst_ni ) // 1-bit active high synchronous reset + ); + // POP Generator + always_comb begin : WAVE_DISPATCHER + // wave_t_gr[ind_wfifo] = W_RESULT[ind_wfifo][47]; + wave_t_gr[ind_wfifo] = ~W_CARRYOUT[ind_wfifo]; + wave_pop[ind_wfifo] = 0; + wave_pop_prev[ind_wfifo] = |({wave_pop_r[ind_wfifo], wave_pop_r2[ind_wfifo]}); + if (time_en & ~t_fifo_wave_empty[ind_wfifo]) + if ( wave_t_gr[ind_wfifo] & ~wave_pop_prev[ind_wfifo] ) + wave_pop [ind_wfifo] = 1'b1 ; + end //ALWAYS + end // FOR +endgenerate + +/////////////////////////////////////////////////////////////////////////////// +/// DATA PORT +/////////////////////////////////////////////////////////////////////////////// +genvar ind_dfifo; +generate + for (ind_dfifo=0; ind_dfifo < OUT_DPORT_QTY; ind_dfifo=ind_dfifo+1) begin: DATA_PORT + // DATA FIFO + BRAM_FIFO_DC_2 # ( + .FIFO_DW (OUT_DPORT_DW+48) , + .FIFO_AW (FIFO_DEPTH) + ) data_fifo_inst ( + .wr_clk_i ( c_clk_i ) , + .wr_rst_ni ( c_rst_ni ) , + .wr_en_i ( 1'b1 ) , + .push_i ( c_fifo_data_push_s[ind_dfifo] ) , + .data_i ( {c_fifo_data_in_r[OUT_DPORT_DW-1:0],c_fifo_time_in_r} ) , + .rd_clk_i ( t_clk_i ) , + .rd_rst_ni ( t_rst_ni ) , + .rd_en_i ( time_en ) , + .pop_i ( data_pop [ind_dfifo] ) , + .data_o ( {t_fifo_data_dt[ind_dfifo], t_fifo_data_time[ind_dfifo]} ) , + .flush_i ( core_rst ), + .async_empty_o ( t_fifo_data_empty [ind_dfifo] ) , // SYNC with RD_CLK + .async_full_o ( c_fifo_data_full [ind_dfifo] ) ); // SYNC with WR_CLK + // Time Comparator + ADDSUB_MACRO #( + .DEVICE ("7SERIES"), // Target Device: "7SERIES" + .LATENCY ( 1 ), // Desired clock cycle latency, 0-2 + .WIDTH ( 48 ) // Input / output bus width, 1-48 + ) ADDSUB_MACRO_D_inst ( + .CARRYOUT ( D_CARRYOUT[ind_dfifo] ), // 1-bit carry-out output signal + .RESULT ( /*D_RESULT[ind_dfifo]*/ ), // Add/sub result output, width defined by WIDTH parameter + .B ( time_abs_r[47:0] ), // Input A bus, width defined by WIDTH parameter + .ADD_SUB ( 1'b0 ), // 1-bit add/sub input, high selects add, low selects subtract + .A ( t_fifo_data_time[ind_dfifo] ), // Input B bus, width defined by WIDTH parameter + .CARRYIN ( 1'b0 ), // 1-bit carry-in input + .CE ( 1'b1 ), // 1-bit clock enable input + .CLK ( t_clk_i ), // 1-bit clock input + .RST ( ~t_rst_ni ) // 1-bit active high synchronous reset + ); + // POP Generator + always_comb begin : DATA_DISPATCHER + // data_t_gr[ind_dfifo] = D_RESULT[ind_dfifo][47]; + data_t_gr[ind_dfifo] = ~D_CARRYOUT[ind_dfifo]; + data_pop[ind_dfifo] = 0; + data_pop_prev[ind_dfifo] = |({data_pop_r[ind_dfifo], data_pop_r2[ind_dfifo]}); + if (time_en & ~t_fifo_data_empty[ind_dfifo] ) + if ( data_t_gr[ind_dfifo] & ~data_pop_prev[ind_dfifo] ) + data_pop [ind_dfifo] = 1'b1 ; + end //ALWAYS + end //FOR +endgenerate + + +/////////////////////////////////////////////////////////////////////////////// +// OUTPUTS +/////////////////////////////////////////////////////////////////////////////// + + +/////////////////////////////////////////////////////////////////////////////// +// OUT TRIGGERS +reg port_trig_r [OUT_TRIG_QTY]; +integer ind_tport; +always_ff @ (posedge t_clk_i, negedge t_rst_ni) begin + for (ind_tport=0; ind_tport < OUT_TRIG_QTY; ind_tport=ind_tport+1) begin: OUT_TRIG_PORT + if (!t_rst_ni) + port_trig_r[ind_tport] <= 1'b0; + else if (time_rst) + port_trig_r[ind_tport] <= 1'b0; + else + if (trig_pop[ind_tport]) + port_trig_r[ind_tport] <= t_fifo_trig_dt[ind_tport] ; + end +end +assign port_trig_o = port_trig_r; + +/////////////////////////////////////////////////////////////////////////////// +// OUT DATA +reg [OUT_DPORT_DW-1:0] port_dt_r [OUT_DPORT_QTY]; +integer ind_dport; +always_ff @ (posedge t_clk_i, negedge t_rst_ni) begin + for (ind_dport=0; ind_dport < OUT_DPORT_QTY; ind_dport=ind_dport+1) begin: OUT_DATA_PORT + if (!t_rst_ni) + port_dt_r[ind_dport] <= '{default:'0} ; + else if (time_rst) + port_dt_r[ind_dport] <= '{default:'0} ; + else + if (data_pop[ind_dport]) + port_dt_r[ind_dport] <= t_fifo_data_dt[ind_dport] ; + end +end +assign port_tvalid_o = data_pop_r; +assign port_tdata_o = port_dt_r; + + +/////////////////////////////////////////////////////////////////////////////// +// OUT WAVES +// REGISTERED OUTPUT +reg m_axis_tvalid_r [ OUT_WPORT_QTY] ; +reg [167:0] m_axis_tdata_r [ OUT_WPORT_QTY] ; +integer ind_wport; +always_ff @ (posedge t_clk_i, negedge t_rst_ni) begin + for (ind_wport=0; ind_wport < OUT_WPORT_QTY; ind_wport=ind_wport+1) begin: OUT_WAVE_PORT + if (!t_rst_ni) begin + m_axis_tvalid_r[ind_wport] <= 1'b0 ; + m_axis_tdata_r [ind_wport] <= '{default:'0} ; + end else if (time_rst) begin + m_axis_tvalid_r[ind_wport] <= 1'b0 ; + m_axis_tdata_r [ind_wport] <= '{default:'0} ; + end else begin + m_axis_tvalid_r[ind_wport] <= wave_pop [ind_wport] ; + m_axis_tdata_r[ind_wport] <= t_fifo_wave_dt [ind_wport] ; + end + end +end + +assign m_axis_tvalid = m_axis_tvalid_r ; +assign m_axis_tdata = m_axis_tdata_r ; + +///// DEBUG + assign fifo_dt_do = {t_fifo_data_time[0][27:0], t_fifo_data_dt[0][3:0]} ; + + assign axi_fifo_do[31:28] = t_fifo_data_dt[0][3:0] ; + assign axi_fifo_do[27:12] = t_fifo_data_time[0][15:0] ; + assign axi_fifo_do[11: 8] = { some_fifo_full , wfifo_full , dfifo_full , tfifo_full }; + assign axi_fifo_do[ 7: 4] = { all_fifo_full , all_wfifo_full , all_dfifo_full, all_tfifo_full }; + assign axi_fifo_do[ 3: 0] = { all_fifo_empty, all_wfifo_empty, all_dfifo_empty, all_tfifo_empty }; + + assign c_fifo_do[15:11] = { c_fifo_wave_push_s[0],c_fifo_data_push_s[1],c_fifo_data_push_s[0],c_fifo_trig_push_s[1],c_fifo_trig_push_s[0]}; + assign c_fifo_do[10: 9] = { c_fifo_wave_full[1], c_fifo_wave_full[0] }; + assign c_fifo_do[ 8: 7] = { c_fifo_data_full[1], c_fifo_data_full[0] }; + assign c_fifo_do[ 6: 5] = { c_fifo_trig_full[1], c_fifo_trig_full[0] }; + assign c_fifo_do[ 4: 0] = { all_fifo_full, all_wfifo_full, all_dfifo_full, all_tfifo_full, 1'b0 }; + + assign t_fifo_do[15:11] = { wave_pop_r[0], data_pop_r[1], data_pop_r[0], trig_pop_r[1], trig_pop_r[0] } ; + assign t_fifo_do[10: 9] = { c_fifo_wave_empty[1], c_fifo_wave_empty[0] }; + assign t_fifo_do[ 8: 7] = { c_fifo_data_empty[1], c_fifo_data_empty[0] }; + assign t_fifo_do[ 6: 5] = { c_fifo_trig_empty[1], c_fifo_trig_empty[0] }; + assign t_fifo_do[ 4: 0] = { all_fifo_empty, all_wfifo_empty, all_dfifo_empty, all_tfifo_empty, 1'b0 }; +endmodule + diff --git a/firmware/ip/qick_processor/src/qproc_inport_reg.sv b/firmware/ip/qick_processor/src/qproc_inport_reg.sv new file mode 100644 index 0000000..534c282 --- /dev/null +++ b/firmware/ip/qick_processor/src/qproc_inport_reg.sv @@ -0,0 +1,60 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 11-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: + This block register the input of the sAxi. + Indicates the arrival of new data in port_tnew_o +*/ +////////////////////////////////////////////////////////////////////////////// + +`include "_qproc_defines.svh" + +module qproc_inport_reg # ( + parameter PORT_QTY = 2 +)( +// CLK & RST. + input wire c_clk_i , + input wire c_rst_ni , + input wire c_clear , +// DATA INPUT INTERFACE + input wire port_tvalid_i [ PORT_QTY ] , + input wire [63:0] port_tdata_i [ PORT_QTY ] , +// DATA OUTPUT INTERFACE + output wire [15:0 ] port_tnew_o , + output wire [63:0] port_tdata_o [ PORT_QTY ] + ); + +localparam ZFP = 16 - PORT_QTY; // Zero Fill for Input Port + + +// REGISTR INPUTS +reg [63:0] port_dt_r [PORT_QTY] ; +reg [PORT_QTY-1:0] port_dt_new ; + +genvar ind; +generate + for (ind=0; ind < PORT_QTY; ind=ind+1) begin + always_ff @(posedge c_clk_i) + if (!c_rst_ni) begin + port_dt_r[ind] <= 0 ; + port_dt_new[ind] <= 0 ; + end else begin + if ( port_tvalid_i[ind] ) begin + port_dt_r[ind] <= port_tdata_i[ind]; + port_dt_new[ind] <= 1'b1; + end else if (c_clear) + port_dt_new[ind] <= 0 ; + end + end +endgenerate + +assign port_tnew_o = { {ZFP{1'b0}} , port_dt_new }; + +assign port_tdata_o = port_dt_r ; + +endmodule diff --git a/firmware/ip/qick_processor/src/qproc_mem_ctrl.v b/firmware/ip/qick_processor/src/qproc_mem_ctrl.v new file mode 100644 index 0000000..109524f --- /dev/null +++ b/firmware/ip/qick_processor/src/qproc_mem_ctrl.v @@ -0,0 +1,224 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: +// Assembled memory access module. Three modes of accessing the memory: +// +// * Single access using the in/out ports. It's only available when busy_o = 0. +// +// * AXIS read: this mode allows to send data using m_axis_* interface, using +// ADDR_REG as the starting address and LEN_REG to indicate the number of +// samples to be transferred. The last sample will assert m_axis_tlast_o to +// indicate the external block transaction is done. Similar to AXIS write +// mode, the user needs to set START_REG = 1 to start the process. +// +// * AXIS write: this mode receives data from s_axis_* interface and writes +// into the memory using ADDR_REG as the starting address. The user must also +// provide the START_REG = 1 to allow starting receiving data. The block will +// rely on s_axis_tlast_i = 1 to finish the writing process. +// +// When not performing any AXIS transaction, the block will grant access to +// the memory using the single access interface. This is a very basic +// handshake interface to allow external blocks to easily communicate and +// perform single-access transaction. +// +// Once a AXIS transaction is done, the user must set START_REG = 0 and back +// to 1 if a new AXIS transaction needs to be executed. START_REG = 1 steady +// will not allow further AXIS transactions, and will only allow +// single-access. +// +// Registers: +// +// MODE_REG : indicates the type of the next AXIS transaction. +// * 0 : AXIS Read (from memory to m_axis). +// * 1 : AXIS Write (from s_axis to memory). +// +// START_REG : starts execution of indicated AXIS transaction. +// * 0 : Stop. +// * 1 : Execute Operation. +// +// ADDR_REG : starting memory address for either AXIS read or write. +// +// LEN_REG : number of samples to be transferred in AXIS read mode. +// +*/ +////////////////////////////////////////////////////////////////////////////// + +module qproc_mem_ctrl # ( + parameter PMEM_AW = 16 , + parameter DMEM_AW = 16 , + parameter WMEM_AW = 16 +)( + // CLK & RST. + input wire ps_clk_i , + input wire ps_rst_ni , +// EXTERNAL MEMORY ACCESS + output wire [1:0] ext_core_sel_o , + output wire [1:0] ext_mem_sel_o , //00-NONE 01-PMEM 10-DMEM 11-WMEM + output wire ext_mem_we_o , + output wire [15:0] ext_mem_addr_o , + output wire [167:0] ext_mem_w_dt_o , + input wire [167:0] ext_mem_r_dt_i , +// AXIS Slave + input wire [255:0] s_axis_tdata_i , + input wire s_axis_tlast_i , + input wire s_axis_tvalid_i, + output wire s_axis_tready_o, +// AXIS Master for sending data. + output wire [255:0] m_axis_tdata_o , + output wire m_axis_tlast_o , + output wire m_axis_tvalid_o, + input wire m_axis_tready_i, +//Control Regiters + input wire [6 :0] MEM_CTRL , + input wire [15:0] MEM_ADDR , + input wire [15:0] MEM_LEN , + input wire [31:0] MEM_DT_I , + output wire [31:0] MEM_DT_O , + output wire [31:0] DEBUG_O ); + +// SIGNALS +wire ar_exec, ar_end ; +wire aw_exec, aw_end ; +wire mem_start, mem_op, mem_source ; +wire [1:0] mem_sel ; +wire mem_we_single, mem_we_axis; +wire [31:0] mem_w_dt_single; +wire [255:0] mem_w_dt_axis; +wire [15:0] mem_w_addr_axis, mem_r_addr_axis ; +wire [15:0] axis_addr, mem_addr_single, ext_mem_addr; +wire [1:0] core_sel; + +assign mem_start = MEM_CTRL[ 0 ] ; // 1-Start Go to 0 For Next +assign mem_op = MEM_CTRL[ 1 ] ; // 0-READ , 1-WRITE +assign mem_sel = MEM_CTRL[3:2] ; // 01-Pmem , 10-Dmem , 11-Wmem +assign mem_source = MEM_CTRL[ 4 ] ; // 0-AXIS, 1-REGISTERS (Single) +assign core_sel = MEM_CTRL[6:5] ; // Core Selection + +wire start_single; +assign start_axis = mem_start & ~mem_source ; +assign start_single = mem_start & mem_source ; + +assign axis_addr = mem_op ? mem_w_addr_axis : mem_r_addr_axis ; +assign ext_mem_addr = mem_source ? mem_addr_single : axis_addr ; + +// Registe-READ ONLY with DMEM +assign dmem_we_single = mem_we_single & mem_sel == 2'b10; + + +// Data AXI-Read Format (From ext_mem_r_dt_i to mem_r_dt_axis ) +wire [255:0] mem_r_dt_axis; + +assign mem_r_dt_axis = (mem_sel == 2'b01)? {184'd0, ext_mem_r_dt_i } : //PMEM + (mem_sel == 2'b10)? {224'd0, ext_mem_r_dt_i }: //DMEM + (mem_sel == 2'b11)? { 80'd0, ext_mem_r_dt_i[167:88],8'd0, ext_mem_r_dt_i[87:0]}: // WMEM + 0; + +// Data AXI-Write Format ( From mem_w_dt_axis TO ext_mem_w_dt_o ) +wire [71 :0] ext_pmem_w_dt; +wire [31 :0] ext_dmem_w_dt; +wire [167:0] ext_wmem_w_dt; + +wire [31 :0] freq, phase, env, gain, lenght, conf; +assign freq = mem_w_dt_axis[ 31 : 0] ; // 32-bit FREQ +assign phase = mem_w_dt_axis[ 63 : 32] ; // 32-bit PHASE +assign env = mem_w_dt_axis[ 95 : 64] ; // 32-bit ENV +assign gain = mem_w_dt_axis[127 : 96] ; // 32-bit GAIN +assign lenght = mem_w_dt_axis[159 :128] ; // 32-bit LENGHT +assign conf = mem_w_dt_axis[191 :160] ; // 32-bit CONF + + +assign ext_pmem_w_dt = mem_w_dt_axis[71:0]; +assign ext_dmem_w_dt = mem_source ? mem_w_dt_single : mem_w_dt_axis[31:0] ; +assign ext_wmem_w_dt = {conf[15:0], lenght, gain, env[23:0], phase, freq} ; + +assign ext_mem_w_dt_o = (mem_sel == 2'b01)? ext_pmem_w_dt : + (mem_sel == 2'b10)? ext_dmem_w_dt : + (mem_sel == 2'b11)? ext_wmem_w_dt : + 0; + + +// OUTPUTS +assign ext_core_sel_o = core_sel; +assign ext_mem_sel_o = mem_sel; +assign ext_mem_we_o = dmem_we_single | mem_we_axis ; +assign ext_mem_addr_o = ext_mem_addr; + + +data_mem_ctrl #( + .N(16) + ) data_mem_ctrl_i ( + .aclk_i ( ps_clk_i ) , + .aresetn_i ( ps_rst_ni ) , + .sel_o ( ) , + .ar_exec_o ( ar_exec ) , + .ar_exec_ack_i ( ar_end ) , + .aw_exec_o ( aw_exec ) , + .aw_exec_ack_i ( aw_end ) , + .busy_o ( busy_o ) , + .mem_op_i ( mem_op ) , + .mem_start_i ( start_axis ) ); + +mem_rw #( + .N( 16 ), + .B( 32 ) +) mem_rw_i ( + .aclk_i ( ps_clk_i ) , + .aresetn_i ( ps_rst_ni ) , + .rw_i ( mem_op ) , + .exec_i ( start_single ) , + .exec_ack_o ( end_single_o ) , + .addr_i ( MEM_ADDR ) , + .di_i ( MEM_DT_I ) , + .do_o ( MEM_DT_O ) , + .mem_we_o ( mem_we_single ) , + .mem_di_o ( mem_w_dt_single ) , + .mem_do_i ( ext_mem_r_dt_i[31:0] ) , + .mem_addr_o ( mem_addr_single ) ); + +axis_read #( + .N( 16 ), + .B( 256 ) +) axis_read_i ( + .aclk_i ( ps_clk_i ) , + .aresetn_i ( ps_rst_ni ) , + .addr_i ( MEM_ADDR ) , + .len_i ( MEM_LEN ) , + .exec_i ( ar_exec ) , + .exec_ack_o ( ar_end ) , + .mem_we_o ( ) , + .mem_addr_o ( mem_r_addr_axis ) , + .mem_do_i ( mem_r_dt_axis ) , + .m_axis_tready_i ( m_axis_tready_i ) , + .m_axis_tdata_o ( m_axis_tdata_o ) , + .m_axis_tlast_o ( m_axis_tlast_o ) , + .m_axis_tvalid_o ( m_axis_tvalid_o ) ); + +axis_write #( + .N( 16 ), + .B( 256 ) +) axis_write_i ( + .aclk_i ( ps_clk_i ) , + .aresetn_i ( ps_rst_ni ) , + .s_axis_tdata_i ( s_axis_tdata_i ) , + .s_axis_tlast_i ( s_axis_tlast_i ) , + .s_axis_tvalid_i ( s_axis_tvalid_i ) , + .s_axis_tready_o ( s_axis_tready_o ) , + .mem_we_o ( mem_we_axis ) , + .mem_di_o ( mem_w_dt_axis ) , + .mem_addr_o ( mem_w_addr_axis ) , + .exec_i ( aw_exec ) , + .exec_ack_o ( aw_end ) , + .addr_i ( MEM_ADDR ) ); + +assign DEBUG_O[31:24] = 8'd0; +assign DEBUG_O[23:16] = {mem_op, core_sel, mem_source,mem_sel, ar_exec, aw_exec} ; +assign DEBUG_O[15:8] = ext_mem_addr [7:0] ; +assign DEBUG_O[7:0] = ext_mem_w_dt_o[7:0] ; + +endmodule diff --git a/firmware/ip/qick_processor/src/qproc_time_ctrl.sv b/firmware/ip/qick_processor/src/qproc_time_ctrl.sv new file mode 100644 index 0000000..6899713 --- /dev/null +++ b/firmware/ip/qick_processor/src/qproc_time_ctrl.sv @@ -0,0 +1,116 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 11-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: + Controls the Time Counter. time_abs_o +*/ +////////////////////////////////////////////////////////////////////////////// + +module qproc_time_ctrl ( + input wire t_clk_i , + input wire t_rst_ni , + input wire time_en_i , // Time RUNS + input wire time_rst_i , // Set Time to 0 + input wire time_init_i , // Set Time to current OFFSET + input wire time_updt_i , // Increment Time updt_dt_i + input wire [31:0] updt_dt_i , + output wire [47:0] time_abs_o ); + +// Time ABS +/////////////////////////////////////////////////////////////////////////////// +reg [47:0] time_abs; + +wire[47:0] time_update_dt; +assign time_update_dt = { { 16{updt_dt_i[31]} } ,updt_dt_i}; //Sign Extend updt_dt_i + + +enum {ST_IDLE, ST_RESET, ST_INIT, ST_LOAD_OFFSET, ST_INCREMENT, ST_UPDATE } ctrl_time_st, ctrl_time_st_nxt; + +////////// Sequential Logic +always @ (posedge t_clk_i) begin : CTRL_SYNC_PROC + if (!t_rst_ni) ctrl_time_st <= ST_IDLE; + else ctrl_time_st <= ctrl_time_st_nxt; +end + +////////// Comb Logic - Outputs and State +reg [47:0] time_inc; +reg [47:0] initial_offset; +wire [47:0] updated_offset ; +reg time_cnt_en, time_c_in; + +wire time_cnt_rst; +assign time_cnt_rst = time_rst_i | time_init_i ; + + +always_comb begin : CTRL_ST_AND_OUTPUT_DECODE + time_cnt_en = 1'b0; + time_inc = 1'b0; + time_c_in = 1'b0; + + ctrl_time_st_nxt = ctrl_time_st; // Default Current State + case (ctrl_time_st) + ST_IDLE : begin + if ( time_rst_i ) ctrl_time_st_nxt = ST_RESET; + else if ( time_init_i ) ctrl_time_st_nxt = ST_INIT; + else if ( time_updt_i ) ctrl_time_st_nxt = ST_UPDATE; + else if ( time_en_i ) ctrl_time_st_nxt = ST_INCREMENT; + end + ST_RESET : begin + if ( time_en_i ) + ctrl_time_st_nxt = ST_INCREMENT; + else + ctrl_time_st_nxt = ST_IDLE; + end + ST_INIT : begin + time_cnt_en = 1'b1; + ctrl_time_st_nxt = ST_LOAD_OFFSET; + end + ST_LOAD_OFFSET : begin + time_cnt_en = 1'b1; + time_inc = updt_dt_i ; + ctrl_time_st_nxt = ST_INCREMENT; + end + ST_INCREMENT : begin + time_cnt_en = 1'b1; + time_inc = 48'd1 ; + if ( time_rst_i ) ctrl_time_st_nxt = ST_RESET; + else if ( time_init_i ) ctrl_time_st_nxt = ST_INIT; + else if ( time_updt_i ) ctrl_time_st_nxt = ST_UPDATE; + else if ( !time_en_i ) ctrl_time_st_nxt = ST_IDLE; + end + ST_UPDATE : begin + time_cnt_en = 1'b1; + time_inc = time_update_dt ; + time_c_in = 1'b1; + ctrl_time_st_nxt = ST_INCREMENT; + end + endcase +end + + +// Time Operation + ADDSUB_MACRO #( + .DEVICE ("7SERIES"), // Target Device: "7SERIES" + .LATENCY ( 1 ), // Desired clock cycle latency, 0-2 + .WIDTH ( 48 ) // Input / output bus width, 1-48 + ) TIME_ADDER ( + .CARRYOUT ( ), // 1-bit carry-out output signal + .RESULT ( time_abs ), // Add/sub result output, width defined by WIDTH parameter + .B ( time_abs ), // Input A bus, width defined by WIDTH parameter + .ADD_SUB ( 1'b1 ), // 1-bit add/sub input, high selects add, low selects subtract + .A ( time_inc ), // Input B bus, width defined by WIDTH parameter + .CARRYIN ( time_c_in ), // 1-bit carry-in input + .CE ( time_cnt_en | time_cnt_rst ), // 1-bit clock enable input + .CLK ( t_clk_i ), // 1-bit clock input + .RST ( time_cnt_rst ) // 1-bit active high synchronous reset + ); + +assign time_abs_o = time_abs; + +endmodule + diff --git a/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.veo b/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.veo new file mode 100644 index 0000000..5653a79 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.veo @@ -0,0 +1,85 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:axi_vip:1.1 +// IP Revision: 14 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +axi_mst_0 your_instance_name ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .m_axi_awaddr(m_axi_awaddr), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid + .m_axi_awready(m_axi_awready), // input wire m_axi_awready + .m_axi_wdata(m_axi_wdata), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb(m_axi_wstrb), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid + .m_axi_wready(m_axi_wready), // input wire m_axi_wready + .m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid + .m_axi_bready(m_axi_bready), // output wire m_axi_bready + .m_axi_araddr(m_axi_araddr), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid + .m_axi_arready(m_axi_arready), // input wire m_axi_arready + .m_axi_rdata(m_axi_rdata), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid + .m_axi_rready(m_axi_rready) // output wire m_axi_rready +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file axi_mst_0.v when simulating +// the core, axi_mst_0. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.vho b/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.vho new file mode 100644 index 0000000..4ca1788 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.vho @@ -0,0 +1,116 @@ +-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of AMD and is protected under U.S. and international copyright +-- and other intellectual property laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- AMD, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) AMD shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or AMD had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- AMD products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of AMD products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. +-- IP VLNV: xilinx.com:ip:axi_vip:1.1 +-- IP Revision: 14 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT axi_mst_0 + PORT ( + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_awvalid : OUT STD_LOGIC; + m_axi_awready : IN STD_LOGIC; + m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_wvalid : OUT STD_LOGIC; + m_axi_wready : IN STD_LOGIC; + m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_bvalid : IN STD_LOGIC; + m_axi_bready : OUT STD_LOGIC; + m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_arvalid : OUT STD_LOGIC; + m_axi_arready : IN STD_LOGIC; + m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_rvalid : IN STD_LOGIC; + m_axi_rready : OUT STD_LOGIC + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : axi_mst_0 + PORT MAP ( + aclk => aclk, + aresetn => aresetn, + m_axi_awaddr => m_axi_awaddr, + m_axi_awprot => m_axi_awprot, + m_axi_awvalid => m_axi_awvalid, + m_axi_awready => m_axi_awready, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_araddr => m_axi_araddr, + m_axi_arprot => m_axi_arprot, + m_axi_arvalid => m_axi_arvalid, + m_axi_arready => m_axi_arready, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_rvalid => m_axi_rvalid, + m_axi_rready => m_axi_rready + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file axi_mst_0.vhd when simulating +-- the core, axi_mst_0. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + + + diff --git a/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.xci b/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..156d86e --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,215 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "axi_mst_0", + "component_reference": "xilinx.com:ip:axi_vip:1.1", + "ip_revision": "14", + "gen_directory": ".", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "axi_mst_0", "resolve_type": "user", "usage": "all" } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ], + "INTERFACE_MODE": [ { "value": "MASTER", "value_src": "user", "resolve_type": "user", "usage": "all" } ], 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Socket + AXIMM Socket for Write + + + xtlm::xtlm_aximm_target_socket + xtlm.h + + + provides + + + tlm + + + name + rd_socket + + + + + + + 1 + + + + + + + C_AXI_PROTOCOL + 2 + + + C_AXI_INTERFACE_MODE + 0 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_WDATA_WIDTH + 32 + + + C_AXI_RDATA_WIDTH + 32 + + + C_AXI_WID_WIDTH + 0 + + + C_AXI_RID_WIDTH + 0 + + + C_AXI_AWUSER_WIDTH + 0 + + + C_AXI_ARUSER_WIDTH + 0 + + + C_AXI_WUSER_WIDTH + 0 + + + C_AXI_RUSER_WIDTH + 0 + + + C_AXI_BUSER_WIDTH + 0 + + + C_AXI_SUPPORTS_NARROW + 0 + + + C_AXI_HAS_BURST + 0 + + + C_AXI_HAS_LOCK + 0 + + + C_AXI_HAS_CACHE + 0 + + + C_AXI_HAS_REGION + 0 + + + C_AXI_HAS_PROT + 1 + + + C_AXI_HAS_QOS + 0 + + + C_AXI_HAS_WSTRB + 1 + + + C_AXI_HAS_BRESP + 1 + + + C_AXI_HAS_RRESP + 1 + + + C_AXI_HAS_ARESETN + 1 + + + + + + choice_list_04fafd91 + AXI3 + AXI4 + AXI4LITE + + + choice_list_6240decd + READ_ONLY + READ_WRITE + WRITE_ONLY + + + choice_list_642e7122 + MASTER + PASS_THROUGH + SLAVE + + + choice_list_99ba8646 + 32 + 64 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_0fc128e8 + 0 + 0 + + + + + xilinx_synthesisconstraints_view_fileset + + axi_mst_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_systemcsimulation_view_fileset + + sysc/axi_vip.h + systemCSource + true + + + sysc/axi_vip.cpp + systemCSource + axi_vip_v1_1_14 + + + sysc/sim_ipc_aximm_master.cpp + systemCSource + axi_vip_v1_1_14 + + + sysc/sim_ipc_aximm_slave.cpp + systemCSource + axi_vip_v1_1_14 + + + sysc/sim_ipc_aximm_master.h + systemCSource + true + axi_vip_v1_1_14 + + + sysc/sim_ipc_aximm_slave.h + systemCSource + true + axi_vip_v1_1_14 + + + + xilinx_systemcsimulationwrapper_view_fileset + + sim/axi_mst_0_sc.h + systemCSource + true + + + sim/axi_mst_0_sc.cpp + systemCSource + + + sim/axi_mst_0.h + systemCSource + true + + + sim/axi_mst_0.cpp + systemCSource + + + sim/axi_mst_0_stub.sv + systemVerilogSource + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + sim/axi_mst_0_pkg.sv + systemVerilogSource + + + hdl/axi_vip_v1_1_vl_rfs.sv + systemVerilogSource + USED_IN_ipstatic + axi_vip_v1_1_14 + + + + xilinx_veriloginstantiationtemplate_view_fileset + + axi_mst_0.vho + vhdlTemplate + + + axi_mst_0.veo + verilogTemplate + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + hdl/axi_infrastructure_v1_1_0.vh + verilogSource + true + axi_infrastructure_v1_1_0 + + + hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/axi_vip_v1_1_vlsyn_rfs.sv + systemVerilogSource + axi_vip_v1_1_14 + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/axi_mst_0.sv + systemVerilogSource + xil_defaultlib + + + + xilinx_versioninformation_view_fileset + + doc/axi_vip_v1_1_changelog.txt + text + axi_vip_v1_1_14 + + + + The AXI Verification IP. + + + Component_Name + Component Name + axi_mst_0 + + + PROTOCOL + PROTOCOL + AXI4LITE + + + READ_WRITE_MODE + READ_WRITE MODE + READ_WRITE + + + INTERFACE_MODE + INTERFACE MODE + MASTER + + + ADDR_WIDTH + ADDRESS WIDTH + 32 + + + DATA_WIDTH + DATA WIDTH + 32 + + + ID_WIDTH + ID WIDTH + 0 + + + + false + + + + + + AWUSER_WIDTH + AWUSER WIDTH + 0 + + + + false + + + + + + ARUSER_WIDTH + ARUSER WIDTH + 0 + + + + false + + + + + + RUSER_WIDTH + RUSER WIDTH + 0 + + + + false + + + + + + WUSER_WIDTH + WUSER WIDTH + 0 + + + + false + + + + + + BUSER_WIDTH + BUSER WIDTH + 0 + + + + false + + + + + + WUSER_BITS_PER_BYTE + WUSER BITS PER BYTE + 0 + + + + false + + + + + + RUSER_BITS_PER_BYTE + RUSER BITS PER BYTE + 0 + + + + false + + + + + + HAS_USER_BITS_PER_BYTE + HAS USER_BITS_PER_BYTE + 0 + + + + false + + + + + + SUPPORTS_NARROW + SUPPORTS NARROW + 0 + + + + false + + + + + + HAS_SIZE + HAS SIZE + 0 + + + + false + + + + + + HAS_BURST + HAS BURST + 0 + + + + false + + + + + + HAS_LOCK + HAS LOCK + 0 + + + + false + + + + + + HAS_CACHE + HAS CACHE + 0 + + + + false + + + + + + HAS_REGION + HAS REGION + 0 + + + + false + + + + + + HAS_QOS + HAS QOS + 0 + + + + false + + + + + + HAS_PROT + HAS PROT + 1 + + + HAS_WSTRB + HAS WSTRB + 1 + + + HAS_BRESP + HAS BRESP + 1 + + + HAS_RRESP + HAS RRESP + 1 + + + HAS_ACLKEN + HAS ACLKEN + 0 + + + HAS_ARESETN + HAS ARESETN + 1 + + + VIP_PKG_NAME + VIP_PKG_NAME + 0 + + + + + AXI Verification IP + + xtlm + xtlm_ipc_v1_0 + protobuf + + 14 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2023.1 + + + + + + + + + + diff --git a/firmware/ip/qick_processor/src/tb/dmem_issue35.mem b/firmware/ip/qick_processor/src/tb/dmem_issue35.mem new file mode 100644 index 0000000..5b9462d --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/dmem_issue35.mem @@ -0,0 +1,2 @@ +// DMEM content +00000000 diff --git a/firmware/ip/qick_processor/src/tb/prog.bin b/firmware/ip/qick_processor/src/tb/prog.bin new file mode 100644 index 0000000..7c3e521 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/prog.bin @@ -0,0 +1,32 @@ +// TPROC Program Memory File +//H_ADF__CND__S_T_F_WR_OP___| immAddr/rsA0__Port/rsA1_| rsD0__ rsD1__ ImmData__| rDest +000_000__000__0_0_0_00_00___00000___000000__000000____0_0000000__0_0000000__0000000000000000__0000000 //NOP +100_011__000__11__0_00_00______00000000000__000000__________00000000000000001111111111000010__0000001 //REG_WR +100_011__000__11__0_00_00______00000000000__000000__________00000000000000000000001011010000__0100001 //REG_WR +100_011__000__11__0_00_00______00000000000__000000__________00000000000000000000000000110000__0000010 //REG_WR +100_010__000__00__1__0000______00000000000__000000____0_0000000_____000000000000000000001010__0100000 //REG_WR +100_010__000__00__0__1100______00000000000__000000____0_0000001_____000000000000000000000000__0101110 //REG_WR +010_001__000___010___0000___00000___000000__000000____0_0101110__0_0100001__0000000000000000__0000000 //ARITH +000_000__000__0_0_0_00_00___00000___000000__000000____0_0000000__0_0000000__0000000000000000__0000000 //NOP +000_000__000__0_0_0_00_00___00000___000000__000000____0_0000000__0_0000000__0000000000000000__0000000 //NOP +000_000__000__0_0_0_00_00___00000___000000__000000____0_0000000__0_0000000__0000000000000000__0000000 //NOP +000_000__000__0_0_0_00_00___00000___000000__000000____0_0000000__0_0000000__0000000000000000__0000000 //NOP +000_000__000__0_0_0_00_00___00000___000000__000000____0_0000000__0_0000000__0000000000000000__0000000 //NOP +100_010__000__00__0__1010______00000000000__000000____0_0000011_____000000000000000000000000__0101111 //REG_WR +101_001__000__0_0_0_00_00___00000___100000__000000____0_0101111__0_0000000__0000000000000000__0000000 //DMEM_WR +001_110__011__00__1_10_01_______00000000101_000000____0_0100000_____000000000000000000000001__0100000 //JUMP +001_111__000__10__0_00_00_______00000011010_000000__________00000000000000000000000000000000__0000000 //CALL +100_011__000__11__0_00_00______00000000000__000000__________00000000000000001111111111100001__0000001 //REG_WR +100_011__000__11__0_00_00______00000000000__000000__________00000000000000000000001011010000__0100001 //REG_WR +100_011__000__11__0_00_00______00000000000__000000__________00000000000000000000000000110000__0000010 //REG_WR +100_010__000__00__1__0000______00000000000__000000____0_0000000_____000000000000000000001010__0100000 //REG_WR +100_010__000__00__0__0100______00000000000__000000____0_0000001_____000000000111111111111111__0101110 //REG_WR +010_001__000___010___0000___00000___000000__000000____0_0101110__0_0100001__0000000000000000__0000000 //ARITH +001_111__110__00__0_00_00_______00000010110_000000__________00000000000000000000000000000000__0000000 //JUMP +101_010__000__0_0_0_00_11___00000___100000__000000____0_0000011_____000000000000000000001111__0000000 //DMEM_WR +001_110__011__00__1_10_01_______00000010100_000000____0_0100000_____000000000000000000000001__0100000 //JUMP +001_111__000__00__0_00_00_______00000011001_000000__________00000000000000000000000000000000__0000000 //JUMP +100_010__000__00__1__0000______00000000000__000000____0_0000000_____000000000000000000001010__0100000 //REG_WR +101_011__000__0_1_0_00_00___00000___100000__000000__________00000000000000000000000000000000__0000000 //DMEM_WR +001_110__011__00__1_10_01_______00000011011_000000____0_0100000_____000000000000000000000001__0100000 //JUMP +001_011__000__11__0_00_00_______00000000000_000000__________00000000000000000000000000000000__0000000 //RET diff --git a/firmware/ip/qick_processor/src/tb/prog_issue35.mem b/firmware/ip/qick_processor/src/tb/prog_issue35.mem new file mode 100644 index 0000000..335f88c --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/prog_issue35.mem @@ -0,0 +1,36 @@ +// PMEM content +000000000000000000 +8c600000000000000c +8c600000000000000e +dcc001040000000000 +4c080000000000c000 +8c6000000000000020 +8c600000000000398e +dd8000300000000000 +dd8000348000000000 +dd8000350000000000 +88000000070000050e +dd8000100000000000 +dd8000148000000000 +dd8000150000000000 +8c600000000000000e +dcc000000000000000 +dcc000200000000000 +dcc000400000000000 +8c6000000000004d0e +dcc000600000000000 +8c600000000000998e +dcc000800000000000 +8c600000000000e68e +dcc000a00000000000 +dcc000c00000000000 +dcc000e00000000000 +8c600000000001330e +dcc000600000000000 +08110000058001a180 +39110380058001a180 +4c0800000000020680 +88000000060000008c +081100001000000000 +398800c010000000a0 +3c0004400000000000 diff --git a/firmware/ip/qick_processor/src/tb/tb_axis_qick_processor.sv b/firmware/ip/qick_processor/src/tb/tb_axis_qick_processor.sv new file mode 100644 index 0000000..2fa530d --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/tb_axis_qick_processor.sv @@ -0,0 +1,1018 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: +Test Bench for Qick Processor Testing +*/ +////////////////////////////////////////////////////////////////////////////// + +`include "_qproc_defines.svh" + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + + + +//`define T_TCLK 1.953125 // Half Clock Period for Simulation +`define T_TCLK 1.302 // Half Clock Period for Simulation +`define T_CCLK 2.5 // Half Clock Period for Simulation +`define T_SCLK 5 // Half Clock Period for Simulation + + +`define GEN_SYNC 1 +`define DUAL_CORE 0 +`define IO_CTRL 0 +`define DEBUG 3 +`define TNET 0 +`define QCOM 0 +`define CUSTOM_PERIPH 1 +`define LFSR 1 +`define DIVIDER 1 +`define ARITH 1 +`define TIME_READ 1 +`define FIFO_DEPTH 9 +`define PMEM_AW 8 +`define DMEM_AW 10 +`define WMEM_AW 4 +`define REG_AW 4 +`define IN_PORT_QTY 2 +`define OUT_TRIG_QTY 8 +`define OUT_DPORT_QTY 1 +`define OUT_DPORT_DW 4 +`define OUT_WPORT_QTY 3 + + +module tb_axis_qick_processor (); + +/////////////////////////////////////////////////////////////////////////////// + + + +//wire [31:0] port_data_o [`OUT_WPORT_QTY] ; +//wire m_axis_tvalid [`OUT_WPORT_QTY] ; +//wire m_axis_tdata [`OUT_WPORT_QTY] ; + + +// VIP Agent +axi_mst_0_mst_t axi_mst_0_agent; +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +xil_axi_resp_t resp; +//AXI-LITE +//wire s_axi_aclk ; +wire s_ps_dma_aresetn ; +wire [7:0] s_axi_awaddr ; +wire [2:0] s_axi_awprot ; +wire s_axi_awvalid ; +wire s_axi_awready ; +wire [31:0] s_axi_wdata ; +wire [3:0] s_axi_wstrb ; +wire [3:0] s_axi_wstrb ; +wire s_axi_wvalid ; +wire s_axi_wready ; +wire [1:0] s_axi_bresp ; +wire s_axi_bvalid ; +wire s_axi_bready ; +wire [7:0] s_axi_araddr ; +wire [2:0] s_axi_arprot ; +wire s_axi_arvalid ; +wire s_axi_arready ; +wire [31:0] s_axi_rdata ; +wire [1:0] s_axi_rresp ; +wire s_axi_rvalid ; +wire s_axi_rready ; + +////////////////////////////////////////////////////////////////////////// +// CLK Generation +reg c_clk, t_clk, s_ps_dma_aclk, rst_ni; + +initial begin + t_clk = 1'b0; + forever # (`T_TCLK) t_clk = ~t_clk; +end + +initial begin + c_clk = 1'b0; + forever # (`T_CCLK) c_clk = ~c_clk; +end + +initial begin + s_ps_dma_aclk = 1'b0; + #0.5 + forever # (`T_SCLK) s_ps_dma_aclk = ~s_ps_dma_aclk; +end + + assign s_ps_dma_aresetn = rst_ni; + + + + + +reg [255:0] max_value ; +reg axis_dma_start ; + + + + +reg [255 :0] s_dma_axis_tdata_i ; +reg s_dma_axis_tlast_i ; +reg s_dma_axis_tvalid_i ; +reg m_dma_axis_tready_i ; +wire [63 :0] port_0_dt_i ; +reg [63 :0] port_1_dt_i ; +reg s_axi_aclk ; +reg s_axi_aresetn ; + + + +reg axis_aclk ; +reg axis_aresetn ; +reg m0_axis_tready =0 ; +reg m1_axis_tready =0 ; +reg m2_axis_tready =0 ; +reg m3_axis_tready =0 ; +reg m4_axis_tready =0 ; +reg m5_axis_tready =0 ; +reg m6_axis_tready =0 ; +reg m7_axis_tready =0 ; + +wire s_dma_axis_tready_o ; +wire [255 :0] m_dma_axis_tdata_o ; +wire m_dma_axis_tlast_o ; +wire m_dma_axis_tvalid_o ; + +wire [167:0] m0_axis_tdata ; +wire m0_axis_tvalid ; +wire [167:0] m1_axis_tdata ; +wire m1_axis_tvalid ; +wire [167:0] m2_axis_tdata ; +wire m2_axis_tvalid ; +wire [167:0] m3_axis_tdata ; +wire m3_axis_tvalid ; +wire [167:0] m4_axis_tdata ; +wire m4_axis_tvalid ; +wire [167:0] m5_axis_tdata ; +wire m5_axis_tvalid ; +wire [167:0] m6_axis_tdata ; +wire m6_axis_tvalid ; +wire [167:0] m7_axis_tdata ; +wire m7_axis_tvalid ; +wire [`OUT_DPORT_DW-1:0] port_0_dt_o, port_1_dt_o, port_2_dt_o, port_3_dt_o ; + +wire qnet_en_o ; +wire [4 :0] qnet_op_o ; +wire [31:0] qnet_a_dt_o ; +wire [31:0] qnet_b_dt_o ; +wire [31:0] qnet_c_dt_o ; +wire [31:0] qnet_d_dt_o ; +reg qnet_rdy_i ; +reg [31 :0] qnet_dt_i [2] ; +reg [31 :0] qcom_dt_i [2] ; +reg [31 :0] qp1_dt_i [2] ; +reg [31 :0] qp2_dt_i [2] ; + +wire periph_en_o ; +wire [4 :0] periph_op_o ; +wire [31:0] periph_a_dt_o ; +wire [31:0] periph_b_dt_o ; +wire [31:0] periph_c_dt_o ; +wire [31:0] periph_d_dt_o ; +reg periph_rdy_i ; +reg [31 :0] periph_dt_i [2] ; + + +reg s0_axis_tvalid , s1_axis_tvalid ; +reg [15:0] waves, wtime; +reg [31:0] axi_dt; + + +int val_A, val_B, val_C, val_D, result ; +reg [31:0] result_r, result_2r, result_3r ; + +always_ff @ (posedge c_clk) begin + result_r <= result; + result_2r <= result_r; + result_3r <= result_2r; +end + +// Register ADDRESS +parameter REG_TPROC_CTRL = 0 * 4 ; +parameter REG_TPROC_CFG = 1 * 4 ; +parameter REG_MEM_ADDR = 2 * 4 ; +parameter REG_MEM_LEN = 3 * 4 ; +parameter REG_MEM_DT_I = 4 * 4 ; +parameter REG_AXI_W_DT1 = 5 * 4 ; +parameter REG_AXI_W_DT2 = 6 * 4 ; +parameter REG_CORE_CFG = 7 * 4 ; +parameter REG_AXI_DT_SRC = 8 * 4 ; +parameter REG_MEM_DT_O = 10 * 4 ; +parameter REG_AXI_R_DT1 = 11 * 4 ; +parameter REG_AXI_R_DT2 = 12 * 4 ; +parameter REG_TIME_USR = 13 * 4 ; +parameter REG_TPROC_STATUS = 14 * 4 ; +parameter REG_TPROC_DEBUG = 15 * 4 ; + + + +axi_mst_0 axi_mst_0_i + ( + .aclk (s_ps_dma_aclk ), + .aresetn (s_ps_dma_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + + +reg proc_start_i, proc_stop_i ; +reg core_start_i, core_stop_i ; +reg time_rst_i, time_init_i, time_updt_i; + +reg [47:0] offset_dt_i ; +wire [47:0] t_time_abs_o ; +reg time_updt_i; + +wire [31:0] ps_debug_do; + +reg qp1_en_r; +reg [31:0] qp1_a_dt_r, qp1_b_dt_r; +wire [31:0] qp1_a_dt_o, qp1_b_dt_o, qp1_c_dt_o, qp1_d_dt_o; +always_ff @ (posedge c_clk) begin + qp1_en_r <= qp1_en_o; + qp1_a_dt_r <= qp1_a_dt_o; + qp1_b_dt_r <= qp1_b_dt_o; +end + +assign qp1_rdy_i = ~qp1_en_r; +assign qp1_dt_i[0] = qp1_a_dt_r; +assign qp1_dt_i[1] = qp1_b_dt_r; +assign qp1_vld_i = qp1_en_r ; + + +axis_qick_processor # ( + .DUAL_CORE ( `DUAL_CORE ) , + .GEN_SYNC ( `GEN_SYNC ) , + .IO_CTRL ( `IO_CTRL ) , + .DEBUG ( `DEBUG ) , + .TNET ( `TNET ) , + .QCOM ( `QCOM ) , + .CUSTOM_PERIPH ( `CUSTOM_PERIPH ) , + .LFSR ( `LFSR ) , + .DIVIDER ( `DIVIDER ) , + .ARITH ( `ARITH ) , + .TIME_READ ( `TIME_READ ) , + .FIFO_DEPTH ( `FIFO_DEPTH ) , + .PMEM_AW ( `PMEM_AW ) , + .DMEM_AW ( `DMEM_AW ) , + .WMEM_AW ( `WMEM_AW ) , + .REG_AW ( `REG_AW ) , + .IN_PORT_QTY ( `IN_PORT_QTY ) , + .OUT_TRIG_QTY ( `OUT_TRIG_QTY ) , + .OUT_DPORT_QTY ( `OUT_DPORT_QTY ) , + .OUT_DPORT_DW ( `OUT_DPORT_DW ) , + .OUT_WPORT_QTY ( `OUT_WPORT_QTY ) +) AXIS_QPROC ( + .t_clk_i ( t_clk ) , + .t_resetn ( rst_ni ) , + .c_clk_i ( c_clk ) , + .c_resetn ( rst_ni ) , + .ps_clk_i ( s_ps_dma_aclk ) , + .ps_resetn ( s_ps_dma_aresetn ) , + .ext_flag_i ( ext_flag_i ) , + .proc_start_i ( proc_start_i ) , + .proc_stop_i ( proc_stop_i ) , + .core_start_i ( core_start_i ) , + .core_stop_i ( core_stop_i ) , + .time_rst_i ( time_rst_i ) , + .time_init_i ( time_init_i ) , + .time_updt_i ( time_updt_i ) , + .time_dt_i ( offset_dt_i ) , + .t_time_abs_o ( t_time_abs_o ) , + .ps_debug_do ( ps_debug_do ) , + + .qnet_en_o ( qnet_en_o ) , + .qnet_op_o ( qnet_op_o ) , + .qnet_a_dt_o ( qnet_a_dt_o ) , + .qnet_b_dt_o ( qnet_b_dt_o ) , + .qnet_c_dt_o ( qnet_c_dt_o ) , + .qnet_rdy_i ( qnet_rdy_i ) , + .qnet_dt1_i ( qnet_dt_i[0] ) , + .qnet_dt2_i ( qnet_dt_i[1] ) , + .qnet_vld_i ( qnet_vld_i ) , + .qnet_flag_i ( qnet_flag_i ) , + + .qcom_en_o ( qcom_en_o ) , + .qcom_op_o ( qcom_op_o ) , + .qcom_dt_o ( qcom_dt_o ) , + .qcom_rdy_i ( qcom_rdy_i ) , + .qcom_dt1_i ( qcom_dt_i[0] ) , + .qcom_dt2_i ( qcom_dt_i[1] ) , + .qcom_vld_i ( qcom_vld_i ) , + .qcom_flag_i ( qcom_flag_i ) , + + .qp1_en_o ( qp1_en_o ) , + .qp1_op_o ( qp1_op_o ) , + .qp1_a_dt_o ( qp1_a_dt_o ) , + .qp1_b_dt_o ( qp1_b_dt_o ) , + .qp1_c_dt_o ( qp1_c_dt_o ) , + .qp1_d_dt_o ( qp1_d_dt_o ) , + .qp1_rdy_i ( qp1_rdy_i ) , + .qp1_dt1_i ( qp1_dt_i[0] ) , + .qp1_dt2_i ( qp1_dt_i[1] ) , + .qp1_vld_i ( qp1_vld_i ) , + .qp1_flag_i ( qp1_flag_i ) , + + .qp2_en_o ( qp2_en_o ) , + .qp2_op_o ( qp2_op_o ) , + .qp2_a_dt_o ( qp2_a_dt_o ) , + .qp2_b_dt_o ( qp2_b_dt_o ) , + .qp2_c_dt_o ( qp2_c_dt_o ) , + .qp2_d_dt_o ( qp2_d_dt_o ) , + .qp2_rdy_i ( qpb_rdy_i ) , + .qp2_dt1_i ( qp2_dt_i[0] ) , + .qp2_dt2_i ( qp2_dt_i[1] ) , + .qp2_vld_i ( qp2_vld_i ) , + + .s_dma_axis_tdata_i ( s_dma_axis_tdata_i ) , + .s_dma_axis_tlast_i ( s_dma_axis_tlast_i ) , + .s_dma_axis_tvalid_i ( s_dma_axis_tvalid_i ) , + .s_dma_axis_tready_o ( s_dma_axis_tready_o ) , + .m_dma_axis_tdata_o ( m_dma_axis_tdata_o ) , + .m_dma_axis_tlast_o ( m_dma_axis_tlast_o ) , + .m_dma_axis_tvalid_o ( m_dma_axis_tvalid_o ) , + .m_dma_axis_tready_i ( m_dma_axis_tready_i ) , + .s0_axis_tdata ( port_0_dt_i ) , + .s0_axis_tvalid ( port_0_vld ) , + .s1_axis_tdata ( port_1_dt_i ) , + .s1_axis_tvalid ( s1_axis_tvalid ) , + .s2_axis_tdata ( 64'd2 ) , + .s2_axis_tvalid ( 1'b0 ) , + .s3_axis_tdata ( 64'd3 ) , + .s3_axis_tvalid ( 1'b0 ) , + .s4_axis_tdata ( 64'd4 ) , + .s4_axis_tvalid ( 1'b0 ) , + .s5_axis_tdata ( 64'd5 ) , + .s5_axis_tvalid ( 1'b0 ) , + .s6_axis_tdata ( 64'd6 ) , + .s6_axis_tvalid ( 1'b0 ) , + .s7_axis_tdata ( 64'd7 ) , + .s7_axis_tvalid ( 1'b0 ) , + .s_axi_awaddr ( s_axi_awaddr[7:0] ) , + .s_axi_awprot ( s_axi_awprot ) , + .s_axi_awvalid ( s_axi_awvalid ) , + .s_axi_awready ( s_axi_awready ) , + .s_axi_wdata ( s_axi_wdata ) , + .s_axi_wstrb ( s_axi_wstrb ) , + .s_axi_wvalid ( s_axi_wvalid ) , + .s_axi_wready ( s_axi_wready ) , + .s_axi_bresp ( s_axi_bresp ) , + .s_axi_bvalid ( s_axi_bvalid ) , + .s_axi_bready ( s_axi_bready ) , + .s_axi_araddr ( s_axi_araddr[7:0] ) , + .s_axi_arprot ( s_axi_arprot ) , + .s_axi_arvalid ( s_axi_arvalid ) , + .s_axi_arready ( s_axi_arready ) , + .s_axi_rdata ( s_axi_rdata ) , + .s_axi_rresp ( s_axi_rresp ) , + .s_axi_rvalid ( s_axi_rvalid ) , + .s_axi_rready ( s_axi_rready ) , + .m0_axis_tdata ( m0_axis_tdata ) , + .m0_axis_tvalid ( m0_axis_tvalid ) , + .m0_axis_tready ( m0_axis_tready ) , + .m1_axis_tdata ( m1_axis_tdata ) , + .m1_axis_tvalid ( m1_axis_tvalid ) , + .m1_axis_tready ( m1_axis_tready ) , + .m2_axis_tdata ( m2_axis_tdata ) , + .m2_axis_tvalid ( m2_axis_tvalid ) , + .m2_axis_tready ( m2_axis_tready ) , + .m3_axis_tdata ( m3_axis_tdata ) , + .m3_axis_tvalid ( m3_axis_tvalid ) , + .m3_axis_tready ( m3_axis_tready ) , + .m4_axis_tdata ( m4_axis_tdata ) , + .m4_axis_tvalid ( m4_axis_tvalid ) , + .m4_axis_tready ( m4_axis_tready ) , + .m5_axis_tdata ( m5_axis_tdata ) , + .m5_axis_tvalid ( m5_axis_tvalid ) , + .m5_axis_tready ( m5_axis_tready ) , + .m6_axis_tdata ( m6_axis_tdata ) , + .m6_axis_tvalid ( m6_axis_tvalid ) , + .m6_axis_tready ( m6_axis_tready ) , + .m7_axis_tdata ( m7_axis_tdata ) , + .m7_axis_tvalid ( m7_axis_tvalid ) , + .m7_axis_tready ( m7_axis_tready ) , + .port_0_dt_o ( port_0_dt_o ) , + .port_1_dt_o ( port_1_dt_o ) , + .port_2_dt_o ( port_2_dt_o ) , + .port_3_dt_o ( port_3_dt_o ) ); + +wire port_0_vld, qnet_vld_i, qnet_flag_i, periph_flag_i, ext_flag_i; +assign port_0_dt_i = port_1_dt_o; +assign port_0_vld = port_0_dt_o[0]; +assign qnet_vld_i = t_time_abs_o[3]&t_time_abs_o[2]&t_time_abs_o[1] ; +assign qnet_flag_i = ~t_time_abs_o[5] & ~t_time_abs_o[4] & t_time_abs_o[3] ; +assign periph_flag_i = ~t_time_abs_o[5] & t_time_abs_o[4] & t_time_abs_o[3] ; +assign ext_flag_i = t_time_abs_o[5] & t_time_abs_o[4] & t_time_abs_o[3] ; + +reg periph_vld_i ; +reg qcom_rdy_i, qpb_rdy_i; + +initial begin + + $display("*** Start Test ***"); + + $display("AXI_WDATA_WIDTH %d", `AXI_WDATA_WIDTH); + + $display("LFSR %d", `LFSR); + $display("DIVIDER %d", `DIVIDER); + $display("ARITH %d", `ARITH); + $display("TIME_READ %d", `TIME_READ); + + $display("DMEM_AW %d", `DMEM_AW); + $display("WMEM_AW %d", `WMEM_AW); + $display("REG_AW %d", `REG_AW); + $display("IN_PORT_QTY %d", `IN_PORT_QTY); + $display("OUT_DPORT_QTY %d", `OUT_DPORT_QTY); + $display("OUT_WPORT_QTY %d", `OUT_WPORT_QTY); + + + AXIS_QPROC.QPROC.CORE_0.CORE_MEM.D_MEM.RAM = '{default:'0} ; + AXIS_QPROC.QPROC.CORE_0.CORE_MEM.W_MEM.RAM = '{default:'0} ; + AXIS_QPROC.QPROC.DISPATCHER.TRIG_FIFO[0].trig_fifo_inst.fifo_mem.RAM = '{default:'0} ; + AXIS_QPROC.QPROC.DISPATCHER.DATA_FIFO[0].data_fifo_inst.fifo_mem.RAM = '{default:'0} ; + AXIS_QPROC.QPROC.DISPATCHER.WAVE_FIFO[0].wave_fifo_inst.fifo_mem.RAM = '{default:'0} ; + + //AXIS_QPROC.QPROC.TRIG_FIFO[0].trig_fifo_inst.fifo_mem.RAM = '{default:'0} ; + //AXIS_QPROC.QPROC.DATA_FIFO[0].data_fifo_inst.fifo_mem.RAM = '{default:'0} ; + //AXIS_QPROC.QPROC.WAVE_FIFO[0].wave_fifo_inst.fifo_mem.RAM = '{default:'0} ; + + //AXIS_QPROC.QPROC.WAVE_FIFO[1].wave_fifo_inst.fifo_mem.RAM = '{default:'0} ; + //AXIS_QPROC.QPROC.WAVE_FIFO[2].wave_fifo_inst.fifo_mem.RAM = '{default:'0} ; + //AXIS_QPROC.QPROC.WAVE_FIFO[3].wave_fifo_inst.fifo_mem.RAM = '{default:'0} ; + //AXIS_QPROC.QPROC.WAVE_FIFO[4].wave_fifo_inst.fifo_mem.RAM = '{default:'0} ; + //AXIS_QPROC.QPROC.DATA_FIFO[1].data_fifo_inst.fifo_mem.RAM = '{default:'0} ; + + + //$readmemb("/home/mdifeder/repos/qick-spin/firmware/ip/qick_processor/src/tb/prog.bin", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.P_MEM.RAM); + //$readmemb("/home/mdifeder/repos/qick-spin/firmware/ip/qick_processor/src/tb/wave.bin", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.W_MEM.RAM); +// $readmemb("/home/mdifeder/IPs/qick_processor/src/tb/prog.bin", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.P_MEM.RAM); + $readmemb("prog.bin", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.P_MEM.RAM); + //$readmemb("/home/mdifeder/IPs/qick_processor/src/tb/wave.bin", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.W_MEM.RAM); + $readmemb("wave.bin", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.W_MEM.RAM); + + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb_axis_qick_processor.axi_mst_0_i.inst.IF); + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + // Start agents. + axi_mst_0_agent.start_master(); + + +// INITIAL VALUES + + qnet_dt_i = '{default:'0} ; + rst_ni = 1'b0; + axi_dt = 0 ; + axis_dma_start = 1'b0; + s1_axis_tvalid = 1'b0 ; + port_1_dt_i = 0; + qcom_rdy_i = 0 ; + qpb_rdy_i = 0 ; + periph_dt_i = {0,0} ; + qnet_rdy_i = 0 ; + qnet_dt_i [2] = {0,0} ; + proc_start_i = 1'b0; + proc_stop_i = 1'b0; + core_start_i = 1'b0; + core_stop_i = 1'b0; + time_rst_i = 1'b0; + time_init_i = 1'b0; + time_updt_i = 1'b0; + offset_dt_i = 0 ; + periph_vld_i = 1'b0; + + m_dma_axis_tready_i = 1'b1; + max_value = 0; + #10; + repeat(16) @ (posedge s_ps_dma_aclk); #0.1; + rst_ni = 1'b1; + #10; + + + WRITE_AXI( REG_TPROC_CTRL , 4); //PROC_START + #1000; + WRITE_AXI( REG_TPROC_CTRL , 16); //CORE_START + #1000; + WRITE_AXI( REG_TPROC_CTRL , 128); //PROC_RUN + #900; + + force tb_axis_qick_processor.AXIS_QPROC.QPROC.DISPATCHER.some_fifo_full = 1'b1; + #100ns; + force tb_axis_qick_processor.AXIS_QPROC.QPROC.DISPATCHER.some_fifo_full = 1'b0; + + #1000; + + +// TEST_AXI (); + //TEST_SINGLE_READ_AXI(); + // TEST_DMA_AXI (); + //TEST_SINGLE_READ_AXI(); + +// WRITE_AXI( REG_TPROC_CFG , 512); //DISABLE NET CTRL NOTHING HAPPENS +// TEST_STATES(); +// // +// WRITE_AXI( REG_TPROC_CFG , 0); //DISABLE NET CTRL ONLY NET COMMANDS +// TEST_STATES(); +// // +// WRITE_AXI( REG_TPROC_CFG , 1536); //ENABLE IO ONLY IO COMMANDS +// TEST_STATES(); +// // +// WRITE_AXI( REG_TPROC_CFG , 1024); //ENABLE IO ENABLE NET +// TEST_STATES(); + +// WRITE_AXI( REG_CORE_CFG , 2); //LFSR CHange when READ + + +// //#100; +// //@ (posedge t_clk); #0.1; +//// proc_start_i = 1'b1; +//// @ (posedge t_clk); #0.1; +//// proc_start_i = 1'b0; + +// WRITE_AXI( REG_TPROC_CFG, 1024); //ENABLE EXTERNAL CONTROL + + +// #100; +// @ (posedge c_clk); #0.1; +// proc_start_i = 1'b1; +// @ (posedge c_clk); #0.1; +// proc_start_i = 1'b0; + + +// WRITE_AXI( REG_TPROC_CTRL , 8192); //SET_FLAG +// WRITE_AXI( REG_TPROC_CTRL , 16384); //CLR_FLAG +// WRITE_AXI( REG_TPROC_CTRL , 8192); //SET_FLAG +// WRITE_AXI( REG_TPROC_CTRL , 16384); //CLR_FLAG +// WRITE_AXI( REG_TPROC_CTRL , 8192); //SET_FLAG +// WRITE_AXI( REG_TPROC_CTRL , 16384); //CLR_FLAG + +// #1000; + +/* +// CONFIGURE LFSR + @ (posedge s_ps_dma_aclk); #0.1; + WRITE_AXI( REG_TPROC_W_DT1 , 4); // + WRITE_AXI( REG_TPROC_W_DT2 , 10); // + WRITE_AXI( REG_CORE_CFG, 1); //LFSR FREE RUN + WRITE_AXI( REG_CORE_CFG, 2); //LFSR LAST + WRITE_AXI( REG_TPROC_CTRL , 4); //START + + + WRITE_AXI( REG_READ_SEL, 0); //SELECT READ + WRITE_AXI( REG_READ_SEL, 1); //SELECT READ + WRITE_AXI( REG_READ_SEL, 2); //SELECT READ + WRITE_AXI( REG_READ_SEL, 3); //SELECT READ + WRITE_AXI( REG_READ_SEL, 4); //SELECT READ + WRITE_AXI( REG_READ_SEL, 5); //SELECT READ + WRITE_AXI( REG_READ_SEL, 6); //SELECT READ + WRITE_AXI( REG_READ_SEL, 7); //SELECT READ + WRITE_AXI( REG_READ_SEL, 8); //SELECT READ + WRITE_AXI( REG_READ_SEL, 1); //SELECT READ + + #1000; +// WRITE_AXI( REG_TPROC_CTRL , 8); //STOP + WRITE_AXI( REG_TPROC_CTRL , 4); //START + #1000; + WRITE_AXI( REG_TPROC_CTRL , 4); //START + #1000; + WRITE_AXI( REG_TPROC_CTRL , 4); //START + #1000; + + //WRITE_AXI( REG_TPROC_CFG , 6144); //CONTINUE IF FULL + // PROCESSOR START + WRITE_AXI( REG_TPROC_W_DT1 , 4); // + WRITE_AXI( REG_TPROC_W_DT2 , 10); // + WRITE_AXI( REG_TPROC_CTRL , 8192); //COND_SET +// PORT DATA IN + @ (posedge c_clk); #0.1; + s1_axis_tvalid = 1'b1 ; + port_1_dt_i = 13; + @ (posedge c_clk); #0.1; + s1_axis_tvalid = 1'b0 ; + port_1_dt_i = 0; + #25; +*/ + + + $display("*** End Test ***"); + $finish(); +end + + +integer DATA_RD; + +/// DMA SIMULATOR +always_ff @(posedge s_ps_dma_aclk) begin + if (axis_dma_start) begin + if (s_dma_axis_tdata_i < axis_dma_len ) begin + s_dma_axis_tdata_i <= s_dma_axis_tdata_i + 1'b1 ; + s_dma_axis_tvalid_i <= 1; + end else if (s_dma_axis_tdata_i == axis_dma_len ) begin + s_dma_axis_tdata_i <= s_dma_axis_tdata_i + 1'b1 ; + s_dma_axis_tlast_i <= 1'b1; + s_dma_axis_tvalid_i <= 1'b1; + end else begin + s_dma_axis_tdata_i <= 0 ; + s_dma_axis_tlast_i <= 0 ; + s_dma_axis_tvalid_i <= 0 ; + end + end else begin + s_dma_axis_tdata_i <= 0 ; + s_dma_axis_tlast_i <= 0 ; + s_dma_axis_tvalid_i <= 0 ; + end +end + + +reg [15:0] axis_dma_len; +task TEST_SINGLE_READ_AXI (); begin + $display("Running TEST_SINGLE_READ_AXI Task"); + + //DATA MEMORY READ + ///////////////////////////////////////////// + // ADDR + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_1_10_0_1; // '00'_CORE0 - '1'_SINGLE - '10'_DMEM - '0'_WRITE - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + data_wr = 32'b00000000_00000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + + //PROGRAM MEMORY WRITE + ///////////////////////////////////////////// + // ADDR + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + // DATA + data_wr = 127; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_DT_I, prot, data_wr, resp); + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_1_01_1_1; // '00'_CORE0 - '1'_SINGLE - '01'_PMEM - '1'_WRITE - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + data_wr = 32'b00000000_00000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + //DATA MEMORY WRITE + ///////////////////////////////////////////// + // ADDR + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + // DATA + data_wr = 255; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_DT_I, prot, data_wr, resp); + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_1_10_1_1; // '00'_CORE0 - '1'_SINGLE - '10'_DMEM - '1'_WRITE - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + data_wr = 32'b00000000_00000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + + + //DATA MEMORY READ + ///////////////////////////////////////////// + // ADDR + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_1_10_0_1; // '00'_CORE0 - '1'_SINGLE - '10'_DMEM - '0'_WRITE - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + data_wr = 32'b00000000_00000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + +end +endtask + +task TEST_DMA_AXI (); begin + $display("Running TEST_DMA_AXI Task"); + + //PROGRAM MEMORY WRITE + ///////////////////////////////////////////// + // DATA LEN + axis_dma_len = 50; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); + // START ADDR + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_0_01_1_1; // '00'_CORE0 - '0'_AXI - '01'_PMEM - '1'_WRITE - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + //Start DMA TRANSFER + @(posedge s_dma_axis_tready_o); + axis_dma_start = 1'b1; + @(posedge s_dma_axis_tlast_i); + axis_dma_start = 1'b0; + data_wr = 32'b00000000_00000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + + + //PROGRAM MEMORY READ + ///////////////////////////////////////////// + // DATA LEN + axis_dma_len = 25; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); + // START ADDR + data_wr = 25; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_0_01_0_1; // '00'_CORE0 - '0'_AXI - '01'_PMEM - '0'_READ - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + + //Wait for READ - DMA TRANSFER + @(posedge m_dma_axis_tlast_o); + data_wr = 32'b00000000_0000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + + + //DATA MEMORY WRITE + ///////////////////////////////////////////// + // DATA LEN + axis_dma_len = 50; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); + // START ADDR + data_wr = 10; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_0_10_1_1; // '00'_CORE0 - '0'_AXI - '10'_DMEM - '1'_WRITE - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + + //Start DMA TRANSFER + @(posedge s_dma_axis_tready_o); + axis_dma_start = 1'b1; + @(posedge s_dma_axis_tlast_i); + axis_dma_start = 1'b0; + data_wr = 32'b00000000_0000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + + + //DATA MEMORY READ + ///////////////////////////////////////////// + // DATA LEN + axis_dma_len = 50; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); + // START ADDR + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_0_10_0_1; // '00'_CORE0 - '0'_AXI - '10'_DMEM - '0'_READ - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + + //Wait for READ - DMA TRANSFER + @(posedge m_dma_axis_tlast_o); + data_wr = 32'b00000000_0000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + + /* + //WAVE MEMORY WRITE + ///////////////////////////////////////////// + // DATA LEN + axis_dma_len = 15; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); + // START ADDR + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_0_11_1_1; // '00'_CORE0 - '0'_AXI - '11'_WMEM - '1'_WRITE - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + + //Start DMA TRANSFER + @(posedge s_dma_axis_tready_o); + axis_dma_start = 1'b1; + @(posedge s_dma_axis_tlast_i); + axis_dma_start = 1'b0; + data_wr = 32'b00000000_0000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + */ + + //WAVE MEMORY READ + ///////////////////////////////////////////// + // DATA LEN + axis_dma_len = 15; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); + // START ADDR + data_wr = 0; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + //CONFIGURE TPROC () + data_wr = 32'b0000000000000000000000000_00_0_11_0_1; // '00'_CORE0 - '0'_AXI - '11'_WMEM - '0'_READ - '1'_START + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + + //Wait for READ - DMA TRANSFER + @(posedge m_dma_axis_tlast_o); + data_wr = 32'b00000000_0000000_00000000_00000000; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + @ (posedge s_ps_dma_aclk); #0.1; + + + +end +endtask + + +task WRITE_AXI(integer PORT_AXI, DATA_AXI); begin + $display("Running WRITE_AXI() Task"); + //$display("PORT %d", PORT_AXI); + //$display("DATA %d", DATA_AXI); + @ (posedge s_ps_dma_aclk); #0.1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(PORT_AXI, prot, DATA_AXI, resp); + end +endtask + +task READ_AXI(integer ADDR_AXI); begin + $display("Running READ_AXI() Task"); + @ (posedge s_ps_dma_aclk); #0.1; + axi_mst_0_agent.AXI4LITE_READ_BURST(ADDR_AXI, 0, DATA_RD, resp); + $display("READ AXI_DATA %d", DATA_RD); + end +endtask + +task COND_CLEAR; begin + $display("Running COND CLEAR Task"); + @ (posedge s_ps_dma_aclk); #0.1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CTRL, prot, 2048, resp); + end +endtask + +task COND_SET; begin + $display("Running COND SET Task"); + @ (posedge s_ps_dma_aclk); #0.1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CTRL, prot, 20481024, resp); + end +endtask + + +integer cnt ; +integer axi_addr ; +integer num; + +task TEST_STATES; begin + $display("Running TPROC TEST_STATES Task"); + +// PROCESSOR START + #1000; + @ (posedge c_clk); #0.1; + proc_start_i = 1'b1; + @ (posedge c_clk); #0.1; + proc_start_i = 1'b0; +// PROCESSOR STOP + #1000; + @ (posedge c_clk); #0.1; + proc_stop_i = 1'b1; + @ (posedge c_clk); #0.1; + proc_stop_i = 1'b0; +// PROCESSOR START + #1000; + @ (posedge c_clk); #0.1; + proc_start_i = 1'b1; + @ (posedge c_clk); #0.1; + proc_start_i = 1'b0; + +// CORE STOP + #1000; + @ (posedge c_clk); #0.1; + core_stop_i = 1'b1; + @ (posedge c_clk); #0.1; + core_stop_i = 1'b0; +// CORE START + #1000; + @ (posedge c_clk); #0.1; + core_start_i = 1'b1; + @ (posedge c_clk); #0.1; + core_start_i = 1'b0; + +// PROCESSOR START + #1000; + @ (posedge c_clk); #0.1; + proc_start_i = 1'b1; + @ (posedge c_clk); #0.1; + proc_start_i = 1'b0; + +// CORE START + #1000; + @ (posedge c_clk); #0.1; + core_start_i = 1'b1; + @ (posedge c_clk); #0.1; + core_start_i = 1'b0; + +// TIME RESET + #1000; + @ (posedge t_clk); #0.1; + time_rst_i = 1'b1; + @ (posedge t_clk); #0.1; + time_rst_i = 1'b0; +// TIME INIT + #1000; + @ (posedge t_clk); #0.1; + time_init_i = 1'b1; + offset_dt_i = 100; + @ (posedge t_clk); #0.1; + time_init_i = 1'b0; +// TIME UPDATE + #1000; + @ (posedge t_clk); #0.1; + time_updt_i = 1'b1; + offset_dt_i = 50; + @ (posedge t_clk); #0.1; + time_updt_i = 1'b0; + + @ (posedge c_clk); #0.1; + + + end +endtask + + +task TEST_AXI (); begin + $display("Running TEST_AXI Task"); + WRITE_AXI( REG_TPROC_CTRL , 1); //TIME_RST + #1000; + WRITE_AXI( REG_TPROC_CTRL , 2); //TIME_UPDT + #1000; + WRITE_AXI( REG_TPROC_CTRL , 4); //PROC_START + #1000; + WRITE_AXI( REG_TPROC_CTRL , 8); //PROC_STOP + #1000; + WRITE_AXI( REG_TPROC_CTRL , 16); //CORE_START + #1000; + WRITE_AXI( REG_TPROC_CTRL , 32); //CORE_STOP + #1000; + WRITE_AXI( REG_TPROC_CTRL , 64); //PROC_RST + #1000; + WRITE_AXI( REG_TPROC_CTRL , 128); //PROC_RUN + #1000; + WRITE_AXI( REG_TPROC_CTRL , 256); //PROC_PAUSE + #1000; + WRITE_AXI( REG_TPROC_CTRL , 512); //PROC_FREEZE + #1000; + WRITE_AXI( REG_TPROC_CTRL , 8); //PROC_STOP + #1000; + WRITE_AXI( REG_TPROC_CTRL , 1024); //PROC_STEP + #1000; + WRITE_AXI( REG_TPROC_CTRL , 2048); //CORE_STEP + #1000; + WRITE_AXI( REG_TPROC_CTRL , 4096); //TIME_STEP + + #100; + WRITE_AXI( REG_TPROC_CTRL , 8192); //PROC_START + WRITE_AXI( REG_TPROC_CTRL , 16384); //PROC_RST + #100; + + +end +endtask + + +/* +always @(posedge t_clk) + if (!rst_ni) + count_bin_i <= 0; + else + count_bin_i <= count_bin_i + 1'b1; + +reg [31:0] count_gray, count_bin_i, count_bin_o; +bin_2_gray bin_2_gray_inst (count_bin_i , count_gray ); +gray_2_bin gray_2_bin_inst (count_gray , count_bin_o ); +*/ + +endmodule diff --git a/firmware/ip/qick_processor/src/tb/tb_qick_processor_issue35.sv b/firmware/ip/qick_processor/src/tb/tb_qick_processor_issue35.sv new file mode 100644 index 0000000..1dc6da3 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/tb_qick_processor_issue35.sv @@ -0,0 +1,923 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 10-2023 +// Version : 2 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : tProc_v2 +/* Description: +Test Bench for Qick Processor Testing +*/ +////////////////////////////////////////////////////////////////////////////// + +`include "_qproc_defines.svh" + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + + + +//`define T_TCLK 1.953125 // Half Clock Period for Simulation +`define T_TCLK 1.302 // Half Clock Period for Simulation +`define T_CCLK 2.5 // Half Clock Period for Simulation +`define T_SCLK 5 // Half Clock Period for Simulation + + +`define GEN_SYNC 1 +`define DUAL_CORE 0 +`define IO_CTRL 1 +`define DEBUG 3 +`define TNET 0 +`define QCOM 0 +`define CUSTOM_PERIPH 1 +`define LFSR 1 +`define DIVIDER 1 +`define ARITH 1 +`define TIME_READ 1 +`define FIFO_DEPTH 8 +`define PMEM_AW 12 +`define DMEM_AW 14 +`define WMEM_AW 10 +`define REG_AW 4 +`define IN_PORT_QTY 2 +`define OUT_TRIG_QTY 8 +`define OUT_DPORT_QTY 2 +`define OUT_DPORT_DW 8 +`define OUT_WPORT_QTY 3 + +module tb_qick_processor_issue35 (); + + +// VIP Agent +axi_mst_0_mst_t axi_mst_0_agent; +xil_axi_prot_t prot = 0; +reg[31:0] data_wr = 32'h12345678; +xil_axi_resp_t resp; +//AXI-LITE +//wire s_axi_aclk ; +wire s_ps_dma_aresetn ; +wire [7:0] s_axi_awaddr ; +wire [2:0] s_axi_awprot ; +wire s_axi_awvalid ; +wire s_axi_awready ; +wire [31:0] s_axi_wdata ; +wire [3:0] s_axi_wstrb ; +wire [3:0] s_axi_wstrb ; +wire s_axi_wvalid ; +wire s_axi_wready ; +wire [1:0] s_axi_bresp ; +wire s_axi_bvalid ; +wire s_axi_bready ; +wire [7:0] s_axi_araddr ; +wire [2:0] s_axi_arprot ; +wire s_axi_arvalid ; +wire s_axi_arready ; +wire [31:0] s_axi_rdata ; +wire [1:0] s_axi_rresp ; +wire s_axi_rvalid ; +wire s_axi_rready ; + +////////////////////////////////////////////////////////////////////////// +// CLK Generation +reg c_clk, t_clk, s_ps_dma_aclk, rst_ni; + +initial begin + t_clk = 1'b0; + forever # (`T_TCLK) t_clk = ~t_clk; +end + +initial begin + c_clk = 1'b0; + forever # (`T_CCLK) c_clk = ~c_clk; +end + +initial begin + s_ps_dma_aclk = 1'b0; + #0.5 + forever # (`T_SCLK) s_ps_dma_aclk = ~s_ps_dma_aclk; +end + + assign s_ps_dma_aresetn = rst_ni; + + + + + +reg [255:0] max_value ; +reg axis_dma_start ; + + + + +reg [255 :0] s_dma_axis_tdata_i ; +reg s_dma_axis_tlast_i ; +reg s_dma_axis_tvalid_i ; +reg m_dma_axis_tready_i ; +wire [63 :0] port_0_dt_i ; +reg [63 :0] port_1_dt_i ; +reg s_axi_aclk ; +reg s_axi_aresetn ; + + + +reg axis_aclk ; +reg axis_aresetn ; +reg m0_axis_tready =1 ; +reg m1_axis_tready =0 ; +reg m2_axis_tready =0 ; +reg m3_axis_tready =0 ; +reg m4_axis_tready =0 ; +reg m5_axis_tready =0 ; +reg m6_axis_tready =0 ; +reg m7_axis_tready =0 ; + +wire s_dma_axis_tready_o ; +wire [255 :0] m_dma_axis_tdata_o ; +wire m_dma_axis_tlast_o ; +wire m_dma_axis_tvalid_o ; + +wire [167:0] m0_axis_tdata ; +wire m0_axis_tvalid ; +wire [167:0] m1_axis_tdata ; +wire m1_axis_tvalid ; +wire [167:0] m2_axis_tdata ; +wire m2_axis_tvalid ; +wire [167:0] m3_axis_tdata ; +wire m3_axis_tvalid ; +wire [167:0] m4_axis_tdata ; +wire m4_axis_tvalid ; +wire [167:0] m5_axis_tdata ; +wire m5_axis_tvalid ; +wire [167:0] m6_axis_tdata ; +wire m6_axis_tvalid ; +wire [167:0] m7_axis_tdata ; +wire m7_axis_tvalid ; +wire [`OUT_DPORT_DW-1:0] port_0_dt_o, port_1_dt_o, port_2_dt_o, port_3_dt_o ; + +wire qnet_en_o ; +wire [4 :0] qnet_op_o ; +wire [31:0] qnet_a_dt_o ; +wire [31:0] qnet_b_dt_o ; +wire [31:0] qnet_c_dt_o ; +wire [31:0] qnet_d_dt_o ; +reg qnet_rdy_i ; +reg [31 :0] qnet_dt_i [2] ; +reg [31 :0] qcom_dt_i [2] ; +reg [31 :0] qp1_dt_i [2] ; +reg [31 :0] qp2_dt_i [2] ; + +wire periph_en_o ; +wire [4 :0] periph_op_o ; +wire [31:0] periph_a_dt_o ; +wire [31:0] periph_b_dt_o ; +wire [31:0] periph_c_dt_o ; +wire [31:0] periph_d_dt_o ; +reg periph_rdy_i ; +reg [31 :0] periph_dt_i [2] ; + + +reg s0_axis_tvalid , s1_axis_tvalid ; +reg [15:0] waves, wtime; +reg [31:0] axi_dt; + + +int val_A, val_B, val_C, val_D, result ; +reg [31:0] result_r, result_2r, result_3r ; + +always_ff @ (posedge c_clk) begin + result_r <= result; + result_2r <= result_r; + result_3r <= result_2r; +end + +// Register ADDRESS +parameter REG_TPROC_CTRL = 0 * 4 ; +parameter REG_TPROC_CFG = 1 * 4 ; +parameter REG_MEM_ADDR = 2 * 4 ; +parameter REG_MEM_LEN = 3 * 4 ; +parameter REG_MEM_DT_I = 4 * 4 ; +parameter REG_AXI_W_DT1 = 5 * 4 ; +parameter REG_AXI_W_DT2 = 6 * 4 ; +parameter REG_CORE_CFG = 7 * 4 ; +parameter REG_AXI_DT_SRC = 8 * 4 ; +parameter REG_MEM_DT_O = 10 * 4 ; +parameter REG_AXI_R_DT1 = 11 * 4 ; +parameter REG_AXI_R_DT2 = 12 * 4 ; +parameter REG_TIME_USR = 13 * 4 ; +parameter REG_TPROC_STATUS = 14 * 4 ; +parameter REG_TPROC_DEBUG = 15 * 4 ; + + + +axi_mst_0 axi_mst_0_i + ( + .aclk (s_ps_dma_aclk ), + .aresetn (s_ps_dma_aresetn ), + .m_axi_araddr (s_axi_araddr ), + .m_axi_arprot (s_axi_arprot ), + .m_axi_arready (s_axi_arready ), + .m_axi_arvalid (s_axi_arvalid ), + .m_axi_awaddr (s_axi_awaddr ), + .m_axi_awprot (s_axi_awprot ), + .m_axi_awready (s_axi_awready ), + .m_axi_awvalid (s_axi_awvalid ), + .m_axi_bready (s_axi_bready ), + .m_axi_bresp (s_axi_bresp ), + .m_axi_bvalid (s_axi_bvalid ), + .m_axi_rdata (s_axi_rdata ), + .m_axi_rready (s_axi_rready ), + .m_axi_rresp (s_axi_rresp ), + .m_axi_rvalid (s_axi_rvalid ), + .m_axi_wdata (s_axi_wdata ), + .m_axi_wready (s_axi_wready ), + .m_axi_wstrb (s_axi_wstrb ), + .m_axi_wvalid (s_axi_wvalid ) + ); + + +reg proc_start_i, proc_stop_i ; +reg core_start_i, core_stop_i ; +reg time_rst_i, time_init_i, time_updt_i; + +reg [47:0] offset_dt_i ; +wire [47:0] t_time_abs_o ; +reg time_updt_i; + +wire [31:0] ps_debug_do; + +reg qp1_en_r; +reg [31:0] qp1_a_dt_r, qp1_b_dt_r; +wire [31:0] qp1_a_dt_o, qp1_b_dt_o, qp1_c_dt_o, qp1_d_dt_o; +always_ff @ (posedge c_clk) begin + qp1_en_r <= qp1_en_o; + qp1_a_dt_r <= qp1_a_dt_o; + qp1_b_dt_r <= qp1_b_dt_o; +end + +assign qp1_rdy_i = ~qp1_en_r; +assign qp1_dt_i[0] = qp1_a_dt_r; +assign qp1_dt_i[1] = qp1_b_dt_r; +assign qp1_vld_i = qp1_en_r ; + + +axis_qick_processor # ( + .DUAL_CORE ( `DUAL_CORE ) , + .GEN_SYNC ( `GEN_SYNC ) , + .IO_CTRL ( `IO_CTRL ) , + .DEBUG ( `DEBUG ) , + .TNET ( `TNET ) , + .QCOM ( `QCOM ) , + .CUSTOM_PERIPH ( `CUSTOM_PERIPH ) , + .LFSR ( `LFSR ) , + .DIVIDER ( `DIVIDER ) , + .ARITH ( `ARITH ) , + .TIME_READ ( `TIME_READ ) , + .FIFO_DEPTH ( `FIFO_DEPTH ) , + .PMEM_AW ( `PMEM_AW ) , + .DMEM_AW ( `DMEM_AW ) , + .WMEM_AW ( `WMEM_AW ) , + .REG_AW ( `REG_AW ) , + .IN_PORT_QTY ( `IN_PORT_QTY ) , + .OUT_TRIG_QTY ( `OUT_TRIG_QTY ) , + .OUT_DPORT_QTY ( `OUT_DPORT_QTY ) , + .OUT_DPORT_DW ( `OUT_DPORT_DW ) , + .OUT_WPORT_QTY ( `OUT_WPORT_QTY ) +) AXIS_QPROC ( + .t_clk_i ( t_clk ) , + .t_resetn ( rst_ni ) , + .c_clk_i ( c_clk ) , + .c_resetn ( rst_ni ) , + .ps_clk_i ( s_ps_dma_aclk ) , + .ps_resetn ( s_ps_dma_aresetn ) , + .ext_flag_i ( ext_flag_i ) , + .proc_start_i ( proc_start_i ) , + .proc_stop_i ( proc_stop_i ) , + .core_start_i ( core_start_i ) , + .core_stop_i ( core_stop_i ) , + .time_rst_i ( time_rst_i ) , + .time_init_i ( time_init_i ) , + .time_updt_i ( time_updt_i ) , + .time_dt_i ( offset_dt_i ) , + .t_time_abs_o ( t_time_abs_o ) , + .ps_debug_do ( ps_debug_do ) , + + .qnet_en_o ( qnet_en_o ) , + .qnet_op_o ( qnet_op_o ) , + .qnet_a_dt_o ( qnet_a_dt_o ) , + .qnet_b_dt_o ( qnet_b_dt_o ) , + .qnet_c_dt_o ( qnet_c_dt_o ) , + .qnet_rdy_i ( qnet_rdy_i ) , + .qnet_dt1_i ( qnet_dt_i[0] ) , + .qnet_dt2_i ( qnet_dt_i[1] ) , + .qnet_vld_i ( qnet_vld_i ) , + .qnet_flag_i ( qnet_flag_i ) , + + .qcom_en_o ( qcom_en_o ) , + .qcom_op_o ( qcom_op_o ) , + .qcom_dt_o ( qcom_dt_o ) , + .qcom_rdy_i ( qcom_rdy_i ) , + .qcom_dt1_i ( qcom_dt_i[0] ) , + .qcom_dt2_i ( qcom_dt_i[1] ) , + .qcom_vld_i ( qcom_vld_i ) , + .qcom_flag_i ( qcom_flag_i ) , + + .qp1_en_o ( qp1_en_o ) , + .qp1_op_o ( qp1_op_o ) , + .qp1_a_dt_o ( qp1_a_dt_o ) , + .qp1_b_dt_o ( qp1_b_dt_o ) , + .qp1_c_dt_o ( qp1_c_dt_o ) , + .qp1_d_dt_o ( qp1_d_dt_o ) , + .qp1_rdy_i ( qp1_rdy_i ) , + .qp1_dt1_i ( qp1_dt_i[0] ) , + .qp1_dt2_i ( qp1_dt_i[1] ) , + .qp1_vld_i ( qp1_vld_i ) , + .qp1_flag_i ( qp1_flag_i ) , + + .qp2_en_o ( qp2_en_o ) , + .qp2_op_o ( qp2_op_o ) , + .qp2_a_dt_o ( qp2_a_dt_o ) , + .qp2_b_dt_o ( qp2_b_dt_o ) , + .qp2_c_dt_o ( qp2_c_dt_o ) , + .qp2_d_dt_o ( qp2_d_dt_o ) , + .qp2_rdy_i ( qpb_rdy_i ) , + .qp2_dt1_i ( qp2_dt_i[0] ) , + .qp2_dt2_i ( qp2_dt_i[1] ) , + .qp2_vld_i ( qp2_vld_i ) , + + .s_dma_axis_tdata_i ( s_dma_axis_tdata_i ) , + .s_dma_axis_tlast_i ( s_dma_axis_tlast_i ) , + .s_dma_axis_tvalid_i ( s_dma_axis_tvalid_i ) , + .s_dma_axis_tready_o ( s_dma_axis_tready_o ) , + .m_dma_axis_tdata_o ( m_dma_axis_tdata_o ) , + .m_dma_axis_tlast_o ( m_dma_axis_tlast_o ) , + .m_dma_axis_tvalid_o ( m_dma_axis_tvalid_o ) , + .m_dma_axis_tready_i ( m_dma_axis_tready_i ) , + .s0_axis_tdata ( port_0_dt_i ) , + .s0_axis_tvalid ( port_0_vld ) , + .s1_axis_tdata ( port_1_dt_i ) , + .s1_axis_tvalid ( s1_axis_tvalid ) , + .s2_axis_tdata ( 64'd2 ) , + .s2_axis_tvalid ( 1'b0 ) , + .s3_axis_tdata ( 64'd3 ) , + .s3_axis_tvalid ( 1'b0 ) , + .s4_axis_tdata ( 64'd4 ) , + .s4_axis_tvalid ( 1'b0 ) , + .s5_axis_tdata ( 64'd5 ) , + .s5_axis_tvalid ( 1'b0 ) , + .s6_axis_tdata ( 64'd6 ) , + .s6_axis_tvalid ( 1'b0 ) , + .s7_axis_tdata ( 64'd7 ) , + .s7_axis_tvalid ( 1'b0 ) , + .s_axi_awaddr ( s_axi_awaddr[7:0] ) , + .s_axi_awprot ( s_axi_awprot ) , + .s_axi_awvalid ( s_axi_awvalid ) , + .s_axi_awready ( s_axi_awready ) , + .s_axi_wdata ( s_axi_wdata ) , + .s_axi_wstrb ( s_axi_wstrb ) , + .s_axi_wvalid ( s_axi_wvalid ) , + .s_axi_wready ( s_axi_wready ) , + .s_axi_bresp ( s_axi_bresp ) , + .s_axi_bvalid ( s_axi_bvalid ) , + .s_axi_bready ( s_axi_bready ) , + .s_axi_araddr ( s_axi_araddr[7:0] ) , + .s_axi_arprot ( s_axi_arprot ) , + .s_axi_arvalid ( s_axi_arvalid ) , + .s_axi_arready ( s_axi_arready ) , + .s_axi_rdata ( s_axi_rdata ) , + .s_axi_rresp ( s_axi_rresp ) , + .s_axi_rvalid ( s_axi_rvalid ) , + .s_axi_rready ( s_axi_rready ) , + .m0_axis_tdata ( m0_axis_tdata ) , + .m0_axis_tvalid ( m0_axis_tvalid ) , + .m0_axis_tready ( m0_axis_tready ) , + .m1_axis_tdata ( m1_axis_tdata ) , + .m1_axis_tvalid ( m1_axis_tvalid ) , + .m1_axis_tready ( m1_axis_tready ) , + .m2_axis_tdata ( m2_axis_tdata ) , + .m2_axis_tvalid ( m2_axis_tvalid ) , + .m2_axis_tready ( m2_axis_tready ) , + .m3_axis_tdata ( m3_axis_tdata ) , + .m3_axis_tvalid ( m3_axis_tvalid ) , + .m3_axis_tready ( m3_axis_tready ) , + .m4_axis_tdata ( m4_axis_tdata ) , + .m4_axis_tvalid ( m4_axis_tvalid ) , + .m4_axis_tready ( m4_axis_tready ) , + .m5_axis_tdata ( m5_axis_tdata ) , + .m5_axis_tvalid ( m5_axis_tvalid ) , + .m5_axis_tready ( m5_axis_tready ) , + .m6_axis_tdata ( m6_axis_tdata ) , + .m6_axis_tvalid ( m6_axis_tvalid ) , + .m6_axis_tready ( m6_axis_tready ) , + .m7_axis_tdata ( m7_axis_tdata ) , + .m7_axis_tvalid ( m7_axis_tvalid ) , + .m7_axis_tready ( m7_axis_tready ) , + .port_0_dt_o ( port_0_dt_o ) , + .port_1_dt_o ( port_1_dt_o ) , + .port_2_dt_o ( port_2_dt_o ) , + .port_3_dt_o ( port_3_dt_o ) ); + +wire port_0_vld, qnet_vld_i, qnet_flag_i, periph_flag_i, ext_flag_i; +assign port_0_dt_i = port_1_dt_o; +assign port_0_vld = port_0_dt_o[0]; +assign qnet_vld_i = t_time_abs_o[3]&t_time_abs_o[2]&t_time_abs_o[1] ; +assign qnet_flag_i = ~t_time_abs_o[5] & ~t_time_abs_o[4] & t_time_abs_o[3] ; +assign periph_flag_i = ~t_time_abs_o[5] & t_time_abs_o[4] & t_time_abs_o[3] ; +assign ext_flag_i = t_time_abs_o[5] & t_time_abs_o[4] & t_time_abs_o[3] ; + +reg periph_vld_i ; +reg qcom_rdy_i, qpb_rdy_i; + +initial begin + + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb_qick_processor_issue35.axi_mst_0_i.inst.IF); + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + // Start agents. + axi_mst_0_agent.start_master(); + + + $display("*** Start Test ***"); + + $display("AXI_WDATA_WIDTH %d", `AXI_WDATA_WIDTH); + + $display("LFSR %d", `LFSR); + $display("DIVIDER %d", `DIVIDER); + $display("ARITH %d", `ARITH); + $display("TIME_READ %d", `TIME_READ); + + $display("DMEM_AW %d", `DMEM_AW); + $display("WMEM_AW %d", `WMEM_AW); + $display("REG_AW %d", `REG_AW); + $display("IN_PORT_QTY %d", `IN_PORT_QTY); + $display("OUT_DPORT_QTY %d", `OUT_DPORT_QTY); + $display("OUT_WPORT_QTY %d", `OUT_WPORT_QTY); + + + AXIS_QPROC.QPROC.CORE_0.CORE_MEM.P_MEM.RAM = '{default:'0} ; + AXIS_QPROC.QPROC.CORE_0.CORE_MEM.D_MEM.RAM = '{default:'0} ; + AXIS_QPROC.QPROC.CORE_0.CORE_MEM.W_MEM.RAM = '{default:'0} ; + +// AXIS_QPROC.QPROC.DISPATCHER.TRIG_FIFO[0].trig_fifo_inst.fifo_mem.RAM = '{default:'0} ; +// AXIS_QPROC.QPROC.DISPATCHER.DATA_FIFO[0].data_fifo_inst.fifo_mem.RAM = '{default:'0} ; +// AXIS_QPROC.QPROC.DISPATCHER.DATA_FIFO[1].data_fifo_inst.fifo_mem.RAM = '{default:'0} ; +// AXIS_QPROC.QPROC.DISPATCHER.WAVE_FIFO[0].wave_fifo_inst.fifo_mem.RAM = '{default:'0} ; + +// for (int i=0; i < 1 /*`OUT_TRIG_QTY*/; i=i+1) +// AXIS_QPROC.QPROC.DISPATCHER.TRIG_FIFO[i].trig_fifo_inst.fifo_mem.RAM = '{default:'0} ; +// for (int i=0; i < `OUT_DPORT_QTY; i=i+1) +// AXIS_QPROC.QPROC.DISPATCHER.DATA_FIFO[i].data_fifo_inst.fifo_mem.RAM = '{default:'0} ; +// for (int i=0; i < `OUT_WPORT_QTY; i=i+1) +// AXIS_QPROC.QPROC.DISPATCHER.WAVE_FIFO[i].wave_fifo_inst.fifo_mem.RAM = '{default:'0} ; + + // Load Memories + +// $readmemb("/home/mdifeder/IPs/qick_processor/src/tb/prog.bin", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.P_MEM.RAM); +// $readmemb("prog.bin", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.P_MEM.RAM); + $readmemh("prog_issue35.mem", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.P_MEM.RAM); + //$readmemb("/home/mdifeder/IPs/qick_processor/src/tb/wave.bin", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.W_MEM.RAM); + $readmemh("wave_issue35.mem", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.W_MEM.RAM); + $readmemh("dmem_issue35.mem", AXIS_QPROC.QPROC.CORE_0.CORE_MEM.D_MEM.RAM); + + +// INITIAL VALUES + + qnet_dt_i = '{default:'0} ; + rst_ni = 1'b0; + axi_dt = 0 ; + axis_dma_start = 1'b0; + s1_axis_tvalid = 1'b0 ; + port_1_dt_i = 0; + qcom_rdy_i = 0 ; + qpb_rdy_i = 0 ; + periph_dt_i = {0,0} ; + qnet_rdy_i = 0 ; + qnet_dt_i [2] = {0,0} ; + proc_start_i = 1'b0; + proc_stop_i = 1'b0; + core_start_i = 1'b0; + core_stop_i = 1'b0; + time_rst_i = 1'b0; + time_init_i = 1'b0; + time_updt_i = 1'b0; + offset_dt_i = 0 ; + periph_vld_i = 1'b0; + + m_dma_axis_tready_i = 1'b1; + max_value = 0; + + #0.5us; + + repeat(16) @ (posedge s_ps_dma_aclk); #0.1; + rst_ni = 1'b1; + + #0.5us; + + WRITE_AXI( REG_TPROC_CFG , 32'h0001_0000); // prev_mask_dbg + + + repeat (2) begin + + WRITE_AXI( REG_TPROC_CTRL , 4); //PROC_START + + #5us; + + WRITE_AXI( REG_TPROC_CTRL , 8); //PROC_STOP + + #5us; + end + + + $display("*** End Test ***"); + $finish(); +end + + +//integer DATA_RD; + +///// DMA SIMULATOR +//always_ff @(posedge s_ps_dma_aclk) begin +// if (axis_dma_start) begin +// if (s_dma_axis_tdata_i < axis_dma_len ) begin +// s_dma_axis_tdata_i <= s_dma_axis_tdata_i + 1'b1 ; +// s_dma_axis_tvalid_i <= 1; +// end else if (s_dma_axis_tdata_i == axis_dma_len ) begin +// s_dma_axis_tdata_i <= s_dma_axis_tdata_i + 1'b1 ; +// s_dma_axis_tlast_i <= 1'b1; +// s_dma_axis_tvalid_i <= 1'b1; +// end else begin +// s_dma_axis_tdata_i <= 0 ; +// s_dma_axis_tlast_i <= 0 ; +// s_dma_axis_tvalid_i <= 0 ; +// end +// end else begin +// s_dma_axis_tdata_i <= 0 ; +// s_dma_axis_tlast_i <= 0 ; +// s_dma_axis_tvalid_i <= 0 ; +// end +//end + + +//reg [15:0] axis_dma_len; +//task TEST_SINGLE_READ_AXI (); begin +// $display("Running TEST_SINGLE_READ_AXI Task"); + +// //DATA MEMORY READ +// ///////////////////////////////////////////// +// // ADDR +// data_wr = 0; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_1_10_0_1; // '00'_CORE0 - '1'_SINGLE - '10'_DMEM - '0'_WRITE - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; +// data_wr = 32'b00000000_00000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; + +// //PROGRAM MEMORY WRITE +// ///////////////////////////////////////////// +// // ADDR +// data_wr = 0; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); +// // DATA +// data_wr = 127; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_DT_I, prot, data_wr, resp); +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_1_01_1_1; // '00'_CORE0 - '1'_SINGLE - '01'_PMEM - '1'_WRITE - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; +// data_wr = 32'b00000000_00000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; +// //DATA MEMORY WRITE +// ///////////////////////////////////////////// +// // ADDR +// data_wr = 0; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); +// // DATA +// data_wr = 255; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_DT_I, prot, data_wr, resp); +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_1_10_1_1; // '00'_CORE0 - '1'_SINGLE - '10'_DMEM - '1'_WRITE - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; +// data_wr = 32'b00000000_00000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; + + +// //DATA MEMORY READ +// ///////////////////////////////////////////// +// // ADDR +// data_wr = 0; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_1_10_0_1; // '00'_CORE0 - '1'_SINGLE - '10'_DMEM - '0'_WRITE - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; +// data_wr = 32'b00000000_00000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; + +//end +//endtask + +//task TEST_DMA_AXI (); begin +// $display("Running TEST_DMA_AXI Task"); + +// //PROGRAM MEMORY WRITE +// ///////////////////////////////////////////// +// // DATA LEN +// axis_dma_len = 50; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); +// // START ADDR +// data_wr = 0; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); + +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_0_01_1_1; // '00'_CORE0 - '0'_AXI - '01'_PMEM - '1'_WRITE - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// //Start DMA TRANSFER +// @(posedge s_dma_axis_tready_o); +// axis_dma_start = 1'b1; +// @(posedge s_dma_axis_tlast_i); +// axis_dma_start = 1'b0; +// data_wr = 32'b00000000_00000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; + + +// //PROGRAM MEMORY READ +// ///////////////////////////////////////////// +// // DATA LEN +// axis_dma_len = 25; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); +// // START ADDR +// data_wr = 25; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_0_01_0_1; // '00'_CORE0 - '0'_AXI - '01'_PMEM - '0'_READ - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + +// //Wait for READ - DMA TRANSFER +// @(posedge m_dma_axis_tlast_o); +// data_wr = 32'b00000000_0000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; + + +// //DATA MEMORY WRITE +// ///////////////////////////////////////////// +// // DATA LEN +// axis_dma_len = 50; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); +// // START ADDR +// data_wr = 10; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_0_10_1_1; // '00'_CORE0 - '0'_AXI - '10'_DMEM - '1'_WRITE - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + +// //Start DMA TRANSFER +// @(posedge s_dma_axis_tready_o); +// axis_dma_start = 1'b1; +// @(posedge s_dma_axis_tlast_i); +// axis_dma_start = 1'b0; +// data_wr = 32'b00000000_0000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; + + +// //DATA MEMORY READ +// ///////////////////////////////////////////// +// // DATA LEN +// axis_dma_len = 50; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); +// // START ADDR +// data_wr = 0; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_0_10_0_1; // '00'_CORE0 - '0'_AXI - '10'_DMEM - '0'_READ - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + +// //Wait for READ - DMA TRANSFER +// @(posedge m_dma_axis_tlast_o); +// data_wr = 32'b00000000_0000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; + +// /* +// //WAVE MEMORY WRITE +// ///////////////////////////////////////////// +// // DATA LEN +// axis_dma_len = 15; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); +// // START ADDR +// data_wr = 0; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_0_11_1_1; // '00'_CORE0 - '0'_AXI - '11'_WMEM - '1'_WRITE - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + +// //Start DMA TRANSFER +// @(posedge s_dma_axis_tready_o); +// axis_dma_start = 1'b1; +// @(posedge s_dma_axis_tlast_i); +// axis_dma_start = 1'b0; +// data_wr = 32'b00000000_0000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; +// */ + +// //WAVE MEMORY READ +// ///////////////////////////////////////////// +// // DATA LEN +// axis_dma_len = 15; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_LEN, prot, axis_dma_len, resp); +// // START ADDR +// data_wr = 0; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_MEM_ADDR, prot, data_wr, resp); +// //CONFIGURE TPROC () +// data_wr = 32'b0000000000000000000000000_00_0_11_0_1; // '00'_CORE0 - '0'_AXI - '11'_WMEM - '0'_READ - '1'_START +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); + +// //Wait for READ - DMA TRANSFER +// @(posedge m_dma_axis_tlast_o); +// data_wr = 32'b00000000_0000000_00000000_00000000; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CFG, prot, data_wr, resp); +// @ (posedge s_ps_dma_aclk); #0.1; + + + +//end +//endtask + + +task WRITE_AXI(integer PORT_AXI, DATA_AXI); begin + $display("Running WRITE_AXI() Task"); + //$display("PORT %d", PORT_AXI); + //$display("DATA %d", DATA_AXI); + @ (posedge s_ps_dma_aclk); #0.1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(PORT_AXI, prot, DATA_AXI, resp); + end +endtask + +//task READ_AXI(integer ADDR_AXI); begin +// $display("Running READ_AXI() Task"); +// @ (posedge s_ps_dma_aclk); #0.1; +// axi_mst_0_agent.AXI4LITE_READ_BURST(ADDR_AXI, 0, DATA_RD, resp); +// $display("READ AXI_DATA %d", DATA_RD); +// end +//endtask + +//task COND_CLEAR; begin +// $display("Running COND CLEAR Task"); +// @ (posedge s_ps_dma_aclk); #0.1; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CTRL, prot, 2048, resp); +// end +//endtask + +//task COND_SET; begin +// $display("Running COND SET Task"); +// @ (posedge s_ps_dma_aclk); #0.1; +// axi_mst_0_agent.AXI4LITE_WRITE_BURST(REG_TPROC_CTRL, prot, 20481024, resp); +// end +//endtask + + +//integer cnt ; +//integer axi_addr ; +//integer num; + +//task TEST_STATES; begin +// $display("Running TPROC TEST_STATES Task"); + +//// PROCESSOR START +// #1000; +// @ (posedge c_clk); #0.1; +// proc_start_i = 1'b1; +// @ (posedge c_clk); #0.1; +// proc_start_i = 1'b0; +//// PROCESSOR STOP +// #1000; +// @ (posedge c_clk); #0.1; +// proc_stop_i = 1'b1; +// @ (posedge c_clk); #0.1; +// proc_stop_i = 1'b0; +//// PROCESSOR START +// #1000; +// @ (posedge c_clk); #0.1; +// proc_start_i = 1'b1; +// @ (posedge c_clk); #0.1; +// proc_start_i = 1'b0; + +//// CORE STOP +// #1000; +// @ (posedge c_clk); #0.1; +// core_stop_i = 1'b1; +// @ (posedge c_clk); #0.1; +// core_stop_i = 1'b0; +//// CORE START +// #1000; +// @ (posedge c_clk); #0.1; +// core_start_i = 1'b1; +// @ (posedge c_clk); #0.1; +// core_start_i = 1'b0; + +//// PROCESSOR START +// #1000; +// @ (posedge c_clk); #0.1; +// proc_start_i = 1'b1; +// @ (posedge c_clk); #0.1; +// proc_start_i = 1'b0; + +//// CORE START +// #1000; +// @ (posedge c_clk); #0.1; +// core_start_i = 1'b1; +// @ (posedge c_clk); #0.1; +// core_start_i = 1'b0; + +//// TIME RESET +// #1000; +// @ (posedge t_clk); #0.1; +// time_rst_i = 1'b1; +// @ (posedge t_clk); #0.1; +// time_rst_i = 1'b0; +//// TIME INIT +// #1000; +// @ (posedge t_clk); #0.1; +// time_init_i = 1'b1; +// offset_dt_i = 100; +// @ (posedge t_clk); #0.1; +// time_init_i = 1'b0; +//// TIME UPDATE +// #1000; +// @ (posedge t_clk); #0.1; +// time_updt_i = 1'b1; +// offset_dt_i = 50; +// @ (posedge t_clk); #0.1; +// time_updt_i = 1'b0; + +// @ (posedge c_clk); #0.1; + + +// end +//endtask + + +//task TEST_AXI (); begin +// $display("Running TEST_AXI Task"); +// WRITE_AXI( REG_TPROC_CTRL , 1); //TIME_RST +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 2); //TIME_UPDT +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 4); //PROC_START +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 8); //PROC_STOP +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 16); //CORE_START +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 32); //CORE_STOP +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 64); //PROC_RST +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 128); //PROC_RUN +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 256); //PROC_PAUSE +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 512); //PROC_FREEZE +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 8); //PROC_STOP +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 1024); //PROC_STEP +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 2048); //CORE_STEP +// #1000; +// WRITE_AXI( REG_TPROC_CTRL , 4096); //TIME_STEP + +// #100; +// WRITE_AXI( REG_TPROC_CTRL , 8192); //PROC_START +// WRITE_AXI( REG_TPROC_CTRL , 16384); //PROC_RST +// #100; + + +//end +//endtask + + +///* +//always @(posedge t_clk) +// if (!rst_ni) +// count_bin_i <= 0; +// else +// count_bin_i <= count_bin_i + 1'b1; + +//reg [31:0] count_gray, count_bin_i, count_bin_o; +//bin_2_gray bin_2_gray_inst (count_bin_i , count_gray ); +//gray_2_bin gray_2_bin_inst (count_gray , count_bin_o ); +//*/ + +endmodule diff --git a/firmware/ip/qick_processor/src/tb/tb_qproc.wcfg b/firmware/ip/qick_processor/src/tb/tb_qproc.wcfg new file mode 100644 index 0000000..45fc5e3 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/tb_qproc.wcfg @@ -0,0 +1,605 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ps_clk_i + ps_clk_i + + + proc_start_i + proc_start_i + + + proc_stop_i + proc_stop_i + + + core_start_i + core_start_i + + + core_stop_i + core_stop_i + + + time_rst_i + time_rst_i + + + time_updt_i + time_updt_i + + + time_updt_dt_i[31:0] + time_updt_dt_i[31:0] + + + int_time_en + int_time_en + + + int_time_cmd[3:0] + int_time_cmd[3:0] + + + int_time_dt[31:0] + int_time_dt[31:0] + + + TPROC_CTRL[15:0] + TPROC_CTRL[15:0] + + + xreg_TPROC_CTRL[15:0] + xreg_TPROC_CTRL[15:0] + UNSIGNEDDECRADIX + + + xreg_TPROC_CFG[15:0] + xreg_TPROC_CFG[15:0] + + + xreg_TPROC_W_DT[31:0] + xreg_TPROC_W_DT[31:0] + + + c_clk_i + c_clk_i + + + all_fifo_full + all_fifo_full + + + all_fifo_full_i + all_fifo_full_i + + + some_fifo_full + some_fifo_full + + + core_st[31:0] + core_st[31:0] + #FF00FF + true + + + c_pmem_addr_i[7:0] + c_pmem_addr_i[7:0] + + + t_clk_i + t_clk_i + + + time_st[31:0] + time_st[31:0] + #FF00FF + true + + + t_time_abs_o[47:0] + t_time_abs_o[47:0] + UNSIGNEDDECRADIX + + + t_core_rst_prev_net + t_core_rst_prev_net + + + core_rst_run_p + core_rst_run_p + + + core_rst_stop_p + core_rst_stop_p + + + core_rst_prev_p + core_rst_prev_p + + + core_run_p + core_run_p + + + core_stop_p + core_stop_p + + + time_stop_p + time_stop_p + + + time_run_p + time_run_p + + + time_rst_stop_p + time_rst_stop_p + + + time_rst_run_p + time_rst_run_p + + + time_update_p + time_update_p + + + core_step_p + core_step_p + + + time_step_p + time_step_p + + + RAM[0:255][71:0] + RAM[0:255][71:0] + + + QPROC_CTRL + label + + + proc_start_io + proc_start_io + + + proc_stop_io + proc_stop_io + + + core_start_i + core_start_i + + + core_stop_i + core_stop_i + + + ctrl_c_stop + ctrl_c_stop + + + ctrl_c_rst_run + ctrl_c_rst_run + + + ctrl_c_run + ctrl_c_run + + + ctrl_c_rst_stop + ctrl_c_rst_stop + + + ctrl_c_step + ctrl_c_step + + + core_st[31:0] + core_st[31:0] + #FF00FF + true + + + some_fifo_full + some_fifo_full + + + fifo_ok + fifo_ok + + + core_en + core_en + + + en_i + en_i + + + halt + halt + + + fetch_en + fetch_en + + + + clk_a_i + clk_a_i + + + en_a_i + en_a_i + + + we_a_i + we_a_i + + + addr_a_i[7:0] + addr_a_i[7:0] + + + dt_a_i[71:0] + dt_a_i[71:0] + + + dt_a_o[71:0] + dt_a_o[71:0] + + + c_fifo_trig_full[7:0] + c_fifo_trig_full[7:0] + + + c_fifo_data_full[0:0] + c_fifo_data_full[0:0] + + + c_fifo_wave_full[2:0] + c_fifo_wave_full[2:0] + + + pulse_sync_o + pulse_sync_o + + + CORE_P_MEM + label + + clk_a_i + clk_a_i + + + en_a_i + en_a_i + + + we_a_i + we_a_i + + + addr_a_i[7:0] + addr_a_i[7:0] + + + dt_a_i[71:0] + dt_a_i[71:0] + + + dt_a_o[71:0] + dt_a_o[71:0] + + + rDest + label + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + if_op_code[15:0] + if_op_code[15:0] + + + if_op_data[55:0] + if_op_data[55:0] + + + r_if_op_code[15:0] + r_if_op_code[15:0] + + + r_if_op_data[55:0] + r_if_op_data[55:0] + + + + PC_prev[7:0] + PC_prev[7:0] + + + PC_curr[7:0] + PC_curr[7:0] + + + PC_nxt[7:0] + PC_nxt[7:0] + + + TRIG_FIFO_0 + label + + wr_clk_i + wr_clk_i + + + wr_rst_ni + wr_rst_ni + + + wr_en_i + wr_en_i + + + push_i + push_i + + + data_i[48:0] + data_i[48:0] + + + rd_clk_i + rd_clk_i + + + rd_rst_ni + rd_rst_ni + + + rd_en_i + rd_en_i + + + pop_i + pop_i + + + data_o[48:0] + data_o[48:0] + + + flush_i + flush_i + + + async_empty_o + async_empty_o + + + async_full_o + async_full_o + + + + cfg_pc_nxt[2:0] + cfg_pc_nxt[2:0] + + + id_branch_cond_ok + id_branch_cond_ok + + + id_ret + id_ret + + + id_AI + id_AI + + + id_type_br + id_type_br + + + id_exec_ok + id_exec_ok + + + id_cond_ok + id_cond_ok + + + id_cond_used + id_cond_used + + + id_COND[2:0] + id_COND[2:0] + + + alu_fZ_r + alu_fZ_r + + + x1_alu_fZ + x1_alu_fZ + + + .flag_we + .flag_we + + + AB_alu + label + + Z_o + Z_o + + + C_o + C_o + + + S_o + S_o + + + alu_result_o[31:0] + alu_result_o[31:0] + + + clk_i + clk_i + + + A_i[31:0] + A_i[31:0] + + + B_i[31:0] + B_i[31:0] + + + alu_op_i[3:0] + alu_op_i[3:0] + + + + [0][31:0] + [0][31:0] + + + [0][31:0] + [0][31:0] + + + [0][31:0] + [0][31:0] + + + [0] + [0] + + + [0] + [0] + + + .src[1:0] + .src[1:0] + + + .src[1:0] + .src[1:0] + + + [0][31:0] + [0][31:0] + + + m_axis_tdata[0:2][167:0] + m_axis_tdata[0:2][167:0] + + + m_axis_tvalid[0:2] + m_axis_tvalid[0:2] + + + clk_i + clk_i + + + rst_ni + rst_ni + + + restart_i + restart_i + + + en_i + en_i + + + x1_ctrl + x1_ctrl + + + x2_ctrl + x2_ctrl + + + wmem_we_o + wmem_we_o + + + wmem_addr_o[3:0] + wmem_addr_o[3:0] + + + wmem_w_dt_o[167:0] + wmem_w_dt_o[167:0] + + + wmem_r_dt_i[167:0] + wmem_r_dt_i[167:0] + + diff --git a/firmware/ip/qick_processor/src/tb/tb_qproc_issue35.wcfg b/firmware/ip/qick_processor/src/tb/tb_qproc_issue35.wcfg new file mode 100644 index 0000000..864795a --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/tb_qproc_issue35.wcfg @@ -0,0 +1,658 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + t_resetn + t_resetn + + + c_resetn + c_resetn + + + ps_resetn + ps_resetn + + + QPROC_CTRL + label + + proc_start_io + proc_start_io + + + proc_stop_io + proc_stop_io + + + core_start_i + core_start_i + + + core_stop_i + core_stop_i + + + ctrl_c_stop + ctrl_c_stop + + + ctrl_c_rst_run + ctrl_c_rst_run + + + ctrl_c_run + ctrl_c_run + + + ctrl_c_rst_stop + ctrl_c_rst_stop + + + ctrl_c_step + ctrl_c_step + + + + pulse_sync_o + pulse_sync_o + #FFA500 + true + + + DEBUG_OUT + label + + ps_debug_do[31:0] + ps_debug_do[31:0] + + + c_core_do[31:0] + c_core_do[31:0] + + + c_debug_do[31:0] + c_debug_do[31:0] + + + c_time_usr_do[31:0] + c_time_usr_do[31:0] + SIGNEDDECRADIX + + + c_time_ref_do[31:0] + c_time_ref_do[31:0] + UNSIGNEDDECRADIX + + + c_port_do[31:0] + c_port_do[31:0] + + + t_debug_do[31:0] + t_debug_do[31:0] + + + t_fifo_do[31:0] + t_fifo_do[31:0] + + + t_time_abs_o[47:0] + t_time_abs_o[47:0] + UNSIGNEDDECRADIX + + + + CORE_PMEM + label + + clk_a_i + clk_a_i + + + en_a_i + en_a_i + + + addr_a_i[11:0] + addr_a_i[11:0] + UNSIGNEDDECRADIX + + + dt_a_o[71:0] + dt_a_o[71:0] + HEXRADIX + + + + CORE_WMEM + label + + wmem_addr_o[9:0] + wmem_addr_o[9:0] + UNSIGNEDDECRADIX + #FFA500 + true + + + wmem_r_dt_i[167:0] + wmem_r_dt_i[167:0] + #FFA500 + true + + + wmem_data + label + #FFA500 + true + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + + CORE_PIPELINE + label + + CPU_STAGE_1 + label + + r_mem_rst + r_mem_rst + + + r_if_op_code[15:0] + r_if_op_code[15:0] + + + r_if_op_data[55:0] + r_if_op_data[55:0] + + + + CPU_STAGE_2 + label + + PC_curr[11:0] + PC_curr[11:0] + UNSIGNEDDECRADIX + + + PC_prev[11:0] + PC_prev[11:0] + UNSIGNEDDECRADIX + + + + CPU_STAGE_3 + label + + rd_ctrl + rd_ctrl + + + rd_reg + rd_reg + + + + CPU_STAGE_4 + label + + x1_ctrl + x1_ctrl + + + + CPU_STAGE_5 + label + + x2_ctrl + x2_ctrl + + + + + HAZARD_CTRL + label + + clk_i + clk_i + + + rst_ni + rst_ni + + + halt_i + halt_i + + + rs_A_addr_i[0:1][5:0] + rs_A_addr_i[0:1][5:0] + + + rs_A_dt_i[0:1][31:0] + rs_A_dt_i[0:1][31:0] + + + rs_D_addr_i[0:1][6:0] + rs_D_addr_i[0:1][6:0] + + + rs_D_dt_i[0:1][31:0] + rs_D_dt_i[0:1][31:0] + + + id_reg_i + id_reg_i + + + rd_reg_i + rd_reg_i + + + x1_reg_i + x1_reg_i + + + x2_reg_i + x2_reg_i + + + wr_reg_i + wr_reg_i + + + rd_periph_use + rd_periph_use + + + x1_periph_use + x1_periph_use + + + x2_periph_use + x2_periph_use + + + id_wmem_we + id_wmem_we + + + id_flag_used + id_flag_used + + + flag_we + flag_we + + + id_jmp_i + id_jmp_i + + + x1_alu_dt_i[31:0] + x1_alu_dt_i[31:0] + + + x2_alu_dt_i[31:0] + x2_alu_dt_i[31:0] + + + x2_dmem_dt_i[31:0] + x2_dmem_dt_i[31:0] + + + rd_imm_dt_i[31:0] + rd_imm_dt_i[31:0] + + + x1_imm_dt_i[31:0] + x1_imm_dt_i[31:0] + + + x2_imm_dt_i[31:0] + x2_imm_dt_i[31:0] + + + reg_A_dt_o[0:1][31:0] + reg_A_dt_o[0:1][31:0] + + + reg_D_dt_o[0:1][31:0] + reg_D_dt_o[0:1][31:0] + + + bubble_id_o + bubble_id_o + + + bubble_rd_o + bubble_rd_o + + + + FullPathName + [0][47:0] + [0][47:0] + UNSIGNEDDECRADIX + #00FFFF + true + + + FullPathName + [0] + [0] + + + FullPathName + [0] + [0] + + + FullPathName + [0] + [0] + + + [14][31:0] + [14][31:0] + UNSIGNEDDECRADIX + + + core_en + core_en + #00FFFF + true + + + core_st[31:0] + core_st[31:0] + #FF00FF + true + + + time_st[31:0] + time_st[31:0] + #FF00FF + true + + + time_abs_i[47:0] + time_abs_i[47:0] + HEXRADIX + #FFFF00 + true + + + DISPATCHER_WAVE_FIFO_0 + label + + + wr_clk_i + wr_clk_i + + + wr_rst_ni + wr_rst_ni + + + wr_en_i + wr_en_i + + + push_i + push_i + + + data_i[215:0] + data_i[215:0] + + + flush_i + flush_i + + + async_full_o + async_full_o + + + rd_clk_i + rd_clk_i + + + rd_rst_ni + rd_rst_ni + + + rd_en_i + rd_en_i + + + pop_i + pop_i + + + data_o[215:0] + data_o[215:0] + + + async_empty_o + async_empty_o + + + + FullPathName + [0] + [0] + + + DISPATCHER_TRIG_FIFO_0 + label + + + wr_clk_i + wr_clk_i + + + wr_rst_ni + wr_rst_ni + + + wr_en_i + wr_en_i + + + push_i + push_i + + + data_i[48:0] + data_i[48:0] + + + rd_clk_i + rd_clk_i + + + rd_rst_ni + rd_rst_ni + + + rd_en_i + rd_en_i + + + pop_i + pop_i + + + data_o[48:0] + data_o[48:0] + + + flush_i + flush_i + + + async_empty_o + async_empty_o + + + async_full_o + async_full_o + + + + FullPathName + [0] + [0] + + + FullPathName + [0] + [0] + + + FullPathName + [0] + [0] + + + TPROC_OUTPUTS + label + + + trig_0_o + trig_0_o + #00FFFF + true + + + port_0_dt_o[7:0] + port_0_dt_o[7:0] + #00FFFF + true + + + m0_axis_tdata[167:0] + m0_axis_tdata[167:0] + #00FFFF + true + + + m0_axis_tvalid + m0_axis_tvalid + #00FFFF + true + + + + FullPathName + [0] + [0] + + + FullPathName + [0] + [0] + + + FullPathName + [0] + [0] + + + FullPathName + [0] + [0] + + + FullPathName + [0] + [0] + + + FullPathName + [0] + [0] + + + xreg_TPROC_CFG[15:0] + xreg_TPROC_CFG[15:0] + + + xreg_TPROC_DBG[15:0] + xreg_TPROC_DBG[15:0] + + diff --git a/firmware/ip/qick_processor/src/tb/tb_qproc_issue37.wcfg b/firmware/ip/qick_processor/src/tb/tb_qproc_issue37.wcfg new file mode 100644 index 0000000..22b6850 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/tb_qproc_issue37.wcfg @@ -0,0 +1,853 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ps_clk_i + ps_clk_i + + + proc_start_i + proc_start_i + + + proc_stop_i + proc_stop_i + + + xreg_TPROC_CTRL[15:0] + xreg_TPROC_CTRL[15:0] + UNSIGNEDDECRADIX + + + xreg_TPROC_CFG[15:0] + xreg_TPROC_CFG[15:0] + + + c_clk_i + c_clk_i + + + some_fifo_full + some_fifo_full + + + core_st[31:0] + core_st[31:0] + #FF00FF + true + + + c_pmem_addr_i[11:0] + c_pmem_addr_i[11:0] + + + t_clk_i + t_clk_i + + + time_st[31:0] + time_st[31:0] + #FF00FF + true + + + t_core_rst_prev_net + t_core_rst_prev_net + + + core_rst_run_p + core_rst_run_p + + + time_rst_run_p + time_rst_run_p + + + RAM[0:4095][71:0] + RAM[0:4095][71:0] + HEXRADIX + + + QPROC_CTRL + label + + proc_start_io + proc_start_io + + + proc_stop_io + proc_stop_io + + + core_start_i + core_start_i + + + core_stop_i + core_stop_i + + + ctrl_c_stop + ctrl_c_stop + + + ctrl_c_rst_run + ctrl_c_rst_run + + + ctrl_c_run + ctrl_c_run + + + ctrl_c_rst_stop + ctrl_c_rst_stop + + + ctrl_c_step + ctrl_c_step + + + core_st[31:0] + core_st[31:0] + #FF00FF + true + + + some_fifo_full + some_fifo_full + + + fifo_ok + fifo_ok + + + core_en + core_en + + + en_i + en_i + + + halt + halt + + + fetch_en + fetch_en + + + + pulse_sync_o + pulse_sync_o + #FFA500 + true + + + out_port_data + out_port_data + + + + DEBUG_OUT + label + + ps_debug_do[31:0] + ps_debug_do[31:0] + + + c_core_do[31:0] + c_core_do[31:0] + + + c_debug_do[31:0] + c_debug_do[31:0] + + + c_time_usr_do[31:0] + c_time_usr_do[31:0] + SIGNEDDECRADIX + + + c_time_ref_do[31:0] + c_time_ref_do[31:0] + UNSIGNEDDECRADIX + + + c_port_do[31:0] + c_port_do[31:0] + + + t_debug_do[31:0] + t_debug_do[31:0] + + + t_fifo_do[31:0] + t_fifo_do[31:0] + + + t_time_abs_o[47:0] + t_time_abs_o[47:0] + UNSIGNEDDECRADIX + + + + some_fifo_full + some_fifo_full + #00FFFF + true + + + core_en + core_en + #00FFFF + true + + + halt + halt + #00FFFF + true + + + stall + stall + + + port_we + port_we + + + port_o + port_o + + + t_time_abs_o[47:0] + t_time_abs_o[47:0] + UNSIGNEDDECRADIX + + + label + [0][167:0] + [0][167:0] + m_axis_tdata[0][167:0] + #FF00FF + true + + + label + [0] + [0] + m_axis_tvalid[0] + #FF00FF + true + + + DISPATCHER_WAVE_FIFO_0 + label + + + wr_clk_i + wr_clk_i + + + wr_rst_ni + wr_rst_ni + + + wr_en_i + wr_en_i + + + push_i + push_i + + + data_i[215:0] + data_i[215:0] + + + time + label + UNSIGNEDDECRADIX + + [31] + [31] + + + [30] + [30] + + + [29] + [29] + + + [28] + [28] + + + [27] + [27] + + + [26] + [26] + + + [25] + [25] + + + [24] + [24] + + + [23] + [23] + + + [22] + [22] + + + [21] + [21] + + + [20] + [20] + + + [19] + [19] + + + [18] + [18] + + + [17] + [17] + + + [16] + [16] + + + [15] + [15] + + + [14] + [14] + + + [13] + [13] + + + [12] + [12] + + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + data_i + label + + [59] + [59] + + + [58] + [58] + + + [57] + [57] + + + [56] + [56] + + + [55] + [55] + + + [54] + [54] + + + [53] + [53] + + + [52] + [52] + + + [51] + [51] + + + [50] + [50] + + + [49] + [49] + + + [48] + [48] + + + + async_full_o + async_full_o + + + rd_clk_i + rd_clk_i + + + rd_rst_ni + rd_rst_ni + + + rd_en_i + rd_en_i + + + pop_i + pop_i + + + data_o[215:0] + data_o[215:0] + + + async_empty_o + async_empty_o + + + flush_i + flush_i + + + + CORE_PMEM + label + + + clk_a_i + clk_a_i + + + en_a_i + en_a_i + + + addr_a_i[11:0] + addr_a_i[11:0] + UNSIGNEDDECRADIX + + + dt_a_o[71:0] + dt_a_o[71:0] + HEXRADIX + + + + CORE_WMEM + label + + + wmem_addr_o[9:0] + wmem_addr_o[9:0] + UNSIGNEDDECRADIX + #FFA500 + true + + + wmem_r_dt_i[167:0] + wmem_r_dt_i[167:0] + #FFA500 + true + + + wmem_data + label + #FFA500 + true + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + + + + label + [0] + [0] + c_fifo_wave_push[0] + + + label + [0] + [0] + c_fifo_wave_push_r[0] + #00FF00 + true + + + label + [0] + [0] + c_fifo_wave_push_s[0] + #FFFF00 + true + + + c_fifo_data_in_r[167:0] + c_fifo_data_in_r[167:0] + #FFFF00 + true + + + x1_rsA0_dt[31:0] + x1_rsA0_dt[31:0] + + + .cfg_addr_imm + .cfg_addr_imm + + + r_rd_imm_addr[10:0] + r_rd_imm_addr[10:0] + + + [0][31:0] + [0][31:0] + + + CPU_STAGE_1 + label + + r_mem_rst + r_mem_rst + + + r_if_op_code[15:0] + r_if_op_code[15:0] + + + r_if_op_data[55:0] + r_if_op_data[55:0] + + + + CPU_STAGE_2 + label + + PC_curr[11:0] + PC_curr[11:0] + UNSIGNEDDECRADIX + + + PC_prev[11:0] + PC_prev[11:0] + UNSIGNEDDECRADIX + + + + CPU_STAGE_3 + label + + rd_ctrl + rd_ctrl + + + rd_reg + rd_reg + + + + CPU_STAGE_4 + label + + x1_ctrl + x1_ctrl + + + + CPU_STAGE_5 + label + + x2_ctrl + x2_ctrl + + + + HAZARD_CTRL + label + + + clk_i + clk_i + + + rst_ni + rst_ni + + + halt_i + halt_i + + + rs_A_addr_i[0:1][5:0] + rs_A_addr_i[0:1][5:0] + + + rs_A_dt_i[0:1][31:0] + rs_A_dt_i[0:1][31:0] + + + rs_D_addr_i[0:1][6:0] + rs_D_addr_i[0:1][6:0] + + + rs_D_dt_i[0:1][31:0] + rs_D_dt_i[0:1][31:0] + + + id_reg_i + id_reg_i + + + rd_reg_i + rd_reg_i + + + x1_reg_i + x1_reg_i + + + x2_reg_i + x2_reg_i + + + wr_reg_i + wr_reg_i + + + rd_periph_use + rd_periph_use + + + x1_periph_use + x1_periph_use + + + x2_periph_use + x2_periph_use + + + id_wmem_we + id_wmem_we + + + id_flag_used + id_flag_used + + + flag_we + flag_we + + + id_jmp_i + id_jmp_i + + + x1_alu_dt_i[31:0] + x1_alu_dt_i[31:0] + + + x2_alu_dt_i[31:0] + x2_alu_dt_i[31:0] + + + x2_dmem_dt_i[31:0] + x2_dmem_dt_i[31:0] + + + rd_imm_dt_i[31:0] + rd_imm_dt_i[31:0] + + + x1_imm_dt_i[31:0] + x1_imm_dt_i[31:0] + + + x2_imm_dt_i[31:0] + x2_imm_dt_i[31:0] + + + reg_A_dt_o[0:1][31:0] + reg_A_dt_o[0:1][31:0] + + + reg_D_dt_o[0:1][31:0] + reg_D_dt_o[0:1][31:0] + + + bubble_id_o + bubble_id_o + + + bubble_rd_o + bubble_rd_o + + + + id_type_wp + id_type_wp + + + port_we + port_we + + + stall_id_wp + stall_id_wp + + + [0][31:0] + [0][31:0] + + + [0][167:0] + [0][167:0] + + + [0][71:0] + [0][71:0] + + diff --git a/firmware/ip/qick_processor/src/tb/wave.bin b/firmware/ip/qick_processor/src/tb/wave.bin new file mode 100644 index 0000000..ed64e20 --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/wave.bin @@ -0,0 +1,16 @@ +// WAVE Memory File +// CONFIG_16 _ LENGHT 32 _ GAIN_32 _ ENV_24 _ PHASE_32 _ FREQ_32 +_0000000000100000_00000000000000000000000000010000_00000000000000000000000000001000_000000000000000000000100_00000000000000000000000000000010_00000000000000000000000000000001 +_1111111111111111_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000000001_00000000000000000000000000000001 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000000010_00000000000000000000000000000010 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000000011_00000000000000000000000000000011 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000000100_00000000000000000000000000000100 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000000101_00000000000000000000000000000101 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000000110_00000000000000000000000000000110 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000000111_00000000000000000000000000000111 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000001000_00000000000000000000000000001000 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000001001_00000000000000000000000000001001 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000001010_00000000000000000000000000001010 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000001011_00000000000000000000000000001011 +_0000000000000000_00000000000000000000000000000000_00000000000000000000000000000000_000000000000000000000000_00000000000000000000000000001100_00000000000000000000000000001100 + diff --git a/firmware/ip/qick_processor/src/tb/wave_issue35.mem b/firmware/ip/qick_processor/src/tb/wave_issue35.mem new file mode 100644 index 0000000..847b5cc --- /dev/null +++ b/firmware/ip/qick_processor/src/tb/wave_issue35.mem @@ -0,0 +1,10 @@ +// WMEM content +080000002600007ffe000000000000000014d55556 +090000002600003fff000000000000000014d55556 +080000002600007ffe000000260000000014d55556 +080000004c00007ffe000000000000000014d55556 +090000004d00007ffe000000000000000014d55556 +080000002600007ffe000000004000000014d55556 +090000002600003fff000000004000000014d55556 +080000002600007ffe000000264000000014d55556 +0800000003000000000000000000000000e0bfffff diff --git a/firmware/ip/qick_processor/xgui/qick_processor_v2_0.tcl b/firmware/ip/qick_processor/xgui/qick_processor_v2_0.tcl new file mode 100644 index 0000000..132bedb --- /dev/null +++ b/firmware/ip/qick_processor/xgui/qick_processor_v2_0.tcl @@ -0,0 +1,443 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_static_text $IPINST -name "Introduction" -parent ${Page_0} -text {Values for Memory size, port quantity, and register amount can be modified in order to make a smaller and faster processor} + #Adding Group + set Process [ipgui::add_group $IPINST -name "Process" -parent ${Page_0} -display_name {Processor Options}] + set_property tooltip {Process} ${Process} + ipgui::add_param $IPINST -name "REG_AW" -parent ${Process} + ipgui::add_static_text $IPINST -name "dreg" -parent ${Process} -text {User can define the amount of 32-bits General Purpouse Data registers. This value impacts on the max freq of the processor.} + #Adding Group + set Memory_Configuration [ipgui::add_group $IPINST -name "Memory Configuration" -parent ${Process} -display_name {Core Memory}] + ipgui::add_param $IPINST -name "PMEM_AW" -parent ${Memory_Configuration} + set DMEM_AW [ipgui::add_param $IPINST -name "DMEM_AW" -parent ${Memory_Configuration}] + set_property tooltip {DmemAw} ${DMEM_AW} + ipgui::add_param $IPINST -name "WMEM_AW" -parent ${Memory_Configuration} + + #Adding Group + set IN_Port_Configuration [ipgui::add_group $IPINST -name "IN Port Configuration" -parent ${Process} -display_name {IN Configuration} -layout horizontal] + #Adding Group + set QICK_PORTS [ipgui::add_group $IPINST -name "QICK PORTS" -parent ${IN_Port_Configuration}] + set_property tooltip {G_PORTS} ${QICK_PORTS} + ipgui::add_param $IPINST -name "IN_PORT_QTY" -parent ${QICK_PORTS} + ipgui::add_param $IPINST -name "EXT_FLAG" -parent ${QICK_PORTS} -widget checkBox + + #Adding Group + set QICK_CONTROL [ipgui::add_group $IPINST -name "QICK CONTROL" -parent ${IN_Port_Configuration}] + set_property tooltip {GCTRL} ${QICK_CONTROL} + set IO_CTRL [ipgui::add_param $IPINST -name "IO_CTRL" -parent ${QICK_CONTROL} -widget checkBox] + set_property tooltip {External Inputs Qick Control Pins} ${IO_CTRL} + ipgui::add_param $IPINST -name "TIME_CTRL" -parent ${QICK_CONTROL} -widget checkBox + ipgui::add_param $IPINST -name "CORE_CTRL" -parent ${QICK_CONTROL} -widget checkBox + + + #Adding Group + set OUT_Port_Configuration [ipgui::add_group $IPINST -name "OUT Port Configuration" -parent ${Process} -display_name {OUT Configuration} -layout horizontal] + set_property tooltip {OUT Configuration} ${OUT_Port_Configuration} + #Adding Group + set GROUP1 [ipgui::add_group $IPINST -name "GROUP1" -parent ${OUT_Port_Configuration} -display_name {QICK PORTS}] + set_property tooltip {G_PORTS} ${GROUP1} + ipgui::add_param $IPINST -name "OUT_TRIG_QTY" -parent ${GROUP1} + ipgui::add_param $IPINST -name "OUT_WPORT_QTY" -parent ${GROUP1} + ipgui::add_param $IPINST -name "OUT_DPORT_QTY" -parent ${GROUP1} + ipgui::add_param $IPINST -name "OUT_DPORT_DW" -parent ${GROUP1} + ipgui::add_param $IPINST -name "FIFO_DEPTH" -parent ${GROUP1} -widget comboBox + + #Adding Group + set GROUP [ipgui::add_group $IPINST -name "GROUP" -parent ${OUT_Port_Configuration} -display_name {QICK SIGNALS}] + set_property tooltip {G_SIGNALS} ${GROUP} + ipgui::add_param $IPINST -name "OUT_TIME" -parent ${GROUP} -widget checkBox + ipgui::add_param $IPINST -name "GEN_SYNC" -parent ${GROUP} -widget checkBox + + + #Adding Group + set Options [ipgui::add_group $IPINST -name "Options" -parent ${Process} -display_name {Internal Peripherals} -layout horizontal] + set LFSR [ipgui::add_param $IPINST -name "LFSR" -parent ${Options} -widget checkBox] + set_property tooltip {Linear Feedback Shit Register} ${LFSR} + ipgui::add_param $IPINST -name "ARITH" -parent ${Options} -widget checkBox + set DIVIDER [ipgui::add_param $IPINST -name "DIVIDER" -parent ${Options} -widget checkBox] + set_property tooltip {32-bit Integer Divider (Quotient - Reminder)} ${DIVIDER} + ipgui::add_param $IPINST -name "TIME_READ" -parent ${Options} -widget checkBox + + #Adding Group + set External_Peripherals [ipgui::add_group $IPINST -name "External Peripherals" -parent ${Process} -display_name {External Peripherals Interfaces}] + ipgui::add_param $IPINST -name "QNET" -parent ${External_Peripherals} -widget checkBox + ipgui::add_param $IPINST -name "QCOM" -parent ${External_Peripherals} -widget checkBox + ipgui::add_param $IPINST -name "CUSTOM_PERIPH" -parent ${External_Peripherals} -widget comboBox + + + #Adding Group + set Debug [ipgui::add_group $IPINST -name "Debug" -parent ${Page_0}] + ipgui::add_param $IPINST -name "DEBUG" -parent ${Debug} -widget comboBox + + + +} + +proc update_PARAM_VALUE.ARITH { PARAM_VALUE.ARITH } { + # Procedure called to update ARITH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ARITH { PARAM_VALUE.ARITH } { + # Procedure called to validate ARITH + return true +} + +proc update_PARAM_VALUE.CALL_DEPTH { PARAM_VALUE.CALL_DEPTH } { + # Procedure called to update CALL_DEPTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CALL_DEPTH { PARAM_VALUE.CALL_DEPTH } { + # Procedure called to validate CALL_DEPTH + return true +} + +proc update_PARAM_VALUE.CORE_CTRL { PARAM_VALUE.CORE_CTRL } { + # Procedure called to update CORE_CTRL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CORE_CTRL { PARAM_VALUE.CORE_CTRL } { + # Procedure called to validate CORE_CTRL + return true +} + +proc update_PARAM_VALUE.CUSTOM_PERIPH { PARAM_VALUE.CUSTOM_PERIPH } { + # Procedure called to update CUSTOM_PERIPH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CUSTOM_PERIPH { PARAM_VALUE.CUSTOM_PERIPH } { + # Procedure called to validate CUSTOM_PERIPH + return true +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + +proc update_PARAM_VALUE.DIVIDER { PARAM_VALUE.DIVIDER } { + # Procedure called to update DIVIDER when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DIVIDER { PARAM_VALUE.DIVIDER } { + # Procedure called to validate DIVIDER + return true +} + +proc update_PARAM_VALUE.DMEM_AW { PARAM_VALUE.DMEM_AW } { + # Procedure called to update DMEM_AW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMEM_AW { PARAM_VALUE.DMEM_AW } { + # Procedure called to validate DMEM_AW + return true +} + +proc update_PARAM_VALUE.DUAL_CORE { PARAM_VALUE.DUAL_CORE } { + # Procedure called to update DUAL_CORE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DUAL_CORE { PARAM_VALUE.DUAL_CORE } { + # Procedure called to validate DUAL_CORE + return true +} + +proc update_PARAM_VALUE.EXT_FLAG { PARAM_VALUE.EXT_FLAG } { + # Procedure called to update EXT_FLAG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.EXT_FLAG { PARAM_VALUE.EXT_FLAG } { + # Procedure called to validate EXT_FLAG + return true +} + +proc update_PARAM_VALUE.FIFO_DEPTH { PARAM_VALUE.FIFO_DEPTH } { + # Procedure called to update FIFO_DEPTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FIFO_DEPTH { PARAM_VALUE.FIFO_DEPTH } { + # Procedure called to validate FIFO_DEPTH + return true +} + +proc update_PARAM_VALUE.GEN_SYNC { PARAM_VALUE.GEN_SYNC } { + # Procedure called to update GEN_SYNC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.GEN_SYNC { PARAM_VALUE.GEN_SYNC } { + # Procedure called to validate GEN_SYNC + return true +} + +proc update_PARAM_VALUE.IN_PORT_QTY { PARAM_VALUE.IN_PORT_QTY } { + # Procedure called to update IN_PORT_QTY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IN_PORT_QTY { PARAM_VALUE.IN_PORT_QTY } { + # Procedure called to validate IN_PORT_QTY + return true +} + +proc update_PARAM_VALUE.IO_CTRL { PARAM_VALUE.IO_CTRL } { + # Procedure called to update IO_CTRL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IO_CTRL { PARAM_VALUE.IO_CTRL } { + # Procedure called to validate IO_CTRL + return true +} + +proc update_PARAM_VALUE.LFSR { PARAM_VALUE.LFSR } { + # Procedure called to update LFSR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.LFSR { PARAM_VALUE.LFSR } { + # Procedure called to validate LFSR + return true +} + +proc update_PARAM_VALUE.OUT_DPORT_DW { PARAM_VALUE.OUT_DPORT_DW } { + # Procedure called to update OUT_DPORT_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_DPORT_DW { PARAM_VALUE.OUT_DPORT_DW } { + # Procedure called to validate OUT_DPORT_DW + return true +} + +proc update_PARAM_VALUE.OUT_DPORT_QTY { PARAM_VALUE.OUT_DPORT_QTY } { + # Procedure called to update OUT_DPORT_QTY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_DPORT_QTY { PARAM_VALUE.OUT_DPORT_QTY } { + # Procedure called to validate OUT_DPORT_QTY + return true +} + +proc update_PARAM_VALUE.OUT_TIME { PARAM_VALUE.OUT_TIME } { + # Procedure called to update OUT_TIME when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_TIME { PARAM_VALUE.OUT_TIME } { + # Procedure called to validate OUT_TIME + return true +} + +proc update_PARAM_VALUE.OUT_TRIG_QTY { PARAM_VALUE.OUT_TRIG_QTY } { + # Procedure called to update OUT_TRIG_QTY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_TRIG_QTY { PARAM_VALUE.OUT_TRIG_QTY } { + # Procedure called to validate OUT_TRIG_QTY + return true +} + +proc update_PARAM_VALUE.OUT_WPORT_QTY { PARAM_VALUE.OUT_WPORT_QTY } { + # Procedure called to update OUT_WPORT_QTY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_WPORT_QTY { PARAM_VALUE.OUT_WPORT_QTY } { + # Procedure called to validate OUT_WPORT_QTY + return true +} + +proc update_PARAM_VALUE.PMEM_AW { PARAM_VALUE.PMEM_AW } { + # Procedure called to update PMEM_AW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PMEM_AW { PARAM_VALUE.PMEM_AW } { + # Procedure called to validate PMEM_AW + return true +} + +proc update_PARAM_VALUE.QCOM { PARAM_VALUE.QCOM } { + # Procedure called to update QCOM when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QCOM { PARAM_VALUE.QCOM } { + # Procedure called to validate QCOM + return true +} + +proc update_PARAM_VALUE.QNET { PARAM_VALUE.QNET } { + # Procedure called to update QNET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QNET { PARAM_VALUE.QNET } { + # Procedure called to validate QNET + return true +} + +proc update_PARAM_VALUE.REG_AW { PARAM_VALUE.REG_AW } { + # Procedure called to update REG_AW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.REG_AW { PARAM_VALUE.REG_AW } { + # Procedure called to validate REG_AW + return true +} + +proc update_PARAM_VALUE.TIME_CTRL { PARAM_VALUE.TIME_CTRL } { + # Procedure called to update TIME_CTRL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TIME_CTRL { PARAM_VALUE.TIME_CTRL } { + # Procedure called to validate TIME_CTRL + return true +} + +proc update_PARAM_VALUE.TIME_READ { PARAM_VALUE.TIME_READ } { + # Procedure called to update TIME_READ when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TIME_READ { PARAM_VALUE.TIME_READ } { + # Procedure called to validate TIME_READ + return true +} + +proc update_PARAM_VALUE.WMEM_AW { PARAM_VALUE.WMEM_AW } { + # Procedure called to update WMEM_AW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.WMEM_AW { PARAM_VALUE.WMEM_AW } { + # Procedure called to validate WMEM_AW + return true +} + + +proc update_MODELPARAM_VALUE.PMEM_AW { MODELPARAM_VALUE.PMEM_AW PARAM_VALUE.PMEM_AW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PMEM_AW}] ${MODELPARAM_VALUE.PMEM_AW} +} + +proc update_MODELPARAM_VALUE.DMEM_AW { MODELPARAM_VALUE.DMEM_AW PARAM_VALUE.DMEM_AW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMEM_AW}] ${MODELPARAM_VALUE.DMEM_AW} +} + +proc update_MODELPARAM_VALUE.WMEM_AW { MODELPARAM_VALUE.WMEM_AW PARAM_VALUE.WMEM_AW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.WMEM_AW}] ${MODELPARAM_VALUE.WMEM_AW} +} + +proc update_MODELPARAM_VALUE.REG_AW { MODELPARAM_VALUE.REG_AW PARAM_VALUE.REG_AW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.REG_AW}] ${MODELPARAM_VALUE.REG_AW} +} + +proc update_MODELPARAM_VALUE.IN_PORT_QTY { MODELPARAM_VALUE.IN_PORT_QTY PARAM_VALUE.IN_PORT_QTY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IN_PORT_QTY}] ${MODELPARAM_VALUE.IN_PORT_QTY} +} + +proc update_MODELPARAM_VALUE.OUT_DPORT_QTY { MODELPARAM_VALUE.OUT_DPORT_QTY PARAM_VALUE.OUT_DPORT_QTY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_DPORT_QTY}] ${MODELPARAM_VALUE.OUT_DPORT_QTY} +} + +proc update_MODELPARAM_VALUE.OUT_WPORT_QTY { MODELPARAM_VALUE.OUT_WPORT_QTY PARAM_VALUE.OUT_WPORT_QTY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_WPORT_QTY}] ${MODELPARAM_VALUE.OUT_WPORT_QTY} +} + +proc update_MODELPARAM_VALUE.LFSR { MODELPARAM_VALUE.LFSR PARAM_VALUE.LFSR } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LFSR}] ${MODELPARAM_VALUE.LFSR} +} + +proc update_MODELPARAM_VALUE.DIVIDER { MODELPARAM_VALUE.DIVIDER PARAM_VALUE.DIVIDER } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DIVIDER}] ${MODELPARAM_VALUE.DIVIDER} +} + +proc update_MODELPARAM_VALUE.ARITH { MODELPARAM_VALUE.ARITH PARAM_VALUE.ARITH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ARITH}] ${MODELPARAM_VALUE.ARITH} +} + +proc update_MODELPARAM_VALUE.TIME_READ { MODELPARAM_VALUE.TIME_READ PARAM_VALUE.TIME_READ } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TIME_READ}] ${MODELPARAM_VALUE.TIME_READ} +} + +proc update_MODELPARAM_VALUE.DUAL_CORE { MODELPARAM_VALUE.DUAL_CORE PARAM_VALUE.DUAL_CORE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DUAL_CORE}] ${MODELPARAM_VALUE.DUAL_CORE} +} + +proc update_MODELPARAM_VALUE.IO_CTRL { MODELPARAM_VALUE.IO_CTRL PARAM_VALUE.IO_CTRL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IO_CTRL}] ${MODELPARAM_VALUE.IO_CTRL} +} + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + +proc update_MODELPARAM_VALUE.CUSTOM_PERIPH { MODELPARAM_VALUE.CUSTOM_PERIPH PARAM_VALUE.CUSTOM_PERIPH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CUSTOM_PERIPH}] ${MODELPARAM_VALUE.CUSTOM_PERIPH} +} + +proc update_MODELPARAM_VALUE.OUT_DPORT_DW { MODELPARAM_VALUE.OUT_DPORT_DW PARAM_VALUE.OUT_DPORT_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_DPORT_DW}] ${MODELPARAM_VALUE.OUT_DPORT_DW} +} + +proc update_MODELPARAM_VALUE.OUT_TRIG_QTY { MODELPARAM_VALUE.OUT_TRIG_QTY PARAM_VALUE.OUT_TRIG_QTY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_TRIG_QTY}] ${MODELPARAM_VALUE.OUT_TRIG_QTY} +} + +proc update_MODELPARAM_VALUE.FIFO_DEPTH { MODELPARAM_VALUE.FIFO_DEPTH PARAM_VALUE.FIFO_DEPTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FIFO_DEPTH}] ${MODELPARAM_VALUE.FIFO_DEPTH} +} + +proc update_MODELPARAM_VALUE.EXT_FLAG { MODELPARAM_VALUE.EXT_FLAG PARAM_VALUE.EXT_FLAG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.EXT_FLAG}] ${MODELPARAM_VALUE.EXT_FLAG} +} + +proc update_MODELPARAM_VALUE.QCOM { MODELPARAM_VALUE.QCOM PARAM_VALUE.QCOM } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QCOM}] ${MODELPARAM_VALUE.QCOM} +} + +proc update_MODELPARAM_VALUE.CALL_DEPTH { MODELPARAM_VALUE.CALL_DEPTH PARAM_VALUE.CALL_DEPTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CALL_DEPTH}] ${MODELPARAM_VALUE.CALL_DEPTH} +} + +proc update_MODELPARAM_VALUE.OUT_TIME { MODELPARAM_VALUE.OUT_TIME PARAM_VALUE.OUT_TIME } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_TIME}] ${MODELPARAM_VALUE.OUT_TIME} +} + +proc update_MODELPARAM_VALUE.QNET { MODELPARAM_VALUE.QNET PARAM_VALUE.QNET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QNET}] ${MODELPARAM_VALUE.QNET} +} + +proc update_MODELPARAM_VALUE.TIME_CTRL { MODELPARAM_VALUE.TIME_CTRL PARAM_VALUE.TIME_CTRL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TIME_CTRL}] ${MODELPARAM_VALUE.TIME_CTRL} +} + +proc update_MODELPARAM_VALUE.CORE_CTRL { MODELPARAM_VALUE.CORE_CTRL PARAM_VALUE.CORE_CTRL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CORE_CTRL}] ${MODELPARAM_VALUE.CORE_CTRL} +} + +proc update_MODELPARAM_VALUE.GEN_SYNC { MODELPARAM_VALUE.GEN_SYNC PARAM_VALUE.GEN_SYNC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.GEN_SYNC}] ${MODELPARAM_VALUE.GEN_SYNC} +} + diff --git a/firmware/ip/qick_sg_translator/component.xml b/firmware/ip/qick_sg_translator/component.xml new file mode 100644 index 0000000..417746e --- /dev/null +++ b/firmware/ip/qick_sg_translator/component.xml @@ -0,0 +1,736 @@ + + + user.org + user + sg_translator + 1.0 + + + m_int4_axis + + + + + + + TDATA + + + m_int4_axis_tdata + + + + + TVALID + + + m_int4_axis_tvalid + + + + + TREADY + + + m_int4_axis_tready + + + + + + + false + + + + + + m_mux4_axis + + + + + + + TDATA + + + m_mux4_axis_tdata + + + + + TVALID + + + m_mux4_axis_tvalid + + + + + TREADY + + + m_mux4_axis_tready + + + + + + + false + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + aclk + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + m_int4_axis:m_mux4_axis:s_tproc_axis:m_gen_v6_axis:m_readout_v3_axis + + + ASSOCIATED_RESET + aresetn + + + + + m_gen_v6_axis + + + + true + + + + TDATA + + + m_gen_v6_axis_tdata + + + + + TVALID + + + m_gen_v6_axis_tvalid + + + + + TREADY + + + m_gen_v6_axis_tready + + + + + + NUM_READ_OUTSTANDING + + + + NUM_WRITE_OUTSTANDING + + + + + + + true + + + + + + s_tproc_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + m_readout_v3_axis + + + + true + + + + TVALID + + + m_readout_axis_tvalid + + + + + TREADY + + + m_readout_axis_tready + + + + + TDATA + + + m_readout_axis_tdata + + + + + + + false + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + sg_translator + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + ef542ab9 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + sg_translator + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + ef542ab9 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 7315fcc5 + + + + + + + aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 167 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_gen_v6_axis_tdata + + out + + 159 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_gen_v6_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_gen_v6_axis_tready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_int4_axis_tdata + + out + + 87 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_int4_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_int4_axis_tready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_mux4_axis_tdata + + out + + 39 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_mux4_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_mux4_axis_tready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_readout_axis_tdata + + out + + 87 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_readout_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_readout_axis_tready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + OUT_TYPE + Out Type + 0 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_ea9dd076 + 0 + 1 + 2 + 3 + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/sg_translator.v + verilogSource + CHECKSUM_ef542ab9 + IMPORTED_FILE + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/sg_translator.v + verilogSource + IMPORTED_FILE + + + + xilinx_xpgui_view_fileset + + xgui/sg_translator_v1_0.tcl + tclSource + CHECKSUM_7315fcc5 + XGUI_VERSION_2 + + + + qick_sg_translator + + + OUT_TYPE + Signal Generator Output Type + 0 + + + Component_Name + sg_translator_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + kintexu + + + /UserIP + + qick_sg_translator + package_project + 10 + 2024-03-19T19:59:06Z + + /home/mdifeder/Projects/20.2/IPs/axis_sg_translator + /home/mdifeder/Projects/20.2/IPs/axis_sg_translator + /home/mdifeder/Projects/20.2/IPs/axis_sg_translator + /home/mdifeder/Projects/20.2/IPs/axis_sg_translator + /home/mdifeder/Projects/20.2/IPs/axis_sg_translator + /home/mdifeder/Projects/20.2/IPs/axis_sg_translator + /home/mdifeder/Projects/20.2/IPs/axis_sg_translator + /home/mdifeder/Projects/20.2/IPs/axis_sg_translator + /home/mdifeder/Projects/20.2/IPs/axis_sg_translator + /home/mdifeder/Projects/20.2/IPs/axis_sg_translator + /home/mdifeder/Projects/20.2/IPs/axis_sg_translator + /home/mdifeder/Projects/20.2/IPs/axis_sg_translator + /home/mdifeder/Projects/20.2/IPs/axis_sg_translator + /home/mdifeder/Projects/20.2/IPs/axis_sg_translator + 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/home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + /home/mdifeder/Projects/ZCU216/q3diamond/ip/axis_sg_translator + + + + 2022.1 + + + + + + + + diff --git a/firmware/ip/qick_sg_translator/src/sg_translator.v b/firmware/ip/qick_sg_translator/src/sg_translator.v new file mode 100644 index 0000000..47531f4 --- /dev/null +++ b/firmware/ip/qick_sg_translator/src/sg_translator.v @@ -0,0 +1,152 @@ +/* +TRANSLATE from tProc_v2 to diferente Signals Souorces. + +// tProc-v2 OUT +// |-----------|-----------|-----------|-----------|-----------|-----------| +// | 167..152 | 151..120 | 119..88 | 87..64 | 63..32 | 31..0 | +// |-----------|-----------|-----------|-----------|-----------|-----------| +// | CONF | LENGHT | GAIN | ENV | PHASE | FREQ | +// | 16-bit | 32-bit | 32-bit | 24-bit | 32-bit | 32-bit | +// |-----------|-----------|-----------|-----------|-----------|-----------| + + +*/ +module sg_translator # ( + OUT_TYPE = 0 //(0:gen_v6, 0:int4_v1, 0:mux4_v1, ) +) ( +// Reset and clock. + input wire aresetn , + input wire aclk , +// IN WAVE PORT + input wire [167:0] s_axis_tdata , + input wire s_axis_tvalid , + output wire s_axis_tready , + // OUT DATA gen_v6 (SEL:0) + output wire [159:0] m_gen_v6_axis_tdata , + output wire m_gen_v6_axis_tvalid , + input wire m_gen_v6_axis_tready , + // OUT DATA int4_v1 (SEL:1) + output wire [87:0] m_int4_axis_tdata , + output wire m_int4_axis_tvalid , + input wire m_int4_axis_tready , + // OUT DATA mux4_v1 (SEL:2) + output wire [39:0] m_mux4_axis_tdata , + output wire m_mux4_axis_tvalid , + input wire m_mux4_axis_tready , + // OUT DATA readout_v3 (SEL:3) + output wire [87:0] m_readout_axis_tdata , + output wire m_readout_axis_tvalid , + input wire m_readout_axis_tready +); + +// GET Data from tPtoc_v2 +/////////////////////////////////////////////////////////////////////////////// +wire [31:0] freq, phase, gain, nsamp ; +wire [23:0] addr ; +wire [23:0] conf ; + +wire [1:0] outsel ; +wire mode, stdysel, phrst; + +assign conf = s_axis_tdata[167:152] ; +assign nsamp = s_axis_tdata[151:120] ; +assign gain = s_axis_tdata[119: 88] ; +assign addr = s_axis_tdata[ 87: 64] ; +assign phase = s_axis_tdata[ 63: 32] ; +assign freq = s_axis_tdata[ 31: 0] ; + +assign phrst = conf[4] ; +assign stdysel = conf[3] ; +assign mode = conf[2] ; +assign outsel = conf[1:0] ; + + +assign gen_v6_en = (OUT_TYPE == 0) ; +assign int4_en = (OUT_TYPE == 1) ; +assign mux4_en = (OUT_TYPE == 2) ; +assign readout_en = (OUT_TYPE == 3) ; + +// OUTPUTS + +/////////////////////////////////////////////////////////////////////////////// +assign s_axis_tready = ( gen_v6_en ) ? m_gen_v6_axis_tready : ( + ( int4_en ) ? m_int4_axis_tready : ( + ( mux4_en ) ? m_mux4_axis_tready : ( + ( readout_en ) ? m_readout_axis_tready : 0 ))); +/////////////////////////////////////////////////////////////////////////////// + + +/////////////////////////////////////////////////////////////////////////////// +// axis_signal_gen_v6 +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// | 159 .. 149 | 148 | 147 | 146 | 145 .. 144 | 143 .. 128 | 127 .. 112 | 111 .. 96 | 95 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +// | xxxx | phrst | stdysel | mode | outsel | nsamp | xxxx | gain | xxxx | addr | phase | freq | +// |------------|-------|---------|------|------------|------------|------------|-----------|----------|----------|----------|---------| +assign m_gen_v6_axis_tdata[159:149] = 0 ; +assign m_gen_v6_axis_tdata[148] = phrst ; +assign m_gen_v6_axis_tdata[147] = stdysel ; +assign m_gen_v6_axis_tdata[146] = mode ; +assign m_gen_v6_axis_tdata[145:144] = outsel ; +assign m_gen_v6_axis_tdata[143:128] = nsamp [15:0] ; +assign m_gen_v6_axis_tdata[127:112] = 0 ; +assign m_gen_v6_axis_tdata[111: 96] = gain [15:0] ; +assign m_gen_v6_axis_tdata[ 95: 80] = 0 ; +assign m_gen_v6_axis_tdata[ 79: 64] = addr [15:0] ; +assign m_gen_v6_axis_tdata[ 63: 32] = phase [31:0] ; +assign m_gen_v6_axis_tdata[ 31: 0] = freq [31:0] ; + +assign m_gen_v6_axis_tvalid = gen_v6_en ? s_axis_tvalid : 0 ; + + +/////////////////////////////////////////////////////////////////////////////// +// axis_sg_int4_v1 +// |-------|---------|------|----------|----------|----------|----------|----------|---------| +// | 84 | 83 | 82 | 81 .. 80 | 79 .. 64 | 63 .. 48 | 47 .. 32 | 31 .. 16 | 15 .. 0 | +// |-------|---------|------|----------|----------|----------|----------|----------|---------| +// | phrst | stdysel | mode | outsel | nsamp | gain | addr | phase | freq | +// | 1-bit | 1-bit | 1-bit| 2-bit | 16-bit | 16-bit | 16-bit | 16-bit | 16-bit| +// |-------|---------|------|----------|----------|----------|----------|----------|---------| +assign m_int4_axis_tdata[87:85] = 0 ; +assign m_int4_axis_tdata[84] = phrst ; +assign m_int4_axis_tdata[83] = stdysel ; +assign m_int4_axis_tdata[82] = mode ; +assign m_int4_axis_tdata[81:80] = outsel ; +assign m_int4_axis_tdata[79:64] = nsamp [15:0] ; +assign m_int4_axis_tdata[63:48] = gain [15:0] ; +assign m_int4_axis_tdata[47:32] = addr [15:0] ; +assign m_int4_axis_tdata[31:16] = phase [15:0] ; +assign m_int4_axis_tdata[15:0 ] = freq [15:0] ; + +assign m_int4_axis_tvalid = int4_en ? s_axis_tvalid : 0 ; + +/////////////////////////////////////////////////////////////////////////////// +// axis_sg_mux_4_v1 +// |----------|---------| +// | 39 .. 32 | 31 .. 0 | +// |----------|---------| +// | mask | nsamp | +// |----------|---------| +assign m_mux4_axis_tdata[39:32] = conf [7: 0] ; +assign m_mux4_axis_tdata[31:0] = nsamp [31:0] ; + +assign m_mux4_axis_tvalid = mux4_en ? s_axis_tvalid : 0 ; + +/////////////////////////////////////////////////////////////////////////////// +// axis_readout_v3 +// |----------|-------|------|----------|----------|----------|---------| +// | 87 .. 84 | 83 | 82 | 81 .. 80 | 79 .. 64 | 63 .. 32 | 31 .. 0 | +// |----------|-------|------|----------|----------|----------|---------| +// | xxxx | phrst | mode | outsel | nsamp | phase | freq | +// |----------|-------|------|----------|----------|----------|---------| +assign m_readout_axis_tdata[87:84] = 0 ; +assign m_readout_axis_tdata[83] = phrst ; +assign m_readout_axis_tdata[82] = mode ; +assign m_readout_axis_tdata[81:80] = outsel ; +assign m_readout_axis_tdata[79:64 ] = nsamp [15:0] ; +assign m_readout_axis_tdata[ 63: 32] = phase [31:0] ; +assign m_readout_axis_tdata[ 31: 0] = freq [31:0] ; + +assign m_readout_axis_tvalid = readout_en ? s_axis_tvalid : 0 ; + +endmodule diff --git a/firmware/ip/qick_sg_translator/xgui/qick_sg_translator_v1_0.tcl b/firmware/ip/qick_sg_translator/xgui/qick_sg_translator_v1_0.tcl new file mode 100644 index 0000000..9b06bbc --- /dev/null +++ b/firmware/ip/qick_sg_translator/xgui/qick_sg_translator_v1_0.tcl @@ -0,0 +1,22 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + ipgui::add_param $IPINST -name "OUT_TYPE" + +} + +proc update_PARAM_VALUE.OUT_TYPE { PARAM_VALUE.OUT_TYPE } { + # Procedure called to update OUT_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_TYPE { PARAM_VALUE.OUT_TYPE } { + # Procedure called to validate OUT_TYPE + return true +} + + +proc update_MODELPARAM_VALUE.OUT_TYPE { MODELPARAM_VALUE.OUT_TYPE PARAM_VALUE.OUT_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_TYPE}] ${MODELPARAM_VALUE.OUT_TYPE} +} + diff --git a/firmware/ip/qick_sg_translator/xgui/sg_translator_v1_0.tcl b/firmware/ip/qick_sg_translator/xgui/sg_translator_v1_0.tcl new file mode 100644 index 0000000..9b06bbc --- /dev/null +++ b/firmware/ip/qick_sg_translator/xgui/sg_translator_v1_0.tcl @@ -0,0 +1,22 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + ipgui::add_param $IPINST -name "OUT_TYPE" + +} + +proc update_PARAM_VALUE.OUT_TYPE { PARAM_VALUE.OUT_TYPE } { + # Procedure called to update OUT_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_TYPE { PARAM_VALUE.OUT_TYPE } { + # Procedure called to validate OUT_TYPE + return true +} + + +proc update_MODELPARAM_VALUE.OUT_TYPE { MODELPARAM_VALUE.OUT_TYPE PARAM_VALUE.OUT_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_TYPE}] ${MODELPARAM_VALUE.OUT_TYPE} +} + diff --git a/firmware/ip/qick_time_tagger/component.xml b/firmware/ip/qick_time_tagger/component.xml new file mode 100644 index 0000000..0c85c28 --- /dev/null +++ b/firmware/ip/qick_time_tagger/component.xml @@ -0,0 +1,1901 @@ + + + Fermi + user + qick_time_tagger + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + adc_aresetn + + + + + + + RST + + + adc_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + c_aresetn + + + + + + + RST + + + c_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + ps_aresetn + + + + + + + RST + + + ps_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + adc_clk + + + + + + + CLK + + + adc_clk + + + + + + ASSOCIATED_RESET + adc_aresetn + + + ASSOCIATED_BUSIF + s0_axis_adc0:s1_axis_adc1:s2_axis_adc2:s3_axis_adc3 + + + + + c_clk + + + + + + + CLK + + + c_clk + + + + + + ASSOCIATED_RESET + c_aresetn + + + ASSOCIATED_BUSIF + qick_peripheral + + + + + ps_clk + + + + + + + CLK + + + ps_clk + + + + + + ASSOCIATED_RESET + ps_aresetn + + + ASSOCIATED_BUSIF + s_axi:m_axis_dma + + + + + qick_peripheral + + + + + + + b_dt + + + qtag_dt2_i + + + + + c_dt + + + qtag_dt3_i + + + + + a_dt + + + qtag_dt1_i + + + + + flag + + + qtag_flag_o + + + + + d_dt + + + qtag_dt4_i + + + + + rdy + + + qtag_rdy_o + + + + + Enable + + + qtag_en_i + + + + + dt_in_2 + + + qtag_dt2_o + + + + + Operation + + + qtag_op_i + + + + + dt_in_1 + + + qtag_dt1_o + + + + + dt_valid + + + qtag_vld_o + + + + + + s0_axis_adc0 + + + + + + + TVALID + + + adc0_s_axis_tvalid_i + + + + + TDATA + + + adc0_s_axis_tdata_i + + + + + TREADY + + + adc0_s_axis_tready_o + + + + + + s1_axis_adc1 + + + + + + + TDATA + + + adc1_s_axis_tdata_i + + + + + TREADY + + + adc1_s_axis_tready_o + + + + + TVALID + + + adc1_s_axis_tvalid_i + + + + + + + false + + + + + + s2_axis_adc2 + + + + + + + TVALID + + + adc2_s_axis_tvalid_i + + + + + TDATA + + + adc2_s_axis_tdata_i + + + + + TREADY + + + adc2_s_axis_tready_o + + + + + + + false + + + + + + s3_axis_adc3 + + + + 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xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc0_s_axis_tdata_i + + in + + 127 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc0_s_axis_tready_o + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc1_s_axis_tvalid_i + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc1_s_axis_tdata_i + + in + + 127 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc1_s_axis_tready_o + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc2_s_axis_tvalid_i + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc2_s_axis_tdata_i + + in + + 127 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc2_s_axis_tready_o + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc3_s_axis_tvalid_i + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc3_s_axis_tdata_i + + in + + 127 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc3_s_axis_tready_o + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_m_axis_tready_i + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_m_axis_tvalid_o + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_m_axis_tdata_o + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_m_axis_tlast_o + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + qtt_do + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + + + CMP_SLOPE + Cmp Slope + 0 + + + CMP_INTER + Cmp Inter + 4 + + + TAG_FIFO_AW + Tag Fifo Aw + 16 + + + SMP_DW + Smp Dw + 16 + + + SMP_CK + Smp Ck + 8 + + + SMP_STORE + Smp Store + 0 + + + SMP_FIFO_AW + Smp Fifo Aw + 18 + + + DEBUG + Debug + 1 + + + ADC_QTY + Adc Qty + 1 + + + ARM_STORE + Arm Store + 1 + + + ARM_FIFO_AW + Arm Fifo Aw + 10 + + + EXT_ARM + Ext Arm + 0 + + + + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_aa031417 + 1 + 2 + 3 + 4 + + + choice_pairs_2501fc2f + 0 + 1 + 2 + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/_qtt_dma.sv + systemVerilogSource + IMPORTED_FILE + + + src/_qtt_ips.sv + systemVerilogSource + IMPORTED_FILE + + + src/_qtt_mem.sv + systemVerilogSource + IMPORTED_FILE + + + src/qick_time_tagger.sv + systemVerilogSource + IMPORTED_FILE + + + src/qtt_cmd.sv + systemVerilogSource + IMPORTED_FILE + + + src/qtt_tag_calc.sv + systemVerilogSource + IMPORTED_FILE + + + src/smp_mem.sv + systemVerilogSource + IMPORTED_FILE + + + src/tag_gen.sv + systemVerilogSource + IMPORTED_FILE + + + src/tag_mem.sv + systemVerilogSource + IMPORTED_FILE + + + src/axi_slv_qtt.vhd + vhdlSource + IMPORTED_FILE + + + src/axi_qick_time_tagger.sv + systemVerilogSource + CHECKSUM_0bd61aa1 + IMPORTED_FILE + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/_qtt_dma.sv + systemVerilogSource + IMPORTED_FILE + + + src/_qtt_ips.sv + systemVerilogSource + IMPORTED_FILE + + + src/_qtt_mem.sv + systemVerilogSource + IMPORTED_FILE + + + src/qick_time_tagger.sv + systemVerilogSource + IMPORTED_FILE + + + src/qtt_cmd.sv + systemVerilogSource + IMPORTED_FILE + + + src/qtt_tag_calc.sv + systemVerilogSource + IMPORTED_FILE + + + src/smp_mem.sv + systemVerilogSource + IMPORTED_FILE + + + src/tag_gen.sv + systemVerilogSource + IMPORTED_FILE + + + src/tag_mem.sv + systemVerilogSource + IMPORTED_FILE + + + src/axi_slv_qtt.vhd + vhdlSource + IMPORTED_FILE + + + src/axi_qick_time_tagger.sv + systemVerilogSource + IMPORTED_FILE + + + + xilinx_testbench_view_fileset + + src/TB/tb_qtag_behav.wcfg + unknown + IMPORTED_FILE + USED_IN_simulation + USED_IN_testbench + + + src/TB/tb_smp_fifo.wcfg + unknown + IMPORTED_FILE + USED_IN_simulation + USED_IN_testbench + + + src/TB/tb_tag_fifo.wcfg + unknown + IMPORTED_FILE + USED_IN_simulation + USED_IN_testbench + + + src/TB/tb_tag_fifo.sv + systemVerilogSource + IMPORTED_FILE + USED_IN_simulation + USED_IN_testbench + + + src/TB/tb_fifo_dma_behav.wcfg + unknown + IMPORTED_FILE + USED_IN_simulation + USED_IN_testbench + + + + xilinx_xpgui_view_fileset + + xgui/qick_time_tagger_v1_0.tcl + tclSource + CHECKSUM_c492f711 + XGUI_VERSION_2 + + + + qick_time_tagger + + + CMP_SLOPE + Compare with Slope (Constant Fraction Discrimination) + 0 + + + CMP_INTER + Interpolation bits (0 No interpolation) + 4 + + + TAG_FIFO_AW + TAG FIFO Address width + 16 + + + SMP_DW + Smp Dw + 16 + + + SMP_CK + Smp Ck + 8 + + + SMP_STORE + Store Samples + 0 + + + SMP_FIFO_AW + Sample FIFO Address Width + 18 + + + DEBUG + Debug + 1 + + + Component_Name + axi_qick_time_tagger_v1_0 + + + ADC_QTY + Number of ADCs + 1 + + + ARM_STORE + Store Number of Triggers per ARM in ADC0 + 1 + + + ARM_FIFO_AW + ARM Triggers FIFO Address Width + 10 + + + EXT_ARM + IO ARM Control + 0 + + + + + + /UserIP + + qick_time_tagger + level_2 + package_project + + XPM_CDC + + 28 + 2025-02-26T02:45:24Z + + + 2023.1 + + + + + + + + + diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_fifo_dma.sv b/firmware/ip/qick_time_tagger/src/TB/tb_fifo_dma.sv new file mode 100644 index 0000000..83fd54d --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_fifo_dma.sv @@ -0,0 +1,308 @@ +//////4///////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : mdife +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/10ps + +`define HP_CLK 3 // Half Clock Period for Simulation +`define HP_CCLK 2 // Half Clock Period for Simulation + +localparam DEBUG = 1; // Debugging + +module tb_fifo_dma(); + +// Signals +/////////////////////////////////////////////////////////////////////////////// +reg wr_clk_i, rd_clk_i, ready; +reg rst_ni; + +// CLK Generation +////////////////////////////////////////////////////////////////////////// +initial begin + wr_clk_i = 1'b0; + forever # (`HP_CCLK) wr_clk_i = ~wr_clk_i; +end +initial begin + rd_clk_i = 1'b0; + forever # (`HP_CCLK) rd_clk_i = ~rd_clk_i; +end +initial begin + ready = 1'b0; + forever begin + #(1) + //#(16) + //#(24) + //#(34) + //#(37) + @ (posedge rd_clk_i); #0.4; + ready = ~ready; + end +end + + +parameter DW = 32 ; +parameter AW = 16 ; + +reg rst_ni; + + +wire [2:0] trig_inter; +reg [DW-1:0] data_i; +wire [DW-1:0] data_0; +wire [20:0] dma_qty_o, rd_qty_o; +/* +FIFO_SC_DMA # ( + .FIFO_DW ( DW ) , + .FIFO_AW ( AW ) +) fifo_dma ( + .clk_i ( wr_clk_i ) , + .rst_ni ( rst_ni ) , + .push_i ( push_i ) , + .data_i ( data_i ) , + .rd_pop_i ( rd_pop_i ) , + .rd_pop_o ( rd_pop_o ) , + .rd_qty_o ( rd_qty_o ) , + .rd_empty_o ( ) , + .dma_pop_i ( dma_pop_i ) , + .dma_pop_o ( dma_pop_o ) , + .dma_qty_o ( dma_qty_o ) , + .dma_empty_o ( async_empty_o ) , + .dt_o ( ) , + .full_o ( async_full_o ) ); +*/ + +reg push_i, rd_pop_i, dma_pop_i; +reg flush_i; +/* +FIFO_DC_DMA # ( + .DMA_BLOCK ( 1 ) , + .RD_BLOCK ( 1 ) , + .FIFO_DW ( DW ) , + .FIFO_AW ( AW ) +) fifo_dc_dma ( + .wr_clk_i ( wr_clk_i ) , + .wr_rst_ni ( rst_ni ) , + .rd_clk_i ( rd_clk_i ) , + .rd_rst_ni ( rst_ni ) , + .flush_i ( flush_i ) , + .push_i ( push_i ) , + .data_i ( data_i ) , + .rd_pop_i ( rd_pop_i ) , + .rd_pop_o ( ) , + .rd_qty_o ( ) , + .rd_empty_o ( ) , + .dma_pop_i ( fifo_pop_o ) , + .dma_pop_o ( fifo_pop_i ) , + .dma_qty_o ( ) , + .dma_empty_o ( ) , + .dt_o ( fifo_dt_o ) , + .full_o ( ) ); + +FIFO_DC_DMA_2 # ( + .DMA_BLOCK ( 1 ) , + .RD_BLOCK ( 1 ) , + .FIFO_DW ( DW ) , + .FIFO_AW ( AW ) +) fifo_dc_dma_2 ( + .wr_clk_i ( wr_clk_i ) , + .wr_rst_ni ( rst_ni ) , + .rd_clk_i ( rd_clk_i ) , + .rd_rst_ni ( rst_ni ) , + .flush_i ( flush_i ) , + .push_i ( push_i ) , + .data_i ( data_i ) , + .proc_pop_i ( rd_pop_i ) , + .proc_pop_o ( ) , + .proc_qty_o ( ) , + .proc_empty_o ( ) , + .dma_pop_i ( fifo_pop_o ) , + .dma_pop_o ( ) , + .dma_qty_o ( ) , + .dma_empty_o ( ) , + .dt_o ( ) , + .full_o ( ) ); +*/ +TAG_FIFO_TC # ( + .DMA_BLOCK ( 1 ) , + .RD_BLOCK ( 1 ) , + .FIFO_DW ( 32 ) , + .FIFO_AW ( AW ) +) tag_mem ( + .dma_clk_i ( rd_clk_i ) , + .dma_rst_ni ( rst_ni ) , + .c_clk_i ( rd_clk_i ) , + .c_rst_ni ( rst_ni ) , + .adc_clk_i ( wr_clk_i ) , + .adc_rst_ni ( rst_ni ) , + .flush_i ( flush_i ) , + .adc_push_i ( push_i ) , + .adc_data_i ( data_i ) , + .c_pop_i ( rd_pop_i ) , + .c_pop_o ( ) , + .c_qty_o ( ) , + .c_empty_o ( ) , + .dma_pop_i ( dma_pop_i ) , + .dma_pop_o ( dma_pop_o ) , + .dma_qty_o ( ) , + .dma_empty_o ( ) , + .dt_o ( fifo_dt_o ) , + .full_o ( ) ); + +wire [DW-1:0] fifo_dt_o; +reg dma_req_i; +reg [AW-1:0] dma_len_i; + +dma_fifo_rd # ( + .MEM_AW ( AW ) , // Memory Address Width + .MEM_DW ( DW) , // Memory Data Width + .DMA_DW ( DW) // DMA Data Width +) dma_fifo_rd ( + .clk_i ( rd_clk_i ) , + .rst_ni ( rst_ni ) , + .dma_req_i ( dma_req_i ) , + .dma_ack_o ( dma_ack_o ) , + .dma_len_i ( dma_len_i ) , + .fifo_pop_o ( dma_pop_i ) , + .fifo_pop_i ( dma_pop_o ) , + .fifo_dt_i ( fifo_dt_o ) , + .m_axis_tready_i ( ready ) , + .m_axis_tdata_o ( m_axis_tdata_o ) , + .m_axis_tvalid_o ( m_axis_tvalid_o ) , + .m_axis_tlast_o ( m_axis_tlast_o ) ); + + +initial begin + START_SIMULATION(); + FIFO_PUSH(); // Write 20 + #50; + FIFO_RD(); //Read 5 + #50; + FIFO_DMA(); //Read 10 + #50; + FIFO_BOTH(); //Read 10 and 10 + #50; + FIFO_PUSH(); // Write 20 + #50; + FIFO_BOTH(); //Read 10 and 10 + #50; + FIFO_RD_BOTH_WR(); //Read 10 and 10writes 10 +end + + +task START_SIMULATION (); begin + $display("START SIMULATION"); + rst_ni = 1'b0; +flush_i = 1'b0; + push_i = 0; + data_i = 5; + rd_pop_i = 1'b0; + dma_pop_i = 1'b0; + dma_req_i = 0; + dma_len_i = 10; + #10; + @ (posedge rd_clk_i); #0.1; + rst_ni = 1'b1; + @ (posedge rd_clk_i); #0.1; + end +endtask + + + +integer t; + + +task FIFO_PUSH(); begin + $display("PUSH DATA"); + for (t=0; t<32; t=t+1) begin + data_i = t; + push_i = 1'b1; + @ (posedge wr_clk_i); #0.1; + push_i = 1'b0; + @ (posedge wr_clk_i); #0.1; + end + push_i = 1'b0; +end +endtask + +task FIFO_RD(); begin + $display("RD DATA"); + for (t=0; t<5; t=t+1) begin + #10; + @ (posedge rd_clk_i); #0.1; + rd_pop_i = 1'b1; + @ (posedge rd_clk_i); #0.1; + rd_pop_i = 1'b0; + end + #10; +end +endtask + +task FIFO_DMA(); begin + $display("DMA DATA"); + @ (posedge rd_clk_i); #0.1; + dma_req_i = 1'b1; + wait ( dma_ack_o == 1'b1); + dma_req_i = 1'b0; + wait ( dma_ack_o == 1'b0); + #10; + +end +endtask + +task FIFO_BOTH(); begin + $display("RD and DMA DATA"); + @ (posedge rd_clk_i); #0.1; + dma_req_i = 1'b1; + wait ( dma_ack_o == 1'b1); + dma_req_i = 1'b0; + + for (t=0; t<10; t=t+1) begin + #10; + @ (posedge rd_clk_i); #0.1; + rd_pop_i = 1'b1; + @ (posedge rd_clk_i); #0.1; + rd_pop_i = 1'b0; + end + #10; + wait ( dma_ack_o == 1'b0); + #10; + #10; +end +endtask + +task FIFO_RD_BOTH_WR(); begin + $display("RD and DMA DATA and PUSH"); + @ (posedge rd_clk_i); #0.1; + dma_req_i = 1'b1; + wait ( dma_ack_o == 1'b1); + dma_req_i = 1'b0; + + for (t=0; t<10; t=t+1) begin + #10; + @ (posedge rd_clk_i); #0.1; + rd_pop_i = 1'b1; + @ (posedge rd_clk_i); #0.1; + rd_pop_i = 1'b0; + + #10; + @ (posedge wr_clk_i); #0.1; + data_i = t; + push_i = 1'b1; + @ (posedge wr_clk_i); #0.1; + push_i = 1'b0; + + end + #10; + + wait ( dma_ack_o == 1'b0); + #10; + #10; +end +endtask +endmodule + + + + diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_fifo_dma_behav.wcfg b/firmware/ip/qick_time_tagger/src/TB/tb_fifo_dma_behav.wcfg new file mode 100644 index 0000000..740b0cb --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_fifo_dma_behav.wcfg @@ -0,0 +1,131 @@ + + + + + + + + + + + + + + + + + + + + + + + + adc_push_i + adc_push_i + #D2691E + true + + + c_pop_i + c_pop_i + #D2691E + true + + + dma_pop_i + dma_pop_i + #D2691E + true + + + flush_i + flush_i + #D2691E + true + + + do_dma_pop + do_dma_pop + #D2691E + true + + + do_proc_pop + do_proc_pop + #D2691E + true + + + do_push + do_push + #D2691E + true + + + c_pop_o + c_pop_o + #D2691E + true + + + dma_pop_o + dma_pop_o + #D2691E + true + + + dt_o[31:0] + dt_o[31:0] + #D2691E + true + UNSIGNEDDECRADIX + + + m_axis_tready_i + m_axis_tready_i + #0000FF + true + + + m_axis_tdata_o[31:0] + m_axis_tdata_o[31:0] + #0000FF + true + UNSIGNEDDECRADIX + + + m_axis_tvalid_o + m_axis_tvalid_o + #0000FF + true + + + m_axis_tlast_o + m_axis_tlast_o + #0000FF + true + + + dma_rd_st[31:0] + dma_rd_st[31:0] + + + len_cnt[15:0] + len_cnt[15:0] + UNSIGNEDDECRADIX + + + len_cnt_en + len_cnt_en + + + lp_cnt[3:0] + lp_cnt[3:0] + UNSIGNEDDECRADIX + + + lp_cnt_en + lp_cnt_en + + diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_qtag.sv b/firmware/ip/qick_time_tagger/src/TB/tb_qtag.sv new file mode 100644 index 0000000..bf51ad8 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_qtag.sv @@ -0,0 +1,434 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : mdife +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/10ps + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +`define T_PS_CLK 11 // Half Clock Period for Simulation +`define T_C_CLK 3 // 1.66 // Half Clock Period for Simulation +`define T_ADC_CLK 2 // 1.66 // Half Clock Period for Simulation + +`define ADC_QTY 1 +`define DMA_RD 1 +`define PROC_RD 0 +`define CMP_SLOPE 0 +`define CMP_INTER 4 +`define ARM_STORE 1 +`define SMP_STORE 1 +`define TAG_FIFO_AW 19 +`define ARM_FIFO_AW 5 +`define SMP_FIFO_AW 15 +`define SMP_DW 16 +`define SMP_CK 8 +`define DEBUG 1 + +module tb_qick_time_tagger(); + +/////////////////////////////////////////////////////////////////////////////// + +// VIP Agent +axi_mst_0_mst_t axi_mst_0_agent; +xil_axi_prot_t prot = 0; +xil_axi_resp_t resp; + +// Signals +reg c_clk, adc_clk, ps_clk; +reg rst_ni; +reg[31:0] data_wr = 32'h12345678; + +integer t; +real x [`SMP_CK]; +reg [`SMP_DW-1:0] y [`SMP_CK]; +reg [`SMP_DW*`SMP_CK-1:0] adc_dt ; +wire [`SMP_DW*`SMP_CK-1:0] adc0_s_axis_tdata_i, adc1_s_axis_tdata_i, adc2_s_axis_tdata_i, adc3_s_axis_tdata_i ; + + +assign adc0_s_axis_tdata_i = adc_dt; +assign adc1_s_axis_tdata_i = adc_dt; +assign adc2_s_axis_tdata_i = adc_dt; +assign adc3_s_axis_tdata_i = adc_dt; + + +//AXI-LITE +wire [7:0] s_axi_awaddr ; +wire [2:0] s_axi_awprot ; +wire s_axi_awvalid ; +wire s_axi_awready ; +wire [31:0] s_axi_wdata ; +wire [3:0] s_axi_wstrb ; +wire s_axi_wvalid ; +wire s_axi_wready ; +wire [1:0] s_axi_bresp ; +wire s_axi_bvalid ; +wire s_axi_bready ; +wire [7:0] s_axi_araddr ; +wire [2:0] s_axi_arprot ; +wire s_axi_arvalid ; +wire s_axi_arready ; +wire [31:0] s_axi_rdata ; +wire [1:0] s_axi_rresp ; +wire s_axi_rvalid ; +wire s_axi_rready ; + + +////////////////////////////////////////////////////////////////////////// +// CLK Generation +initial begin + c_clk = 1'b0; + forever # (`T_C_CLK) c_clk = ~c_clk; +end +initial begin + adc_clk = 1'b0; + forever # (`T_ADC_CLK) adc_clk = ~adc_clk; +end +initial begin + ps_clk = 1'b0; + forever # (`T_PS_CLK) ps_clk = ~ps_clk; +end + +reg arm_i; +reg qtag_en_i ; +reg [4 :0] qtag_op_i ; +reg [31:0] qtag_dt1_i, qtag_dt2_i, qtag_dt3_i, qtag_dt4_i ; + +wire qtag_rdy_o, qtag_vld_o, qtag_flag_o ; +wire [31:0] qtag_dt1_o, qtag_dt2_o; + +//reg [15:0] threshold; +//wire[31:0] time_ck_s0 , time_ck_s1 , time_ck_s2 , time_ck_s3 ; +//wire[2:0] time_adc_s0, time_adc_s1, time_adc_s2, time_adc_s3; +//wire[3:0] time_int_s0, time_int_s1, time_int_s2, time_int_s3; + + +// Register ADDRESS +parameter QTT_CTRL = 0 * 4 ; +parameter QTT_CFG = 1 * 4 ; +parameter DMA_CFG = 2 * 4 ; +parameter AXI_DT1 = 3 * 4 ; +parameter PROC_DT = 5 * 4 ; +parameter PROC_QTY = 6 * 4 ; +parameter TAG0_QTY = 7 * 4 ; +parameter TAG1_QTY = 8 * 4 ; +parameter TAG2_QTY = 9 * 4 ; +parameter TAG3_QTY = 10* 4 ; +parameter SMP_QTY = 11* 4 ; +parameter ARM_QTY = 12* 4 ; + +////////////////////////////////////////////////////////////////////////// +// AXI AGENT +axi_mst_0 axi_mst_0_i ( + .aclk ( ps_clk ), + .aresetn ( rst_ni ), + .m_axi_araddr ( s_axi_araddr ), + .m_axi_arprot ( s_axi_arprot ), + .m_axi_arready ( s_axi_arready ), + .m_axi_arvalid ( s_axi_arvalid ), + .m_axi_awaddr ( s_axi_awaddr ), + .m_axi_awprot ( s_axi_awprot ), + .m_axi_awready ( s_axi_awready ), + .m_axi_awvalid ( s_axi_awvalid ), + .m_axi_bready ( s_axi_bready ), + .m_axi_bresp ( s_axi_bresp ), + .m_axi_bvalid ( s_axi_bvalid ), + .m_axi_rdata ( s_axi_rdata ), + .m_axi_rready ( s_axi_rready ), + .m_axi_rresp ( s_axi_rresp ), + .m_axi_rvalid ( s_axi_rvalid ), + .m_axi_wdata ( s_axi_wdata ), + .m_axi_wready ( s_axi_wready ), + .m_axi_wstrb ( s_axi_wstrb ), + .m_axi_wvalid ( s_axi_wvalid )); + +axi_qick_time_tagger # ( + .ADC_QTY ( `ADC_QTY ) , + .DMA_RD ( `DMA_RD ) , + .PROC_RD ( `PROC_RD ) , + .CMP_SLOPE ( `CMP_SLOPE ) , + .CMP_INTER ( `CMP_INTER ) , + .ARM_STORE ( `ARM_STORE ) , + .SMP_STORE ( `SMP_STORE ) , + .TAG_FIFO_AW ( `TAG_FIFO_AW ) , + .ARM_FIFO_AW ( `ARM_FIFO_AW ) , + .SMP_FIFO_AW ( `SMP_FIFO_AW ) , + .SMP_DW ( `SMP_DW ) , + .SMP_CK ( `SMP_CK ) , + .DEBUG ( `DEBUG ) +) axi_qick_time_tagger ( +// Core and AXI CLK & RST + .c_clk ( c_clk ) , + .c_aresetn ( rst_ni ) , + .adc_clk ( adc_clk ) , + .adc_aresetn ( rst_ni ) , + .ps_clk ( ps_clk ) , + .ps_aresetn ( rst_ni ) , + .arm_i ( arm_i ) , + .qtag_en_i ( qtag_en_i ) , + .qtag_op_i ( qtag_op_i ) , + .qtag_dt1_i ( qtag_dt1_i ) , + .qtag_dt2_i ( qtag_dt2_i ) , + .qtag_dt3_i ( qtag_dt3_i ) , + .qtag_dt4_i ( qtag_dt4_i ) , + .qtag_rdy_o ( qtag_rdy_o ) , + .qtag_dt1_o ( qtag_dt1_o ) , + .qtag_dt2_o ( qtag_dt2_o ) , + .qtag_vld_o ( qtag_vld_o ) , + .qtag_flag_o ( qtag_flag_o ) , + .s_axi_awaddr ( s_axi_awaddr ) , + .s_axi_awprot ( s_axi_awprot ) , + .s_axi_awvalid ( s_axi_awvalid ) , + .s_axi_awready ( s_axi_awready ) , + .s_axi_wdata ( s_axi_wdata ) , + .s_axi_wstrb ( s_axi_wstrb ) , + .s_axi_wvalid ( s_axi_wvalid ) , + .s_axi_wready ( s_axi_wready ) , + .s_axi_bresp ( s_axi_bresp ) , + .s_axi_bvalid ( s_axi_bvalid ) , + .s_axi_bready ( s_axi_bready ) , + .s_axi_araddr ( s_axi_araddr ) , + .s_axi_arprot ( s_axi_arprot ) , + .s_axi_arvalid ( s_axi_arvalid ) , + .s_axi_arready ( s_axi_arready ) , + .s_axi_rdata ( s_axi_rdata ) , + .s_axi_rresp ( s_axi_rresp ) , + .s_axi_rvalid ( s_axi_rvalid ) , + .s_axi_rready ( s_axi_rready ) , + .adc0_s_axis_tvalid_i ( adc0_s_axis_tvalid_i ) , + .adc0_s_axis_tdata_i ( adc0_s_axis_tdata_i ) , + .adc0_s_axis_tready_o ( adc0_s_axis_tready_o ) , + .adc1_s_axis_tvalid_i ( adc1_s_axis_tvalid_i ) , + .adc1_s_axis_tdata_i ( adc1_s_axis_tdata_i ) , + .adc1_s_axis_tready_o ( adc1_s_axis_tready_o ) , + .adc2_s_axis_tvalid_i ( adc2_s_axis_tvalid_i ) , + .adc2_s_axis_tdata_i ( adc2_s_axis_tdata_i ) , + .adc2_s_axis_tready_o ( adc2_s_axis_tready_o ) , + .adc3_s_axis_tvalid_i ( adc3_s_axis_tvalid_i ) , + .adc3_s_axis_tdata_i ( adc3_s_axis_tdata_i ) , + .adc3_s_axis_tready_o ( adc3_s_axis_tready_o ) , + .dma_m_axis_tready_i ( dma_m_axis_tready_i ) , + .dma_m_axis_tvalid_o ( dma_m_axis_tvalid_o ) , + .dma_m_axis_tdata_o ( dma_m_axis_tdata_o ) , + .dma_m_axis_tlast_o ( dma_m_axis_tlast_o ) , + .qtt_do ( qtt_do ) +); + +integer FILTER, SLOPE, INTER, SMP_NUM, rand_mult, tmp; +reg p_start; + + +initial begin + rand_mult = 0; + START_SIMULATION(); + arm_i = 1'b1; + #10000; + arm_i = 1'b0; + CMD_DISARM(); + CMD_POP_DT(); + WRITE_AXI( AXI_DT1 , 3950); + CMD_SET_THR(); + WRITE_AXI( AXI_DT1 , 50); + CMD_SET_DEAD_TIME(); + + CMD_RST(); + FILTER = 1; + SLOPE = 0; + INTER = 4; + SMP_NUM = 6; + WRITE_AXI( QTT_CFG , 1* FILTER+ 2* SLOPE + 4*INTER + 32* SMP_NUM); // NO FILTER + + CMD_ARM(); + AMP = 24; + SIM_SINE(); + SIM_SINE(); + CMD_DISARM(); + WRITE_AXI( DMA_CFG , 16*3); + WRITE_AXI( QTT_CTRL , 32); + @ (posedge dma_m_axis_tlast_o); + WRITE_AXI( DMA_CFG , 16*2); + WRITE_AXI( QTT_CTRL , 32); + @ (posedge dma_m_axis_tlast_o); + WRITE_AXI( DMA_CFG , 16*1); + WRITE_AXI( QTT_CTRL , 32); + @ (posedge dma_m_axis_tlast_o); + + + //CMD_DMA_RD(); + + CMD_SMP_RD (); + #10000; + + for (INTER=0; INTER<=4; INTER=INTER+1) begin + CMD_DISARM(); + WRITE_AXI( QTT_CFG , 1* FILTER+ 2* SLOPE + 4*INTER + 32* SMP_NUM ); // NO FILTER INVERT INPUT + CMD_ARM(); + for (AMP=2; AMP<=32; AMP=AMP*2) begin + SIM_RANDOM(); + SIM_PULSES(); + end + CMD_SMP_RD (); + #10000; + end + SIM_RANDOM(); + CMD_DISARM(); + WRITE_AXI( DMA_CFG , 0+16*1); + WRITE_AXI( QTT_CTRL , 32); + #10000; + WRITE_AXI( DMA_CFG , 0+16*2); + WRITE_AXI( QTT_CTRL , 32); + #10000; + WRITE_AXI( DMA_CFG , 0+16*3); + WRITE_AXI( QTT_CTRL , 32); + #10000; + +//Micro POP + @ (posedge c_clk); #0.1; + qtag_en_i = 1; + qtag_op_i = 2; + @ (posedge c_clk); #0.1; + qtag_en_i = 0; + qtag_op_i = 2; + + @ (posedge c_clk); #0.1; + CMD_POP_DT(); + CMD_POP_DT(); + +end +reg adc0_s_axis_tvalid_i, adc1_s_axis_tvalid_i, adc2_s_axis_tvalid_i, adc3_s_axis_tvalid_i; +reg dma_m_axis_tready_i; + +task START_SIMULATION (); begin + $display("START SIMULATION"); + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb_qick_time_tagger.axi_mst_0_i.inst.IF); + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + // Start agents. + axi_mst_0_agent.start_master(); + rst_ni = 1'b0; + dma_m_axis_tready_i = 1'b1; + adc0_s_axis_tvalid_i = 1'b1; + adc1_s_axis_tvalid_i = 1'b1; + adc2_s_axis_tvalid_i = 1'b1; + adc3_s_axis_tvalid_i = 1'b1; + + arm_i = 1'b0; + qtag_en_i = 0; + qtag_op_i = 0; + qtag_dt1_i = 0; + qtag_dt2_i = 0; + qtag_dt3_i = 0; + qtag_dt4_i = 0; + p_start = 0; + adc_dt = 0; + + @ (posedge ps_clk); #0.1; + rst_ni = 1'b1; + @ (posedge adc_clk); #0.1; + p_start = 1; + @ (posedge adc_clk); #0.1; + p_start = 0; + + end +endtask + +task WRITE_AXI(integer PORT_AXI, DATA_AXI); begin + @ (posedge ps_clk); #0.1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(PORT_AXI, prot, DATA_AXI, resp); + end +endtask + +task CMD_DISARM (); + WRITE_AXI( QTT_CTRL , 1 + 2 * 0); +endtask +task CMD_ARM (); + WRITE_AXI( QTT_CTRL , 1 + 2 * 1); +endtask +task CMD_POP_DT (); + WRITE_AXI( QTT_CTRL , 1 + 2 * 2); +endtask +task CMD_SET_THR (); + WRITE_AXI( QTT_CTRL , 1 + 2 * 4); +endtask +task CMD_SET_DEAD_TIME (); + WRITE_AXI( QTT_CTRL , 1 + 2 * 5); +endtask +task CMD_RST (); + WRITE_AXI( QTT_CTRL , 1 + 2 * 7); +endtask + +task CMD_DMA_RD (); + WRITE_AXI( DMA_CFG , 16*5); + WRITE_AXI( QTT_CTRL , 32); + @ (posedge dma_m_axis_tlast_o); +endtask + +task CMD_SMP_RD (); + WRITE_AXI( DMA_CFG , 5+16*SMP_NUM*`SMP_CK*4); + WRITE_AXI( QTT_CTRL , 32); + @ (posedge dma_m_axis_tlast_o); + +endtask + + +integer AMP; +integer i; + +task SIM_SINE(); begin +//50t per sinewave + for (t=0; t<84000; t=t+1) begin + @ (posedge adc_clk); #0.1; + for (i=0; i<`SMP_CK; i=i+1) begin + x[i] = ( (`SMP_CK*t) + i ) / (`SMP_CK*100.0) * (44.0 / 7.0); + y[i] = $sin(x[i])*1000*AMP ; + adc_dt[i*`SMP_DW +: `SMP_DW ] = y[i]; + end + end + adc_dt = 0; +end +endtask + +task SIM_PULSES(); begin + for (t=0; t<5; t=t+1) begin + @ (posedge adc_clk); #0.1; + for (i=0; i<`SMP_CK; i=i+1) begin + x[i] = ( (`SMP_CK*t)+i ) * (22.0/7.0) / 10/8 ; + y[i] = $sin(x[i])*1000*AMP+($random %10)*rand_mult; + adc_dt[i*`SMP_DW +: `SMP_DW ] = y[i]; + end + end + for (t=0; t<25; t=t+1) begin + @ (posedge adc_clk); #0.1; + for (i=0; i<`SMP_CK; i=i+1) begin + x[i] = ( (`SMP_CK*t)+i ) * (22.0/7.0) / 50/8 ; + y[i] = $cos(x[i])*1000*AMP+($random %10); + adc_dt[i*`SMP_DW +: `SMP_DW ] = y[i]; + end + end + for (t=0; t<20; t=t+1) begin + @ (posedge adc_clk); #0.1; + for (i=0; i<`SMP_CK; i=i+1) begin + y[i] = ($random %100); + adc_dt[i*`SMP_DW +: `SMP_DW ] = y[i]; + end + end + adc_dt = 0; +end +endtask + + +task SIM_RANDOM(); begin + for (t=0; t<50; t=t+1) begin + @ (posedge adc_clk); #0.1; + for (i=0; i<`SMP_CK; i=i+1) begin + y[i] = ($random %100); + adc_dt[i*`SMP_DW +: `SMP_DW ] = y[i]; + end + end +end +endtask + +endmodule diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_qtag_behav.wcfg b/firmware/ip/qick_time_tagger/src/TB/tb_qtag_behav.wcfg new file mode 100644 index 0000000..361b9be --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_qtag_behav.wcfg @@ -0,0 +1,526 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + time_trig_st[31:0] + time_trig_st[31:0] + UNSIGNEDDECRADIX + #FF00FF + true + + + time_cnt[28:0] + time_cnt[28:0] + + + CMD + label + + adc_clk + adc_clk + + + arm_i + arm_i + + + ext_arm_t01 + ext_arm_t01 + + + ext_arm_t10 + ext_arm_t10 + + + qtt_arm + qtt_arm + + + cmd_req + cmd_req + + + p_en_i + p_en_i + + + p_op_i[4:0] + p_op_i[4:0] + + + p_dt_i[31:0] + p_dt_i[31:0] + UNSIGNEDDECRADIX + + + cmd_dt[31:0] + cmd_dt[31:0] + UNSIGNEDDECRADIX + + + cmd_disarm + cmd_disarm + + + cmd_arm + cmd_arm + + + cmd_pop + cmd_pop + + + cmd_set_th + cmd_set_th + + + cmd_set_inh + cmd_set_inh + + + cmd_reset + cmd_reset + + + + qtt_cmp_inh[7:0] + qtt_cmp_inh[7:0] + #FFFF00 + true + UNSIGNEDDECRADIX + + + cfg_filter_i + cfg_filter_i + + + cfg_slope_i + cfg_slope_i + + + cfg_inter_i[2:0] + cfg_inter_i[2:0] + + + cfg_smp_wr_qty_i[4:0] + cfg_smp_wr_qty_i[4:0] + + + adc_smp[7:0][15:0] + adc_smp[7:0][15:0] + SIGNEDDECRADIX + + + ftr_smp[7:0][16:0] + ftr_smp[7:0][16:0] + SIGNEDDECRADIX + + + adc_smp[7:0][15:0] + adc_smp[7:0][15:0] + SIGNEDDECRADIX + + + trig_cal_st[31:0] + trig_cal_st[31:0] + #FF00FF + true + + + [0][15:0] + [0][15:0] + STYLE_ANALOG + 100 + SIGNEDDECRADIX + ANALOG_YRANGETYPE_FIXED + -32000.000000 + 32000.000000 + ANALOG_INTERPOLATION_LINEAR + ANALOG_OFFSCALE_HIDE + 0.000000 + + + adc_rst_ni + adc_rst_ni + + + tag_gen_en + tag_gen_en + + + trig_event + trig_event + + + trig_o + trig_o + #0000FF + true + + + cmp_o + cmp_o + #0000FF + true + + + \ARM.trig_cnt [31:0] + \ARM.trig_cnt [31:0] + UNSIGNEDDECRADIX + + + mem[0:31][31:0] + mem[0:31][31:0] + + + [0][31:0] + [0][31:0] + UNSIGNEDDECRADIX + + + [1][31:0] + [1][31:0] + UNSIGNEDDECRADIX + + + [2][31:0] + [2][31:0] + UNSIGNEDDECRADIX + + + [3][31:0] + [3][31:0] + UNSIGNEDDECRADIX + + + [4][31:0] + [4][31:0] + UNSIGNEDDECRADIX + + + [5][31:0] + [5][31:0] + UNSIGNEDDECRADIX + + + [6][31:0] + [6][31:0] + UNSIGNEDDECRADIX + + + [7][31:0] + [7][31:0] + + + [8][31:0] + [8][31:0] + + + [9][31:0] + [9][31:0] + + + [10][31:0] + [10][31:0] + + + [11][31:0] + [11][31:0] + + + [12][31:0] + [12][31:0] + + + [13][31:0] + [13][31:0] + + + [14][31:0] + [14][31:0] + + + [15][31:0] + [15][31:0] + + + [16][31:0] + [16][31:0] + + + [17][31:0] + [17][31:0] + + + [18][31:0] + [18][31:0] + + + [19][31:0] + [19][31:0] + + + [20][31:0] + [20][31:0] + + + [21][31:0] + [21][31:0] + + + [22][31:0] + [22][31:0] + + + [23][31:0] + [23][31:0] + + + [24][31:0] + [24][31:0] + + + [25][31:0] + [25][31:0] + + + [26][31:0] + [26][31:0] + + + [27][31:0] + [27][31:0] + + + [28][31:0] + [28][31:0] + + + [29][31:0] + [29][31:0] + + + [30][31:0] + [30][31:0] + + + [31][31:0] + [31][31:0] + + + [0][31:0] + [0][31:0] + + + [1][31:0] + [1][31:0] + + + [2][31:0] + [2][31:0] + + + [3][31:0] + [3][31:0] + + + [4][31:0] + [4][31:0] + + + [5][31:0] + [5][31:0] + + + [6][31:0] + [6][31:0] + + + [7][31:0] + [7][31:0] + + + [8][31:0] + [8][31:0] + + + [9][31:0] + [9][31:0] + + + [10][31:0] + [10][31:0] + + + [11][31:0] + [11][31:0] + + + [12][31:0] + [12][31:0] + + + [13][31:0] + [13][31:0] + + + [14][31:0] + [14][31:0] + + + [15][31:0] + [15][31:0] + + + [16][31:0] + [16][31:0] + + + [17][31:0] + [17][31:0] + + + [18][31:0] + [18][31:0] + + + [19][31:0] + [19][31:0] + + + [20][31:0] + [20][31:0] + + + [21][31:0] + [21][31:0] + + + [22][31:0] + [22][31:0] + + + [23][31:0] + [23][31:0] + + + [24][31:0] + [24][31:0] + + + [25][31:0] + [25][31:0] + + + [26][31:0] + [26][31:0] + + + [27][31:0] + [27][31:0] + + + [28][31:0] + [28][31:0] + + + [29][31:0] + [29][31:0] + + + [30][31:0] + [30][31:0] + + + [31][31:0] + [31][31:0] + + + + dma_len_i[19:0] + dma_len_i[19:0] + UNSIGNEDDECRADIX + + + dma_req_i + dma_req_i + + + pop_req_o + pop_req_o + + + pop_ack_i + pop_ack_i + + + dma_rd_st[31:0] + dma_rd_st[31:0] + #FF00FF + true + + + len_cnt[19:0] + len_cnt[19:0] + UNSIGNEDDECRADIX + + + len_cnt_p1[19:0] + len_cnt_p1[19:0] + UNSIGNEDDECRADIX + + + len_cnt_rst + len_cnt_rst + + + len_cnt_last + len_cnt_last + + + dma_m_axis_tvalid_o + dma_m_axis_tvalid_o + #0000FF + true + + + dma_m_axis_tdata_o[31:0] + dma_m_axis_tdata_o[31:0] + #0000FF + true + UNSIGNEDDECRADIX + + + dma_m_axis_tlast_o + dma_m_axis_tlast_o + #0000FF + true + + + dma_qty_o[0:3][18:0] + dma_qty_o[0:3][18:0] + + + diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_qtt_cmp.sv b/firmware/ip/qick_time_tagger/src/TB/tb_qtt_cmp.sv new file mode 100644 index 0000000..51725b3 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_qtt_cmp.sv @@ -0,0 +1,547 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : mdife +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/10ps + +import axi_vip_pkg::*; +import axi_mst_0_pkg::*; + +`define T_C_CLK 2 // 1.66 // Half Clock Period for Simulation +`define T_ADC_CLK 1 // 1.66 // Half Clock Period for Simulation +`define T_PS_CLK 10 // Half Clock Period for Simulation + +`define DMA_RD 1 +`define PROC_RD 1 +`define CMP_SLOPE 1 +`define CMP_INTER 4 +`define SMP_DW 16 +`define SMP_CK 8 +`define TAG_FIFO_AW 10 +`define SMP_STORE 0 +`define SMP_FIFO_AW 10 +`define DEBUG 2 + + +module tb_qick_time_tagger(); + +/////////////////////////////////////////////////////////////////////////////// + +// VIP Agent +axi_mst_0_mst_t axi_mst_0_agent; +xil_axi_prot_t prot = 0; +xil_axi_resp_t resp; + +// Signals +reg c_clk, adc_clk, ps_clk; +reg rst_ni; +reg[31:0] data_wr = 32'h12345678; + +integer t; +real x0, x1, x2, x3,x4, x5, x6, x7 ; +reg [`SMP_DW-1:0] y0, y1, y2, y3,y4, y5, y6, y7 ; +reg [`SMP_DW*`SMP_CK-1:0] adc_dt, adc_s_axis_tdata_i ; + +//AXI-LITE +wire [7:0] s_axi_awaddr ; +wire [2:0] s_axi_awprot ; +wire s_axi_awvalid ; +wire s_axi_awready ; +wire [31:0] s_axi_wdata ; +wire [3:0] s_axi_wstrb ; +wire s_axi_wvalid ; +wire s_axi_wready ; +wire [1:0] s_axi_bresp ; +wire s_axi_bvalid ; +wire s_axi_bready ; +wire [7:0] s_axi_araddr ; +wire [2:0] s_axi_arprot ; +wire s_axi_arvalid ; +wire s_axi_arready ; +wire [31:0] s_axi_rdata ; +wire [1:0] s_axi_rresp ; +wire s_axi_rvalid ; +wire s_axi_rready ; + + +////////////////////////////////////////////////////////////////////////// +// CLK Generation +initial begin + c_clk = 1'b0; + forever # (`T_C_CLK) c_clk = ~c_clk; +end +initial begin + adc_clk = 1'b0; + forever # (`T_ADC_CLK) adc_clk = ~adc_clk; +end +initial begin + ps_clk = 1'b0; + forever # (`T_PS_CLK) ps_clk = ~ps_clk; +end + +reg pulse_f; +reg dma_m_axis_tready_i; + + +always @ (posedge ps_clk, negedge rst_ni) begin + if ( !rst_ni ) + dma_m_axis_tready_i = 1'b1; + else + if ( dma_m_axis_tvalid_o) begin + #0.5; + dma_m_axis_tready_i = 0; + #100; + end else begin + #0.5; + dma_m_axis_tready_i = 1'b1; + end +end + +always_ff @ (posedge adc_clk, negedge rst_ni) begin + if ( !rst_ni ) pulse_f <= 1'b0; + else + if ( pulse_f2 | rdy_a) pulse_f <= 1'b1; + if ( pulse_f ) pulse_f <= 1'b0; +end + + +reg qtag_en_i ; +reg [4 :0] qtag_op_i ; +reg [31:0] qtag_dt1_i, qtag_dt2_i, qtag_dt3_i, qtag_dt4_i ; + +wire qtag_rdy_o, qtag_vld_o, qtag_flag_o ; +wire [31:0] qtag_dt1_o, qtag_dt2_o; + +// Register ADDRESS +parameter QTT_CTRL = 0 * 4 ; +parameter QTT_CFG = 1 * 4 ; +parameter QTT_ADDR = 2 * 4 ; +parameter QTT_LEN = 3 * 4 ; +parameter AXI_DT1 = 4 * 4 ; +parameter AXI_DT2 = 5 * 4 ; +parameter AXI_DT3 = 6 * 4 ; +parameter AXI_DT4 = 7 * 4 ; +parameter QTT_DT1 = 9 * 4 ; +parameter QTT_DT2 = 10* 4 ; +parameter QTT_DT3 = 11* 4 ; +parameter QTT_DT4 = 12* 4 ; +parameter QTT_STATUS = 14* 4 ; +parameter QTT_DEBUG = 15* 4 ; + + + +pulse_cdc pulse_f2s ( + .clk_a_i ( adc_clk ) , + .rst_a_ni ( rst_ni ) , + .pulse_a_i ( pulse_f ) , + .rdy_a_o ( rdy_a ) , + .clk_b_i ( ps_clk ) , + .rst_b_ni ( rst_ni ) , + .pulse_b_o ( pulse_slow ) ); + +pulse_cdc pulse_s2f ( + .clk_a_i ( ps_clk ) , + .rst_a_ni ( rst_ni ) , + .pulse_a_i ( pulse_slow ) , + .rdy_a_o ( ) , + .clk_b_i ( adc_clk ) , + .rst_b_ni ( rst_ni ) , + .pulse_b_o ( pulse_f2 ) ); +////////////////////////////////////////////////////////////////////////// +// AXI AGENT +axi_mst_0 axi_mst_0_i ( + .aclk ( ps_clk ), + .aresetn ( rst_ni ), + .m_axi_araddr ( s_axi_araddr ), + .m_axi_arprot ( s_axi_arprot ), + .m_axi_arready ( s_axi_arready ), + .m_axi_arvalid ( s_axi_arvalid ), + .m_axi_awaddr ( s_axi_awaddr ), + .m_axi_awprot ( s_axi_awprot ), + .m_axi_awready ( s_axi_awready ), + .m_axi_awvalid ( s_axi_awvalid ), + .m_axi_bready ( s_axi_bready ), + .m_axi_bresp ( s_axi_bresp ), + .m_axi_bvalid ( s_axi_bvalid ), + .m_axi_rdata ( s_axi_rdata ), + .m_axi_rready ( s_axi_rready ), + .m_axi_rresp ( s_axi_rresp ), + .m_axi_rvalid ( s_axi_rvalid ), + .m_axi_wdata ( s_axi_wdata ), + .m_axi_wready ( s_axi_wready ), + .m_axi_wstrb ( s_axi_wstrb ), + .m_axi_wvalid ( s_axi_wvalid )); + + +axi_qick_time_tagger # ( + .DMA_RD ( `DMA_RD ) , + .PROC_RD ( `PROC_RD ) , + .CMP_SLOPE ( `CMP_SLOPE ) , + .CMP_INTER ( `CMP_INTER ) , + .TAG_FIFO_AW ( `TAG_FIFO_AW ) , + .SMP_DW ( `SMP_DW ) , + .SMP_CK ( `SMP_CK ) , + .SMP_STORE ( `SMP_STORE ) , + .SMP_FIFO_AW ( `SMP_FIFO_AW ) , + .DEBUG ( `DEBUG ) +) axi_qick_time_tagger ( + .c_clk ( c_clk ), + .c_aresetn ( rst_ni ), + .adc_clk ( adc_clk ), + .adc_aresetn ( rst_ni ), + .ps_clk ( ps_clk ), + .ps_aresetn ( rst_ni ), + .qtag_en_i ( qtag_en_i ), + .qtag_op_i ( qtag_op_i ), + .qtag_dt1_i ( qtag_dt1_i ), + .qtag_dt2_i ( qtag_dt2_i ), + .qtag_dt3_i ( qtag_dt3_i ), + .qtag_dt4_i ( qtag_dt4_i ), + .qtag_rdy_o ( qtag_rdy_o ), + .qtag_dt1_o ( qtag_dt1_o ), + .qtag_dt2_o ( qtag_dt2_o ), + .qtag_vld_o ( qtag_vld_o ), + .qtag_flag_o ( qtag_flag_o ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awprot ( s_axi_awprot ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awready ( s_axi_awready ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wstrb ( s_axi_wstrb ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wready ( s_axi_wready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arprot ( s_axi_arprot ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_arready ( s_axi_arready ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rready ( s_axi_rready ), + .adc_s_axis_tvalid_i ( adc_s_axis_tvalid_i ), + .adc_s_axis_tdata_i ( adc_s_axis_tdata_i ), + .adc_s_axis_tready_o ( adc_s_axis_tready_o ), + .dma_m_axis_tready_i ( dma_m_axis_tready_i ), + .dma_m_axis_tvalid_o ( dma_m_axis_tvalid_o ), + .dma_m_axis_tdata_o ( dma_m_axis_tdata_o ), + .dma_m_axis_tlast_o ( dma_m_axis_tlast_o ), + .qtt_do ( )); + +reg [15:0] threshold; +wire[31:0] time_ck_s0 , time_ck_s1 , time_ck_s2 , time_ck_s3 ; +wire[2:0] time_adc_s0, time_adc_s1, time_adc_s2, time_adc_s3; +wire[3:0] time_int_s0, time_int_s1, time_int_s2, time_int_s3; + + +thr_cmp CMP_0 ( + .clk_i ( adc_clk ) , + .rst_ni ( rst_ni ) , + .cfg_filter_i ( 0 ) , + .cfg_slope_i ( 0 ) , + .cfg_inter_i ( 1 ), + .th_i ( threshold ) , + .dt_i ( adc_dt ) , + .trig_time_ck_o ( time_ck_s0 ) , + .trig_time_adc_o ( time_adc_s0 ) , + .trig_time_int_o ( time_int_s0 ) , + .trig_vld_o ( time_vld_s0 ) ); +thr_cmp CMP_1 ( + .clk_i ( adc_clk ) , + .rst_ni ( rst_ni ) , + .cfg_filter_i ( 0 ) , + .cfg_slope_i ( 1 ) , + .cfg_inter_i ( 0 ), + .th_i ( threshold ) , + .dt_i ( adc_dt ) , + .trig_time_ck_o ( time_ck_s1 ) , + .trig_time_adc_o ( time_adc_s1 ) , + .trig_time_int_o ( time_int_s1 ) , + .trig_vld_o ( time_vld_s1 ) ); +thr_cmp CMP_2 ( + .clk_i ( adc_clk ) , + .rst_ni ( rst_ni ) , + .cfg_filter_i ( 1 ) , + .cfg_slope_i ( 0 ) , + .cfg_inter_i ( 1 ), + .th_i ( threshold ) , + .dt_i ( adc_dt ) , + .trig_time_ck_o ( time_ck_s2 ) , + .trig_time_adc_o ( time_adc_s2 ) , + .trig_time_int_o ( time_int_s2 ) , + .trig_vld_o ( time_vld_s2 ) ); +thr_cmp CMP_3 ( + .clk_i ( adc_clk ) , + .rst_ni ( rst_ni ) , + .cfg_filter_i ( 1 ) , + .cfg_slope_i ( 1 ) , + .cfg_inter_i ( 0 ), + .th_i ( threshold ) , + .dt_i ( adc_dt ) , + .trig_time_ck_o ( time_ck_s3 ) , + .trig_time_adc_o ( time_adc_s3 ) , + .trig_time_int_o ( time_int_s3 ) , + .trig_vld_o ( time_vld_s3 ) ); + +assign adc_s_axis_tvalid_i = 1'b1; +assign adc_s_axis_tdata_i = adc_dt; + +integer INTER, rand_mult, tmp; +reg p_start; + +initial begin + rand_mult = 0; + START_SIMULATION(); + // TEST_AXI () ; + // TEST_CMD (); + WRITE_AXI( QTT_CFG , 5); // SET DEAD TIME + WRITE_AXI( AXI_DT1 , 30); + WRITE_AXI( QTT_CTRL , 1); + + WRITE_AXI( QTT_CFG , 4); // SET THR + WRITE_AXI( AXI_DT1 , 3630); + WRITE_AXI( QTT_CTRL , 1); + + for (tmp=0; tmp<=100; tmp=tmp+1) begin + for (INTER=0; INTER<=7; INTER=INTER+1) begin + //for (AMP=2; AMP<=32; AMP=AMP*2) begin + for (AMP=2; AMP<=32; AMP=AMP+1) begin + WRITE_AXI( QTT_CFG , INTER*32+1); + WRITE_AXI( QTT_CTRL , 1 ); + SIM_RANDOM(); + SIM_PULSES(); + end + //WRITE_AXI( QTT_CFG , 0); // DISARM + //WRITE_AXI( QTT_CTRL , 1); + end + SIM_RANDOM(); + SIM_RANDOM(); + SIM_RANDOM(); + end + WRITE_AXI( QTT_CFG , 0); // DISARM + WRITE_AXI( QTT_CTRL , 1); + +//Micro POP + qtag_en_i = 1; + qtag_op_i = 2; + @ (posedge c_clk); #0.1; + qtag_en_i = 0; + qtag_op_i = 2; + + @ (posedge c_clk); #0.1; + WRITE_AXI( QTT_LEN , 10); + WRITE_AXI( QTT_CTRL , 4); // TAG READ + #5000; + @ (posedge c_clk); #0.1; + WRITE_AXI( QTT_LEN , 10); + WRITE_AXI( QTT_CTRL , 4); // TAG READ + +//DMA POP + WRITE_AXI( QTT_CFG , 2); // POP + WRITE_AXI( QTT_CTRL , 1); +//DMA POP + WRITE_AXI( QTT_CFG , 2); // POP + WRITE_AXI( QTT_CTRL , 1); +//DMA POP + WRITE_AXI( QTT_CFG , 2); // POP + WRITE_AXI( QTT_CTRL , 1); + + WRITE_AXI( QTT_CFG , 1); // ARM + WRITE_AXI( QTT_CTRL , 1); + + WRITE_AXI( QTT_CFG , 7); // RESET + WRITE_AXI( QTT_CTRL , 1); + +end + +task START_SIMULATION (); begin + $display("START SIMULATION"); + // Create agents. + axi_mst_0_agent = new("axi_mst_0 VIP Agent",tb_qick_time_tagger.axi_mst_0_i.inst.IF); + // Set tag for agents. + axi_mst_0_agent.set_agent_tag ("axi_mst_0 VIP"); + // Start agents. + axi_mst_0_agent.start_master(); + rst_ni = 1'b0; + qtag_en_i = 0; + qtag_op_i = 0; + qtag_dt1_i = 0; + qtag_dt2_i = 0; + qtag_dt3_i = 0; + qtag_dt4_i = 0; + p_start = 0; + adc_dt = 0; + + @ (posedge ps_clk); #0.1; + rst_ni = 1'b1; + @ (posedge adc_clk); #0.1; + p_start = 1; + @ (posedge adc_clk); #0.1; + p_start = 0; + + end +endtask + +task WRITE_AXI(integer PORT_AXI, DATA_AXI); begin + @ (posedge ps_clk); #0.1; + axi_mst_0_agent.AXI4LITE_WRITE_BURST(PORT_AXI, prot, DATA_AXI, resp); + end +endtask + + +task TEST_AXI (); begin + $display("-----Writting AXI "); + WRITE_AXI( QTT_CTRL , 1); + WRITE_AXI( QTT_CFG , 2); + WRITE_AXI( QTT_ADDR , 3); + WRITE_AXI( QTT_LEN , 4); + WRITE_AXI( AXI_DT1 , 5); + WRITE_AXI( AXI_DT2 , 6); + WRITE_AXI( AXI_DT3 , 7); + WRITE_AXI( AXI_DT4 , 8); +end +endtask + +task TEST_CMD (); begin + $display("-----Writting AXI "); + WRITE_AXI( QTT_CTRL , 1); // RST + + WRITE_AXI( QTT_CFG , 1); // ARM + WRITE_AXI( QTT_CTRL , 2); // CMD + + WRITE_AXI( QTT_CFG , 2); // DISARM + WRITE_AXI( QTT_CTRL , 2); // CMD + + WRITE_AXI( QTT_CFG , 8); // SET_THR + WRITE_AXI( AXI_DT1 , 456); + WRITE_AXI( QTT_CTRL , 2); // CMD + + WRITE_AXI( QTT_CFG , 9); // SET_DEAD_TIME + WRITE_AXI( AXI_DT1 , 123); + WRITE_AXI( QTT_CTRL , 2); // CMD + + WRITE_AXI( QTT_ADDR , 3); + WRITE_AXI( QTT_LEN , 10); + WRITE_AXI( QTT_CTRL , 4); // TAG READ + WRITE_AXI( QTT_CTRL , 8); // SMP READ +end +endtask + +task SIM_QTT(); begin + $display("SIM TAGGER"); + for (t=0; t<=360; t=t+1) begin + @ (posedge adc_clk); #0.1; + x0 = ( (8*t)+0 ) * (22.0/7.0) / 180/4; + x1 = ( (8*t)+1 ) * (22.0/7.0) / 180/4; + x2 = ( (8*t)+2 ) * (22.0/7.0) / 180/4; + x3 = ( (8*t)+3 ) * (22.0/7.0) / 180/4; + x4 = ( (8*t)+4 ) * (22.0/7.0) / 180/4; + x5 = ( (8*t)+5 ) * (22.0/7.0) / 180/4; + x6 = ( (8*t)+6 ) * (22.0/7.0) / 180/4; + x7 = ( (8*t)+7 ) * (22.0/7.0) / 180/4; + y0 = 255*$sin(0.5*x0) + 255*$sin(3*x0) + 511*$sin(2*x0); + y1 = 255*$sin(0.5*x1) + 255*$sin(3*x1) + 511*$sin(2*x1); + y2 = 255*$sin(0.5*x2) + 255*$sin(3*x2) + 511*$sin(2*x2); + y3 = 255*$sin(0.5*x3) + 255*$sin(3*x3) + 511*$sin(2*x3); + y4 = 255*$sin(0.5*x4) + 255*$sin(3*x4) + 511*$sin(2*x4); + y5 = 255*$sin(0.5*x5) + 255*$sin(3*x5) + 511*$sin(2*x5); + y6 = 255*$sin(0.5*x6) + 255*$sin(3*x6) + 511*$sin(2*x6); + y7 = 255*$sin(0.5*x7) + 255*$sin(3*x7) + 511*$sin(2*x7); + adc_dt = {y7, y6, y5, y4, y3, y2, y1, y0}; + end +end +endtask + +integer AMP; + + +task SIM_PULSES(); begin + for (t=0; t<5; t=t+1) begin + @ (posedge adc_clk); #0.1; + //x = (t)* (22.0/7.0)/20; + //y = $sin(x) ; + //yd = y *1000*AMP+($random %100); + x0 = ( (8*t)+0 ) * (22.0/7.0) / 10/8; + x1 = ( (8*t)+1 ) * (22.0/7.0) / 10/8; + x2 = ( (8*t)+2 ) * (22.0/7.0) / 10/8; + x3 = ( (8*t)+3 ) * (22.0/7.0) / 10/8; + x4 = ( (8*t)+4 ) * (22.0/7.0) / 10/8; + x5 = ( (8*t)+5 ) * (22.0/7.0) / 10/8; + x6 = ( (8*t)+6 ) * (22.0/7.0) / 10/8; + x7 = ( (8*t)+7 ) * (22.0/7.0) / 10/8; + y0 = $sin(x0)*1000*AMP+($random %10)*rand_mult; + y1 = $sin(x1)*1000*AMP+($random %10)*rand_mult; + y2 = $sin(x2)*1000*AMP+($random %10)*rand_mult; + y3 = $sin(x3)*1000*AMP+($random %10)*rand_mult; + y4 = $sin(x4)*1000*AMP+($random %10)*rand_mult; + y5 = $sin(x5)*1000*AMP+($random %10)*rand_mult; + y6 = $sin(x6)*1000*AMP+($random %10)*rand_mult; + y7 = $sin(x7)*1000*AMP+($random %10)*rand_mult; + adc_dt = {y7, y6, y5, y4, y3, y2, y1, y0}; + + end + for (t=0; t<25; t=t+1) begin + @ (posedge adc_clk); #0.1; + //x = (t)* (22.0/7.0)/100; + //y = $cos(x); + //yd = y *1000*AMP+($random %100); + x0 = ( (8*t)+0 ) * (22.0/7.0) / 50/8; + x1 = ( (8*t)+1 ) * (22.0/7.0) / 50/8; + x2 = ( (8*t)+2 ) * (22.0/7.0) / 50/8; + x3 = ( (8*t)+3 ) * (22.0/7.0) / 50/8; + x4 = ( (8*t)+4 ) * (22.0/7.0) / 50/8; + x5 = ( (8*t)+5 ) * (22.0/7.0) / 50/8; + x6 = ( (8*t)+6 ) * (22.0/7.0) / 50/8; + x7 = ( (8*t)+7 ) * (22.0/7.0) / 50/8; + y0 = $cos(x0)*1000*AMP+($random %10); + y1 = $cos(x1)*1000*AMP+($random %10); + y2 = $cos(x2)*1000*AMP+($random %10); + y3 = $cos(x3)*1000*AMP+($random %10); + y4 = $cos(x4)*1000*AMP+($random %10); + y5 = $cos(x5)*1000*AMP+($random %10); + y6 = $cos(x6)*1000*AMP+($random %10); + y7 = $cos(x7)*1000*AMP+($random %10); + adc_dt = {y7, y6, y5, y4, y3, y2, y1, y0}; + end + for (t=0; t<20; t=t+1) begin + @ (posedge adc_clk); #0.1; + y0 = ($random %100); + y1 = ($random %100); + y2 = ($random %100); + y3 = ($random %100); + y4 = ($random %100); + y5 = ($random %100); + y6 = ($random %100); + y7 = ($random %100); + adc_dt = {y7, y6, y5, y4, y3, y2, y1, y0}; + end + adc_dt = 0; +end +endtask + + +task SIM_RANDOM(); begin + for (t=0; t<50; t=t+1) begin + @ (posedge adc_clk); #0.1; + y0 = ($random %100); + y1 = ($random %100); + y2 = ($random %100); + y3 = ($random %100); + y4 = ($random %100); + y5 = ($random %100); + y6 = ($random %100); + y7 = ($random %100); + adc_dt = {y7, y6, y5, y4, y3, y2, y1, y0}; + end +end +endtask + +endmodule + + + + diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_smp_fifo.sv b/firmware/ip/qick_time_tagger/src/TB/tb_smp_fifo.sv new file mode 100644 index 0000000..e901444 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_smp_fifo.sv @@ -0,0 +1,185 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024-5-1 +// Versión : 1 +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/10ps + +`define WR_CLK 3 // Half Clock Period for Simulation +`define RD_CLK 11 // Half Clock Period for Simulation + +module tb_smp_mem(); + +parameter DW = 16 ; +parameter AW = 8 ; +parameter SMP_CK = 8 ; + +// Signals +/////////////////////////////////////////////////////////////////////////////// +reg wr_clk_i, rd_clk_i; +reg rst_ni, ready; + +// CLK +////////////////////////////////////////////////////////////////////////// +initial begin + wr_clk_i = 1'b0; + forever # (`WR_CLK) wr_clk_i = ~wr_clk_i; +end +initial begin + rd_clk_i = 1'b0; + forever # (`RD_CLK) rd_clk_i = ~rd_clk_i; +end + +// READY +////////////////////////////////////////////////////////////////////////// +initial begin + ready = 1'b0; + forever begin + //#(1) + #(15*`RD_CLK*2) + //#(16) + @ (posedge rd_clk_i); #0.4; + ready = ~ready; + end +end + +reg [DW-1:0] data_i; +wire [AW-1:0] dma_qty ; +reg push_i, dma_pop_i; +reg flush_i; + +reg [SMP_CK*DW-1:0] adc_dt ; + +smp_mem # ( + .SMP_DW ( DW ) , // Samples WIDTH + .SMP_CK ( SMP_CK ) , // Samples per Clock + .SMP_FIFO_AW ( AW ) // Size of SAMPLES FIFO Memory +) SMP_MEM ( +// Core and AXI CLK & RST + .dma_clk_i ( rd_clk_i ) , + .dma_rst_ni ( rst_ni ) , + .adc_clk_i ( wr_clk_i ) , + .adc_rst_ni ( rst_ni ) , + .qtt_rst_req_i ( flush_i ) , + .qtt_rst_ack_o ( flush_o ) , + .cfg_smp_wr_qty_i ( 4'd5 ) , + .tag_wr_i ( push_i ) , + .adc_dt_i ( adc_dt ) , + .dma_pop_i ( dma_pop_i ) , + .dma_pop_o ( dma_pop_o ) , + .dma_dt_o ( dma_dt_o ) , + .dma_qty_o ( dma_qty ) , + .smp_empty_o ( ) , + .smp_full_o ( ) , + .smp_debug_o ( ) ); + +wire [DW-1:0] dma_dt_o; +reg dma_req_i; +reg [AW-1:0] dma_len_i; + +dma_fifo_rd # ( + .MEM_AW ( AW ) , // Memory Address Width + .MEM_DW ( DW) , // Memory Data Width + .DMA_DW ( DW) // DMA Data Width +) dma_fifo_rd ( + .clk_i ( rd_clk_i ) , + .rst_ni ( rst_ni ) , + .dma_req_i ( dma_req_i ) , + .dma_ack_o ( dma_ack_o ) , + .dma_len_i ( dma_len_i ) , + .pop_req_o ( dma_pop_i ) , + .pop_ack_i ( dma_pop_o ) , + .fifo_dt_i ( dma_dt_o ) , + .m_axis_tready_i ( ready ) , + .m_axis_tdata_o ( m_axis_tdata_o ) , + .m_axis_tvalid_o ( m_axis_tvalid_o ) , + .m_axis_tlast_o ( m_axis_tlast_o ) ); + + +initial begin + START_SIMULATION(); + FIFO_PUSH(); // Write 20 + #5000; + dma_len_i = 22; + FIFO_DMA(); + #50; + dma_len_i = 5; + FIFO_DMA(); + #50; +end + + +task START_SIMULATION (); begin + $display("START SIMULATION"); + rst_ni = 1'b0; +flush_i = 1'b0; + push_i = 0; + data_i = 5; + dma_pop_i = 1'b0; + dma_req_i = 0; + dma_len_i = 0; + adc_dt = 0 ; + #10; + @ (posedge rd_clk_i); #0.1; + rst_ni = 1'b1; + @ (posedge rd_clk_i); #0.1; + end +endtask + + + +integer t, x, y; +integer x0, x1, x2, x3,x4, x5, x6, x7 ; +reg [DW-1:0] y0, y1, y2, y3,y4, y5, y6, y7 ; + + +task FIFO_PUSH(); begin + $display("PUSH DATA"); + push_i = 1'b1; + @ (posedge wr_clk_i); #0.1; + push_i = 1'b0; + @ (posedge wr_clk_i); #0.1; + for (t=0; t<=9; t=t+1) begin + @ (posedge wr_clk_i); #0.1; + x0 = ( (8*t)+0 ) ; + x1 = ( (8*t)+1 ) ; + x2 = ( (8*t)+2 ) ; + x3 = ( (8*t)+3 ) ; + x4 = ( (8*t)+4 ) ; + x5 = ( (8*t)+5 ) ; + x6 = ( (8*t)+6 ) ; + x7 = ( (8*t)+7 ) ; + y0 = x0 ; + y1 = x1 ; + y2 = x2 ; + y3 = x3 ; + y4 = x4 ; + y5 = x5 ; + y6 = x6 ; + y7 = x7 ; + adc_dt = {y7, y6, y5, y4, y3, y2, y1, y0}; + end + push_i = 1'b0; +end + +endtask + + + +task FIFO_DMA(); begin + $display("DMA DATA"); + @ (posedge rd_clk_i); #0.1; + dma_req_i = 1'b1; + wait ( dma_ack_o == 1'b1); + dma_req_i = 1'b0; + wait ( dma_ack_o == 1'b0); + #10; + +end +endtask + + +endmodule diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_smp_fifo.wcfg b/firmware/ip/qick_time_tagger/src/TB/tb_smp_fifo.wcfg new file mode 100644 index 0000000..aa501d5 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_smp_fifo.wcfg @@ -0,0 +1,149 @@ + + + + + + + + + + + + + + + + + + + + + + + + adc_clk_i + adc_clk_i + + + dma_pop_i + dma_pop_i + + + smp_wr_st[31:0] + smp_wr_st[31:0] + + + smp_wr_cnt[7:0] + smp_wr_cnt[7:0] + + + tag_wr_i + tag_wr_i + + + adc_dt_i[127:0] + adc_dt_i[127:0] + + + smp_wr_dt[127:0] + smp_wr_dt[127:0] + + + data_i[127:0] + data_i[127:0] + + + push_i + push_i + + + mem[0:255][15:0] + mem[0:255][15:0] + UNSIGNEDDECRADIX + + + smp_empty_o + smp_empty_o + + + smp_full_o + smp_full_o + + + wr_push + wr_push + + + we_a_i + we_a_i + + + dt_a_i[15:0] + dt_a_i[15:0] + + + dma_clk_i + dma_clk_i + + + dma_pop_o + dma_pop_o + + + dma_dt_o[31:0] + dma_dt_o[31:0] + UNSIGNEDDECRADIX + + + dma_qty_o[7:0] + dma_qty_o[7:0] + UNSIGNEDDECRADIX + + + m_axis_tdata_o[15:0] + m_axis_tdata_o[15:0] + UNSIGNEDDECRADIX + #0000FF + true + + + m_axis_tlast_o + m_axis_tlast_o + #0000FF + true + + + m_axis_tvalid_o + m_axis_tvalid_o + #0000FF + true + + + addr_a_i[7:0] + addr_a_i[7:0] + #FFFF00 + true + + + we_a_i + we_a_i + #FFFF00 + true + + + dt_a_i[15:0] + dt_a_i[15:0] + #FFFF00 + true + + + addr_b_i[7:0] + addr_b_i[7:0] + UNSIGNEDDECRADIX + + + dt_b_o[15:0] + dt_b_o[15:0] + UNSIGNEDDECRADIX + + diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_smp_mem.sv b/firmware/ip/qick_time_tagger/src/TB/tb_smp_mem.sv new file mode 100644 index 0000000..412611f --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_smp_mem.sv @@ -0,0 +1,184 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024-5-1 +// Versión : 1 +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/10ps + +`define WR_CLK 3 // Half Clock Period for Simulation +`define RD_CLK 11 // Half Clock Period for Simulation + +module tb_smp_mem(); + +parameter DW = 16 ; +parameter AW = 5 ; +parameter PUSH_QTY = 8 ; + +// Signals +/////////////////////////////////////////////////////////////////////////////// +reg wr_clk_i, rd_clk_i; +reg rst_ni, ready; + +// CLK +////////////////////////////////////////////////////////////////////////// +initial begin + wr_clk_i = 1'b0; + forever # (`WR_CLK) wr_clk_i = ~wr_clk_i; +end +initial begin + rd_clk_i = 1'b0; + forever # (`RD_CLK) rd_clk_i = ~rd_clk_i; +end + +// READY +////////////////////////////////////////////////////////////////////////// +initial begin + ready = 1'b0; + forever begin + //#(1) + #(5*`RD_CLK*2) + //#(16) + @ (posedge rd_clk_i); #0.4; + ready = ~ready; + end +end + +reg [DW-1:0] data_i; +wire [DW-1:0] data_0; +wire [20:0] dma_qty ; +reg push_i, dma_pop_i; +reg flush_i; + +reg [PUSH_QTY*DW-1:0] adc_dt ; + +SMP_MEM # ( + .PUSH_QTY ( PUSH_QTY ), // Number of Samples in adc_data (MAX 16) + .FIFO_DW ( DW ), // Sample Data Width + .FIFO_AW ( AW ) // Memory bit address Width +) SMP_MEM ( + .adc_clk_i ( wr_clk_i ), + .adc_rst_ni ( rst_ni ), + .dma_clk_i ( rd_clk_i ), + .dma_rst_ni ( rst_ni ), + .flush_i ( flush_i ), + .flush_o ( flush_o ), + .adc_push_i ( push_i ), + .adc_data_i ( adc_dt ), + .dma_pop_i ( dma_pop_i ), + .dma_pop_o ( dma_pop_o ), + .dma_qty_o ( dma_qty ), + .dma_empty_o ( ), + .dt_o ( fifo_dt_o ), + .full_o ( ), + .debug_do ( )); + +wire [DW-1:0] fifo_dt_o; +reg dma_req_i; +reg [AW-1:0] dma_len_i; + +dma_fifo_rd # ( + .MEM_AW ( AW ) , // Memory Address Width + .MEM_DW ( DW) , // Memory Data Width + .DMA_DW ( DW) // DMA Data Width +) dma_fifo_rd ( + .clk_i ( rd_clk_i ) , + .rst_ni ( rst_ni ) , + .dma_req_i ( dma_req_i ) , + .dma_ack_o ( dma_ack_o ) , + .dma_len_i ( dma_len_i ) , + .pop_req_o ( dma_pop_i ) , + .pop_ack_i ( dma_pop_o ) , + .fifo_dt_i ( fifo_dt_o ) , + .m_axis_tready_i ( ready ) , + .m_axis_tdata_o ( m_axis_tdata_o ) , + .m_axis_tvalid_o ( m_axis_tvalid_o ) , + .m_axis_tlast_o ( m_axis_tlast_o ) ); + + +initial begin + START_SIMULATION(); + FIFO_PUSH(); // Write 20 + #50; + dma_len_i = 22; + FIFO_DMA(); + #50; + dma_len_i = 5; + FIFO_DMA(); + #50; +end + + +task START_SIMULATION (); begin + $display("START SIMULATION"); + rst_ni = 1'b0; +flush_i = 1'b0; + push_i = 0; + data_i = 5; + dma_pop_i = 1'b0; + dma_req_i = 0; + dma_len_i = 0; + adc_dt = 0 ; + #10; + @ (posedge rd_clk_i); #0.1; + rst_ni = 1'b1; + @ (posedge rd_clk_i); #0.1; + end +endtask + + + +integer t, x, y; +integer x0, x1, x2, x3,x4, x5, x6, x7 ; +reg [DW-1:0] y0, y1, y2, y3,y4, y5, y6, y7 ; + + +task FIFO_PUSH(); begin + $display("PUSH DATA"); + for (t=0; t<=10; t=t+1) begin + @ (posedge wr_clk_i); #0.1; + x0 = ( (8*t)+0 ) ; + x1 = ( (8*t)+1 ) ; + x2 = ( (8*t)+2 ) ; + x3 = ( (8*t)+3 ) ; + x4 = ( (8*t)+4 ) ; + x5 = ( (8*t)+5 ) ; + x6 = ( (8*t)+6 ) ; + x7 = ( (8*t)+7 ) ; + y0 = x0 ; + y1 = x1 ; + y2 = x2 ; + y3 = x3 ; + y4 = x4 ; + y5 = x5 ; + y6 = x6 ; + y7 = x7 ; + adc_dt = {y7, y6, y5, y4, y3, y2, y1, y0}; + push_i = 1'b1; + @ (posedge wr_clk_i); #0.1; + push_i = 1'b0; + @ (posedge wr_clk_i); #0.1; + end + push_i = 1'b0; +end + +endtask + + + +task FIFO_DMA(); begin + $display("DMA DATA"); + @ (posedge rd_clk_i); #0.1; + dma_req_i = 1'b1; + wait ( dma_ack_o == 1'b1); + dma_req_i = 1'b0; + wait ( dma_ack_o == 1'b0); + #10; + +end +endtask + + +endmodule diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_tag_fifo.sv b/firmware/ip/qick_time_tagger/src/TB/tb_tag_fifo.sv new file mode 100644 index 0000000..15eddc1 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_tag_fifo.sv @@ -0,0 +1,239 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024-5-1 +// Versión : 1 +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/10ps + +`define WR_CLK 3 // Half Clock Period for Simulation +`define RD_CLK 11 // Half Clock Period for Simulation +`define CORE_CLK 5 // Half Clock Period for Simulation + +module tb_tag_mem(); + + +parameter MEM_QTY = 4 ; +parameter DW = 32 ; +parameter AW = 16 ; +//parameter SMP_CK = 8 ; + +// Signals +/////////////////////////////////////////////////////////////////////////////// +reg wr_clk_i, rd_clk_i, core_clk_i; +reg rst_ni, ready; + +// CLK +////////////////////////////////////////////////////////////////////////// +initial begin + wr_clk_i = 1'b0; + forever # (`WR_CLK) wr_clk_i = ~wr_clk_i; +end +initial begin + rd_clk_i = 1'b0; + forever # (`RD_CLK) rd_clk_i = ~rd_clk_i; +end +initial begin + core_clk_i = 1'b0; + forever # (`CORE_CLK) core_clk_i = ~core_clk_i; +end + +// READY +////////////////////////////////////////////////////////////////////////// +initial begin + ready = 1'b0; + forever begin + //#(1) + #(15*`RD_CLK*2) + //#(16) + @ (posedge rd_clk_i); #0.4; + ready = ~ready; + end +end + +reg [DW-1:0] data_i; +reg push_i, dma_pop_i; +reg flush_i; + +reg [MEM_QTY-1:0] tag_wr_i; +reg [31:0] tag_dt_i [MEM_QTY] ; +reg [AW-1:0] dma_qty_o[MEM_QTY] ; +wire [DW-1:0] dma_dt_o; + +reg [32-1:0] tag_debug_o ; +reg [AW-1:0] proc_qty_o ; +reg qtt_pop_req; +reg [DW-1:0] m_axis_tdata_o ; + + +tag_mem # ( + .MEM_QTY ( MEM_QTY ), // Amount of Memories +// .DMA_RD ( 1 ), // TAG FIFO Read from DMA +// .PROC_RD ( 0 ), // TAG FIFO Read from tProcessor + .TAG_FIFO_AW ( AW ), // Size of TAG FIFO Memory + .DEBUG ( 0 ) +) TAG_MEM ( + .dma_clk_i ( rd_clk_i ), + .dma_rst_ni ( rst_ni ), + .c_clk_i ( core_clk_i ), + .c_rst_ni ( rst_ni ), + .adc_clk_i ( wr_clk_i ), + .adc_rst_ni ( rst_ni ), + .qtt_pop_req_i ( qtt_pop_req ), + .qtt_rst_req_i ( flush_i ), + .qtt_rst_ack_o ( qtt_rst_ack_o ), + .tag_wr_i ( tag_wr_i ), + .tag_dt_i ( tag_dt_i ), + .dma_qty_o ( dma_qty_o ), + .proc_qty_o ( proc_qty_o ), + .empty_o ( tag_empty_o ), + .full_o ( tag_full_o ), + .dma_sel_i ( dma_sel_i ), + .dma_pop_i ( dma_pop_i ), + .dma_pop_o ( dma_pop_o ), + .dma_dt_o ( dma_dt_o ), + .debug_do ( tag_debug_o ) +); + +reg dma_req_i; +reg [AW-1:0] dma_len_i; + +dma_fifo_rd # ( + .MEM_AW ( AW ) , // Memory Address Width + .MEM_DW ( DW) , // Memory Data Width + .DMA_DW ( DW) // DMA Data Width +) dma_fifo_rd ( + .clk_i ( rd_clk_i ) , + .rst_ni ( rst_ni ) , + .dma_req_i ( dma_req_i ) , + .dma_ack_o ( dma_ack_o ) , + .dma_len_i ( dma_len_i ) , + .pop_req_o ( dma_pop_i ) , + .pop_ack_i ( dma_pop_o ) , + .fifo_dt_i ( dma_dt_o ) , + .m_axis_tready_i ( ready ) , + .m_axis_tdata_o ( m_axis_tdata_o ) , + .m_axis_tvalid_o ( m_axis_tvalid_o ) , + .m_axis_tlast_o ( m_axis_tlast_o ) ); + +reg [3:0] tag_wr_sel; +reg [1:0] dma_sel_i; +initial begin + START_SIMULATION(); + #1000; + tag_wr_sel = 4'b0001; + TAG_WR(); + tag_wr_sel = 4'b0010; + TAG_WR(); + tag_wr_sel = 4'b0100; + TAG_WR(); + tag_wr_sel = 4'b1000; + TAG_WR(); + tag_wr_sel = 4'b1010; + TAG_WR(); + tag_wr_sel = 4'b0101; + TAG_WR(); + tag_wr_sel = 4'b1111; + TAG_WR(); + #1000; + +// @ (posedge wr_clk_i); #0.1; +// flush_i = 1'b1; +// @ (posedge wr_clk_i); #0.1; +// @ (posedge wr_clk_i); #0.1; +// flush_i = 1'b0; +// #1000; + + TAG_POP(); + TAG_POP(); + TAG_POP(); + + #1000; + dma_len_i = 22; + dma_sel_i = 2'b00; + FIFO_DMA(); + #1000; + dma_len_i = 5; + dma_sel_i = 2'b01; + FIFO_DMA(); + #1000; + dma_sel_i = 2'b10; + FIFO_DMA(); + #1000; + dma_sel_i = 2'b11; + FIFO_DMA(); + #1000; +end + + +task START_SIMULATION (); begin + $display("START SIMULATION"); + rst_ni = 1'b0; +flush_i = 1'b0; + push_i = 0; + data_i = 5; + dma_sel_i = 2'b00; + dma_pop_i = 1'b0; + dma_req_i = 0; + dma_len_i = 0; + qtt_pop_req = 0; + tag_wr_i = '{default:'0} ; + tag_dt_i = '{default:'0} ; + #10; + @ (posedge rd_clk_i); #0.1; + rst_ni = 1'b1; + @ (posedge rd_clk_i); #0.1; + end +endtask + + + +integer t, ind; +task TAG_WR(); begin + $display("PUSH DATA"); + @ (posedge wr_clk_i); #0.1; + for (t=0; t<=9; t=t+1) begin + @ (posedge wr_clk_i); #0.1; + for (ind=0; ind<=MEM_QTY; ind=ind+1) begin + tag_dt_i[ind] = ((ind+1)*t+ind+1); + tag_wr_i[ind] = tag_wr_sel[ind]; + @ (posedge wr_clk_i); #0.1; + tag_wr_i = '{default:'0}; + end + end + push_i = 1'b0; +end + +endtask + +task TAG_POP(); begin + $display("POP TAGS"); + @ (posedge core_clk_i); #0.1; + for (t=0; t<=9; t=t+1) begin + @ (posedge core_clk_i); #0.1; + qtt_pop_req = 1; + @ (posedge core_clk_i); #0.1; + qtt_pop_req = 0; + #200; + end +end + +endtask + + +task FIFO_DMA(); begin + $display("DMA DATA"); + @ (posedge rd_clk_i); #0.1; + dma_req_i = 1'b1; + wait ( dma_ack_o == 1'b1); + dma_req_i = 1'b0; + wait ( dma_ack_o == 1'b0); + #10; + +end +endtask + + +endmodule diff --git a/firmware/ip/qick_time_tagger/src/TB/tb_tag_fifo.wcfg b/firmware/ip/qick_time_tagger/src/TB/tb_tag_fifo.wcfg new file mode 100644 index 0000000..51ebce9 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/TB/tb_tag_fifo.wcfg @@ -0,0 +1,84 @@ + + + + + + + + + + + + + + + + + + + + + + + + adc_clk_i + adc_clk_i + + + tag_dt_i[0:3][31:0] + tag_dt_i[0:3][31:0] + UNSIGNEDDECRADIX + + + + tag_wr_i[0:3] + tag_wr_i[0:3] + UNSIGNEDDECRADIX + + + + dma_clk_i + dma_clk_i + + + dma_sel_i[1:0] + dma_sel_i[1:0] + + + dma_dt_o[31:0] + dma_dt_o[31:0] + + + dma_req_i + dma_req_i + + + dma_ack_o + dma_ack_o + + + m_axis_tdata_o[15:0] + m_axis_tdata_o[15:0] + UNSIGNEDDECRADIX + #0000FF + true + + + m_axis_tvalid_o + m_axis_tvalid_o + #0000FF + true + + + m_axis_tlast_o + m_axis_tlast_o + #0000FF + true + + + dma_qty_o[0:3][7:0] + dma_qty_o[0:3][7:0] + UNSIGNEDDECRADIX + + + diff --git a/firmware/ip/qick_time_tagger/src/_qtt_dma.sv b/firmware/ip/qick_time_tagger/src/_qtt_dma.sv new file mode 100644 index 0000000..3786567 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/_qtt_dma.sv @@ -0,0 +1,184 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_5_31 +/////////////////////////////////////////////////////////////////////////////// + +module dma_fifo_rd # ( + parameter MEM_AW = 16 , // Memory Address Width + parameter MEM_DW = 8 , // Memory Data Width + parameter DMA_DW = 8 // DMA Data Width +) ( + input wire clk_i , + input wire rst_ni , + input wire dma_req_i , + output wire dma_ack_o , + input wire [MEM_AW-1:0] dma_len_i , + output wire pop_req_o , //fifo_pop_o , + input wire pop_ack_i , //fifo_pop_i , + input wire [MEM_DW-1:0] fifo_dt_i , + input wire m_axis_tready_i , + output wire [DMA_DW-1:0] m_axis_tdata_o , + output wire m_axis_tvalid_o , + output wire m_axis_tlast_o , + output wire [15:0] dma_do , + output wire [25:0] dma_reg_do + ); + +///// Signals +/////////////////////////////////////////////////////////////////////////////// +reg [MEM_AW-1:0] len_cnt ; +wire [MEM_AW-1:0] len_cnt_p1 ; +reg len_cnt_rst, dma_rd_ack ; +reg fifo_rd ; // Reading FIFO for streaming +reg dt_bf ; // Data received when not Ready. Should Buffer +reg dt_vld ; // Data Valid on input. +reg dt_last ; // Last Data of Stream +reg dt_tx ; // Transmitting Data +reg dt_w ; // Data Buffered is is waiting for rdy + +reg [3:0] lp_cnt ; // Last FIFO REQ Pulse +wire [3:0] lp_cnt_p1 ; // Last FIFO REQ Pulse +reg lp_cnt_en ; // Last FIFO REQ Pulse + + +assign len_dma_one = (dma_len_i == 1) ; +assign len_cnt_last = (len_cnt_p1 == dma_len_i) ; +assign last_rd_addr = len_cnt_last & m_axis_tvalid_o ; + +///// DMA STATE +/////////////////////////////////////////////////////////////////////////////// +typedef enum { ST_IDLE, ST_TXING, ST_LAST, ST_END } TYPE_DMA_RD_ST; +(* fsm_encoding = "sequential" *) TYPE_DMA_RD_ST dma_rd_st; +TYPE_DMA_RD_ST dma_rd_st_nxt; + +always_ff @ (posedge clk_i, negedge rst_ni) begin + if ( !rst_ni ) dma_rd_st <= ST_IDLE; + else dma_rd_st <= dma_rd_st_nxt; +end + +always_comb begin + dma_rd_st_nxt = dma_rd_st; + dma_rd_ack = 1'b1; + len_cnt_rst = 1'b0; + fifo_rd = 1'b0; + dt_bf = 1'b0; + dt_vld = 1'b0; + dt_last = 1'b0; + dt_tx = 1'b0; + lp_cnt_en = 1'b0; + case (dma_rd_st) + ST_IDLE: begin + dma_rd_ack = 1'b0; + len_cnt_rst = 1'b1; + if (dma_req_i) + if (len_dma_one) dma_rd_st_nxt = ST_LAST; + else dma_rd_st_nxt = ST_TXING; + end + ST_TXING : begin + dt_bf = pop_ack_i & !m_axis_tready_i ; + fifo_rd = ~dt_bf; // Read From FIFO if no data is waiting for READY + dt_tx = 1'b1; + dt_vld = pop_ack_i ; + //if (len_cnt_last & len_cnt_en) + if (len_cnt_last & m_axis_tvalid_o) + dma_rd_st_nxt = ST_LAST; + end + ST_LAST : begin + lp_cnt_en = m_axis_tready_i; + fifo_rd = &lp_cnt; //Read from FIFO, every 8 READY (IN CASE TPROC has read ) + dt_bf = pop_ack_i & !m_axis_tready_i ; + dt_vld = pop_ack_i ; + dt_last = 1'b1; + dt_tx = 1'b1; + if ( m_axis_tvalid_o & m_axis_tready_i) dma_rd_st_nxt = ST_END; + end + ST_END : begin + if (!dma_req_i & m_axis_tready_i) dma_rd_st_nxt = ST_IDLE; + end + endcase +end + +// Len Count +assign len_cnt_p1 = len_cnt + 1'b1; + +always_ff @ (posedge clk_i, negedge rst_ni) begin + if ( !rst_ni ) + len_cnt <= 0; + else begin + if ( len_cnt_rst ) + len_cnt <= 1; + else if ( m_axis_tvalid_o ) + len_cnt <= len_cnt_p1; + end +end + +// Last Pulse Count +assign lp_cnt_p1 = lp_cnt + 1'b1; +always_ff @ (posedge clk_i, negedge rst_ni) begin + if ( !rst_ni ) lp_cnt <= 0; + else if ( lp_cnt_en ) lp_cnt <= lp_cnt_p1; + else lp_cnt <= 0; +end + + +// OUT Buffer +reg [MEM_DW-1:0] dt_r ; +always_ff @ (posedge clk_i, negedge rst_ni) begin + if ( !rst_ni ) begin + dt_r <= 0; + dt_w <= 0; + end else if ( dt_bf ) begin + dt_w <= 1'b1; + dt_r <= fifo_dt_i; + end else if ( dt_w & m_axis_tready_i) begin + dt_w <= 1'b0; + end +end + + +// Assign outputs. +reg [3:0] cnt_fifo_rd, cnt_vld; + +always_ff @ (posedge clk_i, negedge rst_ni) begin + if ( !rst_ni ) begin + cnt_fifo_rd <= 0; + cnt_vld <= 0; + end else begin + if ( dt_vld ) cnt_fifo_rd <= cnt_fifo_rd + 1'b1; + else if ( m_axis_tvalid_o ) cnt_vld <= cnt_vld + 1'b1; + end +end + +// ILA Debug 16 Bits +assign dma_do[0] = dma_req_i ; +assign dma_do[1] = dma_rd_ack ; +assign dma_do[2] = pop_req_o ; +assign dma_do[3] = pop_ack_i ; +assign dma_do[4] = fifo_rd ; +assign dma_do[5] = dt_tx ; +assign dma_do[6] = dt_w ; +assign dma_do[7] = dt_vld ; +assign dma_do[8] = dt_bf ; +assign dma_do[9] = lp_cnt_en ; +assign dma_do[11:10] = len_cnt[1:0]; +assign dma_do[13:12] = cnt_fifo_rd[1:0]; +assign dma_do[15:14] = cnt_vld[1:0]; + +// Register Debug 24 Bits +assign dma_reg_do[9:0] = dma_do[9:0]; +assign dma_reg_do[15:10] = len_cnt[5:0]; +assign dma_reg_do[19:16] = cnt_fifo_rd; +assign dma_reg_do[23:20] = cnt_vld ; +assign dma_reg_do[25:24] = dma_rd_st[1:0] ; + +assign pop_req_o = fifo_rd & m_axis_tready_i ; +assign m_axis_tvalid_o = dt_tx & (dt_w | dt_vld) & m_axis_tready_i ; +assign m_axis_tdata_o = dt_w ? dt_r : fifo_dt_i ; +assign m_axis_tlast_o = dt_last & m_axis_tvalid_o;; +assign dma_ack_o = dma_rd_ack ; + +endmodule + + diff --git a/firmware/ip/qick_time_tagger/src/_qtt_ips.sv b/firmware/ip/qick_time_tagger/src/_qtt_ips.sv new file mode 100644 index 0000000..76bdd66 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/_qtt_ips.sv @@ -0,0 +1,385 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_5_31 +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +/// Clock Domain Register Change +/////////////////////////////////////////////////////////////////////////////// +/* +sync_reg # ( + .DW ( ) +) sync_tx_i ( + .dt_i ( ) , + .clk_i ( ) , + .rst_ni ( ) , + .dt_o ( ) ); +*/ + +module sync_reg # ( + parameter DW = 32 +)( + input wire [DW-1:0] dt_i , + input wire clk_i , + input wire rst_ni , + output wire [DW-1:0] dt_o ); + +(* ASYNC_REG = "TRUE" *) reg [DW-1:0] data_rcd, data_r ; +always_ff @(posedge clk_i) + if(!rst_ni) begin + data_rcd <= 0; + data_r <= 0; + end else begin + data_rcd <= dt_i; + data_r <= data_rcd; + end +assign dt_o = data_r ; + +endmodule + +/////////////////////////////////////////////////////////////////////////////// +/// Priority Encoder +/////////////////////////////////////////////////////////////////////////////// +module priority_encoder # ( + parameter DW = 5 , + parameter OUT = "NO_REG" +)( + input wire clk_i , + input wire rst_ni , + input wire [2**DW-1:0] one_hot_dt_i , + output reg [DW-1:0] bin_dt_o , + output reg vld_o ); + +localparam ONE_HOT_DW = 2**DW; + +integer i ; +reg valid; +reg [DW-1 : 0] bin_dt ; + +always_comb begin + valid = 1'b0; + bin_dt = 0; + for (i = 0 ; i < ONE_HOT_DW; i=i+1) + if (!valid & one_hot_dt_i[i]) begin + valid = 1'b1; + bin_dt = i; + end +end + +generate + if (OUT == "NO_REG") begin: no_output_register // 1 clock cycle read + assign vld_o = valid ; + assign bin_dt_o = bin_dt ; + end else begin: output_register // 2 clock cycle read + reg vld_r = {DW{1'b0}}; + reg [DW-1:0] bin_dt_r = {DW{1'b0}}; + always @(posedge clk_i) vld_r <= valid; + always @(posedge clk_i) bin_dt_r <= bin_dt; + assign vld_o = vld_r ; + assign bin_dt_o = bin_dt_r ; + end +endgenerate + +endmodule + + +/////////////////////////////////////////////////////////////////////////////// +/// Sincronice Chain of Pulses +/////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////// +/* +sync_pulse # ( + .QUEUE_AW ( ) + .BLOCK ( ) +) sync_p_i ( + .a_clk_i ( ) , + .a_rst_ni ( ) , + .a_pulse_i ( ) , + .b_clk_i ( ) , + .b_rst_ni ( ) , + .b_pulse_o ( ) , + .pulse_full ( ) ); +*/ +module sync_pulse # ( + parameter QUEUE_AW = 4 , + parameter BLOCK = 0 +) ( + input wire a_clk_i , + input wire a_rst_ni , + input wire a_pulse_i , + input wire b_clk_i , + input wire b_rst_ni , + input wire b_en_i , + output reg b_pulse_o , + output wire pulse_full ); + +wire [QUEUE_AW-1:0] wr_gptr_p1, rd_gptr_p1 ; +wire [QUEUE_AW-1:0] wr_gptr, rd_gptr ; + +// Pulse Counters +reg [QUEUE_AW-1:0] wr_gptr_cdc, wr_gptr_r; +always_ff @(posedge b_clk_i) begin + wr_gptr_cdc <= wr_gptr; + wr_gptr_r <= wr_gptr_cdc; +end + +//Check for Out Pulses +assign pulse_empty = (rd_gptr == wr_gptr_r) ; + + +///// DEBUG +generate + if (BLOCK) begin + // BLOCK IF QUEUE FULL + reg [QUEUE_AW-1:0] rd_gptr_rcd, rd_gptr_r; + always_ff @(posedge a_clk_i) begin + rd_gptr_rcd <= rd_gptr; + rd_gptr_r <= rd_gptr_rcd; + end + assign pulse_full = (rd_gptr_r == wr_gptr_p1) ; + end else begin + assign pulse_full = 1'b0; + end +endgenerate + +always @(posedge b_clk_i) begin + if ( !b_rst_ni ) b_pulse_o <= 1'b0; + else if ( b_pulse_o ) b_pulse_o <= 1'b0; + else if ( !pulse_empty & b_en_i) b_pulse_o <= 1'b1; +end + +//Gray Code Counters +gcc #( + .DW ( QUEUE_AW ) +) gcc_wr_ptr ( + .clk_i ( a_clk_i ) , + .rst_ni ( a_rst_ni ) , + .async_clear_i ( 1'b0 ) , + .clear_o ( ) , + .cnt_en_i ( a_pulse_i & ~pulse_full ) , + .count_bin_o ( ) , + .count_gray_o ( wr_gptr ) , + .count_bin_p1_o ( ) , + .count_gray_p1_o ( wr_gptr_p1 ) ); + +gcc #( + .DW ( QUEUE_AW ) +) gcc_rd_ptr ( + .clk_i ( b_clk_i ) , + .rst_ni ( b_rst_ni ) , + .async_clear_i ( 1'b0 ) , + .clear_o ( ) , + .cnt_en_i ( b_pulse_o ) , + .count_bin_o ( ) , + .count_gray_o ( rd_gptr ) , + .count_bin_p1_o ( ) , + .count_gray_p1_o ( rd_gptr_p1 ) ); + +endmodule + +/* +pulse_cdc pulse_cdc_inst ( + .clk_a_i ( ) , + .rst_a_ni ( ) , + .pulse_a_i ( ) , + .rdy_a_o ( ) , + .clk_b_i ( ) , + .rst_b_ni ( ) , + .pulse_b_o ( ) ); +*/ +module pulse_cdc ( + input wire clk_a_i , + input wire rst_a_ni , + input wire pulse_a_i , + output wire rdy_a_o , + input wire clk_b_i , + input wire rst_b_ni , + output wire pulse_b_o ); + +/// REQ +/////////////////////////////////////////////////////////////////////////////// +reg a_pulse_req; +always_ff @ (posedge clk_a_i, negedge rst_a_ni) begin + if ( !rst_a_ni ) begin + a_pulse_req <= 1'b0; + end else + if ( pulse_a_i ) a_pulse_req <= 1'b1; + else if ( a_pulse_ack ) a_pulse_req <= 1'b0; +end + +(* ASYNC_REG = "TRUE" *) reg pulse_req_cdc, b_pulse_req ; +reg pulse_b_req_r, pulse_b; +always_ff @(posedge clk_b_i, negedge rst_b_ni) + if(!rst_b_ni) begin + pulse_req_cdc <= 0; + b_pulse_req <= 0; + pulse_b_req_r <= 0; + pulse_b <= 0; + end else begin + pulse_req_cdc <= a_pulse_req; + b_pulse_req <= pulse_req_cdc; + pulse_b_req_r <= b_pulse_req; + pulse_b <= b_pulse_req & !pulse_b_req_r; + end + +/// ACK +/////////////////////////////////////////////////////////////////////////////// +reg b_pulse_ack; +always_ff @ (posedge clk_a_i, negedge rst_a_ni) begin + if ( !rst_a_ni ) begin + b_pulse_ack <= 1'b0; + end else + if ( b_pulse_req ) b_pulse_ack <= 1'b1; + else if ( !b_pulse_req ) b_pulse_ack <= 1'b0; +end + +(* ASYNC_REG = "TRUE" *) reg pulse_ack_cdc, a_pulse_ack ; +always_ff @(posedge clk_a_i, negedge rst_a_ni) + if(!rst_a_ni) begin + pulse_ack_cdc <= 0; + a_pulse_ack <= 0; + end else begin + pulse_ack_cdc <= b_pulse_ack; + a_pulse_ack <= pulse_ack_cdc; + end + +assign pulse_b_o = pulse_b; +assign rdy_a_o = !(a_pulse_req | a_pulse_ack); + +endmodule + + +/////////////////////////////////////////////////////////////////////////////// +// X-Interpolator +/////////////////////////////////////////////////////////////////////////////// +module x_inter #( + parameter DW = 16 , + parameter IW = 4 +) ( + input wire clk_i , + input wire rst_ni , + input wire start_i , + input wire [2:0] cfg_inter_i , + input wire [DW-1:0] curr_i , + input wire [DW-1:0] prev_i , + input wire [DW-1:0] thr_i , + output wire end_o , + output wire ready_o , + output wire [IW-1:0] x_int_o ); + +// Registers +reg [IW+DW-1:0] sub_temp, r_temp, r_temp_nxt; +reg [DW-1:0] inB ; +reg [IW-1:0] q_temp; +reg [2:0] ind_bit; +reg working, qtb; + +wire [2:0] ind_bit_m1 ; + +assign ind_bit_m1 = ind_bit - 1'b1; +assign div_start = start_i; +assign div_end = (ind_bit==0) ; + + +// State Machine +/////////////////////////////////////////////////////////////////////////// +enum {IDLE, WORKING} div_st, div_st_nxt; +always_ff @(posedge clk_i) + if (!rst_ni) div_st <= IDLE; + else div_st <= div_st_nxt; + +always_comb begin + div_st_nxt = div_st; + working = 1'b0; + case (div_st) + IDLE: begin + if ( div_start ) div_st_nxt = WORKING; + end + WORKING: begin + working = 1'b1; + if ( div_end ) begin + div_st_nxt = IDLE; + end + end + endcase +end + +always_ff @ (posedge clk_i) begin + if (!rst_ni) begin + ind_bit <= -1; + q_temp <= 0 ; + r_temp <= 0 ; + inB <= 0 ; + end else if (div_start) begin + ind_bit <= cfg_inter_i; + q_temp <= 0 ; + r_temp <= ( (thr_i - prev_i) << cfg_inter_i); + inB <= ( curr_i - prev_i ); + end else if (working) begin + ind_bit <= ind_bit_m1; + r_temp <= r_temp_nxt ; + q_temp[ind_bit_m1] <= qtb ; + end +end + +/////////////////////////////////////////////////////////////////////////// +always_comb begin + qtb = 1'b0; + r_temp_nxt = r_temp ; + sub_temp = inB << ind_bit_m1 ; + if (r_temp >= sub_temp ) begin + qtb = 1'b1 ; + r_temp_nxt = r_temp - sub_temp ; + end else + r_temp_nxt = r_temp; +end + +/* +// In case wnat to use a DSP +wire [IW+DW-1:0] d_sub_a; +reg [IW+DW-1:0] r_temp_nxt_dsp, sub_temp_dsp; +ADDSUB_MACRO #( + .DEVICE ("7SERIES"), // Target Device: "7SERIES" + .LATENCY (0), // Desired clock cycle latency, 0-2 + .WIDTH (IW+DW) // Input / output bus width, 1-48 + ) ADDSUB_MACRO_inst ( + .CARRYOUT ( ), // 1-bit carry-out output signal + .RESULT ( d_sub_a ),// Add/sub result output, width defined by WIDTH parameter + .A ( r_temp ),// Input A bus, width defined by WIDTH parameter + .ADD_SUB ( 1'b0 ),// 1-bit add/sub input, high selects add, low selects subtract + .B ( sub_temp_dsp ),// Input B bus, width defined by WIDTH parameter + .CARRYIN ( 1'b0 ),// 1-bit carry-in input + .CE ( 1'b1 ),// 1-bit clock enable input + .CLK ( clk_i ),// 1-bit clock input + .RST ( ~rst_ni) // 1-bit active high synchronous reset +); + +always_comb begin + qtb = 1'b0; + sub_temp_dsp = inB << ind_bit_m1 ; + if (d_sub_a[IW+DW-1] == r_temp[IW+DW-1]) begin // (r_temp >= sub_temp ) begin + qtb = 1'b1 ; + r_temp_nxt_dsp = d_sub_a ; + end else + r_temp_nxt_dsp = r_temp; +end +*/ + +/////////////////////////////////////////////////////////////////////////// +// OUT REG +//always_ff @ (posedge clk_i) begin +// if (!rst_ni) x_int_o <= 0; +// else if (div_end) x_int_o <= q_temp; +//end + +assign x_int_o = q_temp; +assign ready_o = ~working; +assign end_o = div_end; + + + +endmodule + diff --git a/firmware/ip/qick_time_tagger/src/_qtt_mem.sv b/firmware/ip/qick_time_tagger/src/_qtt_mem.sv new file mode 100644 index 0000000..fbf4a01 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/_qtt_mem.sv @@ -0,0 +1,311 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024-5-1 +// Versión : 2 +/////////////////////////////////////////////////////////////////////////////// +// BRAM_DP_DC_EN +// gcc +// FIFO_DC +// BRAM_SC +// TAG_FIFO_TC + +////////////////////////////////////////////////////////////////////////////// +// BRAM +////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////// +module BRAM_DP_DC_EN # ( + parameter MEM_AW = 16 , + parameter MEM_DW = 16 , + parameter RAM_OUT = "NO_REG" // Select "NO_REG" or "REG" +) ( + input wire clk_a_i , + input wire en_a_i , + input wire we_a_i , + input wire [MEM_AW-1:0] addr_a_i , + input wire [MEM_DW-1:0] dt_a_i , + output wire [MEM_DW-1:0] dt_a_o , + input wire clk_b_i , + input wire en_b_i , + input wire we_b_i , + input wire [MEM_AW-1:0] addr_b_i , + input wire [MEM_DW-1:0] dt_b_i , + output wire [MEM_DW-1:0] dt_b_o ); + +localparam RAM_SIZE = 2**MEM_AW ; + +reg [MEM_DW-1:0] mem [RAM_SIZE]; +reg [MEM_DW-1:0] mem_dt_a = {MEM_DW{1'b0}}; +reg [MEM_DW-1:0] mem_dt_b = {MEM_DW{1'b0}}; + +always @(posedge clk_a_i) + if (en_a_i) begin + mem_dt_a <= mem[addr_a_i] ; + if (we_a_i) + mem[addr_a_i] <= dt_a_i; + end +always @(posedge clk_b_i) + if (en_b_i) + if (we_b_i) + mem[addr_b_i] <= dt_b_i; + else + mem_dt_b <= mem[addr_b_i] ; + +generate + if (RAM_OUT == "NO_REG") begin: no_output_register // 1 clock cycle read + assign dt_a_o = mem_dt_a ; + assign dt_b_o = mem_dt_b ; + end else begin: output_register // 2 clock cycle read + reg [MEM_DW-1:0] mem_dt_a_r = {MEM_DW{1'b0}}; + reg [MEM_DW-1:0] mem_dt_b_r = {MEM_DW{1'b0}}; + always @(posedge clk_a_i) if (en_a_i) mem_dt_a_r <= mem_dt_a; + always @(posedge clk_b_i) if (en_b_i) mem_dt_b_r <= mem_dt_b; + assign dt_a_o = mem_dt_a_r ; + assign dt_b_o = mem_dt_b_r ; + end +endgenerate + +endmodule + + + + + + +//GRAY CODE COUNTER +////////////////////////////////////////////////////////////////////////////// +module gcc # ( + parameter DW = 32 +)( + input wire clk_i , + input wire rst_ni , + input wire async_clear_i , + output wire clear_o , + input wire cnt_en_i , + output wire [DW-1:0] count_bin_o , + output wire [DW-1:0] count_gray_o , + output wire [DW-1:0] count_bin_p1_o , + output wire [DW-1:0] count_gray_p1_o); + +reg [DW-1:0] count_bin ; // count turned into binary number +wire [DW-1:0] count_bin_p1; // count_bin+1 + +reg [DW-1:0] count_bin_r, count_gray_r; + +integer ind; +always_comb begin + count_bin[DW-1] = count_gray_r[DW-1]; + for (ind=DW-2 ; ind>=0; ind=ind-1) begin + count_bin[ind] = count_bin[ind+1]^count_gray_r[ind]; + end +end + +reg clear_rcd, clear_r; +always_ff @(posedge clk_i, negedge rst_ni) + if(!rst_ni) begin + clear_rcd <= 0; + clear_r <= 0; + end else begin + clear_rcd <= async_clear_i; + clear_r <= clear_rcd; + end + +assign count_bin_p1 = count_bin + 1'b1 ; + +reg [DW-1:0] count_bin_2r, count_gray_2r; +always_ff @(posedge clk_i, negedge rst_ni) + if(!rst_ni) begin + count_gray_r <= 1; + count_bin_r <= 1; + count_gray_2r <= 0; + count_bin_2r <= 0; + end else begin + if (clear_r) begin + count_gray_r <= 1; + count_bin_r <= 1; + count_gray_2r <= 0; + count_bin_2r <= 0; + end else if (cnt_en_i) begin + count_gray_r <= count_bin_p1 ^ {1'b0,count_bin_p1[DW-1:1]}; + count_bin_r <= count_bin_p1; + count_gray_2r <= count_gray_r; + count_bin_2r <= count_bin_r; + + end + end + +assign clear_o = clear_r ; +assign count_bin_o = count_bin_2r ; +assign count_gray_o = count_gray_2r ; +assign count_bin_p1_o = count_bin_r ; +assign count_gray_p1_o = count_gray_r ; + +endmodule + +////////////////////////////////////////////////////////////////////////////// +module FIFO_DC # ( + parameter FIFO_DW = 32 , + parameter FIFO_AW = 18 +) ( + input wire wr_clk_i , + input wire wr_rst_ni , + input wire wr_en_i , + input wire push_i , + input wire [FIFO_DW - 1:0] data_i , + input wire rd_clk_i , + input wire rd_rst_ni , + input wire rd_en_i , + input wire pop_i , + output wire [FIFO_DW - 1:0] data_o , + input wire flush_i , + output wire async_empty_o , + output wire async_full_o ); + +// The WRITE_POINTER is on the Last Empty Value +// The READ_POINTER is on the Last Value +wire [FIFO_AW-1:0] rd_gptr_p1 ; +wire [FIFO_AW-1:0] wr_gptr_p1 ; +wire [FIFO_AW-1:0] rd_ptr, wr_ptr, rd_gptr, wr_gptr ; +wire clr_wr, clr_rd; + +// Sample Pointers +reg [FIFO_AW-1:0] wr_gptr_rcd, wr_gptr_r; +always_ff @(posedge rd_clk_i) begin + wr_gptr_rcd <= wr_gptr; + wr_gptr_r <= wr_gptr_rcd; +end + +reg [FIFO_AW-1:0] rd_gptr_rcd, rd_gptr_r; +always_ff @(posedge wr_clk_i) begin + rd_gptr_rcd <= rd_gptr; + rd_gptr_r <= rd_gptr_rcd; +end + + +reg clr_fifo_req, clr_fifo_ack; +reg clr_rd_rdc, clr_rd_r; +always_ff @(posedge wr_clk_i, negedge wr_rst_ni) begin + if (!wr_rst_ni) begin + clr_fifo_req <= 0 ; + clr_fifo_ack <= 0 ; + clr_rd_rdc <= 0 ; + clr_rd_r <= 0 ; + end else begin + clr_rd_rdc <= clr_rd; + clr_rd_r <= clr_rd_rdc; + if ( flush_i ) clr_fifo_req <= 1 ; + else if ( clr_fifo_ack ) clr_fifo_req <= 0 ; + if ( clear_all ) clr_fifo_ack <= 1 ; + else if ( clr_fifo_ack & clear_none) clr_fifo_ack <= 0 ; + end +end + +assign clear_all = clr_rd_r & clr_wr; +assign clear_none = !clr_rd_r & !clr_wr; + +wire busy; +assign busy = clr_fifo_ack | clr_fifo_req ; + +wire [FIFO_DW - 1:0] mem_dt; + +wire async_empty, async_full; + +//SYNC with POP (RD_CLK) +assign async_empty = (rd_gptr == wr_gptr_r) ; + +//SYNC with PUSH (WR_CLK) +assign async_full = (rd_gptr_r == wr_gptr_p1) ; + +wire do_pop, do_push; +assign do_pop = pop_i & !async_empty; +assign do_push = push_i & !async_full; + +assign async_empty_o = async_empty | busy; // While RESETTING, Shows EMPTY +assign async_full_o = async_full | busy; +assign data_o = mem_dt; + +//Gray Code Counters +gcc #( + .DW ( FIFO_AW ) +) gcc_wr_ptr ( + .clk_i ( wr_clk_i ) , + .rst_ni ( wr_rst_ni ) , + .async_clear_i ( clr_fifo_req ) , + .clear_o ( clr_wr ) , + .cnt_en_i ( do_push ) , + .count_bin_o ( wr_ptr ) , + .count_gray_o ( wr_gptr ) , + .count_bin_p1_o ( ) , + .count_gray_p1_o ( wr_gptr_p1 ) ); + +gcc #( + .DW ( FIFO_AW ) +) gcc_rd_ptr ( + .clk_i ( rd_clk_i ) , + .rst_ni ( rd_rst_ni ) , + .async_clear_i ( clr_fifo_req ) , + .clear_o ( clr_rd ) , + .cnt_en_i ( do_pop ) , + .count_bin_o ( rd_ptr ) , + .count_gray_o ( rd_gptr ) , + .count_bin_p1_o ( ) , + .count_gray_p1_o ( rd_gptr_p1 ) ); + +// Data +BRAM_DP_DC_EN # ( + .MEM_AW ( FIFO_AW ) , + .MEM_DW ( FIFO_DW ) , + .RAM_OUT ( "NO_REG" ) // Select "NO_REG" or "REG" +) fifo_mem ( + .clk_a_i ( wr_clk_i ) , + .en_a_i ( wr_en_i ) , + .we_a_i ( do_push ) , + .addr_a_i ( wr_ptr ) , + .dt_a_i ( data_i ) , + .dt_a_o ( ) , + .clk_b_i ( rd_clk_i ) , + .en_b_i ( rd_en_i ) , + .we_b_i ( 1'b0 ) , + .addr_b_i ( rd_ptr ) , + .dt_b_i ( ) , + .dt_b_o ( mem_dt ) ); + +endmodule + +////////////////////////////////////////////////////////////////////////////// +module BRAM_SC # ( + parameter MEM_AW = 18 , + parameter MEM_DW = 32 +) ( + input wire clk_i , + input wire we_a_i , + input wire [MEM_AW-1:0] addr_a_i , + input wire [MEM_DW-1:0] dt_a_i , + input wire [MEM_AW-1:0] addr_b_i , + output wire [MEM_DW-1:0] dt_b_o ); + +localparam RAM_SIZE = 2**MEM_AW ; + +reg [MEM_DW-1:0] mem [RAM_SIZE]; +reg [MEM_DW-1:0] mem_dt_b = {MEM_DW{1'b0}}; + +// Port A WRITE only - Port B READ only +always @(posedge clk_i) begin + mem_dt_b <= mem[addr_b_i] ; + if (we_a_i) mem[addr_a_i] <= dt_a_i; +end + +assign dt_b_o = mem_dt_b ; + +endmodule + + + + + +/////////////////////////////////////////////////////////////////////////////// + + + diff --git a/firmware/ip/qick_time_tagger/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/qick_time_tagger/src/axi_mst_0/axi_mst_0.xci new file mode 100644 index 0000000..545bc11 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/axi_mst_0/axi_mst_0.xci @@ -0,0 +1,200 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_mst_0 + + + ACTIVE_LOW + + 100000000 + 0 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 2 + 32 + 0 + 0 + 0 + 32 + 0 + 0 + 32 + 0 + 0 + 0 + axi_mst_0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + MASTER + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + zynquplusRFSOC + xilinx.com:zcu111:part0:1.4 + + xczu28dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2020.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/ip/qick_time_tagger/src/axi_qick_time_tagger.sv b/firmware/ip/qick_time_tagger/src/axi_qick_time_tagger.sv new file mode 100644 index 0000000..8e844c1 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/axi_qick_time_tagger.sv @@ -0,0 +1,338 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_7_24 +// Version : 13 +/////////////////////////////////////////////////////////////////////////////// +// QICK PROCESSOR : Time Tagger +////////////////////////////////////////////////////////////////////////////// + +module axi_qick_time_tagger # ( + parameter EXT_ARM = 0 , // External ARM Control + parameter ADC_QTY = 1 , // Number of ADC Inputs + parameter CMP_INTER = 4 , // Max Number of Interpolation bits + parameter ARM_STORE = 1 , // Store NUmber of Triggers on each ARM + parameter SMP_STORE = 0 , // Store Sample Values + parameter TAG_FIFO_AW = 16 , // Size of TAG FIFO Memory + parameter ARM_FIFO_AW = 10 , // Size of ARM FIFO Memory + parameter SMP_FIFO_AW = 18 , // Size of SAMPLE FIFO Memory + parameter CMP_SLOPE = 0 , // Compare with SLOPE Option + parameter SMP_DW = 16 , // Samples WIDTH + parameter SMP_CK = 8 , // Samples per Clock + parameter DEBUG = 1 +) ( +// Core and AXI CLK & RST + input wire c_clk , + input wire c_aresetn , + input wire adc_clk , + input wire adc_aresetn , + input wire ps_clk , + input wire ps_aresetn , +// EXTERNAL INTERFACE + input wire arm_i , + output wire trig_o , + output wire cmp_o , +// PROCESSOR INTERFACE + input wire qtag_en_i , + input wire [ 4:0] qtag_op_i , + input wire [31:0] qtag_dt1_i , + input wire [31:0] qtag_dt2_i , + input wire [31:0] qtag_dt3_i , + input wire [31:0] qtag_dt4_i , + output reg qtag_rdy_o , + output reg [31:0] qtag_dt1_o , + output reg [31:0] qtag_dt2_o , + output reg qtag_vld_o , + output reg qtag_flag_o , +// AXI INTERFACE + input wire [5:0] s_axi_awaddr , + input wire [2:0] s_axi_awprot , + input wire s_axi_awvalid , + output wire s_axi_awready , + input wire [31:0] s_axi_wdata , + input wire [ 3:0] s_axi_wstrb , + input wire s_axi_wvalid , + output wire s_axi_wready , + output wire [ 1:0] s_axi_bresp , + output wire s_axi_bvalid , + input wire s_axi_bready , + input wire [ 5:0] s_axi_araddr , + input wire [ 2:0] s_axi_arprot , + input wire s_axi_arvalid , + output wire s_axi_arready , + output wire [31:0] s_axi_rdata , + output wire [ 1:0] s_axi_rresp , + output wire s_axi_rvalid , + input wire s_axi_rready , +///// ADC DATA + input wire adc0_s_axis_tvalid_i , + input wire [SMP_CK*SMP_DW-1:0] adc0_s_axis_tdata_i , + output wire adc0_s_axis_tready_o , + input wire adc1_s_axis_tvalid_i , + input wire [SMP_CK*SMP_DW-1:0] adc1_s_axis_tdata_i , + output wire adc1_s_axis_tready_o , + input wire adc2_s_axis_tvalid_i , + input wire [SMP_CK*SMP_DW-1:0] adc2_s_axis_tdata_i , + output wire adc2_s_axis_tready_o , + input wire adc3_s_axis_tvalid_i , + input wire [SMP_CK*SMP_DW-1:0] adc3_s_axis_tdata_i , + output wire adc3_s_axis_tready_o , +///// DATA DMA + input wire dma_m_axis_tready_i , + output wire dma_m_axis_tvalid_o , + output wire [31:0] dma_m_axis_tdata_o , + output wire dma_m_axis_tlast_o , +///// DEBUG + output wire [31:0] qtt_do + ); + +// Signal Declaration +////////////////////////////////////////////////////////////////////////// + + +wire [31:0] tag_dt ; +wire [TAG_FIFO_AW-1:0] dma_qty [4] ; +wire [TAG_FIFO_AW-1:0] proc_qty ; +wire [SMP_FIFO_AW-1:0] smp_qty ; +wire [ARM_FIFO_AW-1:0] arm_qty ; + + +wire [2:0] cfg_inter; +wire [4:0] qtt_op; + +wire [ 2:0] dma_mem_sel; +wire [19:0] dma_len; +wire [4:0] cfg_smp_wr_qty; + +// PERIPHERAL +/////////////////////////////////////////////////////////////////////////////// +wire [31:0] qtt_reg_debug_s, qtt_debug_s; + +wire [ 7:0] axi_reg_CTRL; +wire [10:0] axi_reg_CFG; +wire [23:0] axi_reg_DMA_CFG ; +wire [31:0] axi_reg_AXI_DT1 ; +wire [31:0] axi_reg_PROC_DT ; +wire [31:0] axi_reg_PROC_QTY, axi_reg_TAG0_QTY ; +wire [31:0] axi_reg_TAG1_QTY, axi_reg_TAG2_QTY, axi_reg_TAG3_QTY ; +wire [31:0] axi_reg_SMP_QTY, axi_reg_ARM_QTY ; +wire [31:0] axi_reg_THR_INH , axi_reg_QTT_STATUS, axi_reg_QTT_DEBUG; + +wire [SMP_DW-1:0] qtt_cmp_th; +wire[7:0] qtt_cmp_inh; +wire [23:0]qtt_reg_status_s; + +wire [SMP_CK*SMP_DW-1:0] adc_dt [ADC_QTY]; + +generate + if (ADC_QTY == 1 ) begin: ONE_ADC + assign adc_dt = '{adc0_s_axis_tdata_i}; + end else if (ADC_QTY == 2) begin: TWO_ADC + assign adc_dt = '{adc0_s_axis_tdata_i, adc1_s_axis_tdata_i}; + end else if (ADC_QTY == 3) begin: TWO_ADC + assign adc_dt = '{adc0_s_axis_tdata_i, adc1_s_axis_tdata_i, adc2_s_axis_tdata_i}; + end else if (ADC_QTY == 4) begin: TWO_ADC + assign adc_dt = '{adc0_s_axis_tdata_i, adc1_s_axis_tdata_i, adc2_s_axis_tdata_i, adc3_s_axis_tdata_i}; + end +endgenerate +generate + +endgenerate + +qick_time_tagger # ( + .ADC_QTY ( ADC_QTY ) , + .CMP_SLOPE ( CMP_SLOPE ) , + .CMP_INTER ( CMP_INTER ) , + .ARM_STORE ( ARM_STORE ) , + .SMP_STORE ( SMP_STORE ) , + .TAG_FIFO_AW ( TAG_FIFO_AW ) , + .ARM_FIFO_AW ( ARM_FIFO_AW ) , + .SMP_FIFO_AW ( SMP_FIFO_AW ) , + .SMP_DW ( SMP_DW ) , + .SMP_CK ( SMP_CK ) , + .DEBUG ( DEBUG ) +) QTT ( + .ps_clk_i ( ps_clk ) , + .ps_rst_ni ( ps_aresetn ) , + .c_clk_i ( c_clk ) , + .c_rst_ni ( c_aresetn ) , + .adc_clk_i ( adc_clk ) , + .adc_rst_ni ( adc_aresetn ) , + .qtt_pop_req_i ( qtt_pop_req ) , + .qtt_rst_req_i ( qtt_rst_req ) , + .qtt_rst_ack_o ( qtt_rst_ack ) , + .cfg_invert_i ( cfg_invert ), + .cfg_filter_i ( cfg_filter ), + .cfg_slope_i ( cfg_slope ), + .cfg_inter_i ( cfg_inter ), + .cfg_smp_wr_qty_i ( cfg_smp_wr_qty ) , + .arm_i ( qtt_arm ) , // Arm Trigger (ONE works) + .cmp_th_i ( qtt_cmp_th ) , // Threhold Data + .cmp_inh_i ( qtt_cmp_inh ) , // Inhibit Clock Pulses + .adc_dt_i ( adc_dt ) , +// DMA + .dma_req_i ( dma_rd ) , + .dma_mem_sel_i ( dma_mem_sel ) , + .dma_len_i ( dma_len ) , + .dma_ack_o ( ) , + .dma_m_axis_tready_i ( dma_m_axis_tready_i ) , + .dma_m_axis_tvalid_o ( dma_m_axis_tvalid_o ) , + .dma_m_axis_tdata_o ( dma_m_axis_tdata_o ) , + .dma_m_axis_tlast_o ( dma_m_axis_tlast_o ) , +//PROC + .tag_dt_o ( tag_dt ) , + .tag_vld_o ( qtt_tag_vld ) , + .trig_o ( trig_o ) , + .cmp_o ( cmp_o ) , +//DATA + .proc_qty_o ( proc_qty ) , + .dma_qty_o ( dma_qty ) , + .smp_qty_o ( smp_qty ) , + .arm_qty_o ( arm_qty ) , + .qtt_debug_o ( qtt_debug_s ) , + .qtt_reg_status_o ( qtt_reg_status_s ) , + .qtt_reg_debug_o ( qtt_reg_debug_s ) ); + +wire[7:0] cmd_cnt_do; +qtt_cmd CMD ( + .clk_i ( adc_clk ) , + .rst_ni ( adc_aresetn ) , + .c_clk_i ( c_clk ) , + .c_rst_ni ( c_aresetn ) , + .ext_arm_i ( arm_i ) , + .c_en_i ( qtag_en_i ) , + .c_op_i ( qtag_op_i ) , + .c_dt_i ( qtag_dt1_i ) , + .p_en_i ( qtt_cmd_en ) , + .p_op_i ( qtt_op ) , + .p_dt_i ( axi_reg_AXI_DT1 ) , + .pop_req_o ( qtt_pop_req ) , +// .pop_ack_i ( qtt_pop_ack ) , + .rst_req_o ( qtt_rst_req ) , + .rst_ack_i ( qtt_rst_ack ) , + .peek_o ( cmd_peek ) , + .qtt_arm_o ( qtt_arm ) , + .qtt_cmp_th_o ( qtt_cmp_th ) , + .qtt_cmp_inh_o ( qtt_cmp_inh ) , + .cmd_cnt_do ( cmd_cnt_do ) ); + + + +assign qtt_cmd_en = axi_reg_CTRL[0]; +assign qtt_op = {1'b0,axi_reg_CTRL[4:1]}; +assign dma_rd = axi_reg_CTRL[5]; + +assign cfg_filter = axi_reg_CFG[0]; +assign cfg_slope = axi_reg_CFG[1]; +assign cfg_inter = axi_reg_CFG[4:2]; +assign cfg_smp_wr_qty = axi_reg_CFG[9:5]; +assign cfg_invert = axi_reg_CFG[10]; + +assign dma_mem_sel = axi_reg_DMA_CFG[ 2:0]; +assign dma_len = axi_reg_DMA_CFG[23:4]; + +// AXI REGISTER ASSIGNMENT +/////////////////////////////////////////////////////////////////////////////// +localparam zf_taw = 20-TAG_FIFO_AW; +localparam zf_saw = 20-SMP_FIFO_AW; +localparam zf_aaw = 20-ARM_FIFO_AW; +localparam zf_th = 16-SMP_DW; + +assign axi_reg_PROC_DT = tag_dt; +assign axi_reg_PROC_QTY = { 12'd0, {zf_taw{1'b0}}, proc_qty }; +assign axi_reg_TAG0_QTY = { 12'd0, {zf_taw{1'b0}}, dma_qty[0] }; +assign axi_reg_TAG1_QTY = { 12'd0, {zf_taw{1'b0}}, dma_qty[1] }; +assign axi_reg_TAG2_QTY = { 12'd0, {zf_taw{1'b0}}, dma_qty[2] }; +assign axi_reg_TAG3_QTY = { 12'd0, {zf_taw{1'b0}}, dma_qty[3] }; +assign axi_reg_SMP_QTY = { 12'd0, {zf_saw{1'b0}}, smp_qty }; +assign axi_reg_ARM_QTY = { 12'd0, {zf_aaw{1'b0}}, arm_qty }; +assign axi_reg_THR_INH = { 8'd0, qtt_cmp_inh, {zf_th{1'b0}}, qtt_cmp_th }; +assign axi_reg_QTT_STATUS = { qtt_reg_status_s , cmd_cnt_do } ; + +///// DATA PROC + +/////////////////////////////////////////////////////////////////////////////// +// AXI Registers +/////////////////////////////////////////////////////////////////////////////// +axi_slv_qtt AXI_REG ( + .aclk ( ps_clk ), + .aresetn ( ps_aresetn ), + .awaddr ( s_axi_awaddr[5:0] ), + .awprot ( s_axi_awprot ), + .awvalid ( s_axi_awvalid ), + .awready ( s_axi_awready ), + .wdata ( s_axi_wdata ), + .wstrb ( s_axi_wstrb ), + .wvalid ( s_axi_wvalid ), + .wready ( s_axi_wready ), + .bresp ( s_axi_bresp ), + .bvalid ( s_axi_bvalid ), + .bready ( s_axi_bready ), + .araddr ( s_axi_araddr ), + .arprot ( s_axi_arprot ), + .arvalid ( s_axi_arvalid ), + .arready ( s_axi_arready ), + .rdata ( s_axi_rdata ), + .rresp ( s_axi_rresp ), + .rvalid ( s_axi_rvalid ), + .rready ( s_axi_rready ), +// Registers + .CTRL (axi_reg_CTRL ), + .CFG (axi_reg_CFG ), + .DMA_CFG (axi_reg_DMA_CFG ), + .AXI_DT1 (axi_reg_AXI_DT1 ), + .PROC_DT (axi_reg_PROC_DT ), + .PROC_QTY (axi_reg_PROC_QTY ), + .TAG0_QTY (axi_reg_TAG0_QTY ), + .TAG1_QTY (axi_reg_TAG1_QTY ), + .TAG2_QTY (axi_reg_TAG2_QTY ), + .TAG3_QTY (axi_reg_TAG3_QTY ), + .SMP_QTY (axi_reg_SMP_QTY ), + .ARM_QTY (axi_reg_ARM_QTY ), + .THR_INH (axi_reg_THR_INH ), + .QTT_STATUS (axi_reg_QTT_STATUS ), + .QTT_DEBUG (axi_reg_QTT_DEBUG ) +); + + + +/////////////////////////////////////////////////////////////////////////////// +// OUT SIGNALS +/////////////////////////////////////////////////////////////////////////////// +assign adc0_s_axis_tready_o = 1'b1; +assign adc1_s_axis_tready_o = 1'b1; +assign adc2_s_axis_tready_o = 1'b1; +assign adc3_s_axis_tready_o = 1'b1; + +assign qtag_rdy_o = 1; +assign qtag_dt1_o = tag_dt; +//assign qtag_dt2_o = axi_reg_PROC_QTY; +assign qtag_vld_o = qtt_tag_vld | cmd_peek; +assign qtag_flag_o = 0; + +sync_reg # ( + .DW ( 32 ) +) sync_dt2 ( + .dt_i ( axi_reg_PROC_QTY ) , + .clk_i ( c_clk ) , + .rst_ni ( c_aresetn ) , + .dt_o ( qtag_dt2_o ) ); + +// DEBUG +/////////////////////////////////////////////////////////////////////////////// +generate + if (DEBUG == 0 ) begin: DEBUG_NO + assign axi_reg_QTT_DEBUG = 0; + assign qtt_do = 0; + end else if (DEBUG == 1) begin: DEBUG_REG + assign axi_reg_QTT_DEBUG = qtt_reg_debug_s; + assign qtt_do = 0; + end else if (DEBUG == 2) begin: DEBUG_OUT + assign axi_reg_QTT_DEBUG = qtt_reg_debug_s; + assign qtt_do = qtt_debug_s; + end +endgenerate + + +endmodule diff --git a/firmware/ip/qick_time_tagger/src/axi_slv_qtt.vhd b/firmware/ip/qick_time_tagger/src/axi_slv_qtt.vhd new file mode 100644 index 0000000..5f37aea --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/axi_slv_qtt.vhd @@ -0,0 +1,521 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_slv_qtt is + Generic ( + DATA_WIDTH : integer := 32; + ADDR_WIDTH : integer := 6); + Port ( + aclk : in std_logic; + aresetn : in std_logic; + -- Write Address Channel. + awaddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + awprot : in std_logic_vector(2 downto 0); + awvalid : in std_logic; + awready : out std_logic; + -- Write Data Channel. + wdata : in std_logic_vector(DATA_WIDTH-1 downto 0); + wstrb : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + wvalid : in std_logic; + wready : out std_logic; + -- Write Response Channel. + bresp : out std_logic_vector(1 downto 0); + bvalid : out std_logic; + bready : in std_logic; + -- Read Address Channel. + araddr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + arprot : in std_logic_vector(2 downto 0); + arvalid : in std_logic; + arready : out std_logic; + -- Read Data Channel. + rdata : out std_logic_vector(DATA_WIDTH-1 downto 0); + rresp : out std_logic_vector(1 downto 0); + rvalid : out std_logic; + rready : in std_logic; + -- Registers. + CTRL : out std_logic_vector ( 7 downto 0) ; + CFG : out std_logic_vector (10 downto 0) ; + DMA_CFG : out std_logic_vector (23 downto 0) ; + AXI_DT1 : out std_logic_vector (31 downto 0) ; + PROC_DT : in std_logic_vector (31 downto 0) ; + PROC_QTY : in std_logic_vector (31 downto 0) ; + TAG0_QTY : in std_logic_vector (31 downto 0) ; + TAG1_QTY : in std_logic_vector (31 downto 0) ; + TAG2_QTY : in std_logic_vector (31 downto 0) ; + TAG3_QTY : in std_logic_vector (31 downto 0) ; + SMP_QTY : in std_logic_vector (31 downto 0) ; + ARM_QTY : in std_logic_vector (31 downto 0) ; + THR_INH : in std_logic_vector (31 downto 0) ; + QTT_STATUS : in std_logic_vector (31 downto 0) ; + QTT_DEBUG : in std_logic_vector (31 downto 0) ); +end axi_slv_qtt; + +architecture rtl of axi_slv_qtt is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 16 + signal slv_reg0 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + + signal slv_reg0_rst : std_logic; +begin + -- I/O Connections assignments + + awready <= axi_awready; + wready <= axi_wready; + bresp <= axi_bresp; + bvalid <= axi_bvalid; + arreadY <= axi_arready; + rdata <= axi_rdata; + rresp <= axi_rresp; + rvalid <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (bready = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and awvalid = '1' and wvalid = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= awaddr; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and wvalid = '1' and awvalid = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and wvalid and axi_awready and awvalid ; + + process (aclk) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(aclk) then + if aresetn = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + -- Reset + if (unsigned(slv_reg0) /= 0) then slv_reg0_rst <= ('1'); else slv_reg0_rst <= ('0'); end if; + if (slv_reg0_rst = '1') then slv_reg0 <= (others => '0'); end if; + if (slv_reg_wren = '1') then + case loc_addr is + when b"0000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"0111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1000" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1001" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1010" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1011" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1100" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1101" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1110" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"1111" => + for byte_index in 0 to (DATA_WIDTH/8-1) loop + if ( wstrb(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= wdata(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and awvalid = '1' and axi_wready = '1' and wvalid = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (bready = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and arvalid = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= araddr; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and arvalid = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and rready = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and arvalid and (not axi_rvalid) ; + -- 4 : TAVG_LOW_REG (r). + -- 5 : TAVG_HIGH_REG(r). + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, axi_araddr) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"0000" => + reg_data_out <= slv_reg0; + when b"0001" => + reg_data_out <= slv_reg1; + when b"0010" => + reg_data_out <= slv_reg2; + when b"0011" => + reg_data_out <= slv_reg3; + when b"0100" => + reg_data_out <= slv_reg4; + when b"0101" => + reg_data_out <= PROC_DT; + when b"0110" => + reg_data_out <= PROC_QTY; + when b"0111" => + reg_data_out <= TAG0_QTY; + when b"1000" => + reg_data_out <= TAG1_QTY; + when b"1001" => + reg_data_out <= TAG2_QTY; + when b"1010" => + reg_data_out <= TAG3_QTY; + when b"1011" => + reg_data_out <= SMP_QTY; + when b"1100" => + reg_data_out <= ARM_QTY; + when b"1101" => + reg_data_out <= THR_INH; + when b"1110" => + reg_data_out <= QTT_STATUS; + when b"1111" => + reg_data_out <= QTT_DEBUG; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( aclk ) is + begin + if (rising_edge (aclk)) then + if ( aresetn = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + +CTRL <= slv_reg0( 7 downto 0); +CFG <= slv_reg1(10 downto 0); +DMA_CFG <= slv_reg2(23 downto 0); +AXI_DT1 <= slv_reg3(31 downto 0); + +end rtl; diff --git a/firmware/ip/qick_time_tagger/src/qick_time_tagger.sv b/firmware/ip/qick_time_tagger/src/qick_time_tagger.sv new file mode 100644 index 0000000..c09b0e2 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/qick_time_tagger.sv @@ -0,0 +1,362 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024-6-21 +// Version : 1 +/////////////////////////////////////////////////////////////////////////////// + +module qick_time_tagger # ( + parameter ADC_QTY = 4 , // Number of ADC Inputs + parameter CMP_SLOPE = 1 , // Compare with SLOPE + parameter CMP_INTER = 4 , // Max Number of Interpolation bits + parameter ARM_STORE = 1 , // Store NUmber of Triggers on each ARM + parameter SMP_STORE = 1 , // Store Sample Values + parameter TAG_FIFO_AW = 19 , // Size of TAG FIFO Memory + parameter ARM_FIFO_AW = 10 , // Size of ARM FIFO Memory + parameter SMP_FIFO_AW = 10 , // Size of SAMPLE FIFO Memory + parameter SMP_DW = 19 , // Samples WIDTH + parameter SMP_CK = 8 , // Samples per Clock + parameter DEBUG = 1 +) ( +// Core and AXI CLK & RST + input wire ps_clk_i , + input wire ps_rst_ni , + input wire c_clk_i , + input wire c_rst_ni , + input wire adc_clk_i , + input wire adc_rst_ni , + input wire qtt_pop_req_i , + input wire qtt_rst_req_i , // reset from qtt_cmd, on ADC clock + output wire qtt_rst_ack_o , + input wire cfg_invert_i , + input wire cfg_filter_i , + input wire cfg_slope_i , + input wire [2:0] cfg_inter_i , + input wire [4:0] cfg_smp_wr_qty_i , + input wire arm_i , // Arm Trigger (ONE works) + input wire [SMP_DW-1:0] cmp_th_i , // Threhold Data + input wire [7:0] cmp_inh_i , // Inhibit Clock Pulses + input wire [SMP_CK*SMP_DW-1:0] adc_dt_i[ADC_QTY] , +///// DATA DMA + input wire dma_req_i , + input wire [2:0] dma_mem_sel_i , + input wire [19:0] dma_len_i , + output wire dma_ack_o , + input wire dma_m_axis_tready_i , + output wire dma_m_axis_tvalid_o , + output wire [31:0] dma_m_axis_tdata_o , + output wire dma_m_axis_tlast_o , +///// DATA PROC + output wire [31:0] tag_dt_o , + output wire tag_vld_o , + output wire trig_o , + output wire cmp_o , + +///// DATA OUT + output wire [TAG_FIFO_AW-1:0] proc_qty_o , + output wire [TAG_FIFO_AW-1:0] dma_qty_o [4] , + output wire [SMP_FIFO_AW-1:0] smp_qty_o , + output wire [ARM_FIFO_AW-1:0] arm_qty_o , +///// STATUS & DEBUG + output wire [31:0] qtt_debug_o , + output wire [23:0] qtt_reg_status_o , + output wire [31:0] qtt_reg_debug_o + ); + +// Signal Declaration +////////////////////////////////////////////////////////////////////////// +wire [15:0] dma_ds; +wire [25:0] dma_reg_ds; + +wire [31:0] tag_fifo_dt, arm_fifo_dt, smp_fifo_dt; +wire tag_dma_pop_req, tag_dma_pop_ack ; +wire arm_dma_pop_req, arm_dma_pop_ack ; +wire smp_dma_pop_req, smp_dma_pop_ack ; + +wire [ADC_QTY-1:0] tag_vld_s ; +wire [31:0] tag_dt_s [ADC_QTY]; + +wire trig_event; +wire [TAG_FIFO_AW-1:0] dma_qty_s [4]; + + +// Synchronize Input Signals +////////////////////////////////////////////////////////////////////////// + +sync_reg # ( + .DW ( 1 ) +) sync_arm ( + .dt_i ( arm_i ), + .clk_i ( adc_clk_i ), + .rst_ni ( adc_rst_ni ), + .dt_o ( arm_s ) +); + +// Control State Machine +////////////////////////////////////////////////////////////////////////// +typedef enum { ST_RST, ST_IDLE, ST_ARMED } TYPE_TRIG_ST; +(* fsm_encoding = "one_hot" *) TYPE_TRIG_ST time_trig_st; +TYPE_TRIG_ST time_trig_st_nxt; + +always_ff @ (posedge adc_clk_i, negedge adc_rst_ni) begin + if ( !adc_rst_ni ) time_trig_st <= ST_IDLE; + else time_trig_st <= time_trig_st_nxt; +end + +reg inhibit, tag_gen_en, qtt_rst; +; +always_comb begin + time_trig_st_nxt = time_trig_st; + tag_gen_en = 1'b0; + qtt_rst = 1'b0; + case (time_trig_st) + ST_RST: begin + qtt_rst = 1'b1; + if ( !qtt_rst_req_i ) time_trig_st_nxt = ST_IDLE; + end + ST_IDLE: begin + if ( qtt_rst_req_i ) time_trig_st_nxt = ST_RST; + else if ( arm_s ) time_trig_st_nxt = ST_ARMED; + end + ST_ARMED: begin + tag_gen_en = 1'b1; + if (!arm_s) + time_trig_st_nxt = ST_IDLE; + end + endcase +end + +// Time Counter +////////////////////////////////////////////////////////////////////////// +reg [28:0] time_cnt; +always_ff @(posedge adc_clk_i) begin + if (!adc_rst_ni) time_cnt <= 0; + else + if (tag_gen_en) time_cnt <= time_cnt + 1'b1; + else time_cnt <= 0; +end + +assign tag_mem_sel = (dma_mem_sel_i[2] == 1'b0); +assign arm_mem_sel = (dma_mem_sel_i == 3'b100); +assign smp_mem_sel = (dma_mem_sel_i == 3'b101); + +assign tag_dma_pop_req = dma_pop_req & tag_mem_sel ; +assign arm_dma_pop_req = dma_pop_req & arm_mem_sel ; +assign smp_dma_pop_req = dma_pop_req & smp_mem_sel ; + +assign dma_pop_ack = tag_mem_sel & tag_dma_pop_ack | arm_mem_sel & arm_dma_pop_ack | smp_mem_sel & smp_dma_pop_ack ; + +reg [31:0] dma_fifo_dt ; +always_comb + case (dma_mem_sel_i) + 3'b000: dma_fifo_dt = tag_fifo_dt; // tag0_dt + 3'b001: dma_fifo_dt = tag_fifo_dt; // tag1_dt + 3'b010: dma_fifo_dt = tag_fifo_dt; // tag2_dt + 3'b011: dma_fifo_dt = tag_fifo_dt; // tag3_dt + 3'b100: dma_fifo_dt = arm_fifo_dt; + 3'b101: dma_fifo_dt = smp_fifo_dt; + default: dma_fifo_dt = tag_fifo_dt; + endcase + +// Instances +////////////////////////////////////////////////////////////////////////// +tag_gen #( + .ADC_QTY ( ADC_QTY ), + .CMP_SLOPE ( CMP_SLOPE ), + .CMP_INTER ( CMP_INTER ), + .SMP_DW ( SMP_DW ), + .SMP_CK ( SMP_CK ) +) TAG_GEN ( + .clk_i ( adc_clk_i ), + .rst_ni ( adc_rst_ni ), + .cfg_invert_i ( cfg_invert_i ), + .cfg_filter_i ( cfg_filter_i ), + .cfg_slope_i ( cfg_slope_i ), + .cfg_inter_i ( cfg_inter_i ), + .time_ck_i ( time_cnt ), + .cmp_th_i ( cmp_th_i ), + .cmp_inh_i ( cmp_inh_i ), + .en_i ( tag_gen_en ), + .adc_dt_i ( adc_dt_i ), + .trig_o ( trig_event ), + .cmp_o ( cmp_s ) , + .tag_vld_o ( tag_vld_s ), + .tag_dt_o ( tag_dt_s ) +); + +tag_mem # ( + .MEM_QTY ( ADC_QTY ), // Amount of Memories + .TAG_FIFO_AW ( TAG_FIFO_AW ), // Size of TAG FIFO Memory + .DEBUG ( DEBUG ) +) TAG_MEM ( + .dma_clk_i ( ps_clk_i ), + .dma_rst_ni ( ps_rst_ni ), + .c_clk_i ( c_clk_i ), + .c_rst_ni ( c_rst_ni ), + .adc_clk_i ( adc_clk_i ), + .adc_rst_ni ( adc_rst_ni ), + .qtt_pop_req_i ( qtt_pop_req_i ), + .qtt_pop_ack_o ( qtt_pop_ack ), + .qtt_rst_req_i ( qtt_rst_req_i ), + .qtt_rst_ack_o ( ), + .tag_wr_i ( tag_vld_s ), + .tag_dt_i ( tag_dt_s ), + .dma_qty_o ( dma_qty_o ), + .proc_qty_o ( proc_qty_o ), + .empty_o ( tag_empty_o ), + .full_o ( tag_full_o ), + .dma_sel_i ( dma_mem_sel_i[1:0]), + .dma_pop_i ( tag_dma_pop_req ), + .dma_pop_o ( tag_dma_pop_ack ), + .dma_dt_o ( tag_fifo_dt ), + .debug_do ( tag_debug_o ) +); + +dma_fifo_rd # ( + .MEM_AW ( 20 ), // Memory Address Width + .MEM_DW ( 32 ), // Memory Data Width + .DMA_DW ( 32 ) // DMA Data Width +) DMA ( + .clk_i ( ps_clk_i ), + .rst_ni ( ps_rst_ni ), + .dma_req_i ( dma_req_i ), + .dma_ack_o ( dma_ack_o ), + .dma_len_i ( dma_len_i ), + .pop_req_o ( dma_pop_req ), + .pop_ack_i ( dma_pop_ack ), + .fifo_dt_i ( dma_fifo_dt ), + .m_axis_tready_i ( dma_m_axis_tready_i ), + .m_axis_tdata_o ( dma_m_axis_tdata_o ), + .m_axis_tvalid_o ( dma_m_axis_tvalid_o ), + .m_axis_tlast_o ( dma_m_axis_tlast_o ), + .dma_do ( dma_ds ), + .dma_reg_do ( dma_reg_ds ) +); + +generate + if (SMP_STORE == 1 ) begin: SMP + smp_mem # ( + .SMP_DW ( SMP_DW ) , // Samples WIDTH + .SMP_CK ( SMP_CK ) , // Samples per Clock + .SMP_FIFO_AW ( SMP_FIFO_AW ) // Size of SAMPLES FIFO Memory + ) SMP_MEM ( + // Core and AXI CLK & RST + .dma_clk_i ( ps_clk_i ) , + .dma_rst_ni ( ps_rst_ni ) , + .adc_clk_i ( adc_clk_i ) , + .adc_rst_ni ( adc_rst_ni ) , + .qtt_rst_req_i ( qtt_rst_req_i ) , + .qtt_rst_ack_o ( ) , + .cfg_smp_wr_qty_i ( cfg_smp_wr_qty_i ) , + .tag_wr_i ( trig_event ) , + .adc_dt_i ( adc_dt_i[0] ) , + .dma_pop_i ( smp_dma_pop_req ) , + .dma_pop_o ( smp_dma_pop_ack ) , + .dma_dt_o ( smp_fifo_dt ) , + .dma_qty_o ( smp_qty_o ) , + .smp_empty_o ( smp_empty ) , + .smp_full_o ( smp_full ) , + .debug_do ( smp_debug ) + ); + end else begin + assign smp_dma_pop_ack = 0; + assign smp_fifo_dt = 0; + assign smp_qty_o = 0; + assign smp_empty = 1; + assign smp_full = 0; + assign smp_debug = 0; + end + + if (ARM_STORE ==1 ) begin: ARM + wire arm_t10; + reg arm_r; + // ARM signal + ////////////////////////////////////////////////////////////////////////// + always_ff @(posedge adc_clk_i) begin + if (!adc_rst_ni) arm_r <= 0; + else arm_r <= arm_s; + end + + assign arm_t10 = arm_r & !arm_s ; + + // Trig Counter + ////////////////////////////////////////////////////////////////////////// + reg [31:0] trig_cnt; + always_ff @(posedge adc_clk_i) begin + if ( !adc_rst_ni ) trig_cnt <= 0; + else if ( !tag_gen_en ) trig_cnt <= 0; + else if ( trig_event ) trig_cnt <= trig_cnt + 1'b1; + end + + TAG_FIFO_DC # ( + .FIFO_AW ( ARM_FIFO_AW ) + ) ARM_MEM ( + .dma_clk_i ( ps_clk_i ), + .dma_rst_ni ( ps_rst_ni ), + .adc_clk_i ( adc_clk_i ), + .adc_rst_ni ( adc_rst_ni ), + .flush_i ( qtt_rst_req_i ), + .flush_o ( ), + .adc_push_i ( arm_t10 ), + .adc_data_i ( trig_cnt ), + .dma_pop_i ( arm_dma_pop_req ), + .dma_pop_o ( arm_dma_pop_ack ), + .dma_qty_o ( arm_qty_o ), + .dma_dt_o ( arm_fifo_dt ), + .empty_o ( arm_empty ), + .full_o ( arm_full ), + .debug_do ( ) + ); + end else begin + assign arm_dma_pop_ack = 0; + assign arm_fifo_dt = 0; + assign arm_qty_o = 0; + assign arm_empty = 1; + assign arm_full = 0; + end +endgenerate + + +// STATUS +/////////////////////////////////////////////////////////////////////////////// +assign qtt_reg_status_o[7:0] = time_trig_st[7:0]; +assign qtt_reg_status_o[9:8] = dma_reg_ds[25:24]; +assign qtt_reg_status_o[23:10] = 0; + +// DEBUG +/////////////////////////////////////////////////////////////////////////////// + +assign qtt_debug_o[31:16] = dma_ds; +assign qtt_reg_debug_o[5:4] = 2'b00; +assign qtt_reg_debug_o[31:6] = dma_reg_ds; + + +/////////////////////////////////////////////////////////////////////////////// +// OUT SIGNALS +/////////////////////////////////////////////////////////////////////////////// +pulse_cdc tag_vld_sync ( + .clk_a_i ( ps_clk_i ) , + .rst_a_ni ( ps_rst_ni ) , + .pulse_a_i ( qtt_pop_ack ) , + .rdy_a_o ( ) , + .clk_b_i ( c_clk_i ) , + .rst_b_ni ( c_rst_ni ) , + .pulse_b_o ( tadg_vld ) +); + +reg [31:0] tag_dt_r; +always_ff @(posedge c_clk_i) begin + if ( !c_rst_ni ) tag_dt_r <= 0; + else if ( qtt_pop_ack ) tag_dt_r <= tag_fifo_dt; +end + +assign qtt_rst_ack_o = qtt_rst; + + +assign tag_dt_o = tag_dt_r; +assign tag_vld_o = tadg_vld; +assign trig_o = trig_event; +assign cmp_o = cmp_s; + +endmodule diff --git a/firmware/ip/qick_time_tagger/src/qtt_cmd.sv b/firmware/ip/qick_time_tagger/src/qtt_cmd.sv new file mode 100644 index 0000000..ef18466 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/qtt_cmd.sv @@ -0,0 +1,221 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_5_31 +/////////////////////////////////////////////////////////////////////////////// + + +module qtt_cmd ( + input wire clk_i , // ADC clock + input wire rst_ni , // reset on ADC clock + input wire c_clk_i , // tProc core clock + input wire c_rst_ni , // reset on tProc core clock + input wire ext_arm_i , // external arm signal (typ. on ADC clock) + input wire c_en_i , // command enable, from tProc core (core clock is assumed to be slower than ADC clock) + input wire [4:0] c_op_i , // command opcode, from tProc core + input wire [31:0] c_dt_i , // command data, from tProc core + input wire p_en_i , // command enable, from AXI registers + input wire [4:0] p_op_i , // command opcode, from AXI registers + input wire [31:0] p_dt_i , // command data, from AXI registers + output wire pop_req_o , // pop, to time tagger + output wire rst_req_o , // reset, to time tagger + input wire rst_ack_i , // reset acknowledge, from time tagger + output wire peek_o , // peek (data-valid), to tProc core + output wire qtt_arm_o , // arm signal, to time tagger and AXI register + output wire [15:0] qtt_cmp_th_o , // threshold, to time tagger and AXI register + output wire [7 :0] qtt_cmp_inh_o , // deadtime, to time tagger and AXI register + output wire [7 :0] cmd_cnt_do ); // command count, to AXI register + + +// Sincronization +/////////////////////////////////////////////////////////////////////////////// +wire p_en_r, p_en_r_t01; +wire ext_arm_r, ext_arm_t01, ext_arm_t10; +wire [4:0] p_op_r; +reg ext_arm_2r, p_en_2r; + +sync_reg # ( + .DW ( 7 ) +) sync_cmd ( + .dt_i ( {ext_arm_i, p_en_i, p_op_i} ) , + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .dt_o ( {ext_arm_r, p_en_r, p_op_r} ) ); + +reg c_en_r; +reg [4:0] c_op_r; +reg [31:0] c_dt_r; +wire cdc_ack; + +always_ff @(posedge c_clk_i) + if (!c_rst_ni) begin + c_en_r <= 0; + c_op_r <= 5'd0; + c_dt_r <= 32'd0; + end else begin + c_op_r <= c_op_i; + c_dt_r <= c_dt_i; + if (cdc_ack) begin + c_en_r <= 0; + end else if (c_en_i) begin + c_en_r <= c_en_i; + end + end +wire c_en_2r; +wire [4:0] c_op_2r; +wire [31:0] c_dt_2r; + +xpm_cdc_handshake #( + .DEST_EXT_HSK(0), // DECIMAL; 0=internal handshake, 1=external handshake + .DEST_SYNC_FF(2), // DECIMAL; range: 2-10 + .INIT_SYNC_FF(0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values + .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages + .SRC_SYNC_FF(2), // DECIMAL; range: 2-10 + .WIDTH(37) // DECIMAL; range: 1-1024 +) +xpm_cdc_handshake_core ( + .dest_out({c_op_2r, c_dt_2r}), // WIDTH-bit output: Input bus (src_in) synchronized to destination clock domain. + .dest_req(c_en_2r), // When DEST_EXT_HSK = 0, this signal asserts for one clock period when dest_out bus is valid. This output is registered. + .src_rcv(cdc_ack), // 1-bit output: Acknowledgement from destination logic that src_in has been received. + .dest_ack(), // 1-bit input: optional; required when DEST_EXT_HSK = 1 + .dest_clk(clk_i), // 1-bit input: Destination clock. + .src_clk(c_clk_i), // 1-bit input: Source clock. + .src_in({c_op_r, c_dt_r}), // WIDTH-bit input: Input bus that will be synchronized to the destination clock domain. + .src_send(c_en_r) // 1-bit input: Assertion of this signal allows the src_in bus to be synchronized to the destination clock domain. +); + +assign p_en_r_t01 = !p_en_2r & p_en_r; +assign ext_arm_t01 = !ext_arm_2r & ext_arm_r; +assign ext_arm_t10 = ext_arm_2r & !ext_arm_r; + +// COMMAND OPERATON +reg cmd_req; +reg [ 4:0] cmd_op; +reg [31:0] cmd_dt; +reg [ 3:0] p_cmd_cnt, c_cmd_cnt; + +always_ff @(posedge clk_i) + if (!rst_ni) begin + cmd_req <= 1'b0; + cmd_op <= 5'd0; + cmd_dt <= 0; + p_cmd_cnt <= 3'd0; + c_cmd_cnt <= 3'd0; + end else begin + p_en_2r <= p_en_r; + ext_arm_2r <= ext_arm_r; + // Python Command + if (p_en_r_t01) begin + cmd_req <= 1'b1; + cmd_op <= p_op_r ; + cmd_dt <= p_dt_i ; + p_cmd_cnt <= p_cmd_cnt + 1'b1; + // Processor Command + end else if (c_en_2r) begin + cmd_req <= 1'b1; + cmd_op <= c_op_2r ; + cmd_dt <= c_dt_2r ; + c_cmd_cnt <= c_cmd_cnt + 1'b1; + //External ARM + end else if (ext_arm_t01) begin + cmd_req <= 1'b1; + cmd_op <= 5'b00001 ; + cmd_dt <= 0 ; + c_cmd_cnt <= c_cmd_cnt + 1'b1; + //External DISARM + end else if (ext_arm_t10) begin + cmd_req <= 1'b1; + cmd_op <= 5'b00000 ; + cmd_dt <= 0 ; + c_cmd_cnt <= c_cmd_cnt + 1'b1; + + end else + if ( cmd_req ) cmd_req <= 1'b0; + end + +// Command Decoding +/////////////////////////////////////////////////////////////////////////////// + +assign ext_arm_t01 = !ext_arm_2r & ext_arm_r; +assign ext_arm_t10 = ext_arm_2r & !ext_arm_r; + +assign cmd_disarm = cmd_req & ( cmd_op==5'b00000 ); +assign cmd_arm = cmd_req & ( cmd_op==5'b00001 ); +assign cmd_pop = cmd_req & ( cmd_op==5'b00010 ); +assign cmd_peek = cmd_req & ( cmd_op==5'b00011 ); +assign cmd_set_th = cmd_req & ( cmd_op==5'b00100 ); +assign cmd_set_inh = cmd_req & ( cmd_op==5'b00101 ); + +assign cmd_reset = cmd_req & ( cmd_op==5'b00111 ); + + + +// Command Processing +/////////////////////////////////////////////////////////////////////////////// +reg qtt_arm, qtt_rst, qtt_pop; +reg[15:0] qtt_cmp_th; +reg[ 7:0] qtt_cmp_inh; +reg core_peek; + +always_ff @ (posedge clk_i, negedge rst_ni) begin + if ( !rst_ni ) begin + qtt_arm <= 0; + qtt_cmp_th <= 0; + qtt_cmp_inh <= 0; + qtt_rst <= 0; + qtt_pop <= 0; + core_peek <= 0; + + end + else if ( cmd_arm ) qtt_arm <= 1'b1; + else if ( cmd_disarm ) qtt_arm <= 1'b0; + else if ( cmd_reset ) qtt_rst <= 1'b1; + else if ( rst_ack_i ) qtt_rst <= 1'b0; + else if ( cmd_pop ) qtt_pop <= 1'b1; + else if ( qtt_pop ) qtt_pop <= 1'b0; + else if ( cmd_peek ) core_peek <= 1'b1; + else if ( core_peek ) core_peek <= 1'b0; + + else if ( cmd_set_th ) qtt_cmp_th <= cmd_dt[15:0]; + else if ( cmd_set_inh ) qtt_cmp_inh <= cmd_dt[7:0]; +end + +/* +pulse_cdc peek_sync ( + .clk_a_i ( clk_i ) , + .rst_a_ni ( rst_ni ) , + .pulse_a_i ( core_peek) , + .rdy_a_o ( ) , + .clk_b_i ( c_clk_i ) , + .rst_b_ni ( c_rst_ni ) , + .pulse_b_o ( peek_o ) +); +*/ + +sync_pulse # ( + .QUEUE_AW ( 8 ) , + .BLOCK ( 0 ) +) peek_sync ( + .a_clk_i ( clk_i ) , + .a_rst_ni ( rst_ni ) , + .a_pulse_i ( core_peek ) , + .b_clk_i ( c_clk_i ) , + .b_rst_ni ( c_rst_ni) , + .b_pulse_o ( peek_o ) , + .b_en_i ( 1'b1 ) , + .pulse_full ( ) ); + +// OUTPUTS +/////////////////////////////////////////////////////////////////////////////// +assign pop_req_o = qtt_pop ; +assign rst_req_o = qtt_rst; +assign qtt_arm_o = qtt_arm ; +assign qtt_cmp_th_o = qtt_cmp_th ; +assign qtt_cmp_inh_o = qtt_cmp_inh ; + +// DEBUG +/////////////////////////////////////////////////////////////////////////////// +assign cmd_cnt_do ={ c_cmd_cnt, p_cmd_cnt }; + +endmodule diff --git a/firmware/ip/qick_time_tagger/src/qtt_tag_calc.sv b/firmware/ip/qick_time_tagger/src/qtt_tag_calc.sv new file mode 100644 index 0000000..093cf8a --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/qtt_tag_calc.sv @@ -0,0 +1,259 @@ +module qtt_tag_calc # ( + parameter CMP_SLOPE = 1 , // Compare with SLOPE + parameter CMP_INTER = 1 , // Interpolate SAMPLES + parameter SMP_DW = 16 , //Sample Data width + parameter SMP_CK = 8 // Samples per Clock +) ( + input wire clk_i , + input wire rst_ni , + input wire arm_i , + input wire cfg_invert_i , + input wire cfg_filter_i , + input wire [2:0] cfg_inter_i , + input wire cfg_slope_i , + input wire [28:0] time_ck_i , + input wire [SMP_DW-1:0] cmp_th_i , + input wire [7:0] cmp_inh_i , // Inhibit Clock Pulses + input wire [SMP_CK*SMP_DW-1:0] dt_i , + output wire trig_o , + output wire cmp_o , + output wire tag_vld_o , + output wire [31:0] tag_dt_o , + output wire [7:0] debug_do +); + +// Signal Declaration +/////////////////////////////////////////////////////////////////////////////// +reg signed [SMP_DW-1:0] adc_smp [SMP_CK-1:0] ; +reg signed [SMP_DW-1:0] adc_prev_smp [SMP_CK-1:0]; +reg signed [SMP_DW-1:0] adc_prev_smp_0 ; +reg signed [SMP_DW-1:0] adc_2prev_smp [SMP_CK-1:0]; +reg signed [SMP_DW-1:0] adc_2prev_smp_0; +reg signed [SMP_DW:0] ftr_smp [SMP_CK-1:0]; +reg signed [SMP_DW:0] ftr_prev_smp [SMP_CK-1:0]; +reg signed [SMP_DW:0] cmp_smp [SMP_CK-1:0]; +reg signed [SMP_DW:0] cmp_prev_smp [SMP_CK-1:0]; + +reg [SMP_CK-1:0] cmp_s ; +wire [ 2:0] enc_s, enc_m1; +reg [28:0] time_ck_r, time_ck_2r; +wire [28:0] time_ck_s; +wire [ 2:0] time_adc_s; +wire [ 6:0] time_inter_s; +reg [28:0] trig_time_ck_r; +reg [ 2:0] trig_time_adc_r; +reg [CMP_INTER-1:0] trig_time_inter_r; +wire [CMP_INTER-1:0] thr_inter_smp; +wire x_inter_end; + +// Signed comparison values. +wire signed [SMP_DW:0] cmp_smp_s [SMP_CK-1:0]; +wire signed [SMP_DW:0] cmp_thr_s ; +wire [SMP_CK-1:0] cmp_flg ; +assign cmp_thr_s = {cmp_th_i, 1'b0}; + +// Control State Machine +////////////////////////////////////////////////////////////////////////// +typedef enum { ST_IDLE, ST_ARMED, ST_INTER, ST_INHIBIT } TYPE_TRIG_ST; +(* fsm_encoding = "one_hot" *) TYPE_TRIG_ST trig_cal_st; +TYPE_TRIG_ST trig_calc_st_nxt; + +always_ff @ (posedge clk_i, negedge rst_ni) begin + if ( !rst_ni ) trig_cal_st <= ST_IDLE; + else trig_cal_st <= trig_calc_st_nxt; +end + +reg inhibit; +always_comb begin + trig_calc_st_nxt = trig_cal_st; + inhibit = 1'b1; + case (trig_cal_st) + ST_IDLE: begin + if (arm_i) trig_calc_st_nxt = ST_ARMED; + end + ST_ARMED: begin + inhibit = 1'b0; + if (!arm_i) trig_calc_st_nxt = ST_IDLE; + else if (trigger_cmp_s) begin + if (|cfg_inter_i ) trig_calc_st_nxt = ST_INTER; + else trig_calc_st_nxt = ST_INHIBIT; + end + end + ST_INTER: begin + if (x_inter_end) trig_calc_st_nxt = ST_INHIBIT; // IF INHIBIT IS SHORTER, TAKES MORE TIME + end + ST_INHIBIT : begin + if (inhibit_end) trig_calc_st_nxt = ST_ARMED; + end + endcase +end + +// Inhibit Counter +////////////////////////////////////////////////////////////////////////// +reg [7:0] inhibit_cnt, inhibit_cnt_p1 ; +assign inhibit_cnt_p1 = inhibit_cnt + 1'b1; + +always_ff @(posedge clk_i) begin + if (!rst_ni) inhibit_cnt <= 0; + else + if (arm_i & inhibit) inhibit_cnt <= inhibit_cnt_p1; + else inhibit_cnt <= 0; +end + +assign inhibit_end = ( inhibit_cnt == cmp_inh_i ) ; + +assign trigger_cmp = !inhibit & trigger_cmp_s ; + + + + + +// Samples Processing +/////////////////////////////////////////////////////////////////////////////// + +// Store las Sample of current, for prev next. +always_ff @(posedge clk_i) begin + if ( !rst_ni ) begin + adc_prev_smp_0 <= 0; + adc_2prev_smp_0 <= 0; + time_ck_r <= 0; + time_ck_2r <= 0; + end else begin + adc_prev_smp_0 <= adc_smp[SMP_CK-1]; + adc_2prev_smp_0 <= adc_smp[SMP_CK-2]; + time_ck_r <= time_ck_i; + time_ck_2r <= time_ck_r; + end +end + + +genvar i; +generate + for (i=0; i cmp_thr_s); + always_ff @(posedge clk_i) cmp_s[i] = cmp_flg[i]; + end +endgenerate + + + +// Time Tag +/////////////////////////////////////////////////////////////////////////////// + +assign enc_zero = ~|enc_s ; +assign enc_m1 = enc_s - 1'b1 ; +assign time_ck_s = (cfg_inter_i & enc_zero) ? time_ck_2r : time_ck_r; +assign time_adc_s = cfg_inter_i ? enc_m1 : enc_s ; +assign time_inter_s = cfg_inter_i ? thr_inter_smp : 0 ; + +always_ff @(posedge clk_i) begin + if ( !rst_ni ) begin + trig_time_ck_r <= 0; + trig_time_adc_r <= 0; + trig_time_inter_r <= 0; + end else begin + if (trigger_cmp) begin + trig_time_ck_r <= time_ck_s; + trig_time_adc_r <= time_adc_s; + end + if (x_inter_end) + trig_time_inter_r <= time_inter_s; + end +end + + + +// INSTANCES +/////////////////////////////////////////////////////////////////////////////// +priority_encoder # ( + .DW ( 3 ) , + .OUT ("TNO_REG") +) ENCODER ( + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .one_hot_dt_i ( cmp_s ) , + .bin_dt_o ( enc_s ) , + .vld_o ( trigger_cmp_s ) +); + +generate + if (CMP_INTER > 0 ) begin: INTER + x_inter #( + .DW ( SMP_DW ) , + .IW ( CMP_INTER ) + ) INTERPOLATOR ( + .clk_i ( clk_i ) , + .rst_ni ( rst_ni ) , + .start_i ( trigger_cmp ) , + .cfg_inter_i( cfg_inter_i ) , + .thr_i ( cmp_th_i ) , + .curr_i ( ftr_smp[enc_s] ) , + .prev_i ( ftr_prev_smp[enc_s] ) , + .end_o ( x_inter_end ) , + .ready_o ( ) , + .x_int_o ( thr_inter_smp ) ); + end else begin + assign x_inter_end = trigger_cmp; + assign thr_inter_smp = 7'b0; + end +endgenerate + +// DEBUG +/////////////////////////////////////////////////////////////////////////////// +assign debug_do = 0; + +// OUT +/////////////////////////////////////////////////////////////////////////////// +wire[6:0] trig_time_inter_s; + +localparam zfp = 6-CMP_INTER; +assign trig_time_inter_s = {{ zfp {1'b0}}, trig_time_inter_r}; + +assign tag_dt_o = ( cfg_inter_i ) == 3'b000 ? { trig_time_ck_r[28:0], trig_time_adc_r } : // No Interpolation + ( cfg_inter_i ) == 3'b001 ? { trig_time_ck_r[27:0], trig_time_adc_r, trig_time_inter_s[0] } : // Interpolation of 1 bit + ( cfg_inter_i ) == 3'b010 ? { trig_time_ck_r[26:0], trig_time_adc_r, trig_time_inter_s[1:0] } : // Interpolation of 2 bit + ( cfg_inter_i ) == 3'b011 ? { trig_time_ck_r[25:0], trig_time_adc_r, trig_time_inter_s[2:0] } : // Interpolation of 3 bit + ( cfg_inter_i ) == 3'b100 ? { trig_time_ck_r[24:0], trig_time_adc_r, trig_time_inter_s[3:0] } : // Interpolation of 4 bit + ( cfg_inter_i ) == 3'b101 ? { trig_time_ck_r[23:0], trig_time_adc_r, trig_time_inter_s[4:0] } : // Interpolation of 5 bit + ( cfg_inter_i ) == 3'b110 ? { trig_time_ck_r[22:0], trig_time_adc_r, trig_time_inter_s[5:0] } : // Interpolation of 6 bit + { trig_time_ck_r[21:0], trig_time_adc_r, trig_time_inter_s[6:0] } ; // Interpolation of 7 bit +assign tag_vld_o = arm_i & x_inter_end; +assign trig_o = trigger_cmp; +assign cmp_o = trigger_cmp_s; + +endmodule diff --git a/firmware/ip/qick_time_tagger/src/smp_mem.sv b/firmware/ip/qick_time_tagger/src/smp_mem.sv new file mode 100644 index 0000000..ed1dafe --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/smp_mem.sv @@ -0,0 +1,349 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_5_31 +/////////////////////////////////////////////////////////////////////////////// + +module smp_mem # ( + parameter SMP_DW = 16 , // Samples WIDTH + parameter SMP_CK = 8 , // Samples per Clock + parameter SMP_FIFO_AW = 10 // Size of SAMPLES FIFO Memory +) ( +// Core and AXI CLK & RST + input wire dma_clk_i , + input wire dma_rst_ni , + input wire adc_clk_i , + input wire adc_rst_ni , + input wire qtt_rst_req_i , //flush_i + output wire qtt_rst_ack_o , //flush_o +// Configuration + input wire [4:0] cfg_smp_wr_qty_i , +///// ADC TRIG + input wire tag_wr_i , + input wire [SMP_CK*SMP_DW-1:0] adc_dt_i , +///// DATA DMA + input wire dma_pop_i , + output wire dma_pop_o , + output wire [31:0] dma_dt_o , + output wire [SMP_FIFO_AW-1:0] dma_qty_o , + output wire smp_empty_o , + output wire smp_full_o , +///// STATUS & DEBUG + output wire [7:0] debug_do +); + +////////////////////////////////////////////////////////////////////////// +// SMP STORE +////////////////////////////////////////////////////////////////////////// +wire [SMP_DW-1:0] smp_fifo_dt; + + reg [SMP_CK*SMP_DW-1:0] smp_wr_dt, smp_wr_dt_r, smp_wr_dt_2r, smp_wr_dt_3r ; + reg [4:0] smp_wr_cnt ; + wire[4:0] smp_wr_cnt_p1 ; + // Control State Machine + ////////////////////////////////////////////////////////////////////////// + typedef enum { ST_SMP_IDLE, ST_SMP_WR } TYPE_SMP_WR_ST; + (* fsm_encoding = "one_hot" *) TYPE_SMP_WR_ST smp_wr_st; + TYPE_SMP_WR_ST smp_wr_st_nxt; + + always_ff @ (posedge adc_clk_i, negedge adc_rst_ni) begin + if ( !adc_rst_ni ) smp_wr_st <= ST_SMP_IDLE; + else smp_wr_st <= smp_wr_st_nxt; + end + reg smp_wr; + always_comb begin + smp_wr_st_nxt = smp_wr_st; + smp_wr = 1'b0; + case (smp_wr_st) + ST_SMP_IDLE: begin + if (tag_wr_i) smp_wr_st_nxt = ST_SMP_WR; + end + ST_SMP_WR : begin + smp_wr = 1'b1; + if (smp_wr_end) smp_wr_st_nxt = ST_SMP_IDLE; + end + endcase + end + // Number of Samples to Store + ////////////////////////////////////////////////////////////////////////// + always_ff @(posedge adc_clk_i) begin + if (!adc_rst_ni) smp_wr_cnt <= 0; + else + if (smp_wr) smp_wr_cnt <= smp_wr_cnt_p1; + else smp_wr_cnt <= 0; + end + assign smp_wr_cnt_p1 = smp_wr_cnt + 1'b1; + assign smp_wr_end = ( smp_wr_cnt_p1 == cfg_smp_wr_qty_i ) ; + + always_ff @(posedge adc_clk_i) begin + if ( !adc_rst_ni) begin + smp_wr_dt <= 0; + smp_wr_dt_r <= 0; + end else begin + smp_wr_dt <= adc_dt_i; + smp_wr_dt_r <= smp_wr_dt; + smp_wr_dt_2r <= smp_wr_dt_r; + smp_wr_dt_3r <= smp_wr_dt_2r; + + end + end + SMP_FIFO_DC # ( + .SMP_CK ( SMP_CK ), // Number of Samples in adc_data (MAX 16) + .SMP_DW ( SMP_DW ), // Sample Data Width + .FIFO_AW ( SMP_FIFO_AW ) // Memory bit address Width + ) SMP_FIFO_DC ( + .adc_clk_i ( adc_clk_i ), + .adc_rst_ni ( adc_rst_ni ), + .dma_clk_i ( dma_clk_i ), + .dma_rst_ni ( dma_rst_ni ), + .flush_i ( qtt_rst_req_i ), + .flush_o ( qtt_rst_ack_o ), + .adc_push_i ( smp_wr ), + .adc_data_i ( smp_wr_dt_3r ), + .dma_pop_i ( dma_pop_i ), + .dma_pop_o ( dma_pop_o ), + .dma_qty_o ( dma_qty_o ), + .dma_empty_o ( smp_empty_o ), + .dt_o ( smp_fifo_dt ), + .full_o ( smp_full_o ), + .debug_do ( )); + + +// DEBUG +/////////////////////////////////////////////////////////////////////////////// +assign debug_do = 0; + + +// OUT +/////////////////////////////////////////////////////////////////////////////// +localparam sfp = 32-SMP_DW; +assign dma_dt_o = {{ sfp {smp_fifo_dt[SMP_DW-1]}}, smp_fifo_dt}; + +endmodule + +/////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////// + +module SMP_FIFO_DC # ( + parameter SMP_CK = 8 , // Number of Samples in adc_data (MAX 16) + parameter SMP_DW = 16 , // Sample Data Width + parameter FIFO_AW = 10 // Memory bit address Width +) ( + input wire adc_clk_i , + input wire adc_rst_ni , + input wire dma_clk_i , + input wire dma_rst_ni , + input wire flush_i , + output wire flush_o , + input wire adc_push_i , + input wire [SMP_CK*SMP_DW-1:0] adc_data_i , + input wire dma_pop_i , + output wire dma_pop_o , + output wire [FIFO_AW-1:0] dma_qty_o , + output wire dma_empty_o , + output wire [SMP_DW - 1:0] dt_o , + output wire full_o , + output wire [15:0] debug_do + ); + +/////////////////////////////////////////////////////////////////////////////// +// Signal Declaration + +// The WRITE_POINTER is on the Last Empty Value +// The READ_POINTER is on the Last Value + +reg [FIFO_AW-1:0] rd_dma_ptr , wr_ptr; +wire [FIFO_AW-1:0] rd_dma_ptr_p1, wr_ptr_p1 ; +reg [FIFO_AW-1:0] dma_qty; +wire [FIFO_AW-1:0] addr_b ; +wire dma_empty, dma_full; +wire [SMP_DW - 1:0] data_s, mem_dt; +wire do_dma_pop; +reg do_dma_pop_r ; +wire [SMP_CK*SMP_DW-1:0] wr_smp_data ; +reg [SMP_CK*SMP_DW-1:0] wr_dt_r ; +wire [SMP_DW-1:0] wr_dt ; +wire [SMP_DW-1:0] wr_dt1, wr_dt2, wr_dt3 ; +wire [3:0] wr_cnt_p1 ; +reg [3:0] wr_cnt ; +reg wr_push; +reg wr_smp_pop, wr_smp_push; + +/////////////////////////////////////////////////////////////////////////////// +// WRITE SAMPLE FIFO +/////////////////////////////////////////////////////////////////////////////// +FIFO_DC # ( + .FIFO_DW ( SMP_CK*SMP_DW ), + .FIFO_AW ( 8 ) +) WR_SMP_FIFO ( + .wr_clk_i ( adc_clk_i ), + .wr_rst_ni ( adc_rst_ni ), + .wr_en_i ( 1'b1 ), + .push_i ( adc_push_i ), + .data_i ( adc_data_i ), + .rd_clk_i ( dma_clk_i ), + .rd_rst_ni ( dma_rst_ni ), + .rd_en_i ( 1'b1 ), + .pop_i ( wr_smp_pop ), + .data_o ( wr_smp_data ), + .flush_i ( flush_i ), + .async_empty_o ( wr_smp_empty), + .async_full_o ( wr_smp_full ) +); + + + +/////////////////////////////////////////////////////////////////////////////// +// WRITE Control state +typedef enum { WR_IDLE, WR_PUSH_DT, WR_POP_DT } TYPE_WR_ST ; +(* fsm_encoding = "sequential" *) TYPE_WR_ST smp_wr_st; +TYPE_WR_ST smp_wr_st_nxt; + +always_ff @ (posedge dma_clk_i) begin + if ( !dma_rst_ni ) smp_wr_st <= WR_IDLE; + else smp_wr_st <= smp_wr_st_nxt; +end + +always_comb begin + smp_wr_st_nxt = smp_wr_st; // Default Current + wr_smp_pop = 1'b0; + wr_smp_push = 1'b0; + case (smp_wr_st) + WR_IDLE : begin + if ( !wr_smp_empty ) + smp_wr_st_nxt = WR_POP_DT; + end + WR_POP_DT : begin + wr_smp_pop = 1'b1; + smp_wr_st_nxt = WR_PUSH_DT; + end + WR_PUSH_DT : begin + wr_smp_push = 1'b1; + if ( wr_last_dt | flush_i ) begin + wr_smp_push = 1'b0; + smp_wr_st_nxt = WR_IDLE; + end + end + endcase +end + +assign wr_cnt_p1 = wr_cnt + 1'b1; +assign wr_last_dt = (wr_cnt_p1 == SMP_CK) ; + + +always_ff @(posedge dma_clk_i, negedge dma_rst_ni) begin + if (!dma_rst_ni ) begin + wr_push <= 1'b0; + wr_dt_r <= 0; + wr_cnt <= 0; + end else begin + // Register DT + if ( wr_smp_pop ) wr_dt_r <= wr_smp_data; + // Increment Counter + if ( wr_push ) wr_cnt <= wr_cnt_p1; + else wr_cnt <= 0; + // Push to OUT FIFO + if ( flush_i ) wr_push <= 1'b0; + else if ( wr_smp_push ) wr_push <= 1'b1; + else wr_push <= 1'b0; + end +end + +assign wr_dt = wr_dt_r[SMP_DW*wr_cnt +: SMP_DW]; + + + +//wire flush_dma; +/* +pulse_cdc flush_sync ( + .clk_a_i ( adc_clk_i ) , + .rst_a_ni ( adc_rst_ni ) , + .pulse_a_i ( flush_i ) , + .rdy_a_o ( ) , + .clk_b_i ( dma_clk_i ) , + .rst_b_ni ( dma_rst_ni ) , + .pulse_b_o ( flush_dma ) +); +*/ +/* +sync_pulse # ( + .QUEUE_AW ( 8 ) , + .BLOCK ( 0 ) +) flush_sync ( + .a_clk_i ( adc_clk_i ) , + .a_rst_ni ( adc_rst_ni ) , + .a_pulse_i ( flush_i ) , + .b_clk_i ( dma_clk_i ) , + .b_rst_ni ( dma_rst_ni ) , + .b_pulse_o ( flush_dma ) , + .b_en_i ( 1'b1 ) , + .pulse_full ( ) ); +*/ + +/////////////////////////////////////////////////////////////////////////////// +// READ +/////////////////////////////////////////////////////////////////////////////// +assign do_dma_pop = (dma_pop_i & !dma_empty ) | (wr_push & dma_full) ; // POP IF FULL +assign dma_empty = (rd_dma_ptr == wr_ptr) ; +assign dma_full = (rd_dma_ptr == wr_ptr_p1) ; + +// DMA Data QTY +always_ff @(posedge dma_clk_i) begin + if ( !dma_rst_ni | flush_i ) dma_qty <= 0; + else if ( wr_push & !do_dma_pop ) dma_qty <= dma_qty + 1'b1 ; + else if ( !wr_push & do_dma_pop ) dma_qty <= dma_qty - 1'b1 ; +end + + +/////////////////////////////////////////////////////////////////////////////// +// POINTERS +/////////////////////////////////////////////////////////////////////////////// +assign wr_ptr_p1 = wr_ptr + 1'b1 ; +assign rd_dma_ptr_p1 = rd_dma_ptr + 1'b1 ; + +always_ff @(posedge dma_clk_i, negedge dma_rst_ni) begin + if (!dma_rst_ni) begin + wr_ptr <= 0; + rd_dma_ptr <= 0; + end else if (flush_i) begin + wr_ptr <= 0; + rd_dma_ptr <= 0; + end else begin + if ( wr_push ) wr_ptr <= wr_ptr_p1; + if ( do_dma_pop ) rd_dma_ptr <= rd_dma_ptr_p1; + end +end + +BRAM_SC # ( + .MEM_AW ( FIFO_AW ) , + .MEM_DW ( SMP_DW ) +) SMP_FIFO ( + .clk_i ( dma_clk_i ), + .we_a_i ( wr_push ), + .addr_a_i ( wr_ptr ), + .dt_a_i ( wr_dt ), + .addr_b_i ( rd_dma_ptr ), + .dt_b_o ( mem_dt )); + +// OUT +/////////////////////////////////////////////////////////////////////////////// + +always_ff @(posedge dma_clk_i) begin + if (!dma_rst_ni) begin + do_dma_pop_r <= 0; + end else begin + do_dma_pop_r <= do_dma_pop; + end +end + +assign flush_o = wr_smp_empty & wr_smp_full ; +assign full_o = dma_full; + +assign dma_qty_o = dma_qty; +assign dma_empty_o = dma_empty; // While RESETTING, Shows EMPTY +assign dma_pop_o = do_dma_pop_r; +assign dt_o = mem_dt; + +endmodule diff --git a/firmware/ip/qick_time_tagger/src/tag_gen.sv b/firmware/ip/qick_time_tagger/src/tag_gen.sv new file mode 100644 index 0000000..62f72e3 --- /dev/null +++ b/firmware/ip/qick_time_tagger/src/tag_gen.sv @@ -0,0 +1,70 @@ +/////////////////////////////////////////////////////////////////////////////// +// FERMI RESEARCH LAB +/////////////////////////////////////////////////////////////////////////////// +// Author : Martin Di Federico +// Date : 2024_5_31 +/////////////////////////////////////////////////////////////////////////////// + +module tag_gen # ( + parameter ADC_QTY = 1 , // Number of ADC Inputs + parameter CMP_SLOPE = 1 , // Compare with SLOPE + parameter CMP_INTER = 1 , // Interpolate SAMPLES + parameter SMP_DW = 16 , //Sample Data width + parameter SMP_CK = 8 // Samples per Clock +) ( + input wire clk_i , + input wire rst_ni , + input wire cfg_invert_i , + input wire cfg_filter_i , + input wire [2:0] cfg_inter_i , + input wire cfg_slope_i , + input wire [28:0] time_ck_i , + input wire [SMP_DW-1:0] cmp_th_i , + input wire [7:0] cmp_inh_i , // Inhibit Clock Pulses + input wire en_i , + input wire [SMP_CK*SMP_DW-1:0] adc_dt_i [ADC_QTY], + output wire trig_o , + output wire cmp_o , + output wire [ADC_QTY-1:0] tag_vld_o , + output wire [31:0] tag_dt_o [ADC_QTY] +); + +// Signal Declaration +////////////////////////////////////////////////////////////////////////// +wire [ADC_QTY-1:0] trig_s, cmp_s ; + +genvar ind; +generate + for (ind=0; ind Last Empty Value +// READ_POINTER > Last Value + +assign wr_ptr_p1 = wr_ptr + 1'b1 ; +assign rd_ptr_p1 = rd_ptr + 1'b1 ; + +always_ff @(posedge dma_clk_i, negedge dma_rst_ni) begin + if (!dma_rst_ni) begin + wr_ptr <= 0; + rd_ptr <= 0; + end else if (flush_i) begin + wr_ptr <= 0; + rd_ptr <= 0; + end else begin + if ( do_push ) wr_ptr <= wr_ptr_p1; + if ( do_pop ) rd_ptr <= rd_ptr_p1; + end +end + +assign tag_empty = (rd_ptr == wr_ptr) ; +assign tag_full = (rd_ptr == wr_ptr_p1) ; + +//wire flush_dma; +/* +pulse_cdc flush_sync ( + .clk_a_i ( adc_clk_i ) , + .rst_a_ni ( adc_rst_ni ) , + .pulse_a_i ( flush_i ) , + .rdy_a_o ( ) , + .clk_b_i ( dma_clk_i ) , + .rst_b_ni ( dma_rst_ni ) , + .pulse_b_o ( flush_dma ) +); +*/ +/* +sync_pulse # ( + .QUEUE_AW ( 8 ) , + .BLOCK ( 0 ) +) flush_sync ( + .a_clk_i ( adc_clk_i ) , + .a_rst_ni ( adc_rst_ni ) , + .a_pulse_i ( flush_i ) , + .b_clk_i ( dma_clk_i ) , + .b_rst_ni ( dma_rst_ni ) , + .b_pulse_o ( flush_dma ) , + .b_en_i ( 1'b1 ) , + .pulse_full ( ) ); +*/ + +// TAG QTY +always_ff @(posedge dma_clk_i) begin + if ( !dma_rst_ni | flush_i ) tag_qty <= 0; + else if ( do_push & !do_pop ) tag_qty <= tag_qty + 1'b1 ; + else if ( !do_push & do_pop ) tag_qty <= tag_qty - 1'b1 ; +end + + +BRAM_SC # ( + .MEM_DW ( 32 ) , + .MEM_AW ( FIFO_AW ) +) FIFO_TAG ( + .clk_i ( dma_clk_i ), + .we_a_i ( do_push ), + .addr_a_i ( wr_ptr ), + .dt_a_i ( data_s ), + .addr_b_i ( rd_ptr ), + .dt_b_o ( mem_dt )); + +// DEBUG +/////////////////////////////////////////////////////////////////////////////// +assign debug_do[0] = tag_full ; +assign debug_do[1] = tag_empty; +assign debug_do[2] = push_empty; +assign debug_do[3] = do_push; +assign debug_do[4] = dma_pop_i ; +assign debug_do[5] = do_pop ; +assign debug_do[6] = flush_i; +assign debug_do[7] = flush_o; + +// OUT +/////////////////////////////////////////////////////////////////////////////// + +always_ff @(posedge dma_clk_i) begin + if (!dma_rst_ni) begin + do_pop_r <= 0; + end else begin + do_pop_r <= do_pop; + end +end + +assign flush_o = push_empty & push_full ; +assign full_o = tag_full ; +assign empty_o = tag_empty ; + +assign dma_qty_o = tag_qty; +assign dma_pop_o = do_pop_r; +assign dma_dt_o = mem_dt; + +endmodule + +module TAG_FIFO_TC # ( + parameter TAG_DW = 32 , + parameter FIFO_AW = 18 +) ( + input wire tag_clk_i , + input wire tag_rst_ni , + input wire c_clk_i , + input wire c_rst_ni , + input wire dma_clk_i , + input wire dma_rst_ni , + input wire flush_i , + output wire flush_o , + input wire tag_push_i , + input wire [TAG_DW - 1:0] tag_data_i , + input wire tag_pop_i , + output wire c_pop_o , + output wire [FIFO_AW-1:0] c_qty_o , + output wire c_empty_o , + input wire dma_pop_i , + output wire dma_pop_o , + output wire [FIFO_AW-1:0] dma_qty_o , + output wire dma_empty_o , + output wire [TAG_DW - 1:0] dt_o , + output wire full_o , + output wire [15:0] debug_do ); + + +// The WRITE_POINTER is on the Last Empty Value +// The READ_POINTER is on the Last Value + +wire [FIFO_AW-1:0] wr_ptr_p1 ; +reg [FIFO_AW-1:0] rd_dma_ptr, rd_proc_ptr, wr_ptr; +wire [FIFO_AW-1:0] addr_b ; +wire [TAG_DW-1:0] data_s, mem_dt; +reg [FIFO_AW-1:0] dma_qty, proc_qty; +wire dma_full, proc_full; +wire dma_empty, proc_empty ; +wire do_dma_pop, do_proc_pop; +reg do_dma_pop_r, do_proc_pop_r ; + + +/////////////////////////////////////////////////////////////////////////////// +// WRITE +/////////////////////////////////////////////////////////////////////////////// +reg do_push; + +FIFO_DC # ( + .FIFO_DW ( 32 ), + .FIFO_AW ( 10 ) +) FIFO_PUSH ( + .wr_clk_i ( tag_clk_i ), + .wr_rst_ni ( tag_rst_ni ), + .wr_en_i ( 1'b1 ), + .push_i ( tag_push_i ), + .data_i ( tag_data_i ), + .rd_clk_i ( dma_clk_i ), + .rd_rst_ni ( dma_rst_ni ), + .rd_en_i ( 1'b1 ), + .pop_i ( do_push ), + .data_o ( data_s ), + .flush_i ( flush_i ), + .async_empty_o ( push_empty ), + .async_full_o ( push_full ) +); + +always_ff @(posedge dma_clk_i, negedge dma_rst_ni) begin + if (!dma_rst_ni ) begin + do_push <= 1'b0; + end else begin + if ( flush_i ) do_push <= 1'b0; + else if ( !push_empty & !do_push ) do_push <= 1'b1; + else if ( do_push ) do_push <= 1'b0; + end +end + +/////////////////////////////////////////////////////////////////////////////// +// POINTERS +/////////////////////////////////////////////////////////////////////////////// +assign wr_ptr_p1 = wr_ptr + 1'b1 ; + +always_ff @(posedge dma_clk_i, negedge dma_rst_ni) begin + if (!dma_rst_ni) begin + wr_ptr <= 0; + rd_dma_ptr <= 0; + rd_proc_ptr <= 0; + end else if (flush_i) begin + wr_ptr <= 0; + rd_dma_ptr <= 0; + rd_proc_ptr <= 0; + end else begin + if ( do_push ) wr_ptr <= wr_ptr_p1; + if ( do_proc_pop ) rd_proc_ptr <= rd_proc_ptr + 1'b1 ; + if ( do_dma_pop ) rd_dma_ptr <= rd_dma_ptr + 1'b1 ; + end +end + +//wire flush_dma; +/* +pulse_cdc flush_sync ( + .clk_a_i ( tag_clk_i ) , + .rst_a_ni ( tag_rst_ni ) , + .pulse_a_i ( flush_i ) , + .rdy_a_o ( ) , + .clk_b_i ( dma_clk_i ) , + .rst_b_ni ( dma_rst_ni ) , + .pulse_b_o ( flush_dma ) +); +*/ +/* +sync_pulse # ( + .QUEUE_AW ( 8 ) , + .BLOCK ( 0 ) +) flush_sync ( + .a_clk_i ( tag_clk_i ) , + .a_rst_ni ( tag_rst_ni ) , + .a_pulse_i ( flush_i ) , + .b_clk_i ( dma_clk_i ) , + .b_rst_ni ( dma_rst_ni ) , + .b_pulse_o ( flush_dma ) , + .b_en_i ( 1'b1 ) , + .pulse_full ( ) ); +*/ + +/////////////////////////////////////////////////////////////////////////////// +// READ (tProc has Priority) +/////////////////////////////////////////////////////////////////////////////// +assign do_dma_pop = (dma_pop_i & !dma_empty & !do_proc_pop) | (do_push & dma_full) ; // POP IF FULL +assign dma_empty = (rd_dma_ptr == wr_ptr) ; +assign dma_full = (rd_dma_ptr == wr_ptr_p1) ; +// DMA Data QTY +always_ff @(posedge dma_clk_i) begin + if ( !dma_rst_ni | flush_i ) dma_qty <= 0; + else if ( do_push & !do_dma_pop ) dma_qty <= dma_qty + 1'b1 ; + else if ( !do_push & do_dma_pop ) dma_qty <= dma_qty - 1'b1 ; +end + +sync_pulse # ( + .QUEUE_AW ( 8 ) , + .BLOCK ( 0 ) +) sync_p_i ( + .a_clk_i ( tag_clk_i ) , + .a_rst_ni ( tag_rst_ni ) , + .a_pulse_i ( tag_pop_i ) , + .b_clk_i ( dma_clk_i ) , + .b_rst_ni ( dma_rst_ni) , + .b_pulse_o ( c_pop_s ) , + .b_en_i ( 1'b1 ) , + .pulse_full ( ) ); + +assign do_proc_pop = ( c_pop_s & !proc_empty) | (do_push & proc_full); // POP IF FULL +assign proc_empty = ( rd_proc_ptr == wr_ptr) ; +assign proc_full = ( rd_proc_ptr == wr_ptr_p1) ; +// PROC_RD Data QTY +always_ff @(posedge dma_clk_i) begin + if ( !dma_rst_ni | flush_i ) proc_qty <= 0; + else if ( do_push & !do_proc_pop ) proc_qty <= proc_qty + 1'b1 ; + else if ( !do_push & do_proc_pop ) proc_qty <= proc_qty - 1'b1 ; +end + + +assign addr_b = do_proc_pop ? rd_proc_ptr : rd_dma_ptr; + +BRAM_SC # ( + .MEM_AW ( FIFO_AW ) , + .MEM_DW ( TAG_DW ) +) FIFO_TAG ( + .clk_i ( dma_clk_i ), + .we_a_i ( do_push ), + .addr_a_i ( wr_ptr ), + .dt_a_i ( data_s ), + .addr_b_i ( addr_b ), + .dt_b_o ( mem_dt ) +); + +// OUT +/////////////////////////////////////////////////////////////////////////////// + +always_ff @(posedge dma_clk_i) begin + if (!dma_rst_ni) begin + do_proc_pop_r <= 0; + do_dma_pop_r <= 0; + end else begin + do_proc_pop_r <= do_proc_pop; + do_dma_pop_r <= do_dma_pop; + end +end + +// DEBUG +/////////////////////////////////////////////////////////////////////////////// +assign debug_do[0] = dma_full ; +assign debug_do[1] = dma_empty; +assign debug_do[2] = proc_full; +assign debug_do[3] = proc_empty; +assign debug_do[4] = do_push; +assign debug_do[5] = dma_pop_i ; +assign debug_do[6] = do_dma_pop ; +assign debug_do[7] = dma_pop_o; +assign debug_do[8] = tag_pop_i; +assign debug_do[9] = do_proc_pop; +assign debug_do[10] = c_pop_o; +assign debug_do[11] = flush_i; +assign debug_do[12] = flush_o; +assign debug_do[13] = full_o; +assign debug_do[15:14] = 0; + + +// OUT +/////////////////////////////////////////////////////////////////////////////// + +assign flush_o = push_empty & push_full ; +assign full_o = proc_full | dma_full; + +assign c_qty_o = proc_qty; +assign c_empty_o = proc_empty ; // While RESETTING, Shows EMPTY +assign c_pop_o = do_proc_pop_r; + +assign dma_qty_o = dma_qty; +assign dma_empty_o = dma_empty; // While RESETTING, Shows EMPTY +assign dma_pop_o = do_dma_pop_r; +assign dt_o = mem_dt; + +endmodule diff --git a/firmware/ip/qick_time_tagger/xgui/axi_qick_time_tagger_v1_0.tcl b/firmware/ip/qick_time_tagger/xgui/axi_qick_time_tagger_v1_0.tcl new file mode 100644 index 0000000..c083cb1 --- /dev/null +++ b/firmware/ip/qick_time_tagger/xgui/axi_qick_time_tagger_v1_0.tcl @@ -0,0 +1,173 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + #Adding Group + set TAG_FIFO [ipgui::add_group $IPINST -name "TAG FIFO" -parent ${Page_0}] + ipgui::add_param $IPINST -name "TAG_FIFO_AW" -parent ${TAG_FIFO} + + #Adding Group + set Threshold_Comparison [ipgui::add_group $IPINST -name "Threshold Comparison" -parent ${Page_0}] + ipgui::add_param $IPINST -name "CMP_SLOPE" -parent ${Threshold_Comparison} -widget checkBox + ipgui::add_param $IPINST -name "CMP_INTER" -parent ${Threshold_Comparison} + + #Adding Group + set TAG_FIFO_Read_Sources [ipgui::add_group $IPINST -name "TAG FIFO Read Sources" -parent ${Page_0}] + ipgui::add_param $IPINST -name "DMA_RD" -parent ${TAG_FIFO_Read_Sources} -widget checkBox + ipgui::add_param $IPINST -name "PROC_RD" -parent ${TAG_FIFO_Read_Sources} -widget checkBox + + #Adding Group + set Samples_Options [ipgui::add_group $IPINST -name "Samples Options" -parent ${Page_0}] + ipgui::add_param $IPINST -name "SMP_STORE" -parent ${Samples_Options} -widget checkBox + ipgui::add_param $IPINST -name "SMP_FIFO_AW" -parent ${Samples_Options} + + #Adding Group + set Debug [ipgui::add_group $IPINST -name "Debug" -parent ${Page_0}] + ipgui::add_param $IPINST -name "DEBUG" -parent ${Debug} -widget checkBox + + + +} + +proc update_PARAM_VALUE.CMP_INTER { PARAM_VALUE.CMP_INTER } { + # Procedure called to update CMP_INTER when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CMP_INTER { PARAM_VALUE.CMP_INTER } { + # Procedure called to validate CMP_INTER + return true +} + +proc update_PARAM_VALUE.CMP_SLOPE { PARAM_VALUE.CMP_SLOPE } { + # Procedure called to update CMP_SLOPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CMP_SLOPE { PARAM_VALUE.CMP_SLOPE } { + # Procedure called to validate CMP_SLOPE + return true +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + +proc update_PARAM_VALUE.DMA_RD { PARAM_VALUE.DMA_RD } { + # Procedure called to update DMA_RD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_RD { PARAM_VALUE.DMA_RD } { + # Procedure called to validate DMA_RD + return true +} + +proc update_PARAM_VALUE.PROC_RD { PARAM_VALUE.PROC_RD } { + # Procedure called to update PROC_RD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PROC_RD { PARAM_VALUE.PROC_RD } { + # Procedure called to validate PROC_RD + return true +} + +proc update_PARAM_VALUE.SMP_CK { PARAM_VALUE.SMP_CK } { + # Procedure called to update SMP_CK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SMP_CK { PARAM_VALUE.SMP_CK } { + # Procedure called to validate SMP_CK + return true +} + +proc update_PARAM_VALUE.SMP_DW { PARAM_VALUE.SMP_DW } { + # Procedure called to update SMP_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SMP_DW { PARAM_VALUE.SMP_DW } { + # Procedure called to validate SMP_DW + return true +} + +proc update_PARAM_VALUE.SMP_FIFO_AW { PARAM_VALUE.SMP_FIFO_AW } { + # Procedure called to update SMP_FIFO_AW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SMP_FIFO_AW { PARAM_VALUE.SMP_FIFO_AW } { + # Procedure called to validate SMP_FIFO_AW + return true +} + +proc update_PARAM_VALUE.SMP_STORE { PARAM_VALUE.SMP_STORE } { + # Procedure called to update SMP_STORE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SMP_STORE { PARAM_VALUE.SMP_STORE } { + # Procedure called to validate SMP_STORE + return true +} + +proc update_PARAM_VALUE.TAG_FIFO_AW { PARAM_VALUE.TAG_FIFO_AW } { + # Procedure called to update TAG_FIFO_AW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TAG_FIFO_AW { PARAM_VALUE.TAG_FIFO_AW } { + # Procedure called to validate TAG_FIFO_AW + return true +} + + +proc update_MODELPARAM_VALUE.DMA_RD { MODELPARAM_VALUE.DMA_RD PARAM_VALUE.DMA_RD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_RD}] ${MODELPARAM_VALUE.DMA_RD} +} + +proc update_MODELPARAM_VALUE.PROC_RD { MODELPARAM_VALUE.PROC_RD PARAM_VALUE.PROC_RD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PROC_RD}] ${MODELPARAM_VALUE.PROC_RD} +} + +proc update_MODELPARAM_VALUE.CMP_SLOPE { MODELPARAM_VALUE.CMP_SLOPE PARAM_VALUE.CMP_SLOPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CMP_SLOPE}] ${MODELPARAM_VALUE.CMP_SLOPE} +} + +proc update_MODELPARAM_VALUE.CMP_INTER { MODELPARAM_VALUE.CMP_INTER PARAM_VALUE.CMP_INTER } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CMP_INTER}] ${MODELPARAM_VALUE.CMP_INTER} +} + +proc update_MODELPARAM_VALUE.TAG_FIFO_AW { MODELPARAM_VALUE.TAG_FIFO_AW PARAM_VALUE.TAG_FIFO_AW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TAG_FIFO_AW}] ${MODELPARAM_VALUE.TAG_FIFO_AW} +} + +proc update_MODELPARAM_VALUE.SMP_DW { MODELPARAM_VALUE.SMP_DW PARAM_VALUE.SMP_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SMP_DW}] ${MODELPARAM_VALUE.SMP_DW} +} + +proc update_MODELPARAM_VALUE.SMP_CK { MODELPARAM_VALUE.SMP_CK PARAM_VALUE.SMP_CK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SMP_CK}] ${MODELPARAM_VALUE.SMP_CK} +} + +proc update_MODELPARAM_VALUE.SMP_STORE { MODELPARAM_VALUE.SMP_STORE PARAM_VALUE.SMP_STORE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SMP_STORE}] ${MODELPARAM_VALUE.SMP_STORE} +} + +proc update_MODELPARAM_VALUE.SMP_FIFO_AW { MODELPARAM_VALUE.SMP_FIFO_AW PARAM_VALUE.SMP_FIFO_AW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SMP_FIFO_AW}] ${MODELPARAM_VALUE.SMP_FIFO_AW} +} + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + diff --git a/firmware/ip/qick_time_tagger/xgui/qick_time_tagger_v1_0.tcl b/firmware/ip/qick_time_tagger/xgui/qick_time_tagger_v1_0.tcl new file mode 100644 index 0000000..1b581ee --- /dev/null +++ b/firmware/ip/qick_time_tagger/xgui/qick_time_tagger_v1_0.tcl @@ -0,0 +1,211 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + #Adding Group + set Control [ipgui::add_group $IPINST -name "Control" -parent ${Page_0}] + ipgui::add_static_text $IPINST -name "CtrlText" -parent ${Control} -text {The Time tagger can be controlled from tProcessor and Python} + set EXT_ARM [ipgui::add_param $IPINST -name "EXT_ARM" -parent ${Control} -widget checkBox] + set_property tooltip {External ARM Control} ${EXT_ARM} + + #Adding Group + set TAG_FIFO [ipgui::add_group $IPINST -name "TAG FIFO" -parent ${Page_0} -display_name {ADC Tags}] + ipgui::add_param $IPINST -name "ADC_QTY" -parent ${TAG_FIFO} -widget comboBox + ipgui::add_param $IPINST -name "TAG_FIFO_AW" -parent ${TAG_FIFO} + #Adding Group + set Threshold_Comparison [ipgui::add_group $IPINST -name "Threshold Comparison" -parent ${TAG_FIFO}] + ipgui::add_param $IPINST -name "CMP_SLOPE" -parent ${Threshold_Comparison} -widget checkBox + ipgui::add_param $IPINST -name "CMP_INTER" -parent ${Threshold_Comparison} + + + #Adding Group + set ADC0_Options [ipgui::add_group $IPINST -name "ADC0 Options" -parent ${Page_0}] + #Adding Group + set Samples_Options [ipgui::add_group $IPINST -name "Samples Options" -parent ${ADC0_Options} -display_name {Samples}] + ipgui::add_param $IPINST -name "SMP_STORE" -parent ${Samples_Options} -widget checkBox + ipgui::add_param $IPINST -name "SMP_FIFO_AW" -parent ${Samples_Options} + + #Adding Group + set ARM_Triggers [ipgui::add_group $IPINST -name "ARM Triggers" -parent ${ADC0_Options} -display_name {ARM Info}] + ipgui::add_param $IPINST -name "ARM_STORE" -parent ${ARM_Triggers} -widget checkBox + ipgui::add_param $IPINST -name "ARM_FIFO_AW" -parent ${ARM_Triggers} + + + #Adding Group + set Debug [ipgui::add_group $IPINST -name "Debug" -parent ${Page_0}] + ipgui::add_param $IPINST -name "DEBUG" -parent ${Debug} -widget comboBox + + + +} + +proc update_PARAM_VALUE.ADC_QTY { PARAM_VALUE.ADC_QTY } { + # Procedure called to update ADC_QTY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_QTY { PARAM_VALUE.ADC_QTY } { + # Procedure called to validate ADC_QTY + return true +} + +proc update_PARAM_VALUE.ARM_FIFO_AW { PARAM_VALUE.ARM_FIFO_AW } { + # Procedure called to update ARM_FIFO_AW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ARM_FIFO_AW { PARAM_VALUE.ARM_FIFO_AW } { + # Procedure called to validate ARM_FIFO_AW + return true +} + +proc update_PARAM_VALUE.ARM_STORE { PARAM_VALUE.ARM_STORE } { + # Procedure called to update ARM_STORE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ARM_STORE { PARAM_VALUE.ARM_STORE } { + # Procedure called to validate ARM_STORE + return true +} + +proc update_PARAM_VALUE.CMP_INTER { PARAM_VALUE.CMP_INTER } { + # Procedure called to update CMP_INTER when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CMP_INTER { PARAM_VALUE.CMP_INTER } { + # Procedure called to validate CMP_INTER + return true +} + +proc update_PARAM_VALUE.CMP_SLOPE { PARAM_VALUE.CMP_SLOPE } { + # Procedure called to update CMP_SLOPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CMP_SLOPE { PARAM_VALUE.CMP_SLOPE } { + # Procedure called to validate CMP_SLOPE + return true +} + +proc update_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to update DEBUG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEBUG { PARAM_VALUE.DEBUG } { + # Procedure called to validate DEBUG + return true +} + +proc update_PARAM_VALUE.EXT_ARM { PARAM_VALUE.EXT_ARM } { + # Procedure called to update EXT_ARM when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.EXT_ARM { PARAM_VALUE.EXT_ARM } { + # Procedure called to validate EXT_ARM + return true +} + +proc update_PARAM_VALUE.SMP_CK { PARAM_VALUE.SMP_CK } { + # Procedure called to update SMP_CK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SMP_CK { PARAM_VALUE.SMP_CK } { + # Procedure called to validate SMP_CK + return true +} + +proc update_PARAM_VALUE.SMP_DW { PARAM_VALUE.SMP_DW } { + # Procedure called to update SMP_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SMP_DW { PARAM_VALUE.SMP_DW } { + # Procedure called to validate SMP_DW + return true +} + +proc update_PARAM_VALUE.SMP_FIFO_AW { PARAM_VALUE.SMP_FIFO_AW } { + # Procedure called to update SMP_FIFO_AW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SMP_FIFO_AW { PARAM_VALUE.SMP_FIFO_AW } { + # Procedure called to validate SMP_FIFO_AW + return true +} + +proc update_PARAM_VALUE.SMP_STORE { PARAM_VALUE.SMP_STORE } { + # Procedure called to update SMP_STORE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SMP_STORE { PARAM_VALUE.SMP_STORE } { + # Procedure called to validate SMP_STORE + return true +} + +proc update_PARAM_VALUE.TAG_FIFO_AW { PARAM_VALUE.TAG_FIFO_AW } { + # Procedure called to update TAG_FIFO_AW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TAG_FIFO_AW { PARAM_VALUE.TAG_FIFO_AW } { + # Procedure called to validate TAG_FIFO_AW + return true +} + + +proc update_MODELPARAM_VALUE.CMP_SLOPE { MODELPARAM_VALUE.CMP_SLOPE PARAM_VALUE.CMP_SLOPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CMP_SLOPE}] ${MODELPARAM_VALUE.CMP_SLOPE} +} + +proc update_MODELPARAM_VALUE.CMP_INTER { MODELPARAM_VALUE.CMP_INTER PARAM_VALUE.CMP_INTER } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CMP_INTER}] ${MODELPARAM_VALUE.CMP_INTER} +} + +proc update_MODELPARAM_VALUE.TAG_FIFO_AW { MODELPARAM_VALUE.TAG_FIFO_AW PARAM_VALUE.TAG_FIFO_AW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TAG_FIFO_AW}] ${MODELPARAM_VALUE.TAG_FIFO_AW} +} + +proc update_MODELPARAM_VALUE.SMP_DW { MODELPARAM_VALUE.SMP_DW PARAM_VALUE.SMP_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SMP_DW}] ${MODELPARAM_VALUE.SMP_DW} +} + +proc update_MODELPARAM_VALUE.SMP_CK { MODELPARAM_VALUE.SMP_CK PARAM_VALUE.SMP_CK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SMP_CK}] ${MODELPARAM_VALUE.SMP_CK} +} + +proc update_MODELPARAM_VALUE.SMP_STORE { MODELPARAM_VALUE.SMP_STORE PARAM_VALUE.SMP_STORE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SMP_STORE}] ${MODELPARAM_VALUE.SMP_STORE} +} + +proc update_MODELPARAM_VALUE.SMP_FIFO_AW { MODELPARAM_VALUE.SMP_FIFO_AW PARAM_VALUE.SMP_FIFO_AW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SMP_FIFO_AW}] ${MODELPARAM_VALUE.SMP_FIFO_AW} +} + +proc update_MODELPARAM_VALUE.DEBUG { MODELPARAM_VALUE.DEBUG PARAM_VALUE.DEBUG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEBUG}] ${MODELPARAM_VALUE.DEBUG} +} + +proc update_MODELPARAM_VALUE.ADC_QTY { MODELPARAM_VALUE.ADC_QTY PARAM_VALUE.ADC_QTY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_QTY}] ${MODELPARAM_VALUE.ADC_QTY} +} + +proc update_MODELPARAM_VALUE.ARM_STORE { MODELPARAM_VALUE.ARM_STORE PARAM_VALUE.ARM_STORE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ARM_STORE}] ${MODELPARAM_VALUE.ARM_STORE} +} + +proc update_MODELPARAM_VALUE.ARM_FIFO_AW { MODELPARAM_VALUE.ARM_FIFO_AW PARAM_VALUE.ARM_FIFO_AW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ARM_FIFO_AW}] ${MODELPARAM_VALUE.ARM_FIFO_AW} +} + +proc update_MODELPARAM_VALUE.EXT_ARM { MODELPARAM_VALUE.EXT_ARM PARAM_VALUE.EXT_ARM } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.EXT_ARM}] ${MODELPARAM_VALUE.EXT_ARM} +} + diff --git a/firmware/ip/qick_vec2bit/component.xml b/firmware/ip/qick_vec2bit/component.xml new file mode 100644 index 0000000..2ed18be --- /dev/null +++ b/firmware/ip/qick_vec2bit/component.xml @@ -0,0 +1,479 @@ + + + FERMI + user + qick_vec2bit + 1.0 + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + qick_vec2bit + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 2255dc03 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + + + viewChecksum + ab23a7c5 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f7ada015 + + + + + + + din + + in + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout0 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout1 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout2 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout3 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout4 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout5 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout6 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout7 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout8 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout9 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout10 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout11 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout12 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout13 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout14 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout15 + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + + + IN_DW + In Dw + 16 + + + OUT_QTY + Out Qty + 4 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/qick_vec2bit.v + verilogSource + CHECKSUM_2255dc03 + xil_defaultlib + + + + xilinx_xpgui_view_fileset + + xgui/qick_vec2bit_v1_0.tcl + tclSource + CHECKSUM_f7ada015 + XGUI_VERSION_2 + + + + qick_vec2bit + + + IN_DW + In Dw + 16 + + + OUT_QTY + Out Qty + 4 + + + Component_Name + qick_vect2bits_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /UserIP + + qick_vec2bit + package_project + 5 + 2023-06-12T16:47:20Z + + + 2022.1 + + + + + + + diff --git a/firmware/ip/qick_vec2bit/gui/qick_vect2bits_v1_0.gtcl b/firmware/ip/qick_vec2bit/gui/qick_vect2bits_v1_0.gtcl new file mode 100644 index 0000000..ccf952f --- /dev/null +++ b/firmware/ip/qick_vec2bit/gui/qick_vect2bits_v1_0.gtcl @@ -0,0 +1,2 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_OUT_QTY_ENABLEMENT {IN_DW } {expr $IN_DW > 1} diff --git a/firmware/ip/qick_vec2bit/src/qick_vec2bit.v b/firmware/ip/qick_vec2bit/src/qick_vec2bit.v new file mode 100644 index 0000000..20488f8 --- /dev/null +++ b/firmware/ip/qick_vec2bit/src/qick_vec2bit.v @@ -0,0 +1,45 @@ +`timescale 1ns / 1ps + +module qick_vec2bit # ( + parameter IN_DW = 16 , + parameter OUT_QTY = 4 +)( + input wire [IN_DW-1:0] din, + output wire dout0 , + output wire dout1 , + output wire dout2 , + output wire dout3 , + output wire dout4 , + output wire dout5 , + output wire dout6 , + output wire dout7 , + output wire dout8 , + output wire dout9 , + output wire dout10 , + output wire dout11 , + output wire dout12 , + output wire dout13 , + output wire dout14 , + output wire dout15 ); + +// OUTPUTS +///////////////////////////////////////////////// + + assign dout0 = din[0]; + assign dout1 = din[1]; + assign dout2 = din[2]; + assign dout3 = din[3]; + assign dout4 = din[4]; + assign dout5 = din[5]; + assign dout6 = din[6]; + assign dout7 = din[7]; + assign dout8 = din[8]; + assign dout9 = din[9]; + assign dout10 = din[10]; + assign dout11 = din[11]; + assign dout12 = din[12]; + assign dout13 = din[13]; + assign dout14 = din[14]; + assign dout15 = din[15]; + +endmodule diff --git a/firmware/ip/qick_vec2bit/src/qick_vect2bits.v b/firmware/ip/qick_vec2bit/src/qick_vect2bits.v new file mode 100644 index 0000000..abc542e --- /dev/null +++ b/firmware/ip/qick_vec2bit/src/qick_vect2bits.v @@ -0,0 +1,45 @@ +`timescale 1ns / 1ps + +module qick_vect2bits # ( + parameter IN_DW = 16 , + parameter OUT_QTY = 4 +)( + input wire [IN_DW-1:0] din, + output wire dout0 , + output wire dout1 , + output wire dout2 , + output wire dout3 , + output wire dout4 , + output wire dout5 , + output wire dout6 , + output wire dout7 , + output wire dout8 , + output wire dout9 , + output wire dout10 , + output wire dout11 , + output wire dout12 , + output wire dout13 , + output wire dout14 , + output wire dout15 ); + +// OUTPUTS +///////////////////////////////////////////////// + + assign dout0 = din[0]; + assign dout1 = din[1]; + assign dout2 = din[2]; + assign dout3 = din[3]; + assign dout4 = din[4]; + assign dout5 = din[5]; + assign dout6 = din[6]; + assign dout7 = din[7]; + assign dout8 = din[8]; + assign dout9 = din[9]; + assign dout10 = din[10]; + assign dout11 = din[11]; + assign dout12 = din[12]; + assign dout13 = din[13]; + assign dout14 = din[14]; + assign dout15 = din[15]; + +endmodule diff --git a/firmware/ip/qick_vec2bit/xgui/qick_vec2bit_v1_0.tcl b/firmware/ip/qick_vec2bit/xgui/qick_vec2bit_v1_0.tcl new file mode 100644 index 0000000..291a44e --- /dev/null +++ b/firmware/ip/qick_vec2bit/xgui/qick_vec2bit_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "IN_DW" -parent ${Page_0} + ipgui::add_param $IPINST -name "OUT_QTY" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.IN_DW { PARAM_VALUE.IN_DW } { + # Procedure called to update IN_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IN_DW { PARAM_VALUE.IN_DW } { + # Procedure called to validate IN_DW + return true +} + +proc update_PARAM_VALUE.OUT_QTY { PARAM_VALUE.OUT_QTY } { + # Procedure called to update OUT_QTY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_QTY { PARAM_VALUE.OUT_QTY } { + # Procedure called to validate OUT_QTY + return true +} + + +proc update_MODELPARAM_VALUE.IN_DW { MODELPARAM_VALUE.IN_DW PARAM_VALUE.IN_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IN_DW}] ${MODELPARAM_VALUE.IN_DW} +} + +proc update_MODELPARAM_VALUE.OUT_QTY { MODELPARAM_VALUE.OUT_QTY PARAM_VALUE.OUT_QTY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_QTY}] ${MODELPARAM_VALUE.OUT_QTY} +} + diff --git a/firmware/ip/qick_vec2bit/xgui/qick_vec2bits_v1_0.tcl b/firmware/ip/qick_vec2bit/xgui/qick_vec2bits_v1_0.tcl new file mode 100644 index 0000000..e6fa1df --- /dev/null +++ b/firmware/ip/qick_vec2bit/xgui/qick_vec2bits_v1_0.tcl @@ -0,0 +1,38 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + ipgui::add_param $IPINST -name "IN_DW" + set OUT_QTY [ipgui::add_param $IPINST -name "OUT_QTY"] + set_property tooltip {Number of 1bit Outputs} ${OUT_QTY} + +} + +proc update_PARAM_VALUE.IN_DW { PARAM_VALUE.IN_DW } { + # Procedure called to update IN_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IN_DW { PARAM_VALUE.IN_DW } { + # Procedure called to validate IN_DW + return true +} + +proc update_PARAM_VALUE.OUT_QTY { PARAM_VALUE.OUT_QTY } { + # Procedure called to update OUT_QTY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_QTY { PARAM_VALUE.OUT_QTY } { + # Procedure called to validate OUT_QTY + return true +} + + +proc update_MODELPARAM_VALUE.IN_DW { MODELPARAM_VALUE.IN_DW PARAM_VALUE.IN_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IN_DW}] ${MODELPARAM_VALUE.IN_DW} +} + +proc update_MODELPARAM_VALUE.OUT_QTY { MODELPARAM_VALUE.OUT_QTY PARAM_VALUE.OUT_QTY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_QTY}] ${MODELPARAM_VALUE.OUT_QTY} +} + diff --git a/firmware/ip/qick_vec2bit/xgui/qick_vect2bits_v1_0.tcl b/firmware/ip/qick_vec2bit/xgui/qick_vect2bits_v1_0.tcl new file mode 100644 index 0000000..291a44e --- /dev/null +++ b/firmware/ip/qick_vec2bit/xgui/qick_vect2bits_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "IN_DW" -parent ${Page_0} + ipgui::add_param $IPINST -name "OUT_QTY" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.IN_DW { PARAM_VALUE.IN_DW } { + # Procedure called to update IN_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IN_DW { PARAM_VALUE.IN_DW } { + # Procedure called to validate IN_DW + return true +} + +proc update_PARAM_VALUE.OUT_QTY { PARAM_VALUE.OUT_QTY } { + # Procedure called to update OUT_QTY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_QTY { PARAM_VALUE.OUT_QTY } { + # Procedure called to validate OUT_QTY + return true +} + + +proc update_MODELPARAM_VALUE.IN_DW { MODELPARAM_VALUE.IN_DW PARAM_VALUE.IN_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IN_DW}] ${MODELPARAM_VALUE.IN_DW} +} + +proc update_MODELPARAM_VALUE.OUT_QTY { MODELPARAM_VALUE.OUT_QTY PARAM_VALUE.OUT_QTY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_QTY}] ${MODELPARAM_VALUE.OUT_QTY} +} + diff --git a/firmware/photon_counting/._qick_4x2.bit b/firmware/photon_counting/._qick_4x2.bit deleted file mode 100644 index c3027f5..0000000 Binary files a/firmware/photon_counting/._qick_4x2.bit and /dev/null differ diff --git a/firmware/photon_counting/qick_4x2.bit b/firmware/photon_counting/qick_4x2.bit deleted file mode 100644 index be65f0c..0000000 Binary files a/firmware/photon_counting/qick_4x2.bit and /dev/null differ diff --git a/firmware/qick_111_ADC45/qick_111.bit b/firmware/zcu111/qickdawg_111.bit similarity index 81% rename from firmware/qick_111_ADC45/qick_111.bit rename to firmware/zcu111/qickdawg_111.bit index c86e22c..71c943e 100644 Binary files a/firmware/qick_111_ADC45/qick_111.bit and b/firmware/zcu111/qickdawg_111.bit differ diff --git a/firmware/photon_counting_9ghz/qick_4x2.hwh b/firmware/zcu111/qickdawg_111.hwh similarity index 83% rename from firmware/photon_counting_9ghz/qick_4x2.hwh rename to firmware/zcu111/qickdawg_111.hwh index 42b0608..fc929b0 100644 --- a/firmware/photon_counting_9ghz/qick_4x2.hwh +++ b/firmware/zcu111/qickdawg_111.hwh @@ -1,50 +1,50 @@  - + - + - + - + - + - + - + - + - + - + - + @@ -69,14 +69,14 @@ - + - + - + - + @@ -94,27 +94,27 @@ - + - + - + - + - + @@ -139,7 +139,7 @@ - + @@ -169,42 +169,92 @@ - + - + - + - + - + - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - + - + @@ -228,19 +278,19 @@ - + - - + + - + - + @@ -249,8 +299,8 @@ - - + + @@ -270,7 +320,7 @@ - + @@ -282,28 +332,58 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - + - - + + - + - - + + - + - - + + @@ -621,9 +701,9 @@ - - - + + + @@ -649,16 +729,16 @@ - + - - + + - + @@ -668,159 +748,159 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -843,7 +923,7 @@ - + @@ -860,12 +940,12 @@ - + - + - + @@ -928,7 +1008,7 @@ - + @@ -981,8 +1061,8 @@ - - + + @@ -995,8 +1075,8 @@ - - + + @@ -1022,9 +1102,9 @@ - + - + @@ -1051,7 +1131,7 @@ - + @@ -1135,7 +1215,7 @@ - + @@ -1173,7 +1253,7 @@ - + @@ -2088,16 +2168,16 @@ - - + + - + - + @@ -2109,162 +2189,162 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -2296,10 +2376,10 @@ - + - + @@ -2352,7 +2432,7 @@ - + @@ -2407,7 +2487,7 @@ - + @@ -2423,6 +2503,7 @@ + @@ -3308,16 +3389,16 @@ - - + + - + - + @@ -3329,162 +3410,162 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -3516,10 +3597,10 @@ - + - + @@ -3572,7 +3653,7 @@ - + @@ -3627,7 +3708,7 @@ - + @@ -3643,6 +3724,7 @@ + @@ -4528,16 +4610,16 @@ - - + + - + - + @@ -4549,147 +4631,147 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -4720,15 +4802,15 @@ - + - + - + @@ -4781,7 +4863,7 @@ - + @@ -4833,7 +4915,7 @@ - + @@ -4850,6 +4932,7 @@ + @@ -5735,16 +5818,16 @@ - - + + - + - + @@ -5756,162 +5839,162 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -5943,10 +6026,10 @@ - + - + @@ -5999,7 +6082,7 @@ - + @@ -6054,7 +6137,7 @@ - + @@ -6070,6 +6153,7 @@ + @@ -6906,7 +6990,7 @@ - + @@ -6933,7 +7017,7 @@ - + @@ -6955,21 +7039,21 @@ - - + + - + - + - + @@ -6981,147 +7065,147 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -7148,82 +7232,82 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -7250,20 +7334,20 @@ - + - + - + - + @@ -7282,8 +7366,8 @@ - - + + @@ -7316,7 +7400,7 @@ - + @@ -7364,7 +7448,7 @@ - + @@ -7419,7 +7503,7 @@ - + @@ -7442,7 +7526,7 @@ - + @@ -7459,6 +7543,8 @@ + + @@ -8995,16 +9081,16 @@ - + - - + + - + @@ -9016,87 +9102,87 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -9111,10 +9197,10 @@ - + - + @@ -9133,8 +9219,8 @@ - - + + @@ -9181,7 +9267,7 @@ - + @@ -9191,639 +9277,639 @@ - + - + - + - + - + - + - + - + - - + + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + + - + - + - + - + + - + - - + - + - + - + - - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - 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@@ -28848,7 +32587,7 @@ - + @@ -28922,7 +32661,7 @@ - + @@ -28991,58 +32730,67 @@ - + - - - + + - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + - + - - - + + + + + - + + + + diff --git a/firmware/zcu111/zcu111_src/bd_2022-1.tcl b/firmware/zcu111/zcu111_src/bd_2022-1.tcl new file mode 100644 index 0000000..c71eccc --- /dev/null +++ b/firmware/zcu111/zcu111_src/bd_2022-1.tcl @@ -0,0 +1,2747 @@ + +################################################################ +# This is a generated script based on design: d_1 +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2022.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source d_1_script.tcl + + +# The design that will be created by this Tcl script contains the following +# module references: +# vect2bits_16 + +# Please add the sources of those modules before sourcing this Tcl script. + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu28dr-ffvg1517-2-e + set_property BOARD_PART xilinx.com:zcu111:part0:1.4 [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name d_1 + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_bram_ctrl:4.1\ +xilinx.com:ip:blk_mem_gen:8.4\ +xilinx.com:ip:axi_dma:7.1\ +xilinx.com:ip:axi_intc:4.1\ +xilinx.com:ip:smartconnect:1.0\ +user.org:user:axis_avg_buffer:1.1\ +xilinx.com:ip:axis_broadcaster:1.1\ +user.org:user:axis_buffer_ddr_v1:1.0\ +user.org:user:axis_cdcsync_v1:1.0\ +xilinx.com:ip:axis_clock_converter:1.1\ +xilinx.com:ip:axis_dwidth_converter:1.1\ +user.org:user:axis_readout_v2:1.0\ +xilinx.com:ip:axis_register_slice:1.1\ +user.org:user:axis_set_reg:1.0\ +user.org:user:axis_signal_gen_v6:1.0\ +xilinx.com:ip:axis_switch:1.1\ +user.org:user:axis_tproc64x32_x8:1.0\ +xilinx.com:ip:clk_wiz:6.0\ +xilinx.com:ip:ddr4:2.2\ +user.org:user:mr_buffer_et:1.1\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:usp_rf_data_converter:2.6\ +xilinx.com:ip:xlconcat:2.1\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:zynq_ultra_ps_e:3.4\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 1 +if { $bCheckModules == 1 } { + set list_check_mods "\ +vect2bits_16\ +" + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set adc0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc0_clk ] + + set dac0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac0_clk ] + + set dac1_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac1_clk ] + + set ddr4_pl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_pl ] + + set sys_clk_ddr4 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk_ddr4 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {300000000} \ + ] $sys_clk_ddr4 + + set sysref_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0 sysref_in ] + + set vin0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin0 ] + + set vin1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin1 ] + + set vout0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout0 ] + + set vout1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout1 ] + + set vout2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout2 ] + + set vout3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout3 ] + + set vout4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout4 ] + + set vout5 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout5 ] + + set vout6 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout6 ] + + + # Create ports + set PMOD0_0_LS [ create_bd_port -dir O PMOD0_0_LS ] + set PMOD0_1_LS [ create_bd_port -dir O PMOD0_1_LS ] + set PMOD0_2_LS [ create_bd_port -dir O PMOD0_2_LS ] + set PMOD0_3_LS [ create_bd_port -dir O PMOD0_3_LS ] + set PMOD0_4_LS [ create_bd_port -dir O PMOD0_4_LS ] + set PMOD0_5_LS [ create_bd_port -dir O PMOD0_5_LS ] + set PMOD0_6_LS [ create_bd_port -dir O PMOD0_6_LS ] + set PMOD0_7_LS [ create_bd_port -dir O PMOD0_7_LS ] + set PMOD1_0_LS [ create_bd_port -dir I PMOD1_0_LS ] + + # Create instance: axi_bram_ctrl_0, and set properties + set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {64} \ + CONFIG.ECC_TYPE {0} \ + CONFIG.SINGLE_PORT_BRAM {1} \ + ] $axi_bram_ctrl_0 + + # Create instance: axi_bram_ctrl_0_bram, and set properties + set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] + set_property -dict [ list \ + CONFIG.EN_SAFETY_CKT {false} \ + CONFIG.Enable_B {Use_ENB_Pin} \ + CONFIG.Memory_Type {True_Dual_Port_RAM} \ + CONFIG.Port_B_Clock {100} \ + CONFIG.Port_B_Enable_Rate {100} \ + CONFIG.Port_B_Write_Rate {50} \ + CONFIG.Read_Width_B {64} \ + CONFIG.Use_RSTB_Pin {true} \ + CONFIG.Write_Width_B {64} \ + ] $axi_bram_ctrl_0_bram + + # Create instance: axi_dma_avg, and set properties + set axi_dma_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_avg ] + set_property -dict [ list \ + CONFIG.c_include_mm2s {0} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_include_stscntrl_strm {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_avg + + # Create instance: axi_dma_buf, and set properties + set axi_dma_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_buf ] + set_property -dict [ list \ + CONFIG.c_include_mm2s {0} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_include_stscntrl_strm {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_buf + + # Create instance: axi_dma_gen, and set properties + set axi_dma_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_gen ] + set_property -dict [ list \ + CONFIG.c_include_mm2s {1} \ + CONFIG.c_include_s2mm {0} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_include_stscntrl_strm {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_gen + + # Create instance: axi_dma_mr, and set properties + set axi_dma_mr [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_mr ] + set_property -dict [ list \ + CONFIG.c_include_mm2s {0} \ + CONFIG.c_include_s2mm {1} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_include_stscntrl_strm {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_mr + + # Create instance: axi_dma_tproc, and set properties + set axi_dma_tproc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_tproc ] + set_property -dict [ list \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_include_stscntrl_strm {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_tproc + + # Create instance: axi_intc_0, and set properties + set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ] + set_property -dict [ list \ + CONFIG.C_IRQ_CONNECTION {1} \ + ] $axi_intc_0 + + # Create instance: axi_smc, and set properties + set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] + set_property -dict [ list \ + CONFIG.NUM_SI {6} \ + ] $axi_smc + + # Create instance: axi_smc_1, and set properties + set axi_smc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc_1 ] + set_property -dict [ list \ + CONFIG.NUM_SI {2} \ + ] $axi_smc_1 + + # Create instance: axis_avg_buffer_0, and set properties + set axis_avg_buffer_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.1 axis_avg_buffer_0 ] + set_property -dict [ list \ + CONFIG.N_AVG {14} \ + ] $axis_avg_buffer_0 + + # Create instance: axis_avg_buffer_1, and set properties + set axis_avg_buffer_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.1 axis_avg_buffer_1 ] + set_property -dict [ list \ + CONFIG.N_AVG {14} \ + ] $axis_avg_buffer_1 + + # Create instance: axis_broadcaster_0, and set properties + set axis_broadcaster_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 axis_broadcaster_0 ] + set_property -dict [ list \ + CONFIG.HAS_TREADY {0} \ + ] $axis_broadcaster_0 + + # Create instance: axis_broadcaster_1, and set properties + set axis_broadcaster_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 axis_broadcaster_1 ] + set_property -dict [ list \ + CONFIG.HAS_TREADY {0} \ + ] $axis_broadcaster_1 + + # Create instance: axis_buffer_ddr_v1_0, and set properties + set axis_buffer_ddr_v1_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_buffer_ddr_v1:1.0 axis_buffer_ddr_v1_0 ] + set_property -dict [ list \ + CONFIG.TARGET_SLAVE_BASE_ADDR {0x00000000} \ + ] $axis_buffer_ddr_v1_0 + + # Create instance: axis_cdcsync_v1_0, and set properties + set axis_cdcsync_v1_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_cdcsync_v1:1.0 axis_cdcsync_v1_0 ] + set_property -dict [ list \ + CONFIG.B {160} \ + CONFIG.N {4} \ + ] $axis_cdcsync_v1_0 + + # Create instance: axis_cdcsync_v1_1, and set properties + set axis_cdcsync_v1_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_cdcsync_v1:1.0 axis_cdcsync_v1_1 ] + set_property -dict [ list \ + CONFIG.B {160} \ + CONFIG.N {4} \ + ] $axis_cdcsync_v1_1 + + # Create instance: axis_clk_cnvrt_avg_0, and set properties + set axis_clk_cnvrt_avg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_0 ] + + # Create instance: axis_clk_cnvrt_avg_1, and set properties + set axis_clk_cnvrt_avg_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_1 ] + + # Create instance: axis_clock_converter_0, and set properties + set axis_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clock_converter_0 ] + + # Create instance: axis_dwidth_converter_0, and set properties + set axis_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_converter_0 ] + set_property -dict [ list \ + CONFIG.M_TDATA_NUM_BYTES {64} \ + CONFIG.S_TDATA_NUM_BYTES {4} \ + ] $axis_dwidth_converter_0 + + # Create instance: axis_readout_v2_0, and set properties + set axis_readout_v2_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_0 ] + + # Create instance: axis_readout_v2_1, and set properties + set axis_readout_v2_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_1 ] + + # Create instance: axis_register_slice_0, and set properties + set axis_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_0 ] + + # Create instance: axis_register_slice_1, and set properties + set axis_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_1 ] + + # Create instance: axis_set_reg_0, and set properties + set axis_set_reg_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_set_reg:1.0 axis_set_reg_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {160} \ + ] $axis_set_reg_0 + + # Create instance: axis_signal_gen_v6_0, and set properties + set axis_signal_gen_v6_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_0 ] + + # Create instance: axis_signal_gen_v6_1, and set properties + set axis_signal_gen_v6_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_1 ] + + # Create instance: axis_signal_gen_v6_2, and set properties + set axis_signal_gen_v6_2 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_2 ] + + # Create instance: axis_signal_gen_v6_3, and set properties + set axis_signal_gen_v6_3 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_3 ] + + # Create instance: axis_signal_gen_v6_4, and set properties + set axis_signal_gen_v6_4 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_4 ] + + # Create instance: axis_signal_gen_v6_5, and set properties + set axis_signal_gen_v6_5 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_5 ] + + # Create instance: axis_signal_gen_v6_6, and set properties + set axis_signal_gen_v6_6 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_6 ] + + # Create instance: axis_switch_avg, and set properties + set axis_switch_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_avg ] + set_property -dict [ list \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_avg + + # Create instance: axis_switch_buf, and set properties + set axis_switch_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_buf ] + set_property -dict [ list \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_buf + + # Create instance: axis_switch_ddr, and set properties + set axis_switch_ddr [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_ddr ] + set_property -dict [ list \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_ddr + + # Create instance: axis_switch_gen, and set properties + set axis_switch_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_gen ] + set_property -dict [ list \ + CONFIG.DECODER_REG {1} \ + CONFIG.NUM_MI {7} \ + CONFIG.NUM_SI {1} \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_gen + + # Create instance: axis_switch_mr, and set properties + set axis_switch_mr [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_mr ] + set_property -dict [ list \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_mr + + # Create instance: axis_tproc64x32_x8_0, and set properties + set axis_tproc64x32_x8_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_tproc64x32_x8:1.0 axis_tproc64x32_x8_0 ] + set_property -dict [ list \ + CONFIG.DMEM_N {12} \ + CONFIG.PMEM_N {20} \ + ] $axis_tproc64x32_x8_0 + + # Create instance: clk_adc0_x2, and set properties + set clk_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_adc0_x2 ] + set_property -dict [ list \ + CONFIG.CLKIN1_JITTER_PS {39.06} \ + CONFIG.CLKOUT1_JITTER {73.505} \ + CONFIG.CLKOUT1_PHASE_ERROR {77.298} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {512} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {4.750} \ + CONFIG.MMCM_CLKIN1_PERIOD {3.906} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {2.375} \ + CONFIG.MMCM_DIVCLK_DIVIDE {1} \ + CONFIG.OPTIMIZE_CLOCKING_STRUCTURE_EN {true} \ + CONFIG.PRIM_SOURCE {Global_buffer} \ + ] $clk_adc0_x2 + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [ list \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.C0.BANK_GROUP_WIDTH {1} \ + CONFIG.C0.DDR4_AxiAddressWidth {32} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_CLKFBOUT_MULT {10} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3} \ + CONFIG.C0.DDR4_CasLatency {19} \ + CONFIG.C0.DDR4_DIVCLK_DIVIDE {3} \ + CONFIG.C0.DDR4_DataWidth {64} \ + CONFIG.C0.DDR4_InputClockPeriod {3334} \ + CONFIG.C0.DDR4_MemoryPart {MT40A512M16LY-075} \ + CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk1_300mhz} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_075} \ + ] $ddr4_0 + + # Create instance: mr_buffer_et_0, and set properties + set mr_buffer_et_0 [ create_bd_cell -type ip -vlnv user.org:user:mr_buffer_et:1.1 mr_buffer_et_0 ] + set_property -dict [ list \ + CONFIG.B {32} \ + CONFIG.N {10} \ + ] $mr_buffer_et_0 + + # Create instance: ps8_0_axi_periph, and set properties + set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] + set_property -dict [ list \ + CONFIG.NUM_MI {27} \ + ] $ps8_0_axi_periph + + # Create instance: rst_100, and set properties + set rst_100 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_100 ] + + # Create instance: rst_adc0, and set properties + set rst_adc0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0 ] + + # Create instance: rst_adc0_x2, and set properties + set rst_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0_x2 ] + + # Create instance: rst_dac0, and set properties + set rst_dac0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac0 ] + + # Create instance: rst_dac1, and set properties + set rst_dac1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac1 ] + + # Create instance: rst_ddr4, and set properties + set rst_ddr4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ddr4 ] + + # Create instance: usp_rf_data_converter_0, and set properties + set usp_rf_data_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.6 usp_rf_data_converter_0 ] + set_property -dict [ list \ + CONFIG.ADC0_Enable {1} \ + CONFIG.ADC0_Fabric_Freq {512.000} \ + CONFIG.ADC0_Outclk_Freq {256.000} \ + CONFIG.ADC0_PLL_Enable {true} \ + CONFIG.ADC0_Refclk_Freq {204.800} \ + CONFIG.ADC0_Sampling_Rate {4.096} \ + CONFIG.ADC_Decimation_Mode00 {1} \ + CONFIG.ADC_Decimation_Mode01 {1} \ + CONFIG.ADC_Decimation_Mode02 {1} \ + CONFIG.ADC_Decimation_Mode03 {1} \ + CONFIG.ADC_Mixer_Type00 {0} \ + CONFIG.ADC_Mixer_Type01 {0} \ + CONFIG.ADC_Mixer_Type02 {0} \ + CONFIG.ADC_Mixer_Type03 {0} \ + CONFIG.ADC_RESERVED_1_00 {false} \ + CONFIG.ADC_RESERVED_1_02 {false} \ + CONFIG.ADC_Slice00_Enable {true} \ + CONFIG.ADC_Slice01_Enable {true} \ + CONFIG.ADC_Slice02_Enable {true} \ + CONFIG.ADC_Slice03_Enable {true} \ + CONFIG.DAC0_Enable {1} \ + CONFIG.DAC0_Fabric_Freq {384.000} \ + CONFIG.DAC0_Outclk_Freq {384.000} \ + CONFIG.DAC0_PLL_Enable {true} \ + CONFIG.DAC0_Refclk_Freq {204.800} \ + CONFIG.DAC0_Sampling_Rate {6.144} \ + CONFIG.DAC1_Enable {1} \ + CONFIG.DAC1_Fabric_Freq {384.000} \ + CONFIG.DAC1_Outclk_Freq {384.000} \ + CONFIG.DAC1_PLL_Enable {true} \ + CONFIG.DAC1_Refclk_Freq {204.800} \ + CONFIG.DAC1_Sampling_Rate {6.144} \ + CONFIG.DAC_Interpolation_Mode00 {1} \ + CONFIG.DAC_Interpolation_Mode01 {1} \ + CONFIG.DAC_Interpolation_Mode02 {1} \ + CONFIG.DAC_Interpolation_Mode10 {1} \ + CONFIG.DAC_Interpolation_Mode11 {1} \ + CONFIG.DAC_Interpolation_Mode12 {1} \ + CONFIG.DAC_Interpolation_Mode13 {1} \ + CONFIG.DAC_Mixer_Type00 {0} \ + CONFIG.DAC_Mixer_Type01 {0} \ + CONFIG.DAC_Mixer_Type02 {0} \ + CONFIG.DAC_Mixer_Type10 {0} \ + CONFIG.DAC_Mixer_Type11 {0} \ + CONFIG.DAC_Mixer_Type12 {0} \ + CONFIG.DAC_Mixer_Type13 {0} \ + CONFIG.DAC_Slice00_Enable {true} \ + CONFIG.DAC_Slice01_Enable {true} \ + CONFIG.DAC_Slice02_Enable {true} \ + CONFIG.DAC_Slice10_Enable {true} \ + CONFIG.DAC_Slice11_Enable {true} \ + CONFIG.DAC_Slice12_Enable {true} \ + CONFIG.DAC_Slice13_Enable {true} \ + ] $usp_rf_data_converter_0 + + # Create instance: vect2bits_16_0, and set properties + set block_name vect2bits_16 + set block_cell_name vect2bits_16_0 + if { [catch {set vect2bits_16_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $vect2bits_16_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ + CONFIG.NUM_PORTS {6} \ + ] $xlconcat_0 + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {64} \ + ] $xlconstant_0 + + # Create instance: xlconstant_1, and set properties + set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] + set_property -dict [ list \ + CONFIG.CONST_WIDTH {1} \ + ] $xlconstant_1 + + # Create instance: xlconstant_2, and set properties + set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {1} \ + ] $xlconstant_2 + + # Create instance: xlconstant_3, and set properties + set xlconstant_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_3 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {8} \ + ] $xlconstant_3 + + # Create instance: zynq_ultra_ps_e_0, and set properties + set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.4 zynq_ultra_ps_e_0 ] + set_property -dict [ list \ + CONFIG.CAN0_BOARD_INTERFACE {custom} \ + CONFIG.CAN1_BOARD_INTERFACE {custom} \ + CONFIG.CSU_BOARD_INTERFACE {custom} \ + CONFIG.DP_BOARD_INTERFACE {custom} \ + CONFIG.GEM0_BOARD_INTERFACE {custom} \ + CONFIG.GEM1_BOARD_INTERFACE {custom} \ + CONFIG.GEM2_BOARD_INTERFACE {custom} \ + CONFIG.GEM3_BOARD_INTERFACE {custom} \ + CONFIG.GPIO_BOARD_INTERFACE {custom} \ + CONFIG.IIC0_BOARD_INTERFACE {custom} \ + CONFIG.IIC1_BOARD_INTERFACE {custom} \ + CONFIG.NAND_BOARD_INTERFACE {custom} \ + CONFIG.PCIE_BOARD_INTERFACE {custom} \ + CONFIG.PJTAG_BOARD_INTERFACE {custom} \ + CONFIG.PMU_BOARD_INTERFACE {custom} \ + CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \ + CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ + CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ + CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ + CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \ + CONFIG.PSU_IMPORT_BOARD_PRESET {} \ + CONFIG.PSU_MIO_0_DIRECTION {out} \ + CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_0_POLARITY {Default} \ + CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_0_SLEW {fast} \ + CONFIG.PSU_MIO_10_DIRECTION {inout} \ + CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_10_POLARITY {Default} \ + CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_10_SLEW {fast} \ + CONFIG.PSU_MIO_11_DIRECTION {inout} \ + CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_11_POLARITY {Default} \ + CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_11_SLEW {fast} \ + CONFIG.PSU_MIO_12_DIRECTION {out} \ + CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_12_POLARITY {Default} \ + CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_12_SLEW {fast} \ + CONFIG.PSU_MIO_13_DIRECTION {inout} \ + CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_13_POLARITY {Default} \ + CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_13_SLEW {fast} \ + CONFIG.PSU_MIO_14_DIRECTION {inout} \ + CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_14_POLARITY {Default} \ + CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_14_SLEW {fast} \ + CONFIG.PSU_MIO_15_DIRECTION {inout} \ + CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_15_POLARITY {Default} \ + CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_15_SLEW {fast} \ + CONFIG.PSU_MIO_16_DIRECTION {inout} \ + CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_16_POLARITY {Default} \ + CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_16_SLEW {fast} \ + CONFIG.PSU_MIO_17_DIRECTION {inout} \ + CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_17_POLARITY {Default} \ + CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_17_SLEW {fast} \ + CONFIG.PSU_MIO_18_DIRECTION {in} \ + CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_18_POLARITY {Default} \ + CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_18_SLEW {fast} \ + CONFIG.PSU_MIO_19_DIRECTION {out} \ + CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_19_POLARITY {Default} \ + CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_19_SLEW {fast} \ + CONFIG.PSU_MIO_1_DIRECTION {inout} \ + CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_1_POLARITY {Default} \ + CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_1_SLEW {fast} \ + CONFIG.PSU_MIO_20_DIRECTION {inout} \ + CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_20_POLARITY {Default} \ + CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_20_SLEW {fast} \ + CONFIG.PSU_MIO_21_DIRECTION {inout} \ + CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_21_POLARITY {Default} \ + CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_21_SLEW {fast} \ + CONFIG.PSU_MIO_22_DIRECTION {inout} \ + CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_22_POLARITY {Default} \ + CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_22_SLEW {fast} \ + CONFIG.PSU_MIO_23_DIRECTION {inout} \ + CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_23_POLARITY {Default} \ + CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_23_SLEW {fast} \ + CONFIG.PSU_MIO_24_DIRECTION {inout} \ + CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_24_POLARITY {Default} \ + CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_24_SLEW {fast} \ + CONFIG.PSU_MIO_25_DIRECTION {inout} \ + CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_25_POLARITY {Default} \ + CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_25_SLEW {fast} \ + CONFIG.PSU_MIO_26_DIRECTION {inout} \ + CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_26_POLARITY {Default} \ + CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_26_SLEW {fast} \ + CONFIG.PSU_MIO_27_DIRECTION {out} \ + CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_27_POLARITY {Default} \ + CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_27_SLEW {fast} \ + CONFIG.PSU_MIO_28_DIRECTION {in} \ + CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_28_POLARITY {Default} \ + CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_28_SLEW {fast} \ + CONFIG.PSU_MIO_29_DIRECTION {out} \ + CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_29_POLARITY {Default} \ + CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_29_SLEW {fast} \ + CONFIG.PSU_MIO_2_DIRECTION {inout} \ + CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_2_POLARITY {Default} \ + CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_2_SLEW {fast} \ + CONFIG.PSU_MIO_30_DIRECTION {in} \ + CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_30_POLARITY {Default} \ + CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_30_SLEW {fast} \ + CONFIG.PSU_MIO_31_DIRECTION {inout} \ + CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_31_POLARITY {Default} \ + CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_31_SLEW {fast} \ + CONFIG.PSU_MIO_32_DIRECTION {out} \ + CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_32_POLARITY {Default} \ + CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_32_SLEW {fast} \ + CONFIG.PSU_MIO_33_DIRECTION {out} \ + CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_33_POLARITY {Default} \ + CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_33_SLEW {fast} \ + CONFIG.PSU_MIO_34_DIRECTION {out} \ + CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_34_POLARITY {Default} \ + CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_34_SLEW {fast} \ + CONFIG.PSU_MIO_35_DIRECTION {out} \ + CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_35_POLARITY {Default} \ + CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_35_SLEW {fast} \ + CONFIG.PSU_MIO_36_DIRECTION {out} \ + CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_36_POLARITY {Default} \ + CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_36_SLEW {fast} \ + CONFIG.PSU_MIO_37_DIRECTION {out} \ + CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_37_POLARITY {Default} \ + CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_37_SLEW {fast} \ + CONFIG.PSU_MIO_38_DIRECTION {inout} \ + CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_38_POLARITY {Default} \ + CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_38_SLEW {fast} \ + CONFIG.PSU_MIO_39_DIRECTION {inout} \ + CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_39_POLARITY {Default} \ + CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_39_SLEW {fast} \ + CONFIG.PSU_MIO_3_DIRECTION {inout} \ + CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_3_POLARITY {Default} \ + CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_3_SLEW {fast} \ + CONFIG.PSU_MIO_40_DIRECTION {inout} \ + CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_40_POLARITY {Default} \ + CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_40_SLEW {fast} \ + CONFIG.PSU_MIO_41_DIRECTION {inout} \ + CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_41_POLARITY {Default} \ + CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_41_SLEW {fast} \ + CONFIG.PSU_MIO_42_DIRECTION {inout} \ + CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_42_POLARITY {Default} \ + CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_42_SLEW {fast} \ + CONFIG.PSU_MIO_43_DIRECTION {inout} \ + CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_43_POLARITY {Default} \ + CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_43_SLEW {fast} \ + CONFIG.PSU_MIO_44_DIRECTION {inout} \ + CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_44_POLARITY {Default} \ + CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_44_SLEW {fast} \ + CONFIG.PSU_MIO_45_DIRECTION {in} \ + CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_45_POLARITY {Default} \ + CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_45_SLEW {fast} \ + CONFIG.PSU_MIO_46_DIRECTION {inout} \ + CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_46_POLARITY {Default} \ + CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_46_SLEW {fast} \ + CONFIG.PSU_MIO_47_DIRECTION {inout} \ + CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_47_POLARITY {Default} \ + CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_47_SLEW {fast} \ + CONFIG.PSU_MIO_48_DIRECTION {inout} \ + CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_48_POLARITY {Default} \ + CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_48_SLEW {fast} \ + CONFIG.PSU_MIO_49_DIRECTION {inout} \ + CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_49_POLARITY {Default} \ + CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_49_SLEW {fast} \ + CONFIG.PSU_MIO_4_DIRECTION {inout} \ + CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_4_POLARITY {Default} \ + CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_4_SLEW {fast} \ + CONFIG.PSU_MIO_50_DIRECTION {inout} \ + CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_50_POLARITY {Default} \ + CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_50_SLEW {fast} \ + CONFIG.PSU_MIO_51_DIRECTION {out} \ + CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_51_POLARITY {Default} \ + CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_51_SLEW {fast} \ + CONFIG.PSU_MIO_52_DIRECTION {in} \ + CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_52_POLARITY {Default} \ + CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_52_SLEW {fast} \ + CONFIG.PSU_MIO_53_DIRECTION {in} \ + CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_53_POLARITY {Default} \ + CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_53_SLEW {fast} \ + CONFIG.PSU_MIO_54_DIRECTION {inout} \ + CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_54_POLARITY {Default} \ + CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_54_SLEW {fast} \ + CONFIG.PSU_MIO_55_DIRECTION {in} \ + CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_55_POLARITY {Default} \ + CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_55_SLEW {fast} \ + CONFIG.PSU_MIO_56_DIRECTION {inout} \ + CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_56_POLARITY {Default} \ + CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_56_SLEW {fast} \ + CONFIG.PSU_MIO_57_DIRECTION {inout} \ + CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_57_POLARITY {Default} \ + CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_57_SLEW {fast} \ + CONFIG.PSU_MIO_58_DIRECTION {out} \ + CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_58_POLARITY {Default} \ + CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_58_SLEW {fast} \ + CONFIG.PSU_MIO_59_DIRECTION {inout} \ + CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_59_POLARITY {Default} \ + CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_59_SLEW {fast} \ + CONFIG.PSU_MIO_5_DIRECTION {out} \ + CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_5_POLARITY {Default} \ + CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_5_SLEW {fast} \ + CONFIG.PSU_MIO_60_DIRECTION {inout} \ + CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_60_POLARITY {Default} \ + CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_60_SLEW {fast} \ + CONFIG.PSU_MIO_61_DIRECTION {inout} \ + CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_61_POLARITY {Default} \ + CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_61_SLEW {fast} \ + CONFIG.PSU_MIO_62_DIRECTION {inout} \ + CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_62_POLARITY {Default} \ + CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_62_SLEW {fast} \ + CONFIG.PSU_MIO_63_DIRECTION {inout} \ + CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_63_POLARITY {Default} \ + CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_63_SLEW {fast} \ + CONFIG.PSU_MIO_64_DIRECTION {out} \ + CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_64_POLARITY {Default} \ + CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_64_SLEW {fast} \ + CONFIG.PSU_MIO_65_DIRECTION {out} \ + CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_65_POLARITY {Default} \ + CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_65_SLEW {fast} \ + CONFIG.PSU_MIO_66_DIRECTION {out} \ + CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_66_POLARITY {Default} \ + CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_66_SLEW {fast} \ + CONFIG.PSU_MIO_67_DIRECTION {out} \ + CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_67_POLARITY {Default} \ + CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_67_SLEW {fast} \ + CONFIG.PSU_MIO_68_DIRECTION {out} \ + CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_68_POLARITY {Default} \ + CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_68_SLEW {fast} \ + CONFIG.PSU_MIO_69_DIRECTION {out} \ + CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_69_POLARITY {Default} \ + CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_69_SLEW {fast} \ + CONFIG.PSU_MIO_6_DIRECTION {out} \ + CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_6_POLARITY {Default} \ + CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_6_SLEW {fast} \ + CONFIG.PSU_MIO_70_DIRECTION {in} \ + CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_70_POLARITY {Default} \ + CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_70_SLEW {fast} \ + CONFIG.PSU_MIO_71_DIRECTION {in} \ + CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_71_POLARITY {Default} \ + CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_71_SLEW {fast} \ + CONFIG.PSU_MIO_72_DIRECTION {in} \ + CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_72_POLARITY {Default} \ + CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_72_SLEW {fast} \ + CONFIG.PSU_MIO_73_DIRECTION {in} \ + CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_73_POLARITY {Default} \ + CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_73_SLEW {fast} \ + CONFIG.PSU_MIO_74_DIRECTION {in} \ + CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_74_POLARITY {Default} \ + CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_74_SLEW {fast} \ + CONFIG.PSU_MIO_75_DIRECTION {in} \ + CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_75_POLARITY {Default} \ + CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_75_SLEW {fast} \ + CONFIG.PSU_MIO_76_DIRECTION {out} \ + CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_76_POLARITY {Default} \ + CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_76_SLEW {fast} \ + CONFIG.PSU_MIO_77_DIRECTION {inout} \ + CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_77_POLARITY {Default} \ + CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_77_SLEW {fast} \ + CONFIG.PSU_MIO_7_DIRECTION {out} \ + CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_7_POLARITY {Default} \ + CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_7_SLEW {fast} \ + CONFIG.PSU_MIO_8_DIRECTION {inout} \ + CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_8_POLARITY {Default} \ + CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_8_SLEW {fast} \ + CONFIG.PSU_MIO_9_DIRECTION {inout} \ + CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_9_POLARITY {Default} \ + CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_9_SLEW {fast} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {\ +Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\ +SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI\ +Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART\ +0#UART 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO1\ +MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO\ +3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1 MIO#SD 1#SD\ +1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB\ +0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\ +3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ + CONFIG.PSU_MIO_TREE_SIGNALS {\ +sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#gpio0[20]#gpio0[21]#gpio0[22]#gpio0[23]#gpio0[24]#gpio0[25]#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \ + CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \ + CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_SMC_CYCLE_T0 {NA} \ + CONFIG.PSU_SMC_CYCLE_T1 {NA} \ + CONFIG.PSU_SMC_CYCLE_T2 {NA} \ + CONFIG.PSU_SMC_CYCLE_T3 {NA} \ + CONFIG.PSU_SMC_CYCLE_T4 {NA} \ + CONFIG.PSU_SMC_CYCLE_T5 {NA} \ + CONFIG.PSU_SMC_CYCLE_T6 {NA} \ + CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ + CONFIG.PSU_VALUE_SILVERSION {3} \ + CONFIG.PSU__ACPU0__POWER__ON {1} \ + CONFIG.PSU__ACPU1__POWER__ON {1} \ + CONFIG.PSU__ACPU2__POWER__ON {1} \ + CONFIG.PSU__ACPU3__POWER__ON {1} \ + CONFIG.PSU__ACTUAL__IP {1} \ + CONFIG.PSU__ACT_DDR_FREQ_MHZ {1066.656006} \ + CONFIG.PSU__AFI0_COHERENCY {0} \ + CONFIG.PSU__AFI1_COHERENCY {0} \ + CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \ + CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.988037} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {533.328003} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.999750} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785446} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {299.997009} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {0} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \ + CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.328003} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999500} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.994995} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.984985} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.998749} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.498123} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.998749} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.498123} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999800} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ + CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ + CONFIG.PSU__CSU_COHERENCY {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__DDRC__ADDR_MIRROR {0} \ + CONFIG.PSU__DDRC__AL {0} \ + CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \ + CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ + CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ + CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ + CONFIG.PSU__DDRC__CL {15} \ + CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ + CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ + CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \ + CONFIG.PSU__DDRC__CWL {14} \ + CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ + CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ + CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ + CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ + CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ + CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ + CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ + CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ + CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ + CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ + CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ + CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ + CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ + CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ + CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ + CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ + CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ + CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ + CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ + CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ + CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ + CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ + CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ + CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ + CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ + CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ + CONFIG.PSU__DDRC__ECC {Disabled} \ + CONFIG.PSU__DDRC__ECC_SCRUB {0} \ + CONFIG.PSU__DDRC__ENABLE {1} \ + CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \ + CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \ + CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ + CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ + CONFIG.PSU__DDRC__EN_2ND_CLK {0} \ + CONFIG.PSU__DDRC__FGRM {1X} \ + CONFIG.PSU__DDRC__FREQ_MHZ {1} \ + CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \ + CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__LP_ASR {manual normal} \ + CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ + CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ + CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ + CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ + CONFIG.PSU__DDRC__PLL_BYPASS {0} \ + CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ + CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \ + CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \ + CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \ + CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ + CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ + CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ + CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ + CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ + CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ + CONFIG.PSU__DDRC__T_FAW {30.0} \ + CONFIG.PSU__DDRC__T_RAS_MIN {33} \ + CONFIG.PSU__DDRC__T_RC {47.06} \ + CONFIG.PSU__DDRC__T_RCD {15} \ + CONFIG.PSU__DDRC__T_RP {15} \ + CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ + CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \ + CONFIG.PSU__DDRC__VREF {1} \ + CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ + CONFIG.PSU__DDR_QOS_ENABLE {0} \ + CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \ + CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \ + CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \ + CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \ + CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \ + CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \ + CONFIG.PSU__DEVICE_TYPE {RFSOC} \ + CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ + CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ + CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \ + CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \ + CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DLL__ISUSED {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ + CONFIG.PSU__DP__LANE_SEL {Dual Lower} \ + CONFIG.PSU__DP__REF_CLK_FREQ {27} \ + CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \ + CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \ + CONFIG.PSU__ENET0__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET0__PTP__ENABLE {0} \ + CONFIG.PSU__ENET0__TSU__ENABLE {0} \ + CONFIG.PSU__ENET1__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET1__PTP__ENABLE {0} \ + CONFIG.PSU__ENET1__TSU__ENABLE {0} \ + CONFIG.PSU__ENET2__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET2__PTP__ENABLE {0} \ + CONFIG.PSU__ENET2__TSU__ENABLE {0} \ + CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ + CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ + CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ + CONFIG.PSU__ENET3__PTP__ENABLE {0} \ + CONFIG.PSU__ENET3__TSU__ENABLE {0} \ + CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \ + CONFIG.PSU__EN_EMIO_TRACE {0} \ + CONFIG.PSU__EP__IP {0} \ + CONFIG.PSU__EXPAND__CORESIGHT {0} \ + CONFIG.PSU__EXPAND__FPD_SLAVES {0} \ + CONFIG.PSU__EXPAND__GIC {0} \ + CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \ + CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \ + CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ + CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {99.999001} \ + CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__FPGA_PL0_ENABLE {1} \ + CONFIG.PSU__FPGA_PL1_ENABLE {0} \ + CONFIG.PSU__FPGA_PL2_ENABLE {0} \ + CONFIG.PSU__FPGA_PL3_ENABLE {0} \ + CONFIG.PSU__FP__POWER__ON {1} \ + CONFIG.PSU__FTM__CTI_IN_0 {0} \ + CONFIG.PSU__FTM__CTI_IN_1 {0} \ + CONFIG.PSU__FTM__CTI_IN_2 {0} \ + CONFIG.PSU__FTM__CTI_IN_3 {0} \ + CONFIG.PSU__FTM__CTI_OUT_0 {0} \ + CONFIG.PSU__FTM__CTI_OUT_1 {0} \ + CONFIG.PSU__FTM__CTI_OUT_2 {0} \ + CONFIG.PSU__FTM__CTI_OUT_3 {0} \ + CONFIG.PSU__FTM__GPI {0} \ + CONFIG.PSU__FTM__GPO {0} \ + CONFIG.PSU__GEM0_COHERENCY {0} \ + CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM1_COHERENCY {0} \ + CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM2_COHERENCY {0} \ + CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM3_COHERENCY {0} \ + CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM__TSU__ENABLE {0} \ + CONFIG.PSU__GEN_IPI_0__MASTER {APU} \ + CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \ + CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \ + CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \ + CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ + CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ + CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__GPIO_EMIO_WIDTH {1} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {} \ + CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \ + CONFIG.PSU__GPU_PP0__POWER__ON {0} \ + CONFIG.PSU__GPU_PP1__POWER__ON {0} \ + CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__GT__PRE_EMPH_LVL_4 {} \ + CONFIG.PSU__GT__VLT_SWNG_LVL_4 {} \ + CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \ + CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \ + CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \ + CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {99.999985} \ + CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \ + CONFIG.PSU__IRQ_P2F_AMS__INT {0} \ + CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \ + CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_CAN0__INT {0} \ + CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \ + CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSU_DMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSU__INT {0} \ + CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \ + CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT0_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT0__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT1_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT1__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT2_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT2__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPU__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \ + CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_NAND__INT {0} \ + CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \ + CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \ + CONFIG.PSU__IRQ_P2F_SATA__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO0_WAKE__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO0__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \ + CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \ + CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_UART0__INT {0} \ + CONFIG.PSU__IRQ_P2F_UART1__INT {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \ + CONFIG.PSU__L2_BANK0__POWER__ON {1} \ + CONFIG.PSU__LPDMA0_COHERENCY {0} \ + CONFIG.PSU__LPDMA1_COHERENCY {0} \ + CONFIG.PSU__LPDMA2_COHERENCY {0} \ + CONFIG.PSU__LPDMA3_COHERENCY {0} \ + CONFIG.PSU__LPDMA4_COHERENCY {0} \ + CONFIG.PSU__LPDMA5_COHERENCY {0} \ + CONFIG.PSU__LPDMA6_COHERENCY {0} \ + CONFIG.PSU__LPDMA7_COHERENCY {0} \ + CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \ + CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \ + CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \ + CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ + CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__NAND_COHERENCY {0} \ + CONFIG.PSU__NAND_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \ + CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \ + CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \ + CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \ + CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \ + CONFIG.PSU__NUM_FABRIC_RESETS {1} \ + CONFIG.PSU__OCM_BANK0__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK1__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK2__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK3__POWER__ON {1} \ + CONFIG.PSU__OVERRIDE_HPX_QOS {0} \ + CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ + CONFIG.PSU__PCIE__ACS_VIOLAION {0} \ + CONFIG.PSU__PCIE__ACS_VIOLATION {0} \ + CONFIG.PSU__PCIE__AER_CAPABILITY {0} \ + CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \ + CONFIG.PSU__PCIE__BAR0_64BIT {0} \ + CONFIG.PSU__PCIE__BAR0_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR0_VAL {} \ + CONFIG.PSU__PCIE__BAR1_64BIT {0} \ + CONFIG.PSU__PCIE__BAR1_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR1_VAL {} \ + CONFIG.PSU__PCIE__BAR2_64BIT {0} \ + CONFIG.PSU__PCIE__BAR2_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR2_VAL {} \ + CONFIG.PSU__PCIE__BAR3_64BIT {0} \ + CONFIG.PSU__PCIE__BAR3_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR3_VAL {} \ + CONFIG.PSU__PCIE__BAR4_64BIT {0} \ + CONFIG.PSU__PCIE__BAR4_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR4_VAL {} \ + CONFIG.PSU__PCIE__BAR5_64BIT {0} \ + CONFIG.PSU__PCIE__BAR5_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR5_VAL {} \ + CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \ + CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \ + CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \ + CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \ + CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \ + CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \ + CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \ + CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \ + CONFIG.PSU__PCIE__DEVICE_ID {} \ + CONFIG.PSU__PCIE__ECRC_CHECK {0} \ + CONFIG.PSU__PCIE__ECRC_ERR {0} \ + CONFIG.PSU__PCIE__ECRC_GEN {0} \ + CONFIG.PSU__PCIE__EROM_ENABLE {0} \ + CONFIG.PSU__PCIE__EROM_VAL {} \ + CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \ + CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \ + CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \ + CONFIG.PSU__PCIE__INTX_GENERATION {0} \ + CONFIG.PSU__PCIE__LANE0__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE1__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE2__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE3__ENABLE {0} \ + CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \ + CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \ + CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \ + CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \ + CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \ + CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \ + CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \ + CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \ + CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \ + CONFIG.PSU__PCIE__MULTIHEADER {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \ + CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \ + CONFIG.PSU__PCIE__RECEIVER_ERR {0} \ + CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \ + CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \ + CONFIG.PSU__PCIE__REVISION_ID {} \ + CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \ + CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \ + CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \ + CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \ + CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \ + CONFIG.PSU__PCIE__VENDOR_ID {} \ + CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PL_CLK0_BUF {TRUE} \ + CONFIG.PSU__PL_CLK1_BUF {FALSE} \ + CONFIG.PSU__PL_CLK2_BUF {FALSE} \ + CONFIG.PSU__PL_CLK3_BUF {FALSE} \ + CONFIG.PSU__PL__POWER__ON {1} \ + CONFIG.PSU__PMU_COHERENCY {0} \ + CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ + CONFIG.PSU__PMU__GPI0__ENABLE {0} \ + CONFIG.PSU__PMU__GPI1__ENABLE {0} \ + CONFIG.PSU__PMU__GPI2__ENABLE {0} \ + CONFIG.PSU__PMU__GPI3__ENABLE {0} \ + CONFIG.PSU__PMU__GPI4__ENABLE {0} \ + CONFIG.PSU__PMU__GPI5__ENABLE {0} \ + CONFIG.PSU__PMU__GPO0__ENABLE {1} \ + CONFIG.PSU__PMU__GPO0__IO {MIO 32} \ + CONFIG.PSU__PMU__GPO1__ENABLE {1} \ + CONFIG.PSU__PMU__GPO1__IO {MIO 33} \ + CONFIG.PSU__PMU__GPO2__ENABLE {1} \ + CONFIG.PSU__PMU__GPO2__IO {MIO 34} \ + CONFIG.PSU__PMU__GPO2__POLARITY {low} \ + CONFIG.PSU__PMU__GPO3__ENABLE {1} \ + CONFIG.PSU__PMU__GPO3__IO {MIO 35} \ + CONFIG.PSU__PMU__GPO3__POLARITY {low} \ + CONFIG.PSU__PMU__GPO4__ENABLE {1} \ + CONFIG.PSU__PMU__GPO4__IO {MIO 36} \ + CONFIG.PSU__PMU__GPO4__POLARITY {low} \ + CONFIG.PSU__PMU__GPO5__ENABLE {1} \ + CONFIG.PSU__PMU__GPO5__IO {MIO 37} \ + CONFIG.PSU__PMU__GPO5__POLARITY {low} \ + CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ + CONFIG.PSU__PRESET_APPLIED {1} \ + CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__DEBUG {0} \ + CONFIG.PSU__PROTECTION__ENABLE {0} \ + CONFIG.PSU__PROTECTION__FPD_SEGMENTS {\ +SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure;\ +WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64;\ +UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \ +SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure;\ +WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64;\ +UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \ +SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure;\ +WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64;\ +UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware |\ +SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write;\ +subsystemId:Secure Subsystem} \ + CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \ + CONFIG.PSU__PROTECTION__LPD_SEGMENTS {\ +SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure;\ +WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64;\ +UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\ +SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure;\ +WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64;\ +UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\ +SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ;\ +WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64;\ +UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure\ +Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ;\ +WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64;\ +UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \ + CONFIG.PSU__PROTECTION__MASTERS {\ +USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ + CONFIG.PSU__PROTECTION__MASTERS_TZ {\ +GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \ + CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \ + CONFIG.PSU__PROTECTION__SLAVES {\ +LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;0|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\ +Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \ + CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \ + CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \ + CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.33333} \ + CONFIG.PSU__QSPI_COHERENCY {0} \ + CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \ + CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \ + CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \ + CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \ + CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \ + CONFIG.PSU__REPORT__DBGLOG {0} \ + CONFIG.PSU__RPU_COHERENCY {0} \ + CONFIG.PSU__RPU__POWER__ON {1} \ + CONFIG.PSU__SATA__LANE0__ENABLE {0} \ + CONFIG.PSU__SATA__LANE1__ENABLE {1} \ + CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \ + CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SATA__REF_CLK_FREQ {125} \ + CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk3} \ + CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP1__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP5__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP6__DATA_WIDTH {128} \ + CONFIG.PSU__SD0_COHERENCY {0} \ + CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__SD0__CLK_100_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD0__CLK_200_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD0__CLK_50_DDR_ITAP_DLY {0x3D} \ + CONFIG.PSU__SD0__CLK_50_DDR_OTAP_DLY {0x4} \ + CONFIG.PSU__SD0__CLK_50_SDR_ITAP_DLY {0x15} \ + CONFIG.PSU__SD0__CLK_50_SDR_OTAP_DLY {0x5} \ + CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \ + CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \ + CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \ + CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SD0__RESET__ENABLE {0} \ + CONFIG.PSU__SD1_COHERENCY {0} \ + CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__SD1__CLK_100_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD1__CLK_200_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD1__CLK_50_DDR_ITAP_DLY {0x3D} \ + CONFIG.PSU__SD1__CLK_50_DDR_OTAP_DLY {0x4} \ + CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \ + CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \ + CONFIG.PSU__SD1__DATA_TRANSFER_MODE {8Bit} \ + CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \ + CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \ + CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \ + CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \ + CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \ + CONFIG.PSU__SD1__RESET__ENABLE {0} \ + CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \ + CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \ + CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SPI1__GRP_SS0__ENABLE {0} \ + CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \ + CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \ + CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \ + CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ + CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \ + CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ + CONFIG.PSU__TCM0A__POWER__ON {1} \ + CONFIG.PSU__TCM0B__POWER__ON {1} \ + CONFIG.PSU__TCM1A__POWER__ON {1} \ + CONFIG.PSU__TCM1B__POWER__ON {1} \ + CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TRACE_PIPELINE_WIDTH {8} \ + CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \ + CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TRISTATE__INVERTED {1} \ + CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ + CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \ + CONFIG.PSU__UART0__BAUD_RATE {115200} \ + CONFIG.PSU__UART0__MODEM__ENABLE {0} \ + CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \ + CONFIG.PSU__UART1__MODEM__ENABLE {0} \ + CONFIG.PSU__UART1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__USB0_COHERENCY {0} \ + CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ + CONFIG.PSU__USB0__REF_CLK_FREQ {26} \ + CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \ + CONFIG.PSU__USB0__RESET__ENABLE {0} \ + CONFIG.PSU__USB1_COHERENCY {0} \ + CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__USB1__RESET__ENABLE {0} \ + CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ + CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ + CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP1 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP2 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP3 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP4 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP5 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP6 {0} \ + CONFIG.PSU__USE__ADMA {0} \ + CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \ + CONFIG.PSU__USE__AUDIO {0} \ + CONFIG.PSU__USE__CLK {0} \ + CONFIG.PSU__USE__CLK0 {0} \ + CONFIG.PSU__USE__CLK1 {0} \ + CONFIG.PSU__USE__CLK2 {0} \ + CONFIG.PSU__USE__CLK3 {0} \ + CONFIG.PSU__USE__CROSS_TRIGGER {0} \ + CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \ + CONFIG.PSU__USE__DEBUG__TEST {0} \ + CONFIG.PSU__USE__EVENT_RPU {0} \ + CONFIG.PSU__USE__FABRIC__RST {1} \ + CONFIG.PSU__USE__FTM {0} \ + CONFIG.PSU__USE__GDMA {0} \ + CONFIG.PSU__USE__IRQ {0} \ + CONFIG.PSU__USE__IRQ0 {1} \ + CONFIG.PSU__USE__IRQ1 {0} \ + CONFIG.PSU__USE__M_AXI_GP0 {1} \ + CONFIG.PSU__USE__M_AXI_GP1 {1} \ + CONFIG.PSU__USE__M_AXI_GP2 {0} \ + CONFIG.PSU__USE__PROC_EVENT_BUS {0} \ + CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \ + CONFIG.PSU__USE__RST0 {0} \ + CONFIG.PSU__USE__RST1 {0} \ + CONFIG.PSU__USE__RST2 {0} \ + CONFIG.PSU__USE__RST3 {0} \ + CONFIG.PSU__USE__RTC {0} \ + CONFIG.PSU__USE__STM {0} \ + CONFIG.PSU__USE__S_AXI_ACE {0} \ + CONFIG.PSU__USE__S_AXI_ACP {0} \ + CONFIG.PSU__USE__S_AXI_GP0 {1} \ + CONFIG.PSU__USE__S_AXI_GP1 {0} \ + CONFIG.PSU__USE__S_AXI_GP2 {0} \ + CONFIG.PSU__USE__S_AXI_GP3 {0} \ + CONFIG.PSU__USE__S_AXI_GP4 {0} \ + CONFIG.PSU__USE__S_AXI_GP5 {0} \ + CONFIG.PSU__USE__S_AXI_GP6 {0} \ + CONFIG.PSU__USE__USB3_0_HUB {0} \ + CONFIG.PSU__USE__USB3_1_HUB {0} \ + CONFIG.PSU__USE__VIDEO {0} \ + CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \ + CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \ + CONFIG.QSPI_BOARD_INTERFACE {custom} \ + CONFIG.SATA_BOARD_INTERFACE {custom} \ + CONFIG.SD0_BOARD_INTERFACE {custom} \ + CONFIG.SD1_BOARD_INTERFACE {custom} \ + CONFIG.SPI0_BOARD_INTERFACE {custom} \ + CONFIG.SPI1_BOARD_INTERFACE {custom} \ + CONFIG.SUBPRESET1 {Custom} \ + CONFIG.SUBPRESET2 {Custom} \ + CONFIG.SWDT0_BOARD_INTERFACE {custom} \ + CONFIG.SWDT1_BOARD_INTERFACE {custom} \ + CONFIG.TRACE_BOARD_INTERFACE {custom} \ + CONFIG.TTC0_BOARD_INTERFACE {custom} \ + CONFIG.TTC1_BOARD_INTERFACE {custom} \ + CONFIG.TTC2_BOARD_INTERFACE {custom} \ + CONFIG.TTC3_BOARD_INTERFACE {custom} \ + CONFIG.UART0_BOARD_INTERFACE {custom} \ + CONFIG.UART1_BOARD_INTERFACE {custom} \ + CONFIG.USB0_BOARD_INTERFACE {custom} \ + CONFIG.USB1_BOARD_INTERFACE {custom} \ + ] $zynq_ultra_ps_e_0 + + # Create interface connections + connect_bd_intf_net -intf_net adc2_clk_0_1 [get_bd_intf_ports adc2_clk_0] [get_bd_intf_pins usp_rf_data_converter_0/adc2_clk] + connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTA] + connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXIS_MM2S] [get_bd_intf_pins axis_tproc64x32_x8_0/s0_axis] + connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S1 [get_bd_intf_pins axi_dma_gen/M_AXIS_MM2S] [get_bd_intf_pins axis_switch_gen/S00_AXIS] + connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_tproc/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S00_AXI] + connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S1 [get_bd_intf_pins axi_dma_gen/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S02_AXI] + connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_tproc/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S01_AXI] + connect_bd_intf_net -intf_net axi_dma_avg_M_AXI_S2MM [get_bd_intf_pins axi_dma_avg/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S03_AXI] + connect_bd_intf_net -intf_net axi_dma_buf_M_AXI_S2MM [get_bd_intf_pins axi_dma_buf/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S04_AXI] + connect_bd_intf_net -intf_net axi_dma_mr_M_AXI_S2MM [get_bd_intf_pins axi_dma_mr/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S05_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_dma_tproc/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins ps8_0_axi_periph/M08_AXI] [get_bd_intf_pins usp_rf_data_converter_0/s_axi] + connect_bd_intf_net -intf_net axis_avg_buffer_0_m0_axis [get_bd_intf_pins axis_avg_buffer_0/m0_axis] [get_bd_intf_pins axis_switch_avg/S00_AXIS] + connect_bd_intf_net -intf_net axis_avg_buffer_0_m1_axis [get_bd_intf_pins axis_avg_buffer_0/m1_axis] [get_bd_intf_pins axis_switch_buf/S00_AXIS] + connect_bd_intf_net -intf_net axis_avg_buffer_0_m2_axis [get_bd_intf_pins axis_avg_buffer_0/m2_axis] [get_bd_intf_pins axis_clk_cnvrt_avg_0/S_AXIS] + connect_bd_intf_net -intf_net axis_avg_buffer_1_m0_axis [get_bd_intf_pins axis_avg_buffer_1/m0_axis] [get_bd_intf_pins axis_switch_avg/S01_AXIS] + connect_bd_intf_net -intf_net axis_avg_buffer_1_m1_axis [get_bd_intf_pins axis_avg_buffer_1/m1_axis] [get_bd_intf_pins axis_switch_buf/S01_AXIS] + connect_bd_intf_net -intf_net axis_avg_buffer_1_m2_axis [get_bd_intf_pins axis_avg_buffer_1/m2_axis] [get_bd_intf_pins axis_clk_cnvrt_avg_1/S_AXIS] + connect_bd_intf_net -intf_net axis_broadcaster_0_M00_AXIS [get_bd_intf_pins axis_avg_buffer_0/s_axis] [get_bd_intf_pins axis_broadcaster_0/M00_AXIS] + connect_bd_intf_net -intf_net axis_broadcaster_0_M01_AXIS [get_bd_intf_pins axis_broadcaster_0/M01_AXIS] [get_bd_intf_pins axis_switch_ddr/S00_AXIS] + connect_bd_intf_net -intf_net axis_broadcaster_1_M00_AXIS [get_bd_intf_pins axis_avg_buffer_1/s_axis] [get_bd_intf_pins axis_broadcaster_1/M00_AXIS] + connect_bd_intf_net -intf_net axis_broadcaster_1_M01_AXIS [get_bd_intf_pins axis_broadcaster_1/M01_AXIS] [get_bd_intf_pins axis_switch_ddr/S01_AXIS] + connect_bd_intf_net -intf_net axis_buffer_ddr_v1_0_m_axi [get_bd_intf_pins axi_smc_1/S01_AXI] [get_bd_intf_pins axis_buffer_ddr_v1_0/m_axi] + connect_bd_intf_net -intf_net axis_cdcsync_v1_0_m0_axis [get_bd_intf_pins axis_cdcsync_v1_0/m0_axis] [get_bd_intf_pins axis_signal_gen_v6_0/s1_axis] + connect_bd_intf_net -intf_net axis_cdcsync_v1_0_m1_axis [get_bd_intf_pins axis_cdcsync_v1_0/m1_axis] [get_bd_intf_pins axis_signal_gen_v6_1/s1_axis] + connect_bd_intf_net -intf_net axis_cdcsync_v1_0_m2_axis [get_bd_intf_pins axis_cdcsync_v1_0/m2_axis] [get_bd_intf_pins axis_signal_gen_v6_2/s1_axis] + connect_bd_intf_net -intf_net axis_cdcsync_v1_0_m3_axis [get_bd_intf_pins axis_cdcsync_v1_0/m3_axis] [get_bd_intf_pins axis_signal_gen_v6_3/s1_axis] + connect_bd_intf_net -intf_net axis_cdcsync_v1_1_m0_axis [get_bd_intf_pins axis_cdcsync_v1_1/m0_axis] [get_bd_intf_pins axis_signal_gen_v6_4/s1_axis] + connect_bd_intf_net -intf_net axis_cdcsync_v1_1_m1_axis [get_bd_intf_pins axis_cdcsync_v1_1/m1_axis] [get_bd_intf_pins axis_signal_gen_v6_5/s1_axis] + connect_bd_intf_net -intf_net axis_cdcsync_v1_1_m2_axis [get_bd_intf_pins axis_cdcsync_v1_1/m2_axis] [get_bd_intf_pins axis_signal_gen_v6_6/s1_axis] + connect_bd_intf_net -intf_net axis_clk_cnvrt_avg_0_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_avg_0/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s1_axis] + connect_bd_intf_net -intf_net axis_clk_cnvrt_avg_1_M_AXIS [get_bd_intf_pins axis_clk_cnvrt_avg_1/M_AXIS] [get_bd_intf_pins axis_tproc64x32_x8_0/s2_axis] + connect_bd_intf_net -intf_net axis_clock_converter_0_M_AXIS [get_bd_intf_pins axis_buffer_ddr_v1_0/s_axis] [get_bd_intf_pins axis_clock_converter_0/M_AXIS] + connect_bd_intf_net -intf_net axis_dwidth_converter_0_M_AXIS [get_bd_intf_pins axis_clock_converter_0/S_AXIS] [get_bd_intf_pins axis_dwidth_converter_0/M_AXIS] + connect_bd_intf_net -intf_net axis_readout_v2_0_m0_axis [get_bd_intf_pins axis_readout_v2_0/m0_axis] [get_bd_intf_pins axis_switch_mr/S00_AXIS] + connect_bd_intf_net -intf_net axis_readout_v2_0_m1_axis [get_bd_intf_pins axis_broadcaster_0/S_AXIS] [get_bd_intf_pins axis_readout_v2_0/m1_axis] + connect_bd_intf_net -intf_net axis_readout_v2_1_m0_axis [get_bd_intf_pins axis_readout_v2_1/m0_axis] [get_bd_intf_pins axis_switch_mr/S01_AXIS] + connect_bd_intf_net -intf_net axis_readout_v2_1_m1_axis [get_bd_intf_pins axis_broadcaster_1/S_AXIS] [get_bd_intf_pins axis_readout_v2_1/m1_axis] + connect_bd_intf_net -intf_net axis_register_slice_0_M_AXIS [get_bd_intf_pins axis_readout_v2_0/s_axis] [get_bd_intf_pins axis_register_slice_0/M_AXIS] + connect_bd_intf_net -intf_net axis_register_slice_1_M_AXIS [get_bd_intf_pins axis_readout_v2_1/s_axis] [get_bd_intf_pins axis_register_slice_1/M_AXIS] + connect_bd_intf_net -intf_net axis_register_slice_2_M_AXIS [get_bd_intf_pins axis_register_slice_2/M_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/s20_axis] + connect_bd_intf_net -intf_net axis_register_slice_3_M_AXIS [get_bd_intf_pins axis_register_slice_3/M_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/s21_axis] + connect_bd_intf_net -intf_net axis_register_slice_4_M_AXIS [get_bd_intf_pins axis_register_slice_4/M_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/s22_axis] + connect_bd_intf_net -intf_net axis_register_slice_5_M_AXIS [get_bd_intf_pins axis_register_slice_5/M_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/s23_axis] + connect_bd_intf_net -intf_net axis_register_slice_6_M_AXIS [get_bd_intf_pins axis_register_slice_6/M_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/s30_axis] + connect_bd_intf_net -intf_net axis_register_slice_7_M_AXIS [get_bd_intf_pins axis_register_slice_7/M_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/s31_axis] + connect_bd_intf_net -intf_net axis_register_slice_8_M_AXIS [get_bd_intf_pins axis_register_slice_8/M_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/s32_axis] + connect_bd_intf_net -intf_net axis_signal_gen_v6_0_m_axis [get_bd_intf_pins axis_register_slice_2/S_AXIS] [get_bd_intf_pins axis_signal_gen_v6_0/m_axis] + connect_bd_intf_net -intf_net axis_signal_gen_v6_1_m_axis [get_bd_intf_pins axis_register_slice_3/S_AXIS] [get_bd_intf_pins axis_signal_gen_v6_1/m_axis] + connect_bd_intf_net -intf_net axis_signal_gen_v6_2_m_axis [get_bd_intf_pins axis_register_slice_4/S_AXIS] [get_bd_intf_pins axis_signal_gen_v6_2/m_axis] + connect_bd_intf_net -intf_net axis_signal_gen_v6_3_m_axis [get_bd_intf_pins axis_register_slice_5/S_AXIS] [get_bd_intf_pins axis_signal_gen_v6_3/m_axis] + connect_bd_intf_net -intf_net axis_signal_gen_v6_4_m_axis [get_bd_intf_pins axis_register_slice_6/S_AXIS] [get_bd_intf_pins axis_signal_gen_v6_4/m_axis] + connect_bd_intf_net -intf_net axis_signal_gen_v6_5_m_axis [get_bd_intf_pins axis_register_slice_7/S_AXIS] [get_bd_intf_pins axis_signal_gen_v6_5/m_axis] + connect_bd_intf_net -intf_net axis_signal_gen_v6_6_m_axis [get_bd_intf_pins axis_register_slice_8/S_AXIS] [get_bd_intf_pins axis_signal_gen_v6_6/m_axis] + connect_bd_intf_net -intf_net axis_switch_0_M00_AXIS [get_bd_intf_pins axis_signal_gen_v6_0/s0_axis] [get_bd_intf_pins axis_switch_gen/M00_AXIS] + connect_bd_intf_net -intf_net axis_switch_0_M01_AXIS [get_bd_intf_pins axis_signal_gen_v6_1/s0_axis] [get_bd_intf_pins axis_switch_gen/M01_AXIS] + connect_bd_intf_net -intf_net axis_switch_0_M02_AXIS [get_bd_intf_pins axis_signal_gen_v6_2/s0_axis] [get_bd_intf_pins axis_switch_gen/M02_AXIS] + connect_bd_intf_net -intf_net axis_switch_0_M03_AXIS [get_bd_intf_pins axis_signal_gen_v6_3/s0_axis] [get_bd_intf_pins axis_switch_gen/M03_AXIS] + connect_bd_intf_net -intf_net axis_switch_0_M04_AXIS [get_bd_intf_pins axis_signal_gen_v6_4/s0_axis] [get_bd_intf_pins axis_switch_gen/M04_AXIS] + connect_bd_intf_net -intf_net axis_switch_0_M05_AXIS [get_bd_intf_pins axis_signal_gen_v6_5/s0_axis] [get_bd_intf_pins axis_switch_gen/M05_AXIS] + connect_bd_intf_net -intf_net axis_switch_0_M06_AXIS [get_bd_intf_pins axis_signal_gen_v6_6/s0_axis] [get_bd_intf_pins axis_switch_gen/M06_AXIS] + connect_bd_intf_net -intf_net axis_switch_avg_M00_AXIS [get_bd_intf_pins axi_dma_avg/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_avg/M00_AXIS] + connect_bd_intf_net -intf_net axis_switch_buf_M00_AXIS [get_bd_intf_pins axi_dma_buf/S_AXIS_S2MM] [get_bd_intf_pins axis_switch_buf/M00_AXIS] + connect_bd_intf_net -intf_net axis_switch_ddr_M00_AXIS [get_bd_intf_pins axis_dwidth_converter_0/S_AXIS] [get_bd_intf_pins axis_switch_ddr/M00_AXIS] + connect_bd_intf_net -intf_net axis_switch_mr_M00_AXIS [get_bd_intf_pins axis_switch_mr/M00_AXIS] [get_bd_intf_pins mr_buffer_et_0/s00_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m0_axis [get_bd_intf_pins axi_dma_tproc/S_AXIS_S2MM] [get_bd_intf_pins axis_tproc64x32_x8_0/m0_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m1_axis [get_bd_intf_pins axis_set_reg_0/s_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m1_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m2_axis [get_bd_intf_pins axis_cdcsync_v1_0/s0_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m2_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m3_axis [get_bd_intf_pins axis_cdcsync_v1_0/s1_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m3_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m4_axis [get_bd_intf_pins axis_cdcsync_v1_0/s2_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m4_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m5_axis [get_bd_intf_pins axis_cdcsync_v1_0/s3_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m5_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m6_axis [get_bd_intf_pins axis_cdcsync_v1_1/s0_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m6_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m7_axis [get_bd_intf_pins axis_cdcsync_v1_1/s1_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m7_axis] + connect_bd_intf_net -intf_net axis_tproc64x32_x8_0_m8_axis [get_bd_intf_pins axis_cdcsync_v1_1/s2_axis] [get_bd_intf_pins axis_tproc64x32_x8_0/m8_axis] + connect_bd_intf_net -intf_net dac2_clk_0_1 [get_bd_intf_ports dac2_clk_0] [get_bd_intf_pins usp_rf_data_converter_0/dac2_clk] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram_c0] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net default_sysclk_c0_300mhz_1 [get_bd_intf_ports default_sysclk_c0_300mhz] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net -intf_net mr_buffer_et_0_m00_axis [get_bd_intf_pins axi_dma_mr/S_AXIS_S2MM] [get_bd_intf_pins mr_buffer_et_0/m00_axis] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins axis_tproc64x32_x8_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M02_AXI [get_bd_intf_pins axis_signal_gen_v6_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M02_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M03_AXI [get_bd_intf_pins axis_signal_gen_v6_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M03_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M04_AXI [get_bd_intf_pins axis_signal_gen_v6_2/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M04_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M05_AXI [get_bd_intf_pins axis_signal_gen_v6_3/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M05_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M06_AXI [get_bd_intf_pins axi_dma_gen/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M06_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M07_AXI [get_bd_intf_pins axis_switch_gen/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M07_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M09_AXI [get_bd_intf_pins axis_avg_buffer_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M09_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M10_AXI [get_bd_intf_pins axis_avg_buffer_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M10_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M11_AXI [get_bd_intf_pins axis_signal_gen_v6_4/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M11_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M12_AXI [get_bd_intf_pins axis_signal_gen_v6_5/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M12_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M13_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M13_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M14_AXI [get_bd_intf_pins axis_signal_gen_v6_6/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M14_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M15_AXI [get_bd_intf_pins axis_readout_v2_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M15_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M16_AXI [get_bd_intf_pins axis_readout_v2_1/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M16_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M17_AXI [get_bd_intf_pins axis_switch_avg/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M17_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M18_AXI [get_bd_intf_pins axis_switch_buf/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M18_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M19_AXI [get_bd_intf_pins axi_dma_avg/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M19_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M20_AXI [get_bd_intf_pins axi_dma_buf/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M20_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M21_AXI [get_bd_intf_pins axi_dma_mr/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M21_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M22_AXI [get_bd_intf_pins axis_buffer_ddr_v1_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M22_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M23_AXI [get_bd_intf_pins axis_switch_ddr/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M23_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M24_AXI [get_bd_intf_pins axis_switch_mr/S_AXI_CTRL] [get_bd_intf_pins ps8_0_axi_periph/M24_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M25_AXI [get_bd_intf_pins mr_buffer_et_0/s00_axi] [get_bd_intf_pins ps8_0_axi_periph/M25_AXI] + connect_bd_intf_net -intf_net ps8_0_axi_periph_M26_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M26_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HPC0_FPD] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI1 [get_bd_intf_pins axi_smc_1/M00_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] + connect_bd_intf_net -intf_net sysref_in_0_1 [get_bd_intf_ports sysref_in_0] [get_bd_intf_pins usp_rf_data_converter_0/sysref_in] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_m20_axis [get_bd_intf_pins axis_register_slice_0/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m20_axis] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_m22_axis [get_bd_intf_pins axis_register_slice_1/S_AXIS] [get_bd_intf_pins usp_rf_data_converter_0/m22_axis] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout20 [get_bd_intf_ports vout0] [get_bd_intf_pins usp_rf_data_converter_0/vout20] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout21 [get_bd_intf_ports vout1] [get_bd_intf_pins usp_rf_data_converter_0/vout21] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout22 [get_bd_intf_ports vout2] [get_bd_intf_pins usp_rf_data_converter_0/vout22] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout23 [get_bd_intf_ports vout3] [get_bd_intf_pins usp_rf_data_converter_0/vout23] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout30 [get_bd_intf_ports vout4] [get_bd_intf_pins usp_rf_data_converter_0/vout30] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout31 [get_bd_intf_ports vout5] [get_bd_intf_pins usp_rf_data_converter_0/vout31] + connect_bd_intf_net -intf_net usp_rf_data_converter_0_vout32 [get_bd_intf_ports vout6] [get_bd_intf_pins usp_rf_data_converter_0/vout32] + connect_bd_intf_net -intf_net vin20_0_1 [get_bd_intf_ports vin20_0] [get_bd_intf_pins usp_rf_data_converter_0/vin20] + connect_bd_intf_net -intf_net vin22_0_1 [get_bd_intf_ports vin22_0] [get_bd_intf_pins usp_rf_data_converter_0/vin22] + connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD] + connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM1_FPD [get_bd_intf_pins axi_smc_1/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM1_FPD] + + # Create port connections + connect_bd_net -net Net [get_bd_pins axi_smc_1/aresetn] [get_bd_pins axis_buffer_ddr_v1_0/aresetn] [get_bd_pins axis_clock_converter_0/m_axis_aresetn] [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins rst_ddr4/peripheral_aresetn] + connect_bd_net -net PMOD1_0_LS_1 [get_bd_ports PMOD1_0_LS] [get_bd_pins axis_tproc64x32_x8_0/start] + connect_bd_net -net axi_bram_ctrl_0_bram_doutb [get_bd_pins axi_bram_ctrl_0_bram/doutb] [get_bd_pins axis_tproc64x32_x8_0/pmem_do] + connect_bd_net -net axi_dma_avg_s2mm_introut [get_bd_pins axi_dma_avg/s2mm_introut] [get_bd_pins xlconcat_1/In0] + connect_bd_net -net axi_dma_buf_s2mm_introut [get_bd_pins axi_dma_buf/s2mm_introut] [get_bd_pins xlconcat_1/In1] + connect_bd_net -net axi_dma_gen_mm2s_introut [get_bd_pins axi_dma_gen/mm2s_introut] [get_bd_pins xlconcat_1/In3] + connect_bd_net -net axi_dma_mr_s2mm_introut [get_bd_pins axi_dma_mr/s2mm_introut] [get_bd_pins xlconcat_1/In2] + connect_bd_net -net axi_dma_tproc_mm2s_introut [get_bd_pins axi_dma_tproc/mm2s_introut] [get_bd_pins xlconcat_1/In4] + connect_bd_net -net axi_dma_tproc_s2mm_introut [get_bd_pins axi_dma_tproc/s2mm_introut] [get_bd_pins xlconcat_1/In5] + connect_bd_net -net axi_intc_0_irq [get_bd_pins axi_intc_0/irq] [get_bd_pins zynq_ultra_ps_e_0/pl_ps_irq0] + connect_bd_net -net axis_set_reg_0_dout [get_bd_pins axis_set_reg_0/dout] [get_bd_pins vect2bits_16_0/din] + connect_bd_net -net axis_tproc64x32_x8_0_pmem_addr [get_bd_pins axis_tproc64x32_x8_0/pmem_addr] [get_bd_pins xlconcat_0/In0] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins axi_smc_1/aclk] [get_bd_pins axis_buffer_ddr_v1_0/aclk] [get_bd_pins axis_clock_converter_0/m_axis_aclk] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins rst_ddr4/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm1_fpd_aclk] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk_sync_rst [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] [get_bd_pins rst_ddr4/ext_reset_in] + connect_bd_net -net rst_100_bus_struct_reset [get_bd_pins ddr4_0/sys_rst] [get_bd_pins rst_100/bus_struct_reset] + connect_bd_net -net rst_adc_peripheral_aresetn [get_bd_pins axis_avg_buffer_0/s_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axis_aresetn] [get_bd_pins axis_broadcaster_0/aresetn] [get_bd_pins axis_broadcaster_1/aresetn] [get_bd_pins axis_clock_converter_0/s_axis_aresetn] [get_bd_pins axis_dwidth_converter_0/aresetn] [get_bd_pins axis_readout_v2_0/aresetn] [get_bd_pins axis_readout_v2_1/aresetn] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins axis_register_slice_1/aresetn] [get_bd_pins axis_switch_ddr/aresetn] [get_bd_pins axis_switch_mr/aresetn] [get_bd_pins mr_buffer_et_0/s00_axis_aresetn] [get_bd_pins rst_adc/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/m2_axis_aresetn] + connect_bd_net -net rst_dac2_peripheral_aresetn [get_bd_pins axis_cdcsync_v1_0/m_axis_aresetn] [get_bd_pins axis_cdcsync_v1_0/s_axis_aresetn] [get_bd_pins axis_cdcsync_v1_1/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_avg_0/m_axis_aresetn] [get_bd_pins axis_clk_cnvrt_avg_1/m_axis_aresetn] [get_bd_pins axis_register_slice_2/aresetn] [get_bd_pins axis_register_slice_3/aresetn] [get_bd_pins axis_register_slice_4/aresetn] [get_bd_pins axis_register_slice_5/aresetn] [get_bd_pins axis_set_reg_0/s_axis_aresetn] [get_bd_pins axis_signal_gen_v6_0/aresetn] [get_bd_pins axis_signal_gen_v6_1/aresetn] [get_bd_pins axis_signal_gen_v6_2/aresetn] [get_bd_pins axis_signal_gen_v6_3/aresetn] [get_bd_pins axis_tproc64x32_x8_0/aresetn] [get_bd_pins rst_dac2/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s2_axis_aresetn] + connect_bd_net -net rst_dac3_peripheral_aresetn [get_bd_pins axis_cdcsync_v1_1/m_axis_aresetn] [get_bd_pins axis_register_slice_6/aresetn] [get_bd_pins axis_register_slice_7/aresetn] [get_bd_pins axis_register_slice_8/aresetn] [get_bd_pins axis_signal_gen_v6_4/aresetn] [get_bd_pins axis_signal_gen_v6_5/aresetn] [get_bd_pins axis_signal_gen_v6_6/aresetn] [get_bd_pins rst_dac3/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s3_axis_aresetn] + connect_bd_net -net rst_ps8_0_99M_peripheral_aresetn [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_dma_avg/axi_resetn] [get_bd_pins axi_dma_buf/axi_resetn] [get_bd_pins axi_dma_gen/axi_resetn] [get_bd_pins axi_dma_mr/axi_resetn] [get_bd_pins axi_dma_tproc/axi_resetn] [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins axis_avg_buffer_0/m_axis_aresetn] [get_bd_pins axis_avg_buffer_0/s_axi_aresetn] [get_bd_pins axis_avg_buffer_1/m_axis_aresetn] [get_bd_pins axis_avg_buffer_1/s_axi_aresetn] [get_bd_pins axis_buffer_ddr_v1_0/s_axi_aresetn] [get_bd_pins axis_clk_cnvrt_avg_0/s_axis_aresetn] [get_bd_pins axis_clk_cnvrt_avg_1/s_axis_aresetn] [get_bd_pins axis_readout_v2_0/s_axi_aresetn] [get_bd_pins axis_readout_v2_1/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_0/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_0/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_1/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_1/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_2/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_2/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_3/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_3/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_4/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_4/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_5/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_5/s_axi_aresetn] [get_bd_pins axis_signal_gen_v6_6/s0_axis_aresetn] [get_bd_pins axis_signal_gen_v6_6/s_axi_aresetn] [get_bd_pins axis_switch_avg/aresetn] [get_bd_pins axis_switch_avg/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_buf/aresetn] [get_bd_pins axis_switch_buf/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_ddr/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_gen/aresetn] [get_bd_pins axis_switch_gen/s_axi_ctrl_aresetn] [get_bd_pins axis_switch_mr/s_axi_ctrl_aresetn] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aresetn] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aresetn] [get_bd_pins mr_buffer_et_0/m00_axis_aresetn] [get_bd_pins mr_buffer_et_0/s00_axi_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/M02_ARESETN] [get_bd_pins ps8_0_axi_periph/M03_ARESETN] [get_bd_pins ps8_0_axi_periph/M04_ARESETN] [get_bd_pins ps8_0_axi_periph/M05_ARESETN] [get_bd_pins ps8_0_axi_periph/M06_ARESETN] [get_bd_pins ps8_0_axi_periph/M07_ARESETN] [get_bd_pins ps8_0_axi_periph/M08_ARESETN] [get_bd_pins ps8_0_axi_periph/M09_ARESETN] [get_bd_pins ps8_0_axi_periph/M10_ARESETN] [get_bd_pins ps8_0_axi_periph/M11_ARESETN] [get_bd_pins ps8_0_axi_periph/M12_ARESETN] [get_bd_pins ps8_0_axi_periph/M13_ARESETN] [get_bd_pins ps8_0_axi_periph/M14_ARESETN] [get_bd_pins ps8_0_axi_periph/M15_ARESETN] [get_bd_pins ps8_0_axi_periph/M16_ARESETN] [get_bd_pins ps8_0_axi_periph/M17_ARESETN] [get_bd_pins ps8_0_axi_periph/M18_ARESETN] [get_bd_pins ps8_0_axi_periph/M19_ARESETN] [get_bd_pins ps8_0_axi_periph/M20_ARESETN] [get_bd_pins ps8_0_axi_periph/M21_ARESETN] [get_bd_pins ps8_0_axi_periph/M22_ARESETN] [get_bd_pins ps8_0_axi_periph/M23_ARESETN] [get_bd_pins ps8_0_axi_periph/M24_ARESETN] [get_bd_pins ps8_0_axi_periph/M25_ARESETN] [get_bd_pins ps8_0_axi_periph/M26_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_100/peripheral_aresetn] [get_bd_pins usp_rf_data_converter_0/s_axi_aresetn] + connect_bd_net -net usp_rf_data_converter_0_clk_adc2 [get_bd_pins axis_avg_buffer_0/s_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axis_aclk] [get_bd_pins axis_broadcaster_0/aclk] [get_bd_pins axis_broadcaster_1/aclk] [get_bd_pins axis_clock_converter_0/s_axis_aclk] [get_bd_pins axis_dwidth_converter_0/aclk] [get_bd_pins axis_readout_v2_0/aclk] [get_bd_pins axis_readout_v2_1/aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins axis_switch_ddr/aclk] [get_bd_pins axis_switch_mr/aclk] [get_bd_pins mr_buffer_et_0/s00_axis_aclk] [get_bd_pins rst_adc/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_adc2] [get_bd_pins usp_rf_data_converter_0/m2_axis_aclk] + connect_bd_net -net usp_rf_data_converter_0_clk_dac2 [get_bd_pins axi_bram_ctrl_0_bram/clkb] [get_bd_pins axis_cdcsync_v1_0/m_axis_aclk] [get_bd_pins axis_cdcsync_v1_0/s_axis_aclk] [get_bd_pins axis_cdcsync_v1_1/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_avg_0/m_axis_aclk] [get_bd_pins axis_clk_cnvrt_avg_1/m_axis_aclk] [get_bd_pins axis_register_slice_2/aclk] [get_bd_pins axis_register_slice_3/aclk] [get_bd_pins axis_register_slice_4/aclk] [get_bd_pins axis_register_slice_5/aclk] [get_bd_pins axis_set_reg_0/s_axis_aclk] [get_bd_pins axis_signal_gen_v6_0/aclk] [get_bd_pins axis_signal_gen_v6_1/aclk] [get_bd_pins axis_signal_gen_v6_2/aclk] [get_bd_pins axis_signal_gen_v6_3/aclk] [get_bd_pins axis_tproc64x32_x8_0/aclk] [get_bd_pins rst_dac2/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_dac2] [get_bd_pins usp_rf_data_converter_0/s2_axis_aclk] + connect_bd_net -net usp_rf_data_converter_0_clk_dac3 [get_bd_pins axis_cdcsync_v1_1/m_axis_aclk] [get_bd_pins axis_register_slice_6/aclk] [get_bd_pins axis_register_slice_7/aclk] [get_bd_pins axis_register_slice_8/aclk] [get_bd_pins axis_signal_gen_v6_4/aclk] [get_bd_pins axis_signal_gen_v6_5/aclk] [get_bd_pins axis_signal_gen_v6_6/aclk] [get_bd_pins rst_dac3/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/clk_dac3] [get_bd_pins usp_rf_data_converter_0/s3_axis_aclk] + connect_bd_net -net vect2bits_16_0_dout0 [get_bd_ports PMOD0_0_LS] [get_bd_pins vect2bits_16_0/dout0] + connect_bd_net -net vect2bits_16_0_dout1 [get_bd_ports PMOD0_1_LS] [get_bd_pins vect2bits_16_0/dout1] + connect_bd_net -net vect2bits_16_0_dout2 [get_bd_ports PMOD0_2_LS] [get_bd_pins vect2bits_16_0/dout2] + connect_bd_net -net vect2bits_16_0_dout3 [get_bd_ports PMOD0_3_LS] [get_bd_pins vect2bits_16_0/dout3] + connect_bd_net -net vect2bits_16_0_dout4 [get_bd_ports PMOD0_4_LS] [get_bd_pins vect2bits_16_0/dout4] + connect_bd_net -net vect2bits_16_0_dout5 [get_bd_ports PMOD0_5_LS] [get_bd_pins vect2bits_16_0/dout5] + connect_bd_net -net vect2bits_16_0_dout6 [get_bd_ports PMOD0_6_LS] [get_bd_pins vect2bits_16_0/dout6] + connect_bd_net -net vect2bits_16_0_dout7 [get_bd_ports PMOD0_7_LS] [get_bd_pins vect2bits_16_0/dout7] + connect_bd_net -net vect2bits_16_0_dout12 [get_bd_pins mr_buffer_et_0/trigger] [get_bd_pins vect2bits_16_0/dout12] + connect_bd_net -net vect2bits_16_0_dout13 [get_bd_pins axis_buffer_ddr_v1_0/trigger] [get_bd_pins vect2bits_16_0/dout13] + connect_bd_net -net vect2bits_16_0_dout14 [get_bd_pins axis_avg_buffer_0/trigger] [get_bd_pins vect2bits_16_0/dout14] + connect_bd_net -net vect2bits_16_0_dout15 [get_bd_pins axis_avg_buffer_1/trigger] [get_bd_pins vect2bits_16_0/dout15] + connect_bd_net -net xlconcat_0_dout [get_bd_pins axi_bram_ctrl_0_bram/addrb] [get_bd_pins xlconcat_0/dout] + connect_bd_net -net xlconcat_1_dout [get_bd_pins axi_intc_0/intr] [get_bd_pins xlconcat_1/dout] + connect_bd_net -net xlconstant_0_dout [get_bd_pins axi_bram_ctrl_0_bram/dinb] [get_bd_pins xlconstant_0/dout] + connect_bd_net -net xlconstant_1_dout [get_bd_pins axi_bram_ctrl_0_bram/enb] [get_bd_pins xlconstant_1/dout] + connect_bd_net -net xlconstant_2_dout [get_bd_pins axi_bram_ctrl_0_bram/web] [get_bd_pins xlconstant_2/dout] + connect_bd_net -net xlconstant_3_dout [get_bd_pins axi_bram_ctrl_0_bram/rstb] [get_bd_pins xlconstant_3/dout] + connect_bd_net -net xlconstant_4_dout [get_bd_pins xlconcat_0/In1] [get_bd_pins xlconstant_4/dout] + connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_dma_avg/m_axi_s2mm_aclk] [get_bd_pins axi_dma_avg/s_axi_lite_aclk] [get_bd_pins axi_dma_buf/m_axi_s2mm_aclk] [get_bd_pins axi_dma_buf/s_axi_lite_aclk] [get_bd_pins axi_dma_gen/m_axi_mm2s_aclk] [get_bd_pins axi_dma_gen/s_axi_lite_aclk] [get_bd_pins axi_dma_mr/m_axi_s2mm_aclk] [get_bd_pins axi_dma_mr/s_axi_lite_aclk] [get_bd_pins axi_dma_tproc/m_axi_mm2s_aclk] [get_bd_pins axi_dma_tproc/m_axi_s2mm_aclk] [get_bd_pins axi_dma_tproc/s_axi_lite_aclk] [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins axis_avg_buffer_0/m_axis_aclk] [get_bd_pins axis_avg_buffer_0/s_axi_aclk] [get_bd_pins axis_avg_buffer_1/m_axis_aclk] [get_bd_pins axis_avg_buffer_1/s_axi_aclk] [get_bd_pins axis_buffer_ddr_v1_0/s_axi_aclk] [get_bd_pins axis_clk_cnvrt_avg_0/s_axis_aclk] [get_bd_pins axis_clk_cnvrt_avg_1/s_axis_aclk] [get_bd_pins axis_readout_v2_0/s_axi_aclk] [get_bd_pins axis_readout_v2_1/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_0/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_0/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_1/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_1/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_2/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_2/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_3/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_3/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_4/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_4/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_5/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_5/s_axi_aclk] [get_bd_pins axis_signal_gen_v6_6/s0_axis_aclk] [get_bd_pins axis_signal_gen_v6_6/s_axi_aclk] [get_bd_pins axis_switch_avg/aclk] [get_bd_pins axis_switch_avg/s_axi_ctrl_aclk] [get_bd_pins axis_switch_buf/aclk] [get_bd_pins axis_switch_buf/s_axi_ctrl_aclk] [get_bd_pins axis_switch_ddr/s_axi_ctrl_aclk] [get_bd_pins axis_switch_gen/aclk] [get_bd_pins axis_switch_gen/s_axi_ctrl_aclk] [get_bd_pins axis_switch_mr/s_axi_ctrl_aclk] [get_bd_pins axis_tproc64x32_x8_0/m0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s0_axis_aclk] [get_bd_pins axis_tproc64x32_x8_0/s_axi_aclk] [get_bd_pins mr_buffer_et_0/m00_axis_aclk] [get_bd_pins mr_buffer_et_0/s00_axi_aclk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/M02_ACLK] [get_bd_pins ps8_0_axi_periph/M03_ACLK] [get_bd_pins ps8_0_axi_periph/M04_ACLK] [get_bd_pins ps8_0_axi_periph/M05_ACLK] [get_bd_pins ps8_0_axi_periph/M06_ACLK] [get_bd_pins ps8_0_axi_periph/M07_ACLK] [get_bd_pins ps8_0_axi_periph/M08_ACLK] [get_bd_pins ps8_0_axi_periph/M09_ACLK] [get_bd_pins ps8_0_axi_periph/M10_ACLK] [get_bd_pins ps8_0_axi_periph/M11_ACLK] [get_bd_pins ps8_0_axi_periph/M12_ACLK] [get_bd_pins ps8_0_axi_periph/M13_ACLK] [get_bd_pins ps8_0_axi_periph/M14_ACLK] [get_bd_pins ps8_0_axi_periph/M15_ACLK] [get_bd_pins ps8_0_axi_periph/M16_ACLK] [get_bd_pins ps8_0_axi_periph/M17_ACLK] [get_bd_pins ps8_0_axi_periph/M18_ACLK] [get_bd_pins ps8_0_axi_periph/M19_ACLK] [get_bd_pins ps8_0_axi_periph/M20_ACLK] [get_bd_pins ps8_0_axi_periph/M21_ACLK] [get_bd_pins ps8_0_axi_periph/M22_ACLK] [get_bd_pins ps8_0_axi_periph/M23_ACLK] [get_bd_pins ps8_0_axi_periph/M24_ACLK] [get_bd_pins ps8_0_axi_periph/M25_ACLK] [get_bd_pins ps8_0_axi_periph/M26_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_100/slowest_sync_clk] [get_bd_pins usp_rf_data_converter_0/s_axi_aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihpc0_fpd_aclk] + connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_100/ext_reset_in] [get_bd_pins rst_adc/ext_reset_in] [get_bd_pins rst_dac2/ext_reset_in] [get_bd_pins rst_dac3/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] + + # Create address segments + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_mr/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_mr/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axis_buffer_ddr_v1_0/m_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0xA0200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0xA0000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_avg/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0xA0001000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_buf/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0xA0002000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_gen/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0xA0003000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_mr/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0xA0004000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_tproc/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0xA0005000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_intc_0/S_AXI/Reg] -force + assign_bd_address -offset 0xA0006000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_0/s_axi/reg0] -force + assign_bd_address -offset 0xA0007000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_avg_buffer_1/s_axi/reg0] -force + assign_bd_address -offset 0xA0008000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_buffer_ddr_v1_0/s_axi/reg0] -force + assign_bd_address -offset 0xA0009000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_0/s_axi/reg0] -force + assign_bd_address -offset 0xA000A000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_readout_v2_1/s_axi/reg0] -force + assign_bd_address -offset 0xA000B000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_0/s_axi/reg0] -force + assign_bd_address -offset 0xA000C000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_1/s_axi/reg0] -force + assign_bd_address -offset 0xA000D000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_2/s_axi/reg0] -force + assign_bd_address -offset 0xA000E000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_3/s_axi/reg0] -force + assign_bd_address -offset 0xA000F000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_4/s_axi/reg0] -force + assign_bd_address -offset 0xA0010000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_5/s_axi/reg0] -force + assign_bd_address -offset 0xA0011000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_signal_gen_v6_6/s_axi/reg0] -force + assign_bd_address -offset 0xA0012000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_avg/S_AXI_CTRL/Reg] -force + assign_bd_address -offset 0xA0013000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_buf/S_AXI_CTRL/Reg] -force + assign_bd_address -offset 0xA0014000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_ddr/S_AXI_CTRL/Reg] -force + assign_bd_address -offset 0xA0015000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_gen/S_AXI_CTRL/Reg] -force + assign_bd_address -offset 0xA0016000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_switch_mr/S_AXI_CTRL/Reg] -force + assign_bd_address -offset 0x000400000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axis_tproc64x32_x8_0/s_axi/reg0] -force + assign_bd_address -offset 0x000500000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0xA0017000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mr_buffer_et_0/s00_axi/reg0] -force + assign_bd_address -offset 0xA0140000 -range 0x00040000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs usp_rf_data_converter_0/s_axi/Reg] -force + + # Exclude Address Segments + exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_avg/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] + exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_buf/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] + exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_gen/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] + exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_mr/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_mr/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] + exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] + exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_HIGH] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_tproc/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_LPS_OCM] + + # Perform GUI Layout + regenerate_bd_layout -layout_string { + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"0.0795724", + "Default View_TopLeft":"-3393,-88", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS +# -string -flagsOSRD +preplace port adc2_clk_0 -pg 1 -lvl 9 -x 4430 -y 2270 -defaultsOSRD -right +preplace port dac2_clk_0 -pg 1 -lvl 9 -x 4430 -y 2240 -defaultsOSRD -right +preplace port ddr4_sdram_c0 -pg 1 -lvl 9 -x 4430 -y 3720 -defaultsOSRD +preplace port default_sysclk_c0_300mhz -pg 1 -lvl 9 -x 4430 -y 3650 -defaultsOSRD -right +preplace port sysref_in_0 -pg 1 -lvl 9 -x 4430 -y 2150 -defaultsOSRD -right +preplace port vin20_0 -pg 1 -lvl 9 -x 4430 -y 2210 -defaultsOSRD -right +preplace port vin22_0 -pg 1 -lvl 9 -x 4430 -y 2180 -defaultsOSRD -right +preplace port vout0 -pg 1 -lvl 9 -x 4430 -y 1810 -defaultsOSRD +preplace port vout1 -pg 1 -lvl 9 -x 4430 -y 1840 -defaultsOSRD +preplace port vout2 -pg 1 -lvl 9 -x 4430 -y 1870 -defaultsOSRD +preplace port vout3 -pg 1 -lvl 9 -x 4430 -y 1900 -defaultsOSRD +preplace port vout4 -pg 1 -lvl 9 -x 4430 -y 1930 -defaultsOSRD +preplace port vout5 -pg 1 -lvl 9 -x 4430 -y 1960 -defaultsOSRD +preplace port vout6 -pg 1 -lvl 9 -x 4430 -y 1990 -defaultsOSRD +preplace port port-id_PMOD0_0_LS -pg 1 -lvl 9 -x 4430 -y 1280 -defaultsOSRD +preplace port port-id_PMOD0_1_LS -pg 1 -lvl 9 -x 4430 -y 1310 -defaultsOSRD +preplace port port-id_PMOD0_2_LS -pg 1 -lvl 9 -x 4430 -y 1340 -defaultsOSRD +preplace port port-id_PMOD0_3_LS -pg 1 -lvl 9 -x 4430 -y 1370 -defaultsOSRD +preplace port port-id_PMOD0_4_LS -pg 1 -lvl 9 -x 4430 -y 1400 -defaultsOSRD +preplace port port-id_PMOD0_5_LS -pg 1 -lvl 9 -x 4430 -y 1430 -defaultsOSRD +preplace port port-id_PMOD0_6_LS -pg 1 -lvl 9 -x 4430 -y 1460 -defaultsOSRD +preplace port port-id_PMOD0_7_LS -pg 1 -lvl 9 -x 4430 -y 1490 -defaultsOSRD +preplace port port-id_PMOD1_0_LS -pg 1 -lvl 0 -x 0 -y 1510 -defaultsOSRD +preplace inst axi_bram_ctrl_0 -pg 1 -lvl 1 -x 200 -y 1800 -defaultsOSRD +preplace inst axi_bram_ctrl_0_bram -pg 1 -lvl 2 -x 720 -y 1910 -defaultsOSRD +preplace inst axi_dma_avg -pg 1 -lvl 2 -x 720 -y 330 -defaultsOSRD +preplace inst axi_dma_buf -pg 1 -lvl 2 -x 720 -y 510 -defaultsOSRD +preplace inst axi_dma_gen -pg 1 -lvl 2 -x 720 -y 910 -defaultsOSRD +preplace inst axi_dma_mr -pg 1 -lvl 2 -x 720 -y 690 -defaultsOSRD +preplace inst axi_dma_tproc -pg 1 -lvl 2 -x 720 -y 1100 -defaultsOSRD +preplace inst axi_intc_0 -pg 1 -lvl 3 -x 1280 -y 420 -defaultsOSRD +preplace inst axi_smc -pg 1 -lvl 3 -x 1280 -y 680 -defaultsOSRD +preplace inst axi_smc_1 -pg 1 -lvl 7 -x 3800 -y 3870 -defaultsOSRD +preplace inst axis_avg_buffer_0 -pg 1 -lvl 4 -x 2030 -y 3440 -defaultsOSRD +preplace inst axis_avg_buffer_1 -pg 1 -lvl 4 -x 2030 -y 3840 -defaultsOSRD +preplace inst axis_broadcaster_0 -pg 1 -lvl 4 -x 2030 -y 3220 -defaultsOSRD +preplace inst axis_broadcaster_1 -pg 1 -lvl 4 -x 2030 -y 3640 -defaultsOSRD +preplace inst axis_buffer_ddr_v1_0 -pg 1 -lvl 7 -x 3800 -y 3680 -defaultsOSRD +preplace inst axis_cdcsync_v1_0 -pg 1 -lvl 3 -x 1280 -y 1670 -defaultsOSRD +preplace inst axis_cdcsync_v1_1 -pg 1 -lvl 3 -x 1280 -y 1990 -defaultsOSRD +preplace inst axis_clk_cnvrt_avg_0 -pg 1 -lvl 5 -x 2770 -y 2610 -defaultsOSRD +preplace inst axis_clk_cnvrt_avg_1 -pg 1 -lvl 5 -x 2770 -y 3230 -defaultsOSRD +preplace inst axis_clock_converter_0 -pg 1 -lvl 6 -x 3370 -y 3840 -defaultsOSRD +preplace inst axis_dwidth_converter_0 -pg 1 -lvl 6 -x 3370 -y 3680 -defaultsOSRD +preplace inst axis_readout_v2_0 -pg 1 -lvl 3 -x 1280 -y 3140 -defaultsOSRD +preplace inst axis_readout_v2_1 -pg 1 -lvl 3 -x 1280 -y 3370 -defaultsOSRD +preplace inst axis_register_slice_0 -pg 1 -lvl 2 -x 720 -y 3090 -defaultsOSRD +preplace inst axis_register_slice_1 -pg 1 -lvl 2 -x 720 -y 3260 -defaultsOSRD +preplace inst axis_register_slice_2 -pg 1 -lvl 5 -x 2770 -y 1610 -defaultsOSRD +preplace inst axis_register_slice_3 -pg 1 -lvl 5 -x 2770 -y 1750 -defaultsOSRD +preplace inst axis_register_slice_4 -pg 1 -lvl 5 -x 2770 -y 1890 -defaultsOSRD +preplace inst axis_register_slice_5 -pg 1 -lvl 5 -x 2770 -y 2030 -defaultsOSRD +preplace inst axis_register_slice_6 -pg 1 -lvl 5 -x 2770 -y 2170 -defaultsOSRD +preplace inst axis_register_slice_7 -pg 1 -lvl 5 -x 2770 -y 2310 -defaultsOSRD +preplace inst axis_register_slice_8 -pg 1 -lvl 5 -x 2770 -y 2450 -defaultsOSRD +preplace inst axis_set_reg_0 -pg 1 -lvl 5 -x 2770 -y 1470 -defaultsOSRD +preplace inst axis_signal_gen_v6_0 -pg 1 -lvl 4 -x 2030 -y 1440 -defaultsOSRD +preplace inst axis_signal_gen_v6_1 -pg 1 -lvl 4 -x 2030 -y 1700 -defaultsOSRD +preplace inst axis_signal_gen_v6_2 -pg 1 -lvl 4 -x 2030 -y 1960 -defaultsOSRD +preplace inst axis_signal_gen_v6_3 -pg 1 -lvl 4 -x 2030 -y 2220 -defaultsOSRD +preplace inst axis_signal_gen_v6_4 -pg 1 -lvl 4 -x 2030 -y 2480 -defaultsOSRD +preplace inst axis_signal_gen_v6_5 -pg 1 -lvl 4 -x 2030 -y 2740 -defaultsOSRD +preplace inst axis_signal_gen_v6_6 -pg 1 -lvl 4 -x 2030 -y 3000 -defaultsOSRD +preplace inst axis_switch_avg -pg 1 -lvl 5 -x 2770 -y 2810 -defaultsOSRD +preplace inst axis_switch_buf -pg 1 -lvl 5 -x 2770 -y 3030 -defaultsOSRD +preplace inst axis_switch_ddr -pg 1 -lvl 5 -x 2770 -y 3720 -defaultsOSRD +preplace inst axis_switch_gen -pg 1 -lvl 3 -x 1280 -y 1270 -defaultsOSRD +preplace inst axis_switch_mr -pg 1 -lvl 5 -x 2770 -y 3440 -defaultsOSRD +preplace inst axis_tproc64x32_x8_0 -pg 1 -lvl 2 -x 720 -y 1410 -defaultsOSRD +preplace inst ddr4_0 -pg 1 -lvl 8 -x 4200 -y 3780 -defaultsOSRD +preplace inst mr_buffer_et_0 -pg 1 -lvl 6 -x 3370 -y 3400 -defaultsOSRD +preplace inst ps8_0_axi_periph -pg 1 -lvl 5 -x 2770 -y 770 -defaultsOSRD +preplace inst rst_100 -pg 1 -lvl 4 -x 2030 -y 500 -defaultsOSRD +preplace inst rst_adc -pg 1 -lvl 4 -x 2030 -y 680 -defaultsOSRD +preplace inst rst_dac2 -pg 1 -lvl 4 -x 2030 -y 860 -defaultsOSRD +preplace inst rst_dac3 -pg 1 -lvl 4 -x 2030 -y 1040 -defaultsOSRD +preplace inst rst_ddr4 -pg 1 -lvl 4 -x 2030 -y 1220 -defaultsOSRD +preplace inst usp_rf_data_converter_0 -pg 1 -lvl 7 -x 3800 -y 1950 -defaultsOSRD +preplace inst vect2bits_16_0 -pg 1 -lvl 7 -x 3800 -y 1500 -defaultsOSRD +preplace inst xlconcat_0 -pg 1 -lvl 2 -x 720 -y 1700 -defaultsOSRD +preplace inst xlconcat_1 -pg 1 -lvl 3 -x 1280 -y 240 -defaultsOSRD +preplace inst xlconstant_0 -pg 1 -lvl 1 -x 200 -y 1920 -defaultsOSRD +preplace inst xlconstant_1 -pg 1 -lvl 1 -x 200 -y 2020 -defaultsOSRD +preplace inst xlconstant_2 -pg 1 -lvl 1 -x 200 -y 2220 -defaultsOSRD +preplace inst xlconstant_3 -pg 1 -lvl 1 -x 200 -y 2120 -defaultsOSRD +preplace inst xlconstant_4 -pg 1 -lvl 1 -x 200 -y 1680 -defaultsOSRD +preplace inst zynq_ultra_ps_e_0 -pg 1 -lvl 4 -x 2030 -y 320 -defaultsOSRD +preplace netloc Net 1 4 4 2410 3880 3150 3940 3610 3970 4020J +preplace netloc PMOD1_0_LS_1 1 0 2 20 1540 NJ +preplace netloc axi_bram_ctrl_0_bram_doutb 1 1 1 490 1560n +preplace netloc axi_dma_avg_s2mm_introut 1 2 1 890 190n +preplace netloc axi_dma_buf_s2mm_introut 1 2 1 900 210n +preplace netloc axi_dma_gen_mm2s_introut 1 2 1 930 250n +preplace netloc axi_dma_mr_s2mm_introut 1 2 1 920 230n +preplace netloc axi_dma_tproc_mm2s_introut 1 2 1 980 270n +preplace netloc axi_dma_tproc_s2mm_introut 1 2 1 1010 290n +preplace netloc axi_intc_0_irq 1 3 1 1440 360n +preplace netloc axis_set_reg_0_dout 1 5 2 N 1470 3560 +preplace netloc axis_tproc64x32_x8_0_pmem_addr 1 1 2 440J 810 900 +preplace netloc ddr4_0_c0_ddr4_ui_clk 1 3 6 1700 200 2460 3890 3160 3950 3560 3990 NJ 3990 4370 +preplace netloc ddr4_0_c0_ddr4_ui_clk_sync_rst 1 3 6 1650 4080 N 4080 N 4080 N 4080 N 4080 4360 +preplace netloc rst_100_bus_struct_reset 1 4 4 2430J 3980 NJ 3980 NJ 3980 4030 +preplace netloc rst_adc_peripheral_aresetn 1 1 6 500 3170 900 3250 1570 4050 2390 3910 3080J 3200 3510 +preplace netloc rst_dac2_peripheral_aresetn 1 1 6 460 800 970 810 1580 180 2500J 3850 3020 3210 3520 +preplace netloc rst_dac3_peripheral_aresetn 1 2 5 1110 2560 1460 4060 2350J 3920 3110 3220 3540 +preplace netloc rst_ps8_0_99M_peripheral_aresetn 1 0 7 50 1480 340 790 1040 510 1500 190 2370 3860 2960 3550 3580 +preplace netloc usp_rf_data_converter_0_clk_adc2 1 1 7 490 3180 890 3260 1510 4090 2550 3900 3090 3230 3530 2250 3940 +preplace netloc usp_rf_data_converter_0_clk_dac2 1 1 7 480 1770 1060 1540 1590 210 2480 3870 3120 3250 3560 2280 3950 +preplace netloc usp_rf_data_converter_0_clk_dac3 1 2 6 1120 2120 1530 4070 2520 3930 3140 3240 3590 2260 3930 +preplace netloc vect2bits_16_0_dout0 1 7 2 3960 1280 N +preplace netloc vect2bits_16_0_dout1 1 7 2 3970 1310 N +preplace netloc vect2bits_16_0_dout2 1 7 2 3990 1340 N +preplace netloc vect2bits_16_0_dout3 1 7 2 4000 1370 N +preplace netloc vect2bits_16_0_dout4 1 7 2 4010 1400 N +preplace netloc vect2bits_16_0_dout5 1 7 2 NJ 1450 4370 +preplace netloc vect2bits_16_0_dout6 1 7 2 NJ 1470 4370 +preplace netloc vect2bits_16_0_dout7 1 7 2 NJ 1490 N +preplace netloc vect2bits_16_0_dout12 1 5 3 3160 3260 NJ 3260 3960 +preplace netloc vect2bits_16_0_dout13 1 6 2 3600 1290 3930 +preplace netloc vect2bits_16_0_dout14 1 3 5 1680 4100 NJ 4100 NJ 4100 N 4100 3980 +preplace netloc vect2bits_16_0_dout15 1 3 5 1690 4110 NJ 4110 NJ 4110 N 4110 3970 +preplace netloc xlconcat_0_dout 1 1 2 450 820 920 +preplace netloc xlconcat_1_dout 1 2 2 1120 70 1410 +preplace netloc xlconstant_0_dout 1 1 1 330 1910n +preplace netloc xlconstant_1_dout 1 1 1 330 1950n +preplace netloc xlconstant_2_dout 1 1 1 350 1990n +preplace netloc xlconstant_3_dout 1 1 1 340 1970n +preplace netloc xlconstant_4_dout 1 1 1 330 1680n +preplace netloc zynq_ultra_ps_e_0_pl_clk0 1 0 7 40 1460 330 230 910 40 1470 170 2540 3840 3100 3540 3570 +preplace netloc zynq_ultra_ps_e_0_pl_resetn0 1 3 2 1710 220 2350 +preplace netloc adc2_clk_0_1 1 6 3 3610 2270 N 2270 N +preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 1 1 330J 1800n +preplace netloc axi_dma_0_M_AXIS_MM2S 1 1 2 500 1620 890 +preplace netloc axi_dma_0_M_AXIS_MM2S1 1 2 1 1030 900n +preplace netloc axi_dma_0_M_AXI_MM2S 1 2 1 990 610n +preplace netloc axi_dma_0_M_AXI_MM2S1 1 2 1 1000 650n +preplace netloc axi_dma_0_M_AXI_S2MM 1 2 1 1020 630n +preplace netloc axi_dma_avg_M_AXI_S2MM 1 2 1 1070 310n +preplace netloc axi_dma_buf_M_AXI_S2MM 1 2 1 1060 490n +preplace netloc axi_dma_mr_M_AXI_S2MM 1 2 1 1050 670n +preplace netloc axi_interconnect_0_M00_AXI 1 1 5 400 -80 NJ -80 N -80 NJ -80 3010 +preplace netloc axi_interconnect_0_M08_AXI 1 5 2 N 670 3590 +preplace netloc axis_avg_buffer_0_m0_axis 1 4 1 2490 2750n +preplace netloc axis_avg_buffer_0_m1_axis 1 4 1 2510 2970n +preplace netloc axis_avg_buffer_0_m2_axis 1 4 1 2380 2570n +preplace netloc axis_avg_buffer_1_m0_axis 1 4 1 2530 2770n +preplace netloc axis_avg_buffer_1_m1_axis 1 4 1 2340 2990n +preplace netloc axis_avg_buffer_1_m2_axis 1 4 1 2360 3190n +preplace netloc axis_broadcaster_0_M00_AXIS 1 3 2 1700 3980 2330 +preplace netloc axis_broadcaster_0_M01_AXIS 1 4 1 2440 3230n +preplace netloc axis_broadcaster_1_M00_AXIS 1 3 2 1710 3990 2320 +preplace netloc axis_broadcaster_1_M01_AXIS 1 4 1 2400 3650n +preplace netloc axis_buffer_ddr_v1_0_m_axi 1 6 2 3650 3960 3930 +preplace netloc axis_cdcsync_v1_0_m0_axis 1 3 1 1490 1380n +preplace netloc axis_cdcsync_v1_0_m1_axis 1 3 1 1520 1640n +preplace netloc axis_cdcsync_v1_0_m2_axis 1 3 1 1410 1680n +preplace netloc axis_cdcsync_v1_0_m3_axis 1 3 1 1460 1700n +preplace netloc axis_cdcsync_v1_1_m0_axis 1 3 1 1430 1960n +preplace netloc axis_cdcsync_v1_1_m1_axis 1 3 1 1420 1980n +preplace netloc axis_cdcsync_v1_1_m2_axis 1 3 1 1410 2000n +preplace netloc axis_clk_cnvrt_avg_0_M_AXIS 1 1 5 420 4010 NJ 4010 NJ 4010 NJ 4010 2950 +preplace netloc axis_clk_cnvrt_avg_1_M_AXIS 1 1 5 430 4020 NJ 4020 NJ 4020 NJ 4020 2910 +preplace netloc axis_clock_converter_0_M_AXIS 1 6 1 3510 3620n +preplace netloc axis_dwidth_converter_0_M_AXIS 1 5 2 3160 3600 3500 +preplace netloc axis_readout_v2_0_m0_axis 1 3 2 1410 3140 2470 +preplace netloc axis_readout_v2_0_m1_axis 1 3 1 1410 3150n +preplace netloc axis_readout_v2_1_m0_axis 1 3 2 1550 3300 2450 +preplace netloc axis_readout_v2_1_m1_axis 1 3 1 1410 3380n +preplace netloc axis_register_slice_0_M_AXIS 1 2 1 N 3090 +preplace netloc axis_register_slice_1_M_AXIS 1 2 1 880 3260n +preplace netloc axis_register_slice_2_M_AXIS 1 5 2 N 1610 3520 +preplace netloc axis_register_slice_3_M_AXIS 1 5 2 N 1750 3510 +preplace netloc axis_register_slice_4_M_AXIS 1 5 2 3010 1810 N +preplace netloc axis_register_slice_5_M_AXIS 1 5 2 3020 1830 N +preplace netloc axis_register_slice_6_M_AXIS 1 5 2 3030 1850 N +preplace netloc axis_register_slice_7_M_AXIS 1 5 2 3040 1870 N +preplace netloc axis_register_slice_8_M_AXIS 1 5 2 3050 1890 N +preplace netloc axis_signal_gen_v6_0_m_axis 1 4 1 2490 1440n +preplace netloc axis_signal_gen_v6_1_m_axis 1 4 1 2490 1700n +preplace netloc axis_signal_gen_v6_2_m_axis 1 4 1 2400 1870n +preplace netloc axis_signal_gen_v6_3_m_axis 1 4 1 2400 2010n +preplace netloc axis_signal_gen_v6_4_m_axis 1 4 1 2420 2150n +preplace netloc axis_signal_gen_v6_5_m_axis 1 4 1 2440 2290n +preplace netloc axis_signal_gen_v6_6_m_axis 1 4 1 2470 2430n +preplace netloc axis_switch_0_M00_AXIS 1 3 1 1570 1210n +preplace netloc axis_switch_0_M01_AXIS 1 3 1 1560 1230n +preplace netloc axis_switch_0_M02_AXIS 1 3 1 1550 1250n +preplace netloc axis_switch_0_M03_AXIS 1 3 1 1540 1270n +preplace netloc axis_switch_0_M04_AXIS 1 3 1 1480 1290n +preplace netloc axis_switch_0_M05_AXIS 1 3 1 1450 1310n +preplace netloc axis_switch_0_M06_AXIS 1 3 1 1440 1330n +preplace netloc axis_switch_avg_M00_AXIS 1 1 5 390 4000 NJ 4000 NJ 4000 NJ 4000 2920 +preplace netloc axis_switch_buf_M00_AXIS 1 1 5 380 4030 NJ 4030 NJ 4030 NJ 4030 2940 +preplace netloc axis_switch_ddr_M00_AXIS 1 5 1 3130 3660n +preplace netloc axis_switch_mr_M00_AXIS 1 5 1 3070 3320n +preplace netloc axis_tproc64x32_x8_0_m0_axis 1 1 2 470 1630 880 +preplace netloc axis_tproc64x32_x8_0_m1_axis 1 2 3 940 80 1440 70 2560J +preplace netloc axis_tproc64x32_x8_0_m2_axis 1 2 1 1010 1360n +preplace netloc axis_tproc64x32_x8_0_m3_axis 1 2 1 990 1380n +preplace netloc axis_tproc64x32_x8_0_m4_axis 1 2 1 980 1400n +preplace netloc axis_tproc64x32_x8_0_m5_axis 1 2 1 960 1420n +preplace netloc axis_tproc64x32_x8_0_m6_axis 1 2 1 950 1440n +preplace netloc axis_tproc64x32_x8_0_m7_axis 1 2 1 940 1460n +preplace netloc axis_tproc64x32_x8_0_m8_axis 1 2 1 930 1480n +preplace netloc dac2_clk_0_1 1 6 3 3620 2240 N 2240 N +preplace netloc ddr4_0_C0_DDR4 1 8 1 N 3720 +preplace netloc default_sysclk_c0_300mhz_1 1 7 2 4020J 3660 4370 +preplace netloc mr_buffer_et_0_m00_axis 1 1 6 420 -70 N -70 N -70 N -70 N -70 3500 +preplace netloc ps8_0_axi_periph_M01_AXI 1 1 5 410 -60 NJ -60 NJ -60 NJ -60 3000 +preplace netloc ps8_0_axi_periph_M02_AXI 1 3 3 1690 90 NJ 90 2910 +preplace netloc ps8_0_axi_periph_M03_AXI 1 3 3 1670 30 NJ 30 2930 +preplace netloc ps8_0_axi_periph_M04_AXI 1 3 3 1680 40 NJ 40 2920 +preplace netloc ps8_0_axi_periph_M05_AXI 1 3 3 1620 -30 NJ -30 3080 +preplace netloc ps8_0_axi_periph_M06_AXI 1 1 5 430 50 NJ 50 N 50 NJ 50 2940 +preplace netloc ps8_0_axi_periph_M07_AXI 1 2 4 1110 -50 NJ -50 NJ -50 3150 +preplace netloc ps8_0_axi_periph_M09_AXI 1 3 3 1600 -40 NJ -40 3140 +preplace netloc ps8_0_axi_periph_M10_AXI 1 3 3 1610 -20 NJ -20 3120 +preplace netloc ps8_0_axi_periph_M11_AXI 1 3 3 1630 -10 NJ -10 3110 +preplace netloc ps8_0_axi_periph_M12_AXI 1 3 3 1640 20 NJ 20 3090 +preplace netloc ps8_0_axi_periph_M13_AXI 1 0 6 30 60 NJ 60 NJ 60 NJ 60 NJ 60 3060 +preplace netloc ps8_0_axi_periph_M14_AXI 1 3 3 1660 80 NJ 80 2990 +preplace netloc ps8_0_axi_periph_M15_AXI 1 2 4 1080 100 NJ 100 NJ 100 2980 +preplace netloc ps8_0_axi_periph_M16_AXI 1 2 4 1090 110 NJ 110 NJ 110 2970 +preplace netloc ps8_0_axi_periph_M17_AXI 1 4 2 2560 3560 2980 +preplace netloc ps8_0_axi_periph_M18_AXI 1 4 2 2570 3570 2970 +preplace netloc ps8_0_axi_periph_M19_AXI 1 1 5 460 90 NJ 90 1590J 120 NJ 120 2960 +preplace netloc ps8_0_axi_periph_M20_AXI 1 1 5 470 120 NJ 120 1580J 130 NJ 130 2950 +preplace netloc ps8_0_axi_periph_M21_AXI 1 1 5 500 130 N 130 1500 140 2570 70 3160 +preplace netloc ps8_0_axi_periph_M22_AXI 1 5 2 N 950 3550 +preplace netloc ps8_0_axi_periph_M23_AXI 1 4 2 2580 3600 2990 +preplace netloc ps8_0_axi_periph_M24_AXI 1 4 2 2580 3580 2930 +preplace netloc ps8_0_axi_periph_M25_AXI 1 5 1 3060 1010n +preplace netloc ps8_0_axi_periph_M26_AXI 1 2 4 1100 4040 N 4040 N 4040 3000 +preplace netloc smartconnect_0_M00_AXI 1 3 1 1410 280n +preplace netloc smartconnect_0_M00_AXI1 1 7 1 4010 3770n +preplace netloc sysref_in_0_1 1 6 3 3650 2210 4000 2150 N +preplace netloc usp_rf_data_converter_0_m20_axis 1 1 7 360 0 NJ 0 N 0 NJ 0 NJ 0 N 0 3950 +preplace netloc usp_rf_data_converter_0_m22_axis 1 1 7 370 10 NJ 10 N 10 NJ 10 NJ 10 N 10 3940 +preplace netloc usp_rf_data_converter_0_vout20 1 7 2 3990 1810 N +preplace netloc usp_rf_data_converter_0_vout21 1 7 2 4000 1840 N +preplace netloc usp_rf_data_converter_0_vout22 1 7 2 4010 1870 N +preplace netloc usp_rf_data_converter_0_vout23 1 7 2 4020 1900 N +preplace netloc usp_rf_data_converter_0_vout30 1 7 2 4030 1930 N +preplace netloc usp_rf_data_converter_0_vout31 1 7 2 4020 1960 N +preplace netloc usp_rf_data_converter_0_vout32 1 7 2 N 1990 N +preplace netloc vin20_0_1 1 6 3 3630 2220 N 2220 4370 +preplace netloc vin22_0_1 1 6 3 3640 2230 4020 2180 N +preplace netloc zynq_ultra_ps_e_0_M_AXI_HPM0_FPD 1 4 1 2390 190n +preplace netloc zynq_ultra_ps_e_0_M_AXI_HPM1_FPD 1 4 3 2320 3590 N 3590 3520 +levelinfo -pg 1 0 200 720 1280 2030 2770 3370 3800 4200 4430 +pagesize -pg 1 -db -bbox -sgen -140 -110 4650 4120 +" +} + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/firmware/zcu216/src/bd_2022-1.tcl b/firmware/zcu216/src/bd_2022-1.tcl new file mode 100644 index 0000000..46d24c8 --- /dev/null +++ b/firmware/zcu216/src/bd_2022-1.tcl @@ -0,0 +1,2799 @@ + +################################################################ +# This is a generated script based on design: d_1 +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2022.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source d_1_script.tcl + + +# The design that will be created by this Tcl script contains the following +# module references: +# vect2bits_16 + +# Please add the sources of those modules before sourcing this Tcl script. + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu49dr-ffvf1760-2-e + set_property BOARD_PART xilinx.com:zcu216:part0:2.0 [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name d_1 + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_bram_ctrl:4.1\ +xilinx.com:ip:blk_mem_gen:8.4\ +xilinx.com:ip:axi_dma:7.1\ +xilinx.com:ip:axi_intc:4.1\ +xilinx.com:ip:smartconnect:1.0\ +user.org:user:axis_avg_buffer:1.1\ +xilinx.com:ip:axis_broadcaster:1.1\ +user.org:user:axis_buffer_ddr_v1:1.0\ +user.org:user:axis_cdcsync_v1:1.0\ +xilinx.com:ip:axis_clock_converter:1.1\ +xilinx.com:ip:axis_dwidth_converter:1.1\ +user.org:user:axis_readout_v2:1.0\ +xilinx.com:ip:axis_register_slice:1.1\ +user.org:user:axis_set_reg:1.0\ +user.org:user:axis_signal_gen_v6:1.0\ +xilinx.com:ip:axis_switch:1.1\ +user.org:user:axis_tproc64x32_x8:1.0\ +xilinx.com:ip:ddr4:2.2\ +user.org:user:mr_buffer_et:1.1\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:usp_rf_data_converter:2.6\ +xilinx.com:ip:xlconcat:2.1\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:zynq_ultra_ps_e:3.4\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 1 +if { $bCheckModules == 1 } { + set list_check_mods "\ +vect2bits_16\ +" + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set adc2_clk_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc2_clk_0 ] + + set dac2_clk_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac2_clk_0 ] + + set ddr4_sdram_c0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram_c0 ] + + set default_sysclk_c0_300mhz [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 default_sysclk_c0_300mhz ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {300000000} \ + ] $default_sysclk_c0_300mhz + + set sysref_in_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0 sysref_in_0 ] + + set vin20_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin20_0 ] + + set vin22_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin22_0 ] + + set vout0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout0 ] + + set vout1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout1 ] + + set vout2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout2 ] + + set vout3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout3 ] + + set vout4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout4 ] + + set vout5 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout5 ] + + set vout6 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout6 ] + + + # Create ports + set PMOD0_0_LS [ create_bd_port -dir O PMOD0_0_LS ] + set PMOD0_1_LS [ create_bd_port -dir O PMOD0_1_LS ] + set PMOD0_2_LS [ create_bd_port -dir O PMOD0_2_LS ] + set PMOD0_3_LS [ create_bd_port -dir O PMOD0_3_LS ] + set PMOD0_4_LS [ create_bd_port -dir O PMOD0_4_LS ] + set PMOD0_5_LS [ create_bd_port -dir O PMOD0_5_LS ] + set PMOD0_6_LS [ create_bd_port -dir O PMOD0_6_LS ] + set PMOD0_7_LS [ create_bd_port -dir O PMOD0_7_LS ] + set PMOD1_0_LS [ create_bd_port -dir I PMOD1_0_LS ] + + # Create instance: axi_bram_ctrl_0, and set properties + set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {64} \ + CONFIG.SINGLE_PORT_BRAM {1} \ + ] $axi_bram_ctrl_0 + + # Create instance: axi_bram_ctrl_0_bram, and set properties + set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] + set_property -dict [ list \ + CONFIG.Byte_Size {8} \ + CONFIG.EN_SAFETY_CKT {false} \ + CONFIG.Enable_32bit_Address {true} \ + CONFIG.Enable_B {Use_ENB_Pin} \ + CONFIG.Memory_Type {True_Dual_Port_RAM} \ + CONFIG.Port_B_Clock {100} \ + CONFIG.Port_B_Enable_Rate {100} \ + CONFIG.Port_B_Write_Rate {50} \ + CONFIG.Read_Width_B {64} \ + CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ + CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \ + CONFIG.Use_Byte_Write_Enable {true} \ + CONFIG.Use_RSTA_Pin {true} \ + CONFIG.Use_RSTB_Pin {true} \ + CONFIG.Write_Width_B {64} \ + CONFIG.use_bram_block {BRAM_Controller} \ + ] $axi_bram_ctrl_0_bram + + # Create instance: axi_dma_avg, and set properties + set axi_dma_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_avg ] + set_property -dict [ list \ + CONFIG.c_include_mm2s {0} \ + CONFIG.c_include_s2mm {1} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_avg + + # Create instance: axi_dma_buf, and set properties + set axi_dma_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_buf ] + set_property -dict [ list \ + CONFIG.c_include_mm2s {0} \ + CONFIG.c_include_s2mm {1} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_buf + + # Create instance: axi_dma_gen, and set properties + set axi_dma_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_gen ] + set_property -dict [ list \ + CONFIG.c_include_s2mm {0} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_gen + + # Create instance: axi_dma_mr, and set properties + set axi_dma_mr [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_mr ] + set_property -dict [ list \ + CONFIG.c_include_mm2s {0} \ + CONFIG.c_include_s2mm {1} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_mr + + # Create instance: axi_dma_tproc, and set properties + set axi_dma_tproc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_tproc ] + set_property -dict [ list \ + CONFIG.c_include_s2mm {1} \ + CONFIG.c_include_sg {0} \ + CONFIG.c_sg_length_width {26} \ + ] $axi_dma_tproc + + # Create instance: axi_intc_0, and set properties + set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ] + set_property -dict [ list \ + CONFIG.C_IRQ_CONNECTION {1} \ + ] $axi_intc_0 + + # Create instance: axi_smc, and set properties + set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] + set_property -dict [ list \ + CONFIG.NUM_SI {6} \ + ] $axi_smc + + # Create instance: axi_smc_1, and set properties + set axi_smc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc_1 ] + + # Create instance: axis_avg_buffer_0, and set properties + set axis_avg_buffer_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.1 axis_avg_buffer_0 ] + set_property -dict [ list \ + CONFIG.N_AVG {14} \ + ] $axis_avg_buffer_0 + + # Create instance: axis_avg_buffer_1, and set properties + set axis_avg_buffer_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_avg_buffer:1.1 axis_avg_buffer_1 ] + set_property -dict [ list \ + CONFIG.N_AVG {14} \ + ] $axis_avg_buffer_1 + + # Create instance: axis_broadcaster_0, and set properties + set axis_broadcaster_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 axis_broadcaster_0 ] + set_property -dict [ list \ + CONFIG.HAS_TREADY {0} \ + ] $axis_broadcaster_0 + + # Create instance: axis_broadcaster_1, and set properties + set axis_broadcaster_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 axis_broadcaster_1 ] + set_property -dict [ list \ + CONFIG.HAS_TREADY {0} \ + ] $axis_broadcaster_1 + + # Create instance: axis_buffer_ddr_v1_0, and set properties + set axis_buffer_ddr_v1_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_buffer_ddr_v1:1.0 axis_buffer_ddr_v1_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.TARGET_SLAVE_BASE_ADDR {0x00000000} \ + ] $axis_buffer_ddr_v1_0 + + # Create instance: axis_cdcsync_v1_0, and set properties + set axis_cdcsync_v1_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_cdcsync_v1:1.0 axis_cdcsync_v1_0 ] + set_property -dict [ list \ + CONFIG.B {160} \ + CONFIG.N {4} \ + ] $axis_cdcsync_v1_0 + + # Create instance: axis_cdcsync_v1_1, and set properties + set axis_cdcsync_v1_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_cdcsync_v1:1.0 axis_cdcsync_v1_1 ] + set_property -dict [ list \ + CONFIG.B {160} \ + CONFIG.N {4} \ + ] $axis_cdcsync_v1_1 + + # Create instance: axis_clk_cnvrt_avg_0, and set properties + set axis_clk_cnvrt_avg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_0 ] + + # Create instance: axis_clk_cnvrt_avg_1, and set properties + set axis_clk_cnvrt_avg_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_1 ] + + # Create instance: axis_clock_converter_0, and set properties + set axis_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clock_converter_0 ] + + # Create instance: axis_dwidth_converter_0, and set properties + set axis_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_converter_0 ] + set_property -dict [ list \ + CONFIG.M_TDATA_NUM_BYTES {32} \ + ] $axis_dwidth_converter_0 + + # Create instance: axis_readout_v2_0, and set properties + set axis_readout_v2_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_0 ] + + # Create instance: axis_readout_v2_1, and set properties + set axis_readout_v2_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_readout_v2:1.0 axis_readout_v2_1 ] + + # Create instance: axis_register_slice_0, and set properties + set axis_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_0 ] + + # Create instance: axis_register_slice_1, and set properties + set axis_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_1 ] + + # Create instance: axis_register_slice_2, and set properties + set axis_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_2 ] + + # Create instance: axis_register_slice_3, and set properties + set axis_register_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_3 ] + + # Create instance: axis_register_slice_4, and set properties + set axis_register_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_4 ] + + # Create instance: axis_register_slice_5, and set properties + set axis_register_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_5 ] + + # Create instance: axis_register_slice_6, and set properties + set axis_register_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_6 ] + + # Create instance: axis_register_slice_7, and set properties + set axis_register_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_7 ] + + # Create instance: axis_register_slice_8, and set properties + set axis_register_slice_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_8 ] + + # Create instance: axis_set_reg_0, and set properties + set axis_set_reg_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_set_reg:1.0 axis_set_reg_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {160} \ + ] $axis_set_reg_0 + + # Create instance: axis_signal_gen_v6_0, and set properties + set axis_signal_gen_v6_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_0 ] + + # Create instance: axis_signal_gen_v6_1, and set properties + set axis_signal_gen_v6_1 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_1 ] + + # Create instance: axis_signal_gen_v6_2, and set properties + set axis_signal_gen_v6_2 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_2 ] + + # Create instance: axis_signal_gen_v6_3, and set properties + set axis_signal_gen_v6_3 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_3 ] + + # Create instance: axis_signal_gen_v6_4, and set properties + set axis_signal_gen_v6_4 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_4 ] + + # Create instance: axis_signal_gen_v6_5, and set properties + set axis_signal_gen_v6_5 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_5 ] + + # Create instance: axis_signal_gen_v6_6, and set properties + set axis_signal_gen_v6_6 [ create_bd_cell -type ip -vlnv user.org:user:axis_signal_gen_v6:1.0 axis_signal_gen_v6_6 ] + + # Create instance: axis_switch_avg, and set properties + set axis_switch_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_avg ] + set_property -dict [ list \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_avg + + # Create instance: axis_switch_buf, and set properties + set axis_switch_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_buf ] + set_property -dict [ list \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_buf + + # Create instance: axis_switch_ddr, and set properties + set axis_switch_ddr [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_ddr ] + set_property -dict [ list \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_ddr + + # Create instance: axis_switch_gen, and set properties + set axis_switch_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_gen ] + set_property -dict [ list \ + CONFIG.DECODER_REG {1} \ + CONFIG.NUM_MI {7} \ + CONFIG.NUM_SI {1} \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_gen + + # Create instance: axis_switch_mr, and set properties + set axis_switch_mr [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_mr ] + set_property -dict [ list \ + CONFIG.ROUTING_MODE {1} \ + ] $axis_switch_mr + + # Create instance: axis_tproc64x32_x8_0, and set properties + set axis_tproc64x32_x8_0 [ create_bd_cell -type ip -vlnv user.org:user:axis_tproc64x32_x8:1.0 axis_tproc64x32_x8_0 ] + set_property -dict [ list \ + CONFIG.DMEM_N {12} \ + CONFIG.PMEM_N {20} \ + ] $axis_tproc64x32_x8_0 + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [ list \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.C0.CS_WIDTH {2} \ + CONFIG.C0.DDR4_AxiAddressWidth {32} \ + CONFIG.C0.DDR4_AxiDataWidth {256} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3} \ + CONFIG.C0.DDR4_Clamshell {true} \ + CONFIG.C0.DDR4_DataWidth {32} \ + CONFIG.C0.DDR4_InputClockPeriod {3334} \ + CONFIG.C0.DDR4_MemoryPart {MT40A1G8WE-075E} \ + CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk_c0_300mhz} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c0} \ + ] $ddr4_0 + + # Create instance: mr_buffer_et_0, and set properties + set mr_buffer_et_0 [ create_bd_cell -type ip -vlnv user.org:user:mr_buffer_et:1.1 mr_buffer_et_0 ] + set_property -dict [ list \ + CONFIG.B {32} \ + CONFIG.N {10} \ + ] $mr_buffer_et_0 + + # Create instance: ps8_0_axi_periph, and set properties + set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] + set_property -dict [ list \ + CONFIG.NUM_MI {27} \ + ] $ps8_0_axi_periph + + # Create instance: rst_100, and set properties + set rst_100 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_100 ] + + # Create instance: rst_adc, and set properties + set rst_adc [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc ] + set_property -dict [ list \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $rst_adc + + # Create instance: rst_dac2, and set properties + set rst_dac2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac2 ] + set_property -dict [ list \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $rst_dac2 + + # Create instance: rst_dac3, and set properties + set rst_dac3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac3 ] + set_property -dict [ list \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $rst_dac3 + + # Create instance: rst_ddr4, and set properties + set rst_ddr4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ddr4 ] + + # Create instance: usp_rf_data_converter_0, and set properties + set usp_rf_data_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.6 usp_rf_data_converter_0 ] + set_property -dict [ list \ + CONFIG.ADC2_Clock_Dist {0} \ + CONFIG.ADC2_Fabric_Freq {307.200} \ + CONFIG.ADC2_Outclk_Freq {307.200} \ + CONFIG.ADC2_PLL_Enable {true} \ + CONFIG.ADC2_Refclk_Freq {245.760} \ + CONFIG.ADC2_Sampling_Rate {2.4576} \ + CONFIG.ADC3_Enable {0} \ + CONFIG.ADC3_Fabric_Freq {0.0} \ + CONFIG.ADC_Coarse_Mixer_Freq20 {3} \ + CONFIG.ADC_Coarse_Mixer_Freq22 {3} \ + CONFIG.ADC_Coarse_Mixer_Freq30 {0} \ + CONFIG.ADC_Data_Width20 {8} \ + CONFIG.ADC_Decimation_Mode20 {1} \ + CONFIG.ADC_Decimation_Mode22 {1} \ + CONFIG.ADC_Decimation_Mode30 {0} \ + CONFIG.ADC_Mixer_Type20 {1} \ + CONFIG.ADC_Mixer_Type22 {1} \ + CONFIG.ADC_Mixer_Type30 {3} \ + CONFIG.ADC_OBS22 {false} \ + CONFIG.ADC_OBS31 {false} \ + CONFIG.ADC_OBS32 {false} \ + CONFIG.ADC_OBS33 {false} \ + CONFIG.ADC_RESERVED_1_20 {false} \ + CONFIG.ADC_RESERVED_1_21 {false} \ + CONFIG.ADC_RESERVED_1_22 {false} \ + CONFIG.ADC_RESERVED_1_23 {false} \ + CONFIG.ADC_RESERVED_1_30 {false} \ + CONFIG.ADC_RESERVED_1_31 {false} \ + CONFIG.ADC_RESERVED_1_32 {false} \ + CONFIG.ADC_RESERVED_1_33 {false} \ + CONFIG.ADC_Slice00_Enable {false} \ + CONFIG.ADC_Slice20_Enable {true} \ + CONFIG.ADC_Slice21_Enable {false} \ + CONFIG.ADC_Slice22_Enable {true} \ + CONFIG.ADC_Slice30_Enable {false} \ + CONFIG.DAC2_Clock_Dist {1} \ + CONFIG.DAC2_Fabric_Freq {430.080} \ + CONFIG.DAC2_Outclk_Freq {430.080} \ + CONFIG.DAC2_PLL_Enable {true} \ + CONFIG.DAC2_Refclk_Freq {245.760} \ + CONFIG.DAC2_Sampling_Rate {6.88128} \ + CONFIG.DAC3_Clock_Source {6} \ + CONFIG.DAC3_Fabric_Freq {430.080} \ + CONFIG.DAC3_Outclk_Freq {430.080} \ + CONFIG.DAC3_PLL_Enable {true} \ + CONFIG.DAC3_Refclk_Freq {245.760} \ + CONFIG.DAC3_Sampling_Rate {6.88128} \ + CONFIG.DAC_Coarse_Mixer_Freq20 {3} \ + CONFIG.DAC_Coarse_Mixer_Freq21 {3} \ + CONFIG.DAC_Coarse_Mixer_Freq22 {3} \ + CONFIG.DAC_Coarse_Mixer_Freq23 {3} \ + CONFIG.DAC_Coarse_Mixer_Freq30 {3} \ + CONFIG.DAC_Coarse_Mixer_Freq31 {3} \ + CONFIG.DAC_Coarse_Mixer_Freq32 {3} \ + CONFIG.DAC_Interpolation_Mode20 {1} \ + CONFIG.DAC_Interpolation_Mode21 {1} \ + CONFIG.DAC_Interpolation_Mode22 {1} \ + CONFIG.DAC_Interpolation_Mode23 {1} \ + CONFIG.DAC_Interpolation_Mode30 {1} \ + CONFIG.DAC_Interpolation_Mode31 {1} \ + CONFIG.DAC_Interpolation_Mode32 {1} \ + CONFIG.DAC_Mixer_Type20 {1} \ + CONFIG.DAC_Mixer_Type21 {1} \ + CONFIG.DAC_Mixer_Type22 {1} \ + CONFIG.DAC_Mixer_Type23 {1} \ + CONFIG.DAC_Mixer_Type30 {1} \ + CONFIG.DAC_Mixer_Type31 {1} \ + CONFIG.DAC_Mixer_Type32 {1} \ + CONFIG.DAC_Mode20 {3} \ + CONFIG.DAC_Mode21 {3} \ + CONFIG.DAC_Mode22 {3} \ + CONFIG.DAC_Mode23 {3} \ + CONFIG.DAC_Mode30 {3} \ + CONFIG.DAC_Mode31 {3} \ + CONFIG.DAC_Mode32 {3} \ + CONFIG.DAC_Slice20_Enable {true} \ + CONFIG.DAC_Slice21_Enable {true} \ + CONFIG.DAC_Slice22_Enable {true} \ + CONFIG.DAC_Slice23_Enable {true} \ + CONFIG.DAC_Slice30_Enable {true} \ + CONFIG.DAC_Slice31_Enable {true} \ + CONFIG.DAC_Slice32_Enable {true} \ + CONFIG.DAC_Slice33_Enable {false} \ + CONFIG.DAC_VOP_Mode {0} \ + ] $usp_rf_data_converter_0 + + # Create instance: vect2bits_16_0, and set properties + set block_name vect2bits_16 + set block_cell_name vect2bits_16_0 + if { [catch {set vect2bits_16_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $vect2bits_16_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + + # Create instance: xlconcat_1, and set properties + set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ] + set_property -dict [ list \ + CONFIG.NUM_PORTS {6} \ + ] $xlconcat_1 + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {64} \ + ] $xlconstant_0 + + # Create instance: xlconstant_1, and set properties + set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {1} \ + CONFIG.CONST_WIDTH {1} \ + ] $xlconstant_1 + + # Create instance: xlconstant_2, and set properties + set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {8} \ + ] $xlconstant_2 + + # Create instance: xlconstant_3, and set properties + set xlconstant_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_3 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {1} \ + ] $xlconstant_3 + + # Create instance: xlconstant_4, and set properties + set xlconstant_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_4 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {12} \ + ] $xlconstant_4 + + # Create instance: zynq_ultra_ps_e_0, and set properties + set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.4 zynq_ultra_ps_e_0 ] + set_property -dict [ list \ + CONFIG.CAN0_BOARD_INTERFACE {custom} \ + CONFIG.CAN1_BOARD_INTERFACE {custom} \ + CONFIG.CSU_BOARD_INTERFACE {custom} \ + CONFIG.DP_BOARD_INTERFACE {custom} \ + CONFIG.GEM0_BOARD_INTERFACE {custom} \ + CONFIG.GEM1_BOARD_INTERFACE {custom} \ + CONFIG.GEM2_BOARD_INTERFACE {custom} \ + CONFIG.GEM3_BOARD_INTERFACE {custom} \ + CONFIG.GPIO_BOARD_INTERFACE {custom} \ + CONFIG.IIC0_BOARD_INTERFACE {custom} \ + CONFIG.IIC1_BOARD_INTERFACE {custom} \ + CONFIG.NAND_BOARD_INTERFACE {custom} \ + CONFIG.PCIE_BOARD_INTERFACE {custom} \ + CONFIG.PJTAG_BOARD_INTERFACE {custom} \ + CONFIG.PMU_BOARD_INTERFACE {custom} \ + CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \ + CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ + CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ + CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ + CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {1} \ + CONFIG.PSU_IMPORT_BOARD_PRESET {} \ + CONFIG.PSU_MIO_0_DIRECTION {out} \ + CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_0_POLARITY {Default} \ + CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_0_SLEW {fast} \ + CONFIG.PSU_MIO_10_DIRECTION {inout} \ + CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_10_POLARITY {Default} \ + CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_10_SLEW {fast} \ + CONFIG.PSU_MIO_11_DIRECTION {inout} \ + CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_11_POLARITY {Default} \ + CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_11_SLEW {fast} \ + CONFIG.PSU_MIO_12_DIRECTION {out} \ + CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_12_POLARITY {Default} \ + CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_12_SLEW {fast} \ + CONFIG.PSU_MIO_13_DIRECTION {inout} \ + CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_13_POLARITY {Default} \ + CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_13_SLEW {fast} \ + CONFIG.PSU_MIO_14_DIRECTION {inout} \ + CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_14_POLARITY {Default} \ + CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_14_SLEW {fast} \ + CONFIG.PSU_MIO_15_DIRECTION {inout} \ + CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_15_POLARITY {Default} \ + CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_15_SLEW {fast} \ + CONFIG.PSU_MIO_16_DIRECTION {inout} \ + CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_16_POLARITY {Default} \ + CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_16_SLEW {fast} \ + CONFIG.PSU_MIO_17_DIRECTION {inout} \ + CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_17_POLARITY {Default} \ + CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_17_SLEW {fast} \ + CONFIG.PSU_MIO_18_DIRECTION {in} \ + CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_18_POLARITY {Default} \ + CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_18_SLEW {fast} \ + CONFIG.PSU_MIO_19_DIRECTION {out} \ + CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_19_POLARITY {Default} \ + CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_19_SLEW {fast} \ + CONFIG.PSU_MIO_1_DIRECTION {inout} \ + CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_1_POLARITY {Default} \ + CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_1_SLEW {fast} \ + CONFIG.PSU_MIO_20_DIRECTION {inout} \ + CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_20_POLARITY {Default} \ + CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_20_SLEW {fast} \ + CONFIG.PSU_MIO_21_DIRECTION {inout} \ + CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_21_POLARITY {Default} \ + CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_21_SLEW {fast} \ + CONFIG.PSU_MIO_22_DIRECTION {inout} \ + CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_22_POLARITY {Default} \ + CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_22_SLEW {fast} \ + CONFIG.PSU_MIO_23_DIRECTION {inout} \ + CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_23_POLARITY {Default} \ + CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_23_SLEW {fast} \ + CONFIG.PSU_MIO_24_DIRECTION {inout} \ + CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_24_POLARITY {Default} \ + CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_24_SLEW {fast} \ + CONFIG.PSU_MIO_25_DIRECTION {inout} \ + CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_25_POLARITY {Default} \ + CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_25_SLEW {fast} \ + CONFIG.PSU_MIO_26_DIRECTION {inout} \ + CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_26_POLARITY {Default} \ + CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_26_SLEW {fast} \ + CONFIG.PSU_MIO_27_DIRECTION {inout} \ + CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_27_POLARITY {Default} \ + CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_27_SLEW {fast} \ + CONFIG.PSU_MIO_28_DIRECTION {inout} \ + CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_28_POLARITY {Default} \ + CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_28_SLEW {fast} \ + CONFIG.PSU_MIO_29_DIRECTION {inout} \ + CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_29_POLARITY {Default} \ + CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_29_SLEW {fast} \ + CONFIG.PSU_MIO_2_DIRECTION {inout} \ + CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_2_POLARITY {Default} \ + CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_2_SLEW {fast} \ + CONFIG.PSU_MIO_30_DIRECTION {inout} \ + CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_30_POLARITY {Default} \ + CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_30_SLEW {fast} \ + CONFIG.PSU_MIO_31_DIRECTION {inout} \ + CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_31_POLARITY {Default} \ + CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_31_SLEW {fast} \ + CONFIG.PSU_MIO_32_DIRECTION {out} \ + CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_32_POLARITY {Default} \ + CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_32_SLEW {fast} \ + CONFIG.PSU_MIO_33_DIRECTION {out} \ + CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_33_POLARITY {Default} \ + CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_33_SLEW {fast} \ + CONFIG.PSU_MIO_34_DIRECTION {out} \ + CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_34_POLARITY {Default} \ + CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_34_SLEW {fast} \ + CONFIG.PSU_MIO_35_DIRECTION {out} \ + CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_35_POLARITY {Default} \ + CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_35_SLEW {fast} \ + CONFIG.PSU_MIO_36_DIRECTION {out} \ + CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_36_POLARITY {Default} \ + CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_36_SLEW {fast} \ + CONFIG.PSU_MIO_37_DIRECTION {out} \ + CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_37_POLARITY {Default} \ + CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_37_SLEW {fast} \ + CONFIG.PSU_MIO_38_DIRECTION {inout} \ + CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_38_POLARITY {Default} \ + CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_38_SLEW {fast} \ + CONFIG.PSU_MIO_39_DIRECTION {inout} \ + CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_39_POLARITY {Default} \ + CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_39_SLEW {fast} \ + CONFIG.PSU_MIO_3_DIRECTION {inout} \ + CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_3_POLARITY {Default} \ + CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_3_SLEW {fast} \ + CONFIG.PSU_MIO_40_DIRECTION {inout} \ + CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_40_POLARITY {Default} \ + CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_40_SLEW {fast} \ + CONFIG.PSU_MIO_41_DIRECTION {inout} \ + CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_41_POLARITY {Default} \ + CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_41_SLEW {fast} \ + CONFIG.PSU_MIO_42_DIRECTION {inout} \ + CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_42_POLARITY {Default} \ + CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_42_SLEW {fast} \ + CONFIG.PSU_MIO_43_DIRECTION {inout} \ + CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_43_POLARITY {Default} \ + CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_43_SLEW {fast} \ + CONFIG.PSU_MIO_44_DIRECTION {inout} \ + CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_44_POLARITY {Default} \ + CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_44_SLEW {fast} \ + CONFIG.PSU_MIO_45_DIRECTION {in} \ + CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_45_POLARITY {Default} \ + CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_45_SLEW {fast} \ + CONFIG.PSU_MIO_46_DIRECTION {inout} \ + CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_46_POLARITY {Default} \ + CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_46_SLEW {fast} \ + CONFIG.PSU_MIO_47_DIRECTION {inout} \ + CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_47_POLARITY {Default} \ + CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_47_SLEW {fast} \ + CONFIG.PSU_MIO_48_DIRECTION {inout} \ + CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_48_POLARITY {Default} \ + CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_48_SLEW {fast} \ + CONFIG.PSU_MIO_49_DIRECTION {inout} \ + CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_49_POLARITY {Default} \ + CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_49_SLEW {fast} \ + CONFIG.PSU_MIO_4_DIRECTION {inout} \ + CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_4_POLARITY {Default} \ + CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_4_SLEW {fast} \ + CONFIG.PSU_MIO_50_DIRECTION {inout} \ + CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_50_POLARITY {Default} \ + CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_50_SLEW {fast} \ + CONFIG.PSU_MIO_51_DIRECTION {out} \ + CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_51_POLARITY {Default} \ + CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_51_SLEW {fast} \ + CONFIG.PSU_MIO_52_DIRECTION {in} \ + CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_52_POLARITY {Default} \ + CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_52_SLEW {fast} \ + CONFIG.PSU_MIO_53_DIRECTION {in} \ + CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_53_POLARITY {Default} \ + CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_53_SLEW {fast} \ + CONFIG.PSU_MIO_54_DIRECTION {inout} \ + CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_54_POLARITY {Default} \ + CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_54_SLEW {fast} \ + CONFIG.PSU_MIO_55_DIRECTION {in} \ + CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_55_POLARITY {Default} \ + CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_55_SLEW {fast} \ + CONFIG.PSU_MIO_56_DIRECTION {inout} \ + CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_56_POLARITY {Default} \ + CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_56_SLEW {fast} \ + CONFIG.PSU_MIO_57_DIRECTION {inout} \ + CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_57_POLARITY {Default} \ + CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_57_SLEW {fast} \ + CONFIG.PSU_MIO_58_DIRECTION {out} \ + CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_58_POLARITY {Default} \ + CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_58_SLEW {fast} \ + CONFIG.PSU_MIO_59_DIRECTION {inout} \ + CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_59_POLARITY {Default} \ + CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_59_SLEW {fast} \ + CONFIG.PSU_MIO_5_DIRECTION {out} \ + CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_5_POLARITY {Default} \ + CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_5_SLEW {fast} \ + CONFIG.PSU_MIO_60_DIRECTION {inout} \ + CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_60_POLARITY {Default} \ + CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_60_SLEW {fast} \ + CONFIG.PSU_MIO_61_DIRECTION {inout} \ + CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_61_POLARITY {Default} \ + CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_61_SLEW {fast} \ + CONFIG.PSU_MIO_62_DIRECTION {inout} \ + CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_62_POLARITY {Default} \ + CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_62_SLEW {fast} \ + CONFIG.PSU_MIO_63_DIRECTION {inout} \ + CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_63_POLARITY {Default} \ + CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_63_SLEW {fast} \ + CONFIG.PSU_MIO_64_DIRECTION {out} \ + CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_64_POLARITY {Default} \ + CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_64_SLEW {fast} \ + CONFIG.PSU_MIO_65_DIRECTION {out} \ + CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_65_POLARITY {Default} \ + CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_65_SLEW {fast} \ + CONFIG.PSU_MIO_66_DIRECTION {out} \ + CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_66_POLARITY {Default} \ + CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_66_SLEW {fast} \ + CONFIG.PSU_MIO_67_DIRECTION {out} \ + CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_67_POLARITY {Default} \ + CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_67_SLEW {fast} \ + CONFIG.PSU_MIO_68_DIRECTION {out} \ + CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_68_POLARITY {Default} \ + CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_68_SLEW {fast} \ + CONFIG.PSU_MIO_69_DIRECTION {out} \ + CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_69_POLARITY {Default} \ + CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_69_SLEW {fast} \ + CONFIG.PSU_MIO_6_DIRECTION {out} \ + CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_6_POLARITY {Default} \ + CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_6_SLEW {fast} \ + CONFIG.PSU_MIO_70_DIRECTION {in} \ + CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_70_POLARITY {Default} \ + CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_70_SLEW {fast} \ + CONFIG.PSU_MIO_71_DIRECTION {in} \ + CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_71_POLARITY {Default} \ + CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_71_SLEW {fast} \ + CONFIG.PSU_MIO_72_DIRECTION {in} \ + CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_72_POLARITY {Default} \ + CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_72_SLEW {fast} \ + CONFIG.PSU_MIO_73_DIRECTION {in} \ + CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_73_POLARITY {Default} \ + CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_73_SLEW {fast} \ + CONFIG.PSU_MIO_74_DIRECTION {in} \ + CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_74_POLARITY {Default} \ + CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_74_SLEW {fast} \ + CONFIG.PSU_MIO_75_DIRECTION {in} \ + CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_75_POLARITY {Default} \ + CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_75_SLEW {fast} \ + CONFIG.PSU_MIO_76_DIRECTION {out} \ + CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_76_POLARITY {Default} \ + CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_76_SLEW {fast} \ + CONFIG.PSU_MIO_77_DIRECTION {inout} \ + CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_77_POLARITY {Default} \ + CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_77_SLEW {fast} \ + CONFIG.PSU_MIO_7_DIRECTION {out} \ + CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_7_POLARITY {Default} \ + CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_7_SLEW {fast} \ + CONFIG.PSU_MIO_8_DIRECTION {inout} \ + CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_8_POLARITY {Default} \ + CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_8_SLEW {fast} \ + CONFIG.PSU_MIO_9_DIRECTION {inout} \ + CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_9_POLARITY {Default} \ + CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_9_SLEW {fast} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {\ +Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\ +SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI\ +Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART\ +0#UART 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO1\ +MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU\ +GPO 2#PMU GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1\ +MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB\ +0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\ +3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ + CONFIG.PSU_MIO_TREE_SIGNALS {\ +sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#gpio0[20]#gpio0[21]#gpio0[22]#gpio0[23]#gpio0[24]#gpio0[25]#gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#gpio1[30]#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \ + CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \ + CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_SMC_CYCLE_T0 {NA} \ + CONFIG.PSU_SMC_CYCLE_T1 {NA} \ + CONFIG.PSU_SMC_CYCLE_T2 {NA} \ + CONFIG.PSU_SMC_CYCLE_T3 {NA} \ + CONFIG.PSU_SMC_CYCLE_T4 {NA} \ + CONFIG.PSU_SMC_CYCLE_T5 {NA} \ + CONFIG.PSU_SMC_CYCLE_T6 {NA} \ + CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ + CONFIG.PSU_VALUE_SILVERSION {3} \ + CONFIG.PSU__ACPU0__POWER__ON {1} \ + CONFIG.PSU__ACPU1__POWER__ON {1} \ + CONFIG.PSU__ACPU2__POWER__ON {1} \ + CONFIG.PSU__ACPU3__POWER__ON {1} \ + CONFIG.PSU__ACTUAL__IP {1} \ + CONFIG.PSU__ACT_DDR_FREQ_MHZ {1049.999878} \ + CONFIG.PSU__AFI0_COHERENCY {0} \ + CONFIG.PSU__AFI1_COHERENCY {0} \ + CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \ + CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.999756} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {524.999939} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1066} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.999878} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {63} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {63} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {27} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {10} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {320} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.999878} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {0} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \ + CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {524.999939} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.999908} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999992} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.999908} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.999756} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.999977} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.999908} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.499969} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.999977} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {90} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.499969} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.999954} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999996} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ + CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ + CONFIG.PSU__CSU_COHERENCY {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__DDRC__ADDR_MIRROR {0} \ + CONFIG.PSU__DDRC__AL {0} \ + CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \ + CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ + CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ + CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ + CONFIG.PSU__DDRC__CL {15} \ + CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ + CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ + CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \ + CONFIG.PSU__DDRC__CWL {11} \ + CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ + CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ + CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ + CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ + CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ + CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ + CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ + CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ + CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ + CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ + CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ + CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ + CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ + CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ + CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ + CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ + CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ + CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ + CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ + CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ + CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ + CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ + CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ + CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ + CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ + CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ + CONFIG.PSU__DDRC__ECC {Disabled} \ + CONFIG.PSU__DDRC__ECC_SCRUB {0} \ + CONFIG.PSU__DDRC__ENABLE {1} \ + CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \ + CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \ + CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ + CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ + CONFIG.PSU__DDRC__EN_2ND_CLK {0} \ + CONFIG.PSU__DDRC__FGRM {1X} \ + CONFIG.PSU__DDRC__FREQ_MHZ {1} \ + CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \ + CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__LP_ASR {manual normal} \ + CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ + CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ + CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ + CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ + CONFIG.PSU__DDRC__PLL_BYPASS {0} \ + CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ + CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \ + CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \ + CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \ + CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ + CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ + CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ + CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ + CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ + CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ + CONFIG.PSU__DDRC__T_FAW {30.0} \ + CONFIG.PSU__DDRC__T_RAS_MIN {33} \ + CONFIG.PSU__DDRC__T_RC {46.5} \ + CONFIG.PSU__DDRC__T_RCD {15} \ + CONFIG.PSU__DDRC__T_RP {15} \ + CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ + CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \ + CONFIG.PSU__DDRC__VREF {1} \ + CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ + CONFIG.PSU__DDR_QOS_ENABLE {0} \ + CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \ + CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \ + CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \ + CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \ + CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \ + CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.000} \ + CONFIG.PSU__DEVICE_TYPE {RFSOC} \ + CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {0} \ + CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {0} \ + CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__DLL__ISUSED {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \ + CONFIG.PSU__ENET0__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET0__PTP__ENABLE {0} \ + CONFIG.PSU__ENET0__TSU__ENABLE {0} \ + CONFIG.PSU__ENET1__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET1__PTP__ENABLE {0} \ + CONFIG.PSU__ENET1__TSU__ENABLE {0} \ + CONFIG.PSU__ENET2__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET2__PTP__ENABLE {0} \ + CONFIG.PSU__ENET2__TSU__ENABLE {0} \ + CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ + CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ + CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ + CONFIG.PSU__ENET3__PTP__ENABLE {0} \ + CONFIG.PSU__ENET3__TSU__ENABLE {0} \ + CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \ + CONFIG.PSU__EN_EMIO_TRACE {0} \ + CONFIG.PSU__EP__IP {0} \ + CONFIG.PSU__EXPAND__CORESIGHT {0} \ + CONFIG.PSU__EXPAND__FPD_SLAVES {0} \ + CONFIG.PSU__EXPAND__GIC {0} \ + CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \ + CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \ + CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ + CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999985} \ + CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {99.999985} \ + CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__FPGA_PL0_ENABLE {1} \ + CONFIG.PSU__FPGA_PL1_ENABLE {0} \ + CONFIG.PSU__FPGA_PL2_ENABLE {0} \ + CONFIG.PSU__FPGA_PL3_ENABLE {0} \ + CONFIG.PSU__FP__POWER__ON {1} \ + CONFIG.PSU__FTM__CTI_IN_0 {0} \ + CONFIG.PSU__FTM__CTI_IN_1 {0} \ + CONFIG.PSU__FTM__CTI_IN_2 {0} \ + CONFIG.PSU__FTM__CTI_IN_3 {0} \ + CONFIG.PSU__FTM__CTI_OUT_0 {0} \ + CONFIG.PSU__FTM__CTI_OUT_1 {0} \ + CONFIG.PSU__FTM__CTI_OUT_2 {0} \ + CONFIG.PSU__FTM__CTI_OUT_3 {0} \ + CONFIG.PSU__FTM__GPI {0} \ + CONFIG.PSU__FTM__GPO {0} \ + CONFIG.PSU__GEM0_COHERENCY {0} \ + CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM1_COHERENCY {0} \ + CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM2_COHERENCY {0} \ + CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM3_COHERENCY {0} \ + CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM__TSU__ENABLE {0} \ + CONFIG.PSU__GEN_IPI_0__MASTER {APU} \ + CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \ + CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \ + CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \ + CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ + CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ + CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__GPIO_EMIO_WIDTH {1} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {