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Intro

A small chess engine that I hope to submit to one of the efabless / Google shuttle tapeout events.

Aim is to speak UCI over a UART, or some simpler protocol, then to generate scored moves back over the UART. It will be an exercise to learn both cototb for testing and yosys/openlanes for synthesis to gates.

Milestones

  • Parse FEN string
  • CI build with Cocotb
  • Generate psudolegal moves from position, passing edge cases from https://gist.github.com/peterellisjones/8c46c28141c162d1d8a0f0badbc9cff9 and others
  • Validates moves from generator match pychess
  • UCI wrapper to allow expose move generator result as perft fixed for depth=0
  • UART-2-UCI layer for perft over USB serial in hardware
  • move stack / generate next board from position + move / perft variable depth
  • eval?

Tests

Test bench implemented with cocotb and cocotb-test:

$ sudo apt install python3.10-venv python3.10-dev iverilog
$ python3 -m venv venv
$ . venv/bin/activate
$ pip install -r requirements.txt
$ SIM=icarus pytest -o log_cli=True tests

OR

$ docker build .

To build/view waves

$ WAVES=1 pytest -o log_cli=True tests
$ gtkwave sim_build/fen_decode.fst gtksaves/test_fen_decode.gtkw

Hardware

To build for different boards/simulators, use fusesoc, it is included in the requirements.txt above:

$ pip install -r requirements.txt
$ fusesoc library add fpgachess .
$ fusesoc list cores

To see all supported targets:

$ fusesoc core show shuckc:fpgachess:uci

To run a particular target:

$ fusesoc run --target=lint shuckc:fpgachess:uci
$ fusesoc run --target=orangecrab_r0.2 shuckc:fpgachess:uci

Test suites


About

This is a stupid idea - pure hardware FPGA chess engine

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