Add RISC-V for XuanTie C908 #115
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…for some instructions The <w>-specifier allows having 32-bit and 64-bit versions of instructions in one class which saves some work. While parsing, mnemonics are compared first to find the matching class for an instruction. Since add<w> would not be identified as an add-instruction, we first must replace <w> (if present) by the corresponding regex pattern and call re.match(srcline, pattern) afterward. A generic solution for parsing specifiers which modify the mnemonic could be a future task.
The method is set as an attribute during each call of parser() atm. This assignment should happen at a proper place.
…asses from a list
* prep for BranchLoop
* WARN: Not well tested (dry-run OK)
…functions - Add comprehensive save_regs/restore_regs macros to all 8 Kyber basemul RVV functions to enable maximum register availability for SLOTHY optimization - Update _example.py to use RISC_V.BranchLoop for all RVV optimization runners - Generate optimized versions of 5 new Kyber basemul RVV functions using C908 target - Standardize stack allocation (120 bytes) across all RVV functions - Enable advanced loop optimization capabilities for RISC-V vector code This change ensures RVV functions are ready for optimal SLOTHY processing with enhanced register renaming and software pipelining support.
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Adds an implementation for the RISC-V architecture on the XuanTie C908, initially supporting the RV32/64I and RV32/64M ISA extensions, with plans to include RV32/64V in the future. This PR also introduces a new structure for organizing files, classes, and related components. Additionally, it includes a mechanism to reduce the effort required to add new instructions by dynamically generating instruction classes from a simple list. Overall, the changes also aim to streamline the process of adding new architectures, making it faster and more straightforward.