AArch64: Add support for repeated .<dt> specifiers #316
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- Add support for using repeated `.<dt*>` in instruction patterns, while keeping backward compatibility. - Introduce a new static method `_replace_duplicate_mnemonicKey()` in AArch64Instruction to handle duplicate specifiers during parsing and writing. Signed-off-by: willieyz <willie.zhao@chelpis.com>
…ring parsing.
- This commit enforcing that all `.<dt*>` are equal during parsing.
- Here is an example:
- For pattern: `smlsl <Vd>.<dt0>, <Va>.<dt1>, <Vb>.<dt1>`
- When parsing:
- `smlsl v6.4s, v7.4h, v8.4h` -> Passed,
- `smlsl v6.4s, v7.4h, v8.4s` -> Failed,
return `"Inconsistent data type: 4h vs 4s"`
- `smlsl v6.4h, v7.4h, v8.4h` -> Failed,
return `"Inconsistent dt: <dt1>"`
Signed-off-by: willieyz <willie.zhao@chelpis.com>
Signed-off-by: willieyz <willie.zhao@chelpis.com>
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Resolves: AArch64: Don't force numbering of
<dt>annotations in instruction pattern #219Add support for using repeated
.<dt>in instruction patterns, while keeping backward compatibility.This PR solve problem by:
_replace_duplicate_mnemonicKey()inAArch64Instructionto handle duplicate<dt>specifiers during parsing and writing..<dt*>are equal during parsing.smlsl <Vd>.<dt0>, <Va>.<dt1>, <Vb>.<dt1>smlsl v6.4s, v7.4h, v8.4h-> Passed,smlsl v6.4s, v7.4h, v8.4s-> Failed,return
return "Inconsistent dataname: <dt0> vs <dt1> for datatype: 4s"smlsl v6.4s, v7.4h, v8.16b-> Failed,return
"Inconsistent datatype: 4h vs 16b for dataname: <dt1>"