Problem on the SRAM enable logic of the 4081-U1B part

[SONIC3D]

Thanks for your nice project. I'm reading your schematic yesterday, with an SNES cart mapping doc on "http://gatchan.net/uploads/Consoles/SNES/Flashcard/SNES_MemMap.txt"
and "https://wiki.superfamicom.org/schematics-ports-and-pinouts"

I found the SRAM mapping is different from what the doc described. So I create this issue to request your help on confirming if it's intended or just small fault on drawing schematic.

(All address pin name below is referencing to CartSlot pin name, not the NET name in your KiCAD project.)

HiROM mode

With this doc the SRAM enable logic equation in "HiROM mode" is:

!SRAM_CE = (!A15 & BA5 & A14 & A13) & (!nCART & nRESET)
or 
!SRAM_CE = (!BA6 & BA5 & A14 & A13) & (!nCART & nRESET)

and the SRAM should be mapped to segment $20-$3F and $A0-$BF.

When JP1-JP5 shorted with pin1-pin2.(Enable HiROM mode)
Focusing on the part (!A15 & BA5 & A14 & A13) or (!BA6 & BA5 & A14 & A13):

• 4071-U2A part is corresponding to (!A15 and !BA6) which is OK for general adaption.
• 4081-U1A part is corresponding to (A14 & A13).
• But for 4081-U1B part, the equation in your schematic is (BA4 & BA5). Which contains an additional BA4.
  This makes the SRAM be mapped to segment $30-$3F and $B0-$BF. Which is different from the known doc.

LoROM mode

With this doc the SRAM enable logic equation in "LoROM mode" is:

!SRAM_CE = (Vcc & BA5 & BA4 & !A15) & (!nCART & nRESET)
or 
!SRAM_CE = (BA6 & BA5 & BA4 & !A15) & (!nCART & nRESET)

and the SRAM should be mapped to segment $70-$7D and $F0-$FF.

When JP1-JP5 shorted with pin3-pin2.(Enable LoROM mode)
Focusing on the part (Vcc & BA5 & BA4 & !A15) or (BA6 & BA5 & BA4 & !A15):

• JP4 connected to /CART filtered segment $7E-$7F. That's ok.
• 4081-U1A part is corresponding to (!A15). That's ok.
• But for 4081-U1B part the equation in your schematic is (BA6 & BA5). So the BA4 is missed in expression.
  This makes the SRAM be mapped to segment $60-$7D and $E0-$FF. Which is different from the known doc.

My modification

If the above problem is indeed mistake in drawing. I think the modification can be like below.

The solution A uses the expression (BA6 & BA5 & BA4 & !A15) in LoROM mode. It requires an additional AND gate. So I added an 4081. Or it can be achieved with an 3-input AND gate with BA4 BA5 BA6 as input.

The solution A uses the expression (Vcc & BA5 & BA4 & !A15), so the Vcc can be skipped in AND. The additional AND gate component can be saved. The jumper can also be moved to right of the 4081, thus the +5V Vcc can be skipped for HiROM mode.
(Note: I'm still not clear if (Vcc & BA5 & BA4 & !A15) can be apply to all game, as I think this constraint is more wide than adding BA6. I'm not sure if it will interfere other logic in the corresponding page. I'm not that familiar with SNES.)

[SONIC3D]

And pin1 of JP1 currently connects the /CART.
So in HiROM mode(JP1-JP14 all connect pin1-pin2). The ROM data bus will always output on /RD, even on SRAM address range like $3F:$6000. It should interfere the SRAM output.

I think the pin1 of JP1 should connect to logic output of:

(!nCART and BA6) or (!nCART and !BA6 and A15)
Simplified:
!nCART and (BA6 or (!BA6 and A15))

That's 2 AND gates and 1 OR gate.

So that the following mapping is achieved:

	SNES 00:8000-FFFF <---	ROM 008000-00FFFF     // 0000-7FFF is not mapped. Only 8000-FFFF.  (!BA6 and A15)
	SNES 01:8000-FFFF <---	ROM 018000-01FFFF      // Similar, 10000-17FFF is not mapped
	SNES 02:8000-FFFF <---	ROM 028000-02FFFF
	SNES 03:8000-FFFF <---	ROM 038000-03FFFF
	...
	SNES 3E:8000-FFFF <---	ROM 3E8000-3EFFFF
	SNES 3F:8000-FFFF <---	ROM 3F8000-3FFFFF

	SNES 40:0000-FFFF <---	ROM 000000-00FFFF    // 0000-FFFF are all mapped. (BA6)
	SNES 41:0000-FFFF <---	ROM 010000-01FFFF
	SNES 42:0000-FFFF <---	ROM 020000-02FFFF
	SNES 43:0000-FFFF <---	ROM 030000-03FFFF
	... etc

	SNES 7E:0000-FFFF <---	System RAM                    // Here /Cart is high
	SNES 7F:0000-FFFF <---	System RAM                    // Here /Cart is high

	//same thing in banks 80-FF
	//except FE-FF holds more ROM instead of System RAM

	SNES 80:8000-FFFF <---	ROM 008000-00FFFF     // 0000-7FFF is not mapped
	SNES 81:8000-FFFF <---	ROM 018000-01FFFF      // Similar, 10000-17FFF is not mapped
	SNES 82:8000-FFFF <---	ROM 028000-02FFFF
	SNES 83:8000-FFFF <---	ROM 038000-03FFFF
	...
	SNES BE:8000-FFFF <---	ROM 3E8000-3EFFFF
	SNES BF:8000-FFFF <---	ROM 3F8000-3FFFFF

	SNES C0:0000-FFFF <---	ROM 000000-00FFFF
	SNES C1:0000-FFFF <---	ROM 010000-01FFFF
	SNES C2:0000-FFFF <---	ROM 020000-02FFFF
	SNES C3:0000-FFFF <---	ROM 030000-03FFFF
	... etc

	SNES FE:0000-FFFF <---	ROM 3E0000-3EFFFF
	SNES FF:0000-FFFF <---	ROM 3F0000-3FFFFF