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dojyorinfpistm
dojyorin
authored and
fpistm
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Add H562R(G-I)V, H563R(G-I)V and H573RIV.
1 parent 739acb7 commit 1b98ba7

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‎README.md‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -586,11 +586,14 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
586586
| :green_heart: | STM32H503RB | Generic Board | *2.7.0* | |
587587
| :green_heart: | STM32H562RGT | WeAct H562RGT | *2.9.0* | |
588588
| :green_heart: | STM32H562RGT<br>STM32H562RIT | Generic Board | *2.9.0* | |
589+
| :yellow_heart: | STM32H562RGV<br>STM32H562RIV | Generic Board | **2.13.0** | |
589590
| :green_heart: | STM32H563IIKxQ | Generic Board | *2.6.0* | |
590-
| :green_heart: | STM32H563RG<br>STM32H563RI | Generic Board | *2.8.1* | |
591+
| :green_heart: | STM32H563RGT<br>STM32H563RIT | Generic Board | *2.8.1* | |
592+
| :yellow_heart: | STM32H563RGV<br>STM32H563RIV | Generic Board | **2.13.0** | |
591593
| :green_heart: | STM32H563ZG<br>STM32H563ZI | Generic Board | *2.6.0* | |
592594
| :green_heart: | STM32H573IIKxQ | Generic Board | *2.6.0* | |
593-
| :green_heart: | STM32H573RI | Generic Board | *2.8.1* | |
595+
| :green_heart: | STM32H573RIT | Generic Board | *2.8.1* | |
596+
| :yellow_heart: | STM32H573RIV | Generic Board | **2.13.0** | |
594597
| :green_heart: | STM32H573ZI | Generic Board | *2.6.0* | |
595598

596599
### Generic STM32H7 boards

‎boards.txt‎

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9346,6 +9346,15 @@ GenH5.menu.pnum.GENERIC_H562RGTX.build.product_line=STM32H562xx
93469346
GenH5.menu.pnum.GENERIC_H562RGTX.build.variant=STM32H5xx/H562R(G-I)T
93479347
GenH5.menu.pnum.GENERIC_H562RGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H562.svd
93489348

9349+
# Generic H562RGVx
9350+
GenH5.menu.pnum.GENERIC_H562RGVX=Generic H562RGVx
9351+
GenH5.menu.pnum.GENERIC_H562RGVX.upload.maximum_size=1048576
9352+
GenH5.menu.pnum.GENERIC_H562RGVX.upload.maximum_data_size=655360
9353+
GenH5.menu.pnum.GENERIC_H562RGVX.build.board=GENERIC_H562RGVX
9354+
GenH5.menu.pnum.GENERIC_H562RGVX.build.product_line=STM32H562xx
9355+
GenH5.menu.pnum.GENERIC_H562RGVX.build.variant=STM32H5xx/H562R(G-I)V
9356+
GenH5.menu.pnum.GENERIC_H562RGVX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H562.svd
9357+
93499358
# Generic H562RITx
93509359
GenH5.menu.pnum.GENERIC_H562RITX=Generic H562RITx
93519360
GenH5.menu.pnum.GENERIC_H562RITX.upload.maximum_size=2097152
@@ -9355,6 +9364,15 @@ GenH5.menu.pnum.GENERIC_H562RITX.build.product_line=STM32H562xx
93559364
GenH5.menu.pnum.GENERIC_H562RITX.build.variant=STM32H5xx/H562R(G-I)T
93569365
GenH5.menu.pnum.GENERIC_H562RITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H562.svd
93579366

9367+
# Generic H562RIVx
9368+
GenH5.menu.pnum.GENERIC_H562RIVX=Generic H562RIVx
9369+
GenH5.menu.pnum.GENERIC_H562RIVX.upload.maximum_size=2097152
9370+
GenH5.menu.pnum.GENERIC_H562RIVX.upload.maximum_data_size=655360
9371+
GenH5.menu.pnum.GENERIC_H562RIVX.build.board=GENERIC_H562RIVX
9372+
GenH5.menu.pnum.GENERIC_H562RIVX.build.product_line=STM32H562xx
9373+
GenH5.menu.pnum.GENERIC_H562RIVX.build.variant=STM32H5xx/H562R(G-I)V
9374+
GenH5.menu.pnum.GENERIC_H562RIVX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H562.svd
9375+
93589376
# Generic H563IIKxQ
93599377
GenH5.menu.pnum.GENERIC_H563IIKXQ=Generic H563IIKxQ
93609378
GenH5.menu.pnum.GENERIC_H563IIKXQ.upload.maximum_size=2097152
@@ -9373,6 +9391,15 @@ GenH5.menu.pnum.GENERIC_H563RGTX.build.product_line=STM32H563xx
93739391
GenH5.menu.pnum.GENERIC_H563RGTX.build.variant=STM32H5xx/H563R(G-I)T_H573RIT
93749392
GenH5.menu.pnum.GENERIC_H563RGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H563.svd
93759393

9394+
# Generic H563RGVx
9395+
GenH5.menu.pnum.GENERIC_H563RGVX=Generic H563RGVx
9396+
GenH5.menu.pnum.GENERIC_H563RGVX.upload.maximum_size=1048576
9397+
GenH5.menu.pnum.GENERIC_H563RGVX.upload.maximum_data_size=655360
9398+
GenH5.menu.pnum.GENERIC_H563RGVX.build.board=GENERIC_H563RGVX
9399+
GenH5.menu.pnum.GENERIC_H563RGVX.build.product_line=STM32H563xx
9400+
GenH5.menu.pnum.GENERIC_H563RGVX.build.variant=STM32H5xx/H563R(G-I)V_H573RIV
9401+
GenH5.menu.pnum.GENERIC_H563RGVX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H563.svd
9402+
93769403
# Generic H563RITx
93779404
GenH5.menu.pnum.GENERIC_H563RITX=Generic H563RITx
93789405
GenH5.menu.pnum.GENERIC_H563RITX.upload.maximum_size=2097152
@@ -9382,6 +9409,15 @@ GenH5.menu.pnum.GENERIC_H563RITX.build.product_line=STM32H563xx
93829409
GenH5.menu.pnum.GENERIC_H563RITX.build.variant=STM32H5xx/H563R(G-I)T_H573RIT
93839410
GenH5.menu.pnum.GENERIC_H563RITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H563.svd
93849411

9412+
# Generic H563RIVx
9413+
GenH5.menu.pnum.GENERIC_H563RIVX=Generic H563RIVx
9414+
GenH5.menu.pnum.GENERIC_H563RIVX.upload.maximum_size=2097152
9415+
GenH5.menu.pnum.GENERIC_H563RIVX.upload.maximum_data_size=655360
9416+
GenH5.menu.pnum.GENERIC_H563RIVX.build.board=GENERIC_H563RIVX
9417+
GenH5.menu.pnum.GENERIC_H563RIVX.build.product_line=STM32H563xx
9418+
GenH5.menu.pnum.GENERIC_H563RIVX.build.variant=STM32H5xx/H563R(G-I)V_H573RIV
9419+
GenH5.menu.pnum.GENERIC_H563RIVX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H563.svd
9420+
93859421
# Generic H563ZGTx
93869422
GenH5.menu.pnum.GENERIC_H563ZGTX=Generic H563ZGTx
93879423
GenH5.menu.pnum.GENERIC_H563ZGTX.upload.maximum_size=1048576
@@ -9418,6 +9454,15 @@ GenH5.menu.pnum.GENERIC_H573RITX.build.product_line=STM32H573xx
94189454
GenH5.menu.pnum.GENERIC_H573RITX.build.variant=STM32H5xx/H563R(G-I)T_H573RIT
94199455
GenH5.menu.pnum.GENERIC_H573RITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H573.svd
94209456

9457+
# Generic H573RIVx
9458+
GenH5.menu.pnum.GENERIC_H573RIVX=Generic H573RIVx
9459+
GenH5.menu.pnum.GENERIC_H573RIVX.upload.maximum_size=2097152
9460+
GenH5.menu.pnum.GENERIC_H573RIVX.upload.maximum_data_size=655360
9461+
GenH5.menu.pnum.GENERIC_H573RIVX.build.board=GENERIC_H573RIVX
9462+
GenH5.menu.pnum.GENERIC_H573RIVX.build.product_line=STM32H573xx
9463+
GenH5.menu.pnum.GENERIC_H573RIVX.build.variant=STM32H5xx/H563R(G-I)V_H573RIV
9464+
GenH5.menu.pnum.GENERIC_H573RIVX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H573.svd
9465+
94219466
# Generic H573ZITx
94229467
GenH5.menu.pnum.GENERIC_H573ZITX=Generic H573ZITx
94239468
GenH5.menu.pnum.GENERIC_H573ZITX.upload.maximum_size=2097152

‎variants/STM32H5xx/H562R(G-I)V/generic_clock.c‎

Lines changed: 88 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,94 @@
2020
*/
2121
WEAK void SystemClock_Config(void)
2222
{
23-
/* SystemClock_Config can be generated by STM32CubeMX */
24-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
23+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
24+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
25+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
26+
27+
/** Configure the main internal regulator output voltage
28+
*/
29+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
30+
31+
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
32+
33+
/** Initializes the RCC Oscillators according to the specified parameters
34+
* in the RCC_OscInitTypeDef structure.
35+
*/
36+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_HSI48
37+
| RCC_OSCILLATORTYPE_LSI;
38+
RCC_OscInitStruct.CSIState = RCC_CSI_ON;
39+
RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT;
40+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
41+
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
42+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
43+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI;
44+
RCC_OscInitStruct.PLL.PLLM = 2;
45+
RCC_OscInitStruct.PLL.PLLN = 250;
46+
RCC_OscInitStruct.PLL.PLLP = 2;
47+
RCC_OscInitStruct.PLL.PLLQ = 10;
48+
RCC_OscInitStruct.PLL.PLLR = 2;
49+
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1;
50+
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
51+
RCC_OscInitStruct.PLL.PLLFRACN = 0;
52+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
53+
Error_Handler();
54+
}
55+
56+
/** Initializes the CPU, AHB and APB buses clocks
57+
*/
58+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
59+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
60+
| RCC_CLOCKTYPE_PCLK3;
61+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
62+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
63+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
64+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
65+
RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
66+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
67+
Error_Handler();
68+
}
69+
70+
/** Configure the programming delay
71+
*/
72+
__HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2);
73+
74+
/** Initializes the peripherals clock
75+
*/
76+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_ADCDAC
77+
| RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB
78+
| RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2
79+
| RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI6;
80+
PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI;
81+
PeriphClkInitStruct.PLL2.PLL2M = 2;
82+
PeriphClkInitStruct.PLL2.PLL2N = 250;
83+
PeriphClkInitStruct.PLL2.PLL2P = 2;
84+
PeriphClkInitStruct.PLL2.PLL2Q = 15;
85+
PeriphClkInitStruct.PLL2.PLL2R = 4;
86+
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_1;
87+
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE;
88+
PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
89+
PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR;
90+
PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_CSI;
91+
PeriphClkInitStruct.PLL3.PLL3M = 2;
92+
PeriphClkInitStruct.PLL3.PLL3N = 125;
93+
PeriphClkInitStruct.PLL3.PLL3P = 2;
94+
PeriphClkInitStruct.PLL3.PLL3Q = 5;
95+
PeriphClkInitStruct.PLL3.PLL3R = 2;
96+
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_1;
97+
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE;
98+
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
99+
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;
100+
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q;
101+
PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R;
102+
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q;
103+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
104+
PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q;
105+
PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q;
106+
PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q;
107+
PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL3Q;
108+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
109+
Error_Handler();
110+
}
25111
}
26112

27113
#endif /* ARDUINO_GENERIC_* */

‎variants/STM32H5xx/H562R(G-I)V/ldscript.ld‎

Lines changed: 188 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,188 @@
1+
/*
2+
******************************************************************************
3+
**
4+
** @file : LinkerScript.ld
5+
**
6+
** @author : Auto-generated by STM32CubeIDE
7+
**
8+
** @brief : Linker script for STM32H562RIVx Device from STM32H5 series
9+
** 2048KBytes FLASH
10+
** 640KBytes RAM
11+
**
12+
** Set heap size, stack size and stack location according
13+
** to application requirements.
14+
**
15+
** Set memory bank area and size if external memory is used
16+
**
17+
** Target : STMicroelectronics STM32
18+
**
19+
** Distribution: The file is distributed as is, without any warranty
20+
** of any kind.
21+
**
22+
******************************************************************************
23+
** @attention
24+
**
25+
** Copyright (c) 2026 STMicroelectronics.
26+
** All rights reserved.
27+
**
28+
** This software is licensed under terms that can be found in the LICENSE file
29+
** in the root directory of this software component.
30+
** If no LICENSE file comes with this software, it is provided AS-IS.
31+
**
32+
******************************************************************************
33+
*/
34+
35+
/* Entry Point */
36+
ENTRY(Reset_Handler)
37+
38+
/* Highest address of the user mode stack */
39+
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
40+
_sstack = _estack - _Min_Stack_Size;
41+
42+
_Min_Heap_Size = 0x200; /* required amount of heap */
43+
_Min_Stack_Size = 0x400; /* required amount of stack */
44+
45+
/* Memories definition */
46+
MEMORY
47+
{
48+
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
49+
FLASH (rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
50+
}
51+
52+
/* Sections */
53+
SECTIONS
54+
{
55+
/* The startup code into "FLASH" Rom type memory */
56+
.isr_vector :
57+
{
58+
. = ALIGN(4);
59+
KEEP(*(.isr_vector)) /* Startup code */
60+
. = ALIGN(4);
61+
} >FLASH
62+
63+
/* The program code and other data into "FLASH" Rom type memory */
64+
.text :
65+
{
66+
. = ALIGN(4);
67+
*(.text) /* .text sections (code) */
68+
*(.text*) /* .text* sections (code) */
69+
*(.glue_7) /* glue arm to thumb code */
70+
*(.glue_7t) /* glue thumb to arm code */
71+
*(.eh_frame)
72+
73+
KEEP (*(.init))
74+
KEEP (*(.fini))
75+
76+
. = ALIGN(4);
77+
_etext = .; /* define a global symbols at end of code */
78+
} >FLASH
79+
80+
/* Constant data into "FLASH" Rom type memory */
81+
.rodata :
82+
{
83+
. = ALIGN(4);
84+
*(.rodata) /* .rodata sections (constants, strings, etc.) */
85+
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
86+
. = ALIGN(4);
87+
} >FLASH
88+
89+
.ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
90+
{
91+
. = ALIGN(4);
92+
*(.ARM.extab* .gnu.linkonce.armextab.*)
93+
. = ALIGN(4);
94+
} >FLASH
95+
96+
.ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
97+
{
98+
. = ALIGN(4);
99+
__exidx_start = .;
100+
*(.ARM.exidx*)
101+
__exidx_end = .;
102+
. = ALIGN(4);
103+
} >FLASH
104+
105+
.preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
106+
{
107+
. = ALIGN(4);
108+
PROVIDE_HIDDEN (__preinit_array_start = .);
109+
KEEP (*(.preinit_array*))
110+
PROVIDE_HIDDEN (__preinit_array_end = .);
111+
. = ALIGN(4);
112+
} >FLASH
113+
114+
.init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
115+
{
116+
. = ALIGN(4);
117+
PROVIDE_HIDDEN (__init_array_start = .);
118+
KEEP (*(SORT(.init_array.*)))
119+
KEEP (*(.init_array*))
120+
PROVIDE_HIDDEN (__init_array_end = .);
121+
. = ALIGN(4);
122+
} >FLASH
123+
124+
.fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
125+
{
126+
. = ALIGN(4);
127+
PROVIDE_HIDDEN (__fini_array_start = .);
128+
KEEP (*(SORT(.fini_array.*)))
129+
KEEP (*(.fini_array*))
130+
PROVIDE_HIDDEN (__fini_array_end = .);
131+
. = ALIGN(4);
132+
} >FLASH
133+
134+
/* Used by the startup to initialize data */
135+
_sidata = LOADADDR(.data);
136+
137+
/* Initialized data sections into "RAM" Ram type memory */
138+
.data :
139+
{
140+
. = ALIGN(4);
141+
_sdata = .; /* create a global symbol at data start */
142+
*(.data) /* .data sections */
143+
*(.data*) /* .data* sections */
144+
*(.RamFunc) /* .RamFunc sections */
145+
*(.RamFunc*) /* .RamFunc* sections */
146+
147+
. = ALIGN(4);
148+
_edata = .; /* define a global symbol at data end */
149+
150+
} >RAM AT> FLASH
151+
152+
/* Uninitialized data section into "RAM" Ram type memory */
153+
. = ALIGN(4);
154+
.bss :
155+
{
156+
/* This is used by the startup in order to initialize the .bss section */
157+
_sbss = .; /* define a global symbol at bss start */
158+
__bss_start__ = _sbss;
159+
*(.bss)
160+
*(.bss*)
161+
*(COMMON)
162+
163+
. = ALIGN(4);
164+
_ebss = .; /* define a global symbol at bss end */
165+
__bss_end__ = _ebss;
166+
} >RAM
167+
168+
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
169+
._user_heap_stack :
170+
{
171+
. = ALIGN(8);
172+
PROVIDE ( end = . );
173+
PROVIDE ( _end = . );
174+
. = . + _Min_Heap_Size;
175+
. = . + _Min_Stack_Size;
176+
. = ALIGN(8);
177+
} >RAM
178+
179+
/* Remove information from the compiler libraries */
180+
/DISCARD/ :
181+
{
182+
libc.a ( * )
183+
libm.a ( * )
184+
libgcc.a ( * )
185+
}
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.ARM.attributes 0 : { *(.ARM.attributes) }
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}

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