Timer

A timer module with adjustable width.

Timer width can be adjusted via WIDTH parameter. Signal start acts as a synchronous reset, and sets remaining to init_val. Then the module counts down when enabled via en until remaining is zero. When zero is reached done is set and count down stops.

Modules are simulated with Icarus Verilog.

Some values for 100MHz clock:

Time	Minimum Width	Initial value
1 sec	27	d100_000_000
1 min	33	d6_000_000_000
1 hour	39	d360_000_000_000