Add support for RV32E extension in architecture tests

Enable architecture tests for RV32E with appropriate handling of the
reduced register set and ABI.

With this change, users can run tests for RV32E extension using the
following command:

make arch-test RISCV_DEVICE=E

Author: eleanorLYJ

tests/arch-test-target/constants.py

@@ -8,7 +8,9 @@
 
 misa_A = (1 << 0)
 misa_C = (1 << 2)
+misa_E = (1 << 4)
 misa_F = (1 << 5)
+misa_I = (1 << 8)
 misa_M = (1 << 12)
 
 config_temp = '''[RISCOF]

tests/arch-test-target/rv32emu/env/model_test.h

@@ -13,10 +13,17 @@
 /* clang-format on */
 
 // RV_COMPLIANCE_HALT
+#ifndef EXT_E
 #define RVMODEL_HALT \
     add a7, x0, 93;  \
     add a0, x0, 0;   \
     ecall
+#else
+#define RVMODEL_HALT \
+    add t0, x0, 93;  \
+    add a0, x0, 0;   \
+    ecall
+#endif
 
 #define RVMODEL_BOOT
 

tests/arch-test-target/rv32emu/riscof_rv32emu.py

@@ -86,7 +86,11 @@ def build(self, isa_yaml, platform_yaml):
         # will be useful in setting integer value in the compiler string (if not already hardcoded);
         self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32')
 
-        self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else 'ilp32 ')
+        if 'E' not in ispec['ISA']:
+            self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else 'ilp32 ')
+        else:
+            self.compile_cmd = self.compile_cmd+' -mabi='+('lp64e ' if 64 in ispec['supported_xlen'] else 'ilp32e ')
+            self.compile_cmd += '-D EXT_E '
 
     def runTests(self, testList):
         # Delete Makefile if it already exists.

tests/arch-test-target/sail_cSim/env/model_test.h

@@ -13,11 +13,19 @@
 /* clang-format on */
 
 // RV_COMPLIANCE_HALT
+#ifndef EXT_E
 #define RVMODEL_HALT   \
     li x1, 1;          \
     write_tohost:      \
     sw x1, tohost, t5; \
     j write_tohost;
+#else
+#define RVMODEL_HALT    \
+    li x1, 1;           \
+    write_tohost:       \
+    sw x1, tohost, x15; \
+    j write_tohost;
+#endif
 
 #define RVMODEL_BOOT
 

tests/arch-test-target/sail_cSim/riscof_sail_cSim.py

@@ -52,9 +52,15 @@ def build(self, isa_yaml, platform_yaml):
         ispec = utils.load_yaml(isa_yaml)['hart0']
         self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32')
         self.isa = 'rv' + self.xlen
-        self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else 'ilp32 ')
+        if 'E' not in ispec['ISA']:
+            self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else 'ilp32 ')
+        else:
+            self.compile_cmd = self.compile_cmd+' -mabi='+('lp64e ' if 64 in ispec['supported_xlen'] else 'ilp32e ')
+            self.compile_cmd += "-D EXT_E "
         if "I" in ispec["ISA"]:
             self.isa += 'i'
+        if "E" in ispec["ISA"]:
+            self.isa += 'e'
         if "M" in ispec["ISA"]:
             self.isa += 'm'
         if "C" in ispec["ISA"]:

tests/arch-test-target/setup.py

@@ -6,12 +6,18 @@
 def setup_testlist(riscv_device):
     # ISA config file path
     ispec = constants.root + '/rv32emu/rv32emu_isa.yaml'
-    misa = 0x40000100
-    ISA = 'RV32I'
+    misa = 0x40000000
+    ISA = 'RV32'
 
     if not riscv_device:
         raise AssertionError('There is not any ISA.')
 
+    if 'E' in riscv_device:
+        misa |= constants.misa_E
+        ISA += 'E'
+    else:
+        misa |= constants.misa_I
+        ISA += 'I'
     if 'M' in riscv_device:
         misa |= constants.misa_M
         ISA += 'M'