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RinHizakuraRinHizakura
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Use instruction-based emulation for debug mode
In debug mode(gdbstub), we'll need one instruction/cycle per step for trace. For such usecase, using the block-based emulation will be too expensive which slow down the execution. Switch to instruction-based emulation for debug mode.
1 parent f7fd15b commit d16ce4d

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4 files changed

+110
-68
lines changed

4 files changed

+110
-68
lines changed

‎src/emulate.c‎

Lines changed: 79 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -862,12 +862,9 @@ static block_t *block_find_or_translate(riscv_t *rv)
862862
block_translate(rv, next_blk);
863863

864864
optimize_constant(rv, next_blk);
865-
#if RV32_HAS(GDBSTUB)
866-
if (likely(!rv->debug_mode))
867-
#endif
868865
#if RV32_HAS(MOP_FUSION)
869-
/* macro operation fusion */
870-
match_pattern(rv, next_blk);
866+
/* macro operation fusion */
867+
match_pattern(rv, next_blk);
871868
#endif
872869

873870
#if !RV32_HAS(JIT)
@@ -958,7 +955,83 @@ static bool rv_has_plic_trap(riscv_t *rv)
958955
return ((rv->csr_sstatus & SSTATUS_SIE || !rv->priv_mode) &&
959956
(rv->csr_sip & rv->csr_sie));
960957
}
958+
959+
static void rv_check_interrupt(riscv_t *rv)
960+
{
961+
vm_attr_t *attr = PRIV(rv);
962+
/* check for any interrupt after every block/instruction emulation */
963+
if (peripheral_update_ctr-- == 0) {
964+
peripheral_update_ctr = 64;
965+
966+
u8250_check_ready(PRIV(rv)->uart);
967+
if (PRIV(rv)->uart->in_ready)
968+
emu_update_uart_interrupts(rv);
969+
}
970+
971+
if (ctr > attr->timer)
972+
rv->csr_sip |= RV_INT_STI;
973+
else
974+
rv->csr_sip &= ~RV_INT_STI;
975+
976+
if (rv_has_plic_trap(rv)) {
977+
uint32_t intr_applicable = rv->csr_sip & rv->csr_sie;
978+
uint8_t intr_idx = ilog2(intr_applicable);
979+
switch (intr_idx) {
980+
case (SUPERVISOR_SW_INTR & 0xf):
981+
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, SUPERVISOR_SW_INTR, 0);
982+
break;
983+
case (SUPERVISOR_TIMER_INTR & 0xf):
984+
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, SUPERVISOR_TIMER_INTR, 0);
985+
break;
986+
case (SUPERVISOR_EXTERNAL_INTR & 0xf):
987+
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, SUPERVISOR_EXTERNAL_INTR, 0);
988+
break;
989+
default:
990+
break;
991+
}
992+
}
993+
}
994+
#else
995+
static void rv_check_interrupt(riscv_t *rv)
996+
{
997+
return;
998+
}
999+
#endif
1000+
1001+
void rv_step_debug(void *arg)
1002+
{
1003+
assert(arg);
1004+
riscv_t *rv = arg;
1005+
1006+
rv_check_interrupt(rv);
1007+
1008+
retranslate:
1009+
/* fetch the next instruction */
1010+
rv_insn_t ir;
1011+
memset(&ir, 0, sizeof(rv_insn_t));
1012+
1013+
uint32_t insn = rv->io.mem_ifetch(rv, rv->PC);
1014+
#if RV32_HAS(SYSTEM)
1015+
if (!insn && need_retranslate) {
1016+
need_retranslate = false;
1017+
goto retranslate;
1018+
}
9611019
#endif
1020+
assert(insn);
1021+
1022+
/* decode the instruction */
1023+
if (!rv_decode(&ir, insn)) {
1024+
rv->compressed = is_compressed(insn);
1025+
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, ILLEGAL_INSN, insn);
1026+
return;
1027+
}
1028+
1029+
ir.impl = dispatch_table[ir.opcode];
1030+
ir.pc = rv->PC;
1031+
ir.next = NULL;
1032+
ir.impl(rv, &ir, rv->csr_cycle, rv->PC);
1033+
return;
1034+
}
9621035

9631036
void rv_step(void *arg)
9641037
{
@@ -973,40 +1046,7 @@ void rv_step(void *arg)
9731046

9741047
/* loop until hitting the cycle target */
9751048
while (rv->csr_cycle < cycles_target && !rv->halt) {
976-
#if RV32_HAS(SYSTEM) && !RV32_HAS(ELF_LOADER)
977-
/* check for any interrupt after every block emulation */
978-
979-
if (peripheral_update_ctr-- == 0) {
980-
peripheral_update_ctr = 64;
981-
982-
u8250_check_ready(PRIV(rv)->uart);
983-
if (PRIV(rv)->uart->in_ready)
984-
emu_update_uart_interrupts(rv);
985-
}
986-
987-
if (ctr > attr->timer)
988-
rv->csr_sip |= RV_INT_STI;
989-
else
990-
rv->csr_sip &= ~RV_INT_STI;
991-
992-
if (rv_has_plic_trap(rv)) {
993-
uint32_t intr_applicable = rv->csr_sip & rv->csr_sie;
994-
uint8_t intr_idx = ilog2(intr_applicable);
995-
switch (intr_idx) {
996-
case (SUPERVISOR_SW_INTR & 0xf):
997-
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, SUPERVISOR_SW_INTR, 0);
998-
break;
999-
case (SUPERVISOR_TIMER_INTR & 0xf):
1000-
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, SUPERVISOR_TIMER_INTR, 0);
1001-
break;
1002-
case (SUPERVISOR_EXTERNAL_INTR & 0xf):
1003-
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, SUPERVISOR_EXTERNAL_INTR, 0);
1004-
break;
1005-
default:
1006-
break;
1007-
}
1008-
}
1009-
#endif /* RV32_HAS(SYSTEM) && !RV32_HAS(ELF_LOADER) */
1049+
rv_check_interrupt(rv);
10101050

10111051
if (prev && prev->pc_start != last_pc) {
10121052
/* update previous block */

‎src/gdbstub.c‎

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -80,14 +80,12 @@ static gdb_action_t rv_cont(void *args)
8080
{
8181
riscv_t *rv = (riscv_t *) args;
8282
assert(rv);
83-
vm_attr_t *attr = PRIV(rv);
84-
attr->cycle_per_step = 1;
8583

8684
for (; !rv_has_halted(rv) && !rv_is_interrupt(rv);) {
8785
if (breakpoint_map_find(rv->breakpoint_map, rv_get_pc(rv)))
8886
break;
8987

90-
rv_step(rv);
88+
rv_step_debug(rv);
9189
}
9290

9391
/* Clear the interrupt if it's pending */
@@ -100,10 +98,8 @@ static gdb_action_t rv_stepi(void *args)
10098
{
10199
riscv_t *rv = (riscv_t *) args;
102100
assert(rv);
103-
vm_attr_t *attr = PRIV(rv);
104-
attr->cycle_per_step = 1;
105101

106-
rv_step(rv);
102+
rv_step_debug(rv);
107103
return ACT_RESUME;
108104
}
109105

‎src/riscv.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -454,6 +454,9 @@ void rv_debug(riscv_t *rv);
454454
/* step the RISC-V emulator */
455455
void rv_step(void *arg);
456456

457+
/* step the RISC-V emulator for debug mode */
458+
void rv_step_debug(void *arg);
459+
457460
/* set the program counter of a RISC-V emulator */
458461
bool rv_set_pc(riscv_t *rv, riscv_word_t pc);
459462

‎src/rv32_template.c‎

Lines changed: 26 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -224,7 +224,8 @@ RVOP(
224224
* In addition, before relocate_enable_mmu, the block maybe retranslated, \
225225
* thus the branch history lookup table should not be updated too. \
226226
*/ \
227-
IIF(RV32_HAS(SYSTEM)(if (!rv->is_trapped && !reloc_enable_mmu), )) \
227+
IIF(RV32_HAS(SYSTEM)(if (likely(!rv->debug_mode) && !rv->is_trapped && \
228+
!reloc_enable_mmu), )) \
228229
{ \
229230
for (int i = 0; i < HISTORY_SIZE; i++) { \
230231
if (ir->branch_table->PC[i] == PC) { \
@@ -245,31 +246,33 @@ RVOP(
245246
}
246247
#else
247248
#define LOOKUP_OR_UPDATE_BRANCH_HISTORY_TABLE() \
248-
block_t *block = cache_get(rv->block_cache, PC, true); \
249-
if (block) { \
250-
for (int i = 0; i < HISTORY_SIZE; i++) { \
251-
if (ir->branch_table->PC[i] == PC) { \
252-
ir->branch_table->times[i]++; \
253-
if (cache_hot(rv->block_cache, PC)) \
254-
goto end_op; \
249+
if (likely(!rv->debug_mode)) { \
250+
block_t *block = cache_get(rv->block_cache, PC, true); \
251+
if (block) { \
252+
for (int i = 0; i < HISTORY_SIZE; i++) { \
253+
if (ir->branch_table->PC[i] == PC) { \
254+
ir->branch_table->times[i]++; \
255+
if (cache_hot(rv->block_cache, PC)) \
256+
goto end_op; \
257+
} \
255258
} \
256-
} \
257-
/* update branch history table */ \
258-
int min_idx = 0; \
259-
for (int i = 0; i < HISTORY_SIZE; i++) { \
260-
if (!ir->branch_table->times[i]) { \
261-
min_idx = i; \
262-
break; \
263-
} else if (ir->branch_table->times[min_idx] > \
264-
ir->branch_table->times[i]) { \
265-
min_idx = i; \
259+
/* update branch history table */ \
260+
int min_idx = 0; \
261+
for (int i = 0; i < HISTORY_SIZE; i++) { \
262+
if (!ir->branch_table->times[i]) { \
263+
min_idx = i; \
264+
break; \
265+
} else if (ir->branch_table->times[min_idx] > \
266+
ir->branch_table->times[i]) { \
267+
min_idx = i; \
268+
} \
266269
} \
270+
ir->branch_table->times[min_idx] = \
271+
ir->branch_table->PC[min_idx] = PC; \
272+
if (cache_hot(rv->block_cache, PC)) \
273+
goto end_op; \
274+
MUST_TAIL return block->ir_head->impl(rv, block->ir_head, cycle, PC); \
267275
} \
268-
ir->branch_table->times[min_idx] = 1; \
269-
ir->branch_table->PC[min_idx] = PC; \
270-
if (cache_hot(rv->block_cache, PC)) \
271-
goto end_op; \
272-
MUST_TAIL return block->ir_head->impl(rv, block->ir_head, cycle, PC); \
273276
}
274277
#endif
275278

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