Add gaze20

src/mainboard/system76/rpl/Kconfig

@@ -78,6 +78,13 @@ config BOARD_SYSTEM76_GAZE18
 	select EC_SYSTEM76_EC_DGPU
 	select SOC_INTEL_ALDERLAKE_PCH_P
 
+config BOARD_SYSTEM76_GAZE20
+	select BOARD_SYSTEM76_RPL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	select EC_SYSTEM76_EC_DGPU
+	select SOC_INTEL_ALDERLAKE_PCH_P
+
 config BOARD_SYSTEM76_LEMP12
 	select BOARD_SYSTEM76_RPL_COMMON
 	select HAVE_SPD_IN_CBFS
@@ -124,6 +131,7 @@ config VARIANT_DIR
 	default "darp9" if BOARD_SYSTEM76_DARP9
 	default "galp7" if BOARD_SYSTEM76_GALP7
 	default "gaze18" if BOARD_SYSTEM76_GAZE18
+	default "gaze20" if BOARD_SYSTEM76_GAZE20
 	default "lemp12" if BOARD_SYSTEM76_LEMP12
 	default "oryp11" if BOARD_SYSTEM76_ORYP11
 	default "oryp12" if BOARD_SYSTEM76_ORYP12
@@ -140,6 +148,7 @@ config MAINBOARD_PART_NUMBER
 	default "darp9" if BOARD_SYSTEM76_DARP9
 	default "galp7" if BOARD_SYSTEM76_GALP7
 	default "gaze18" if BOARD_SYSTEM76_GAZE18
+	default "gaze20" if BOARD_SYSTEM76_GAZE20
 	default "lemp12" if BOARD_SYSTEM76_LEMP12
 	default "oryp11" if BOARD_SYSTEM76_ORYP11
 	default "oryp12" if BOARD_SYSTEM76_ORYP12
@@ -150,7 +159,7 @@ config MAINBOARD_SMBIOS_PRODUCT_NAME
 	default "Bonobo WS" if BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_BONW15_B
 	default "Darter Pro" if BOARD_SYSTEM76_DARP9
 	default "Galago Pro" if BOARD_SYSTEM76_GALP7
-	default "Gazelle" if BOARD_SYSTEM76_GAZE18
+	default "Gazelle" if BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_GAZE20
 	default "Lemur Pro" if BOARD_SYSTEM76_LEMP12
 	default "Oryx Pro" if BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12
 	default "Serval WS" if BOARD_SYSTEM76_SERW13
@@ -163,6 +172,7 @@ config MAINBOARD_VERSION
 	default "darp9" if BOARD_SYSTEM76_DARP9
 	default "galp7" if BOARD_SYSTEM76_GALP7
 	default "gaze18" if BOARD_SYSTEM76_GAZE18
+	default "gaze20" if BOARD_SYSTEM76_GAZE20
 	default "lemp12" if BOARD_SYSTEM76_LEMP12
 	default "oryp11" if BOARD_SYSTEM76_ORYP11
 	default "oryp12" if BOARD_SYSTEM76_ORYP12
@@ -182,12 +192,12 @@ config DRIVERS_GFX_NVIDIA_BRIDGE
 	default 0x02 if BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_BONW15_B
 
 config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
-	default 45 if BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12
+	default 45 if BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_GAZE20 || BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12
 	default 55 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_SERW13
 	default 80 if BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_BONW15_B
 
 config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
-	default 25 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_BONW15_B || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12 || BOARD_SYSTEM76_SERW13
+	default 25 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_BONW15_B || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_GAZE20 || BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12 || BOARD_SYSTEM76_SERW13
 
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"

src/mainboard/system76/rpl/Kconfig.name

@@ -21,6 +21,9 @@ config BOARD_SYSTEM76_GALP7
 config BOARD_SYSTEM76_GAZE18
 	bool "gaze18"
 
+config BOARD_SYSTEM76_GAZE20
+	bool "gaze20"
+
 config BOARD_SYSTEM76_LEMP12
 	bool "lemp12"
 

src/mainboard/system76/rpl/variants/gaze20/board.fmd

@@ -0,0 +1,12 @@
+FLASH 32M {
+	SI_DESC 4K
+	SI_ME 4824K
+	SI_BIOS@16M 16M {
+		RW_MRC_CACHE 64K
+		SMMSTORE(PRESERVE) 256K
+		WP_RO {
+			FMAP 4K
+			COREBOOT(CBFS)
+		}
+	}
+}

src/mainboard/system76/rpl/variants/gaze20/board_info.txt

@@ -0,0 +1,2 @@
+Board name: gaze20
+Release year: 2025

src/mainboard/system76/rpl/variants/gaze20/gpio.c

@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+	PAD_CFG_NF(GPD2, NATIVE, DEEP, NF1), // LANRTD3_WAKE#
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+	PAD_NC(GPD7, NONE),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // Not documented
+	PAD_CFG_GPI(GPD9, NONE, DEEP), // SLP_WLAN#
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+	PAD_NC(GPD11, NONE),
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
+	PAD_NC(GPP_A6, NONE),
+	PAD_NC(GPP_A7, NONE),
+	PAD_NC(GPP_A8, NONE),
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET_N
+	PAD_NC(GPP_A11, NONE),
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN
+	// GPP_A14 (DGPU_PWR_EN) configured in bootblock
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2), // DP_HPD
+	PAD_NC(GPP_A16, NONE),
+	PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // MDP_B_HPD
+	PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R
+	_PAD_CFG_STRUCT(GPP_A20, 0x86880100, 0x0000), // HDMI_HPD
+	_PAD_CFG_STRUCT(GPP_A21, 0x86880100, 0x0000), // NVVDD_TALERT#
+	PAD_CFG_GPO(GPP_A22, 1, PLTRST), // LAN_PWR_EN
+	PAD_NC(GPP_A23, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+	// GPP_B2 (DGPU_RST#_PCH) configured in bootblock
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
+	PAD_NC(GPP_B4, NONE),
+	PAD_CFG_GPO(GPP_B5, 0, DEEP), // PS8461_SW
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	// GPP_B9 missing
+	// GPP_B10 missing
+	PAD_CFG_GPI(GPP_B11, NONE, PLTRST), // PMCALERT#
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_NC(GPP_B14, NONE), // TOP SWAP OVERRIDE strap
+	PAD_CFG_GPO(GPP_B15, 1, PLTRST), // WLAN_RST#_R
+	_PAD_CFG_STRUCT(GPP_B16, 0x80100100, 0x0000), // INTP_OUT
+	PAD_NC(GPP_B17, NONE),
+	PAD_NC(GPP_B18, NONE), // NO REBOOT strap
+	// GPP_B19 missing
+	// GPP_B20 missing
+	// GPP_B21 missing
+	// GPP_B22 missing
+	PAD_NC(GPP_B23, NONE), // CPUNSSC CLOCK FREQ strap
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_SSD2_PWR_EN
+	PAD_NC(GPP_C3, NONE),
+	PAD_NC(GPP_C4, NONE),
+	PAD_CFG_GPO(GPP_C5, 1, PLTRST), // LAN_RTD3#, TLS CONFIDENTIALITY strap
+	PAD_NC(GPP_C6, NONE),
+	PAD_NC(GPP_C7, NONE),
+	// GPP_C8 missing
+	// GPP_C9 missing
+	// GPP_C10 missing
+	// GPP_C11 missing
+	// GPP_C12 missing
+	// GPP_C13 missing
+	// GPP_C14 missing
+	// GPP_C15 missing
+	// GPP_C16 missing
+	// GPP_C17 missing
+	// GPP_C18 missing
+	// GPP_C19 missing
+	// GPP_C20 missing
+	// GPP_C21 missing
+	// GPP_C22 missing
+	// GPP_C23 missing
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	// GPP_D5 (SSD1_CLKREQ#) configured by FSP
+	PAD_NC(GPP_D6, NONE),
+	PAD_NC(GPP_D7, NONE),
+	// GPP_D8 (GPU_PCIE_CLKREQ3#) configured by FSP
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE), // strap
+	PAD_NC(GPP_D11, NONE),
+	PAD_NC(GPP_D12, NONE), // strap
+	PAD_CFG_GPO(GPP_D13, 0, DEEP), // WLAN_WAKEUP#
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_SSD1_PWR_EN
+	PAD_NC(GPP_D15, NONE),
+	PAD_CFG_GPO(GPP_D16, 0, DEEP), // TEST_R
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
+	_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_NC(GPP_E2, NONE), // BOARD_ID5
+	PAD_CFG_GPO(GPP_E3, 1, DEEP), // PCH_WLAN_EN
+	PAD_NC(GPP_E4, NONE),
+	PAD_NC(GPP_E5, NONE),
+	PAD_NC(GPP_E6, NONE), // JTAG ODT DISABLE strap
+	PAD_NC(GPP_E7, NONE),
+	PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM#
+	PAD_NC(GPP_E9, NONE), // SWI#
+	PAD_NC(GPP_E10, NONE), // strap
+	PAD_NC(GPP_E11, NONE), // strap
+	PAD_NC(GPP_E12, NONE), // BOARD_ID4
+	PAD_NC(GPP_E13, NONE),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_NC(GPP_E17, NONE),
+	PAD_NC(GPP_E18, NONE),
+	PAD_NC(GPP_E19, NONE), // strap
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE), // strap
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RF_RST#
+	// GPP_F5 (XTAL_CLKREQ) configured by FSP
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_CFG_GPO(GPP_F7, 1, DEEP), // GPP_LAN_RST#
+	// GPP_F8 missing
+	PAD_NC(GPP_F9, NONE),
+	PAD_NC(GPP_F10, NONE), // strap
+	PAD_NC(GPP_F11, NONE), // BOARD_ID3
+	PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN_R
+	PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH
+	PAD_NC(GPP_F14, NONE), // BOARD_ID1
+	PAD_NC(GPP_F15, NONE), // BOARD_ID2
+	PAD_NC(GPP_F16, NONE), // BOARD_ID6
+	PAD_NC(GPP_F17, NONE), // BOARD_ID7
+	PAD_CFG_GPO(GPP_F18, 1, DEEP), // CCD_FW_WP#
+	// GPP_F19 (GLAN_CLKREQ#) configured by FSP
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD1_RST#
+	PAD_CFG_GPO(GPP_F21, 1, PLTRST), // M2_SSD2_RST#
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_NC(GPP_H0, NONE), // strap
+	PAD_NC(GPP_H1, NONE), // strap
+	PAD_NC(GPP_H2, NONE), // strap
+	PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // SMD_7411
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // SMC_7411
+	PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD
+	PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD
+	// GPP_H10 (UART0_RX) configured in bootblock
+	// GPP_H11 (UART0_TX) configured in bootblock
+	PAD_NC(GPP_H12, NONE),
+	PAD_NC(GPP_H13, NONE),
+	// GPP_H14 missing
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // I_MDP_CLK
+	// GPP_H16 missing
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // I_MDP_DATA
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+	// GPP_H19 (SSD2_CLKREQ4#) configured by FSP
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	// GPP_H23 (WLAN_CLKREQ5#) configured by FSP
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+
+	/* ------- GPIO Group GPP_T ------- */
+	PAD_NC(GPP_T2, NONE),
+	PAD_NC(GPP_T3, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/rpl/variants/gaze20/gpio_early.c

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
+	PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/system76/rpl/variants/gaze20/hda_verb.c

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC255 */
+	0x10ec0255, /* Vendor ID */
+	0x15582560, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15582560),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x17, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41e79b45),
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/rpl/variants/gaze20/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_F13
+#define DGPU_SSID	0x25601558
+
+#endif