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datapath-design

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RISC-Processor

Ecolash / RISC-Processor

Star 5

𝗠𝗶𝗻𝗶𝗠𝗜𝗣𝗦 | 𝗥𝗜𝗦𝗖 𝗣𝗿𝗼𝗰𝗲𝘀𝘀𝗼𝗿 𝗗𝗲𝘀𝗶𝗴𝗻 | CS39001 𝗖𝗼𝘂𝗿𝘀𝗲 𝗣𝗿𝗼𝗷𝗲𝗰𝘁

pipeline processor assembler vivado hardware-designs assembly-language-programming computer-architecture verilog-hdl instruction-set-architecture mips-architecture control-unit fpga-programming controlpath computer-organization-and-design risc-architecture datapath-design
  • Updated Sep 14, 2025
  • Verilog

shahed22 / Architectural-Design-for-Bus-interface-connected-with-LFSR

Star 1

bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications

asic fsm interface architecture rtl verilog peripherals datapath soc testbench lfsr 32-bit 32bit bus-interface asic-design controlpath datapath-design lfsr-algorithm
  • Updated May 28, 2024
  • Verilog

Awais-Asghar / 5-Stage-Pipelined-RISC-V-Processor-on-FPGA

Star 1

A 5-Stage Pipelined RISC-V Processor designed and implemented on FPGA (Artix-7 Nexys A7). Supports RV32I instructions set (R, I, S, B, U, J types) with ALU, control unit, hazard detection, forwarding, and pipeline registers. Verified through simulation and hardware testing with optimized timing and 4× performance gain.

fpga processor systemverilog pipelining computer-architecture hazard-detection risc-v system-design riscv32 datapath-design pipelined-processor control-logic
  • Updated Oct 13, 2025
  • SystemVerilog

FarrukhAijaz / Single-Cycle-Multi-Cycle-and-Pipeline-ARM-Based-Processor-Design

Star 0

Architecure for the Data path and Controller as well as Hazard Units for a 32 bit ARM based Single Cycle, Multi Cycle and Pipelined Based Processor

processor-architecture arm processor verilog mcu computer-architecture hazard-detection pipeline-processor verilog-hdl 32-bit arm32 pipline processor-design single-cycle-processor multi-cycle-processor multi-cycle-cpu datapath-design
  • Updated Jun 28, 2024
  • Verilog

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