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directed-testing

Here are 2 public repositories matching this topic...

Rex1110 / AES-128

SystemVerilog implementation of AES-128 encryption and decryption , designed for resource efficiency

aes rtl aes-128 systemverilog assertion sva constrained-random-verification directed-testing

Updated Jan 30, 2025
SystemVerilog

nbathula16 / SV-Project

32-bit Single Precision Floating point Multiplication

coverage randomization constraint floating-point testbench normalization multiplier conditional-compilation directed-testing

Updated Mar 23, 2023
SystemVerilog

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