Designed 10 bit multiplier, implemented using structural and RTL level design, and the functionality of 10 bit adder is completely synchronous.
-
Updated
Dec 30, 2017 - VHDL
Designed 10 bit multiplier, implemented using structural and RTL level design, and the functionality of 10 bit adder is completely synchronous.
Add a description, image, and links to the tenbit topic page so that developers can more easily learn about it.
To associate your repository with the tenbit topic, visit your repo's landing page and select "manage topics."