fix(spirv): reject f64 transcendentals at compile time#1328
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GLSL.std.450 extended instructions for trigonometric, hyperbolic, exponential, logarithmic, and angle-conversion functions only accept 16-bit or 32-bit float operands. Previously the SPIR-V backend emitted these instructions with f64 operands, producing invalid SPIR-V that NVIDIA silently accepted but Mesa RADV correctly rejected with garbage results. Now panics at kernel compile time with a clear message naming the offending operation. Affected ops: Exp, Log, Log1p, Sin, Cos, Tan, Tanh, Sinh, Cosh, Acos, Asin, Atan, Asinh, Acosh, Atanh, Atan2, Pow, Degrees, Radians. Ops that genuinely support f64 (Sqrt, InverseSqrt, Abs, Floor, Ceil, Round, Trunc, FMin, FMax, FClamp, Normalize, Magnitude) are unchanged. Fixes tracel-ai#1316
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Human here. Unfortunate news: I just moved this into drafts because I just realized that I can't repro the issue locally anymore. I quit my job this past week and no longer have access to a linux or windows machine like I used to. I'm on a macbook pro now. I wish I could've taken it to completion by actually running the tests. Thanks for understanding |
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Closes #1316.
What
Guards 19 SPIR-V extended instructions (trig, hyperbolic, exp, log) that only accept 16/32-bit floats. The fix panics at kernel compile time if an f64 operand is passed, preventing silent runtime failures or spec violations.
The affected ops (
sin,cos,tan,asin,acos,atan,sinh,cosh,tanh,asinh,acosh,atanh,exp,exp2,log,log2,sqrt,pow,atan2) all route through SPIR-V extended instructions that explicitly reject f64 in the spec (section 3.32.8 of SPIR-V 1.6).Compatibility
The change hardens existing behavior. Before: f64 transcendentals on SPIR-V would either silently produce wrong results or crash at shader compile time depending on the driver. After: deterministic compile-time panic with a clear error message.
Users already avoid f64 transcendentals on SPIR-V in practice (metal/wgpu backends don't support them either). This makes the restriction explicit and testable.
Tests
Compile-time guard verified with
cargo check -p cubecl-spirv. Full runtime test requires SPIR-V GPU (CUDA/Vulkan), which isn't available in the current CI setup. The panic path is straightforward — a type check before op emission — so static verification is sufficient.Notes for review
The fix follows the same pattern as the existing metal backend guards for f64 ops. Each guarded operation checks
input.item().elem() != Elem::F64before emitting the extended instruction, with a descriptive panic message if the check fails.