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fix(ppc): avoid using static TCG variables #2162

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21 changes: 20 additions & 1 deletion qemu/include/tcg/tcg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -720,7 +720,7 @@ struct TCGContext {
void *tb_ret_addr;

/* target/riscv/translate.c */
TCGv cpu_gpr[32], cpu_pc; // also target/mips/translate.c
TCGv cpu_gpr[32], cpu_pc; // also target/mips/translate.c, target/ppc/translate.c
TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
TCGv load_res;
TCGv load_val;
Expand Down Expand Up @@ -803,6 +803,22 @@ struct TCGContext {
// Used to store the start of current instrution.
uint64_t pc_start;

// target/ppc/translate.c
TCGv cpu_gprh[32];
TCGv_i32 cpu_crf[8];
TCGv cpu_nip;
TCGv cpu_msr;
TCGv cpu_ctr;
TCGv cpu_lr;
#if defined(TARGET_PPC64)
TCGv cpu_cfar;
#endif
TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
TCGv cpu_reserve;
TCGv cpu_reserve_val;
TCGv cpu_fpscr;
TCGv_i32 cpu_access_type;

// target/s390x/translate.c
TCGv_i64 psw_addr;
TCGv_i64 psw_mask;
Expand All @@ -813,6 +829,9 @@ struct TCGContext {
TCGv_i64 cc_dst;
TCGv_i64 cc_vr;

char ppc_cpu_reg_names[10 * 3 + 22 * 4 /* GPR */
+ 10 * 4 + 22 * 5 /* SPE GPRh */
+ 8 * 5 /* CRF */];
char s390x_cpu_reg_names[16][4]; // renamed from original cpu_reg_names[][] to avoid name clash with m68k
TCGv_i64 regs[16];
};
Expand Down
5 changes: 3 additions & 2 deletions qemu/target/ppc/helper_regs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -90,8 +90,9 @@ static inline void hreg_compute_hflags(CPUPPCState *env)

/* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */
hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
(1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
(1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR);
(1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) |
(1 << MSR_BE) | (1 << MSR_LE) | (1 << MSR_VSX) |
(1 << MSR_IR) | (1 << MSR_DR);
hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
hreg_compute_mem_idx(env);
env->hflags = env->msr & hflags_mask;
Expand Down
1,408 changes: 701 additions & 707 deletions qemu/target/ppc/translate.c
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Large diffs are not rendered by default.

6 changes: 3 additions & 3 deletions qemu/target/ppc/translate/dfp-impl.inc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ static void gen_##name(DisasContext *ctx) \
gen_update_nip(ctx, ctx->base.pc_next - 4); \
ra = gen_fprp_ptr(tcg_ctx, rA(ctx->opcode)); \
rb = gen_fprp_ptr(tcg_ctx, rB(ctx->opcode)); \
gen_helper_##name(tcg_ctx, cpu_crf[crfD(ctx->opcode)], \
gen_helper_##name(tcg_ctx, tcg_ctx->cpu_crf[crfD(ctx->opcode)], \
tcg_ctx->cpu_env, ra, rb); \
tcg_temp_free_ptr(tcg_ctx, ra); \
tcg_temp_free_ptr(tcg_ctx, rb); \
Expand All @@ -60,7 +60,7 @@ static void gen_##name(DisasContext *ctx) \
gen_update_nip(ctx, ctx->base.pc_next - 4); \
uim = tcg_const_i32(tcg_ctx, UIMM5(ctx->opcode)); \
rb = gen_fprp_ptr(tcg_ctx, rB(ctx->opcode)); \
gen_helper_##name(tcg_ctx, cpu_crf[crfD(ctx->opcode)], \
gen_helper_##name(tcg_ctx, tcg_ctx->cpu_crf[crfD(ctx->opcode)], \
tcg_ctx->cpu_env, uim, rb); \
tcg_temp_free_i32(tcg_ctx, uim); \
tcg_temp_free_ptr(tcg_ctx, rb); \
Expand All @@ -79,7 +79,7 @@ static void gen_##name(DisasContext *ctx) \
gen_update_nip(ctx, ctx->base.pc_next - 4); \
ra = gen_fprp_ptr(tcg_ctx, rA(ctx->opcode)); \
dcm = tcg_const_i32(tcg_ctx, DCM(ctx->opcode)); \
gen_helper_##name(tcg_ctx, cpu_crf[crfD(ctx->opcode)], \
gen_helper_##name(tcg_ctx, tcg_ctx->cpu_crf[crfD(ctx->opcode)], \
tcg_ctx->cpu_env, ra, dcm); \
tcg_temp_free_ptr(tcg_ctx, ra); \
tcg_temp_free_i32(tcg_ctx, dcm); \
Expand Down
76 changes: 38 additions & 38 deletions qemu/target/ppc/translate/fp-impl.inc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -20,15 +20,15 @@ static void gen_set_cr1_from_fpscr(DisasContext *ctx)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx);
tcg_gen_trunc_tl_i32(tcg_ctx, tmp, cpu_fpscr);
tcg_gen_shri_i32(tcg_ctx, cpu_crf[1], tmp, 28);
tcg_gen_trunc_tl_i32(tcg_ctx, tmp, tcg_ctx->cpu_fpscr);
tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_crf[1], tmp, 28);
tcg_temp_free_i32(tcg_ctx, tmp);
}
#else
static void gen_set_cr1_from_fpscr(DisasContext *ctx)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
tcg_gen_shri_tl(tcg_ctx, cpu_crf[1], cpu_fpscr, 28);
tcg_gen_shri_tl(tcg_ctx, tcg_ctx->cpu_crf[1], tcg_ctx->cpu_fpscr, 28);
}
#endif

Expand Down Expand Up @@ -353,7 +353,7 @@ static void gen_ftdiv(DisasContext *ctx)
t1 = tcg_temp_new_i64(tcg_ctx);
get_fpr(tcg_ctx, t0, rA(ctx->opcode));
get_fpr(tcg_ctx, t1, rB(ctx->opcode));
gen_helper_ftdiv(tcg_ctx, cpu_crf[crfD(ctx->opcode)], t0, t1);
gen_helper_ftdiv(tcg_ctx, tcg_ctx->cpu_crf[crfD(ctx->opcode)], t0, t1);
tcg_temp_free_i64(tcg_ctx, t0);
tcg_temp_free_i64(tcg_ctx, t1);
}
Expand All @@ -368,7 +368,7 @@ static void gen_ftsqrt(DisasContext *ctx)
}
t0 = tcg_temp_new_i64(tcg_ctx);
get_fpr(tcg_ctx, t0, rB(ctx->opcode));
gen_helper_ftsqrt(tcg_ctx, cpu_crf[crfD(ctx->opcode)], t0);
gen_helper_ftsqrt(tcg_ctx, tcg_ctx->cpu_crf[crfD(ctx->opcode)], t0);
tcg_temp_free_i64(tcg_ctx, t0);
}

Expand Down Expand Up @@ -605,12 +605,12 @@ static void gen_mcrfs(DisasContext *ctx)
bfa = crfS(ctx->opcode);
nibble = 7 - bfa;
shift = 4 * nibble;
tcg_gen_shri_tl(tcg_ctx, tmp, cpu_fpscr, shift);
tcg_gen_trunc_tl_i32(tcg_ctx, cpu_crf[crfD(ctx->opcode)], tmp);
tcg_gen_andi_i32(tcg_ctx, cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)],
tcg_gen_shri_tl(tcg_ctx, tmp, tcg_ctx->cpu_fpscr, shift);
tcg_gen_trunc_tl_i32(tcg_ctx, tcg_ctx->cpu_crf[crfD(ctx->opcode)], tmp);
tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_crf[crfD(ctx->opcode)], tcg_ctx->cpu_crf[crfD(ctx->opcode)],
0xf);
tcg_temp_free(tcg_ctx, tmp);
tcg_gen_extu_tl_i64(tcg_ctx, tnew_fpscr, cpu_fpscr);
tcg_gen_extu_tl_i64(tcg_ctx, tnew_fpscr, tcg_ctx->cpu_fpscr);
/* Only the exception bits (including FX) should be cleared if read */
tcg_gen_andi_i64(tcg_ctx, tnew_fpscr, tnew_fpscr,
~((0xF << shift) & FP_EX_CLEAR_BITS));
Expand All @@ -632,7 +632,7 @@ static void gen_mffs(DisasContext *ctx)
}
t0 = tcg_temp_new_i64(tcg_ctx);
gen_reset_fpstatus(tcg_ctx);
tcg_gen_extu_tl_i64(tcg_ctx, t0, cpu_fpscr);
tcg_gen_extu_tl_i64(tcg_ctx, t0, tcg_ctx->cpu_fpscr);
set_fpr(tcg_ctx, rD(ctx->opcode), t0);
if (unlikely(Rc(ctx->opcode))) {
gen_set_cr1_from_fpscr(ctx);
Expand All @@ -647,7 +647,7 @@ static void gen_mffsl(DisasContext *ctx)
TCGv_i64 t0;

if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
return;
return gen_mffs(ctx);
}

if (unlikely(!ctx->fpu_enabled)) {
Expand All @@ -656,7 +656,7 @@ static void gen_mffsl(DisasContext *ctx)
}
t0 = tcg_temp_new_i64(tcg_ctx);
gen_reset_fpstatus(tcg_ctx);
tcg_gen_extu_tl_i64(tcg_ctx, t0, cpu_fpscr);
tcg_gen_extu_tl_i64(tcg_ctx, t0, tcg_ctx->cpu_fpscr);
/* Mask everything except mode, status, and enables. */
tcg_gen_andi_i64(tcg_ctx, t0, t0, FP_DRN | FP_STATUS | FP_ENABLES | FP_RN);
set_fpr(tcg_ctx, rD(ctx->opcode), t0);
Expand All @@ -671,7 +671,7 @@ static void gen_mffsce(DisasContext *ctx)
TCGv_i32 mask;

if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
return;
return gen_mffs(ctx);
}

if (unlikely(!ctx->fpu_enabled)) {
Expand All @@ -682,7 +682,7 @@ static void gen_mffsce(DisasContext *ctx)
t0 = tcg_temp_new_i64(tcg_ctx);

gen_reset_fpstatus(tcg_ctx);
tcg_gen_extu_tl_i64(tcg_ctx, t0, cpu_fpscr);
tcg_gen_extu_tl_i64(tcg_ctx, t0, tcg_ctx->cpu_fpscr);
set_fpr(tcg_ctx, rD(ctx->opcode), t0);

/* Clear exception enable bits in the FPSCR. */
Expand All @@ -701,7 +701,7 @@ static void gen_helper_mffscrn(DisasContext *ctx, TCGv_i64 t1)
TCGv_i32 mask = tcg_const_i32(tcg_ctx, 0x0001);

gen_reset_fpstatus(tcg_ctx);
tcg_gen_extu_tl_i64(tcg_ctx, t0, cpu_fpscr);
tcg_gen_extu_tl_i64(tcg_ctx, t0, tcg_ctx->cpu_fpscr);
tcg_gen_andi_i64(tcg_ctx, t0, t0, FP_DRN | FP_ENABLES | FP_RN);
set_fpr(tcg_ctx, rD(ctx->opcode), t0);

Expand All @@ -724,7 +724,7 @@ static void gen_mffscrn(DisasContext *ctx)
TCGv_i64 t1;

if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
return;
return gen_mffs(ctx);
}

if (unlikely(!ctx->fpu_enabled)) {
Expand All @@ -749,7 +749,7 @@ static void gen_mffscrni(DisasContext *ctx)
TCGv_i64 t1;

if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
return;
return gen_mffs(ctx);
}

if (unlikely(!ctx->fpu_enabled)) {
Expand Down Expand Up @@ -783,8 +783,8 @@ static void gen_mtfsb0(DisasContext *ctx)
tcg_temp_free_i32(tcg_ctx, t0);
}
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(tcg_ctx, cpu_crf[1], cpu_fpscr);
tcg_gen_shri_i32(tcg_ctx, cpu_crf[1], cpu_crf[1], FPSCR_OX);
tcg_gen_trunc_tl_i32(tcg_ctx, tcg_ctx->cpu_crf[1], tcg_ctx->cpu_fpscr);
tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_crf[1], tcg_ctx->cpu_crf[1], FPSCR_OX);
}
}

Expand All @@ -808,8 +808,8 @@ static void gen_mtfsb1(DisasContext *ctx)
tcg_temp_free_i32(tcg_ctx, t0);
}
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(tcg_ctx, cpu_crf[1], cpu_fpscr);
tcg_gen_shri_i32(tcg_ctx, cpu_crf[1], cpu_crf[1], FPSCR_OX);
tcg_gen_trunc_tl_i32(tcg_ctx, tcg_ctx->cpu_crf[1], tcg_ctx->cpu_fpscr);
tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_crf[1], tcg_ctx->cpu_crf[1], FPSCR_OX);
}
/* We can raise a deferred exception */
gen_helper_float_check_status(tcg_ctx, tcg_ctx->cpu_env);
Expand Down Expand Up @@ -845,8 +845,8 @@ static void gen_mtfsf(DisasContext *ctx)
gen_helper_store_fpscr(tcg_ctx, tcg_ctx->cpu_env, t1, t0);
tcg_temp_free_i32(tcg_ctx, t0);
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(tcg_ctx, cpu_crf[1], cpu_fpscr);
tcg_gen_shri_i32(tcg_ctx, cpu_crf[1], cpu_crf[1], FPSCR_OX);
tcg_gen_trunc_tl_i32(tcg_ctx, tcg_ctx->cpu_crf[1], tcg_ctx->cpu_fpscr);
tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_crf[1], tcg_ctx->cpu_crf[1], FPSCR_OX);
}
/* We can raise a deferred exception */
gen_helper_float_check_status(tcg_ctx, tcg_ctx->cpu_env);
Expand Down Expand Up @@ -879,8 +879,8 @@ static void gen_mtfsfi(DisasContext *ctx)
tcg_temp_free_i64(tcg_ctx, t0);
tcg_temp_free_i32(tcg_ctx, t1);
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(tcg_ctx, cpu_crf[1], cpu_fpscr);
tcg_gen_shri_i32(tcg_ctx, cpu_crf[1], cpu_crf[1], FPSCR_OX);
tcg_gen_trunc_tl_i32(tcg_ctx, tcg_ctx->cpu_crf[1], tcg_ctx->cpu_fpscr);
tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_crf[1], tcg_ctx->cpu_crf[1], FPSCR_OX);
}
/* We can raise a deferred exception */
gen_helper_float_check_status(tcg_ctx, tcg_ctx->cpu_env);
Expand All @@ -898,13 +898,13 @@ static void glue(gen_, name)(DisasContext *ctx) \
return; \
} \
gen_set_access_type(ctx, ACCESS_FLOAT); \
EA = tcg_temp_new(tcg_ctx); \
t0 = tcg_temp_new_i64(tcg_ctx); \
EA = tcg_temp_new(tcg_ctx); \
t0 = tcg_temp_new_i64(tcg_ctx); \
gen_addr_imm_index(ctx, EA, 0); \
gen_qemu_##ldop(ctx, t0, EA); \
set_fpr(tcg_ctx, rD(ctx->opcode), t0); \
tcg_temp_free(tcg_ctx, EA); \
tcg_temp_free_i64(tcg_ctx, t0); \
set_fpr(tcg_ctx, rD(ctx->opcode), t0); \
tcg_temp_free(tcg_ctx, EA); \
tcg_temp_free_i64(tcg_ctx, t0); \
}

#define GEN_LDUF(name, ldop, opc, type) \
Expand All @@ -927,7 +927,7 @@ static void glue(gen_, name##u)(DisasContext *ctx) \
gen_addr_imm_index(ctx, EA, 0); \
gen_qemu_##ldop(ctx, t0, EA); \
set_fpr(tcg_ctx, rD(ctx->opcode), t0); \
tcg_gen_mov_tl(tcg_ctx, cpu_gpr[rA(ctx->opcode)], EA); \
tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_gpr[rA(ctx->opcode)], EA); \
tcg_temp_free(tcg_ctx, EA); \
tcg_temp_free_i64(tcg_ctx, t0); \
}
Expand All @@ -952,7 +952,7 @@ static void glue(gen_, name##ux)(DisasContext *ctx) \
gen_addr_reg_index(ctx, EA); \
gen_qemu_##ldop(ctx, t0, EA); \
set_fpr(tcg_ctx, rD(ctx->opcode), t0); \
tcg_gen_mov_tl(tcg_ctx, cpu_gpr[rA(ctx->opcode)], EA); \
tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_gpr[rA(ctx->opcode)], EA); \
tcg_temp_free(tcg_ctx, EA); \
tcg_temp_free_i64(tcg_ctx, t0); \
}
Expand Down Expand Up @@ -1172,7 +1172,7 @@ static void glue(gen_, name##u)(DisasContext *ctx) \
gen_addr_imm_index(ctx, EA, 0); \
get_fpr(tcg_ctx, t0, rS(ctx->opcode)); \
gen_qemu_##stop(ctx, t0, EA); \
tcg_gen_mov_tl(tcg_ctx, cpu_gpr[rA(ctx->opcode)], EA); \
tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_gpr[rA(ctx->opcode)], EA); \
tcg_temp_free(tcg_ctx, EA); \
tcg_temp_free_i64(tcg_ctx, t0); \
}
Expand All @@ -1197,7 +1197,7 @@ static void glue(gen_, name##ux)(DisasContext *ctx) \
gen_addr_reg_index(ctx, EA); \
get_fpr(tcg_ctx, t0, rS(ctx->opcode)); \
gen_qemu_##stop(ctx, t0, EA); \
tcg_gen_mov_tl(tcg_ctx, cpu_gpr[rA(ctx->opcode)], EA); \
tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_gpr[rA(ctx->opcode)], EA); \
tcg_temp_free(tcg_ctx, EA); \
tcg_temp_free_i64(tcg_ctx, t0); \
}
Expand Down Expand Up @@ -1387,7 +1387,7 @@ static void gen_lfqu(DisasContext *ctx)
gen_qemu_ld64_i64(ctx, t2, t1);
set_fpr(tcg_ctx, (rd + 1) % 32, t2);
if (ra != 0) {
tcg_gen_mov_tl(tcg_ctx, cpu_gpr[ra], t0);
tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_gpr[ra], t0);
}
tcg_temp_free(tcg_ctx, t0);
tcg_temp_free(tcg_ctx, t1);
Expand All @@ -1414,7 +1414,7 @@ static void gen_lfqux(DisasContext *ctx)
set_fpr(tcg_ctx, (rd + 1) % 32, t2);
tcg_temp_free(tcg_ctx, t1);
if (ra != 0) {
tcg_gen_mov_tl(tcg_ctx, cpu_gpr[ra], t0);
tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_gpr[ra], t0);
}
tcg_temp_free(tcg_ctx, t0);
tcg_temp_free_i64(tcg_ctx, t2);
Expand Down Expand Up @@ -1480,7 +1480,7 @@ static void gen_stfqu(DisasContext *ctx)
gen_qemu_st64_i64(ctx, t2, t1);
tcg_temp_free(tcg_ctx, t1);
if (ra != 0) {
tcg_gen_mov_tl(tcg_ctx, cpu_gpr[ra], t0);
tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_gpr[ra], t0);
}
tcg_temp_free(tcg_ctx, t0);
tcg_temp_free_i64(tcg_ctx, t2);
Expand All @@ -1506,7 +1506,7 @@ static void gen_stfqux(DisasContext *ctx)
gen_qemu_st64_i64(ctx, t2, t1);
tcg_temp_free(tcg_ctx, t1);
if (ra != 0) {
tcg_gen_mov_tl(tcg_ctx, cpu_gpr[ra], t0);
tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_gpr[ra], t0);
}
tcg_temp_free(tcg_ctx, t0);
tcg_temp_free_i64(tcg_ctx, t2);
Expand Down
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