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aarch64: add exception syndrome (ESR) pseudo-register #841

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misson20000
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Closes #838

@aquynh
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aquynh commented May 20, 2017

This is not a real register, so it is confused. I rather having a new API to read/write CPU context.

@misson20000
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Is that the sort of thing uc_query is for, and if so, would this be better off as a uc_query option?

@aquynh
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aquynh commented May 21, 2017 via email

@misson20000
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the exception syndrome shouldn't be set by anything other than the emulator when it encounters an exception, which is why I didn't implement reg_write for it

@misson20000
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Unless you're emulating something with more privileges and exception handlers I guess, but then you'd want to set the exception syndrome for a specific exception level (ESR_EL1, ESR_EL2, and ESR_EL3), and those are real registers (in the cp15 struct) so it makes sense to have those in uc_reg_read and uc_reg_write.

I don't have a way of telling what exception level an exception gets taken to though, so I wouldn't know which of those specific registers to read which is what I wanted a more general exception syndrome pseudo-register for.

@SomeoneWeird
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Any update on this?

@jtojnar jtojnar mentioned this pull request May 18, 2020
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@wtdcode
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wtdcode commented Oct 3, 2021

Closed due to inactivity.

@wtdcode wtdcode closed this Oct 3, 2021
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wtdcode commented Oct 3, 2021

But still link this to #1449 if I have more time or some one could assist me.

Ra2-IFV added a commit to ifvlaboratory/dynarmic that referenced this pull request May 25, 2024
@wtdcode wtdcode reopened this Apr 12, 2025
@wtdcode wtdcode mentioned this pull request Apr 12, 2025
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AArch64 Exception Syndrome Inaccessible
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