verilog: skip compiler directives in enum definition (#4056)

Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com>

Author: hirooih

Units/parser-verilog.r/systemverilog-github4056.d/args.ctags

@@ -0,0 +1 @@
+--sort=no

Units/parser-verilog.r/systemverilog-github4056.d/expected.tags

@@ -0,0 +1,4 @@
+my_enum	input.sv	/^} my_enum;$/;"	T
+OTHER_VAL1	input.sv	/^  OTHER_VAL1,$/;"	c	typedef:my_enum
+OTHER_VAL2	input.sv	/^  OTHER_VAL2$/;"	c	typedef:my_enum
+e	input.sv	/^my_enum e;$/;"	r

Units/parser-verilog.r/systemverilog-github4056.d/input.sv

@@ -0,0 +1,10 @@
+// https://github.com/universal-ctags/ctags/issues/4056
+
+typedef enum {
+  `include "test1.txt"
+  OTHER_VAL1,
+  `include "test2.txt"
+  OTHER_VAL2
+} my_enum;
+
+my_enum e;

parsers/verilog.c

@@ -1614,6 +1614,7 @@ static int pushEnumNames (tokenInfo* token, int c)
 		c = skipWhite (vGetc ());
 		while (c != '}' && c != EOF)
 		{
+			c = skipMacro (c, token);
 			if (!isWordToken (c))
 			{
 				VERBOSE ("Unexpected input: %c\n", c);