Programa de asm insertado

Author: Piloalucard

DATAPATH/ADD.v.bak

@@ -1,6 +1,6 @@
 module ADD(
-	input [31:0] pc,
-	output reg [31:0] sal
+	input [7:0] pc,
+	output reg [7:0] sal
 );
 
 

DATAPATH/DATAPATH.qsf

@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE AUTO
 set_global_assignment -name TOP_LEVEL_ENTITY DATAPATH
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:02:58  APRIL 29, 2020"
-set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
 set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation

DATAPATH/DATAPATH.qws

@@ -17,9 +17,9 @@ initial
 begin
 	clk = 1'b1;
 	$readmemb("TestF1_BReg.mem",DUV.p7.mem);
-	$readmemb("TestF3_MemInst.mem",DUV.p3.MR);
+	$readmemb("Subneteo.txt",DUV.p3.MR);
 	$readmemb("datamemoryTest.mem",DUV.p16.mem2);
-   #60;
+   #10000;
    $stop;
 end
 

DATAPATH/DATAPATH_TB.v

@@ -1,14 +1,13 @@
 
 module INST_MEM(
-	input [31:0] dir,
-	output reg [31:0] datos,d
+	input [7:0] dir,
+	output reg [31:0] datos
 );
-reg [7:0] MR [0:2047];
+reg [7:0] MR [0:127];
 
 
 always@*
 	begin
-		datos={MR[dir],MR[dir+1],MR[dir+2],MR[dir+3]};
-		d=datos;
+		datos<={MR[dir],MR[dir+1],MR[dir+2],MR[dir+3]};
 	end
 endmodule

DATAPATH/INST_MEM.v.bak

@@ -1,8 +1,8 @@
 
 module PC(
 	input clk,
-	input [31:0] ent,
-	output reg [31:0] pc
+	input [7:0] ent,
+	output reg [7:0] pc
 );
 
 
@@ -16,7 +16,7 @@ always @(posedge clk)
 		else
 			begin
 
-				pc=32'd0;
+				pc=8'd0;
 			end
 	end