Mangled path with based number

Based numbers in a mangled path are not escaped.

Example

Veryl
```systemverilog
module ModuleA::<W: u32> {
}
module ModuleB {
  inst u_a: ModuleA::<32'd0>;
}
```

Generated SV
```systemverilog
module project___ModuleA__32'd0;
endmodule

module project_ModuleB;
    project___ModuleA__32'd0 u_a ();
endmodule
//# sourceMappingURL=input.sv.map
```