Memory write error at 0x80000000. MicroBlaze instruction insert overrun

[gari-marcos]

Hello,
First of all, thanks for your tutorial, it's great and easy to follow.
I followed it using an Arty 100 instead of the Arty 35 and everything seemed to work fine. However, when I try to run the program the following error appears:
10:05:47 ERROR : Memory write error at 0x80000000. MicroBlaze instruction insert overrun

I checked the Vitis Log and this is it in case you need it:

10:04:56 INFO	: Checking for BSP changes to sync application flags for project 'DDR3_read_test'...
10:05:27 INFO	: Bit file 'C:/workspace/DDR3_read_test/_ide/bitstream/download.bit' is generated.
10:05:27 INFO	: Connected to target on host '127.0.0.1' and port '3121'.
10:05:27 INFO	: 'targets -set -filter {jtag_cable_name =~ "Digilent USB104 A7 - 100T 210398AE9417A" && level==0 && jtag_device_ctx=="jsn-USB104 A7 - 100T-210398AE9417A-13631093-0"}' command is executed.
10:05:29 INFO	: Device configured successfully with "C:/workspace/DDR3_read_test/_ide/bitstream/download.bit"
10:05:41 INFO	: Connected to target on host '127.0.0.1' and port '3121'.
10:05:42 INFO	: Jtag cable 'Digilent USB104 A7 - 100T 210398AE9417A' is selected.
10:05:42 INFO	: 'jtag frequency' command is executed.
10:05:42 INFO	: 'targets -set -filter {jtag_cable_name =~ "Digilent USB104 A7 - 100T 210398AE9417A" && level==0 && jtag_device_ctx=="jsn-USB104 A7 - 100T-210398AE9417A-13631093-0"}' command is executed.
10:05:44 INFO	: Device configured successfully with "C:/workspace/DDR3_read_test/_ide/bitstream/system_wrapper_leds.bit"
10:05:44 INFO	: Context for processor 'microblaze_0' is selected.
10:05:44 INFO	: Hardware design and registers information is loaded from 'C:/workspace/system/export/system/hw/system_wrapper_leds.xsa'.
10:05:44 INFO	: 'configparams mdm-detect-bscan-mask 2' command is executed.
10:05:44 INFO	: Context for processor 'microblaze_0' is selected.
10:05:44 INFO	: System reset is completed.
10:05:47 INFO	: 'after 3000' command is executed.
10:05:47 INFO	: Context for processor 'microblaze_0' is selected.
10:05:47 ERROR	: Memory write error at 0x80000000. MicroBlaze instruction insert overrun
10:05:47 INFO	: ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
targets -set -filter {jtag_cable_name =~ "Digilent USB104 A7 - 100T 210398AE9417A" && level==0 && jtag_device_ctx=="jsn-USB104 A7 - 100T-210398AE9417A-13631093-0"}
fpga -file C:/workspace/DDR3_read_test/_ide/bitstream/system_wrapper_leds.bit
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
loadhw -hw C:/workspace/system/export/system/hw/system_wrapper_leds.xsa -regs
configparams mdm-detect-bscan-mask 2
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
rst -system
after 3000
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
dow C:/workspace/DDR3_read_test/Debug/DDR3_read_test.elf
----------------End of Script----------------

I checked online and I saw it could be something related to the timing constraints, so I checked the Vivado timing report summary and i got this:

Is there anything I could change in order to work properly?
Thank you in advance

[viktor-nikolov]

Hi!
Honestly, I don't remember seeing such an error before.

As the first troubleshooting step, I recommend that you lower the MicroBlaze's frequency to 100 MHz. As I described in this chapter of the tutorial, lowering the frequency will eliminate the timing violations, and the overall design should be more stable.

Do I understand correctly that you built the HW design from scratch following the tutorial's steps?

Did you also create the Vitis workspace from scratch or re-used the one provided in the project_files? I recommend that you create a brand new Vitis workspace using the HW definition .xsa file exported from your HW design. You then just copy the main.cpp into the src folder of your Vitis workspace.

[gari-marcos]

Hi!
I tried to lower the frequency to 100MHz and the error is still appearing. The thing is I want to run the MicroBlaze at 200MHz as I want to run instructions at that frequency, so I followed the tutorial in order to achieve that. In previously attempts of changing the MicroBlaze frequency to 200MHz the local memory was the one that had problems with it.

Yes, I built the HW from scratch following every step.

I tried to create the Vitis workspace using the .xsa file exported instead of importing the one provided but I still get the same error.

In case I can't set the MicroBlaze clock to 200MHz, is there any way that I can send a signal in a PMOD, for instance, at 200MHz?

Thank you very much

[viktor-nikolov]

tried to lower the frequency to 100MHz and the error is still appearing

Can you upload your HW design here so I can look at it? Please note that limit for attachment size on a GitHub issue is 25 MB for files, which are not pictures or videos.

want to run the MicroBlaze at 200MHz

As I explained in the tutorial, 200 MHz seems on the boundary of what is possible on the Artix 7 FPGA chip.
In a more complex design, where I needed to use AXI Quad SPI IP, I had go with the MicroBlaze frequency down to 160 MHz.

Have you considered using Xilinx Zynq SoC (e.g., Cora Z7)? It comes with one or two ARM cores running at 667 MHz. The overall HW design is much simpler than using a MicroBlaze (see this tutorial).

is there any way that I can send a signal in a PMOD, for instance, at 200MHz?

I believe 200 MHz should be possible on Arty A100 by a logic implemented in the Programmable Logic of the FPGA.
You would need to write such logic in Verilog. Or you can write it in C and convert it to Verilog by Vitis HLS.

[gari-marcos]

Can you upload your HW design here so I can look at it? Please note that limit for attachment size on a GitHub issue is 25 MB for files, which are not pictures or videos.

Sure, I am uploading the .xpr file so you can check it, thank you
project_3.zip

As I explained in the tutorial, 200 MHz seems on the boundary of what is possible on the Artix 7 FPGA chip.

I set 200MHz as a reference value, but I previously tried to change the frequency and set it to a value different than 100MHz and I had problems too.

I will check the Xilinx Zynq SoC to see it if it has what I need, thanks for the tip!

I believe 200 MHz should be possible on Arty A100 by a logic implemented in the Programmable Logic of the FPGA.

Okay, I see. I will check how to implement it.

[viktor-nikolov]

project_3.zip

The .xpr file alone is not enough. I need the full content of the folder from which you took the .xpr file (including sub-folders!).
I suggest you first run reset_project command in the Tcl console to erase synthesis and implementation outputs. That will significantly reduce the overall size.

[gari-marcos]

Sorry, my bad. Here you have the file with every sub folder.
project_3.zip

[viktor-nikolov]

I don't see any obvious issue in your HW design.

I'm getting curious what the issue is. I will change board in your HW design to my Arty A7-35, produce outputs and try to run it. I will have time for this probably tomorrow or during the weekend.

[viktor-nikolov]

Unfortunately, I don't know what the problem is you are facing. It worked for me without issues.

I installed the Vivado and Vitis 2023.2 (in Linux VM).
I opened your HW design and changed the board to Arty A7-35T (I made no other changes; the frequency remained 200 MHz).
Vivado asked me to go through the MIG wizard in order to re-generate it. Nevertheless, the configuration of MIG remained the same. I compared it to your original HW design.

I generated the Vivado outputs, created a Vitis Classic workspace, compiled the main.cpp.
The app ran normally and worked as expected (I checked with a scope connected to the board's pin A0).

Do you have access to other Artix-7 FPGA board? Maybe there is a HW issue with your Arty A7-100T.

[gari-marcos]

I tried with another board, but the error is still appearing. I compiled a 'Hello world' application to try and it didn't run so the problem has to do something with the HW. The error is related to the MIG memory, since the 0x800000 address belongs to it, maybe something about the timing constraints? Do you have any timing violations in your Vivado output?
Thanks

[viktor-nikolov]

Yes, I had a critical warning about timing constraints violations in Vivado. Those should disappear when the MicroBlaze frequency is lowered to 100 MHz, but you said you face the issue even at 100 MHz.

Yes, 0x80000000 is indeed the address at which the start of DDR3 memory is located.

Can you share the export of your Vitis workspace? Let me look at it. Maybe I will spot something.

[gari-marcos]

Okay, sure, I am attaching it in a ZIP file.
Thank you
vitis_export_archive.ide.zip

[viktor-nikolov]

I'm sorry, but I don't see what is wrong with your setup. 😟

I created a new Vitis workspace and imported your export. I didn't see anything suspicious in the project.
Since I don't have Arty A7-100, I updated the hardware specification with Arty A7-35 system_wrapper.xsa from this repository. The build worked normally. I could start the debugger and step through your main.cpp.

When I copied into the Vitis main.cpp from this repository it worked as expected and I saw expected signal on the ping A0.

[gari-marcos]

It's okay, no problem. Thanks for the help! I'll continue working on it and in case I fix it, I'll let you know.

Thank you again!

[changkaile]

It's okay, no problem. Thanks for the help! I'll continue working on it and in case I fix it, I'll let you know.

Thank you again!

Hello.I also meet this problem,have you solved this problem?Thank you.