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wdfk-progwdfk-prog
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添加STM32L4头文件
1 parent 09b020c commit e22d0e2

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6 files changed

+148
-147
lines changed

6 files changed

+148
-147
lines changed

‎inc/irq_stm32f1.h

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
* @date 2022-12-27
77
* @copyright Copyright (c) 2022
88
* @attention
9-
* @par ÐÞ¸ÄÈÕÖ¾:
9+
* @par Change log
1010
* Date Version Author Description
1111
* 2022-12-27 1.0 HLY first version
1212
*/
@@ -22,13 +22,13 @@
2222
[8] = "EXTI2_IRQn", /*!< EXTI Line2 Interrupt */
2323
[9] = "EXTI3_IRQn", /*!< EXTI Line3 Interrupt */
2424
[10] = "EXTI4_IRQn", /*!< EXTI Line4 Interrupt */
25-
[11] = "DMA1_Stream0_IRQn", /*!< DMA1 Stream 0 global Interrupt */
26-
[12] = "DMA1_Stream1_IRQn", /*!< DMA1 Stream 1 global Interrupt */
27-
[13] = "DMA1_Stream2_IRQn", /*!< DMA1 Stream 2 global Interrupt */
28-
[14] = "DMA1_Stream3_IRQn", /*!< DMA1 Stream 3 global Interrupt */
29-
[15] = "DMA1_Stream4_IRQn", /*!< DMA1 Stream 4 global Interrupt */
30-
[16] = "DMA1_Stream5_IRQn", /*!< DMA1 Stream 5 global Interrupt */
31-
[17] = "DMA1_Stream6_IRQn", /*!< DMA1 Stream 6 global Interrupt */
25+
[11] = "DMA1_Stream1_IRQn", /*!< DMA1 Stream 1 global Interrupt */
26+
[12] = "DMA1_Stream2_IRQn", /*!< DMA1 Stream 2 global Interrupt */
27+
[13] = "DMA1_Stream3_IRQn", /*!< DMA1 Stream 3 global Interrupt */
28+
[14] = "DMA1_Stream4_IRQn", /*!< DMA1 Stream 4 global Interrupt */
29+
[15] = "DMA1_Stream5_IRQn", /*!< DMA1 Stream 5 global Interrupt */
30+
[16] = "DMA1_Stream6_IRQn", /*!< DMA1 Stream 6 global Interrupt */
31+
[17] = "DMA1_Stream7_IRQn", /*!< DMA1 Stream 7 global Interrupt */
3232
[18] = "ADC_IRQn", /*!< ADC1 and ADC2 global Interrupts */
3333
#if defined (STM32F102x6) || defined (STM32F102xB)
3434
[19] = "USB_HP_IRQn", /*!< USB Device High Priority */
@@ -86,11 +86,11 @@
8686
[53] = "UART5_IRQn", /*!< UART5 global Interrupt */
8787
[54] = "TIM6_DAC_IRQn", /*!< TIM6 global and DAC1&2 underrun error interrupts */
8888
[55] = "TIM7_IRQn", /*!< TIM7 global interrupt */
89-
[56] = "DMA2_Stream0_IRQn", /*!< DMA2 Stream 0 global Interrupt */
90-
[57] = "DMA2_Stream1_IRQn", /*!< DMA2 Stream 1 global Interrupt */
91-
[58] = "DMA2_Stream2_IRQn", /*!< DMA2 Stream 2 global Interrupt */
92-
[59] = "DMA2_Stream3_IRQn", /*!< DMA2 Stream 3 global Interrupt */
93-
[60] = "DMA2_Stream4_IRQn", /*!< DMA2 Stream 4 global Interrupt */
89+
[56] = "DMA2_Stream1_IRQn", /*!< DMA2 Stream 1 global Interrupt */
90+
[57] = "DMA2_Stream2_IRQn", /*!< DMA2 Stream 2 global Interrupt */
91+
[58] = "DMA2_Stream3_IRQn", /*!< DMA2 Stream 3 global Interrupt */
92+
[59] = "DMA2_Stream4_IRQn", /*!< DMA2 Stream 4 global Interrupt */
93+
[60] = "DMA2_Stream5_IRQn", /*!< DMA2 Stream 5 global Interrupt */
9494
[61] = "ETH_IRQn", /*!< Ethernet global Interrupt */
9595
[62] = "ETH_WKUP_IRQn", /*!< Ethernet Wakeup through EXTI line Interrupt */
9696
[63] = "CAN2_TX_IRQn ", /*!< CAN2 TX Interrupt */

‎inc/irq_stm32f3.h

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
* @date 2022-12-27
77
* @copyright Copyright (c) 2022
88
* @attention
9-
* @par ÐÞ¸ÄÈÕÖ¾:
9+
* @par Change log:
1010
* Date Version Author Description
1111
* 2022-12-27 1.0 HLY first version
1212
*/
@@ -22,13 +22,13 @@
2222
[8] = "EXTI2_IRQn", /*!< EXTI Line2 Interrupt */
2323
[9] = "EXTI3_IRQn", /*!< EXTI Line3 Interrupt */
2424
[10] = "EXTI4_IRQn", /*!< EXTI Line4 Interrupt */
25-
[11] = "DMA1_Stream0_IRQn", /*!< DMA1 Stream 0 global Interrupt */
26-
[12] = "DMA1_Stream1_IRQn", /*!< DMA1 Stream 1 global Interrupt */
27-
[13] = "DMA1_Stream2_IRQn", /*!< DMA1 Stream 2 global Interrupt */
28-
[14] = "DMA1_Stream3_IRQn", /*!< DMA1 Stream 3 global Interrupt */
29-
[15] = "DMA1_Stream4_IRQn", /*!< DMA1 Stream 4 global Interrupt */
30-
[16] = "DMA1_Stream5_IRQn", /*!< DMA1 Stream 5 global Interrupt */
31-
[17] = "DMA1_Stream6_IRQn", /*!< DMA1 Stream 6 global Interrupt */
25+
[11] = "DMA1_Stream1_IRQn", /*!< DMA1 Stream 1 global Interrupt */
26+
[12] = "DMA1_Stream2_IRQn", /*!< DMA1 Stream 2 global Interrupt */
27+
[13] = "DMA1_Stream3_IRQn", /*!< DMA1 Stream 3 global Interrupt */
28+
[14] = "DMA1_Stream4_IRQn", /*!< DMA1 Stream 4 global Interrupt */
29+
[15] = "DMA1_Stream5_IRQn", /*!< DMA1 Stream 5 global Interrupt */
30+
[16] = "DMA1_Stream6_IRQn", /*!< DMA1 Stream 6 global Interrupt */
31+
[17] = "DMA1_Stream7_IRQn", /*!< DMA1 Stream 7 global Interrupt */
3232
[18] = "ADC_IRQn", /*!< ADC1 and ADC2 global Interrupts */
3333
[19] = "CAN1_TX_IRQn", /*!< CAN1 TX Interrupt */
3434
[20] = "CAN1_RX0_IRQn", /*!< CAN1 RX0 Interrupt */
@@ -67,11 +67,11 @@
6767
[53] = "UART5_IRQn", /*!< UART5 global Interrupt */
6868
[54] = "TIM6_DAC_IRQn", /*!< TIM6 global and DAC1&2 underrun error interrupts */
6969
[55] = "TIM7_IRQn", /*!< TIM7 global interrupt */
70-
[56] = "DMA2_Stream0_IRQn", /*!< DMA2 Stream 0 global Interrupt */
71-
[57] = "DMA2_Stream1_IRQn", /*!< DMA2 Stream 1 global Interrupt */
72-
[58] = "DMA2_Stream2_IRQn", /*!< DMA2 Stream 2 global Interrupt */
73-
[59] = "DMA2_Stream3_IRQn", /*!< DMA2 Stream 3 global Interrupt */
74-
[60] = "DMA2_Stream4_IRQn", /*!< DMA2 Stream 4 global Interrupt */
70+
[56] = "DMA2_Stream1_IRQn", /*!< DMA2 Stream 1 global Interrupt */
71+
[57] = "DMA2_Stream2_IRQn", /*!< DMA2 Stream 2 global Interrupt */
72+
[58] = "DMA2_Stream3_IRQn", /*!< DMA2 Stream 3 global Interrupt */
73+
[59] = "DMA2_Stream4_IRQn", /*!< DMA2 Stream 4 global Interrupt */
74+
[60] = "DMA2_Stream5_IRQn", /*!< DMA2 Stream 5 global Interrupt */
7575
#if defined(STM32F373xC) || defined(STM32F378xx)
7676
[61] = "SDADC1_IRQn", /*!< ADC Sigma Delta 1 global Interrupt */
7777
[62] = "SDADC2_IRQn", /*!< ADC Sigma Delta 2 global Interrupt */
@@ -98,9 +98,9 @@
9898
[74] = "USB_HP_IRQn", /*!< USB High Priority global Interrupt */
9999
[75] = "USB_LP_IRQn", /*!< USB Low Priority global Interrupt */
100100
[76] = "USBWakeUp_RMP_IRQn", /*!< USB Wakeup Interrupt remap */
101-
[77] = "TIM20_BRK_IRQn", /*!< TIM20 Break Interrupt */
102-
[78] = "TIM20_UP_IRQn", /*!< TIM20 Update Interrupt */
103-
[79] = "TIM20_TRG_COM_IRQn", /*!< TIM20 Trigger and Commutation Interrupt */
104-
[80] = "TIM20_CC_IRQn", /*!< TIM20 Capture Compare Interrupt */
101+
[77] = "TIM20_BRK_IRQn", /*!< TIM20 Break Interrupt */
102+
[78] = "TIM20_UP_IRQn", /*!< TIM20 Update Interrupt */
103+
[79] = "TIM20_TRG_COM_IRQn", /*!< TIM20 Trigger and Commutation Interrupt */
104+
[80] = "TIM20_CC_IRQn", /*!< TIM20 Capture Compare Interrupt */
105105
[81] = "FPU_IRQn", /*!< Floating point Interrupt */
106-
[84] = "SPI4_IRQn", /*!< SPI4 global Interrupt */
106+
[84] = "SPI4_IRQn", /*!< SPI4 global Interrupt */

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